1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $ 41 */ 42 43 #ifdef __linux__ 44 #include "aic7xxx_osm.h" 45 #include "aic7xxx_inline.h" 46 #include "aicasm/aicasm_insformat.h" 47 #else 48 #include <dev/aic7xxx/aic7xxx_osm.h> 49 #include <dev/aic7xxx/aic7xxx_inline.h> 50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h> 51 #endif 52 53 /***************************** Lookup Tables **********************************/ 54 char *ahc_chip_names[] = 55 { 56 "NONE", 57 "aic7770", 58 "aic7850", 59 "aic7855", 60 "aic7859", 61 "aic7860", 62 "aic7870", 63 "aic7880", 64 "aic7895", 65 "aic7895C", 66 "aic7890/91", 67 "aic7896/97", 68 "aic7892", 69 "aic7899" 70 }; 71 static const u_int num_chip_names = ARRAY_SIZE(ahc_chip_names); 72 73 /* 74 * Hardware error codes. 75 */ 76 struct ahc_hard_error_entry { 77 uint8_t errno; 78 char *errmesg; 79 }; 80 81 static struct ahc_hard_error_entry ahc_hard_errors[] = { 82 { ILLHADDR, "Illegal Host Access" }, 83 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 84 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 85 { SQPARERR, "Sequencer Parity Error" }, 86 { DPARERR, "Data-path Parity Error" }, 87 { MPARERR, "Scratch or SCB Memory Parity Error" }, 88 { PCIERRSTAT, "PCI Error detected" }, 89 { CIOPARERR, "CIOBUS Parity Error" }, 90 }; 91 static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors); 92 93 static struct ahc_phase_table_entry ahc_phase_table[] = 94 { 95 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 96 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 97 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 98 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 99 { P_COMMAND, MSG_NOOP, "in Command phase" }, 100 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 101 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 102 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 103 { P_BUSFREE, MSG_NOOP, "while idle" }, 104 { 0, MSG_NOOP, "in unknown phase" } 105 }; 106 107 /* 108 * In most cases we only wish to itterate over real phases, so 109 * exclude the last element from the count. 110 */ 111 static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1; 112 113 /* 114 * Valid SCSIRATE values. (p. 3-17) 115 * Provides a mapping of tranfer periods in ns to the proper value to 116 * stick in the scsixfer reg. 117 */ 118 static struct ahc_syncrate ahc_syncrates[] = 119 { 120 /* ultra2 fast/ultra period rate */ 121 { 0x42, 0x000, 9, "80.0" }, 122 { 0x03, 0x000, 10, "40.0" }, 123 { 0x04, 0x000, 11, "33.0" }, 124 { 0x05, 0x100, 12, "20.0" }, 125 { 0x06, 0x110, 15, "16.0" }, 126 { 0x07, 0x120, 18, "13.4" }, 127 { 0x08, 0x000, 25, "10.0" }, 128 { 0x19, 0x010, 31, "8.0" }, 129 { 0x1a, 0x020, 37, "6.67" }, 130 { 0x1b, 0x030, 43, "5.7" }, 131 { 0x1c, 0x040, 50, "5.0" }, 132 { 0x00, 0x050, 56, "4.4" }, 133 { 0x00, 0x060, 62, "4.0" }, 134 { 0x00, 0x070, 68, "3.6" }, 135 { 0x00, 0x000, 0, NULL } 136 }; 137 138 /* Our Sequencer Program */ 139 #include "aic7xxx_seq.h" 140 141 /**************************** Function Declarations ***************************/ 142 static void ahc_force_renegotiation(struct ahc_softc *ahc, 143 struct ahc_devinfo *devinfo); 144 static struct ahc_tmode_tstate* 145 ahc_alloc_tstate(struct ahc_softc *ahc, 146 u_int scsi_id, char channel); 147 #ifdef AHC_TARGET_MODE 148 static void ahc_free_tstate(struct ahc_softc *ahc, 149 u_int scsi_id, char channel, int force); 150 #endif 151 static struct ahc_syncrate* 152 ahc_devlimited_syncrate(struct ahc_softc *ahc, 153 struct ahc_initiator_tinfo *, 154 u_int *period, 155 u_int *ppr_options, 156 role_t role); 157 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 158 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 159 struct ahc_devinfo *devinfo); 160 static void ahc_scb_devinfo(struct ahc_softc *ahc, 161 struct ahc_devinfo *devinfo, 162 struct scb *scb); 163 static void ahc_assert_atn(struct ahc_softc *ahc); 164 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 165 struct ahc_devinfo *devinfo, 166 struct scb *scb); 167 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 168 struct ahc_devinfo *devinfo); 169 static void ahc_construct_sdtr(struct ahc_softc *ahc, 170 struct ahc_devinfo *devinfo, 171 u_int period, u_int offset); 172 static void ahc_construct_wdtr(struct ahc_softc *ahc, 173 struct ahc_devinfo *devinfo, 174 u_int bus_width); 175 static void ahc_construct_ppr(struct ahc_softc *ahc, 176 struct ahc_devinfo *devinfo, 177 u_int period, u_int offset, 178 u_int bus_width, u_int ppr_options); 179 static void ahc_clear_msg_state(struct ahc_softc *ahc); 180 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 181 static void ahc_handle_message_phase(struct ahc_softc *ahc); 182 typedef enum { 183 AHCMSG_1B, 184 AHCMSG_2B, 185 AHCMSG_EXT 186 } ahc_msgtype; 187 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 188 u_int msgval, int full); 189 static int ahc_parse_msg(struct ahc_softc *ahc, 190 struct ahc_devinfo *devinfo); 191 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 192 struct ahc_devinfo *devinfo); 193 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 194 struct ahc_devinfo *devinfo); 195 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 196 static void ahc_handle_devreset(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo, 198 cam_status status, char *message, 199 int verbose_level); 200 #ifdef AHC_TARGET_MODE 201 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 202 struct ahc_devinfo *devinfo, 203 struct scb *scb); 204 #endif 205 206 static bus_dmamap_callback_t ahc_dmamap_cb; 207 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 208 static int ahc_init_scbdata(struct ahc_softc *ahc); 209 static void ahc_fini_scbdata(struct ahc_softc *ahc); 210 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 211 struct scb *prev_scb, 212 struct scb *scb); 213 static int ahc_qinfifo_count(struct ahc_softc *ahc); 214 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 215 u_int prev, u_int scbptr); 216 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 217 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 218 u_int scbpos, u_int prev); 219 static void ahc_reset_current_bus(struct ahc_softc *ahc); 220 #ifdef AHC_DUMP_SEQ 221 static void ahc_dumpseq(struct ahc_softc *ahc); 222 #endif 223 static int ahc_loadseq(struct ahc_softc *ahc); 224 static int ahc_check_patch(struct ahc_softc *ahc, 225 struct patch **start_patch, 226 u_int start_instr, u_int *skip_addr); 227 static void ahc_download_instr(struct ahc_softc *ahc, 228 u_int instrptr, uint8_t *dconsts); 229 #ifdef AHC_TARGET_MODE 230 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 231 struct ahc_tmode_lstate *lstate, 232 u_int initiator_id, 233 u_int event_type, 234 u_int event_arg); 235 static void ahc_update_scsiid(struct ahc_softc *ahc, 236 u_int targid_mask); 237 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 238 struct target_cmd *cmd); 239 #endif 240 /************************* Sequencer Execution Control ************************/ 241 /* 242 * Restart the sequencer program from address zero 243 */ 244 void 245 ahc_restart(struct ahc_softc *ahc) 246 { 247 248 ahc_pause(ahc); 249 250 /* No more pending messages. */ 251 ahc_clear_msg_state(ahc); 252 253 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 254 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 255 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 256 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 257 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 258 ahc_outb(ahc, SAVED_LUN, 0xFF); 259 260 /* 261 * Ensure that the sequencer's idea of TQINPOS 262 * matches our own. The sequencer increments TQINPOS 263 * only after it sees a DMA complete and a reset could 264 * occur before the increment leaving the kernel to believe 265 * the command arrived but the sequencer to not. 266 */ 267 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 268 269 /* Always allow reselection */ 270 ahc_outb(ahc, SCSISEQ, 271 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 272 if ((ahc->features & AHC_CMD_CHAN) != 0) { 273 /* Ensure that no DMA operations are in progress */ 274 ahc_outb(ahc, CCSCBCNT, 0); 275 ahc_outb(ahc, CCSGCTL, 0); 276 ahc_outb(ahc, CCSCBCTL, 0); 277 } 278 /* 279 * If we were in the process of DMA'ing SCB data into 280 * an SCB, replace that SCB on the free list. This prevents 281 * an SCB leak. 282 */ 283 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 284 ahc_add_curscb_to_free_list(ahc); 285 ahc_outb(ahc, SEQ_FLAGS2, 286 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 287 } 288 289 /* 290 * Clear any pending sequencer interrupt. It is no 291 * longer relevant since we're resetting the Program 292 * Counter. 293 */ 294 ahc_outb(ahc, CLRINT, CLRSEQINT); 295 296 ahc_outb(ahc, MWI_RESIDUAL, 0); 297 ahc_outb(ahc, SEQCTL, ahc->seqctl); 298 ahc_outb(ahc, SEQADDR0, 0); 299 ahc_outb(ahc, SEQADDR1, 0); 300 301 ahc_unpause(ahc); 302 } 303 304 /************************* Input/Output Queues ********************************/ 305 void 306 ahc_run_qoutfifo(struct ahc_softc *ahc) 307 { 308 struct scb *scb; 309 u_int scb_index; 310 311 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 312 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 313 314 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 315 if ((ahc->qoutfifonext & 0x03) == 0x03) { 316 u_int modnext; 317 318 /* 319 * Clear 32bits of QOUTFIFO at a time 320 * so that we don't clobber an incoming 321 * byte DMA to the array on architectures 322 * that only support 32bit load and store 323 * operations. 324 */ 325 modnext = ahc->qoutfifonext & ~0x3; 326 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 327 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 328 ahc->shared_data_dmamap, 329 /*offset*/modnext, /*len*/4, 330 BUS_DMASYNC_PREREAD); 331 } 332 ahc->qoutfifonext++; 333 334 scb = ahc_lookup_scb(ahc, scb_index); 335 if (scb == NULL) { 336 printf("%s: WARNING no command for scb %d " 337 "(cmdcmplt)\nQOUTPOS = %d\n", 338 ahc_name(ahc), scb_index, 339 (ahc->qoutfifonext - 1) & 0xFF); 340 continue; 341 } 342 343 /* 344 * Save off the residual 345 * if there is one. 346 */ 347 ahc_update_residual(ahc, scb); 348 ahc_done(ahc, scb); 349 } 350 } 351 352 void 353 ahc_run_untagged_queues(struct ahc_softc *ahc) 354 { 355 int i; 356 357 for (i = 0; i < 16; i++) 358 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 359 } 360 361 void 362 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 363 { 364 struct scb *scb; 365 366 if (ahc->untagged_queue_lock != 0) 367 return; 368 369 if ((scb = TAILQ_FIRST(queue)) != NULL 370 && (scb->flags & SCB_ACTIVE) == 0) { 371 scb->flags |= SCB_ACTIVE; 372 ahc_queue_scb(ahc, scb); 373 } 374 } 375 376 /************************* Interrupt Handling *********************************/ 377 void 378 ahc_handle_brkadrint(struct ahc_softc *ahc) 379 { 380 /* 381 * We upset the sequencer :-( 382 * Lookup the error message 383 */ 384 int i; 385 int error; 386 387 error = ahc_inb(ahc, ERROR); 388 for (i = 0; error != 1 && i < num_errors; i++) 389 error >>= 1; 390 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 391 ahc_name(ahc), ahc_hard_errors[i].errmesg, 392 ahc_inb(ahc, SEQADDR0) | 393 (ahc_inb(ahc, SEQADDR1) << 8)); 394 395 ahc_dump_card_state(ahc); 396 397 /* Tell everyone that this HBA is no longer available */ 398 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 399 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 400 CAM_NO_HBA); 401 402 /* Disable all interrupt sources by resetting the controller */ 403 ahc_shutdown(ahc); 404 } 405 406 void 407 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 408 { 409 struct scb *scb; 410 struct ahc_devinfo devinfo; 411 412 ahc_fetch_devinfo(ahc, &devinfo); 413 414 /* 415 * Clear the upper byte that holds SEQINT status 416 * codes and clear the SEQINT bit. We will unpause 417 * the sequencer, if appropriate, after servicing 418 * the request. 419 */ 420 ahc_outb(ahc, CLRINT, CLRSEQINT); 421 switch (intstat & SEQINT_MASK) { 422 case BAD_STATUS: 423 { 424 u_int scb_index; 425 struct hardware_scb *hscb; 426 427 /* 428 * Set the default return value to 0 (don't 429 * send sense). The sense code will change 430 * this if needed. 431 */ 432 ahc_outb(ahc, RETURN_1, 0); 433 434 /* 435 * The sequencer will notify us when a command 436 * has an error that would be of interest to 437 * the kernel. This allows us to leave the sequencer 438 * running in the common case of command completes 439 * without error. The sequencer will already have 440 * dma'd the SCB back up to us, so we can reference 441 * the in kernel copy directly. 442 */ 443 scb_index = ahc_inb(ahc, SCB_TAG); 444 scb = ahc_lookup_scb(ahc, scb_index); 445 if (scb == NULL) { 446 ahc_print_devinfo(ahc, &devinfo); 447 printf("ahc_intr - referenced scb " 448 "not valid during seqint 0x%x scb(%d)\n", 449 intstat, scb_index); 450 ahc_dump_card_state(ahc); 451 panic("for safety"); 452 goto unpause; 453 } 454 455 hscb = scb->hscb; 456 457 /* Don't want to clobber the original sense code */ 458 if ((scb->flags & SCB_SENSE) != 0) { 459 /* 460 * Clear the SCB_SENSE Flag and have 461 * the sequencer do a normal command 462 * complete. 463 */ 464 scb->flags &= ~SCB_SENSE; 465 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 466 break; 467 } 468 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 469 /* Freeze the queue until the client sees the error. */ 470 ahc_freeze_devq(ahc, scb); 471 ahc_freeze_scb(scb); 472 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 473 switch (hscb->shared_data.status.scsi_status) { 474 case SCSI_STATUS_OK: 475 printf("%s: Interrupted for staus of 0???\n", 476 ahc_name(ahc)); 477 break; 478 case SCSI_STATUS_CMD_TERMINATED: 479 case SCSI_STATUS_CHECK_COND: 480 { 481 struct ahc_dma_seg *sg; 482 struct scsi_sense *sc; 483 struct ahc_initiator_tinfo *targ_info; 484 struct ahc_tmode_tstate *tstate; 485 struct ahc_transinfo *tinfo; 486 #ifdef AHC_DEBUG 487 if (ahc_debug & AHC_SHOW_SENSE) { 488 ahc_print_path(ahc, scb); 489 printf("SCB %d: requests Check Status\n", 490 scb->hscb->tag); 491 } 492 #endif 493 494 if (ahc_perform_autosense(scb) == 0) 495 break; 496 497 targ_info = ahc_fetch_transinfo(ahc, 498 devinfo.channel, 499 devinfo.our_scsiid, 500 devinfo.target, 501 &tstate); 502 tinfo = &targ_info->curr; 503 sg = scb->sg_list; 504 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 505 /* 506 * Save off the residual if there is one. 507 */ 508 ahc_update_residual(ahc, scb); 509 #ifdef AHC_DEBUG 510 if (ahc_debug & AHC_SHOW_SENSE) { 511 ahc_print_path(ahc, scb); 512 printf("Sending Sense\n"); 513 } 514 #endif 515 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 516 sg->len = ahc_get_sense_bufsize(ahc, scb); 517 sg->len |= AHC_DMA_LAST_SEG; 518 519 /* Fixup byte order */ 520 sg->addr = ahc_htole32(sg->addr); 521 sg->len = ahc_htole32(sg->len); 522 523 sc->opcode = REQUEST_SENSE; 524 sc->byte2 = 0; 525 if (tinfo->protocol_version <= SCSI_REV_2 526 && SCB_GET_LUN(scb) < 8) 527 sc->byte2 = SCB_GET_LUN(scb) << 5; 528 sc->unused[0] = 0; 529 sc->unused[1] = 0; 530 sc->length = sg->len; 531 sc->control = 0; 532 533 /* 534 * We can't allow the target to disconnect. 535 * This will be an untagged transaction and 536 * having the target disconnect will make this 537 * transaction indestinguishable from outstanding 538 * tagged transactions. 539 */ 540 hscb->control = 0; 541 542 /* 543 * This request sense could be because the 544 * the device lost power or in some other 545 * way has lost our transfer negotiations. 546 * Renegotiate if appropriate. Unit attention 547 * errors will be reported before any data 548 * phases occur. 549 */ 550 if (ahc_get_residual(scb) 551 == ahc_get_transfer_length(scb)) { 552 ahc_update_neg_request(ahc, &devinfo, 553 tstate, targ_info, 554 AHC_NEG_IF_NON_ASYNC); 555 } 556 if (tstate->auto_negotiate & devinfo.target_mask) { 557 hscb->control |= MK_MESSAGE; 558 scb->flags &= ~SCB_NEGOTIATE; 559 scb->flags |= SCB_AUTO_NEGOTIATE; 560 } 561 hscb->cdb_len = sizeof(*sc); 562 hscb->dataptr = sg->addr; 563 hscb->datacnt = sg->len; 564 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 565 hscb->sgptr = ahc_htole32(hscb->sgptr); 566 scb->sg_count = 1; 567 scb->flags |= SCB_SENSE; 568 ahc_qinfifo_requeue_tail(ahc, scb); 569 ahc_outb(ahc, RETURN_1, SEND_SENSE); 570 /* 571 * Ensure we have enough time to actually 572 * retrieve the sense. 573 */ 574 ahc_scb_timer_reset(scb, 5 * 1000000); 575 break; 576 } 577 default: 578 break; 579 } 580 break; 581 } 582 case NO_MATCH: 583 { 584 /* Ensure we don't leave the selection hardware on */ 585 ahc_outb(ahc, SCSISEQ, 586 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 587 588 printf("%s:%c:%d: no active SCB for reconnecting " 589 "target - issuing BUS DEVICE RESET\n", 590 ahc_name(ahc), devinfo.channel, devinfo.target); 591 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 592 "ARG_1 == 0x%x ACCUM = 0x%x\n", 593 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 594 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 595 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 596 "SINDEX == 0x%x\n", 597 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 598 ahc_index_busy_tcl(ahc, 599 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 600 ahc_inb(ahc, SAVED_LUN))), 601 ahc_inb(ahc, SINDEX)); 602 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 603 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 604 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 605 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 606 ahc_inb(ahc, SCB_CONTROL)); 607 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 608 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 609 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 610 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 611 ahc_dump_card_state(ahc); 612 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 613 ahc->msgout_len = 1; 614 ahc->msgout_index = 0; 615 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 616 ahc_outb(ahc, MSG_OUT, HOST_MSG); 617 ahc_assert_atn(ahc); 618 break; 619 } 620 case SEND_REJECT: 621 { 622 u_int rejbyte = ahc_inb(ahc, ACCUM); 623 printf("%s:%c:%d: Warning - unknown message received from " 624 "target (0x%x). Rejecting\n", 625 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 626 break; 627 } 628 case PROTO_VIOLATION: 629 { 630 ahc_handle_proto_violation(ahc); 631 break; 632 } 633 case IGN_WIDE_RES: 634 ahc_handle_ign_wide_residue(ahc, &devinfo); 635 break; 636 case PDATA_REINIT: 637 ahc_reinitialize_dataptrs(ahc); 638 break; 639 case BAD_PHASE: 640 { 641 u_int lastphase; 642 643 lastphase = ahc_inb(ahc, LASTPHASE); 644 printf("%s:%c:%d: unknown scsi bus phase %x, " 645 "lastphase = 0x%x. Attempting to continue\n", 646 ahc_name(ahc), devinfo.channel, devinfo.target, 647 lastphase, ahc_inb(ahc, SCSISIGI)); 648 break; 649 } 650 case MISSED_BUSFREE: 651 { 652 u_int lastphase; 653 654 lastphase = ahc_inb(ahc, LASTPHASE); 655 printf("%s:%c:%d: Missed busfree. " 656 "Lastphase = 0x%x, Curphase = 0x%x\n", 657 ahc_name(ahc), devinfo.channel, devinfo.target, 658 lastphase, ahc_inb(ahc, SCSISIGI)); 659 ahc_restart(ahc); 660 return; 661 } 662 case HOST_MSG_LOOP: 663 { 664 /* 665 * The sequencer has encountered a message phase 666 * that requires host assistance for completion. 667 * While handling the message phase(s), we will be 668 * notified by the sequencer after each byte is 669 * transfered so we can track bus phase changes. 670 * 671 * If this is the first time we've seen a HOST_MSG_LOOP 672 * interrupt, initialize the state of the host message 673 * loop. 674 */ 675 if (ahc->msg_type == MSG_TYPE_NONE) { 676 struct scb *scb; 677 u_int scb_index; 678 u_int bus_phase; 679 680 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 681 if (bus_phase != P_MESGIN 682 && bus_phase != P_MESGOUT) { 683 printf("ahc_intr: HOST_MSG_LOOP bad " 684 "phase 0x%x\n", 685 bus_phase); 686 /* 687 * Probably transitioned to bus free before 688 * we got here. Just punt the message. 689 */ 690 ahc_clear_intstat(ahc); 691 ahc_restart(ahc); 692 return; 693 } 694 695 scb_index = ahc_inb(ahc, SCB_TAG); 696 scb = ahc_lookup_scb(ahc, scb_index); 697 if (devinfo.role == ROLE_INITIATOR) { 698 if (scb == NULL) 699 panic("HOST_MSG_LOOP with " 700 "invalid SCB %x\n", scb_index); 701 702 if (bus_phase == P_MESGOUT) 703 ahc_setup_initiator_msgout(ahc, 704 &devinfo, 705 scb); 706 else { 707 ahc->msg_type = 708 MSG_TYPE_INITIATOR_MSGIN; 709 ahc->msgin_index = 0; 710 } 711 } 712 #ifdef AHC_TARGET_MODE 713 else { 714 if (bus_phase == P_MESGOUT) { 715 ahc->msg_type = 716 MSG_TYPE_TARGET_MSGOUT; 717 ahc->msgin_index = 0; 718 } 719 else 720 ahc_setup_target_msgin(ahc, 721 &devinfo, 722 scb); 723 } 724 #endif 725 } 726 727 ahc_handle_message_phase(ahc); 728 break; 729 } 730 case PERR_DETECTED: 731 { 732 /* 733 * If we've cleared the parity error interrupt 734 * but the sequencer still believes that SCSIPERR 735 * is true, it must be that the parity error is 736 * for the currently presented byte on the bus, 737 * and we are not in a phase (data-in) where we will 738 * eventually ack this byte. Ack the byte and 739 * throw it away in the hope that the target will 740 * take us to message out to deliver the appropriate 741 * error message. 742 */ 743 if ((intstat & SCSIINT) == 0 744 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 745 746 if ((ahc->features & AHC_DT) == 0) { 747 u_int curphase; 748 749 /* 750 * The hardware will only let you ack bytes 751 * if the expected phase in SCSISIGO matches 752 * the current phase. Make sure this is 753 * currently the case. 754 */ 755 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 756 ahc_outb(ahc, LASTPHASE, curphase); 757 ahc_outb(ahc, SCSISIGO, curphase); 758 } 759 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 760 int wait; 761 762 /* 763 * In a data phase. Faster to bitbucket 764 * the data than to individually ack each 765 * byte. This is also the only strategy 766 * that will work with AUTOACK enabled. 767 */ 768 ahc_outb(ahc, SXFRCTL1, 769 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 770 wait = 5000; 771 while (--wait != 0) { 772 if ((ahc_inb(ahc, SCSISIGI) 773 & (CDI|MSGI)) != 0) 774 break; 775 ahc_delay(100); 776 } 777 ahc_outb(ahc, SXFRCTL1, 778 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 779 if (wait == 0) { 780 struct scb *scb; 781 u_int scb_index; 782 783 ahc_print_devinfo(ahc, &devinfo); 784 printf("Unable to clear parity error. " 785 "Resetting bus.\n"); 786 scb_index = ahc_inb(ahc, SCB_TAG); 787 scb = ahc_lookup_scb(ahc, scb_index); 788 if (scb != NULL) 789 ahc_set_transaction_status(scb, 790 CAM_UNCOR_PARITY); 791 ahc_reset_channel(ahc, devinfo.channel, 792 /*init reset*/TRUE); 793 } 794 } else { 795 ahc_inb(ahc, SCSIDATL); 796 } 797 } 798 break; 799 } 800 case DATA_OVERRUN: 801 { 802 /* 803 * When the sequencer detects an overrun, it 804 * places the controller in "BITBUCKET" mode 805 * and allows the target to complete its transfer. 806 * Unfortunately, none of the counters get updated 807 * when the controller is in this mode, so we have 808 * no way of knowing how large the overrun was. 809 */ 810 u_int scbindex = ahc_inb(ahc, SCB_TAG); 811 u_int lastphase = ahc_inb(ahc, LASTPHASE); 812 u_int i; 813 814 scb = ahc_lookup_scb(ahc, scbindex); 815 for (i = 0; i < num_phases; i++) { 816 if (lastphase == ahc_phase_table[i].phase) 817 break; 818 } 819 ahc_print_path(ahc, scb); 820 printf("data overrun detected %s." 821 " Tag == 0x%x.\n", 822 ahc_phase_table[i].phasemsg, 823 scb->hscb->tag); 824 ahc_print_path(ahc, scb); 825 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 826 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 827 ahc_get_transfer_length(scb), scb->sg_count); 828 if (scb->sg_count > 0) { 829 for (i = 0; i < scb->sg_count; i++) { 830 831 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 832 i, 833 (ahc_le32toh(scb->sg_list[i].len) >> 24 834 & SG_HIGH_ADDR_BITS), 835 ahc_le32toh(scb->sg_list[i].addr), 836 ahc_le32toh(scb->sg_list[i].len) 837 & AHC_SG_LEN_MASK); 838 } 839 } 840 /* 841 * Set this and it will take effect when the 842 * target does a command complete. 843 */ 844 ahc_freeze_devq(ahc, scb); 845 if ((scb->flags & SCB_SENSE) == 0) { 846 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 847 } else { 848 scb->flags &= ~SCB_SENSE; 849 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 850 } 851 ahc_freeze_scb(scb); 852 853 if ((ahc->features & AHC_ULTRA2) != 0) { 854 /* 855 * Clear the channel in case we return 856 * to data phase later. 857 */ 858 ahc_outb(ahc, SXFRCTL0, 859 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 860 ahc_outb(ahc, SXFRCTL0, 861 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 862 } 863 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 864 u_int dscommand1; 865 866 /* Ensure HHADDR is 0 for future DMA operations. */ 867 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 868 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 869 ahc_outb(ahc, HADDR, 0); 870 ahc_outb(ahc, DSCOMMAND1, dscommand1); 871 } 872 break; 873 } 874 case MKMSG_FAILED: 875 { 876 u_int scbindex; 877 878 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 879 ahc_name(ahc), devinfo.channel, devinfo.target, 880 devinfo.lun); 881 scbindex = ahc_inb(ahc, SCB_TAG); 882 scb = ahc_lookup_scb(ahc, scbindex); 883 if (scb != NULL 884 && (scb->flags & SCB_RECOVERY_SCB) != 0) 885 /* 886 * Ensure that we didn't put a second instance of this 887 * SCB into the QINFIFO. 888 */ 889 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 890 SCB_GET_CHANNEL(ahc, scb), 891 SCB_GET_LUN(scb), scb->hscb->tag, 892 ROLE_INITIATOR, /*status*/0, 893 SEARCH_REMOVE); 894 break; 895 } 896 case NO_FREE_SCB: 897 { 898 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 899 ahc_dump_card_state(ahc); 900 panic("for safety"); 901 break; 902 } 903 case SCB_MISMATCH: 904 { 905 u_int scbptr; 906 907 scbptr = ahc_inb(ahc, SCBPTR); 908 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 909 scbptr, ahc_inb(ahc, ARG_1), 910 ahc->scb_data->hscbs[scbptr].tag); 911 ahc_dump_card_state(ahc); 912 panic("for saftey"); 913 break; 914 } 915 case OUT_OF_RANGE: 916 { 917 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 918 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 919 "ARG_1 == 0x%x ACCUM = 0x%x\n", 920 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 921 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 922 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 923 "SINDEX == 0x%x\n, A == 0x%x\n", 924 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 925 ahc_index_busy_tcl(ahc, 926 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 927 ahc_inb(ahc, SAVED_LUN))), 928 ahc_inb(ahc, SINDEX), 929 ahc_inb(ahc, ACCUM)); 930 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 931 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 932 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 933 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 934 ahc_inb(ahc, SCB_CONTROL)); 935 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 936 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 937 ahc_dump_card_state(ahc); 938 panic("for safety"); 939 break; 940 } 941 default: 942 printf("ahc_intr: seqint, " 943 "intstat == 0x%x, scsisigi = 0x%x\n", 944 intstat, ahc_inb(ahc, SCSISIGI)); 945 break; 946 } 947 unpause: 948 /* 949 * The sequencer is paused immediately on 950 * a SEQINT, so we should restart it when 951 * we're done. 952 */ 953 ahc_unpause(ahc); 954 } 955 956 void 957 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 958 { 959 u_int scb_index; 960 u_int status0; 961 u_int status; 962 struct scb *scb; 963 char cur_channel; 964 char intr_channel; 965 966 if ((ahc->features & AHC_TWIN) != 0 967 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 968 cur_channel = 'B'; 969 else 970 cur_channel = 'A'; 971 intr_channel = cur_channel; 972 973 if ((ahc->features & AHC_ULTRA2) != 0) 974 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 975 else 976 status0 = 0; 977 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 978 if (status == 0 && status0 == 0) { 979 if ((ahc->features & AHC_TWIN) != 0) { 980 /* Try the other channel */ 981 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 982 status = ahc_inb(ahc, SSTAT1) 983 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 984 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 985 } 986 if (status == 0) { 987 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 988 ahc_outb(ahc, CLRINT, CLRSCSIINT); 989 ahc_unpause(ahc); 990 return; 991 } 992 } 993 994 /* Make sure the sequencer is in a safe location. */ 995 ahc_clear_critical_section(ahc); 996 997 scb_index = ahc_inb(ahc, SCB_TAG); 998 scb = ahc_lookup_scb(ahc, scb_index); 999 if (scb != NULL 1000 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1001 scb = NULL; 1002 1003 if ((ahc->features & AHC_ULTRA2) != 0 1004 && (status0 & IOERR) != 0) { 1005 int now_lvd; 1006 1007 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1008 printf("%s: Transceiver State Has Changed to %s mode\n", 1009 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1010 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1011 /* 1012 * When transitioning to SE mode, the reset line 1013 * glitches, triggering an arbitration bug in some 1014 * Ultra2 controllers. This bug is cleared when we 1015 * assert the reset line. Since a reset glitch has 1016 * already occurred with this transition and a 1017 * transceiver state change is handled just like 1018 * a bus reset anyway, asserting the reset line 1019 * ourselves is safe. 1020 */ 1021 ahc_reset_channel(ahc, intr_channel, 1022 /*Initiate Reset*/now_lvd == 0); 1023 } else if ((status & SCSIRSTI) != 0) { 1024 printf("%s: Someone reset channel %c\n", 1025 ahc_name(ahc), intr_channel); 1026 if (intr_channel != cur_channel) 1027 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1028 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1029 } else if ((status & SCSIPERR) != 0) { 1030 /* 1031 * Determine the bus phase and queue an appropriate message. 1032 * SCSIPERR is latched true as soon as a parity error 1033 * occurs. If the sequencer acked the transfer that 1034 * caused the parity error and the currently presented 1035 * transfer on the bus has correct parity, SCSIPERR will 1036 * be cleared by CLRSCSIPERR. Use this to determine if 1037 * we should look at the last phase the sequencer recorded, 1038 * or the current phase presented on the bus. 1039 */ 1040 struct ahc_devinfo devinfo; 1041 u_int mesg_out; 1042 u_int curphase; 1043 u_int errorphase; 1044 u_int lastphase; 1045 u_int scsirate; 1046 u_int i; 1047 u_int sstat2; 1048 int silent; 1049 1050 lastphase = ahc_inb(ahc, LASTPHASE); 1051 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1052 sstat2 = ahc_inb(ahc, SSTAT2); 1053 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1054 /* 1055 * For all phases save DATA, the sequencer won't 1056 * automatically ack a byte that has a parity error 1057 * in it. So the only way that the current phase 1058 * could be 'data-in' is if the parity error is for 1059 * an already acked byte in the data phase. During 1060 * synchronous data-in transfers, we may actually 1061 * ack bytes before latching the current phase in 1062 * LASTPHASE, leading to the discrepancy between 1063 * curphase and lastphase. 1064 */ 1065 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1066 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1067 errorphase = curphase; 1068 else 1069 errorphase = lastphase; 1070 1071 for (i = 0; i < num_phases; i++) { 1072 if (errorphase == ahc_phase_table[i].phase) 1073 break; 1074 } 1075 mesg_out = ahc_phase_table[i].mesg_out; 1076 silent = FALSE; 1077 if (scb != NULL) { 1078 if (SCB_IS_SILENT(scb)) 1079 silent = TRUE; 1080 else 1081 ahc_print_path(ahc, scb); 1082 scb->flags |= SCB_TRANSMISSION_ERROR; 1083 } else 1084 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1085 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1086 scsirate = ahc_inb(ahc, SCSIRATE); 1087 if (silent == FALSE) { 1088 printf("parity error detected %s. " 1089 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1090 ahc_phase_table[i].phasemsg, 1091 ahc_inw(ahc, SEQADDR0), 1092 scsirate); 1093 if ((ahc->features & AHC_DT) != 0) { 1094 if ((sstat2 & CRCVALERR) != 0) 1095 printf("\tCRC Value Mismatch\n"); 1096 if ((sstat2 & CRCENDERR) != 0) 1097 printf("\tNo terminal CRC packet " 1098 "recevied\n"); 1099 if ((sstat2 & CRCREQERR) != 0) 1100 printf("\tIllegal CRC packet " 1101 "request\n"); 1102 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1103 printf("\tUnexpected %sDT Data Phase\n", 1104 (scsirate & SINGLE_EDGE) 1105 ? "" : "non-"); 1106 } 1107 } 1108 1109 if ((ahc->features & AHC_DT) != 0 1110 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1111 /* 1112 * This error applies regardless of 1113 * data direction, so ignore the value 1114 * in the phase table. 1115 */ 1116 mesg_out = MSG_INITIATOR_DET_ERR; 1117 } 1118 1119 /* 1120 * We've set the hardware to assert ATN if we 1121 * get a parity error on "in" phases, so all we 1122 * need to do is stuff the message buffer with 1123 * the appropriate message. "In" phases have set 1124 * mesg_out to something other than MSG_NOP. 1125 */ 1126 if (mesg_out != MSG_NOOP) { 1127 if (ahc->msg_type != MSG_TYPE_NONE) 1128 ahc->send_msg_perror = TRUE; 1129 else 1130 ahc_outb(ahc, MSG_OUT, mesg_out); 1131 } 1132 /* 1133 * Force a renegotiation with this target just in 1134 * case we are out of sync for some external reason 1135 * unknown (or unreported) by the target. 1136 */ 1137 ahc_fetch_devinfo(ahc, &devinfo); 1138 ahc_force_renegotiation(ahc, &devinfo); 1139 1140 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1141 ahc_unpause(ahc); 1142 } else if ((status & SELTO) != 0) { 1143 u_int scbptr; 1144 1145 /* Stop the selection */ 1146 ahc_outb(ahc, SCSISEQ, 0); 1147 1148 /* No more pending messages */ 1149 ahc_clear_msg_state(ahc); 1150 1151 /* Clear interrupt state */ 1152 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1153 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1154 1155 /* 1156 * Although the driver does not care about the 1157 * 'Selection in Progress' status bit, the busy 1158 * LED does. SELINGO is only cleared by a sucessfull 1159 * selection, so we must manually clear it to insure 1160 * the LED turns off just incase no future successful 1161 * selections occur (e.g. no devices on the bus). 1162 */ 1163 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1164 1165 scbptr = ahc_inb(ahc, WAITING_SCBH); 1166 ahc_outb(ahc, SCBPTR, scbptr); 1167 scb_index = ahc_inb(ahc, SCB_TAG); 1168 1169 scb = ahc_lookup_scb(ahc, scb_index); 1170 if (scb == NULL) { 1171 printf("%s: ahc_intr - referenced scb not " 1172 "valid during SELTO scb(%d, %d)\n", 1173 ahc_name(ahc), scbptr, scb_index); 1174 ahc_dump_card_state(ahc); 1175 } else { 1176 struct ahc_devinfo devinfo; 1177 #ifdef AHC_DEBUG 1178 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1179 ahc_print_path(ahc, scb); 1180 printf("Saw Selection Timeout for SCB 0x%x\n", 1181 scb_index); 1182 } 1183 #endif 1184 ahc_scb_devinfo(ahc, &devinfo, scb); 1185 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1186 ahc_freeze_devq(ahc, scb); 1187 1188 /* 1189 * Cancel any pending transactions on the device 1190 * now that it seems to be missing. This will 1191 * also revert us to async/narrow transfers until 1192 * we can renegotiate with the device. 1193 */ 1194 ahc_handle_devreset(ahc, &devinfo, 1195 CAM_SEL_TIMEOUT, 1196 "Selection Timeout", 1197 /*verbose_level*/1); 1198 } 1199 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1200 ahc_restart(ahc); 1201 } else if ((status & BUSFREE) != 0 1202 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1203 struct ahc_devinfo devinfo; 1204 u_int lastphase; 1205 u_int saved_scsiid; 1206 u_int saved_lun; 1207 u_int target; 1208 u_int initiator_role_id; 1209 char channel; 1210 int printerror; 1211 1212 /* 1213 * Clear our selection hardware as soon as possible. 1214 * We may have an entry in the waiting Q for this target, 1215 * that is affected by this busfree and we don't want to 1216 * go about selecting the target while we handle the event. 1217 */ 1218 ahc_outb(ahc, SCSISEQ, 1219 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1220 1221 /* 1222 * Disable busfree interrupts and clear the busfree 1223 * interrupt status. We do this here so that several 1224 * bus transactions occur prior to clearing the SCSIINT 1225 * latch. It can take a bit for the clearing to take effect. 1226 */ 1227 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1228 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1229 1230 /* 1231 * Look at what phase we were last in. 1232 * If its message out, chances are pretty good 1233 * that the busfree was in response to one of 1234 * our abort requests. 1235 */ 1236 lastphase = ahc_inb(ahc, LASTPHASE); 1237 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1238 saved_lun = ahc_inb(ahc, SAVED_LUN); 1239 target = SCSIID_TARGET(ahc, saved_scsiid); 1240 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1241 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1242 ahc_compile_devinfo(&devinfo, initiator_role_id, 1243 target, saved_lun, channel, ROLE_INITIATOR); 1244 printerror = 1; 1245 1246 if (lastphase == P_MESGOUT) { 1247 u_int tag; 1248 1249 tag = SCB_LIST_NULL; 1250 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1251 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1252 if (ahc->msgout_buf[ahc->msgout_index - 1] 1253 == MSG_ABORT_TAG) 1254 tag = scb->hscb->tag; 1255 ahc_print_path(ahc, scb); 1256 printf("SCB %d - Abort%s Completed.\n", 1257 scb->hscb->tag, tag == SCB_LIST_NULL ? 1258 "" : " Tag"); 1259 ahc_abort_scbs(ahc, target, channel, 1260 saved_lun, tag, 1261 ROLE_INITIATOR, 1262 CAM_REQ_ABORTED); 1263 printerror = 0; 1264 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1265 MSG_BUS_DEV_RESET, TRUE)) { 1266 #ifdef __FreeBSD__ 1267 /* 1268 * Don't mark the user's request for this BDR 1269 * as completing with CAM_BDR_SENT. CAM3 1270 * specifies CAM_REQ_CMP. 1271 */ 1272 if (scb != NULL 1273 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1274 && ahc_match_scb(ahc, scb, target, channel, 1275 CAM_LUN_WILDCARD, 1276 SCB_LIST_NULL, 1277 ROLE_INITIATOR)) { 1278 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1279 } 1280 #endif 1281 ahc_compile_devinfo(&devinfo, 1282 initiator_role_id, 1283 target, 1284 CAM_LUN_WILDCARD, 1285 channel, 1286 ROLE_INITIATOR); 1287 ahc_handle_devreset(ahc, &devinfo, 1288 CAM_BDR_SENT, 1289 "Bus Device Reset", 1290 /*verbose_level*/0); 1291 printerror = 0; 1292 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1293 MSG_EXT_PPR, FALSE)) { 1294 struct ahc_initiator_tinfo *tinfo; 1295 struct ahc_tmode_tstate *tstate; 1296 1297 /* 1298 * PPR Rejected. Try non-ppr negotiation 1299 * and retry command. 1300 */ 1301 tinfo = ahc_fetch_transinfo(ahc, 1302 devinfo.channel, 1303 devinfo.our_scsiid, 1304 devinfo.target, 1305 &tstate); 1306 tinfo->curr.transport_version = 2; 1307 tinfo->goal.transport_version = 2; 1308 tinfo->goal.ppr_options = 0; 1309 ahc_qinfifo_requeue_tail(ahc, scb); 1310 printerror = 0; 1311 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1312 MSG_EXT_WDTR, FALSE)) { 1313 /* 1314 * Negotiation Rejected. Go-narrow and 1315 * retry command. 1316 */ 1317 ahc_set_width(ahc, &devinfo, 1318 MSG_EXT_WDTR_BUS_8_BIT, 1319 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1320 /*paused*/TRUE); 1321 ahc_qinfifo_requeue_tail(ahc, scb); 1322 printerror = 0; 1323 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1324 MSG_EXT_SDTR, FALSE)) { 1325 /* 1326 * Negotiation Rejected. Go-async and 1327 * retry command. 1328 */ 1329 ahc_set_syncrate(ahc, &devinfo, 1330 /*syncrate*/NULL, 1331 /*period*/0, /*offset*/0, 1332 /*ppr_options*/0, 1333 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1334 /*paused*/TRUE); 1335 ahc_qinfifo_requeue_tail(ahc, scb); 1336 printerror = 0; 1337 } 1338 } 1339 if (printerror != 0) { 1340 u_int i; 1341 1342 if (scb != NULL) { 1343 u_int tag; 1344 1345 if ((scb->hscb->control & TAG_ENB) != 0) 1346 tag = scb->hscb->tag; 1347 else 1348 tag = SCB_LIST_NULL; 1349 ahc_print_path(ahc, scb); 1350 ahc_abort_scbs(ahc, target, channel, 1351 SCB_GET_LUN(scb), tag, 1352 ROLE_INITIATOR, 1353 CAM_UNEXP_BUSFREE); 1354 } else { 1355 /* 1356 * We had not fully identified this connection, 1357 * so we cannot abort anything. 1358 */ 1359 printf("%s: ", ahc_name(ahc)); 1360 } 1361 for (i = 0; i < num_phases; i++) { 1362 if (lastphase == ahc_phase_table[i].phase) 1363 break; 1364 } 1365 if (lastphase != P_BUSFREE) { 1366 /* 1367 * Renegotiate with this device at the 1368 * next oportunity just in case this busfree 1369 * is due to a negotiation mismatch with the 1370 * device. 1371 */ 1372 ahc_force_renegotiation(ahc, &devinfo); 1373 } 1374 printf("Unexpected busfree %s\n" 1375 "SEQADDR == 0x%x\n", 1376 ahc_phase_table[i].phasemsg, 1377 ahc_inb(ahc, SEQADDR0) 1378 | (ahc_inb(ahc, SEQADDR1) << 8)); 1379 } 1380 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1381 ahc_restart(ahc); 1382 } else { 1383 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1384 ahc_name(ahc), status); 1385 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1386 } 1387 } 1388 1389 /* 1390 * Force renegotiation to occur the next time we initiate 1391 * a command to the current device. 1392 */ 1393 static void 1394 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1395 { 1396 struct ahc_initiator_tinfo *targ_info; 1397 struct ahc_tmode_tstate *tstate; 1398 1399 targ_info = ahc_fetch_transinfo(ahc, 1400 devinfo->channel, 1401 devinfo->our_scsiid, 1402 devinfo->target, 1403 &tstate); 1404 ahc_update_neg_request(ahc, devinfo, tstate, 1405 targ_info, AHC_NEG_IF_NON_ASYNC); 1406 } 1407 1408 #define AHC_MAX_STEPS 2000 1409 void 1410 ahc_clear_critical_section(struct ahc_softc *ahc) 1411 { 1412 int stepping; 1413 int steps; 1414 u_int simode0; 1415 u_int simode1; 1416 1417 if (ahc->num_critical_sections == 0) 1418 return; 1419 1420 stepping = FALSE; 1421 steps = 0; 1422 simode0 = 0; 1423 simode1 = 0; 1424 for (;;) { 1425 struct cs *cs; 1426 u_int seqaddr; 1427 u_int i; 1428 1429 seqaddr = ahc_inb(ahc, SEQADDR0) 1430 | (ahc_inb(ahc, SEQADDR1) << 8); 1431 1432 /* 1433 * Seqaddr represents the next instruction to execute, 1434 * so we are really executing the instruction just 1435 * before it. 1436 */ 1437 if (seqaddr != 0) 1438 seqaddr -= 1; 1439 cs = ahc->critical_sections; 1440 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1441 1442 if (cs->begin < seqaddr && cs->end >= seqaddr) 1443 break; 1444 } 1445 1446 if (i == ahc->num_critical_sections) 1447 break; 1448 1449 if (steps > AHC_MAX_STEPS) { 1450 printf("%s: Infinite loop in critical section\n", 1451 ahc_name(ahc)); 1452 ahc_dump_card_state(ahc); 1453 panic("critical section loop"); 1454 } 1455 1456 steps++; 1457 if (stepping == FALSE) { 1458 1459 /* 1460 * Disable all interrupt sources so that the 1461 * sequencer will not be stuck by a pausing 1462 * interrupt condition while we attempt to 1463 * leave a critical section. 1464 */ 1465 simode0 = ahc_inb(ahc, SIMODE0); 1466 ahc_outb(ahc, SIMODE0, 0); 1467 simode1 = ahc_inb(ahc, SIMODE1); 1468 if ((ahc->features & AHC_DT) != 0) 1469 /* 1470 * On DT class controllers, we 1471 * use the enhanced busfree logic. 1472 * Unfortunately we cannot re-enable 1473 * busfree detection within the 1474 * current connection, so we must 1475 * leave it on while single stepping. 1476 */ 1477 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE); 1478 else 1479 ahc_outb(ahc, SIMODE1, 0); 1480 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1481 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP); 1482 stepping = TRUE; 1483 } 1484 if ((ahc->features & AHC_DT) != 0) { 1485 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1486 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1487 } 1488 ahc_outb(ahc, HCNTRL, ahc->unpause); 1489 while (!ahc_is_paused(ahc)) 1490 ahc_delay(200); 1491 } 1492 if (stepping) { 1493 ahc_outb(ahc, SIMODE0, simode0); 1494 ahc_outb(ahc, SIMODE1, simode1); 1495 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1496 } 1497 } 1498 1499 /* 1500 * Clear any pending interrupt status. 1501 */ 1502 void 1503 ahc_clear_intstat(struct ahc_softc *ahc) 1504 { 1505 /* Clear any interrupt conditions this may have caused */ 1506 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1507 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1508 CLRREQINIT); 1509 ahc_flush_device_writes(ahc); 1510 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1511 ahc_flush_device_writes(ahc); 1512 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1513 ahc_flush_device_writes(ahc); 1514 } 1515 1516 /**************************** Debugging Routines ******************************/ 1517 #ifdef AHC_DEBUG 1518 uint32_t ahc_debug = AHC_DEBUG_OPTS; 1519 #endif 1520 1521 void 1522 ahc_print_scb(struct scb *scb) 1523 { 1524 int i; 1525 1526 struct hardware_scb *hscb = scb->hscb; 1527 1528 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1529 (void *)scb, 1530 hscb->control, 1531 hscb->scsiid, 1532 hscb->lun, 1533 hscb->cdb_len); 1534 printf("Shared Data: "); 1535 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1536 printf("%#02x", hscb->shared_data.cdb[i]); 1537 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1538 ahc_le32toh(hscb->dataptr), 1539 ahc_le32toh(hscb->datacnt), 1540 ahc_le32toh(hscb->sgptr), 1541 hscb->tag); 1542 if (scb->sg_count > 0) { 1543 for (i = 0; i < scb->sg_count; i++) { 1544 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1545 i, 1546 (ahc_le32toh(scb->sg_list[i].len) >> 24 1547 & SG_HIGH_ADDR_BITS), 1548 ahc_le32toh(scb->sg_list[i].addr), 1549 ahc_le32toh(scb->sg_list[i].len)); 1550 } 1551 } 1552 } 1553 1554 /************************* Transfer Negotiation *******************************/ 1555 /* 1556 * Allocate per target mode instance (ID we respond to as a target) 1557 * transfer negotiation data structures. 1558 */ 1559 static struct ahc_tmode_tstate * 1560 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1561 { 1562 struct ahc_tmode_tstate *master_tstate; 1563 struct ahc_tmode_tstate *tstate; 1564 int i; 1565 1566 master_tstate = ahc->enabled_targets[ahc->our_id]; 1567 if (channel == 'B') { 1568 scsi_id += 8; 1569 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1570 } 1571 if (ahc->enabled_targets[scsi_id] != NULL 1572 && ahc->enabled_targets[scsi_id] != master_tstate) 1573 panic("%s: ahc_alloc_tstate - Target already allocated", 1574 ahc_name(ahc)); 1575 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1576 M_DEVBUF, M_NOWAIT); 1577 if (tstate == NULL) 1578 return (NULL); 1579 1580 /* 1581 * If we have allocated a master tstate, copy user settings from 1582 * the master tstate (taken from SRAM or the EEPROM) for this 1583 * channel, but reset our current and goal settings to async/narrow 1584 * until an initiator talks to us. 1585 */ 1586 if (master_tstate != NULL) { 1587 memcpy(tstate, master_tstate, sizeof(*tstate)); 1588 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1589 tstate->ultraenb = 0; 1590 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1591 memset(&tstate->transinfo[i].curr, 0, 1592 sizeof(tstate->transinfo[i].curr)); 1593 memset(&tstate->transinfo[i].goal, 0, 1594 sizeof(tstate->transinfo[i].goal)); 1595 } 1596 } else 1597 memset(tstate, 0, sizeof(*tstate)); 1598 ahc->enabled_targets[scsi_id] = tstate; 1599 return (tstate); 1600 } 1601 1602 #ifdef AHC_TARGET_MODE 1603 /* 1604 * Free per target mode instance (ID we respond to as a target) 1605 * transfer negotiation data structures. 1606 */ 1607 static void 1608 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1609 { 1610 struct ahc_tmode_tstate *tstate; 1611 1612 /* 1613 * Don't clean up our "master" tstate. 1614 * It has our default user settings. 1615 */ 1616 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1617 || (channel == 'A' && scsi_id == ahc->our_id)) 1618 && force == FALSE) 1619 return; 1620 1621 if (channel == 'B') 1622 scsi_id += 8; 1623 tstate = ahc->enabled_targets[scsi_id]; 1624 if (tstate != NULL) 1625 free(tstate, M_DEVBUF); 1626 ahc->enabled_targets[scsi_id] = NULL; 1627 } 1628 #endif 1629 1630 /* 1631 * Called when we have an active connection to a target on the bus, 1632 * this function finds the nearest syncrate to the input period limited 1633 * by the capabilities of the bus connectivity of and sync settings for 1634 * the target. 1635 */ 1636 struct ahc_syncrate * 1637 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1638 struct ahc_initiator_tinfo *tinfo, 1639 u_int *period, u_int *ppr_options, role_t role) 1640 { 1641 struct ahc_transinfo *transinfo; 1642 u_int maxsync; 1643 1644 if ((ahc->features & AHC_ULTRA2) != 0) { 1645 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1646 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1647 maxsync = AHC_SYNCRATE_DT; 1648 } else { 1649 maxsync = AHC_SYNCRATE_ULTRA; 1650 /* Can't do DT on an SE bus */ 1651 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1652 } 1653 } else if ((ahc->features & AHC_ULTRA) != 0) { 1654 maxsync = AHC_SYNCRATE_ULTRA; 1655 } else { 1656 maxsync = AHC_SYNCRATE_FAST; 1657 } 1658 /* 1659 * Never allow a value higher than our current goal 1660 * period otherwise we may allow a target initiated 1661 * negotiation to go above the limit as set by the 1662 * user. In the case of an initiator initiated 1663 * sync negotiation, we limit based on the user 1664 * setting. This allows the system to still accept 1665 * incoming negotiations even if target initiated 1666 * negotiation is not performed. 1667 */ 1668 if (role == ROLE_TARGET) 1669 transinfo = &tinfo->user; 1670 else 1671 transinfo = &tinfo->goal; 1672 *ppr_options &= transinfo->ppr_options; 1673 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1674 maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2); 1675 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1676 } 1677 if (transinfo->period == 0) { 1678 *period = 0; 1679 *ppr_options = 0; 1680 return (NULL); 1681 } 1682 *period = max(*period, (u_int)transinfo->period); 1683 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1684 } 1685 1686 /* 1687 * Look up the valid period to SCSIRATE conversion in our table. 1688 * Return the period and offset that should be sent to the target 1689 * if this was the beginning of an SDTR. 1690 */ 1691 struct ahc_syncrate * 1692 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1693 u_int *ppr_options, u_int maxsync) 1694 { 1695 struct ahc_syncrate *syncrate; 1696 1697 if ((ahc->features & AHC_DT) == 0) 1698 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1699 1700 /* Skip all DT only entries if DT is not available */ 1701 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1702 && maxsync < AHC_SYNCRATE_ULTRA2) 1703 maxsync = AHC_SYNCRATE_ULTRA2; 1704 1705 for (syncrate = &ahc_syncrates[maxsync]; 1706 syncrate->rate != NULL; 1707 syncrate++) { 1708 1709 /* 1710 * The Ultra2 table doesn't go as low 1711 * as for the Fast/Ultra cards. 1712 */ 1713 if ((ahc->features & AHC_ULTRA2) != 0 1714 && (syncrate->sxfr_u2 == 0)) 1715 break; 1716 1717 if (*period <= syncrate->period) { 1718 /* 1719 * When responding to a target that requests 1720 * sync, the requested rate may fall between 1721 * two rates that we can output, but still be 1722 * a rate that we can receive. Because of this, 1723 * we want to respond to the target with 1724 * the same rate that it sent to us even 1725 * if the period we use to send data to it 1726 * is lower. Only lower the response period 1727 * if we must. 1728 */ 1729 if (syncrate == &ahc_syncrates[maxsync]) 1730 *period = syncrate->period; 1731 1732 /* 1733 * At some speeds, we only support 1734 * ST transfers. 1735 */ 1736 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1737 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1738 break; 1739 } 1740 } 1741 1742 if ((*period == 0) 1743 || (syncrate->rate == NULL) 1744 || ((ahc->features & AHC_ULTRA2) != 0 1745 && (syncrate->sxfr_u2 == 0))) { 1746 /* Use asynchronous transfers. */ 1747 *period = 0; 1748 syncrate = NULL; 1749 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1750 } 1751 return (syncrate); 1752 } 1753 1754 /* 1755 * Convert from an entry in our syncrate table to the SCSI equivalent 1756 * sync "period" factor. 1757 */ 1758 u_int 1759 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1760 { 1761 struct ahc_syncrate *syncrate; 1762 1763 if ((ahc->features & AHC_ULTRA2) != 0) 1764 scsirate &= SXFR_ULTRA2; 1765 else 1766 scsirate &= SXFR; 1767 1768 syncrate = &ahc_syncrates[maxsync]; 1769 while (syncrate->rate != NULL) { 1770 1771 if ((ahc->features & AHC_ULTRA2) != 0) { 1772 if (syncrate->sxfr_u2 == 0) 1773 break; 1774 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1775 return (syncrate->period); 1776 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1777 return (syncrate->period); 1778 } 1779 syncrate++; 1780 } 1781 return (0); /* async */ 1782 } 1783 1784 /* 1785 * Truncate the given synchronous offset to a value the 1786 * current adapter type and syncrate are capable of. 1787 */ 1788 void 1789 ahc_validate_offset(struct ahc_softc *ahc, 1790 struct ahc_initiator_tinfo *tinfo, 1791 struct ahc_syncrate *syncrate, 1792 u_int *offset, int wide, role_t role) 1793 { 1794 u_int maxoffset; 1795 1796 /* Limit offset to what we can do */ 1797 if (syncrate == NULL) { 1798 maxoffset = 0; 1799 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1800 maxoffset = MAX_OFFSET_ULTRA2; 1801 } else { 1802 if (wide) 1803 maxoffset = MAX_OFFSET_16BIT; 1804 else 1805 maxoffset = MAX_OFFSET_8BIT; 1806 } 1807 *offset = min(*offset, maxoffset); 1808 if (tinfo != NULL) { 1809 if (role == ROLE_TARGET) 1810 *offset = min(*offset, (u_int)tinfo->user.offset); 1811 else 1812 *offset = min(*offset, (u_int)tinfo->goal.offset); 1813 } 1814 } 1815 1816 /* 1817 * Truncate the given transfer width parameter to a value the 1818 * current adapter type is capable of. 1819 */ 1820 void 1821 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1822 u_int *bus_width, role_t role) 1823 { 1824 switch (*bus_width) { 1825 default: 1826 if (ahc->features & AHC_WIDE) { 1827 /* Respond Wide */ 1828 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1829 break; 1830 } 1831 /* FALLTHROUGH */ 1832 case MSG_EXT_WDTR_BUS_8_BIT: 1833 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1834 break; 1835 } 1836 if (tinfo != NULL) { 1837 if (role == ROLE_TARGET) 1838 *bus_width = min((u_int)tinfo->user.width, *bus_width); 1839 else 1840 *bus_width = min((u_int)tinfo->goal.width, *bus_width); 1841 } 1842 } 1843 1844 /* 1845 * Update the bitmask of targets for which the controller should 1846 * negotiate with at the next convenient oportunity. This currently 1847 * means the next time we send the initial identify messages for 1848 * a new transaction. 1849 */ 1850 int 1851 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1852 struct ahc_tmode_tstate *tstate, 1853 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1854 { 1855 u_int auto_negotiate_orig; 1856 1857 auto_negotiate_orig = tstate->auto_negotiate; 1858 if (neg_type == AHC_NEG_ALWAYS) { 1859 /* 1860 * Force our "current" settings to be 1861 * unknown so that unless a bus reset 1862 * occurs the need to renegotiate is 1863 * recorded persistently. 1864 */ 1865 if ((ahc->features & AHC_WIDE) != 0) 1866 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1867 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1868 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1869 } 1870 if (tinfo->curr.period != tinfo->goal.period 1871 || tinfo->curr.width != tinfo->goal.width 1872 || tinfo->curr.offset != tinfo->goal.offset 1873 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1874 || (neg_type == AHC_NEG_IF_NON_ASYNC 1875 && (tinfo->goal.offset != 0 1876 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1877 || tinfo->goal.ppr_options != 0))) 1878 tstate->auto_negotiate |= devinfo->target_mask; 1879 else 1880 tstate->auto_negotiate &= ~devinfo->target_mask; 1881 1882 return (auto_negotiate_orig != tstate->auto_negotiate); 1883 } 1884 1885 /* 1886 * Update the user/goal/curr tables of synchronous negotiation 1887 * parameters as well as, in the case of a current or active update, 1888 * any data structures on the host controller. In the case of an 1889 * active update, the specified target is currently talking to us on 1890 * the bus, so the transfer parameter update must take effect 1891 * immediately. 1892 */ 1893 void 1894 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1895 struct ahc_syncrate *syncrate, u_int period, 1896 u_int offset, u_int ppr_options, u_int type, int paused) 1897 { 1898 struct ahc_initiator_tinfo *tinfo; 1899 struct ahc_tmode_tstate *tstate; 1900 u_int old_period; 1901 u_int old_offset; 1902 u_int old_ppr; 1903 int active; 1904 int update_needed; 1905 1906 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1907 update_needed = 0; 1908 1909 if (syncrate == NULL) { 1910 period = 0; 1911 offset = 0; 1912 } 1913 1914 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1915 devinfo->target, &tstate); 1916 1917 if ((type & AHC_TRANS_USER) != 0) { 1918 tinfo->user.period = period; 1919 tinfo->user.offset = offset; 1920 tinfo->user.ppr_options = ppr_options; 1921 } 1922 1923 if ((type & AHC_TRANS_GOAL) != 0) { 1924 tinfo->goal.period = period; 1925 tinfo->goal.offset = offset; 1926 tinfo->goal.ppr_options = ppr_options; 1927 } 1928 1929 old_period = tinfo->curr.period; 1930 old_offset = tinfo->curr.offset; 1931 old_ppr = tinfo->curr.ppr_options; 1932 1933 if ((type & AHC_TRANS_CUR) != 0 1934 && (old_period != period 1935 || old_offset != offset 1936 || old_ppr != ppr_options)) { 1937 u_int scsirate; 1938 1939 update_needed++; 1940 scsirate = tinfo->scsirate; 1941 if ((ahc->features & AHC_ULTRA2) != 0) { 1942 1943 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1944 if (syncrate != NULL) { 1945 scsirate |= syncrate->sxfr_u2; 1946 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1947 scsirate |= ENABLE_CRC; 1948 else 1949 scsirate |= SINGLE_EDGE; 1950 } 1951 } else { 1952 1953 scsirate &= ~(SXFR|SOFS); 1954 /* 1955 * Ensure Ultra mode is set properly for 1956 * this target. 1957 */ 1958 tstate->ultraenb &= ~devinfo->target_mask; 1959 if (syncrate != NULL) { 1960 if (syncrate->sxfr & ULTRA_SXFR) { 1961 tstate->ultraenb |= 1962 devinfo->target_mask; 1963 } 1964 scsirate |= syncrate->sxfr & SXFR; 1965 scsirate |= offset & SOFS; 1966 } 1967 if (active) { 1968 u_int sxfrctl0; 1969 1970 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1971 sxfrctl0 &= ~FAST20; 1972 if (tstate->ultraenb & devinfo->target_mask) 1973 sxfrctl0 |= FAST20; 1974 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1975 } 1976 } 1977 if (active) { 1978 ahc_outb(ahc, SCSIRATE, scsirate); 1979 if ((ahc->features & AHC_ULTRA2) != 0) 1980 ahc_outb(ahc, SCSIOFFSET, offset); 1981 } 1982 1983 tinfo->scsirate = scsirate; 1984 tinfo->curr.period = period; 1985 tinfo->curr.offset = offset; 1986 tinfo->curr.ppr_options = ppr_options; 1987 1988 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1989 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 1990 if (bootverbose) { 1991 if (offset != 0) { 1992 printf("%s: target %d synchronous at %sMHz%s, " 1993 "offset = 0x%x\n", ahc_name(ahc), 1994 devinfo->target, syncrate->rate, 1995 (ppr_options & MSG_EXT_PPR_DT_REQ) 1996 ? " DT" : "", offset); 1997 } else { 1998 printf("%s: target %d using " 1999 "asynchronous transfers\n", 2000 ahc_name(ahc), devinfo->target); 2001 } 2002 } 2003 } 2004 2005 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2006 tinfo, AHC_NEG_TO_GOAL); 2007 2008 if (update_needed) 2009 ahc_update_pending_scbs(ahc); 2010 } 2011 2012 /* 2013 * Update the user/goal/curr tables of wide negotiation 2014 * parameters as well as, in the case of a current or active update, 2015 * any data structures on the host controller. In the case of an 2016 * active update, the specified target is currently talking to us on 2017 * the bus, so the transfer parameter update must take effect 2018 * immediately. 2019 */ 2020 void 2021 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2022 u_int width, u_int type, int paused) 2023 { 2024 struct ahc_initiator_tinfo *tinfo; 2025 struct ahc_tmode_tstate *tstate; 2026 u_int oldwidth; 2027 int active; 2028 int update_needed; 2029 2030 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2031 update_needed = 0; 2032 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2033 devinfo->target, &tstate); 2034 2035 if ((type & AHC_TRANS_USER) != 0) 2036 tinfo->user.width = width; 2037 2038 if ((type & AHC_TRANS_GOAL) != 0) 2039 tinfo->goal.width = width; 2040 2041 oldwidth = tinfo->curr.width; 2042 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2043 u_int scsirate; 2044 2045 update_needed++; 2046 scsirate = tinfo->scsirate; 2047 scsirate &= ~WIDEXFER; 2048 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2049 scsirate |= WIDEXFER; 2050 2051 tinfo->scsirate = scsirate; 2052 2053 if (active) 2054 ahc_outb(ahc, SCSIRATE, scsirate); 2055 2056 tinfo->curr.width = width; 2057 2058 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2059 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 2060 if (bootverbose) { 2061 printf("%s: target %d using %dbit transfers\n", 2062 ahc_name(ahc), devinfo->target, 2063 8 * (0x01 << width)); 2064 } 2065 } 2066 2067 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2068 tinfo, AHC_NEG_TO_GOAL); 2069 if (update_needed) 2070 ahc_update_pending_scbs(ahc); 2071 } 2072 2073 /* 2074 * Update the current state of tagged queuing for a given target. 2075 */ 2076 static void 2077 ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd, 2078 struct ahc_devinfo *devinfo, ahc_queue_alg alg) 2079 { 2080 struct scsi_device *sdev = cmd->device; 2081 2082 ahc_platform_set_tags(ahc, sdev, devinfo, alg); 2083 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2084 devinfo->lun, AC_TRANSFER_NEG); 2085 } 2086 2087 /* 2088 * When the transfer settings for a connection change, update any 2089 * in-transit SCBs to contain the new data so the hardware will 2090 * be set correctly during future (re)selections. 2091 */ 2092 static void 2093 ahc_update_pending_scbs(struct ahc_softc *ahc) 2094 { 2095 struct scb *pending_scb; 2096 int pending_scb_count; 2097 int i; 2098 int paused; 2099 u_int saved_scbptr; 2100 2101 /* 2102 * Traverse the pending SCB list and ensure that all of the 2103 * SCBs there have the proper settings. 2104 */ 2105 pending_scb_count = 0; 2106 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2107 struct ahc_devinfo devinfo; 2108 struct hardware_scb *pending_hscb; 2109 struct ahc_initiator_tinfo *tinfo; 2110 struct ahc_tmode_tstate *tstate; 2111 2112 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2113 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2114 devinfo.our_scsiid, 2115 devinfo.target, &tstate); 2116 pending_hscb = pending_scb->hscb; 2117 pending_hscb->control &= ~ULTRAENB; 2118 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2119 pending_hscb->control |= ULTRAENB; 2120 pending_hscb->scsirate = tinfo->scsirate; 2121 pending_hscb->scsioffset = tinfo->curr.offset; 2122 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2123 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2124 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2125 pending_hscb->control &= ~MK_MESSAGE; 2126 } 2127 ahc_sync_scb(ahc, pending_scb, 2128 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2129 pending_scb_count++; 2130 } 2131 2132 if (pending_scb_count == 0) 2133 return; 2134 2135 if (ahc_is_paused(ahc)) { 2136 paused = 1; 2137 } else { 2138 paused = 0; 2139 ahc_pause(ahc); 2140 } 2141 2142 saved_scbptr = ahc_inb(ahc, SCBPTR); 2143 /* Ensure that the hscbs down on the card match the new information */ 2144 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2145 struct hardware_scb *pending_hscb; 2146 u_int control; 2147 u_int scb_tag; 2148 2149 ahc_outb(ahc, SCBPTR, i); 2150 scb_tag = ahc_inb(ahc, SCB_TAG); 2151 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2152 if (pending_scb == NULL) 2153 continue; 2154 2155 pending_hscb = pending_scb->hscb; 2156 control = ahc_inb(ahc, SCB_CONTROL); 2157 control &= ~(ULTRAENB|MK_MESSAGE); 2158 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2159 ahc_outb(ahc, SCB_CONTROL, control); 2160 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2161 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2162 } 2163 ahc_outb(ahc, SCBPTR, saved_scbptr); 2164 2165 if (paused == 0) 2166 ahc_unpause(ahc); 2167 } 2168 2169 /**************************** Pathing Information *****************************/ 2170 static void 2171 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2172 { 2173 u_int saved_scsiid; 2174 role_t role; 2175 int our_id; 2176 2177 if (ahc_inb(ahc, SSTAT0) & TARGET) 2178 role = ROLE_TARGET; 2179 else 2180 role = ROLE_INITIATOR; 2181 2182 if (role == ROLE_TARGET 2183 && (ahc->features & AHC_MULTI_TID) != 0 2184 && (ahc_inb(ahc, SEQ_FLAGS) 2185 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2186 /* We were selected, so pull our id from TARGIDIN */ 2187 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2188 } else if ((ahc->features & AHC_ULTRA2) != 0) 2189 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2190 else 2191 our_id = ahc_inb(ahc, SCSIID) & OID; 2192 2193 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2194 ahc_compile_devinfo(devinfo, 2195 our_id, 2196 SCSIID_TARGET(ahc, saved_scsiid), 2197 ahc_inb(ahc, SAVED_LUN), 2198 SCSIID_CHANNEL(ahc, saved_scsiid), 2199 role); 2200 } 2201 2202 struct ahc_phase_table_entry* 2203 ahc_lookup_phase_entry(int phase) 2204 { 2205 struct ahc_phase_table_entry *entry; 2206 struct ahc_phase_table_entry *last_entry; 2207 2208 /* 2209 * num_phases doesn't include the default entry which 2210 * will be returned if the phase doesn't match. 2211 */ 2212 last_entry = &ahc_phase_table[num_phases]; 2213 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2214 if (phase == entry->phase) 2215 break; 2216 } 2217 return (entry); 2218 } 2219 2220 void 2221 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2222 u_int lun, char channel, role_t role) 2223 { 2224 devinfo->our_scsiid = our_id; 2225 devinfo->target = target; 2226 devinfo->lun = lun; 2227 devinfo->target_offset = target; 2228 devinfo->channel = channel; 2229 devinfo->role = role; 2230 if (channel == 'B') 2231 devinfo->target_offset += 8; 2232 devinfo->target_mask = (0x01 << devinfo->target_offset); 2233 } 2234 2235 void 2236 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2237 { 2238 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2239 devinfo->target, devinfo->lun); 2240 } 2241 2242 static void 2243 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2244 struct scb *scb) 2245 { 2246 role_t role; 2247 int our_id; 2248 2249 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2250 role = ROLE_INITIATOR; 2251 if ((scb->flags & SCB_TARGET_SCB) != 0) 2252 role = ROLE_TARGET; 2253 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2254 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2255 } 2256 2257 2258 /************************ Message Phase Processing ****************************/ 2259 static void 2260 ahc_assert_atn(struct ahc_softc *ahc) 2261 { 2262 u_int scsisigo; 2263 2264 scsisigo = ATNO; 2265 if ((ahc->features & AHC_DT) == 0) 2266 scsisigo |= ahc_inb(ahc, SCSISIGI); 2267 ahc_outb(ahc, SCSISIGO, scsisigo); 2268 } 2269 2270 /* 2271 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2272 * or enters the initial message out phase, we are interrupted. Fill our 2273 * outgoing message buffer with the appropriate message and beging handing 2274 * the message phase(s) manually. 2275 */ 2276 static void 2277 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2278 struct scb *scb) 2279 { 2280 /* 2281 * To facilitate adding multiple messages together, 2282 * each routine should increment the index and len 2283 * variables instead of setting them explicitly. 2284 */ 2285 ahc->msgout_index = 0; 2286 ahc->msgout_len = 0; 2287 2288 if ((scb->flags & SCB_DEVICE_RESET) == 0 2289 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2290 u_int identify_msg; 2291 2292 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2293 if ((scb->hscb->control & DISCENB) != 0) 2294 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2295 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2296 ahc->msgout_len++; 2297 2298 if ((scb->hscb->control & TAG_ENB) != 0) { 2299 ahc->msgout_buf[ahc->msgout_index++] = 2300 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2301 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2302 ahc->msgout_len += 2; 2303 } 2304 } 2305 2306 if (scb->flags & SCB_DEVICE_RESET) { 2307 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2308 ahc->msgout_len++; 2309 ahc_print_path(ahc, scb); 2310 printf("Bus Device Reset Message Sent\n"); 2311 /* 2312 * Clear our selection hardware in advance of 2313 * the busfree. We may have an entry in the waiting 2314 * Q for this target, and we don't want to go about 2315 * selecting while we handle the busfree and blow it 2316 * away. 2317 */ 2318 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2319 } else if ((scb->flags & SCB_ABORT) != 0) { 2320 if ((scb->hscb->control & TAG_ENB) != 0) 2321 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2322 else 2323 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2324 ahc->msgout_len++; 2325 ahc_print_path(ahc, scb); 2326 printf("Abort%s Message Sent\n", 2327 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2328 /* 2329 * Clear our selection hardware in advance of 2330 * the busfree. We may have an entry in the waiting 2331 * Q for this target, and we don't want to go about 2332 * selecting while we handle the busfree and blow it 2333 * away. 2334 */ 2335 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2336 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2337 ahc_build_transfer_msg(ahc, devinfo); 2338 } else { 2339 printf("ahc_intr: AWAITING_MSG for an SCB that " 2340 "does not have a waiting message\n"); 2341 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2342 devinfo->target_mask); 2343 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2344 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2345 ahc_inb(ahc, MSG_OUT), scb->flags); 2346 } 2347 2348 /* 2349 * Clear the MK_MESSAGE flag from the SCB so we aren't 2350 * asked to send this message again. 2351 */ 2352 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2353 scb->hscb->control &= ~MK_MESSAGE; 2354 ahc->msgout_index = 0; 2355 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2356 } 2357 2358 /* 2359 * Build an appropriate transfer negotiation message for the 2360 * currently active target. 2361 */ 2362 static void 2363 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2364 { 2365 /* 2366 * We need to initiate transfer negotiations. 2367 * If our current and goal settings are identical, 2368 * we want to renegotiate due to a check condition. 2369 */ 2370 struct ahc_initiator_tinfo *tinfo; 2371 struct ahc_tmode_tstate *tstate; 2372 struct ahc_syncrate *rate; 2373 int dowide; 2374 int dosync; 2375 int doppr; 2376 u_int period; 2377 u_int ppr_options; 2378 u_int offset; 2379 2380 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2381 devinfo->target, &tstate); 2382 /* 2383 * Filter our period based on the current connection. 2384 * If we can't perform DT transfers on this segment (not in LVD 2385 * mode for instance), then our decision to issue a PPR message 2386 * may change. 2387 */ 2388 period = tinfo->goal.period; 2389 offset = tinfo->goal.offset; 2390 ppr_options = tinfo->goal.ppr_options; 2391 /* Target initiated PPR is not allowed in the SCSI spec */ 2392 if (devinfo->role == ROLE_TARGET) 2393 ppr_options = 0; 2394 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2395 &ppr_options, devinfo->role); 2396 dowide = tinfo->curr.width != tinfo->goal.width; 2397 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 2398 /* 2399 * Only use PPR if we have options that need it, even if the device 2400 * claims to support it. There might be an expander in the way 2401 * that doesn't. 2402 */ 2403 doppr = ppr_options != 0; 2404 2405 if (!dowide && !dosync && !doppr) { 2406 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2407 dosync = tinfo->goal.offset != 0; 2408 } 2409 2410 if (!dowide && !dosync && !doppr) { 2411 /* 2412 * Force async with a WDTR message if we have a wide bus, 2413 * or just issue an SDTR with a 0 offset. 2414 */ 2415 if ((ahc->features & AHC_WIDE) != 0) 2416 dowide = 1; 2417 else 2418 dosync = 1; 2419 2420 if (bootverbose) { 2421 ahc_print_devinfo(ahc, devinfo); 2422 printf("Ensuring async\n"); 2423 } 2424 } 2425 2426 /* Target initiated PPR is not allowed in the SCSI spec */ 2427 if (devinfo->role == ROLE_TARGET) 2428 doppr = 0; 2429 2430 /* 2431 * Both the PPR message and SDTR message require the 2432 * goal syncrate to be limited to what the target device 2433 * is capable of handling (based on whether an LVD->SE 2434 * expander is on the bus), so combine these two cases. 2435 * Regardless, guarantee that if we are using WDTR and SDTR 2436 * messages that WDTR comes first. 2437 */ 2438 if (doppr || (dosync && !dowide)) { 2439 2440 offset = tinfo->goal.offset; 2441 ahc_validate_offset(ahc, tinfo, rate, &offset, 2442 doppr ? tinfo->goal.width 2443 : tinfo->curr.width, 2444 devinfo->role); 2445 if (doppr) { 2446 ahc_construct_ppr(ahc, devinfo, period, offset, 2447 tinfo->goal.width, ppr_options); 2448 } else { 2449 ahc_construct_sdtr(ahc, devinfo, period, offset); 2450 } 2451 } else { 2452 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2453 } 2454 } 2455 2456 /* 2457 * Build a synchronous negotiation message in our message 2458 * buffer based on the input parameters. 2459 */ 2460 static void 2461 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2462 u_int period, u_int offset) 2463 { 2464 if (offset == 0) 2465 period = AHC_ASYNC_XFER_PERIOD; 2466 ahc->msgout_index += spi_populate_sync_msg( 2467 ahc->msgout_buf + ahc->msgout_index, period, offset); 2468 ahc->msgout_len += 5; 2469 if (bootverbose) { 2470 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2471 ahc_name(ahc), devinfo->channel, devinfo->target, 2472 devinfo->lun, period, offset); 2473 } 2474 } 2475 2476 /* 2477 * Build a wide negotiation message in our message 2478 * buffer based on the input parameters. 2479 */ 2480 static void 2481 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2482 u_int bus_width) 2483 { 2484 ahc->msgout_index += spi_populate_width_msg( 2485 ahc->msgout_buf + ahc->msgout_index, bus_width); 2486 ahc->msgout_len += 4; 2487 if (bootverbose) { 2488 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2489 ahc_name(ahc), devinfo->channel, devinfo->target, 2490 devinfo->lun, bus_width); 2491 } 2492 } 2493 2494 /* 2495 * Build a parallel protocol request message in our message 2496 * buffer based on the input parameters. 2497 */ 2498 static void 2499 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2500 u_int period, u_int offset, u_int bus_width, 2501 u_int ppr_options) 2502 { 2503 if (offset == 0) 2504 period = AHC_ASYNC_XFER_PERIOD; 2505 ahc->msgout_index += spi_populate_ppr_msg( 2506 ahc->msgout_buf + ahc->msgout_index, period, offset, 2507 bus_width, ppr_options); 2508 ahc->msgout_len += 8; 2509 if (bootverbose) { 2510 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2511 "offset %x, ppr_options %x\n", ahc_name(ahc), 2512 devinfo->channel, devinfo->target, devinfo->lun, 2513 bus_width, period, offset, ppr_options); 2514 } 2515 } 2516 2517 /* 2518 * Clear any active message state. 2519 */ 2520 static void 2521 ahc_clear_msg_state(struct ahc_softc *ahc) 2522 { 2523 ahc->msgout_len = 0; 2524 ahc->msgin_index = 0; 2525 ahc->msg_type = MSG_TYPE_NONE; 2526 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2527 /* 2528 * The target didn't care to respond to our 2529 * message request, so clear ATN. 2530 */ 2531 ahc_outb(ahc, CLRSINT1, CLRATNO); 2532 } 2533 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2534 ahc_outb(ahc, SEQ_FLAGS2, 2535 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2536 } 2537 2538 static void 2539 ahc_handle_proto_violation(struct ahc_softc *ahc) 2540 { 2541 struct ahc_devinfo devinfo; 2542 struct scb *scb; 2543 u_int scbid; 2544 u_int seq_flags; 2545 u_int curphase; 2546 u_int lastphase; 2547 int found; 2548 2549 ahc_fetch_devinfo(ahc, &devinfo); 2550 scbid = ahc_inb(ahc, SCB_TAG); 2551 scb = ahc_lookup_scb(ahc, scbid); 2552 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2553 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2554 lastphase = ahc_inb(ahc, LASTPHASE); 2555 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2556 2557 /* 2558 * The reconnecting target either did not send an 2559 * identify message, or did, but we didn't find an SCB 2560 * to match. 2561 */ 2562 ahc_print_devinfo(ahc, &devinfo); 2563 printf("Target did not send an IDENTIFY message. " 2564 "LASTPHASE = 0x%x.\n", lastphase); 2565 scb = NULL; 2566 } else if (scb == NULL) { 2567 /* 2568 * We don't seem to have an SCB active for this 2569 * transaction. Print an error and reset the bus. 2570 */ 2571 ahc_print_devinfo(ahc, &devinfo); 2572 printf("No SCB found during protocol violation\n"); 2573 goto proto_violation_reset; 2574 } else { 2575 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2576 if ((seq_flags & NO_CDB_SENT) != 0) { 2577 ahc_print_path(ahc, scb); 2578 printf("No or incomplete CDB sent to device.\n"); 2579 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2580 /* 2581 * The target never bothered to provide status to 2582 * us prior to completing the command. Since we don't 2583 * know the disposition of this command, we must attempt 2584 * to abort it. Assert ATN and prepare to send an abort 2585 * message. 2586 */ 2587 ahc_print_path(ahc, scb); 2588 printf("Completed command without status.\n"); 2589 } else { 2590 ahc_print_path(ahc, scb); 2591 printf("Unknown protocol violation.\n"); 2592 ahc_dump_card_state(ahc); 2593 } 2594 } 2595 if ((lastphase & ~P_DATAIN_DT) == 0 2596 || lastphase == P_COMMAND) { 2597 proto_violation_reset: 2598 /* 2599 * Target either went directly to data/command 2600 * phase or didn't respond to our ATN. 2601 * The only safe thing to do is to blow 2602 * it away with a bus reset. 2603 */ 2604 found = ahc_reset_channel(ahc, 'A', TRUE); 2605 printf("%s: Issued Channel %c Bus Reset. " 2606 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2607 } else { 2608 /* 2609 * Leave the selection hardware off in case 2610 * this abort attempt will affect yet to 2611 * be sent commands. 2612 */ 2613 ahc_outb(ahc, SCSISEQ, 2614 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2615 ahc_assert_atn(ahc); 2616 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2617 if (scb == NULL) { 2618 ahc_print_devinfo(ahc, &devinfo); 2619 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2620 ahc->msgout_len = 1; 2621 ahc->msgout_index = 0; 2622 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2623 } else { 2624 ahc_print_path(ahc, scb); 2625 scb->flags |= SCB_ABORT; 2626 } 2627 printf("Protocol violation %s. Attempting to abort.\n", 2628 ahc_lookup_phase_entry(curphase)->phasemsg); 2629 } 2630 } 2631 2632 /* 2633 * Manual message loop handler. 2634 */ 2635 static void 2636 ahc_handle_message_phase(struct ahc_softc *ahc) 2637 { 2638 struct ahc_devinfo devinfo; 2639 u_int bus_phase; 2640 int end_session; 2641 2642 ahc_fetch_devinfo(ahc, &devinfo); 2643 end_session = FALSE; 2644 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2645 2646 reswitch: 2647 switch (ahc->msg_type) { 2648 case MSG_TYPE_INITIATOR_MSGOUT: 2649 { 2650 int lastbyte; 2651 int phasemis; 2652 int msgdone; 2653 2654 if (ahc->msgout_len == 0) 2655 panic("HOST_MSG_LOOP interrupt with no active message"); 2656 2657 #ifdef AHC_DEBUG 2658 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2659 ahc_print_devinfo(ahc, &devinfo); 2660 printf("INITIATOR_MSG_OUT"); 2661 } 2662 #endif 2663 phasemis = bus_phase != P_MESGOUT; 2664 if (phasemis) { 2665 #ifdef AHC_DEBUG 2666 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2667 printf(" PHASEMIS %s\n", 2668 ahc_lookup_phase_entry(bus_phase) 2669 ->phasemsg); 2670 } 2671 #endif 2672 if (bus_phase == P_MESGIN) { 2673 /* 2674 * Change gears and see if 2675 * this messages is of interest to 2676 * us or should be passed back to 2677 * the sequencer. 2678 */ 2679 ahc_outb(ahc, CLRSINT1, CLRATNO); 2680 ahc->send_msg_perror = FALSE; 2681 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2682 ahc->msgin_index = 0; 2683 goto reswitch; 2684 } 2685 end_session = TRUE; 2686 break; 2687 } 2688 2689 if (ahc->send_msg_perror) { 2690 ahc_outb(ahc, CLRSINT1, CLRATNO); 2691 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2692 #ifdef AHC_DEBUG 2693 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2694 printf(" byte 0x%x\n", ahc->send_msg_perror); 2695 #endif 2696 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2697 break; 2698 } 2699 2700 msgdone = ahc->msgout_index == ahc->msgout_len; 2701 if (msgdone) { 2702 /* 2703 * The target has requested a retry. 2704 * Re-assert ATN, reset our message index to 2705 * 0, and try again. 2706 */ 2707 ahc->msgout_index = 0; 2708 ahc_assert_atn(ahc); 2709 } 2710 2711 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2712 if (lastbyte) { 2713 /* Last byte is signified by dropping ATN */ 2714 ahc_outb(ahc, CLRSINT1, CLRATNO); 2715 } 2716 2717 /* 2718 * Clear our interrupt status and present 2719 * the next byte on the bus. 2720 */ 2721 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2722 #ifdef AHC_DEBUG 2723 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2724 printf(" byte 0x%x\n", 2725 ahc->msgout_buf[ahc->msgout_index]); 2726 #endif 2727 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2728 break; 2729 } 2730 case MSG_TYPE_INITIATOR_MSGIN: 2731 { 2732 int phasemis; 2733 int message_done; 2734 2735 #ifdef AHC_DEBUG 2736 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2737 ahc_print_devinfo(ahc, &devinfo); 2738 printf("INITIATOR_MSG_IN"); 2739 } 2740 #endif 2741 phasemis = bus_phase != P_MESGIN; 2742 if (phasemis) { 2743 #ifdef AHC_DEBUG 2744 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2745 printf(" PHASEMIS %s\n", 2746 ahc_lookup_phase_entry(bus_phase) 2747 ->phasemsg); 2748 } 2749 #endif 2750 ahc->msgin_index = 0; 2751 if (bus_phase == P_MESGOUT 2752 && (ahc->send_msg_perror == TRUE 2753 || (ahc->msgout_len != 0 2754 && ahc->msgout_index == 0))) { 2755 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2756 goto reswitch; 2757 } 2758 end_session = TRUE; 2759 break; 2760 } 2761 2762 /* Pull the byte in without acking it */ 2763 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2764 #ifdef AHC_DEBUG 2765 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2766 printf(" byte 0x%x\n", 2767 ahc->msgin_buf[ahc->msgin_index]); 2768 #endif 2769 2770 message_done = ahc_parse_msg(ahc, &devinfo); 2771 2772 if (message_done) { 2773 /* 2774 * Clear our incoming message buffer in case there 2775 * is another message following this one. 2776 */ 2777 ahc->msgin_index = 0; 2778 2779 /* 2780 * If this message illicited a response, 2781 * assert ATN so the target takes us to the 2782 * message out phase. 2783 */ 2784 if (ahc->msgout_len != 0) { 2785 #ifdef AHC_DEBUG 2786 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2787 ahc_print_devinfo(ahc, &devinfo); 2788 printf("Asserting ATN for response\n"); 2789 } 2790 #endif 2791 ahc_assert_atn(ahc); 2792 } 2793 } else 2794 ahc->msgin_index++; 2795 2796 if (message_done == MSGLOOP_TERMINATED) { 2797 end_session = TRUE; 2798 } else { 2799 /* Ack the byte */ 2800 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2801 ahc_inb(ahc, SCSIDATL); 2802 } 2803 break; 2804 } 2805 case MSG_TYPE_TARGET_MSGIN: 2806 { 2807 int msgdone; 2808 int msgout_request; 2809 2810 if (ahc->msgout_len == 0) 2811 panic("Target MSGIN with no active message"); 2812 2813 /* 2814 * If we interrupted a mesgout session, the initiator 2815 * will not know this until our first REQ. So, we 2816 * only honor mesgout requests after we've sent our 2817 * first byte. 2818 */ 2819 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2820 && ahc->msgout_index > 0) 2821 msgout_request = TRUE; 2822 else 2823 msgout_request = FALSE; 2824 2825 if (msgout_request) { 2826 2827 /* 2828 * Change gears and see if 2829 * this messages is of interest to 2830 * us or should be passed back to 2831 * the sequencer. 2832 */ 2833 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2834 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2835 ahc->msgin_index = 0; 2836 /* Dummy read to REQ for first byte */ 2837 ahc_inb(ahc, SCSIDATL); 2838 ahc_outb(ahc, SXFRCTL0, 2839 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2840 break; 2841 } 2842 2843 msgdone = ahc->msgout_index == ahc->msgout_len; 2844 if (msgdone) { 2845 ahc_outb(ahc, SXFRCTL0, 2846 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2847 end_session = TRUE; 2848 break; 2849 } 2850 2851 /* 2852 * Present the next byte on the bus. 2853 */ 2854 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2855 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2856 break; 2857 } 2858 case MSG_TYPE_TARGET_MSGOUT: 2859 { 2860 int lastbyte; 2861 int msgdone; 2862 2863 /* 2864 * The initiator signals that this is 2865 * the last byte by dropping ATN. 2866 */ 2867 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2868 2869 /* 2870 * Read the latched byte, but turn off SPIOEN first 2871 * so that we don't inadvertently cause a REQ for the 2872 * next byte. 2873 */ 2874 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2875 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2876 msgdone = ahc_parse_msg(ahc, &devinfo); 2877 if (msgdone == MSGLOOP_TERMINATED) { 2878 /* 2879 * The message is *really* done in that it caused 2880 * us to go to bus free. The sequencer has already 2881 * been reset at this point, so pull the ejection 2882 * handle. 2883 */ 2884 return; 2885 } 2886 2887 ahc->msgin_index++; 2888 2889 /* 2890 * XXX Read spec about initiator dropping ATN too soon 2891 * and use msgdone to detect it. 2892 */ 2893 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2894 ahc->msgin_index = 0; 2895 2896 /* 2897 * If this message illicited a response, transition 2898 * to the Message in phase and send it. 2899 */ 2900 if (ahc->msgout_len != 0) { 2901 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2902 ahc_outb(ahc, SXFRCTL0, 2903 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2904 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2905 ahc->msgin_index = 0; 2906 break; 2907 } 2908 } 2909 2910 if (lastbyte) 2911 end_session = TRUE; 2912 else { 2913 /* Ask for the next byte. */ 2914 ahc_outb(ahc, SXFRCTL0, 2915 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2916 } 2917 2918 break; 2919 } 2920 default: 2921 panic("Unknown REQINIT message type"); 2922 } 2923 2924 if (end_session) { 2925 ahc_clear_msg_state(ahc); 2926 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2927 } else 2928 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2929 } 2930 2931 /* 2932 * See if we sent a particular extended message to the target. 2933 * If "full" is true, return true only if the target saw the full 2934 * message. If "full" is false, return true if the target saw at 2935 * least the first byte of the message. 2936 */ 2937 static int 2938 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2939 { 2940 int found; 2941 u_int index; 2942 2943 found = FALSE; 2944 index = 0; 2945 2946 while (index < ahc->msgout_len) { 2947 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2948 u_int end_index; 2949 2950 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2951 if (ahc->msgout_buf[index+2] == msgval 2952 && type == AHCMSG_EXT) { 2953 2954 if (full) { 2955 if (ahc->msgout_index > end_index) 2956 found = TRUE; 2957 } else if (ahc->msgout_index > index) 2958 found = TRUE; 2959 } 2960 index = end_index; 2961 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2962 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2963 2964 /* Skip tag type and tag id or residue param*/ 2965 index += 2; 2966 } else { 2967 /* Single byte message */ 2968 if (type == AHCMSG_1B 2969 && ahc->msgout_buf[index] == msgval 2970 && ahc->msgout_index > index) 2971 found = TRUE; 2972 index++; 2973 } 2974 2975 if (found) 2976 break; 2977 } 2978 return (found); 2979 } 2980 2981 /* 2982 * Wait for a complete incoming message, parse it, and respond accordingly. 2983 */ 2984 static int 2985 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2986 { 2987 struct ahc_initiator_tinfo *tinfo; 2988 struct ahc_tmode_tstate *tstate; 2989 int reject; 2990 int done; 2991 int response; 2992 u_int targ_scsirate; 2993 2994 done = MSGLOOP_IN_PROG; 2995 response = FALSE; 2996 reject = FALSE; 2997 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2998 devinfo->target, &tstate); 2999 targ_scsirate = tinfo->scsirate; 3000 3001 /* 3002 * Parse as much of the message as is available, 3003 * rejecting it if we don't support it. When 3004 * the entire message is available and has been 3005 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3006 * that we have parsed an entire message. 3007 * 3008 * In the case of extended messages, we accept the length 3009 * byte outright and perform more checking once we know the 3010 * extended message type. 3011 */ 3012 switch (ahc->msgin_buf[0]) { 3013 case MSG_DISCONNECT: 3014 case MSG_SAVEDATAPOINTER: 3015 case MSG_CMDCOMPLETE: 3016 case MSG_RESTOREPOINTERS: 3017 case MSG_IGN_WIDE_RESIDUE: 3018 /* 3019 * End our message loop as these are messages 3020 * the sequencer handles on its own. 3021 */ 3022 done = MSGLOOP_TERMINATED; 3023 break; 3024 case MSG_MESSAGE_REJECT: 3025 response = ahc_handle_msg_reject(ahc, devinfo); 3026 /* FALLTHROUGH */ 3027 case MSG_NOOP: 3028 done = MSGLOOP_MSGCOMPLETE; 3029 break; 3030 case MSG_EXTENDED: 3031 { 3032 /* Wait for enough of the message to begin validation */ 3033 if (ahc->msgin_index < 2) 3034 break; 3035 switch (ahc->msgin_buf[2]) { 3036 case MSG_EXT_SDTR: 3037 { 3038 struct ahc_syncrate *syncrate; 3039 u_int period; 3040 u_int ppr_options; 3041 u_int offset; 3042 u_int saved_offset; 3043 3044 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3045 reject = TRUE; 3046 break; 3047 } 3048 3049 /* 3050 * Wait until we have both args before validating 3051 * and acting on this message. 3052 * 3053 * Add one to MSG_EXT_SDTR_LEN to account for 3054 * the extended message preamble. 3055 */ 3056 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3057 break; 3058 3059 period = ahc->msgin_buf[3]; 3060 ppr_options = 0; 3061 saved_offset = offset = ahc->msgin_buf[4]; 3062 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3063 &ppr_options, 3064 devinfo->role); 3065 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3066 targ_scsirate & WIDEXFER, 3067 devinfo->role); 3068 if (bootverbose) { 3069 printf("(%s:%c:%d:%d): Received " 3070 "SDTR period %x, offset %x\n\t" 3071 "Filtered to period %x, offset %x\n", 3072 ahc_name(ahc), devinfo->channel, 3073 devinfo->target, devinfo->lun, 3074 ahc->msgin_buf[3], saved_offset, 3075 period, offset); 3076 } 3077 ahc_set_syncrate(ahc, devinfo, 3078 syncrate, period, 3079 offset, ppr_options, 3080 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3081 /*paused*/TRUE); 3082 3083 /* 3084 * See if we initiated Sync Negotiation 3085 * and didn't have to fall down to async 3086 * transfers. 3087 */ 3088 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3089 /* We started it */ 3090 if (saved_offset != offset) { 3091 /* Went too low - force async */ 3092 reject = TRUE; 3093 } 3094 } else { 3095 /* 3096 * Send our own SDTR in reply 3097 */ 3098 if (bootverbose 3099 && devinfo->role == ROLE_INITIATOR) { 3100 printf("(%s:%c:%d:%d): Target " 3101 "Initiated SDTR\n", 3102 ahc_name(ahc), devinfo->channel, 3103 devinfo->target, devinfo->lun); 3104 } 3105 ahc->msgout_index = 0; 3106 ahc->msgout_len = 0; 3107 ahc_construct_sdtr(ahc, devinfo, 3108 period, offset); 3109 ahc->msgout_index = 0; 3110 response = TRUE; 3111 } 3112 done = MSGLOOP_MSGCOMPLETE; 3113 break; 3114 } 3115 case MSG_EXT_WDTR: 3116 { 3117 u_int bus_width; 3118 u_int saved_width; 3119 u_int sending_reply; 3120 3121 sending_reply = FALSE; 3122 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3123 reject = TRUE; 3124 break; 3125 } 3126 3127 /* 3128 * Wait until we have our arg before validating 3129 * and acting on this message. 3130 * 3131 * Add one to MSG_EXT_WDTR_LEN to account for 3132 * the extended message preamble. 3133 */ 3134 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3135 break; 3136 3137 bus_width = ahc->msgin_buf[3]; 3138 saved_width = bus_width; 3139 ahc_validate_width(ahc, tinfo, &bus_width, 3140 devinfo->role); 3141 if (bootverbose) { 3142 printf("(%s:%c:%d:%d): Received WDTR " 3143 "%x filtered to %x\n", 3144 ahc_name(ahc), devinfo->channel, 3145 devinfo->target, devinfo->lun, 3146 saved_width, bus_width); 3147 } 3148 3149 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3150 /* 3151 * Don't send a WDTR back to the 3152 * target, since we asked first. 3153 * If the width went higher than our 3154 * request, reject it. 3155 */ 3156 if (saved_width > bus_width) { 3157 reject = TRUE; 3158 printf("(%s:%c:%d:%d): requested %dBit " 3159 "transfers. Rejecting...\n", 3160 ahc_name(ahc), devinfo->channel, 3161 devinfo->target, devinfo->lun, 3162 8 * (0x01 << bus_width)); 3163 bus_width = 0; 3164 } 3165 } else { 3166 /* 3167 * Send our own WDTR in reply 3168 */ 3169 if (bootverbose 3170 && devinfo->role == ROLE_INITIATOR) { 3171 printf("(%s:%c:%d:%d): Target " 3172 "Initiated WDTR\n", 3173 ahc_name(ahc), devinfo->channel, 3174 devinfo->target, devinfo->lun); 3175 } 3176 ahc->msgout_index = 0; 3177 ahc->msgout_len = 0; 3178 ahc_construct_wdtr(ahc, devinfo, bus_width); 3179 ahc->msgout_index = 0; 3180 response = TRUE; 3181 sending_reply = TRUE; 3182 } 3183 /* 3184 * After a wide message, we are async, but 3185 * some devices don't seem to honor this portion 3186 * of the spec. Force a renegotiation of the 3187 * sync component of our transfer agreement even 3188 * if our goal is async. By updating our width 3189 * after forcing the negotiation, we avoid 3190 * renegotiating for width. 3191 */ 3192 ahc_update_neg_request(ahc, devinfo, tstate, 3193 tinfo, AHC_NEG_ALWAYS); 3194 ahc_set_width(ahc, devinfo, bus_width, 3195 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3196 /*paused*/TRUE); 3197 if (sending_reply == FALSE && reject == FALSE) { 3198 3199 /* 3200 * We will always have an SDTR to send. 3201 */ 3202 ahc->msgout_index = 0; 3203 ahc->msgout_len = 0; 3204 ahc_build_transfer_msg(ahc, devinfo); 3205 ahc->msgout_index = 0; 3206 response = TRUE; 3207 } 3208 done = MSGLOOP_MSGCOMPLETE; 3209 break; 3210 } 3211 case MSG_EXT_PPR: 3212 { 3213 struct ahc_syncrate *syncrate; 3214 u_int period; 3215 u_int offset; 3216 u_int bus_width; 3217 u_int ppr_options; 3218 u_int saved_width; 3219 u_int saved_offset; 3220 u_int saved_ppr_options; 3221 3222 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3223 reject = TRUE; 3224 break; 3225 } 3226 3227 /* 3228 * Wait until we have all args before validating 3229 * and acting on this message. 3230 * 3231 * Add one to MSG_EXT_PPR_LEN to account for 3232 * the extended message preamble. 3233 */ 3234 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3235 break; 3236 3237 period = ahc->msgin_buf[3]; 3238 offset = ahc->msgin_buf[5]; 3239 bus_width = ahc->msgin_buf[6]; 3240 saved_width = bus_width; 3241 ppr_options = ahc->msgin_buf[7]; 3242 /* 3243 * According to the spec, a DT only 3244 * period factor with no DT option 3245 * set implies async. 3246 */ 3247 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3248 && period == 9) 3249 offset = 0; 3250 saved_ppr_options = ppr_options; 3251 saved_offset = offset; 3252 3253 /* 3254 * Mask out any options we don't support 3255 * on any controller. Transfer options are 3256 * only available if we are negotiating wide. 3257 */ 3258 ppr_options &= MSG_EXT_PPR_DT_REQ; 3259 if (bus_width == 0) 3260 ppr_options = 0; 3261 3262 ahc_validate_width(ahc, tinfo, &bus_width, 3263 devinfo->role); 3264 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3265 &ppr_options, 3266 devinfo->role); 3267 ahc_validate_offset(ahc, tinfo, syncrate, 3268 &offset, bus_width, 3269 devinfo->role); 3270 3271 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3272 /* 3273 * If we are unable to do any of the 3274 * requested options (we went too low), 3275 * then we'll have to reject the message. 3276 */ 3277 if (saved_width > bus_width 3278 || saved_offset != offset 3279 || saved_ppr_options != ppr_options) { 3280 reject = TRUE; 3281 period = 0; 3282 offset = 0; 3283 bus_width = 0; 3284 ppr_options = 0; 3285 syncrate = NULL; 3286 } 3287 } else { 3288 if (devinfo->role != ROLE_TARGET) 3289 printf("(%s:%c:%d:%d): Target " 3290 "Initiated PPR\n", 3291 ahc_name(ahc), devinfo->channel, 3292 devinfo->target, devinfo->lun); 3293 else 3294 printf("(%s:%c:%d:%d): Initiator " 3295 "Initiated PPR\n", 3296 ahc_name(ahc), devinfo->channel, 3297 devinfo->target, devinfo->lun); 3298 ahc->msgout_index = 0; 3299 ahc->msgout_len = 0; 3300 ahc_construct_ppr(ahc, devinfo, period, offset, 3301 bus_width, ppr_options); 3302 ahc->msgout_index = 0; 3303 response = TRUE; 3304 } 3305 if (bootverbose) { 3306 printf("(%s:%c:%d:%d): Received PPR width %x, " 3307 "period %x, offset %x,options %x\n" 3308 "\tFiltered to width %x, period %x, " 3309 "offset %x, options %x\n", 3310 ahc_name(ahc), devinfo->channel, 3311 devinfo->target, devinfo->lun, 3312 saved_width, ahc->msgin_buf[3], 3313 saved_offset, saved_ppr_options, 3314 bus_width, period, offset, ppr_options); 3315 } 3316 ahc_set_width(ahc, devinfo, bus_width, 3317 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3318 /*paused*/TRUE); 3319 ahc_set_syncrate(ahc, devinfo, 3320 syncrate, period, 3321 offset, ppr_options, 3322 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3323 /*paused*/TRUE); 3324 done = MSGLOOP_MSGCOMPLETE; 3325 break; 3326 } 3327 default: 3328 /* Unknown extended message. Reject it. */ 3329 reject = TRUE; 3330 break; 3331 } 3332 break; 3333 } 3334 #ifdef AHC_TARGET_MODE 3335 case MSG_BUS_DEV_RESET: 3336 ahc_handle_devreset(ahc, devinfo, 3337 CAM_BDR_SENT, 3338 "Bus Device Reset Received", 3339 /*verbose_level*/0); 3340 ahc_restart(ahc); 3341 done = MSGLOOP_TERMINATED; 3342 break; 3343 case MSG_ABORT_TAG: 3344 case MSG_ABORT: 3345 case MSG_CLEAR_QUEUE: 3346 { 3347 int tag; 3348 3349 /* Target mode messages */ 3350 if (devinfo->role != ROLE_TARGET) { 3351 reject = TRUE; 3352 break; 3353 } 3354 tag = SCB_LIST_NULL; 3355 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3356 tag = ahc_inb(ahc, INITIATOR_TAG); 3357 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3358 devinfo->lun, tag, ROLE_TARGET, 3359 CAM_REQ_ABORTED); 3360 3361 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3362 if (tstate != NULL) { 3363 struct ahc_tmode_lstate* lstate; 3364 3365 lstate = tstate->enabled_luns[devinfo->lun]; 3366 if (lstate != NULL) { 3367 ahc_queue_lstate_event(ahc, lstate, 3368 devinfo->our_scsiid, 3369 ahc->msgin_buf[0], 3370 /*arg*/tag); 3371 ahc_send_lstate_events(ahc, lstate); 3372 } 3373 } 3374 ahc_restart(ahc); 3375 done = MSGLOOP_TERMINATED; 3376 break; 3377 } 3378 #endif 3379 case MSG_TERM_IO_PROC: 3380 default: 3381 reject = TRUE; 3382 break; 3383 } 3384 3385 if (reject) { 3386 /* 3387 * Setup to reject the message. 3388 */ 3389 ahc->msgout_index = 0; 3390 ahc->msgout_len = 1; 3391 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3392 done = MSGLOOP_MSGCOMPLETE; 3393 response = TRUE; 3394 } 3395 3396 if (done != MSGLOOP_IN_PROG && !response) 3397 /* Clear the outgoing message buffer */ 3398 ahc->msgout_len = 0; 3399 3400 return (done); 3401 } 3402 3403 /* 3404 * Process a message reject message. 3405 */ 3406 static int 3407 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3408 { 3409 /* 3410 * What we care about here is if we had an 3411 * outstanding SDTR or WDTR message for this 3412 * target. If we did, this is a signal that 3413 * the target is refusing negotiation. 3414 */ 3415 struct scb *scb; 3416 struct ahc_initiator_tinfo *tinfo; 3417 struct ahc_tmode_tstate *tstate; 3418 u_int scb_index; 3419 u_int last_msg; 3420 int response = 0; 3421 3422 scb_index = ahc_inb(ahc, SCB_TAG); 3423 scb = ahc_lookup_scb(ahc, scb_index); 3424 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3425 devinfo->our_scsiid, 3426 devinfo->target, &tstate); 3427 /* Might be necessary */ 3428 last_msg = ahc_inb(ahc, LAST_MSG); 3429 3430 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3431 /* 3432 * Target does not support the PPR message. 3433 * Attempt to negotiate SPI-2 style. 3434 */ 3435 if (bootverbose) { 3436 printf("(%s:%c:%d:%d): PPR Rejected. " 3437 "Trying WDTR/SDTR\n", 3438 ahc_name(ahc), devinfo->channel, 3439 devinfo->target, devinfo->lun); 3440 } 3441 tinfo->goal.ppr_options = 0; 3442 tinfo->curr.transport_version = 2; 3443 tinfo->goal.transport_version = 2; 3444 ahc->msgout_index = 0; 3445 ahc->msgout_len = 0; 3446 ahc_build_transfer_msg(ahc, devinfo); 3447 ahc->msgout_index = 0; 3448 response = 1; 3449 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3450 3451 /* note 8bit xfers */ 3452 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3453 "8bit transfers\n", ahc_name(ahc), 3454 devinfo->channel, devinfo->target, devinfo->lun); 3455 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3456 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3457 /*paused*/TRUE); 3458 /* 3459 * No need to clear the sync rate. If the target 3460 * did not accept the command, our syncrate is 3461 * unaffected. If the target started the negotiation, 3462 * but rejected our response, we already cleared the 3463 * sync rate before sending our WDTR. 3464 */ 3465 if (tinfo->goal.offset != tinfo->curr.offset) { 3466 3467 /* Start the sync negotiation */ 3468 ahc->msgout_index = 0; 3469 ahc->msgout_len = 0; 3470 ahc_build_transfer_msg(ahc, devinfo); 3471 ahc->msgout_index = 0; 3472 response = 1; 3473 } 3474 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3475 /* note asynch xfers and clear flag */ 3476 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3477 /*offset*/0, /*ppr_options*/0, 3478 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3479 /*paused*/TRUE); 3480 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 3481 "Using asynchronous transfers\n", 3482 ahc_name(ahc), devinfo->channel, 3483 devinfo->target, devinfo->lun); 3484 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3485 int tag_type; 3486 int mask; 3487 3488 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3489 3490 if (tag_type == MSG_SIMPLE_TASK) { 3491 printf("(%s:%c:%d:%d): refuses tagged commands. " 3492 "Performing non-tagged I/O\n", ahc_name(ahc), 3493 devinfo->channel, devinfo->target, devinfo->lun); 3494 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE); 3495 mask = ~0x23; 3496 } else { 3497 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 3498 "Performing simple queue tagged I/O only\n", 3499 ahc_name(ahc), devinfo->channel, devinfo->target, 3500 devinfo->lun, tag_type == MSG_ORDERED_TASK 3501 ? "ordered" : "head of queue"); 3502 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC); 3503 mask = ~0x03; 3504 } 3505 3506 /* 3507 * Resend the identify for this CCB as the target 3508 * may believe that the selection is invalid otherwise. 3509 */ 3510 ahc_outb(ahc, SCB_CONTROL, 3511 ahc_inb(ahc, SCB_CONTROL) & mask); 3512 scb->hscb->control &= mask; 3513 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3514 /*type*/MSG_SIMPLE_TASK); 3515 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3516 ahc_assert_atn(ahc); 3517 3518 /* 3519 * This transaction is now at the head of 3520 * the untagged queue for this target. 3521 */ 3522 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3523 struct scb_tailq *untagged_q; 3524 3525 untagged_q = 3526 &(ahc->untagged_queues[devinfo->target_offset]); 3527 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3528 scb->flags |= SCB_UNTAGGEDQ; 3529 } 3530 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3531 scb->hscb->tag); 3532 3533 /* 3534 * Requeue all tagged commands for this target 3535 * currently in our posession so they can be 3536 * converted to untagged commands. 3537 */ 3538 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3539 SCB_GET_CHANNEL(ahc, scb), 3540 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3541 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3542 SEARCH_COMPLETE); 3543 } else { 3544 /* 3545 * Otherwise, we ignore it. 3546 */ 3547 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3548 ahc_name(ahc), devinfo->channel, devinfo->target, 3549 last_msg); 3550 } 3551 return (response); 3552 } 3553 3554 /* 3555 * Process an ingnore wide residue message. 3556 */ 3557 static void 3558 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3559 { 3560 u_int scb_index; 3561 struct scb *scb; 3562 3563 scb_index = ahc_inb(ahc, SCB_TAG); 3564 scb = ahc_lookup_scb(ahc, scb_index); 3565 /* 3566 * XXX Actually check data direction in the sequencer? 3567 * Perhaps add datadir to some spare bits in the hscb? 3568 */ 3569 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3570 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3571 /* 3572 * Ignore the message if we haven't 3573 * seen an appropriate data phase yet. 3574 */ 3575 } else { 3576 /* 3577 * If the residual occurred on the last 3578 * transfer and the transfer request was 3579 * expected to end on an odd count, do 3580 * nothing. Otherwise, subtract a byte 3581 * and update the residual count accordingly. 3582 */ 3583 uint32_t sgptr; 3584 3585 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3586 if ((sgptr & SG_LIST_NULL) != 0 3587 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) { 3588 /* 3589 * If the residual occurred on the last 3590 * transfer and the transfer request was 3591 * expected to end on an odd count, do 3592 * nothing. 3593 */ 3594 } else { 3595 struct ahc_dma_seg *sg; 3596 uint32_t data_cnt; 3597 uint32_t data_addr; 3598 uint32_t sglen; 3599 3600 /* Pull in all of the sgptr */ 3601 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR); 3602 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT); 3603 3604 if ((sgptr & SG_LIST_NULL) != 0) { 3605 /* 3606 * The residual data count is not updated 3607 * for the command run to completion case. 3608 * Explicitly zero the count. 3609 */ 3610 data_cnt &= ~AHC_SG_LEN_MASK; 3611 } 3612 3613 data_addr = ahc_inl(ahc, SHADDR); 3614 3615 data_cnt += 1; 3616 data_addr -= 1; 3617 sgptr &= SG_PTR_MASK; 3618 3619 sg = ahc_sg_bus_to_virt(scb, sgptr); 3620 3621 /* 3622 * The residual sg ptr points to the next S/G 3623 * to load so we must go back one. 3624 */ 3625 sg--; 3626 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 3627 if (sg != scb->sg_list 3628 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3629 3630 sg--; 3631 sglen = ahc_le32toh(sg->len); 3632 /* 3633 * Preserve High Address and SG_LIST bits 3634 * while setting the count to 1. 3635 */ 3636 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3637 data_addr = ahc_le32toh(sg->addr) 3638 + (sglen & AHC_SG_LEN_MASK) - 1; 3639 3640 /* 3641 * Increment sg so it points to the 3642 * "next" sg. 3643 */ 3644 sg++; 3645 sgptr = ahc_sg_virt_to_bus(scb, sg); 3646 } 3647 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3648 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3649 /* 3650 * Toggle the "oddness" of the transfer length 3651 * to handle this mid-transfer ignore wide 3652 * residue. This ensures that the oddness is 3653 * correct for subsequent data transfers. 3654 */ 3655 ahc_outb(ahc, SCB_LUN, 3656 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD); 3657 } 3658 } 3659 } 3660 3661 3662 /* 3663 * Reinitialize the data pointers for the active transfer 3664 * based on its current residual. 3665 */ 3666 static void 3667 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3668 { 3669 struct scb *scb; 3670 struct ahc_dma_seg *sg; 3671 u_int scb_index; 3672 uint32_t sgptr; 3673 uint32_t resid; 3674 uint32_t dataptr; 3675 3676 scb_index = ahc_inb(ahc, SCB_TAG); 3677 scb = ahc_lookup_scb(ahc, scb_index); 3678 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3679 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3680 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3681 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3682 3683 sgptr &= SG_PTR_MASK; 3684 sg = ahc_sg_bus_to_virt(scb, sgptr); 3685 3686 /* The residual sg_ptr always points to the next sg */ 3687 sg--; 3688 3689 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3690 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3691 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3692 3693 dataptr = ahc_le32toh(sg->addr) 3694 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 3695 - resid; 3696 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3697 u_int dscommand1; 3698 3699 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3700 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3701 ahc_outb(ahc, HADDR, 3702 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3703 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3704 } 3705 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3706 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3707 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3708 ahc_outb(ahc, HADDR, dataptr); 3709 ahc_outb(ahc, HCNT + 2, resid >> 16); 3710 ahc_outb(ahc, HCNT + 1, resid >> 8); 3711 ahc_outb(ahc, HCNT, resid); 3712 if ((ahc->features & AHC_ULTRA2) == 0) { 3713 ahc_outb(ahc, STCNT + 2, resid >> 16); 3714 ahc_outb(ahc, STCNT + 1, resid >> 8); 3715 ahc_outb(ahc, STCNT, resid); 3716 } 3717 } 3718 3719 /* 3720 * Handle the effects of issuing a bus device reset message. 3721 */ 3722 static void 3723 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3724 cam_status status, char *message, int verbose_level) 3725 { 3726 #ifdef AHC_TARGET_MODE 3727 struct ahc_tmode_tstate* tstate; 3728 u_int lun; 3729 #endif 3730 int found; 3731 3732 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3733 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3734 status); 3735 3736 #ifdef AHC_TARGET_MODE 3737 /* 3738 * Send an immediate notify ccb to all target mord peripheral 3739 * drivers affected by this action. 3740 */ 3741 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3742 if (tstate != NULL) { 3743 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3744 struct ahc_tmode_lstate* lstate; 3745 3746 lstate = tstate->enabled_luns[lun]; 3747 if (lstate == NULL) 3748 continue; 3749 3750 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3751 MSG_BUS_DEV_RESET, /*arg*/0); 3752 ahc_send_lstate_events(ahc, lstate); 3753 } 3754 } 3755 #endif 3756 3757 /* 3758 * Go back to async/narrow transfers and renegotiate. 3759 */ 3760 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3761 AHC_TRANS_CUR, /*paused*/TRUE); 3762 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3763 /*period*/0, /*offset*/0, /*ppr_options*/0, 3764 AHC_TRANS_CUR, /*paused*/TRUE); 3765 3766 if (status != CAM_SEL_TIMEOUT) 3767 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3768 CAM_LUN_WILDCARD, AC_SENT_BDR); 3769 3770 if (message != NULL 3771 && (verbose_level <= bootverbose)) 3772 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3773 message, devinfo->channel, devinfo->target, found); 3774 } 3775 3776 #ifdef AHC_TARGET_MODE 3777 static void 3778 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3779 struct scb *scb) 3780 { 3781 3782 /* 3783 * To facilitate adding multiple messages together, 3784 * each routine should increment the index and len 3785 * variables instead of setting them explicitly. 3786 */ 3787 ahc->msgout_index = 0; 3788 ahc->msgout_len = 0; 3789 3790 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3791 ahc_build_transfer_msg(ahc, devinfo); 3792 else 3793 panic("ahc_intr: AWAITING target message with no message"); 3794 3795 ahc->msgout_index = 0; 3796 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3797 } 3798 #endif 3799 /**************************** Initialization **********************************/ 3800 /* 3801 * Allocate a controller structure for a new device 3802 * and perform initial initializion. 3803 */ 3804 struct ahc_softc * 3805 ahc_alloc(void *platform_arg, char *name) 3806 { 3807 struct ahc_softc *ahc; 3808 int i; 3809 3810 #ifndef __FreeBSD__ 3811 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); 3812 if (!ahc) { 3813 printf("aic7xxx: cannot malloc softc!\n"); 3814 free(name, M_DEVBUF); 3815 return NULL; 3816 } 3817 #else 3818 ahc = device_get_softc((device_t)platform_arg); 3819 #endif 3820 memset(ahc, 0, sizeof(*ahc)); 3821 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 3822 M_DEVBUF, M_NOWAIT); 3823 if (ahc->seep_config == NULL) { 3824 #ifndef __FreeBSD__ 3825 free(ahc, M_DEVBUF); 3826 #endif 3827 free(name, M_DEVBUF); 3828 return (NULL); 3829 } 3830 LIST_INIT(&ahc->pending_scbs); 3831 /* We don't know our unit number until the OSM sets it */ 3832 ahc->name = name; 3833 ahc->unit = -1; 3834 ahc->description = NULL; 3835 ahc->channel = 'A'; 3836 ahc->channel_b = 'B'; 3837 ahc->chip = AHC_NONE; 3838 ahc->features = AHC_FENONE; 3839 ahc->bugs = AHC_BUGNONE; 3840 ahc->flags = AHC_FNONE; 3841 /* 3842 * Default to all error reporting enabled with the 3843 * sequencer operating at its fastest speed. 3844 * The bus attach code may modify this. 3845 */ 3846 ahc->seqctl = FASTMODE; 3847 3848 for (i = 0; i < AHC_NUM_TARGETS; i++) 3849 TAILQ_INIT(&ahc->untagged_queues[i]); 3850 if (ahc_platform_alloc(ahc, platform_arg) != 0) { 3851 ahc_free(ahc); 3852 ahc = NULL; 3853 } 3854 return (ahc); 3855 } 3856 3857 int 3858 ahc_softc_init(struct ahc_softc *ahc) 3859 { 3860 3861 /* The IRQMS bit is only valid on VL and EISA chips */ 3862 if ((ahc->chip & AHC_PCI) == 0) 3863 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3864 else 3865 ahc->unpause = 0; 3866 ahc->pause = ahc->unpause | PAUSE; 3867 /* XXX The shared scb data stuff should be deprecated */ 3868 if (ahc->scb_data == NULL) { 3869 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3870 M_DEVBUF, M_NOWAIT); 3871 if (ahc->scb_data == NULL) 3872 return (ENOMEM); 3873 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3874 } 3875 3876 return (0); 3877 } 3878 3879 void 3880 ahc_set_unit(struct ahc_softc *ahc, int unit) 3881 { 3882 ahc->unit = unit; 3883 } 3884 3885 void 3886 ahc_set_name(struct ahc_softc *ahc, char *name) 3887 { 3888 if (ahc->name != NULL) 3889 free(ahc->name, M_DEVBUF); 3890 ahc->name = name; 3891 } 3892 3893 void 3894 ahc_free(struct ahc_softc *ahc) 3895 { 3896 int i; 3897 3898 switch (ahc->init_level) { 3899 default: 3900 case 5: 3901 ahc_shutdown(ahc); 3902 /* FALLTHROUGH */ 3903 case 4: 3904 ahc_dmamap_unload(ahc, ahc->shared_data_dmat, 3905 ahc->shared_data_dmamap); 3906 /* FALLTHROUGH */ 3907 case 3: 3908 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, 3909 ahc->shared_data_dmamap); 3910 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat, 3911 ahc->shared_data_dmamap); 3912 /* FALLTHROUGH */ 3913 case 2: 3914 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat); 3915 case 1: 3916 #ifndef __linux__ 3917 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat); 3918 #endif 3919 break; 3920 case 0: 3921 break; 3922 } 3923 3924 #ifndef __linux__ 3925 ahc_dma_tag_destroy(ahc, ahc->parent_dmat); 3926 #endif 3927 ahc_platform_free(ahc); 3928 ahc_fini_scbdata(ahc); 3929 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3930 struct ahc_tmode_tstate *tstate; 3931 3932 tstate = ahc->enabled_targets[i]; 3933 if (tstate != NULL) { 3934 #ifdef AHC_TARGET_MODE 3935 int j; 3936 3937 for (j = 0; j < AHC_NUM_LUNS; j++) { 3938 struct ahc_tmode_lstate *lstate; 3939 3940 lstate = tstate->enabled_luns[j]; 3941 if (lstate != NULL) { 3942 xpt_free_path(lstate->path); 3943 free(lstate, M_DEVBUF); 3944 } 3945 } 3946 #endif 3947 free(tstate, M_DEVBUF); 3948 } 3949 } 3950 #ifdef AHC_TARGET_MODE 3951 if (ahc->black_hole != NULL) { 3952 xpt_free_path(ahc->black_hole->path); 3953 free(ahc->black_hole, M_DEVBUF); 3954 } 3955 #endif 3956 if (ahc->name != NULL) 3957 free(ahc->name, M_DEVBUF); 3958 if (ahc->seep_config != NULL) 3959 free(ahc->seep_config, M_DEVBUF); 3960 #ifndef __FreeBSD__ 3961 free(ahc, M_DEVBUF); 3962 #endif 3963 return; 3964 } 3965 3966 void 3967 ahc_shutdown(void *arg) 3968 { 3969 struct ahc_softc *ahc; 3970 int i; 3971 3972 ahc = (struct ahc_softc *)arg; 3973 3974 /* This will reset most registers to 0, but not all */ 3975 ahc_reset(ahc, /*reinit*/FALSE); 3976 ahc_outb(ahc, SCSISEQ, 0); 3977 ahc_outb(ahc, SXFRCTL0, 0); 3978 ahc_outb(ahc, DSPCISTATUS, 0); 3979 3980 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 3981 ahc_outb(ahc, i, 0); 3982 } 3983 3984 /* 3985 * Reset the controller and record some information about it 3986 * that is only available just after a reset. If "reinit" is 3987 * non-zero, this reset occured after initial configuration 3988 * and the caller requests that the chip be fully reinitialized 3989 * to a runable state. Chip interrupts are *not* enabled after 3990 * a reinitialization. The caller must enable interrupts via 3991 * ahc_intr_enable(). 3992 */ 3993 int 3994 ahc_reset(struct ahc_softc *ahc, int reinit) 3995 { 3996 u_int sblkctl; 3997 u_int sxfrctl1_a, sxfrctl1_b; 3998 int error; 3999 int wait; 4000 4001 /* 4002 * Preserve the value of the SXFRCTL1 register for all channels. 4003 * It contains settings that affect termination and we don't want 4004 * to disturb the integrity of the bus. 4005 */ 4006 ahc_pause(ahc); 4007 sxfrctl1_b = 0; 4008 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4009 u_int sblkctl; 4010 4011 /* 4012 * Save channel B's settings in case this chip 4013 * is setup for TWIN channel operation. 4014 */ 4015 sblkctl = ahc_inb(ahc, SBLKCTL); 4016 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4017 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4018 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4019 } 4020 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4021 4022 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4023 4024 /* 4025 * Ensure that the reset has finished. We delay 1000us 4026 * prior to reading the register to make sure the chip 4027 * has sufficiently completed its reset to handle register 4028 * accesses. 4029 */ 4030 wait = 1000; 4031 do { 4032 ahc_delay(1000); 4033 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4034 4035 if (wait == 0) { 4036 printf("%s: WARNING - Failed chip reset! " 4037 "Trying to initialize anyway.\n", ahc_name(ahc)); 4038 } 4039 ahc_outb(ahc, HCNTRL, ahc->pause); 4040 4041 /* Determine channel configuration */ 4042 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4043 /* No Twin Channel PCI cards */ 4044 if ((ahc->chip & AHC_PCI) != 0) 4045 sblkctl &= ~SELBUSB; 4046 switch (sblkctl) { 4047 case 0: 4048 /* Single Narrow Channel */ 4049 break; 4050 case 2: 4051 /* Wide Channel */ 4052 ahc->features |= AHC_WIDE; 4053 break; 4054 case 8: 4055 /* Twin Channel */ 4056 ahc->features |= AHC_TWIN; 4057 break; 4058 default: 4059 printf(" Unsupported adapter type. Ignoring\n"); 4060 return(-1); 4061 } 4062 4063 /* 4064 * Reload sxfrctl1. 4065 * 4066 * We must always initialize STPWEN to 1 before we 4067 * restore the saved values. STPWEN is initialized 4068 * to a tri-state condition which can only be cleared 4069 * by turning it on. 4070 */ 4071 if ((ahc->features & AHC_TWIN) != 0) { 4072 u_int sblkctl; 4073 4074 sblkctl = ahc_inb(ahc, SBLKCTL); 4075 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4076 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4077 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4078 } 4079 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4080 4081 error = 0; 4082 if (reinit != 0) 4083 /* 4084 * If a recovery action has forced a chip reset, 4085 * re-initialize the chip to our liking. 4086 */ 4087 error = ahc->bus_chip_init(ahc); 4088 #ifdef AHC_DUMP_SEQ 4089 else 4090 ahc_dumpseq(ahc); 4091 #endif 4092 4093 return (error); 4094 } 4095 4096 /* 4097 * Determine the number of SCBs available on the controller 4098 */ 4099 int 4100 ahc_probe_scbs(struct ahc_softc *ahc) { 4101 int i; 4102 4103 for (i = 0; i < AHC_SCB_MAX; i++) { 4104 4105 ahc_outb(ahc, SCBPTR, i); 4106 ahc_outb(ahc, SCB_BASE, i); 4107 if (ahc_inb(ahc, SCB_BASE) != i) 4108 break; 4109 ahc_outb(ahc, SCBPTR, 0); 4110 if (ahc_inb(ahc, SCB_BASE) != 0) 4111 break; 4112 } 4113 return (i); 4114 } 4115 4116 static void 4117 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4118 { 4119 dma_addr_t *baddr; 4120 4121 baddr = (dma_addr_t *)arg; 4122 *baddr = segs->ds_addr; 4123 } 4124 4125 static void 4126 ahc_build_free_scb_list(struct ahc_softc *ahc) 4127 { 4128 int scbsize; 4129 int i; 4130 4131 scbsize = 32; 4132 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4133 scbsize = 64; 4134 4135 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4136 int j; 4137 4138 ahc_outb(ahc, SCBPTR, i); 4139 4140 /* 4141 * Touch all SCB bytes to avoid parity errors 4142 * should one of our debugging routines read 4143 * an otherwise uninitiatlized byte. 4144 */ 4145 for (j = 0; j < scbsize; j++) 4146 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4147 4148 /* Clear the control byte. */ 4149 ahc_outb(ahc, SCB_CONTROL, 0); 4150 4151 /* Set the next pointer */ 4152 if ((ahc->flags & AHC_PAGESCBS) != 0) 4153 ahc_outb(ahc, SCB_NEXT, i+1); 4154 else 4155 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4156 4157 /* Make the tag number, SCSIID, and lun invalid */ 4158 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4159 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4160 ahc_outb(ahc, SCB_LUN, 0xFF); 4161 } 4162 4163 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4164 /* SCB 0 heads the free list. */ 4165 ahc_outb(ahc, FREE_SCBH, 0); 4166 } else { 4167 /* No free list. */ 4168 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4169 } 4170 4171 /* Make sure that the last SCB terminates the free list */ 4172 ahc_outb(ahc, SCBPTR, i-1); 4173 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4174 } 4175 4176 static int 4177 ahc_init_scbdata(struct ahc_softc *ahc) 4178 { 4179 struct scb_data *scb_data; 4180 4181 scb_data = ahc->scb_data; 4182 SLIST_INIT(&scb_data->free_scbs); 4183 SLIST_INIT(&scb_data->sg_maps); 4184 4185 /* Allocate SCB resources */ 4186 scb_data->scbarray = 4187 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4188 M_DEVBUF, M_NOWAIT); 4189 if (scb_data->scbarray == NULL) 4190 return (ENOMEM); 4191 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4192 4193 /* Determine the number of hardware SCBs and initialize them */ 4194 4195 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4196 if (ahc->scb_data->maxhscbs == 0) { 4197 printf("%s: No SCB space found\n", ahc_name(ahc)); 4198 return (ENXIO); 4199 } 4200 4201 /* 4202 * Create our DMA tags. These tags define the kinds of device 4203 * accessible memory allocations and memory mappings we will 4204 * need to perform during normal operation. 4205 * 4206 * Unless we need to further restrict the allocation, we rely 4207 * on the restrictions of the parent dmat, hence the common 4208 * use of MAXADDR and MAXSIZE. 4209 */ 4210 4211 /* DMA tag for our hardware scb structures */ 4212 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4213 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4214 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4215 /*highaddr*/BUS_SPACE_MAXADDR, 4216 /*filter*/NULL, /*filterarg*/NULL, 4217 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4218 /*nsegments*/1, 4219 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4220 /*flags*/0, &scb_data->hscb_dmat) != 0) { 4221 goto error_exit; 4222 } 4223 4224 scb_data->init_level++; 4225 4226 /* Allocation for our hscbs */ 4227 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat, 4228 (void **)&scb_data->hscbs, 4229 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { 4230 goto error_exit; 4231 } 4232 4233 scb_data->init_level++; 4234 4235 /* And permanently map them */ 4236 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, 4237 scb_data->hscbs, 4238 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4239 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); 4240 4241 scb_data->init_level++; 4242 4243 /* DMA tag for our sense buffers */ 4244 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4245 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4246 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4247 /*highaddr*/BUS_SPACE_MAXADDR, 4248 /*filter*/NULL, /*filterarg*/NULL, 4249 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4250 /*nsegments*/1, 4251 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4252 /*flags*/0, &scb_data->sense_dmat) != 0) { 4253 goto error_exit; 4254 } 4255 4256 scb_data->init_level++; 4257 4258 /* Allocate them */ 4259 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat, 4260 (void **)&scb_data->sense, 4261 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { 4262 goto error_exit; 4263 } 4264 4265 scb_data->init_level++; 4266 4267 /* And permanently map them */ 4268 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, 4269 scb_data->sense, 4270 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4271 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); 4272 4273 scb_data->init_level++; 4274 4275 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 4276 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8, 4277 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4278 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4279 /*highaddr*/BUS_SPACE_MAXADDR, 4280 /*filter*/NULL, /*filterarg*/NULL, 4281 PAGE_SIZE, /*nsegments*/1, 4282 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4283 /*flags*/0, &scb_data->sg_dmat) != 0) { 4284 goto error_exit; 4285 } 4286 4287 scb_data->init_level++; 4288 4289 /* Perform initial CCB allocation */ 4290 memset(scb_data->hscbs, 0, 4291 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4292 ahc_alloc_scbs(ahc); 4293 4294 if (scb_data->numscbs == 0) { 4295 printf("%s: ahc_init_scbdata - " 4296 "Unable to allocate initial scbs\n", 4297 ahc_name(ahc)); 4298 goto error_exit; 4299 } 4300 4301 /* 4302 * Reserve the next queued SCB. 4303 */ 4304 ahc->next_queued_scb = ahc_get_scb(ahc); 4305 4306 /* 4307 * Note that we were successfull 4308 */ 4309 return (0); 4310 4311 error_exit: 4312 4313 return (ENOMEM); 4314 } 4315 4316 static void 4317 ahc_fini_scbdata(struct ahc_softc *ahc) 4318 { 4319 struct scb_data *scb_data; 4320 4321 scb_data = ahc->scb_data; 4322 if (scb_data == NULL) 4323 return; 4324 4325 switch (scb_data->init_level) { 4326 default: 4327 case 7: 4328 { 4329 struct sg_map_node *sg_map; 4330 4331 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4332 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4333 ahc_dmamap_unload(ahc, scb_data->sg_dmat, 4334 sg_map->sg_dmamap); 4335 ahc_dmamem_free(ahc, scb_data->sg_dmat, 4336 sg_map->sg_vaddr, 4337 sg_map->sg_dmamap); 4338 free(sg_map, M_DEVBUF); 4339 } 4340 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat); 4341 } 4342 case 6: 4343 ahc_dmamap_unload(ahc, scb_data->sense_dmat, 4344 scb_data->sense_dmamap); 4345 case 5: 4346 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, 4347 scb_data->sense_dmamap); 4348 ahc_dmamap_destroy(ahc, scb_data->sense_dmat, 4349 scb_data->sense_dmamap); 4350 case 4: 4351 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat); 4352 case 3: 4353 ahc_dmamap_unload(ahc, scb_data->hscb_dmat, 4354 scb_data->hscb_dmamap); 4355 case 2: 4356 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, 4357 scb_data->hscb_dmamap); 4358 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat, 4359 scb_data->hscb_dmamap); 4360 case 1: 4361 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat); 4362 break; 4363 case 0: 4364 break; 4365 } 4366 if (scb_data->scbarray != NULL) 4367 free(scb_data->scbarray, M_DEVBUF); 4368 } 4369 4370 void 4371 ahc_alloc_scbs(struct ahc_softc *ahc) 4372 { 4373 struct scb_data *scb_data; 4374 struct scb *next_scb; 4375 struct sg_map_node *sg_map; 4376 dma_addr_t physaddr; 4377 struct ahc_dma_seg *segs; 4378 int newcount; 4379 int i; 4380 4381 scb_data = ahc->scb_data; 4382 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4383 /* Can't allocate any more */ 4384 return; 4385 4386 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4387 4388 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4389 4390 if (sg_map == NULL) 4391 return; 4392 4393 /* Allocate S/G space for the next batch of SCBS */ 4394 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat, 4395 (void **)&sg_map->sg_vaddr, 4396 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 4397 free(sg_map, M_DEVBUF); 4398 return; 4399 } 4400 4401 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4402 4403 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, 4404 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, 4405 &sg_map->sg_physaddr, /*flags*/0); 4406 4407 segs = sg_map->sg_vaddr; 4408 physaddr = sg_map->sg_physaddr; 4409 4410 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4411 newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4412 for (i = 0; i < newcount; i++) { 4413 struct scb_platform_data *pdata; 4414 #ifndef __linux__ 4415 int error; 4416 #endif 4417 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4418 M_DEVBUF, M_NOWAIT); 4419 if (pdata == NULL) 4420 break; 4421 next_scb->platform_data = pdata; 4422 next_scb->sg_map = sg_map; 4423 next_scb->sg_list = segs; 4424 /* 4425 * The sequencer always starts with the second entry. 4426 * The first entry is embedded in the scb. 4427 */ 4428 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4429 next_scb->ahc_softc = ahc; 4430 next_scb->flags = SCB_FREE; 4431 #ifndef __linux__ 4432 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, 4433 &next_scb->dmamap); 4434 if (error != 0) 4435 break; 4436 #endif 4437 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4438 next_scb->hscb->tag = ahc->scb_data->numscbs; 4439 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4440 next_scb, links.sle); 4441 segs += AHC_NSEG; 4442 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4443 next_scb++; 4444 ahc->scb_data->numscbs++; 4445 } 4446 } 4447 4448 void 4449 ahc_controller_info(struct ahc_softc *ahc, char *buf) 4450 { 4451 int len; 4452 4453 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4454 buf += len; 4455 if ((ahc->features & AHC_TWIN) != 0) 4456 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4457 "B SCSI Id=%d, primary %c, ", 4458 ahc->our_id, ahc->our_id_b, 4459 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4460 else { 4461 const char *speed; 4462 const char *type; 4463 4464 speed = ""; 4465 if ((ahc->features & AHC_ULTRA) != 0) { 4466 speed = "Ultra "; 4467 } else if ((ahc->features & AHC_DT) != 0) { 4468 speed = "Ultra160 "; 4469 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4470 speed = "Ultra2 "; 4471 } 4472 if ((ahc->features & AHC_WIDE) != 0) { 4473 type = "Wide"; 4474 } else { 4475 type = "Single"; 4476 } 4477 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4478 speed, type, ahc->channel, ahc->our_id); 4479 } 4480 buf += len; 4481 4482 if ((ahc->flags & AHC_PAGESCBS) != 0) 4483 sprintf(buf, "%d/%d SCBs", 4484 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4485 else 4486 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4487 } 4488 4489 int 4490 ahc_chip_init(struct ahc_softc *ahc) 4491 { 4492 int term; 4493 int error; 4494 u_int i; 4495 u_int scsi_conf; 4496 u_int scsiseq_template; 4497 uint32_t physaddr; 4498 4499 ahc_outb(ahc, SEQ_FLAGS, 0); 4500 ahc_outb(ahc, SEQ_FLAGS2, 0); 4501 4502 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4503 if (ahc->features & AHC_TWIN) { 4504 4505 /* 4506 * Setup Channel B first. 4507 */ 4508 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4509 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4510 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4511 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4512 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4513 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4514 if ((ahc->features & AHC_ULTRA2) != 0) 4515 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4516 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4517 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4518 4519 /* Select Channel A */ 4520 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4521 } 4522 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4523 if ((ahc->features & AHC_ULTRA2) != 0) 4524 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4525 else 4526 ahc_outb(ahc, SCSIID, ahc->our_id); 4527 scsi_conf = ahc_inb(ahc, SCSICONF); 4528 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4529 |term|ahc->seltime 4530 |ENSTIMER|ACTNEGEN); 4531 if ((ahc->features & AHC_ULTRA2) != 0) 4532 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4533 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4534 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4535 4536 /* There are no untagged SCBs active yet. */ 4537 for (i = 0; i < 16; i++) { 4538 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4539 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4540 int lun; 4541 4542 /* 4543 * The SCB based BTT allows an entry per 4544 * target and lun pair. 4545 */ 4546 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4547 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4548 } 4549 } 4550 4551 /* All of our queues are empty */ 4552 for (i = 0; i < 256; i++) 4553 ahc->qoutfifo[i] = SCB_LIST_NULL; 4554 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4555 4556 for (i = 0; i < 256; i++) 4557 ahc->qinfifo[i] = SCB_LIST_NULL; 4558 4559 if ((ahc->features & AHC_MULTI_TID) != 0) { 4560 ahc_outb(ahc, TARGID, 0); 4561 ahc_outb(ahc, TARGID + 1, 0); 4562 } 4563 4564 /* 4565 * Tell the sequencer where it can find our arrays in memory. 4566 */ 4567 physaddr = ahc->scb_data->hscb_busaddr; 4568 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4569 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4570 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4571 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4572 4573 physaddr = ahc->shared_data_busaddr; 4574 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4575 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4576 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4577 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4578 4579 /* 4580 * Initialize the group code to command length table. 4581 * This overrides the values in TARG_SCSIRATE, so only 4582 * setup the table after we have processed that information. 4583 */ 4584 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4585 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4586 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4587 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4588 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4589 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4590 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4591 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4592 4593 if ((ahc->features & AHC_HS_MAILBOX) != 0) 4594 ahc_outb(ahc, HS_MAILBOX, 0); 4595 4596 /* Tell the sequencer of our initial queue positions */ 4597 if ((ahc->features & AHC_TARGETMODE) != 0) { 4598 ahc->tqinfifonext = 1; 4599 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4600 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4601 } 4602 ahc->qinfifonext = 0; 4603 ahc->qoutfifonext = 0; 4604 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4605 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4606 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4607 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext); 4608 ahc_outb(ahc, SDSCB_QOFF, 0); 4609 } else { 4610 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4611 ahc_outb(ahc, QINPOS, ahc->qinfifonext); 4612 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext); 4613 } 4614 4615 /* We don't have any waiting selections */ 4616 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4617 4618 /* Our disconnection list is empty too */ 4619 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4620 4621 /* Message out buffer starts empty */ 4622 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4623 4624 /* 4625 * Setup the allowed SCSI Sequences based on operational mode. 4626 * If we are a target, we'll enalbe select in operations once 4627 * we've had a lun enabled. 4628 */ 4629 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4630 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4631 scsiseq_template |= ENRSELI; 4632 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4633 4634 /* Initialize our list of free SCBs. */ 4635 ahc_build_free_scb_list(ahc); 4636 4637 /* 4638 * Tell the sequencer which SCB will be the next one it receives. 4639 */ 4640 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4641 4642 /* 4643 * Load the Sequencer program and Enable the adapter 4644 * in "fast" mode. 4645 */ 4646 if (bootverbose) 4647 printf("%s: Downloading Sequencer Program...", 4648 ahc_name(ahc)); 4649 4650 error = ahc_loadseq(ahc); 4651 if (error != 0) 4652 return (error); 4653 4654 if ((ahc->features & AHC_ULTRA2) != 0) { 4655 int wait; 4656 4657 /* 4658 * Wait for up to 500ms for our transceivers 4659 * to settle. If the adapter does not have 4660 * a cable attached, the transceivers may 4661 * never settle, so don't complain if we 4662 * fail here. 4663 */ 4664 for (wait = 5000; 4665 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4666 wait--) 4667 ahc_delay(100); 4668 } 4669 ahc_restart(ahc); 4670 return (0); 4671 } 4672 4673 /* 4674 * Start the board, ready for normal operation 4675 */ 4676 int 4677 ahc_init(struct ahc_softc *ahc) 4678 { 4679 int max_targ; 4680 u_int i; 4681 u_int scsi_conf; 4682 u_int ultraenb; 4683 u_int discenable; 4684 u_int tagenable; 4685 size_t driver_data_size; 4686 4687 #ifdef AHC_DEBUG 4688 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4689 ahc->flags |= AHC_SEQUENCER_DEBUG; 4690 #endif 4691 4692 #ifdef AHC_PRINT_SRAM 4693 printf("Scratch Ram:"); 4694 for (i = 0x20; i < 0x5f; i++) { 4695 if (((i % 8) == 0) && (i != 0)) { 4696 printf ("\n "); 4697 } 4698 printf (" 0x%x", ahc_inb(ahc, i)); 4699 } 4700 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4701 for (i = 0x70; i < 0x7f; i++) { 4702 if (((i % 8) == 0) && (i != 0)) { 4703 printf ("\n "); 4704 } 4705 printf (" 0x%x", ahc_inb(ahc, i)); 4706 } 4707 } 4708 printf ("\n"); 4709 /* 4710 * Reading uninitialized scratch ram may 4711 * generate parity errors. 4712 */ 4713 ahc_outb(ahc, CLRINT, CLRPARERR); 4714 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4715 #endif 4716 max_targ = 15; 4717 4718 /* 4719 * Assume we have a board at this stage and it has been reset. 4720 */ 4721 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4722 ahc->our_id = ahc->our_id_b = 7; 4723 4724 /* 4725 * Default to allowing initiator operations. 4726 */ 4727 ahc->flags |= AHC_INITIATORROLE; 4728 4729 /* 4730 * Only allow target mode features if this unit has them enabled. 4731 */ 4732 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4733 ahc->features &= ~AHC_TARGETMODE; 4734 4735 #ifndef __linux__ 4736 /* DMA tag for mapping buffers into device visible space. */ 4737 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4738 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4739 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING 4740 ? (dma_addr_t)0x7FFFFFFFFFULL 4741 : BUS_SPACE_MAXADDR_32BIT, 4742 /*highaddr*/BUS_SPACE_MAXADDR, 4743 /*filter*/NULL, /*filterarg*/NULL, 4744 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE, 4745 /*nsegments*/AHC_NSEG, 4746 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 4747 /*flags*/BUS_DMA_ALLOCNOW, 4748 &ahc->buffer_dmat) != 0) { 4749 return (ENOMEM); 4750 } 4751 #endif 4752 4753 ahc->init_level++; 4754 4755 /* 4756 * DMA tag for our command fifos and other data in system memory 4757 * the card's sequencer must be able to access. For initiator 4758 * roles, we need to allocate space for the qinfifo and qoutfifo. 4759 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4760 * When providing for the target mode role, we must additionally 4761 * provide space for the incoming target command fifo and an extra 4762 * byte to deal with a dma bug in some chip versions. 4763 */ 4764 driver_data_size = 2 * 256 * sizeof(uint8_t); 4765 if ((ahc->features & AHC_TARGETMODE) != 0) 4766 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4767 + /*DMA WideOdd Bug Buffer*/1; 4768 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4769 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4770 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4771 /*highaddr*/BUS_SPACE_MAXADDR, 4772 /*filter*/NULL, /*filterarg*/NULL, 4773 driver_data_size, 4774 /*nsegments*/1, 4775 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4776 /*flags*/0, &ahc->shared_data_dmat) != 0) { 4777 return (ENOMEM); 4778 } 4779 4780 ahc->init_level++; 4781 4782 /* Allocation of driver data */ 4783 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat, 4784 (void **)&ahc->qoutfifo, 4785 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { 4786 return (ENOMEM); 4787 } 4788 4789 ahc->init_level++; 4790 4791 /* And permanently map it in */ 4792 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 4793 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, 4794 &ahc->shared_data_busaddr, /*flags*/0); 4795 4796 if ((ahc->features & AHC_TARGETMODE) != 0) { 4797 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4798 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4799 ahc->dma_bug_buf = ahc->shared_data_busaddr 4800 + driver_data_size - 1; 4801 /* All target command blocks start out invalid. */ 4802 for (i = 0; i < AHC_TMODE_CMDS; i++) 4803 ahc->targetcmds[i].cmd_valid = 0; 4804 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4805 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4806 } 4807 ahc->qinfifo = &ahc->qoutfifo[256]; 4808 4809 ahc->init_level++; 4810 4811 /* Allocate SCB data now that buffer_dmat is initialized */ 4812 if (ahc->scb_data->maxhscbs == 0) 4813 if (ahc_init_scbdata(ahc) != 0) 4814 return (ENOMEM); 4815 4816 /* 4817 * Allocate a tstate to house information for our 4818 * initiator presence on the bus as well as the user 4819 * data for any target mode initiator. 4820 */ 4821 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4822 printf("%s: unable to allocate ahc_tmode_tstate. " 4823 "Failing attach\n", ahc_name(ahc)); 4824 return (ENOMEM); 4825 } 4826 4827 if ((ahc->features & AHC_TWIN) != 0) { 4828 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4829 printf("%s: unable to allocate ahc_tmode_tstate. " 4830 "Failing attach\n", ahc_name(ahc)); 4831 return (ENOMEM); 4832 } 4833 } 4834 4835 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4836 ahc->flags |= AHC_PAGESCBS; 4837 } else { 4838 ahc->flags &= ~AHC_PAGESCBS; 4839 } 4840 4841 #ifdef AHC_DEBUG 4842 if (ahc_debug & AHC_SHOW_MISC) { 4843 printf("%s: hardware scb %u bytes; kernel scb %u bytes; " 4844 "ahc_dma %u bytes\n", 4845 ahc_name(ahc), 4846 (u_int)sizeof(struct hardware_scb), 4847 (u_int)sizeof(struct scb), 4848 (u_int)sizeof(struct ahc_dma_seg)); 4849 } 4850 #endif /* AHC_DEBUG */ 4851 4852 /* 4853 * Look at the information that board initialization or 4854 * the board bios has left us. 4855 */ 4856 if (ahc->features & AHC_TWIN) { 4857 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4858 if ((scsi_conf & RESET_SCSI) != 0 4859 && (ahc->flags & AHC_INITIATORROLE) != 0) 4860 ahc->flags |= AHC_RESET_BUS_B; 4861 } 4862 4863 scsi_conf = ahc_inb(ahc, SCSICONF); 4864 if ((scsi_conf & RESET_SCSI) != 0 4865 && (ahc->flags & AHC_INITIATORROLE) != 0) 4866 ahc->flags |= AHC_RESET_BUS_A; 4867 4868 ultraenb = 0; 4869 tagenable = ALL_TARGETS_MASK; 4870 4871 /* Grab the disconnection disable table and invert it for our needs */ 4872 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4873 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4874 "device parameters\n", ahc_name(ahc)); 4875 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4876 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4877 discenable = ALL_TARGETS_MASK; 4878 if ((ahc->features & AHC_ULTRA) != 0) 4879 ultraenb = ALL_TARGETS_MASK; 4880 } else { 4881 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4882 | ahc_inb(ahc, DISC_DSB)); 4883 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4884 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4885 | ahc_inb(ahc, ULTRA_ENB); 4886 } 4887 4888 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4889 max_targ = 7; 4890 4891 for (i = 0; i <= max_targ; i++) { 4892 struct ahc_initiator_tinfo *tinfo; 4893 struct ahc_tmode_tstate *tstate; 4894 u_int our_id; 4895 u_int target_id; 4896 char channel; 4897 4898 channel = 'A'; 4899 our_id = ahc->our_id; 4900 target_id = i; 4901 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4902 channel = 'B'; 4903 our_id = ahc->our_id_b; 4904 target_id = i % 8; 4905 } 4906 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4907 target_id, &tstate); 4908 /* Default to async narrow across the board */ 4909 memset(tinfo, 0, sizeof(*tinfo)); 4910 if (ahc->flags & AHC_USEDEFAULTS) { 4911 if ((ahc->features & AHC_WIDE) != 0) 4912 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4913 4914 /* 4915 * These will be truncated when we determine the 4916 * connection type we have with the target. 4917 */ 4918 tinfo->user.period = ahc_syncrates->period; 4919 tinfo->user.offset = MAX_OFFSET; 4920 } else { 4921 u_int scsirate; 4922 uint16_t mask; 4923 4924 /* Take the settings leftover in scratch RAM. */ 4925 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4926 mask = (0x01 << i); 4927 if ((ahc->features & AHC_ULTRA2) != 0) { 4928 u_int offset; 4929 u_int maxsync; 4930 4931 if ((scsirate & SOFS) == 0x0F) { 4932 /* 4933 * Haven't negotiated yet, 4934 * so the format is different. 4935 */ 4936 scsirate = (scsirate & SXFR) >> 4 4937 | (ultraenb & mask) 4938 ? 0x08 : 0x0 4939 | (scsirate & WIDEXFER); 4940 offset = MAX_OFFSET_ULTRA2; 4941 } else 4942 offset = ahc_inb(ahc, TARG_OFFSET + i); 4943 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 4944 /* Set to the lowest sync rate, 5MHz */ 4945 scsirate |= 0x1c; 4946 maxsync = AHC_SYNCRATE_ULTRA2; 4947 if ((ahc->features & AHC_DT) != 0) 4948 maxsync = AHC_SYNCRATE_DT; 4949 tinfo->user.period = 4950 ahc_find_period(ahc, scsirate, maxsync); 4951 if (offset == 0) 4952 tinfo->user.period = 0; 4953 else 4954 tinfo->user.offset = MAX_OFFSET; 4955 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 4956 && (ahc->features & AHC_DT) != 0) 4957 tinfo->user.ppr_options = 4958 MSG_EXT_PPR_DT_REQ; 4959 } else if ((scsirate & SOFS) != 0) { 4960 if ((scsirate & SXFR) == 0x40 4961 && (ultraenb & mask) != 0) { 4962 /* Treat 10MHz as a non-ultra speed */ 4963 scsirate &= ~SXFR; 4964 ultraenb &= ~mask; 4965 } 4966 tinfo->user.period = 4967 ahc_find_period(ahc, scsirate, 4968 (ultraenb & mask) 4969 ? AHC_SYNCRATE_ULTRA 4970 : AHC_SYNCRATE_FAST); 4971 if (tinfo->user.period != 0) 4972 tinfo->user.offset = MAX_OFFSET; 4973 } 4974 if (tinfo->user.period == 0) 4975 tinfo->user.offset = 0; 4976 if ((scsirate & WIDEXFER) != 0 4977 && (ahc->features & AHC_WIDE) != 0) 4978 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4979 tinfo->user.protocol_version = 4; 4980 if ((ahc->features & AHC_DT) != 0) 4981 tinfo->user.transport_version = 3; 4982 else 4983 tinfo->user.transport_version = 2; 4984 tinfo->goal.protocol_version = 2; 4985 tinfo->goal.transport_version = 2; 4986 tinfo->curr.protocol_version = 2; 4987 tinfo->curr.transport_version = 2; 4988 } 4989 tstate->ultraenb = 0; 4990 } 4991 ahc->user_discenable = discenable; 4992 ahc->user_tagenable = tagenable; 4993 4994 return (ahc->bus_chip_init(ahc)); 4995 } 4996 4997 void 4998 ahc_intr_enable(struct ahc_softc *ahc, int enable) 4999 { 5000 u_int hcntrl; 5001 5002 hcntrl = ahc_inb(ahc, HCNTRL); 5003 hcntrl &= ~INTEN; 5004 ahc->pause &= ~INTEN; 5005 ahc->unpause &= ~INTEN; 5006 if (enable) { 5007 hcntrl |= INTEN; 5008 ahc->pause |= INTEN; 5009 ahc->unpause |= INTEN; 5010 } 5011 ahc_outb(ahc, HCNTRL, hcntrl); 5012 } 5013 5014 /* 5015 * Ensure that the card is paused in a location 5016 * outside of all critical sections and that all 5017 * pending work is completed prior to returning. 5018 * This routine should only be called from outside 5019 * an interrupt context. 5020 */ 5021 void 5022 ahc_pause_and_flushwork(struct ahc_softc *ahc) 5023 { 5024 int intstat; 5025 int maxloops; 5026 int paused; 5027 5028 maxloops = 1000; 5029 ahc->flags |= AHC_ALL_INTERRUPTS; 5030 paused = FALSE; 5031 do { 5032 if (paused) { 5033 ahc_unpause(ahc); 5034 /* 5035 * Give the sequencer some time to service 5036 * any active selections. 5037 */ 5038 ahc_delay(500); 5039 } 5040 ahc_intr(ahc); 5041 ahc_pause(ahc); 5042 paused = TRUE; 5043 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 5044 intstat = ahc_inb(ahc, INTSTAT); 5045 if ((intstat & INT_PEND) == 0) { 5046 ahc_clear_critical_section(ahc); 5047 intstat = ahc_inb(ahc, INTSTAT); 5048 } 5049 } while (--maxloops 5050 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0) 5051 && ((intstat & INT_PEND) != 0 5052 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0)); 5053 if (maxloops == 0) { 5054 printf("Infinite interrupt loop, INTSTAT = %x", 5055 ahc_inb(ahc, INTSTAT)); 5056 } 5057 ahc_platform_flushwork(ahc); 5058 ahc->flags &= ~AHC_ALL_INTERRUPTS; 5059 } 5060 5061 int 5062 ahc_suspend(struct ahc_softc *ahc) 5063 { 5064 5065 ahc_pause_and_flushwork(ahc); 5066 5067 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 5068 ahc_unpause(ahc); 5069 return (EBUSY); 5070 } 5071 5072 #ifdef AHC_TARGET_MODE 5073 /* 5074 * XXX What about ATIOs that have not yet been serviced? 5075 * Perhaps we should just refuse to be suspended if we 5076 * are acting in a target role. 5077 */ 5078 if (ahc->pending_device != NULL) { 5079 ahc_unpause(ahc); 5080 return (EBUSY); 5081 } 5082 #endif 5083 ahc_shutdown(ahc); 5084 return (0); 5085 } 5086 5087 int 5088 ahc_resume(struct ahc_softc *ahc) 5089 { 5090 5091 ahc_reset(ahc, /*reinit*/TRUE); 5092 ahc_intr_enable(ahc, TRUE); 5093 ahc_restart(ahc); 5094 return (0); 5095 } 5096 5097 /************************** Busy Target Table *********************************/ 5098 /* 5099 * Return the untagged transaction id for a given target/channel lun. 5100 * Optionally, clear the entry. 5101 */ 5102 u_int 5103 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5104 { 5105 u_int scbid; 5106 u_int target_offset; 5107 5108 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5109 u_int saved_scbptr; 5110 5111 saved_scbptr = ahc_inb(ahc, SCBPTR); 5112 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5113 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5114 ahc_outb(ahc, SCBPTR, saved_scbptr); 5115 } else { 5116 target_offset = TCL_TARGET_OFFSET(tcl); 5117 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5118 } 5119 5120 return (scbid); 5121 } 5122 5123 void 5124 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5125 { 5126 u_int target_offset; 5127 5128 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5129 u_int saved_scbptr; 5130 5131 saved_scbptr = ahc_inb(ahc, SCBPTR); 5132 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5133 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5134 ahc_outb(ahc, SCBPTR, saved_scbptr); 5135 } else { 5136 target_offset = TCL_TARGET_OFFSET(tcl); 5137 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5138 } 5139 } 5140 5141 void 5142 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5143 { 5144 u_int target_offset; 5145 5146 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5147 u_int saved_scbptr; 5148 5149 saved_scbptr = ahc_inb(ahc, SCBPTR); 5150 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5151 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5152 ahc_outb(ahc, SCBPTR, saved_scbptr); 5153 } else { 5154 target_offset = TCL_TARGET_OFFSET(tcl); 5155 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5156 } 5157 } 5158 5159 /************************** SCB and SCB queue management **********************/ 5160 int 5161 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5162 char channel, int lun, u_int tag, role_t role) 5163 { 5164 int targ = SCB_GET_TARGET(ahc, scb); 5165 char chan = SCB_GET_CHANNEL(ahc, scb); 5166 int slun = SCB_GET_LUN(scb); 5167 int match; 5168 5169 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5170 if (match != 0) 5171 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5172 if (match != 0) 5173 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5174 if (match != 0) { 5175 #ifdef AHC_TARGET_MODE 5176 int group; 5177 5178 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5179 if (role == ROLE_INITIATOR) { 5180 match = (group != XPT_FC_GROUP_TMODE) 5181 && ((tag == scb->hscb->tag) 5182 || (tag == SCB_LIST_NULL)); 5183 } else if (role == ROLE_TARGET) { 5184 match = (group == XPT_FC_GROUP_TMODE) 5185 && ((tag == scb->io_ctx->csio.tag_id) 5186 || (tag == SCB_LIST_NULL)); 5187 } 5188 #else /* !AHC_TARGET_MODE */ 5189 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5190 #endif /* AHC_TARGET_MODE */ 5191 } 5192 5193 return match; 5194 } 5195 5196 void 5197 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5198 { 5199 int target; 5200 char channel; 5201 int lun; 5202 5203 target = SCB_GET_TARGET(ahc, scb); 5204 lun = SCB_GET_LUN(scb); 5205 channel = SCB_GET_CHANNEL(ahc, scb); 5206 5207 ahc_search_qinfifo(ahc, target, channel, lun, 5208 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5209 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5210 5211 ahc_platform_freeze_devq(ahc, scb); 5212 } 5213 5214 void 5215 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5216 { 5217 struct scb *prev_scb; 5218 5219 prev_scb = NULL; 5220 if (ahc_qinfifo_count(ahc) != 0) { 5221 u_int prev_tag; 5222 uint8_t prev_pos; 5223 5224 prev_pos = ahc->qinfifonext - 1; 5225 prev_tag = ahc->qinfifo[prev_pos]; 5226 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5227 } 5228 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5229 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5230 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5231 } else { 5232 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5233 } 5234 } 5235 5236 static void 5237 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5238 struct scb *scb) 5239 { 5240 if (prev_scb == NULL) { 5241 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5242 } else { 5243 prev_scb->hscb->next = scb->hscb->tag; 5244 ahc_sync_scb(ahc, prev_scb, 5245 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5246 } 5247 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5248 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5249 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5250 } 5251 5252 static int 5253 ahc_qinfifo_count(struct ahc_softc *ahc) 5254 { 5255 uint8_t qinpos; 5256 uint8_t diff; 5257 5258 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5259 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5260 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5261 } else 5262 qinpos = ahc_inb(ahc, QINPOS); 5263 diff = ahc->qinfifonext - qinpos; 5264 return (diff); 5265 } 5266 5267 int 5268 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5269 int lun, u_int tag, role_t role, uint32_t status, 5270 ahc_search_action action) 5271 { 5272 struct scb *scb; 5273 struct scb *prev_scb; 5274 uint8_t qinstart; 5275 uint8_t qinpos; 5276 uint8_t qintail; 5277 uint8_t next; 5278 uint8_t prev; 5279 uint8_t curscbptr; 5280 int found; 5281 int have_qregs; 5282 5283 qintail = ahc->qinfifonext; 5284 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5285 if (have_qregs) { 5286 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5287 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5288 } else 5289 qinstart = ahc_inb(ahc, QINPOS); 5290 qinpos = qinstart; 5291 found = 0; 5292 prev_scb = NULL; 5293 5294 if (action == SEARCH_COMPLETE) { 5295 /* 5296 * Don't attempt to run any queued untagged transactions 5297 * until we are done with the abort process. 5298 */ 5299 ahc_freeze_untagged_queues(ahc); 5300 } 5301 5302 /* 5303 * Start with an empty queue. Entries that are not chosen 5304 * for removal will be re-added to the queue as we go. 5305 */ 5306 ahc->qinfifonext = qinpos; 5307 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5308 5309 while (qinpos != qintail) { 5310 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5311 if (scb == NULL) { 5312 printf("qinpos = %d, SCB index = %d\n", 5313 qinpos, ahc->qinfifo[qinpos]); 5314 panic("Loop 1\n"); 5315 } 5316 5317 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5318 /* 5319 * We found an scb that needs to be acted on. 5320 */ 5321 found++; 5322 switch (action) { 5323 case SEARCH_COMPLETE: 5324 { 5325 cam_status ostat; 5326 cam_status cstat; 5327 5328 ostat = ahc_get_transaction_status(scb); 5329 if (ostat == CAM_REQ_INPROG) 5330 ahc_set_transaction_status(scb, status); 5331 cstat = ahc_get_transaction_status(scb); 5332 if (cstat != CAM_REQ_CMP) 5333 ahc_freeze_scb(scb); 5334 if ((scb->flags & SCB_ACTIVE) == 0) 5335 printf("Inactive SCB in qinfifo\n"); 5336 ahc_done(ahc, scb); 5337 5338 /* FALLTHROUGH */ 5339 } 5340 case SEARCH_REMOVE: 5341 break; 5342 case SEARCH_COUNT: 5343 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5344 prev_scb = scb; 5345 break; 5346 } 5347 } else { 5348 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5349 prev_scb = scb; 5350 } 5351 qinpos++; 5352 } 5353 5354 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5355 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5356 } else { 5357 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5358 } 5359 5360 if (action != SEARCH_COUNT 5361 && (found != 0) 5362 && (qinstart != ahc->qinfifonext)) { 5363 /* 5364 * The sequencer may be in the process of dmaing 5365 * down the SCB at the beginning of the queue. 5366 * This could be problematic if either the first, 5367 * or the second SCB is removed from the queue 5368 * (the first SCB includes a pointer to the "next" 5369 * SCB to dma). If we have removed any entries, swap 5370 * the first element in the queue with the next HSCB 5371 * so the sequencer will notice that NEXT_QUEUED_SCB 5372 * has changed during its dma attempt and will retry 5373 * the DMA. 5374 */ 5375 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5376 5377 if (scb == NULL) { 5378 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5379 found, qinstart, ahc->qinfifonext); 5380 panic("First/Second Qinfifo fixup\n"); 5381 } 5382 /* 5383 * ahc_swap_with_next_hscb forces our next pointer to 5384 * point to the reserved SCB for future commands. Save 5385 * and restore our original next pointer to maintain 5386 * queue integrity. 5387 */ 5388 next = scb->hscb->next; 5389 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5390 ahc_swap_with_next_hscb(ahc, scb); 5391 scb->hscb->next = next; 5392 ahc->qinfifo[qinstart] = scb->hscb->tag; 5393 5394 /* Tell the card about the new head of the qinfifo. */ 5395 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5396 5397 /* Fixup the tail "next" pointer. */ 5398 qintail = ahc->qinfifonext - 1; 5399 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5400 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5401 } 5402 5403 /* 5404 * Search waiting for selection list. 5405 */ 5406 curscbptr = ahc_inb(ahc, SCBPTR); 5407 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5408 prev = SCB_LIST_NULL; 5409 5410 while (next != SCB_LIST_NULL) { 5411 uint8_t scb_index; 5412 5413 ahc_outb(ahc, SCBPTR, next); 5414 scb_index = ahc_inb(ahc, SCB_TAG); 5415 if (scb_index >= ahc->scb_data->numscbs) { 5416 printf("Waiting List inconsistency. " 5417 "SCB index == %d, yet numscbs == %d.", 5418 scb_index, ahc->scb_data->numscbs); 5419 ahc_dump_card_state(ahc); 5420 panic("for safety"); 5421 } 5422 scb = ahc_lookup_scb(ahc, scb_index); 5423 if (scb == NULL) { 5424 printf("scb_index = %d, next = %d\n", 5425 scb_index, next); 5426 panic("Waiting List traversal\n"); 5427 } 5428 if (ahc_match_scb(ahc, scb, target, channel, 5429 lun, SCB_LIST_NULL, role)) { 5430 /* 5431 * We found an scb that needs to be acted on. 5432 */ 5433 found++; 5434 switch (action) { 5435 case SEARCH_COMPLETE: 5436 { 5437 cam_status ostat; 5438 cam_status cstat; 5439 5440 ostat = ahc_get_transaction_status(scb); 5441 if (ostat == CAM_REQ_INPROG) 5442 ahc_set_transaction_status(scb, 5443 status); 5444 cstat = ahc_get_transaction_status(scb); 5445 if (cstat != CAM_REQ_CMP) 5446 ahc_freeze_scb(scb); 5447 if ((scb->flags & SCB_ACTIVE) == 0) 5448 printf("Inactive SCB in Waiting List\n"); 5449 ahc_done(ahc, scb); 5450 /* FALLTHROUGH */ 5451 } 5452 case SEARCH_REMOVE: 5453 next = ahc_rem_wscb(ahc, next, prev); 5454 break; 5455 case SEARCH_COUNT: 5456 prev = next; 5457 next = ahc_inb(ahc, SCB_NEXT); 5458 break; 5459 } 5460 } else { 5461 5462 prev = next; 5463 next = ahc_inb(ahc, SCB_NEXT); 5464 } 5465 } 5466 ahc_outb(ahc, SCBPTR, curscbptr); 5467 5468 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 5469 channel, lun, status, action); 5470 5471 if (action == SEARCH_COMPLETE) 5472 ahc_release_untagged_queues(ahc); 5473 return (found); 5474 } 5475 5476 int 5477 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx, 5478 int target, char channel, int lun, uint32_t status, 5479 ahc_search_action action) 5480 { 5481 struct scb *scb; 5482 int maxtarget; 5483 int found; 5484 int i; 5485 5486 if (action == SEARCH_COMPLETE) { 5487 /* 5488 * Don't attempt to run any queued untagged transactions 5489 * until we are done with the abort process. 5490 */ 5491 ahc_freeze_untagged_queues(ahc); 5492 } 5493 5494 found = 0; 5495 i = 0; 5496 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5497 5498 maxtarget = 16; 5499 if (target != CAM_TARGET_WILDCARD) { 5500 5501 i = target; 5502 if (channel == 'B') 5503 i += 8; 5504 maxtarget = i + 1; 5505 } 5506 } else { 5507 maxtarget = 0; 5508 } 5509 5510 for (; i < maxtarget; i++) { 5511 struct scb_tailq *untagged_q; 5512 struct scb *next_scb; 5513 5514 untagged_q = &(ahc->untagged_queues[i]); 5515 next_scb = TAILQ_FIRST(untagged_q); 5516 while (next_scb != NULL) { 5517 5518 scb = next_scb; 5519 next_scb = TAILQ_NEXT(scb, links.tqe); 5520 5521 /* 5522 * The head of the list may be the currently 5523 * active untagged command for a device. 5524 * We're only searching for commands that 5525 * have not been started. A transaction 5526 * marked active but still in the qinfifo 5527 * is removed by the qinfifo scanning code 5528 * above. 5529 */ 5530 if ((scb->flags & SCB_ACTIVE) != 0) 5531 continue; 5532 5533 if (ahc_match_scb(ahc, scb, target, channel, lun, 5534 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5535 || (ctx != NULL && ctx != scb->io_ctx)) 5536 continue; 5537 5538 /* 5539 * We found an scb that needs to be acted on. 5540 */ 5541 found++; 5542 switch (action) { 5543 case SEARCH_COMPLETE: 5544 { 5545 cam_status ostat; 5546 cam_status cstat; 5547 5548 ostat = ahc_get_transaction_status(scb); 5549 if (ostat == CAM_REQ_INPROG) 5550 ahc_set_transaction_status(scb, status); 5551 cstat = ahc_get_transaction_status(scb); 5552 if (cstat != CAM_REQ_CMP) 5553 ahc_freeze_scb(scb); 5554 if ((scb->flags & SCB_ACTIVE) == 0) 5555 printf("Inactive SCB in untaggedQ\n"); 5556 ahc_done(ahc, scb); 5557 break; 5558 } 5559 case SEARCH_REMOVE: 5560 scb->flags &= ~SCB_UNTAGGEDQ; 5561 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5562 break; 5563 case SEARCH_COUNT: 5564 break; 5565 } 5566 } 5567 } 5568 5569 if (action == SEARCH_COMPLETE) 5570 ahc_release_untagged_queues(ahc); 5571 return (found); 5572 } 5573 5574 int 5575 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5576 int lun, u_int tag, int stop_on_first, int remove, 5577 int save_state) 5578 { 5579 struct scb *scbp; 5580 u_int next; 5581 u_int prev; 5582 u_int count; 5583 u_int active_scb; 5584 5585 count = 0; 5586 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5587 prev = SCB_LIST_NULL; 5588 5589 if (save_state) { 5590 /* restore this when we're done */ 5591 active_scb = ahc_inb(ahc, SCBPTR); 5592 } else 5593 /* Silence compiler */ 5594 active_scb = SCB_LIST_NULL; 5595 5596 while (next != SCB_LIST_NULL) { 5597 u_int scb_index; 5598 5599 ahc_outb(ahc, SCBPTR, next); 5600 scb_index = ahc_inb(ahc, SCB_TAG); 5601 if (scb_index >= ahc->scb_data->numscbs) { 5602 printf("Disconnected List inconsistency. " 5603 "SCB index == %d, yet numscbs == %d.", 5604 scb_index, ahc->scb_data->numscbs); 5605 ahc_dump_card_state(ahc); 5606 panic("for safety"); 5607 } 5608 5609 if (next == prev) { 5610 panic("Disconnected List Loop. " 5611 "cur SCBPTR == %x, prev SCBPTR == %x.", 5612 next, prev); 5613 } 5614 scbp = ahc_lookup_scb(ahc, scb_index); 5615 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5616 tag, ROLE_INITIATOR)) { 5617 count++; 5618 if (remove) { 5619 next = 5620 ahc_rem_scb_from_disc_list(ahc, prev, next); 5621 } else { 5622 prev = next; 5623 next = ahc_inb(ahc, SCB_NEXT); 5624 } 5625 if (stop_on_first) 5626 break; 5627 } else { 5628 prev = next; 5629 next = ahc_inb(ahc, SCB_NEXT); 5630 } 5631 } 5632 if (save_state) 5633 ahc_outb(ahc, SCBPTR, active_scb); 5634 return (count); 5635 } 5636 5637 /* 5638 * Remove an SCB from the on chip list of disconnected transactions. 5639 * This is empty/unused if we are not performing SCB paging. 5640 */ 5641 static u_int 5642 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5643 { 5644 u_int next; 5645 5646 ahc_outb(ahc, SCBPTR, scbptr); 5647 next = ahc_inb(ahc, SCB_NEXT); 5648 5649 ahc_outb(ahc, SCB_CONTROL, 0); 5650 5651 ahc_add_curscb_to_free_list(ahc); 5652 5653 if (prev != SCB_LIST_NULL) { 5654 ahc_outb(ahc, SCBPTR, prev); 5655 ahc_outb(ahc, SCB_NEXT, next); 5656 } else 5657 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5658 5659 return (next); 5660 } 5661 5662 /* 5663 * Add the SCB as selected by SCBPTR onto the on chip list of 5664 * free hardware SCBs. This list is empty/unused if we are not 5665 * performing SCB paging. 5666 */ 5667 static void 5668 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5669 { 5670 /* 5671 * Invalidate the tag so that our abort 5672 * routines don't think it's active. 5673 */ 5674 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5675 5676 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5677 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5678 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5679 } 5680 } 5681 5682 /* 5683 * Manipulate the waiting for selection list and return the 5684 * scb that follows the one that we remove. 5685 */ 5686 static u_int 5687 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5688 { 5689 u_int curscb, next; 5690 5691 /* 5692 * Select the SCB we want to abort and 5693 * pull the next pointer out of it. 5694 */ 5695 curscb = ahc_inb(ahc, SCBPTR); 5696 ahc_outb(ahc, SCBPTR, scbpos); 5697 next = ahc_inb(ahc, SCB_NEXT); 5698 5699 /* Clear the necessary fields */ 5700 ahc_outb(ahc, SCB_CONTROL, 0); 5701 5702 ahc_add_curscb_to_free_list(ahc); 5703 5704 /* update the waiting list */ 5705 if (prev == SCB_LIST_NULL) { 5706 /* First in the list */ 5707 ahc_outb(ahc, WAITING_SCBH, next); 5708 5709 /* 5710 * Ensure we aren't attempting to perform 5711 * selection for this entry. 5712 */ 5713 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5714 } else { 5715 /* 5716 * Select the scb that pointed to us 5717 * and update its next pointer. 5718 */ 5719 ahc_outb(ahc, SCBPTR, prev); 5720 ahc_outb(ahc, SCB_NEXT, next); 5721 } 5722 5723 /* 5724 * Point us back at the original scb position. 5725 */ 5726 ahc_outb(ahc, SCBPTR, curscb); 5727 return next; 5728 } 5729 5730 /******************************** Error Handling ******************************/ 5731 /* 5732 * Abort all SCBs that match the given description (target/channel/lun/tag), 5733 * setting their status to the passed in status if the status has not already 5734 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5735 * is paused before it is called. 5736 */ 5737 int 5738 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5739 int lun, u_int tag, role_t role, uint32_t status) 5740 { 5741 struct scb *scbp; 5742 struct scb *scbp_next; 5743 u_int active_scb; 5744 int i, j; 5745 int maxtarget; 5746 int minlun; 5747 int maxlun; 5748 5749 int found; 5750 5751 /* 5752 * Don't attempt to run any queued untagged transactions 5753 * until we are done with the abort process. 5754 */ 5755 ahc_freeze_untagged_queues(ahc); 5756 5757 /* restore this when we're done */ 5758 active_scb = ahc_inb(ahc, SCBPTR); 5759 5760 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5761 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5762 5763 /* 5764 * Clean out the busy target table for any untagged commands. 5765 */ 5766 i = 0; 5767 maxtarget = 16; 5768 if (target != CAM_TARGET_WILDCARD) { 5769 i = target; 5770 if (channel == 'B') 5771 i += 8; 5772 maxtarget = i + 1; 5773 } 5774 5775 if (lun == CAM_LUN_WILDCARD) { 5776 5777 /* 5778 * Unless we are using an SCB based 5779 * busy targets table, there is only 5780 * one table entry for all luns of 5781 * a target. 5782 */ 5783 minlun = 0; 5784 maxlun = 1; 5785 if ((ahc->flags & AHC_SCB_BTT) != 0) 5786 maxlun = AHC_NUM_LUNS; 5787 } else { 5788 minlun = lun; 5789 maxlun = lun + 1; 5790 } 5791 5792 if (role != ROLE_TARGET) { 5793 for (;i < maxtarget; i++) { 5794 for (j = minlun;j < maxlun; j++) { 5795 u_int scbid; 5796 u_int tcl; 5797 5798 tcl = BUILD_TCL(i << 4, j); 5799 scbid = ahc_index_busy_tcl(ahc, tcl); 5800 scbp = ahc_lookup_scb(ahc, scbid); 5801 if (scbp == NULL 5802 || ahc_match_scb(ahc, scbp, target, channel, 5803 lun, tag, role) == 0) 5804 continue; 5805 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5806 } 5807 } 5808 5809 /* 5810 * Go through the disconnected list and remove any entries we 5811 * have queued for completion, 0'ing their control byte too. 5812 * We save the active SCB and restore it ourselves, so there 5813 * is no reason for this search to restore it too. 5814 */ 5815 ahc_search_disc_list(ahc, target, channel, lun, tag, 5816 /*stop_on_first*/FALSE, /*remove*/TRUE, 5817 /*save_state*/FALSE); 5818 } 5819 5820 /* 5821 * Go through the hardware SCB array looking for commands that 5822 * were active but not on any list. In some cases, these remnants 5823 * might not still have mappings in the scbindex array (e.g. unexpected 5824 * bus free with the same scb queued for an abort). Don't hold this 5825 * against them. 5826 */ 5827 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5828 u_int scbid; 5829 5830 ahc_outb(ahc, SCBPTR, i); 5831 scbid = ahc_inb(ahc, SCB_TAG); 5832 scbp = ahc_lookup_scb(ahc, scbid); 5833 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5834 || (scbp != NULL 5835 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5836 ahc_add_curscb_to_free_list(ahc); 5837 } 5838 5839 /* 5840 * Go through the pending CCB list and look for 5841 * commands for this target that are still active. 5842 * These are other tagged commands that were 5843 * disconnected when the reset occurred. 5844 */ 5845 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5846 while (scbp_next != NULL) { 5847 scbp = scbp_next; 5848 scbp_next = LIST_NEXT(scbp, pending_links); 5849 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5850 cam_status ostat; 5851 5852 ostat = ahc_get_transaction_status(scbp); 5853 if (ostat == CAM_REQ_INPROG) 5854 ahc_set_transaction_status(scbp, status); 5855 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5856 ahc_freeze_scb(scbp); 5857 if ((scbp->flags & SCB_ACTIVE) == 0) 5858 printf("Inactive SCB on pending list\n"); 5859 ahc_done(ahc, scbp); 5860 found++; 5861 } 5862 } 5863 ahc_outb(ahc, SCBPTR, active_scb); 5864 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5865 ahc_release_untagged_queues(ahc); 5866 return found; 5867 } 5868 5869 static void 5870 ahc_reset_current_bus(struct ahc_softc *ahc) 5871 { 5872 uint8_t scsiseq; 5873 5874 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5875 scsiseq = ahc_inb(ahc, SCSISEQ); 5876 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5877 ahc_flush_device_writes(ahc); 5878 ahc_delay(AHC_BUSRESET_DELAY); 5879 /* Turn off the bus reset */ 5880 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5881 5882 ahc_clear_intstat(ahc); 5883 5884 /* Re-enable reset interrupts */ 5885 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5886 } 5887 5888 int 5889 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5890 { 5891 struct ahc_devinfo devinfo; 5892 u_int initiator, target, max_scsiid; 5893 u_int sblkctl; 5894 u_int scsiseq; 5895 u_int simode1; 5896 int found; 5897 int restart_needed; 5898 char cur_channel; 5899 5900 ahc->pending_device = NULL; 5901 5902 ahc_compile_devinfo(&devinfo, 5903 CAM_TARGET_WILDCARD, 5904 CAM_TARGET_WILDCARD, 5905 CAM_LUN_WILDCARD, 5906 channel, ROLE_UNKNOWN); 5907 ahc_pause(ahc); 5908 5909 /* Make sure the sequencer is in a safe location. */ 5910 ahc_clear_critical_section(ahc); 5911 5912 /* 5913 * Run our command complete fifos to ensure that we perform 5914 * completion processing on any commands that 'completed' 5915 * before the reset occurred. 5916 */ 5917 ahc_run_qoutfifo(ahc); 5918 #ifdef AHC_TARGET_MODE 5919 /* 5920 * XXX - In Twin mode, the tqinfifo may have commands 5921 * for an unaffected channel in it. However, if 5922 * we have run out of ATIO resources to drain that 5923 * queue, we may not get them all out here. Further, 5924 * the blocked transactions for the reset channel 5925 * should just be killed off, irrespecitve of whether 5926 * we are blocked on ATIO resources. Write a routine 5927 * to compact the tqinfifo appropriately. 5928 */ 5929 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5930 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5931 } 5932 #endif 5933 5934 /* 5935 * Reset the bus if we are initiating this reset 5936 */ 5937 sblkctl = ahc_inb(ahc, SBLKCTL); 5938 cur_channel = 'A'; 5939 if ((ahc->features & AHC_TWIN) != 0 5940 && ((sblkctl & SELBUSB) != 0)) 5941 cur_channel = 'B'; 5942 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5943 if (cur_channel != channel) { 5944 /* Case 1: Command for another bus is active 5945 * Stealthily reset the other bus without 5946 * upsetting the current bus. 5947 */ 5948 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5949 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5950 #ifdef AHC_TARGET_MODE 5951 /* 5952 * Bus resets clear ENSELI, so we cannot 5953 * defer re-enabling bus reset interrupts 5954 * if we are in target mode. 5955 */ 5956 if ((ahc->flags & AHC_TARGETROLE) != 0) 5957 simode1 |= ENSCSIRST; 5958 #endif 5959 ahc_outb(ahc, SIMODE1, simode1); 5960 if (initiate_reset) 5961 ahc_reset_current_bus(ahc); 5962 ahc_clear_intstat(ahc); 5963 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5964 ahc_outb(ahc, SBLKCTL, sblkctl); 5965 restart_needed = FALSE; 5966 } else { 5967 /* Case 2: A command from this bus is active or we're idle */ 5968 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5969 #ifdef AHC_TARGET_MODE 5970 /* 5971 * Bus resets clear ENSELI, so we cannot 5972 * defer re-enabling bus reset interrupts 5973 * if we are in target mode. 5974 */ 5975 if ((ahc->flags & AHC_TARGETROLE) != 0) 5976 simode1 |= ENSCSIRST; 5977 #endif 5978 ahc_outb(ahc, SIMODE1, simode1); 5979 if (initiate_reset) 5980 ahc_reset_current_bus(ahc); 5981 ahc_clear_intstat(ahc); 5982 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5983 restart_needed = TRUE; 5984 } 5985 5986 /* 5987 * Clean up all the state information for the 5988 * pending transactions on this bus. 5989 */ 5990 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 5991 CAM_LUN_WILDCARD, SCB_LIST_NULL, 5992 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 5993 5994 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5995 5996 #ifdef AHC_TARGET_MODE 5997 /* 5998 * Send an immediate notify ccb to all target more peripheral 5999 * drivers affected by this action. 6000 */ 6001 for (target = 0; target <= max_scsiid; target++) { 6002 struct ahc_tmode_tstate* tstate; 6003 u_int lun; 6004 6005 tstate = ahc->enabled_targets[target]; 6006 if (tstate == NULL) 6007 continue; 6008 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6009 struct ahc_tmode_lstate* lstate; 6010 6011 lstate = tstate->enabled_luns[lun]; 6012 if (lstate == NULL) 6013 continue; 6014 6015 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6016 EVENT_TYPE_BUS_RESET, /*arg*/0); 6017 ahc_send_lstate_events(ahc, lstate); 6018 } 6019 } 6020 #endif 6021 /* Notify the XPT that a bus reset occurred */ 6022 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 6023 CAM_LUN_WILDCARD, AC_BUS_RESET); 6024 6025 /* 6026 * Revert to async/narrow transfers until we renegotiate. 6027 */ 6028 for (target = 0; target <= max_scsiid; target++) { 6029 6030 if (ahc->enabled_targets[target] == NULL) 6031 continue; 6032 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6033 struct ahc_devinfo devinfo; 6034 6035 ahc_compile_devinfo(&devinfo, target, initiator, 6036 CAM_LUN_WILDCARD, 6037 channel, ROLE_UNKNOWN); 6038 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6039 AHC_TRANS_CUR, /*paused*/TRUE); 6040 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6041 /*period*/0, /*offset*/0, 6042 /*ppr_options*/0, AHC_TRANS_CUR, 6043 /*paused*/TRUE); 6044 } 6045 } 6046 6047 if (restart_needed) 6048 ahc_restart(ahc); 6049 else 6050 ahc_unpause(ahc); 6051 return found; 6052 } 6053 6054 6055 /***************************** Residual Processing ****************************/ 6056 /* 6057 * Calculate the residual for a just completed SCB. 6058 */ 6059 void 6060 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6061 { 6062 struct hardware_scb *hscb; 6063 struct status_pkt *spkt; 6064 uint32_t sgptr; 6065 uint32_t resid_sgptr; 6066 uint32_t resid; 6067 6068 /* 6069 * 5 cases. 6070 * 1) No residual. 6071 * SG_RESID_VALID clear in sgptr. 6072 * 2) Transferless command 6073 * 3) Never performed any transfers. 6074 * sgptr has SG_FULL_RESID set. 6075 * 4) No residual but target did not 6076 * save data pointers after the 6077 * last transfer, so sgptr was 6078 * never updated. 6079 * 5) We have a partial residual. 6080 * Use residual_sgptr to determine 6081 * where we are. 6082 */ 6083 6084 hscb = scb->hscb; 6085 sgptr = ahc_le32toh(hscb->sgptr); 6086 if ((sgptr & SG_RESID_VALID) == 0) 6087 /* Case 1 */ 6088 return; 6089 sgptr &= ~SG_RESID_VALID; 6090 6091 if ((sgptr & SG_LIST_NULL) != 0) 6092 /* Case 2 */ 6093 return; 6094 6095 spkt = &hscb->shared_data.status; 6096 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6097 if ((sgptr & SG_FULL_RESID) != 0) { 6098 /* Case 3 */ 6099 resid = ahc_get_transfer_length(scb); 6100 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6101 /* Case 4 */ 6102 return; 6103 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6104 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6105 } else { 6106 struct ahc_dma_seg *sg; 6107 6108 /* 6109 * Remainder of the SG where the transfer 6110 * stopped. 6111 */ 6112 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6113 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6114 6115 /* The residual sg_ptr always points to the next sg */ 6116 sg--; 6117 6118 /* 6119 * Add up the contents of all residual 6120 * SG segments that are after the SG where 6121 * the transfer stopped. 6122 */ 6123 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6124 sg++; 6125 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6126 } 6127 } 6128 if ((scb->flags & SCB_SENSE) == 0) 6129 ahc_set_residual(scb, resid); 6130 else 6131 ahc_set_sense_residual(scb, resid); 6132 6133 #ifdef AHC_DEBUG 6134 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6135 ahc_print_path(ahc, scb); 6136 printf("Handled %sResidual of %d bytes\n", 6137 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6138 } 6139 #endif 6140 } 6141 6142 /******************************* Target Mode **********************************/ 6143 #ifdef AHC_TARGET_MODE 6144 /* 6145 * Add a target mode event to this lun's queue 6146 */ 6147 static void 6148 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6149 u_int initiator_id, u_int event_type, u_int event_arg) 6150 { 6151 struct ahc_tmode_event *event; 6152 int pending; 6153 6154 xpt_freeze_devq(lstate->path, /*count*/1); 6155 if (lstate->event_w_idx >= lstate->event_r_idx) 6156 pending = lstate->event_w_idx - lstate->event_r_idx; 6157 else 6158 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6159 - (lstate->event_r_idx - lstate->event_w_idx); 6160 6161 if (event_type == EVENT_TYPE_BUS_RESET 6162 || event_type == MSG_BUS_DEV_RESET) { 6163 /* 6164 * Any earlier events are irrelevant, so reset our buffer. 6165 * This has the effect of allowing us to deal with reset 6166 * floods (an external device holding down the reset line) 6167 * without losing the event that is really interesting. 6168 */ 6169 lstate->event_r_idx = 0; 6170 lstate->event_w_idx = 0; 6171 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6172 } 6173 6174 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6175 xpt_print_path(lstate->path); 6176 printf("immediate event %x:%x lost\n", 6177 lstate->event_buffer[lstate->event_r_idx].event_type, 6178 lstate->event_buffer[lstate->event_r_idx].event_arg); 6179 lstate->event_r_idx++; 6180 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6181 lstate->event_r_idx = 0; 6182 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6183 } 6184 6185 event = &lstate->event_buffer[lstate->event_w_idx]; 6186 event->initiator_id = initiator_id; 6187 event->event_type = event_type; 6188 event->event_arg = event_arg; 6189 lstate->event_w_idx++; 6190 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6191 lstate->event_w_idx = 0; 6192 } 6193 6194 /* 6195 * Send any target mode events queued up waiting 6196 * for immediate notify resources. 6197 */ 6198 void 6199 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6200 { 6201 struct ccb_hdr *ccbh; 6202 struct ccb_immed_notify *inot; 6203 6204 while (lstate->event_r_idx != lstate->event_w_idx 6205 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6206 struct ahc_tmode_event *event; 6207 6208 event = &lstate->event_buffer[lstate->event_r_idx]; 6209 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6210 inot = (struct ccb_immed_notify *)ccbh; 6211 switch (event->event_type) { 6212 case EVENT_TYPE_BUS_RESET: 6213 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6214 break; 6215 default: 6216 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6217 inot->message_args[0] = event->event_type; 6218 inot->message_args[1] = event->event_arg; 6219 break; 6220 } 6221 inot->initiator_id = event->initiator_id; 6222 inot->sense_len = 0; 6223 xpt_done((union ccb *)inot); 6224 lstate->event_r_idx++; 6225 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6226 lstate->event_r_idx = 0; 6227 } 6228 } 6229 #endif 6230 6231 /******************** Sequencer Program Patching/Download *********************/ 6232 6233 #ifdef AHC_DUMP_SEQ 6234 void 6235 ahc_dumpseq(struct ahc_softc* ahc) 6236 { 6237 int i; 6238 6239 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6240 ahc_outb(ahc, SEQADDR0, 0); 6241 ahc_outb(ahc, SEQADDR1, 0); 6242 for (i = 0; i < ahc->instruction_ram_size; i++) { 6243 uint8_t ins_bytes[4]; 6244 6245 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6246 printf("0x%08x\n", ins_bytes[0] << 24 6247 | ins_bytes[1] << 16 6248 | ins_bytes[2] << 8 6249 | ins_bytes[3]); 6250 } 6251 } 6252 #endif 6253 6254 static int 6255 ahc_loadseq(struct ahc_softc *ahc) 6256 { 6257 struct cs cs_table[num_critical_sections]; 6258 u_int begin_set[num_critical_sections]; 6259 u_int end_set[num_critical_sections]; 6260 struct patch *cur_patch; 6261 u_int cs_count; 6262 u_int cur_cs; 6263 u_int i; 6264 u_int skip_addr; 6265 u_int sg_prefetch_cnt; 6266 int downloaded; 6267 uint8_t download_consts[7]; 6268 6269 /* 6270 * Start out with 0 critical sections 6271 * that apply to this firmware load. 6272 */ 6273 cs_count = 0; 6274 cur_cs = 0; 6275 memset(begin_set, 0, sizeof(begin_set)); 6276 memset(end_set, 0, sizeof(end_set)); 6277 6278 /* Setup downloadable constant table */ 6279 download_consts[QOUTFIFO_OFFSET] = 0; 6280 if (ahc->targetcmds != NULL) 6281 download_consts[QOUTFIFO_OFFSET] += 32; 6282 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6283 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6284 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6285 sg_prefetch_cnt = ahc->pci_cachesize; 6286 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6287 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6288 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6289 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6290 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6291 6292 cur_patch = patches; 6293 downloaded = 0; 6294 skip_addr = 0; 6295 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6296 ahc_outb(ahc, SEQADDR0, 0); 6297 ahc_outb(ahc, SEQADDR1, 0); 6298 6299 for (i = 0; i < sizeof(seqprog)/4; i++) { 6300 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6301 /* 6302 * Don't download this instruction as it 6303 * is in a patch that was removed. 6304 */ 6305 continue; 6306 } 6307 6308 if (downloaded == ahc->instruction_ram_size) { 6309 /* 6310 * We're about to exceed the instruction 6311 * storage capacity for this chip. Fail 6312 * the load. 6313 */ 6314 printf("\n%s: Program too large for instruction memory " 6315 "size of %d!\n", ahc_name(ahc), 6316 ahc->instruction_ram_size); 6317 return (ENOMEM); 6318 } 6319 6320 /* 6321 * Move through the CS table until we find a CS 6322 * that might apply to this instruction. 6323 */ 6324 for (; cur_cs < num_critical_sections; cur_cs++) { 6325 if (critical_sections[cur_cs].end <= i) { 6326 if (begin_set[cs_count] == TRUE 6327 && end_set[cs_count] == FALSE) { 6328 cs_table[cs_count].end = downloaded; 6329 end_set[cs_count] = TRUE; 6330 cs_count++; 6331 } 6332 continue; 6333 } 6334 if (critical_sections[cur_cs].begin <= i 6335 && begin_set[cs_count] == FALSE) { 6336 cs_table[cs_count].begin = downloaded; 6337 begin_set[cs_count] = TRUE; 6338 } 6339 break; 6340 } 6341 ahc_download_instr(ahc, i, download_consts); 6342 downloaded++; 6343 } 6344 6345 ahc->num_critical_sections = cs_count; 6346 if (cs_count != 0) { 6347 6348 cs_count *= sizeof(struct cs); 6349 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6350 if (ahc->critical_sections == NULL) 6351 panic("ahc_loadseq: Could not malloc"); 6352 memcpy(ahc->critical_sections, cs_table, cs_count); 6353 } 6354 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6355 6356 if (bootverbose) { 6357 printf(" %d instructions downloaded\n", downloaded); 6358 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6359 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6360 } 6361 return (0); 6362 } 6363 6364 static int 6365 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6366 u_int start_instr, u_int *skip_addr) 6367 { 6368 struct patch *cur_patch; 6369 struct patch *last_patch; 6370 u_int num_patches; 6371 6372 num_patches = ARRAY_SIZE(patches); 6373 last_patch = &patches[num_patches]; 6374 cur_patch = *start_patch; 6375 6376 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6377 6378 if (cur_patch->patch_func(ahc) == 0) { 6379 6380 /* Start rejecting code */ 6381 *skip_addr = start_instr + cur_patch->skip_instr; 6382 cur_patch += cur_patch->skip_patch; 6383 } else { 6384 /* Accepted this patch. Advance to the next 6385 * one and wait for our intruction pointer to 6386 * hit this point. 6387 */ 6388 cur_patch++; 6389 } 6390 } 6391 6392 *start_patch = cur_patch; 6393 if (start_instr < *skip_addr) 6394 /* Still skipping */ 6395 return (0); 6396 6397 return (1); 6398 } 6399 6400 static void 6401 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6402 { 6403 union ins_formats instr; 6404 struct ins_format1 *fmt1_ins; 6405 struct ins_format3 *fmt3_ins; 6406 u_int opcode; 6407 6408 /* 6409 * The firmware is always compiled into a little endian format. 6410 */ 6411 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6412 6413 fmt1_ins = &instr.format1; 6414 fmt3_ins = NULL; 6415 6416 /* Pull the opcode */ 6417 opcode = instr.format1.opcode; 6418 switch (opcode) { 6419 case AIC_OP_JMP: 6420 case AIC_OP_JC: 6421 case AIC_OP_JNC: 6422 case AIC_OP_CALL: 6423 case AIC_OP_JNE: 6424 case AIC_OP_JNZ: 6425 case AIC_OP_JE: 6426 case AIC_OP_JZ: 6427 { 6428 struct patch *cur_patch; 6429 int address_offset; 6430 u_int address; 6431 u_int skip_addr; 6432 u_int i; 6433 6434 fmt3_ins = &instr.format3; 6435 address_offset = 0; 6436 address = fmt3_ins->address; 6437 cur_patch = patches; 6438 skip_addr = 0; 6439 6440 for (i = 0; i < address;) { 6441 6442 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6443 6444 if (skip_addr > i) { 6445 int end_addr; 6446 6447 end_addr = min(address, skip_addr); 6448 address_offset += end_addr - i; 6449 i = skip_addr; 6450 } else { 6451 i++; 6452 } 6453 } 6454 address -= address_offset; 6455 fmt3_ins->address = address; 6456 /* FALLTHROUGH */ 6457 } 6458 case AIC_OP_OR: 6459 case AIC_OP_AND: 6460 case AIC_OP_XOR: 6461 case AIC_OP_ADD: 6462 case AIC_OP_ADC: 6463 case AIC_OP_BMOV: 6464 if (fmt1_ins->parity != 0) { 6465 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6466 } 6467 fmt1_ins->parity = 0; 6468 if ((ahc->features & AHC_CMD_CHAN) == 0 6469 && opcode == AIC_OP_BMOV) { 6470 /* 6471 * Block move was added at the same time 6472 * as the command channel. Verify that 6473 * this is only a move of a single element 6474 * and convert the BMOV to a MOV 6475 * (AND with an immediate of FF). 6476 */ 6477 if (fmt1_ins->immediate != 1) 6478 panic("%s: BMOV not supported\n", 6479 ahc_name(ahc)); 6480 fmt1_ins->opcode = AIC_OP_AND; 6481 fmt1_ins->immediate = 0xff; 6482 } 6483 /* FALLTHROUGH */ 6484 case AIC_OP_ROL: 6485 if ((ahc->features & AHC_ULTRA2) != 0) { 6486 int i, count; 6487 6488 /* Calculate odd parity for the instruction */ 6489 for (i = 0, count = 0; i < 31; i++) { 6490 uint32_t mask; 6491 6492 mask = 0x01 << i; 6493 if ((instr.integer & mask) != 0) 6494 count++; 6495 } 6496 if ((count & 0x01) == 0) 6497 instr.format1.parity = 1; 6498 } else { 6499 /* Compress the instruction for older sequencers */ 6500 if (fmt3_ins != NULL) { 6501 instr.integer = 6502 fmt3_ins->immediate 6503 | (fmt3_ins->source << 8) 6504 | (fmt3_ins->address << 16) 6505 | (fmt3_ins->opcode << 25); 6506 } else { 6507 instr.integer = 6508 fmt1_ins->immediate 6509 | (fmt1_ins->source << 8) 6510 | (fmt1_ins->destination << 16) 6511 | (fmt1_ins->ret << 24) 6512 | (fmt1_ins->opcode << 25); 6513 } 6514 } 6515 /* The sequencer is a little endian cpu */ 6516 instr.integer = ahc_htole32(instr.integer); 6517 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6518 break; 6519 default: 6520 panic("Unknown opcode encountered in seq program"); 6521 break; 6522 } 6523 } 6524 6525 int 6526 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6527 const char *name, u_int address, u_int value, 6528 u_int *cur_column, u_int wrap_point) 6529 { 6530 int printed; 6531 u_int printed_mask; 6532 6533 if (cur_column != NULL && *cur_column >= wrap_point) { 6534 printf("\n"); 6535 *cur_column = 0; 6536 } 6537 printed = printf("%s[0x%x]", name, value); 6538 if (table == NULL) { 6539 printed += printf(" "); 6540 *cur_column += printed; 6541 return (printed); 6542 } 6543 printed_mask = 0; 6544 while (printed_mask != 0xFF) { 6545 int entry; 6546 6547 for (entry = 0; entry < num_entries; entry++) { 6548 if (((value & table[entry].mask) 6549 != table[entry].value) 6550 || ((printed_mask & table[entry].mask) 6551 == table[entry].mask)) 6552 continue; 6553 6554 printed += printf("%s%s", 6555 printed_mask == 0 ? ":(" : "|", 6556 table[entry].name); 6557 printed_mask |= table[entry].mask; 6558 6559 break; 6560 } 6561 if (entry >= num_entries) 6562 break; 6563 } 6564 if (printed_mask != 0) 6565 printed += printf(") "); 6566 else 6567 printed += printf(" "); 6568 if (cur_column != NULL) 6569 *cur_column += printed; 6570 return (printed); 6571 } 6572 6573 void 6574 ahc_dump_card_state(struct ahc_softc *ahc) 6575 { 6576 struct scb *scb; 6577 struct scb_tailq *untagged_q; 6578 u_int cur_col; 6579 int paused; 6580 int target; 6581 int maxtarget; 6582 int i; 6583 uint8_t last_phase; 6584 uint8_t qinpos; 6585 uint8_t qintail; 6586 uint8_t qoutpos; 6587 uint8_t scb_index; 6588 uint8_t saved_scbptr; 6589 6590 if (ahc_is_paused(ahc)) { 6591 paused = 1; 6592 } else { 6593 paused = 0; 6594 ahc_pause(ahc); 6595 } 6596 6597 saved_scbptr = ahc_inb(ahc, SCBPTR); 6598 last_phase = ahc_inb(ahc, LASTPHASE); 6599 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6600 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6601 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6602 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6603 if (paused) 6604 printf("Card was paused\n"); 6605 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6606 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6607 ahc_inb(ahc, ARG_2)); 6608 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6609 ahc_inb(ahc, SCBPTR)); 6610 cur_col = 0; 6611 if ((ahc->features & AHC_DT) != 0) 6612 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6613 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6614 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6615 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6616 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6617 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6618 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6619 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6620 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6621 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6622 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6623 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6624 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6625 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6626 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6627 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6628 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6629 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6630 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6631 if (cur_col != 0) 6632 printf("\n"); 6633 printf("STACK:"); 6634 for (i = 0; i < STACK_SIZE; i++) 6635 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6636 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6637 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6638 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6639 /* QINFIFO */ 6640 printf("QINFIFO entries: "); 6641 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6642 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6643 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6644 } else 6645 qinpos = ahc_inb(ahc, QINPOS); 6646 qintail = ahc->qinfifonext; 6647 while (qinpos != qintail) { 6648 printf("%d ", ahc->qinfifo[qinpos]); 6649 qinpos++; 6650 } 6651 printf("\n"); 6652 6653 printf("Waiting Queue entries: "); 6654 scb_index = ahc_inb(ahc, WAITING_SCBH); 6655 i = 0; 6656 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6657 ahc_outb(ahc, SCBPTR, scb_index); 6658 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6659 scb_index = ahc_inb(ahc, SCB_NEXT); 6660 } 6661 printf("\n"); 6662 6663 printf("Disconnected Queue entries: "); 6664 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6665 i = 0; 6666 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6667 ahc_outb(ahc, SCBPTR, scb_index); 6668 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6669 scb_index = ahc_inb(ahc, SCB_NEXT); 6670 } 6671 printf("\n"); 6672 6673 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6674 printf("QOUTFIFO entries: "); 6675 qoutpos = ahc->qoutfifonext; 6676 i = 0; 6677 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6678 printf("%d ", ahc->qoutfifo[qoutpos]); 6679 qoutpos++; 6680 } 6681 printf("\n"); 6682 6683 printf("Sequencer Free SCB List: "); 6684 scb_index = ahc_inb(ahc, FREE_SCBH); 6685 i = 0; 6686 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6687 ahc_outb(ahc, SCBPTR, scb_index); 6688 printf("%d ", scb_index); 6689 scb_index = ahc_inb(ahc, SCB_NEXT); 6690 } 6691 printf("\n"); 6692 6693 printf("Sequencer SCB Info: "); 6694 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6695 ahc_outb(ahc, SCBPTR, i); 6696 cur_col = printf("\n%3d ", i); 6697 6698 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6699 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6700 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6701 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6702 } 6703 printf("\n"); 6704 6705 printf("Pending list: "); 6706 i = 0; 6707 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6708 if (i++ > 256) 6709 break; 6710 cur_col = printf("\n%3d ", scb->hscb->tag); 6711 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6712 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6713 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6714 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6715 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6716 printf("("); 6717 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6718 &cur_col, 60); 6719 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6720 printf(")"); 6721 } 6722 } 6723 printf("\n"); 6724 6725 printf("Kernel Free SCB list: "); 6726 i = 0; 6727 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6728 if (i++ > 256) 6729 break; 6730 printf("%d ", scb->hscb->tag); 6731 } 6732 printf("\n"); 6733 6734 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6735 for (target = 0; target <= maxtarget; target++) { 6736 untagged_q = &ahc->untagged_queues[target]; 6737 if (TAILQ_FIRST(untagged_q) == NULL) 6738 continue; 6739 printf("Untagged Q(%d): ", target); 6740 i = 0; 6741 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6742 if (i++ > 256) 6743 break; 6744 printf("%d ", scb->hscb->tag); 6745 } 6746 printf("\n"); 6747 } 6748 6749 ahc_platform_dump_card_state(ahc); 6750 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6751 ahc_outb(ahc, SCBPTR, saved_scbptr); 6752 if (paused == 0) 6753 ahc_unpause(ahc); 6754 } 6755 6756 /************************* Target Mode ****************************************/ 6757 #ifdef AHC_TARGET_MODE 6758 cam_status 6759 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6760 struct ahc_tmode_tstate **tstate, 6761 struct ahc_tmode_lstate **lstate, 6762 int notfound_failure) 6763 { 6764 6765 if ((ahc->features & AHC_TARGETMODE) == 0) 6766 return (CAM_REQ_INVALID); 6767 6768 /* 6769 * Handle the 'black hole' device that sucks up 6770 * requests to unattached luns on enabled targets. 6771 */ 6772 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6773 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6774 *tstate = NULL; 6775 *lstate = ahc->black_hole; 6776 } else { 6777 u_int max_id; 6778 6779 max_id = (ahc->features & AHC_WIDE) ? 16 : 8; 6780 if (ccb->ccb_h.target_id >= max_id) 6781 return (CAM_TID_INVALID); 6782 6783 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6784 return (CAM_LUN_INVALID); 6785 6786 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6787 *lstate = NULL; 6788 if (*tstate != NULL) 6789 *lstate = 6790 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6791 } 6792 6793 if (notfound_failure != 0 && *lstate == NULL) 6794 return (CAM_PATH_INVALID); 6795 6796 return (CAM_REQ_CMP); 6797 } 6798 6799 void 6800 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6801 { 6802 struct ahc_tmode_tstate *tstate; 6803 struct ahc_tmode_lstate *lstate; 6804 struct ccb_en_lun *cel; 6805 cam_status status; 6806 u_long s; 6807 u_int target; 6808 u_int lun; 6809 u_int target_mask; 6810 u_int our_id; 6811 int error; 6812 char channel; 6813 6814 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6815 /*notfound_failure*/FALSE); 6816 6817 if (status != CAM_REQ_CMP) { 6818 ccb->ccb_h.status = status; 6819 return; 6820 } 6821 6822 if (cam_sim_bus(sim) == 0) 6823 our_id = ahc->our_id; 6824 else 6825 our_id = ahc->our_id_b; 6826 6827 if (ccb->ccb_h.target_id != our_id) { 6828 /* 6829 * our_id represents our initiator ID, or 6830 * the ID of the first target to have an 6831 * enabled lun in target mode. There are 6832 * two cases that may preclude enabling a 6833 * target id other than our_id. 6834 * 6835 * o our_id is for an active initiator role. 6836 * Since the hardware does not support 6837 * reselections to the initiator role at 6838 * anything other than our_id, and our_id 6839 * is used by the hardware to indicate the 6840 * ID to use for both select-out and 6841 * reselect-out operations, the only target 6842 * ID we can support in this mode is our_id. 6843 * 6844 * o The MULTARGID feature is not available and 6845 * a previous target mode ID has been enabled. 6846 */ 6847 if ((ahc->features & AHC_MULTIROLE) != 0) { 6848 6849 if ((ahc->features & AHC_MULTI_TID) != 0 6850 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6851 /* 6852 * Only allow additional targets if 6853 * the initiator role is disabled. 6854 * The hardware cannot handle a re-select-in 6855 * on the initiator id during a re-select-out 6856 * on a different target id. 6857 */ 6858 status = CAM_TID_INVALID; 6859 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6860 || ahc->enabled_luns > 0) { 6861 /* 6862 * Only allow our target id to change 6863 * if the initiator role is not configured 6864 * and there are no enabled luns which 6865 * are attached to the currently registered 6866 * scsi id. 6867 */ 6868 status = CAM_TID_INVALID; 6869 } 6870 } else if ((ahc->features & AHC_MULTI_TID) == 0 6871 && ahc->enabled_luns > 0) { 6872 6873 status = CAM_TID_INVALID; 6874 } 6875 } 6876 6877 if (status != CAM_REQ_CMP) { 6878 ccb->ccb_h.status = status; 6879 return; 6880 } 6881 6882 /* 6883 * We now have an id that is valid. 6884 * If we aren't in target mode, switch modes. 6885 */ 6886 if ((ahc->flags & AHC_TARGETROLE) == 0 6887 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6888 u_long s; 6889 ahc_flag saved_flags; 6890 6891 printf("Configuring Target Mode\n"); 6892 ahc_lock(ahc, &s); 6893 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6894 ccb->ccb_h.status = CAM_BUSY; 6895 ahc_unlock(ahc, &s); 6896 return; 6897 } 6898 saved_flags = ahc->flags; 6899 ahc->flags |= AHC_TARGETROLE; 6900 if ((ahc->features & AHC_MULTIROLE) == 0) 6901 ahc->flags &= ~AHC_INITIATORROLE; 6902 ahc_pause(ahc); 6903 error = ahc_loadseq(ahc); 6904 if (error != 0) { 6905 /* 6906 * Restore original configuration and notify 6907 * the caller that we cannot support target mode. 6908 * Since the adapter started out in this 6909 * configuration, the firmware load will succeed, 6910 * so there is no point in checking ahc_loadseq's 6911 * return value. 6912 */ 6913 ahc->flags = saved_flags; 6914 (void)ahc_loadseq(ahc); 6915 ahc_restart(ahc); 6916 ahc_unlock(ahc, &s); 6917 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 6918 return; 6919 } 6920 ahc_restart(ahc); 6921 ahc_unlock(ahc, &s); 6922 } 6923 cel = &ccb->cel; 6924 target = ccb->ccb_h.target_id; 6925 lun = ccb->ccb_h.target_lun; 6926 channel = SIM_CHANNEL(ahc, sim); 6927 target_mask = 0x01 << target; 6928 if (channel == 'B') 6929 target_mask <<= 8; 6930 6931 if (cel->enable != 0) { 6932 u_int scsiseq; 6933 6934 /* Are we already enabled?? */ 6935 if (lstate != NULL) { 6936 xpt_print_path(ccb->ccb_h.path); 6937 printf("Lun already enabled\n"); 6938 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6939 return; 6940 } 6941 6942 if (cel->grp6_len != 0 6943 || cel->grp7_len != 0) { 6944 /* 6945 * Don't (yet?) support vendor 6946 * specific commands. 6947 */ 6948 ccb->ccb_h.status = CAM_REQ_INVALID; 6949 printf("Non-zero Group Codes\n"); 6950 return; 6951 } 6952 6953 /* 6954 * Seems to be okay. 6955 * Setup our data structures. 6956 */ 6957 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 6958 tstate = ahc_alloc_tstate(ahc, target, channel); 6959 if (tstate == NULL) { 6960 xpt_print_path(ccb->ccb_h.path); 6961 printf("Couldn't allocate tstate\n"); 6962 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6963 return; 6964 } 6965 } 6966 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 6967 if (lstate == NULL) { 6968 xpt_print_path(ccb->ccb_h.path); 6969 printf("Couldn't allocate lstate\n"); 6970 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6971 return; 6972 } 6973 memset(lstate, 0, sizeof(*lstate)); 6974 status = xpt_create_path(&lstate->path, /*periph*/NULL, 6975 xpt_path_path_id(ccb->ccb_h.path), 6976 xpt_path_target_id(ccb->ccb_h.path), 6977 xpt_path_lun_id(ccb->ccb_h.path)); 6978 if (status != CAM_REQ_CMP) { 6979 free(lstate, M_DEVBUF); 6980 xpt_print_path(ccb->ccb_h.path); 6981 printf("Couldn't allocate path\n"); 6982 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6983 return; 6984 } 6985 SLIST_INIT(&lstate->accept_tios); 6986 SLIST_INIT(&lstate->immed_notifies); 6987 ahc_lock(ahc, &s); 6988 ahc_pause(ahc); 6989 if (target != CAM_TARGET_WILDCARD) { 6990 tstate->enabled_luns[lun] = lstate; 6991 ahc->enabled_luns++; 6992 6993 if ((ahc->features & AHC_MULTI_TID) != 0) { 6994 u_int targid_mask; 6995 6996 targid_mask = ahc_inb(ahc, TARGID) 6997 | (ahc_inb(ahc, TARGID + 1) << 8); 6998 6999 targid_mask |= target_mask; 7000 ahc_outb(ahc, TARGID, targid_mask); 7001 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 7002 7003 ahc_update_scsiid(ahc, targid_mask); 7004 } else { 7005 u_int our_id; 7006 char channel; 7007 7008 channel = SIM_CHANNEL(ahc, sim); 7009 our_id = SIM_SCSI_ID(ahc, sim); 7010 7011 /* 7012 * This can only happen if selections 7013 * are not enabled 7014 */ 7015 if (target != our_id) { 7016 u_int sblkctl; 7017 char cur_channel; 7018 int swap; 7019 7020 sblkctl = ahc_inb(ahc, SBLKCTL); 7021 cur_channel = (sblkctl & SELBUSB) 7022 ? 'B' : 'A'; 7023 if ((ahc->features & AHC_TWIN) == 0) 7024 cur_channel = 'A'; 7025 swap = cur_channel != channel; 7026 if (channel == 'A') 7027 ahc->our_id = target; 7028 else 7029 ahc->our_id_b = target; 7030 7031 if (swap) 7032 ahc_outb(ahc, SBLKCTL, 7033 sblkctl ^ SELBUSB); 7034 7035 ahc_outb(ahc, SCSIID, target); 7036 7037 if (swap) 7038 ahc_outb(ahc, SBLKCTL, sblkctl); 7039 } 7040 } 7041 } else 7042 ahc->black_hole = lstate; 7043 /* Allow select-in operations */ 7044 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7045 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7046 scsiseq |= ENSELI; 7047 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7048 scsiseq = ahc_inb(ahc, SCSISEQ); 7049 scsiseq |= ENSELI; 7050 ahc_outb(ahc, SCSISEQ, scsiseq); 7051 } 7052 ahc_unpause(ahc); 7053 ahc_unlock(ahc, &s); 7054 ccb->ccb_h.status = CAM_REQ_CMP; 7055 xpt_print_path(ccb->ccb_h.path); 7056 printf("Lun now enabled for target mode\n"); 7057 } else { 7058 struct scb *scb; 7059 int i, empty; 7060 7061 if (lstate == NULL) { 7062 ccb->ccb_h.status = CAM_LUN_INVALID; 7063 return; 7064 } 7065 7066 ahc_lock(ahc, &s); 7067 7068 ccb->ccb_h.status = CAM_REQ_CMP; 7069 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7070 struct ccb_hdr *ccbh; 7071 7072 ccbh = &scb->io_ctx->ccb_h; 7073 if (ccbh->func_code == XPT_CONT_TARGET_IO 7074 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7075 printf("CTIO pending\n"); 7076 ccb->ccb_h.status = CAM_REQ_INVALID; 7077 ahc_unlock(ahc, &s); 7078 return; 7079 } 7080 } 7081 7082 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7083 printf("ATIOs pending\n"); 7084 ccb->ccb_h.status = CAM_REQ_INVALID; 7085 } 7086 7087 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7088 printf("INOTs pending\n"); 7089 ccb->ccb_h.status = CAM_REQ_INVALID; 7090 } 7091 7092 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7093 ahc_unlock(ahc, &s); 7094 return; 7095 } 7096 7097 xpt_print_path(ccb->ccb_h.path); 7098 printf("Target mode disabled\n"); 7099 xpt_free_path(lstate->path); 7100 free(lstate, M_DEVBUF); 7101 7102 ahc_pause(ahc); 7103 /* Can we clean up the target too? */ 7104 if (target != CAM_TARGET_WILDCARD) { 7105 tstate->enabled_luns[lun] = NULL; 7106 ahc->enabled_luns--; 7107 for (empty = 1, i = 0; i < 8; i++) 7108 if (tstate->enabled_luns[i] != NULL) { 7109 empty = 0; 7110 break; 7111 } 7112 7113 if (empty) { 7114 ahc_free_tstate(ahc, target, channel, 7115 /*force*/FALSE); 7116 if (ahc->features & AHC_MULTI_TID) { 7117 u_int targid_mask; 7118 7119 targid_mask = ahc_inb(ahc, TARGID) 7120 | (ahc_inb(ahc, TARGID + 1) 7121 << 8); 7122 7123 targid_mask &= ~target_mask; 7124 ahc_outb(ahc, TARGID, targid_mask); 7125 ahc_outb(ahc, TARGID+1, 7126 (targid_mask >> 8)); 7127 ahc_update_scsiid(ahc, targid_mask); 7128 } 7129 } 7130 } else { 7131 7132 ahc->black_hole = NULL; 7133 7134 /* 7135 * We can't allow selections without 7136 * our black hole device. 7137 */ 7138 empty = TRUE; 7139 } 7140 if (ahc->enabled_luns == 0) { 7141 /* Disallow select-in */ 7142 u_int scsiseq; 7143 7144 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7145 scsiseq &= ~ENSELI; 7146 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7147 scsiseq = ahc_inb(ahc, SCSISEQ); 7148 scsiseq &= ~ENSELI; 7149 ahc_outb(ahc, SCSISEQ, scsiseq); 7150 7151 if ((ahc->features & AHC_MULTIROLE) == 0) { 7152 printf("Configuring Initiator Mode\n"); 7153 ahc->flags &= ~AHC_TARGETROLE; 7154 ahc->flags |= AHC_INITIATORROLE; 7155 /* 7156 * Returning to a configuration that 7157 * fit previously will always succeed. 7158 */ 7159 (void)ahc_loadseq(ahc); 7160 ahc_restart(ahc); 7161 /* 7162 * Unpaused. The extra unpause 7163 * that follows is harmless. 7164 */ 7165 } 7166 } 7167 ahc_unpause(ahc); 7168 ahc_unlock(ahc, &s); 7169 } 7170 } 7171 7172 static void 7173 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7174 { 7175 u_int scsiid_mask; 7176 u_int scsiid; 7177 7178 if ((ahc->features & AHC_MULTI_TID) == 0) 7179 panic("ahc_update_scsiid called on non-multitid unit\n"); 7180 7181 /* 7182 * Since we will rely on the TARGID mask 7183 * for selection enables, ensure that OID 7184 * in SCSIID is not set to some other ID 7185 * that we don't want to allow selections on. 7186 */ 7187 if ((ahc->features & AHC_ULTRA2) != 0) 7188 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7189 else 7190 scsiid = ahc_inb(ahc, SCSIID); 7191 scsiid_mask = 0x1 << (scsiid & OID); 7192 if ((targid_mask & scsiid_mask) == 0) { 7193 u_int our_id; 7194 7195 /* ffs counts from 1 */ 7196 our_id = ffs(targid_mask); 7197 if (our_id == 0) 7198 our_id = ahc->our_id; 7199 else 7200 our_id--; 7201 scsiid &= TID; 7202 scsiid |= our_id; 7203 } 7204 if ((ahc->features & AHC_ULTRA2) != 0) 7205 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7206 else 7207 ahc_outb(ahc, SCSIID, scsiid); 7208 } 7209 7210 void 7211 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7212 { 7213 struct target_cmd *cmd; 7214 7215 /* 7216 * If the card supports auto-access pause, 7217 * we can access the card directly regardless 7218 * of whether it is paused or not. 7219 */ 7220 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7221 paused = TRUE; 7222 7223 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7224 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7225 7226 /* 7227 * Only advance through the queue if we 7228 * have the resources to process the command. 7229 */ 7230 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7231 break; 7232 7233 cmd->cmd_valid = 0; 7234 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 7235 ahc->shared_data_dmamap, 7236 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7237 sizeof(struct target_cmd), 7238 BUS_DMASYNC_PREREAD); 7239 ahc->tqinfifonext++; 7240 7241 /* 7242 * Lazily update our position in the target mode incoming 7243 * command queue as seen by the sequencer. 7244 */ 7245 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7246 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7247 u_int hs_mailbox; 7248 7249 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7250 hs_mailbox &= ~HOST_TQINPOS; 7251 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7252 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7253 } else { 7254 if (!paused) 7255 ahc_pause(ahc); 7256 ahc_outb(ahc, KERNEL_TQINPOS, 7257 ahc->tqinfifonext & HOST_TQINPOS); 7258 if (!paused) 7259 ahc_unpause(ahc); 7260 } 7261 } 7262 } 7263 } 7264 7265 static int 7266 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7267 { 7268 struct ahc_tmode_tstate *tstate; 7269 struct ahc_tmode_lstate *lstate; 7270 struct ccb_accept_tio *atio; 7271 uint8_t *byte; 7272 int initiator; 7273 int target; 7274 int lun; 7275 7276 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7277 target = SCSIID_OUR_ID(cmd->scsiid); 7278 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7279 7280 byte = cmd->bytes; 7281 tstate = ahc->enabled_targets[target]; 7282 lstate = NULL; 7283 if (tstate != NULL) 7284 lstate = tstate->enabled_luns[lun]; 7285 7286 /* 7287 * Commands for disabled luns go to the black hole driver. 7288 */ 7289 if (lstate == NULL) 7290 lstate = ahc->black_hole; 7291 7292 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7293 if (atio == NULL) { 7294 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7295 /* 7296 * Wait for more ATIOs from the peripheral driver for this lun. 7297 */ 7298 if (bootverbose) 7299 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7300 return (1); 7301 } else 7302 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7303 #if 0 7304 printf("Incoming command from %d for %d:%d%s\n", 7305 initiator, target, lun, 7306 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7307 #endif 7308 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7309 7310 if (lstate == ahc->black_hole) { 7311 /* Fill in the wildcards */ 7312 atio->ccb_h.target_id = target; 7313 atio->ccb_h.target_lun = lun; 7314 } 7315 7316 /* 7317 * Package it up and send it off to 7318 * whomever has this lun enabled. 7319 */ 7320 atio->sense_len = 0; 7321 atio->init_id = initiator; 7322 if (byte[0] != 0xFF) { 7323 /* Tag was included */ 7324 atio->tag_action = *byte++; 7325 atio->tag_id = *byte++; 7326 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7327 } else { 7328 atio->ccb_h.flags = 0; 7329 } 7330 byte++; 7331 7332 /* Okay. Now determine the cdb size based on the command code */ 7333 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7334 case 0: 7335 atio->cdb_len = 6; 7336 break; 7337 case 1: 7338 case 2: 7339 atio->cdb_len = 10; 7340 break; 7341 case 4: 7342 atio->cdb_len = 16; 7343 break; 7344 case 5: 7345 atio->cdb_len = 12; 7346 break; 7347 case 3: 7348 default: 7349 /* Only copy the opcode. */ 7350 atio->cdb_len = 1; 7351 printf("Reserved or VU command code type encountered\n"); 7352 break; 7353 } 7354 7355 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7356 7357 atio->ccb_h.status |= CAM_CDB_RECVD; 7358 7359 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7360 /* 7361 * We weren't allowed to disconnect. 7362 * We're hanging on the bus until a 7363 * continue target I/O comes in response 7364 * to this accept tio. 7365 */ 7366 #if 0 7367 printf("Received Immediate Command %d:%d:%d - %p\n", 7368 initiator, target, lun, ahc->pending_device); 7369 #endif 7370 ahc->pending_device = lstate; 7371 ahc_freeze_ccb((union ccb *)atio); 7372 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7373 } 7374 xpt_done((union ccb*)atio); 7375 return (0); 7376 } 7377 7378 #endif 7379