1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $FreeBSD$ 41 */ 42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $" 43 44/* 45 * This file is processed by the aic7xxx_asm utility for use in assembling 46 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 47 * a C header file for use in the kernel portion of the Aic7xxx driver. 48 * 49 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 50 * Adaptec's Technical Documents Department 1-800-934-2766 51 */ 52 53/* 54 * SCSI Sequence Control (p. 3-11). 55 * Each bit, when set starts a specific SCSI sequence on the bus 56 */ 57register SCSISEQ { 58 address 0x000 59 access_mode RW 60 field TEMODE 0x80 61 field ENSELO 0x40 62 field ENSELI 0x20 63 field ENRSELI 0x10 64 field ENAUTOATNO 0x08 65 field ENAUTOATNI 0x04 66 field ENAUTOATNP 0x02 67 field SCSIRSTO 0x01 68} 69 70/* 71 * SCSI Transfer Control 0 Register (pp. 3-13). 72 * Controls the SCSI module data path. 73 */ 74register SXFRCTL0 { 75 address 0x001 76 access_mode RW 77 field DFON 0x80 78 field DFPEXP 0x40 79 field FAST20 0x20 80 field CLRSTCNT 0x10 81 field SPIOEN 0x08 82 field SCAMEN 0x04 83 field CLRCHN 0x02 84} 85 86/* 87 * SCSI Transfer Control 1 Register (pp. 3-14,15). 88 * Controls the SCSI module data path. 89 */ 90register SXFRCTL1 { 91 address 0x002 92 access_mode RW 93 field BITBUCKET 0x80 94 field SWRAPEN 0x40 95 field ENSPCHK 0x20 96 mask STIMESEL 0x18 97 field ENSTIMER 0x04 98 field ACTNEGEN 0x02 99 field STPWEN 0x01 /* Powered Termination */ 100} 101 102/* 103 * SCSI Control Signal Read Register (p. 3-15). 104 * Reads the actual state of the SCSI bus pins 105 */ 106register SCSISIGI { 107 address 0x003 108 access_mode RO 109 field CDI 0x80 110 field IOI 0x40 111 field MSGI 0x20 112 field ATNI 0x10 113 field SELI 0x08 114 field BSYI 0x04 115 field REQI 0x02 116 field ACKI 0x01 117/* 118 * Possible phases in SCSISIGI 119 */ 120 mask PHASE_MASK CDI|IOI|MSGI 121 mask P_DATAOUT 0x00 122 mask P_DATAIN IOI 123 mask P_DATAOUT_DT P_DATAOUT|MSGI 124 mask P_DATAIN_DT P_DATAIN|MSGI 125 mask P_COMMAND CDI 126 mask P_MESGOUT CDI|MSGI 127 mask P_STATUS CDI|IOI 128 mask P_MESGIN CDI|IOI|MSGI 129} 130 131/* 132 * SCSI Control Signal Write Register (p. 3-16). 133 * Writing to this register modifies the control signals on the bus. Only 134 * those signals that are allowed in the current mode (Initiator/Target) are 135 * asserted. 136 */ 137register SCSISIGO { 138 address 0x003 139 access_mode WO 140 field CDO 0x80 141 field IOO 0x40 142 field MSGO 0x20 143 field ATNO 0x10 144 field SELO 0x08 145 field BSYO 0x04 146 field REQO 0x02 147 field ACKO 0x01 148/* 149 * Possible phases to write into SCSISIG0 150 */ 151 mask PHASE_MASK CDI|IOI|MSGI 152 mask P_DATAOUT 0x00 153 mask P_DATAIN IOI 154 mask P_COMMAND CDI 155 mask P_MESGOUT CDI|MSGI 156 mask P_STATUS CDI|IOI 157 mask P_MESGIN CDI|IOI|MSGI 158} 159 160/* 161 * SCSI Rate Control (p. 3-17). 162 * Contents of this register determine the Synchronous SCSI data transfer 163 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 164 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 165 * greater than 0 enables synchronous transfers. 166 */ 167register SCSIRATE { 168 address 0x004 169 access_mode RW 170 field WIDEXFER 0x80 /* Wide transfer control */ 171 field ENABLE_CRC 0x40 /* CRC for D-Phases */ 172 field SINGLE_EDGE 0x10 /* Disable DT Transfers */ 173 mask SXFR 0x70 /* Sync transfer rate */ 174 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 175 mask SOFS 0x0f /* Sync offset */ 176} 177 178/* 179 * SCSI ID (p. 3-18). 180 * Contains the ID of the board and the current target on the 181 * selected channel. 182 */ 183register SCSIID { 184 address 0x005 185 access_mode RW 186 mask TID 0xf0 /* Target ID mask */ 187 mask TWIN_TID 0x70 188 field TWIN_CHNLB 0x80 189 mask OID 0x0f /* Our ID mask */ 190 /* 191 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 192 * The aic7890/91 allow an offset of up to 127 transfers in both wide 193 * and narrow mode. 194 */ 195 alias SCSIOFFSET 196 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 197} 198 199/* 200 * SCSI Latched Data (p. 3-19). 201 * Read/Write latches used to transfer data on the SCSI bus during 202 * Automatic or Manual PIO mode. SCSIDATH can be used for the 203 * upper byte of a 16bit wide asynchronouse data phase transfer. 204 */ 205register SCSIDATL { 206 address 0x006 207 access_mode RW 208} 209 210register SCSIDATH { 211 address 0x007 212 access_mode RW 213} 214 215/* 216 * SCSI Transfer Count (pp. 3-19,20) 217 * These registers count down the number of bytes transferred 218 * across the SCSI bus. The counter is decremented only once 219 * the data has been safely transferred. SDONE in SSTAT0 is 220 * set when STCNT goes to 0 221 */ 222register STCNT { 223 address 0x008 224 size 3 225 access_mode RW 226} 227 228/* ALT_MODE registers (Ultra2 and Ultra160 chips) */ 229register SXFRCTL2 { 230 address 0x013 231 access_mode RW 232 field AUTORSTDIS 0x10 233 field CMDDMAEN 0x08 234 mask ASYNC_SETUP 0x07 235} 236 237/* ALT_MODE register on Ultra160 chips */ 238register OPTIONMODE { 239 address 0x008 240 access_mode RW 241 count 2 242 field AUTORATEEN 0x80 243 field AUTOACKEN 0x40 244 field ATNMGMNTEN 0x20 245 field BUSFREEREV 0x10 246 field EXPPHASEDIS 0x08 247 field SCSIDATL_IMGEN 0x04 248 field AUTO_MSGOUT_DE 0x02 249 field DIS_MSGIN_DUALEDGE 0x01 250 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 251} 252 253/* ALT_MODE register on Ultra160 chips */ 254register TARGCRCCNT { 255 address 0x00a 256 size 2 257 access_mode RW 258 count 2 259} 260 261/* 262 * Clear SCSI Interrupt 0 (p. 3-20) 263 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 264 */ 265register CLRSINT0 { 266 address 0x00b 267 access_mode WO 268 field CLRSELDO 0x40 269 field CLRSELDI 0x20 270 field CLRSELINGO 0x10 271 field CLRSWRAP 0x08 272 field CLRIOERR 0x08 /* Ultra2 Only */ 273 field CLRSPIORDY 0x02 274} 275 276/* 277 * SCSI Status 0 (p. 3-21) 278 * Contains one set of SCSI Interrupt codes 279 * These are most likely of interest to the sequencer 280 */ 281register SSTAT0 { 282 address 0x00b 283 access_mode RO 284 field TARGET 0x80 /* Board acting as target */ 285 field SELDO 0x40 /* Selection Done */ 286 field SELDI 0x20 /* Board has been selected */ 287 field SELINGO 0x10 /* Selection In Progress */ 288 field SWRAP 0x08 /* 24bit counter wrap */ 289 field IOERR 0x08 /* LVD Tranceiver mode changed */ 290 field SDONE 0x04 /* STCNT = 0x000000 */ 291 field SPIORDY 0x02 /* SCSI PIO Ready */ 292 field DMADONE 0x01 /* DMA transfer completed */ 293} 294 295/* 296 * Clear SCSI Interrupt 1 (p. 3-23) 297 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 298 */ 299register CLRSINT1 { 300 address 0x00c 301 access_mode WO 302 field CLRSELTIMEO 0x80 303 field CLRATNO 0x40 304 field CLRSCSIRSTI 0x20 305 field CLRBUSFREE 0x08 306 field CLRSCSIPERR 0x04 307 field CLRPHASECHG 0x02 308 field CLRREQINIT 0x01 309} 310 311/* 312 * SCSI Status 1 (p. 3-24) 313 */ 314register SSTAT1 { 315 address 0x00c 316 access_mode RO 317 field SELTO 0x80 318 field ATNTARG 0x40 319 field SCSIRSTI 0x20 320 field PHASEMIS 0x10 321 field BUSFREE 0x08 322 field SCSIPERR 0x04 323 field PHASECHG 0x02 324 field REQINIT 0x01 325} 326 327/* 328 * SCSI Status 2 (pp. 3-25,26) 329 */ 330register SSTAT2 { 331 address 0x00d 332 access_mode RO 333 field OVERRUN 0x80 334 field SHVALID 0x40 /* Shaddow Layer non-zero */ 335 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 336 field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 337 field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 338 field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 339 field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 340 mask SFCNT 0x1f 341} 342 343/* 344 * SCSI Status 3 (p. 3-26) 345 */ 346register SSTAT3 { 347 address 0x00e 348 access_mode RO 349 count 2 350 mask SCSICNT 0xf0 351 mask OFFCNT 0x0f 352 mask U2OFFCNT 0x7f 353} 354 355/* 356 * SCSI ID for the aic7890/91 chips 357 */ 358register SCSIID_ULTRA2 { 359 address 0x00f 360 access_mode RW 361 mask TID 0xf0 /* Target ID mask */ 362 mask OID 0x0f /* Our ID mask */ 363} 364 365/* 366 * SCSI Interrupt Mode 1 (p. 3-28) 367 * Setting any bit will enable the corresponding function 368 * in SIMODE0 to interrupt via the IRQ pin. 369 */ 370register SIMODE0 { 371 address 0x010 372 access_mode RW 373 count 2 374 field ENSELDO 0x40 375 field ENSELDI 0x20 376 field ENSELINGO 0x10 377 field ENSWRAP 0x08 378 field ENIOERR 0x08 /* LVD Tranceiver mode changes */ 379 field ENSDONE 0x04 380 field ENSPIORDY 0x02 381 field ENDMADONE 0x01 382} 383 384/* 385 * SCSI Interrupt Mode 1 (pp. 3-28,29) 386 * Setting any bit will enable the corresponding function 387 * in SIMODE1 to interrupt via the IRQ pin. 388 */ 389register SIMODE1 { 390 address 0x011 391 access_mode RW 392 field ENSELTIMO 0x80 393 field ENATNTARG 0x40 394 field ENSCSIRST 0x20 395 field ENPHASEMIS 0x10 396 field ENBUSFREE 0x08 397 field ENSCSIPERR 0x04 398 field ENPHASECHG 0x02 399 field ENREQINIT 0x01 400} 401 402/* 403 * SCSI Data Bus (High) (p. 3-29) 404 * This register reads data on the SCSI Data bus directly. 405 */ 406register SCSIBUSL { 407 address 0x012 408 access_mode RW 409} 410 411register SCSIBUSH { 412 address 0x013 413 access_mode RW 414} 415 416/* 417 * SCSI/Host Address (p. 3-30) 418 * These registers hold the host address for the byte about to be 419 * transferred on the SCSI bus. They are counted up in the same 420 * manner as STCNT is counted down. SHADDR should always be used 421 * to determine the address of the last byte transferred since HADDR 422 * can be skewed by write ahead. 423 */ 424register SHADDR { 425 address 0x014 426 size 4 427 access_mode RO 428} 429 430/* 431 * Selection Timeout Timer (p. 3-30) 432 */ 433register SELTIMER { 434 address 0x018 435 access_mode RW 436 count 1 437 field STAGE6 0x20 438 field STAGE5 0x10 439 field STAGE4 0x08 440 field STAGE3 0x04 441 field STAGE2 0x02 442 field STAGE1 0x01 443 alias TARGIDIN 444} 445 446/* 447 * Selection/Reselection ID (p. 3-31) 448 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 449 * device did not set its own ID. 450 */ 451register SELID { 452 address 0x019 453 access_mode RW 454 mask SELID_MASK 0xf0 455 field ONEBIT 0x08 456} 457 458register SCAMCTL { 459 address 0x01a 460 access_mode RW 461 field ENSCAMSELO 0x80 462 field CLRSCAMSELID 0x40 463 field ALTSTIM 0x20 464 field DFLTTID 0x10 465 mask SCAMLVL 0x03 466} 467 468/* 469 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 470 */ 471register TARGID { 472 address 0x01b 473 size 2 474 access_mode RW 475 count 14 476} 477 478/* 479 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 480 * Indicates if external logic has been attached to the chip to 481 * perform the tasks of accessing a serial eeprom, testing termination 482 * strength, and performing cable detection. On the aic7860, most of 483 * these features are handled on chip, but on the aic7855 an attached 484 * aic3800 does the grunt work. 485 */ 486register SPIOCAP { 487 address 0x01b 488 access_mode RW 489 count 10 490 field SOFT1 0x80 491 field SOFT0 0x40 492 field SOFTCMDEN 0x20 493 field EXT_BRDCTL 0x10 /* External Board control */ 494 field SEEPROM 0x08 /* External serial eeprom logic */ 495 field EEPROM 0x04 /* Writable external BIOS ROM */ 496 field ROM 0x02 /* Logic for accessing external ROM */ 497 field SSPIOCPS 0x01 /* Termination and cable detection */ 498} 499 500register BRDCTL { 501 address 0x01d 502 count 11 503 field BRDDAT7 0x80 504 field BRDDAT6 0x40 505 field BRDDAT5 0x20 506 field BRDSTB 0x10 507 field BRDCS 0x08 508 field BRDRW 0x04 509 field BRDCTL1 0x02 510 field BRDCTL0 0x01 511 /* 7890 Definitions */ 512 field BRDDAT4 0x10 513 field BRDDAT3 0x08 514 field BRDDAT2 0x04 515 field BRDRW_ULTRA2 0x02 516 field BRDSTB_ULTRA2 0x01 517} 518 519/* 520 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 521 * Controls the reading and writing of an external serial 1-bit 522 * EEPROM Device. In order to access the serial EEPROM, you must 523 * first set the SEEMS bit that generates a request to the memory 524 * port for access to the serial EEPROM device. When the memory 525 * port is not busy servicing another request, it reconfigures 526 * to allow access to the serial EEPROM. When this happens, SEERDY 527 * gets set high to verify that the memory port access has been 528 * granted. 529 * 530 * After successful arbitration for the memory port, the SEECS bit of 531 * the SEECTL register is connected to the chip select. The SEECK, 532 * SEEDO, and SEEDI are connected to the clock, data out, and data in 533 * lines respectively. The SEERDY bit of SEECTL is useful in that it 534 * gives us an 800 nsec timer. After a write to the SEECTL register, 535 * the SEERDY goes high 800 nsec later. The one exception to this is 536 * when we first request access to the memory port. The SEERDY goes 537 * high to signify that access has been granted and, for this case, has 538 * no implied timing. 539 * 540 * See 93cx6.c for detailed information on the protocol necessary to 541 * read the serial EEPROM. 542 */ 543register SEECTL { 544 address 0x01e 545 count 11 546 field EXTARBACK 0x80 547 field EXTARBREQ 0x40 548 field SEEMS 0x20 549 field SEERDY 0x10 550 field SEECS 0x08 551 field SEECK 0x04 552 field SEEDO 0x02 553 field SEEDI 0x01 554} 555/* 556 * SCSI Block Control (p. 3-32) 557 * Controls Bus type and channel selection. In a twin channel configuration 558 * addresses 0x00-0x1e are gated to the appropriate channel based on this 559 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 560 * on a wide bus. 561 */ 562register SBLKCTL { 563 address 0x01f 564 access_mode RW 565 field DIAGLEDEN 0x80 /* Aic78X0 only */ 566 field DIAGLEDON 0x40 /* Aic78X0 only */ 567 field AUTOFLUSHDIS 0x20 568 field SELBUSB 0x08 569 field ENAB40 0x08 /* LVD transceiver active */ 570 field ENAB20 0x04 /* SE/HVD transceiver active */ 571 field SELWIDE 0x02 572 field XCVR 0x01 /* External transceiver active */ 573} 574 575/* 576 * Sequencer Control (p. 3-33) 577 * Error detection mode and speed configuration 578 */ 579register SEQCTL { 580 address 0x060 581 access_mode RW 582 count 15 583 field PERRORDIS 0x80 584 field PAUSEDIS 0x40 585 field FAILDIS 0x20 586 field FASTMODE 0x10 587 field BRKADRINTEN 0x08 588 field STEP 0x04 589 field SEQRESET 0x02 590 field LOADRAM 0x01 591} 592 593/* 594 * Sequencer RAM Data (p. 3-34) 595 * Single byte window into the Scratch Ram area starting at the address 596 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 597 * four bytes in succession. The SEQADDRs will increment after the most 598 * significant byte is written 599 */ 600register SEQRAM { 601 address 0x061 602 access_mode RW 603 count 2 604} 605 606/* 607 * Sequencer Address Registers (p. 3-35) 608 * Only the first bit of SEQADDR1 holds addressing information 609 */ 610register SEQADDR0 { 611 address 0x062 612 access_mode RW 613} 614 615register SEQADDR1 { 616 address 0x063 617 access_mode RW 618 count 8 619 mask SEQADDR1_MASK 0x01 620} 621 622/* 623 * Accumulator 624 * We cheat by passing arguments in the Accumulator up to the kernel driver 625 */ 626register ACCUM { 627 address 0x064 628 access_mode RW 629 accumulator 630} 631 632register SINDEX { 633 address 0x065 634 access_mode RW 635 sindex 636} 637 638register DINDEX { 639 address 0x066 640 access_mode RW 641} 642 643register ALLONES { 644 address 0x069 645 access_mode RO 646 allones 647} 648 649register ALLZEROS { 650 address 0x06a 651 access_mode RO 652 allzeros 653} 654 655register NONE { 656 address 0x06a 657 access_mode WO 658 none 659} 660 661register FLAGS { 662 address 0x06b 663 access_mode RO 664 count 18 665 field ZERO 0x02 666 field CARRY 0x01 667} 668 669register SINDIR { 670 address 0x06c 671 access_mode RO 672} 673 674register DINDIR { 675 address 0x06d 676 access_mode WO 677} 678 679register FUNCTION1 { 680 address 0x06e 681 access_mode RW 682} 683 684register STACK { 685 address 0x06f 686 access_mode RO 687 count 5 688} 689 690const STACK_SIZE 4 691 692/* 693 * Board Control (p. 3-43) 694 */ 695register BCTL { 696 address 0x084 697 access_mode RW 698 field ACE 0x08 699 field ENABLE 0x01 700} 701 702/* 703 * On the aic78X0 chips, Board Control is replaced by the DSCommand 704 * register (p. 4-64) 705 */ 706register DSCOMMAND0 { 707 address 0x084 708 access_mode RW 709 count 7 710 field CACHETHEN 0x80 /* Cache Threshold enable */ 711 field DPARCKEN 0x40 /* Data Parity Check Enable */ 712 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 713 field EXTREQLCK 0x10 /* External Request Lock */ 714 /* aic7890/91/96/97 only */ 715 field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 716 field RAMPS 0x04 /* External SCB RAM Present */ 717 field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 718 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 719} 720 721register DSCOMMAND1 { 722 address 0x085 723 access_mode RW 724 mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */ 725 field HADDLDSEL1 0x02 /* Host Address Load Select Bits */ 726 field HADDLDSEL0 0x01 727} 728 729/* 730 * Bus On/Off Time (p. 3-44) aic7770 only 731 */ 732register BUSTIME { 733 address 0x085 734 access_mode RW 735 count 2 736 mask BOFF 0xf0 737 mask BON 0x0f 738} 739 740/* 741 * Bus Speed (p. 3-45) aic7770 only 742 */ 743register BUSSPD { 744 address 0x086 745 access_mode RW 746 count 2 747 mask DFTHRSH 0xc0 748 mask STBOFF 0x38 749 mask STBON 0x07 750 mask DFTHRSH_100 0xc0 751 mask DFTHRSH_75 0x80 752} 753 754/* aic7850/55/60/70/80/95 only */ 755register DSPCISTATUS { 756 address 0x086 757 count 4 758 mask DFTHRSH_100 0xc0 759} 760 761/* aic7890/91/96/97 only */ 762register HS_MAILBOX { 763 address 0x086 764 mask HOST_MAILBOX 0xF0 765 mask SEQ_MAILBOX 0x0F 766 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 767} 768 769const HOST_MAILBOX_SHIFT 4 770const SEQ_MAILBOX_SHIFT 0 771 772/* 773 * Host Control (p. 3-47) R/W 774 * Overall host control of the device. 775 */ 776register HCNTRL { 777 address 0x087 778 access_mode RW 779 count 14 780 field POWRDN 0x40 781 field SWINT 0x10 782 field IRQMS 0x08 783 field PAUSE 0x04 784 field INTEN 0x02 785 field CHIPRST 0x01 786 field CHIPRSTACK 0x01 787} 788 789/* 790 * Host Address (p. 3-48) 791 * This register contains the address of the byte about 792 * to be transferred across the host bus. 793 */ 794register HADDR { 795 address 0x088 796 size 4 797 access_mode RW 798} 799 800register HCNT { 801 address 0x08c 802 size 3 803 access_mode RW 804} 805 806/* 807 * SCB Pointer (p. 3-49) 808 * Gate one of the SCBs into the SCBARRAY window. 809 */ 810register SCBPTR { 811 address 0x090 812 access_mode RW 813} 814 815/* 816 * Interrupt Status (p. 3-50) 817 * Status for system interrupts 818 */ 819register INTSTAT { 820 address 0x091 821 access_mode RW 822 field BRKADRINT 0x08 823 field SCSIINT 0x04 824 field CMDCMPLT 0x02 825 field SEQINT 0x01 826 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 827 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 828 mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */ 829 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 830 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 831 mask PDATA_REINIT 0x50|SEQINT /* 832 * Returned to data phase 833 * that requires data 834 * transfer pointers to be 835 * recalculated from the 836 * transfer residual. 837 */ 838 mask HOST_MSG_LOOP 0x60|SEQINT /* 839 * The bus is ready for the 840 * host to perform another 841 * message transaction. This 842 * mechanism is used for things 843 * like sync/wide negotiation 844 * that require a kernel based 845 * message state engine. 846 */ 847 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 848 mask PERR_DETECTED 0x80|SEQINT /* 849 * Either the phase_lock 850 * or inb_next routine has 851 * noticed a parity error. 852 */ 853 mask DATA_OVERRUN 0x90|SEQINT /* 854 * Target attempted to write 855 * beyond the bounds of its 856 * command. 857 */ 858 mask MKMSG_FAILED 0xa0|SEQINT /* 859 * Target completed command 860 * without honoring our ATN 861 * request to issue a message. 862 */ 863 mask MISSED_BUSFREE 0xb0|SEQINT /* 864 * The sequencer never saw 865 * the bus go free after 866 * either a command complete 867 * or disconnect message. 868 */ 869 mask SCB_MISMATCH 0xc0|SEQINT /* 870 * Downloaded SCB's tag does 871 * not match the entry we 872 * intended to download. 873 */ 874 mask NO_FREE_SCB 0xd0|SEQINT /* 875 * get_free_or_disc_scb failed. 876 */ 877 mask OUT_OF_RANGE 0xe0|SEQINT 878 879 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 880 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 881} 882 883/* 884 * Hard Error (p. 3-53) 885 * Reporting of catastrophic errors. You usually cannot recover from 886 * these without a full board reset. 887 */ 888register ERROR { 889 address 0x092 890 access_mode RO 891 count 26 892 field CIOPARERR 0x80 /* Ultra2 only */ 893 field PCIERRSTAT 0x40 /* PCI only */ 894 field MPARERR 0x20 /* PCI only */ 895 field DPARERR 0x10 /* PCI only */ 896 field SQPARERR 0x08 897 field ILLOPCODE 0x04 898 field ILLSADDR 0x02 899 field ILLHADDR 0x01 900} 901 902/* 903 * Clear Interrupt Status (p. 3-52) 904 */ 905register CLRINT { 906 address 0x092 907 access_mode WO 908 count 24 909 field CLRPARERR 0x10 /* PCI only */ 910 field CLRBRKADRINT 0x08 911 field CLRSCSIINT 0x04 912 field CLRCMDINT 0x02 913 field CLRSEQINT 0x01 914} 915 916register DFCNTRL { 917 address 0x093 918 access_mode RW 919 field PRELOADEN 0x80 /* aic7890 only */ 920 field WIDEODD 0x40 921 field SCSIEN 0x20 922 field SDMAEN 0x10 923 field SDMAENACK 0x10 924 field HDMAEN 0x08 925 field HDMAENACK 0x08 926 field DIRECTION 0x04 927 field FIFOFLUSH 0x02 928 field FIFORESET 0x01 929} 930 931register DFSTATUS { 932 address 0x094 933 access_mode RO 934 field PRELOAD_AVAIL 0x80 935 field DFCACHETH 0x40 936 field FIFOQWDEMP 0x20 937 field MREQPEND 0x10 938 field HDONE 0x08 939 field DFTHRESH 0x04 940 field FIFOFULL 0x02 941 field FIFOEMP 0x01 942} 943 944register DFWADDR { 945 address 0x95 946 access_mode RW 947} 948 949register DFRADDR { 950 address 0x97 951 access_mode RW 952} 953 954register DFDAT { 955 address 0x099 956 access_mode RW 957} 958 959/* 960 * SCB Auto Increment (p. 3-59) 961 * Byte offset into the SCB Array and an optional bit to allow auto 962 * incrementing of the address during download and upload operations 963 */ 964register SCBCNT { 965 address 0x09a 966 access_mode RW 967 count 1 968 field SCBAUTO 0x80 969 mask SCBCNT_MASK 0x1f 970} 971 972/* 973 * Queue In FIFO (p. 3-60) 974 * Input queue for queued SCBs (commands that the seqencer has yet to start) 975 */ 976register QINFIFO { 977 address 0x09b 978 access_mode RW 979 count 12 980} 981 982/* 983 * Queue In Count (p. 3-60) 984 * Number of queued SCBs 985 */ 986register QINCNT { 987 address 0x09c 988 access_mode RO 989} 990 991/* 992 * Queue Out FIFO (p. 3-61) 993 * Queue of SCBs that have completed and await the host 994 */ 995register QOUTFIFO { 996 address 0x09d 997 access_mode WO 998 count 7 999} 1000 1001register CRCCONTROL1 { 1002 address 0x09d 1003 access_mode RW 1004 count 3 1005 field CRCONSEEN 0x80 1006 field CRCVALCHKEN 0x40 1007 field CRCENDCHKEN 0x20 1008 field CRCREQCHKEN 0x10 1009 field TARGCRCENDEN 0x08 1010 field TARGCRCCNTEN 0x04 1011} 1012 1013 1014/* 1015 * Queue Out Count (p. 3-61) 1016 * Number of queued SCBs in the Out FIFO 1017 */ 1018register QOUTCNT { 1019 address 0x09e 1020 access_mode RO 1021} 1022 1023register SCSIPHASE { 1024 address 0x09e 1025 access_mode RO 1026 field STATUS_PHASE 0x20 1027 field COMMAND_PHASE 0x10 1028 field MSG_IN_PHASE 0x08 1029 field MSG_OUT_PHASE 0x04 1030 field DATA_IN_PHASE 0x02 1031 field DATA_OUT_PHASE 0x01 1032 mask DATA_PHASE_MASK 0x03 1033} 1034 1035/* 1036 * Special Function 1037 */ 1038register SFUNCT { 1039 address 0x09f 1040 access_mode RW 1041 count 4 1042 field ALT_MODE 0x80 1043} 1044 1045/* 1046 * SCB Definition (p. 5-4) 1047 */ 1048scb { 1049 address 0x0a0 1050 size 64 1051 1052 SCB_CDB_PTR { 1053 size 4 1054 alias SCB_RESIDUAL_DATACNT 1055 alias SCB_CDB_STORE 1056 } 1057 SCB_RESIDUAL_SGPTR { 1058 size 4 1059 } 1060 SCB_SCSI_STATUS { 1061 size 1 1062 } 1063 SCB_TARGET_PHASES { 1064 size 1 1065 } 1066 SCB_TARGET_DATA_DIR { 1067 size 1 1068 } 1069 SCB_TARGET_ITAG { 1070 size 1 1071 } 1072 SCB_DATAPTR { 1073 size 4 1074 } 1075 SCB_DATACNT { 1076 /* 1077 * The last byte is really the high address bits for 1078 * the data address. 1079 */ 1080 size 4 1081 field SG_LAST_SEG 0x80 /* In the fourth byte */ 1082 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 1083 } 1084 SCB_SGPTR { 1085 size 4 1086 field SG_RESID_VALID 0x04 /* In the first byte */ 1087 field SG_FULL_RESID 0x02 /* In the first byte */ 1088 field SG_LIST_NULL 0x01 /* In the first byte */ 1089 } 1090 SCB_CONTROL { 1091 size 1 1092 field TARGET_SCB 0x80 1093 field STATUS_RCVD 0x80 1094 field DISCENB 0x40 1095 field TAG_ENB 0x20 1096 field MK_MESSAGE 0x10 1097 field ULTRAENB 0x08 1098 field DISCONNECTED 0x04 1099 mask SCB_TAG_TYPE 0x03 1100 } 1101 SCB_SCSIID { 1102 size 1 1103 field TWIN_CHNLB 0x80 1104 mask TWIN_TID 0x70 1105 mask TID 0xf0 1106 mask OID 0x0f 1107 } 1108 SCB_LUN { 1109 field SCB_XFERLEN_ODD 0x80 1110 mask LID 0x3f 1111 size 1 1112 } 1113 SCB_TAG { 1114 size 1 1115 } 1116 SCB_CDB_LEN { 1117 size 1 1118 } 1119 SCB_SCSIRATE { 1120 size 1 1121 } 1122 SCB_SCSIOFFSET { 1123 size 1 1124 count 1 1125 } 1126 SCB_NEXT { 1127 size 1 1128 } 1129 SCB_64_SPARE { 1130 size 16 1131 } 1132 SCB_64_BTT { 1133 size 16 1134 } 1135} 1136 1137const SCB_UPLOAD_SIZE 32 1138const SCB_DOWNLOAD_SIZE 32 1139const SCB_DOWNLOAD_SIZE_64 48 1140 1141const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1142 1143/* --------------------- AHA-2840-only definitions -------------------- */ 1144 1145register SEECTL_2840 { 1146 address 0x0c0 1147 access_mode RW 1148 count 2 1149 field CS_2840 0x04 1150 field CK_2840 0x02 1151 field DO_2840 0x01 1152} 1153 1154register STATUS_2840 { 1155 address 0x0c1 1156 access_mode RW 1157 count 4 1158 field EEPROM_TF 0x80 1159 mask BIOS_SEL 0x60 1160 mask ADSEL 0x1e 1161 field DI_2840 0x01 1162} 1163 1164/* --------------------- AIC-7870-only definitions -------------------- */ 1165 1166register CCHADDR { 1167 address 0x0E0 1168 size 8 1169} 1170 1171register CCHCNT { 1172 address 0x0E8 1173} 1174 1175register CCSGRAM { 1176 address 0x0E9 1177} 1178 1179register CCSGADDR { 1180 address 0x0EA 1181} 1182 1183register CCSGCTL { 1184 address 0x0EB 1185 field CCSGDONE 0x80 1186 field CCSGEN 0x08 1187 field SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1188 field CCSGRESET 0x01 1189} 1190 1191register CCSCBCNT { 1192 address 0xEF 1193 count 1 1194} 1195 1196register CCSCBCTL { 1197 address 0x0EE 1198 field CCSCBDONE 0x80 1199 field ARRDONE 0x40 /* SCB Array prefetch done */ 1200 field CCARREN 0x10 1201 field CCSCBEN 0x08 1202 field CCSCBDIR 0x04 1203 field CCSCBRESET 0x01 1204} 1205 1206register CCSCBADDR { 1207 address 0x0ED 1208} 1209 1210register CCSCBRAM { 1211 address 0xEC 1212} 1213 1214/* 1215 * SCB bank address (7895/7896/97 only) 1216 */ 1217register SCBBADDR { 1218 address 0x0F0 1219 access_mode RW 1220 count 3 1221} 1222 1223register CCSCBPTR { 1224 address 0x0F1 1225} 1226 1227register HNSCB_QOFF { 1228 address 0x0F4 1229 count 4 1230} 1231 1232register SNSCB_QOFF { 1233 address 0x0F6 1234} 1235 1236register SDSCB_QOFF { 1237 address 0x0F8 1238} 1239 1240register QOFF_CTLSTA { 1241 address 0x0FA 1242 field SCB_AVAIL 0x40 1243 field SNSCB_ROLLOVER 0x20 1244 field SDSCB_ROLLOVER 0x10 1245 mask SCB_QSIZE 0x07 1246 mask SCB_QSIZE_256 0x06 1247} 1248 1249register DFF_THRSH { 1250 address 0x0FB 1251 mask WR_DFTHRSH 0x70 1252 mask RD_DFTHRSH 0x07 1253 mask RD_DFTHRSH_MIN 0x00 1254 mask RD_DFTHRSH_25 0x01 1255 mask RD_DFTHRSH_50 0x02 1256 mask RD_DFTHRSH_63 0x03 1257 mask RD_DFTHRSH_75 0x04 1258 mask RD_DFTHRSH_85 0x05 1259 mask RD_DFTHRSH_90 0x06 1260 mask RD_DFTHRSH_MAX 0x07 1261 mask WR_DFTHRSH_MIN 0x00 1262 mask WR_DFTHRSH_25 0x10 1263 mask WR_DFTHRSH_50 0x20 1264 mask WR_DFTHRSH_63 0x30 1265 mask WR_DFTHRSH_75 0x40 1266 mask WR_DFTHRSH_85 0x50 1267 mask WR_DFTHRSH_90 0x60 1268 mask WR_DFTHRSH_MAX 0x70 1269 count 4 1270} 1271 1272register SG_CACHE_PRE { 1273 access_mode WO 1274 address 0x0fc 1275 mask SG_ADDR_MASK 0xf8 1276 field LAST_SEG 0x02 1277 field LAST_SEG_DONE 0x01 1278} 1279 1280register SG_CACHE_SHADOW { 1281 access_mode RO 1282 address 0x0fc 1283 mask SG_ADDR_MASK 0xf8 1284 field LAST_SEG 0x02 1285 field LAST_SEG_DONE 0x01 1286} 1287/* ---------------------- Scratch RAM Offsets ------------------------- */ 1288/* These offsets are either to values that are initialized by the board's 1289 * BIOS or are specified by the sequencer code. 1290 * 1291 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1292 * device information, 32-33 and 5a-5f as well. As it turns out, the 1293 * BIOS trashes 20-2f, writing the synchronous negotiation results 1294 * on top of the BIOS values, so we re-use those for our per-target 1295 * scratchspace (actually a value that can be copied directly into 1296 * SCSIRATE). The kernel driver will enable synchronous negotiation 1297 * for all targets that have a value other than 0 in the lower four 1298 * bits of the target scratch space. This should work regardless of 1299 * whether the bios has been installed. 1300 */ 1301 1302scratch_ram { 1303 address 0x020 1304 size 58 1305 1306 /* 1307 * 1 byte per target starting at this address for configuration values 1308 */ 1309 BUSY_TARGETS { 1310 alias TARG_SCSIRATE 1311 size 16 1312 } 1313 /* 1314 * Bit vector of targets that have ULTRA enabled as set by 1315 * the BIOS. The Sequencer relies on a per-SCB field to 1316 * control whether to enable Ultra transfers or not. During 1317 * initialization, we read this field and reuse it for 2 1318 * entries in the busy target table. 1319 */ 1320 ULTRA_ENB { 1321 alias CMDSIZE_TABLE 1322 size 2 1323 count 2 1324 } 1325 /* 1326 * Bit vector of targets that have disconnection disabled as set by 1327 * the BIOS. The Sequencer relies in a per-SCB field to control the 1328 * disconnect priveldge. During initialization, we read this field 1329 * and reuse it for 2 entries in the busy target table. 1330 */ 1331 DISC_DSB { 1332 size 2 1333 count 6 1334 } 1335 CMDSIZE_TABLE_TAIL { 1336 size 4 1337 } 1338 /* 1339 * Partial transfer past cacheline end to be 1340 * transferred using an extra S/G. 1341 */ 1342 MWI_RESIDUAL { 1343 size 1 1344 } 1345 /* 1346 * SCBID of the next SCB to be started by the controller. 1347 */ 1348 NEXT_QUEUED_SCB { 1349 size 1 1350 } 1351 /* 1352 * Single byte buffer used to designate the type or message 1353 * to send to a target. 1354 */ 1355 MSG_OUT { 1356 size 1 1357 } 1358 /* Parameters for DMA Logic */ 1359 DMAPARAMS { 1360 size 1 1361 count 12 1362 field PRELOADEN 0x80 1363 field WIDEODD 0x40 1364 field SCSIEN 0x20 1365 field SDMAEN 0x10 1366 field SDMAENACK 0x10 1367 field HDMAEN 0x08 1368 field HDMAENACK 0x08 1369 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 1370 field FIFOFLUSH 0x02 1371 field FIFORESET 0x01 1372 } 1373 SEQ_FLAGS { 1374 size 1 1375 field NOT_IDENTIFIED 0x80 1376 field NO_CDB_SENT 0x40 1377 field TARGET_CMD_IS_TAGGED 0x40 1378 field DPHASE 0x20 1379 /* Target flags */ 1380 field TARG_CMD_PENDING 0x10 1381 field CMDPHASE_PENDING 0x08 1382 field DPHASE_PENDING 0x04 1383 field SPHASE_PENDING 0x02 1384 field NO_DISCONNECT 0x01 1385 } 1386 /* 1387 * Temporary storage for the 1388 * target/channel/lun of a 1389 * reconnecting target 1390 */ 1391 SAVED_SCSIID { 1392 size 1 1393 } 1394 SAVED_LUN { 1395 size 1 1396 } 1397 /* 1398 * The last bus phase as seen by the sequencer. 1399 */ 1400 LASTPHASE { 1401 size 1 1402 field CDI 0x80 1403 field IOI 0x40 1404 field MSGI 0x20 1405 mask PHASE_MASK CDI|IOI|MSGI 1406 mask P_DATAOUT 0x00 1407 mask P_DATAIN IOI 1408 mask P_COMMAND CDI 1409 mask P_MESGOUT CDI|MSGI 1410 mask P_STATUS CDI|IOI 1411 mask P_MESGIN CDI|IOI|MSGI 1412 mask P_BUSFREE 0x01 1413 } 1414 /* 1415 * head of list of SCBs awaiting 1416 * selection 1417 */ 1418 WAITING_SCBH { 1419 size 1 1420 } 1421 /* 1422 * head of list of SCBs that are 1423 * disconnected. Used for SCB 1424 * paging. 1425 */ 1426 DISCONNECTED_SCBH { 1427 size 1 1428 } 1429 /* 1430 * head of list of SCBs that are 1431 * not in use. Used for SCB paging. 1432 */ 1433 FREE_SCBH { 1434 size 1 1435 } 1436 /* 1437 * head of list of SCBs that have 1438 * completed but have not been 1439 * put into the qoutfifo. 1440 */ 1441 COMPLETE_SCBH { 1442 size 1 1443 } 1444 /* 1445 * Address of the hardware scb array in the host. 1446 */ 1447 HSCB_ADDR { 1448 size 4 1449 } 1450 /* 1451 * Base address of our shared data with the kernel driver in host 1452 * memory. This includes the qoutfifo and target mode 1453 * incoming command queue. 1454 */ 1455 SHARED_DATA_ADDR { 1456 size 4 1457 } 1458 KERNEL_QINPOS { 1459 size 1 1460 } 1461 QINPOS { 1462 size 1 1463 } 1464 QOUTPOS { 1465 size 1 1466 } 1467 /* 1468 * Kernel and sequencer offsets into the queue of 1469 * incoming target mode command descriptors. The 1470 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1471 */ 1472 KERNEL_TQINPOS { 1473 size 1 1474 } 1475 TQINPOS { 1476 size 1 1477 } 1478 ARG_1 { 1479 size 1 1480 count 1 1481 mask SEND_MSG 0x80 1482 mask SEND_SENSE 0x40 1483 mask SEND_REJ 0x20 1484 mask MSGOUT_PHASEMIS 0x10 1485 mask EXIT_MSG_LOOP 0x08 1486 mask CONT_MSG_LOOP 0x04 1487 mask CONT_TARG_SESSION 0x02 1488 alias RETURN_1 1489 } 1490 ARG_2 { 1491 size 1 1492 alias RETURN_2 1493 } 1494 1495 /* 1496 * Snapshot of MSG_OUT taken after each message is sent. 1497 */ 1498 LAST_MSG { 1499 size 1 1500 alias TARG_IMMEDIATE_SCB 1501 } 1502 1503 /* 1504 * Sequences the kernel driver has okayed for us. This allows 1505 * the driver to do things like prevent initiator or target 1506 * operations. 1507 */ 1508 SCSISEQ_TEMPLATE { 1509 size 1 1510 field ENSELO 0x40 1511 field ENSELI 0x20 1512 field ENRSELI 0x10 1513 field ENAUTOATNO 0x08 1514 field ENAUTOATNI 0x04 1515 field ENAUTOATNP 0x02 1516 } 1517} 1518 1519scratch_ram { 1520 address 0x056 1521 size 4 1522 /* 1523 * These scratch ram locations are initialized by the 274X BIOS. 1524 * We reuse them after capturing the BIOS settings during 1525 * initialization. 1526 */ 1527 1528 /* 1529 * The initiator specified tag for this target mode transaction. 1530 */ 1531 HA_274_BIOSGLOBAL { 1532 size 1 1533 field HA_274_EXTENDED_TRANS 0x01 1534 alias INITIATOR_TAG 1535 count 1 1536 } 1537 1538 SEQ_FLAGS2 { 1539 size 1 1540 field SCB_DMA 0x01 1541 field TARGET_MSG_PENDING 0x02 1542 } 1543} 1544 1545scratch_ram { 1546 address 0x05a 1547 size 6 1548 /* 1549 * These are reserved registers in the card's scratch ram on the 2742. 1550 * The EISA configuraiton chip is mapped here. On Rev E. of the 1551 * aic7770, the sequencer can use this area for scratch, but the 1552 * host cannot directly access these registers. On later chips, this 1553 * area can be read and written by both the host and the sequencer. 1554 * Even on later chips, many of these locations are initialized by 1555 * the BIOS. 1556 */ 1557 SCSICONF { 1558 size 1 1559 count 12 1560 field TERM_ENB 0x80 1561 field RESET_SCSI 0x40 1562 field ENSPCHK 0x20 1563 mask HSCSIID 0x07 /* our SCSI ID */ 1564 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1565 } 1566 INTDEF { 1567 address 0x05c 1568 size 1 1569 count 1 1570 field EDGE_TRIG 0x80 1571 mask VECTOR 0x0f 1572 } 1573 HOSTCONF { 1574 address 0x05d 1575 size 1 1576 count 1 1577 } 1578 HA_274_BIOSCTRL { 1579 address 0x05f 1580 size 1 1581 count 1 1582 mask BIOSMODE 0x30 1583 mask BIOSDISABLED 0x30 1584 field CHANNEL_B_PRIMARY 0x08 1585 } 1586} 1587 1588scratch_ram { 1589 address 0x070 1590 size 16 1591 1592 /* 1593 * Per target SCSI offset values for Ultra2 controllers. 1594 */ 1595 TARG_OFFSET { 1596 size 16 1597 count 1 1598 } 1599} 1600 1601const TID_SHIFT 4 1602const SCB_LIST_NULL 0xff 1603const TARGET_CMD_CMPLT 0xfe 1604 1605const CCSGADDR_MAX 0x80 1606const CCSGRAM_MAXSEGS 16 1607 1608/* WDTR Message values */ 1609const BUS_8_BIT 0x00 1610const BUS_16_BIT 0x01 1611const BUS_32_BIT 0x02 1612 1613/* Offset maximums */ 1614const MAX_OFFSET_8BIT 0x0f 1615const MAX_OFFSET_16BIT 0x08 1616const MAX_OFFSET_ULTRA2 0x7f 1617const MAX_OFFSET 0x7f 1618const HOST_MSG 0xff 1619 1620/* Target mode command processing constants */ 1621const CMD_GROUP_CODE_SHIFT 0x05 1622 1623const STATUS_BUSY 0x08 1624const STATUS_QUEUE_FULL 0x28 1625const TARGET_DATA_IN 1 1626 1627/* 1628 * Downloaded (kernel inserted) constants 1629 */ 1630/* Offsets into the SCBID array where different data is stored */ 1631const QOUTFIFO_OFFSET download 1632const QINFIFO_OFFSET download 1633const CACHESIZE_MASK download 1634const INVERTED_CACHESIZE_MASK download 1635const SG_PREFETCH_CNT download 1636const SG_PREFETCH_ALIGN_MASK download 1637const SG_PREFETCH_ADDR_MASK download 1638