1/* 2 * DO NOT EDIT - This file is automatically generated 3 * from the following source files: 4 * 5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $ 7 */ 8typedef int (ahd_reg_print_t)(u_int, u_int *, u_int); 9typedef struct ahd_reg_parse_entry { 10 char *name; 11 uint8_t value; 12 uint8_t mask; 13} ahd_reg_parse_entry_t; 14 15#if AIC_DEBUG_REGISTERS 16ahd_reg_print_t ahd_mode_ptr_print; 17#else 18#define ahd_mode_ptr_print(regvalue, cur_col, wrap) \ 19 ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap) 20#endif 21 22#if AIC_DEBUG_REGISTERS 23ahd_reg_print_t ahd_intstat_print; 24#else 25#define ahd_intstat_print(regvalue, cur_col, wrap) \ 26 ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap) 27#endif 28 29#if AIC_DEBUG_REGISTERS 30ahd_reg_print_t ahd_seqintcode_print; 31#else 32#define ahd_seqintcode_print(regvalue, cur_col, wrap) \ 33 ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap) 34#endif 35 36#if AIC_DEBUG_REGISTERS 37ahd_reg_print_t ahd_clrint_print; 38#else 39#define ahd_clrint_print(regvalue, cur_col, wrap) \ 40 ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap) 41#endif 42 43#if AIC_DEBUG_REGISTERS 44ahd_reg_print_t ahd_error_print; 45#else 46#define ahd_error_print(regvalue, cur_col, wrap) \ 47 ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap) 48#endif 49 50#if AIC_DEBUG_REGISTERS 51ahd_reg_print_t ahd_hcntrl_print; 52#else 53#define ahd_hcntrl_print(regvalue, cur_col, wrap) \ 54 ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap) 55#endif 56 57#if AIC_DEBUG_REGISTERS 58ahd_reg_print_t ahd_hnscb_qoff_print; 59#else 60#define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \ 61 ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap) 62#endif 63 64#if AIC_DEBUG_REGISTERS 65ahd_reg_print_t ahd_hescb_qoff_print; 66#else 67#define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \ 68 ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap) 69#endif 70 71#if AIC_DEBUG_REGISTERS 72ahd_reg_print_t ahd_hs_mailbox_print; 73#else 74#define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \ 75 ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap) 76#endif 77 78#if AIC_DEBUG_REGISTERS 79ahd_reg_print_t ahd_seqintstat_print; 80#else 81#define ahd_seqintstat_print(regvalue, cur_col, wrap) \ 82 ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 83#endif 84 85#if AIC_DEBUG_REGISTERS 86ahd_reg_print_t ahd_clrseqintstat_print; 87#else 88#define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \ 89 ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap) 90#endif 91 92#if AIC_DEBUG_REGISTERS 93ahd_reg_print_t ahd_swtimer_print; 94#else 95#define ahd_swtimer_print(regvalue, cur_col, wrap) \ 96 ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap) 97#endif 98 99#if AIC_DEBUG_REGISTERS 100ahd_reg_print_t ahd_snscb_qoff_print; 101#else 102#define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \ 103 ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap) 104#endif 105 106#if AIC_DEBUG_REGISTERS 107ahd_reg_print_t ahd_sescb_qoff_print; 108#else 109#define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \ 110 ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap) 111#endif 112 113#if AIC_DEBUG_REGISTERS 114ahd_reg_print_t ahd_sdscb_qoff_print; 115#else 116#define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \ 117 ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap) 118#endif 119 120#if AIC_DEBUG_REGISTERS 121ahd_reg_print_t ahd_qoff_ctlsta_print; 122#else 123#define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \ 124 ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap) 125#endif 126 127#if AIC_DEBUG_REGISTERS 128ahd_reg_print_t ahd_intctl_print; 129#else 130#define ahd_intctl_print(regvalue, cur_col, wrap) \ 131 ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap) 132#endif 133 134#if AIC_DEBUG_REGISTERS 135ahd_reg_print_t ahd_dfcntrl_print; 136#else 137#define ahd_dfcntrl_print(regvalue, cur_col, wrap) \ 138 ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap) 139#endif 140 141#if AIC_DEBUG_REGISTERS 142ahd_reg_print_t ahd_dscommand0_print; 143#else 144#define ahd_dscommand0_print(regvalue, cur_col, wrap) \ 145 ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap) 146#endif 147 148#if AIC_DEBUG_REGISTERS 149ahd_reg_print_t ahd_dfstatus_print; 150#else 151#define ahd_dfstatus_print(regvalue, cur_col, wrap) \ 152 ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap) 153#endif 154 155#if AIC_DEBUG_REGISTERS 156ahd_reg_print_t ahd_sg_cache_shadow_print; 157#else 158#define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \ 159 ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap) 160#endif 161 162#if AIC_DEBUG_REGISTERS 163ahd_reg_print_t ahd_sg_cache_pre_print; 164#else 165#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \ 166 ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap) 167#endif 168 169#if AIC_DEBUG_REGISTERS 170ahd_reg_print_t ahd_lqin_print; 171#else 172#define ahd_lqin_print(regvalue, cur_col, wrap) \ 173 ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap) 174#endif 175 176#if AIC_DEBUG_REGISTERS 177ahd_reg_print_t ahd_lunptr_print; 178#else 179#define ahd_lunptr_print(regvalue, cur_col, wrap) \ 180 ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap) 181#endif 182 183#if AIC_DEBUG_REGISTERS 184ahd_reg_print_t ahd_cmdlenptr_print; 185#else 186#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \ 187 ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap) 188#endif 189 190#if AIC_DEBUG_REGISTERS 191ahd_reg_print_t ahd_attrptr_print; 192#else 193#define ahd_attrptr_print(regvalue, cur_col, wrap) \ 194 ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap) 195#endif 196 197#if AIC_DEBUG_REGISTERS 198ahd_reg_print_t ahd_flagptr_print; 199#else 200#define ahd_flagptr_print(regvalue, cur_col, wrap) \ 201 ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap) 202#endif 203 204#if AIC_DEBUG_REGISTERS 205ahd_reg_print_t ahd_cmdptr_print; 206#else 207#define ahd_cmdptr_print(regvalue, cur_col, wrap) \ 208 ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap) 209#endif 210 211#if AIC_DEBUG_REGISTERS 212ahd_reg_print_t ahd_qnextptr_print; 213#else 214#define ahd_qnextptr_print(regvalue, cur_col, wrap) \ 215 ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap) 216#endif 217 218#if AIC_DEBUG_REGISTERS 219ahd_reg_print_t ahd_abrtbyteptr_print; 220#else 221#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \ 222 ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap) 223#endif 224 225#if AIC_DEBUG_REGISTERS 226ahd_reg_print_t ahd_abrtbitptr_print; 227#else 228#define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \ 229 ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap) 230#endif 231 232#if AIC_DEBUG_REGISTERS 233ahd_reg_print_t ahd_lunlen_print; 234#else 235#define ahd_lunlen_print(regvalue, cur_col, wrap) \ 236 ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap) 237#endif 238 239#if AIC_DEBUG_REGISTERS 240ahd_reg_print_t ahd_cdblimit_print; 241#else 242#define ahd_cdblimit_print(regvalue, cur_col, wrap) \ 243 ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap) 244#endif 245 246#if AIC_DEBUG_REGISTERS 247ahd_reg_print_t ahd_maxcmd_print; 248#else 249#define ahd_maxcmd_print(regvalue, cur_col, wrap) \ 250 ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap) 251#endif 252 253#if AIC_DEBUG_REGISTERS 254ahd_reg_print_t ahd_maxcmdcnt_print; 255#else 256#define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \ 257 ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap) 258#endif 259 260#if AIC_DEBUG_REGISTERS 261ahd_reg_print_t ahd_lqctl1_print; 262#else 263#define ahd_lqctl1_print(regvalue, cur_col, wrap) \ 264 ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap) 265#endif 266 267#if AIC_DEBUG_REGISTERS 268ahd_reg_print_t ahd_lqctl2_print; 269#else 270#define ahd_lqctl2_print(regvalue, cur_col, wrap) \ 271 ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap) 272#endif 273 274#if AIC_DEBUG_REGISTERS 275ahd_reg_print_t ahd_scsiseq0_print; 276#else 277#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \ 278 ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap) 279#endif 280 281#if AIC_DEBUG_REGISTERS 282ahd_reg_print_t ahd_scsiseq1_print; 283#else 284#define ahd_scsiseq1_print(regvalue, cur_col, wrap) \ 285 ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap) 286#endif 287 288#if AIC_DEBUG_REGISTERS 289ahd_reg_print_t ahd_sxfrctl0_print; 290#else 291#define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \ 292 ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap) 293#endif 294 295#if AIC_DEBUG_REGISTERS 296ahd_reg_print_t ahd_sxfrctl1_print; 297#else 298#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \ 299 ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap) 300#endif 301 302#if AIC_DEBUG_REGISTERS 303ahd_reg_print_t ahd_dffstat_print; 304#else 305#define ahd_dffstat_print(regvalue, cur_col, wrap) \ 306 ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap) 307#endif 308 309#if AIC_DEBUG_REGISTERS 310ahd_reg_print_t ahd_multargid_print; 311#else 312#define ahd_multargid_print(regvalue, cur_col, wrap) \ 313 ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap) 314#endif 315 316#if AIC_DEBUG_REGISTERS 317ahd_reg_print_t ahd_scsisigo_print; 318#else 319#define ahd_scsisigo_print(regvalue, cur_col, wrap) \ 320 ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap) 321#endif 322 323#if AIC_DEBUG_REGISTERS 324ahd_reg_print_t ahd_scsisigi_print; 325#else 326#define ahd_scsisigi_print(regvalue, cur_col, wrap) \ 327 ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap) 328#endif 329 330#if AIC_DEBUG_REGISTERS 331ahd_reg_print_t ahd_scsiphase_print; 332#else 333#define ahd_scsiphase_print(regvalue, cur_col, wrap) \ 334 ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap) 335#endif 336 337#if AIC_DEBUG_REGISTERS 338ahd_reg_print_t ahd_scsidat_print; 339#else 340#define ahd_scsidat_print(regvalue, cur_col, wrap) \ 341 ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap) 342#endif 343 344#if AIC_DEBUG_REGISTERS 345ahd_reg_print_t ahd_scsibus_print; 346#else 347#define ahd_scsibus_print(regvalue, cur_col, wrap) \ 348 ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap) 349#endif 350 351#if AIC_DEBUG_REGISTERS 352ahd_reg_print_t ahd_targidin_print; 353#else 354#define ahd_targidin_print(regvalue, cur_col, wrap) \ 355 ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap) 356#endif 357 358#if AIC_DEBUG_REGISTERS 359ahd_reg_print_t ahd_selid_print; 360#else 361#define ahd_selid_print(regvalue, cur_col, wrap) \ 362 ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap) 363#endif 364 365#if AIC_DEBUG_REGISTERS 366ahd_reg_print_t ahd_optionmode_print; 367#else 368#define ahd_optionmode_print(regvalue, cur_col, wrap) \ 369 ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap) 370#endif 371 372#if AIC_DEBUG_REGISTERS 373ahd_reg_print_t ahd_sblkctl_print; 374#else 375#define ahd_sblkctl_print(regvalue, cur_col, wrap) \ 376 ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap) 377#endif 378 379#if AIC_DEBUG_REGISTERS 380ahd_reg_print_t ahd_sstat0_print; 381#else 382#define ahd_sstat0_print(regvalue, cur_col, wrap) \ 383 ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap) 384#endif 385 386#if AIC_DEBUG_REGISTERS 387ahd_reg_print_t ahd_simode0_print; 388#else 389#define ahd_simode0_print(regvalue, cur_col, wrap) \ 390 ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap) 391#endif 392 393#if AIC_DEBUG_REGISTERS 394ahd_reg_print_t ahd_clrsint0_print; 395#else 396#define ahd_clrsint0_print(regvalue, cur_col, wrap) \ 397 ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap) 398#endif 399 400#if AIC_DEBUG_REGISTERS 401ahd_reg_print_t ahd_sstat1_print; 402#else 403#define ahd_sstat1_print(regvalue, cur_col, wrap) \ 404 ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap) 405#endif 406 407#if AIC_DEBUG_REGISTERS 408ahd_reg_print_t ahd_clrsint1_print; 409#else 410#define ahd_clrsint1_print(regvalue, cur_col, wrap) \ 411 ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap) 412#endif 413 414#if AIC_DEBUG_REGISTERS 415ahd_reg_print_t ahd_sstat2_print; 416#else 417#define ahd_sstat2_print(regvalue, cur_col, wrap) \ 418 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap) 419#endif 420 421#if AIC_DEBUG_REGISTERS 422ahd_reg_print_t ahd_clrsint2_print; 423#else 424#define ahd_clrsint2_print(regvalue, cur_col, wrap) \ 425 ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap) 426#endif 427 428#if AIC_DEBUG_REGISTERS 429ahd_reg_print_t ahd_perrdiag_print; 430#else 431#define ahd_perrdiag_print(regvalue, cur_col, wrap) \ 432 ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap) 433#endif 434 435#if AIC_DEBUG_REGISTERS 436ahd_reg_print_t ahd_lqistate_print; 437#else 438#define ahd_lqistate_print(regvalue, cur_col, wrap) \ 439 ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap) 440#endif 441 442#if AIC_DEBUG_REGISTERS 443ahd_reg_print_t ahd_soffcnt_print; 444#else 445#define ahd_soffcnt_print(regvalue, cur_col, wrap) \ 446 ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap) 447#endif 448 449#if AIC_DEBUG_REGISTERS 450ahd_reg_print_t ahd_lqostate_print; 451#else 452#define ahd_lqostate_print(regvalue, cur_col, wrap) \ 453 ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap) 454#endif 455 456#if AIC_DEBUG_REGISTERS 457ahd_reg_print_t ahd_lqistat0_print; 458#else 459#define ahd_lqistat0_print(regvalue, cur_col, wrap) \ 460 ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap) 461#endif 462 463#if AIC_DEBUG_REGISTERS 464ahd_reg_print_t ahd_lqimode0_print; 465#else 466#define ahd_lqimode0_print(regvalue, cur_col, wrap) \ 467 ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap) 468#endif 469 470#if AIC_DEBUG_REGISTERS 471ahd_reg_print_t ahd_clrlqiint0_print; 472#else 473#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \ 474 ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap) 475#endif 476 477#if AIC_DEBUG_REGISTERS 478ahd_reg_print_t ahd_lqimode1_print; 479#else 480#define ahd_lqimode1_print(regvalue, cur_col, wrap) \ 481 ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap) 482#endif 483 484#if AIC_DEBUG_REGISTERS 485ahd_reg_print_t ahd_lqistat1_print; 486#else 487#define ahd_lqistat1_print(regvalue, cur_col, wrap) \ 488 ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap) 489#endif 490 491#if AIC_DEBUG_REGISTERS 492ahd_reg_print_t ahd_clrlqiint1_print; 493#else 494#define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \ 495 ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap) 496#endif 497 498#if AIC_DEBUG_REGISTERS 499ahd_reg_print_t ahd_lqistat2_print; 500#else 501#define ahd_lqistat2_print(regvalue, cur_col, wrap) \ 502 ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap) 503#endif 504 505#if AIC_DEBUG_REGISTERS 506ahd_reg_print_t ahd_sstat3_print; 507#else 508#define ahd_sstat3_print(regvalue, cur_col, wrap) \ 509 ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap) 510#endif 511 512#if AIC_DEBUG_REGISTERS 513ahd_reg_print_t ahd_simode3_print; 514#else 515#define ahd_simode3_print(regvalue, cur_col, wrap) \ 516 ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap) 517#endif 518 519#if AIC_DEBUG_REGISTERS 520ahd_reg_print_t ahd_clrsint3_print; 521#else 522#define ahd_clrsint3_print(regvalue, cur_col, wrap) \ 523 ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap) 524#endif 525 526#if AIC_DEBUG_REGISTERS 527ahd_reg_print_t ahd_lqostat0_print; 528#else 529#define ahd_lqostat0_print(regvalue, cur_col, wrap) \ 530 ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap) 531#endif 532 533#if AIC_DEBUG_REGISTERS 534ahd_reg_print_t ahd_clrlqoint0_print; 535#else 536#define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \ 537 ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap) 538#endif 539 540#if AIC_DEBUG_REGISTERS 541ahd_reg_print_t ahd_lqomode0_print; 542#else 543#define ahd_lqomode0_print(regvalue, cur_col, wrap) \ 544 ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap) 545#endif 546 547#if AIC_DEBUG_REGISTERS 548ahd_reg_print_t ahd_lqomode1_print; 549#else 550#define ahd_lqomode1_print(regvalue, cur_col, wrap) \ 551 ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap) 552#endif 553 554#if AIC_DEBUG_REGISTERS 555ahd_reg_print_t ahd_lqostat1_print; 556#else 557#define ahd_lqostat1_print(regvalue, cur_col, wrap) \ 558 ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap) 559#endif 560 561#if AIC_DEBUG_REGISTERS 562ahd_reg_print_t ahd_clrlqoint1_print; 563#else 564#define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \ 565 ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap) 566#endif 567 568#if AIC_DEBUG_REGISTERS 569ahd_reg_print_t ahd_lqostat2_print; 570#else 571#define ahd_lqostat2_print(regvalue, cur_col, wrap) \ 572 ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap) 573#endif 574 575#if AIC_DEBUG_REGISTERS 576ahd_reg_print_t ahd_os_space_cnt_print; 577#else 578#define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \ 579 ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap) 580#endif 581 582#if AIC_DEBUG_REGISTERS 583ahd_reg_print_t ahd_simode1_print; 584#else 585#define ahd_simode1_print(regvalue, cur_col, wrap) \ 586 ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap) 587#endif 588 589#if AIC_DEBUG_REGISTERS 590ahd_reg_print_t ahd_gsfifo_print; 591#else 592#define ahd_gsfifo_print(regvalue, cur_col, wrap) \ 593 ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap) 594#endif 595 596#if AIC_DEBUG_REGISTERS 597ahd_reg_print_t ahd_dffsxfrctl_print; 598#else 599#define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \ 600 ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap) 601#endif 602 603#if AIC_DEBUG_REGISTERS 604ahd_reg_print_t ahd_lqoscsctl_print; 605#else 606#define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \ 607 ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap) 608#endif 609 610#if AIC_DEBUG_REGISTERS 611ahd_reg_print_t ahd_nextscb_print; 612#else 613#define ahd_nextscb_print(regvalue, cur_col, wrap) \ 614 ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap) 615#endif 616 617#if AIC_DEBUG_REGISTERS 618ahd_reg_print_t ahd_clrseqintsrc_print; 619#else 620#define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \ 621 ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap) 622#endif 623 624#if AIC_DEBUG_REGISTERS 625ahd_reg_print_t ahd_seqintsrc_print; 626#else 627#define ahd_seqintsrc_print(regvalue, cur_col, wrap) \ 628 ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap) 629#endif 630 631#if AIC_DEBUG_REGISTERS 632ahd_reg_print_t ahd_seqimode_print; 633#else 634#define ahd_seqimode_print(regvalue, cur_col, wrap) \ 635 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap) 636#endif 637 638#if AIC_DEBUG_REGISTERS 639ahd_reg_print_t ahd_currscb_print; 640#else 641#define ahd_currscb_print(regvalue, cur_col, wrap) \ 642 ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap) 643#endif 644 645#if AIC_DEBUG_REGISTERS 646ahd_reg_print_t ahd_mdffstat_print; 647#else 648#define ahd_mdffstat_print(regvalue, cur_col, wrap) \ 649 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap) 650#endif 651 652#if AIC_DEBUG_REGISTERS 653ahd_reg_print_t ahd_lastscb_print; 654#else 655#define ahd_lastscb_print(regvalue, cur_col, wrap) \ 656 ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap) 657#endif 658 659#if AIC_DEBUG_REGISTERS 660ahd_reg_print_t ahd_shaddr_print; 661#else 662#define ahd_shaddr_print(regvalue, cur_col, wrap) \ 663 ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap) 664#endif 665 666#if AIC_DEBUG_REGISTERS 667ahd_reg_print_t ahd_negoaddr_print; 668#else 669#define ahd_negoaddr_print(regvalue, cur_col, wrap) \ 670 ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap) 671#endif 672 673#if AIC_DEBUG_REGISTERS 674ahd_reg_print_t ahd_negperiod_print; 675#else 676#define ahd_negperiod_print(regvalue, cur_col, wrap) \ 677 ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap) 678#endif 679 680#if AIC_DEBUG_REGISTERS 681ahd_reg_print_t ahd_negoffset_print; 682#else 683#define ahd_negoffset_print(regvalue, cur_col, wrap) \ 684 ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap) 685#endif 686 687#if AIC_DEBUG_REGISTERS 688ahd_reg_print_t ahd_negppropts_print; 689#else 690#define ahd_negppropts_print(regvalue, cur_col, wrap) \ 691 ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap) 692#endif 693 694#if AIC_DEBUG_REGISTERS 695ahd_reg_print_t ahd_negconopts_print; 696#else 697#define ahd_negconopts_print(regvalue, cur_col, wrap) \ 698 ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap) 699#endif 700 701#if AIC_DEBUG_REGISTERS 702ahd_reg_print_t ahd_annexcol_print; 703#else 704#define ahd_annexcol_print(regvalue, cur_col, wrap) \ 705 ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap) 706#endif 707 708#if AIC_DEBUG_REGISTERS 709ahd_reg_print_t ahd_annexdat_print; 710#else 711#define ahd_annexdat_print(regvalue, cur_col, wrap) \ 712 ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap) 713#endif 714 715#if AIC_DEBUG_REGISTERS 716ahd_reg_print_t ahd_scschkn_print; 717#else 718#define ahd_scschkn_print(regvalue, cur_col, wrap) \ 719 ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap) 720#endif 721 722#if AIC_DEBUG_REGISTERS 723ahd_reg_print_t ahd_iownid_print; 724#else 725#define ahd_iownid_print(regvalue, cur_col, wrap) \ 726 ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap) 727#endif 728 729#if AIC_DEBUG_REGISTERS 730ahd_reg_print_t ahd_shcnt_print; 731#else 732#define ahd_shcnt_print(regvalue, cur_col, wrap) \ 733 ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap) 734#endif 735 736#if AIC_DEBUG_REGISTERS 737ahd_reg_print_t ahd_townid_print; 738#else 739#define ahd_townid_print(regvalue, cur_col, wrap) \ 740 ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap) 741#endif 742 743#if AIC_DEBUG_REGISTERS 744ahd_reg_print_t ahd_seloid_print; 745#else 746#define ahd_seloid_print(regvalue, cur_col, wrap) \ 747 ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap) 748#endif 749 750#if AIC_DEBUG_REGISTERS 751ahd_reg_print_t ahd_haddr_print; 752#else 753#define ahd_haddr_print(regvalue, cur_col, wrap) \ 754 ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap) 755#endif 756 757#if AIC_DEBUG_REGISTERS 758ahd_reg_print_t ahd_hcnt_print; 759#else 760#define ahd_hcnt_print(regvalue, cur_col, wrap) \ 761 ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap) 762#endif 763 764#if AIC_DEBUG_REGISTERS 765ahd_reg_print_t ahd_sghaddr_print; 766#else 767#define ahd_sghaddr_print(regvalue, cur_col, wrap) \ 768 ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap) 769#endif 770 771#if AIC_DEBUG_REGISTERS 772ahd_reg_print_t ahd_scbhaddr_print; 773#else 774#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \ 775 ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap) 776#endif 777 778#if AIC_DEBUG_REGISTERS 779ahd_reg_print_t ahd_sghcnt_print; 780#else 781#define ahd_sghcnt_print(regvalue, cur_col, wrap) \ 782 ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap) 783#endif 784 785#if AIC_DEBUG_REGISTERS 786ahd_reg_print_t ahd_scbhcnt_print; 787#else 788#define ahd_scbhcnt_print(regvalue, cur_col, wrap) \ 789 ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap) 790#endif 791 792#if AIC_DEBUG_REGISTERS 793ahd_reg_print_t ahd_dff_thrsh_print; 794#else 795#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \ 796 ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap) 797#endif 798 799#if AIC_DEBUG_REGISTERS 800ahd_reg_print_t ahd_pcixctl_print; 801#else 802#define ahd_pcixctl_print(regvalue, cur_col, wrap) \ 803 ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap) 804#endif 805 806#if AIC_DEBUG_REGISTERS 807ahd_reg_print_t ahd_dchspltstat0_print; 808#else 809#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \ 810 ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap) 811#endif 812 813#if AIC_DEBUG_REGISTERS 814ahd_reg_print_t ahd_dchspltstat1_print; 815#else 816#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \ 817 ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap) 818#endif 819 820#if AIC_DEBUG_REGISTERS 821ahd_reg_print_t ahd_sgspltstat0_print; 822#else 823#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \ 824 ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap) 825#endif 826 827#if AIC_DEBUG_REGISTERS 828ahd_reg_print_t ahd_sgspltstat1_print; 829#else 830#define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \ 831 ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap) 832#endif 833 834#if AIC_DEBUG_REGISTERS 835ahd_reg_print_t ahd_df0pcistat_print; 836#else 837#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \ 838 ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap) 839#endif 840 841#if AIC_DEBUG_REGISTERS 842ahd_reg_print_t ahd_reg0_print; 843#else 844#define ahd_reg0_print(regvalue, cur_col, wrap) \ 845 ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap) 846#endif 847 848#if AIC_DEBUG_REGISTERS 849ahd_reg_print_t ahd_reg_isr_print; 850#else 851#define ahd_reg_isr_print(regvalue, cur_col, wrap) \ 852 ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap) 853#endif 854 855#if AIC_DEBUG_REGISTERS 856ahd_reg_print_t ahd_sg_state_print; 857#else 858#define ahd_sg_state_print(regvalue, cur_col, wrap) \ 859 ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap) 860#endif 861 862#if AIC_DEBUG_REGISTERS 863ahd_reg_print_t ahd_targpcistat_print; 864#else 865#define ahd_targpcistat_print(regvalue, cur_col, wrap) \ 866 ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap) 867#endif 868 869#if AIC_DEBUG_REGISTERS 870ahd_reg_print_t ahd_scbptr_print; 871#else 872#define ahd_scbptr_print(regvalue, cur_col, wrap) \ 873 ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap) 874#endif 875 876#if AIC_DEBUG_REGISTERS 877ahd_reg_print_t ahd_scbautoptr_print; 878#else 879#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \ 880 ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap) 881#endif 882 883#if AIC_DEBUG_REGISTERS 884ahd_reg_print_t ahd_ccsgaddr_print; 885#else 886#define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \ 887 ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap) 888#endif 889 890#if AIC_DEBUG_REGISTERS 891ahd_reg_print_t ahd_ccscbaddr_print; 892#else 893#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \ 894 ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap) 895#endif 896 897#if AIC_DEBUG_REGISTERS 898ahd_reg_print_t ahd_ccscbctl_print; 899#else 900#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \ 901 ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap) 902#endif 903 904#if AIC_DEBUG_REGISTERS 905ahd_reg_print_t ahd_ccsgctl_print; 906#else 907#define ahd_ccsgctl_print(regvalue, cur_col, wrap) \ 908 ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap) 909#endif 910 911#if AIC_DEBUG_REGISTERS 912ahd_reg_print_t ahd_ccsgram_print; 913#else 914#define ahd_ccsgram_print(regvalue, cur_col, wrap) \ 915 ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap) 916#endif 917 918#if AIC_DEBUG_REGISTERS 919ahd_reg_print_t ahd_ccscbram_print; 920#else 921#define ahd_ccscbram_print(regvalue, cur_col, wrap) \ 922 ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap) 923#endif 924 925#if AIC_DEBUG_REGISTERS 926ahd_reg_print_t ahd_brddat_print; 927#else 928#define ahd_brddat_print(regvalue, cur_col, wrap) \ 929 ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap) 930#endif 931 932#if AIC_DEBUG_REGISTERS 933ahd_reg_print_t ahd_brdctl_print; 934#else 935#define ahd_brdctl_print(regvalue, cur_col, wrap) \ 936 ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap) 937#endif 938 939#if AIC_DEBUG_REGISTERS 940ahd_reg_print_t ahd_seeadr_print; 941#else 942#define ahd_seeadr_print(regvalue, cur_col, wrap) \ 943 ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap) 944#endif 945 946#if AIC_DEBUG_REGISTERS 947ahd_reg_print_t ahd_seedat_print; 948#else 949#define ahd_seedat_print(regvalue, cur_col, wrap) \ 950 ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap) 951#endif 952 953#if AIC_DEBUG_REGISTERS 954ahd_reg_print_t ahd_seectl_print; 955#else 956#define ahd_seectl_print(regvalue, cur_col, wrap) \ 957 ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap) 958#endif 959 960#if AIC_DEBUG_REGISTERS 961ahd_reg_print_t ahd_seestat_print; 962#else 963#define ahd_seestat_print(regvalue, cur_col, wrap) \ 964 ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap) 965#endif 966 967#if AIC_DEBUG_REGISTERS 968ahd_reg_print_t ahd_dspdatactl_print; 969#else 970#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \ 971 ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap) 972#endif 973 974#if AIC_DEBUG_REGISTERS 975ahd_reg_print_t ahd_dfdat_print; 976#else 977#define ahd_dfdat_print(regvalue, cur_col, wrap) \ 978 ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap) 979#endif 980 981#if AIC_DEBUG_REGISTERS 982ahd_reg_print_t ahd_dspselect_print; 983#else 984#define ahd_dspselect_print(regvalue, cur_col, wrap) \ 985 ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap) 986#endif 987 988#if AIC_DEBUG_REGISTERS 989ahd_reg_print_t ahd_wrtbiasctl_print; 990#else 991#define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \ 992 ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap) 993#endif 994 995#if AIC_DEBUG_REGISTERS 996ahd_reg_print_t ahd_seqctl0_print; 997#else 998#define ahd_seqctl0_print(regvalue, cur_col, wrap) \ 999 ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap) 1000#endif 1001 1002#if AIC_DEBUG_REGISTERS 1003ahd_reg_print_t ahd_flags_print; 1004#else 1005#define ahd_flags_print(regvalue, cur_col, wrap) \ 1006 ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap) 1007#endif 1008 1009#if AIC_DEBUG_REGISTERS 1010ahd_reg_print_t ahd_seqintctl_print; 1011#else 1012#define ahd_seqintctl_print(regvalue, cur_col, wrap) \ 1013 ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap) 1014#endif 1015 1016#if AIC_DEBUG_REGISTERS 1017ahd_reg_print_t ahd_seqram_print; 1018#else 1019#define ahd_seqram_print(regvalue, cur_col, wrap) \ 1020 ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap) 1021#endif 1022 1023#if AIC_DEBUG_REGISTERS 1024ahd_reg_print_t ahd_prgmcnt_print; 1025#else 1026#define ahd_prgmcnt_print(regvalue, cur_col, wrap) \ 1027 ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap) 1028#endif 1029 1030#if AIC_DEBUG_REGISTERS 1031ahd_reg_print_t ahd_accum_print; 1032#else 1033#define ahd_accum_print(regvalue, cur_col, wrap) \ 1034 ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap) 1035#endif 1036 1037#if AIC_DEBUG_REGISTERS 1038ahd_reg_print_t ahd_sindex_print; 1039#else 1040#define ahd_sindex_print(regvalue, cur_col, wrap) \ 1041 ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap) 1042#endif 1043 1044#if AIC_DEBUG_REGISTERS 1045ahd_reg_print_t ahd_dindex_print; 1046#else 1047#define ahd_dindex_print(regvalue, cur_col, wrap) \ 1048 ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap) 1049#endif 1050 1051#if AIC_DEBUG_REGISTERS 1052ahd_reg_print_t ahd_allones_print; 1053#else 1054#define ahd_allones_print(regvalue, cur_col, wrap) \ 1055 ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap) 1056#endif 1057 1058#if AIC_DEBUG_REGISTERS 1059ahd_reg_print_t ahd_allzeros_print; 1060#else 1061#define ahd_allzeros_print(regvalue, cur_col, wrap) \ 1062 ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap) 1063#endif 1064 1065#if AIC_DEBUG_REGISTERS 1066ahd_reg_print_t ahd_none_print; 1067#else 1068#define ahd_none_print(regvalue, cur_col, wrap) \ 1069 ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap) 1070#endif 1071 1072#if AIC_DEBUG_REGISTERS 1073ahd_reg_print_t ahd_sindir_print; 1074#else 1075#define ahd_sindir_print(regvalue, cur_col, wrap) \ 1076 ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap) 1077#endif 1078 1079#if AIC_DEBUG_REGISTERS 1080ahd_reg_print_t ahd_dindir_print; 1081#else 1082#define ahd_dindir_print(regvalue, cur_col, wrap) \ 1083 ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap) 1084#endif 1085 1086#if AIC_DEBUG_REGISTERS 1087ahd_reg_print_t ahd_stack_print; 1088#else 1089#define ahd_stack_print(regvalue, cur_col, wrap) \ 1090 ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap) 1091#endif 1092 1093#if AIC_DEBUG_REGISTERS 1094ahd_reg_print_t ahd_intvec1_addr_print; 1095#else 1096#define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \ 1097 ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap) 1098#endif 1099 1100#if AIC_DEBUG_REGISTERS 1101ahd_reg_print_t ahd_curaddr_print; 1102#else 1103#define ahd_curaddr_print(regvalue, cur_col, wrap) \ 1104 ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap) 1105#endif 1106 1107#if AIC_DEBUG_REGISTERS 1108ahd_reg_print_t ahd_intvec2_addr_print; 1109#else 1110#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \ 1111 ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap) 1112#endif 1113 1114#if AIC_DEBUG_REGISTERS 1115ahd_reg_print_t ahd_longjmp_addr_print; 1116#else 1117#define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \ 1118 ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap) 1119#endif 1120 1121#if AIC_DEBUG_REGISTERS 1122ahd_reg_print_t ahd_accum_save_print; 1123#else 1124#define ahd_accum_save_print(regvalue, cur_col, wrap) \ 1125 ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap) 1126#endif 1127 1128#if AIC_DEBUG_REGISTERS 1129ahd_reg_print_t ahd_sram_base_print; 1130#else 1131#define ahd_sram_base_print(regvalue, cur_col, wrap) \ 1132 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap) 1133#endif 1134 1135#if AIC_DEBUG_REGISTERS 1136ahd_reg_print_t ahd_waiting_scb_tails_print; 1137#else 1138#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \ 1139 ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap) 1140#endif 1141 1142#if AIC_DEBUG_REGISTERS 1143ahd_reg_print_t ahd_waiting_tid_head_print; 1144#else 1145#define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \ 1146 ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap) 1147#endif 1148 1149#if AIC_DEBUG_REGISTERS 1150ahd_reg_print_t ahd_waiting_tid_tail_print; 1151#else 1152#define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \ 1153 ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap) 1154#endif 1155 1156#if AIC_DEBUG_REGISTERS 1157ahd_reg_print_t ahd_next_queued_scb_addr_print; 1158#else 1159#define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \ 1160 ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap) 1161#endif 1162 1163#if AIC_DEBUG_REGISTERS 1164ahd_reg_print_t ahd_complete_scb_head_print; 1165#else 1166#define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \ 1167 ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap) 1168#endif 1169 1170#if AIC_DEBUG_REGISTERS 1171ahd_reg_print_t ahd_complete_scb_dmainprog_head_print; 1172#else 1173#define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \ 1174 ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap) 1175#endif 1176 1177#if AIC_DEBUG_REGISTERS 1178ahd_reg_print_t ahd_complete_dma_scb_head_print; 1179#else 1180#define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \ 1181 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap) 1182#endif 1183 1184#if AIC_DEBUG_REGISTERS 1185ahd_reg_print_t ahd_complete_dma_scb_tail_print; 1186#else 1187#define ahd_complete_dma_scb_tail_print(regvalue, cur_col, wrap) \ 1188 ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 0x12e, regvalue, cur_col, wrap) 1189#endif 1190 1191#if AIC_DEBUG_REGISTERS 1192ahd_reg_print_t ahd_complete_on_qfreeze_head_print; 1193#else 1194#define ahd_complete_on_qfreeze_head_print(regvalue, cur_col, wrap) \ 1195 ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 0x130, regvalue, cur_col, wrap) 1196#endif 1197 1198#if AIC_DEBUG_REGISTERS 1199ahd_reg_print_t ahd_qfreeze_count_print; 1200#else 1201#define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \ 1202 ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap) 1203#endif 1204 1205#if AIC_DEBUG_REGISTERS 1206ahd_reg_print_t ahd_kernel_qfreeze_count_print; 1207#else 1208#define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \ 1209 ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap) 1210#endif 1211 1212#if AIC_DEBUG_REGISTERS 1213ahd_reg_print_t ahd_saved_mode_print; 1214#else 1215#define ahd_saved_mode_print(regvalue, cur_col, wrap) \ 1216 ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap) 1217#endif 1218 1219#if AIC_DEBUG_REGISTERS 1220ahd_reg_print_t ahd_msg_out_print; 1221#else 1222#define ahd_msg_out_print(regvalue, cur_col, wrap) \ 1223 ahd_print_register(NULL, 0, "MSG_OUT", 0x137, regvalue, cur_col, wrap) 1224#endif 1225 1226#if AIC_DEBUG_REGISTERS 1227ahd_reg_print_t ahd_dmaparams_print; 1228#else 1229#define ahd_dmaparams_print(regvalue, cur_col, wrap) \ 1230 ahd_print_register(NULL, 0, "DMAPARAMS", 0x138, regvalue, cur_col, wrap) 1231#endif 1232 1233#if AIC_DEBUG_REGISTERS 1234ahd_reg_print_t ahd_seq_flags_print; 1235#else 1236#define ahd_seq_flags_print(regvalue, cur_col, wrap) \ 1237 ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap) 1238#endif 1239 1240#if AIC_DEBUG_REGISTERS 1241ahd_reg_print_t ahd_saved_scsiid_print; 1242#else 1243#define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \ 1244 ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x13a, regvalue, cur_col, wrap) 1245#endif 1246 1247#if AIC_DEBUG_REGISTERS 1248ahd_reg_print_t ahd_saved_lun_print; 1249#else 1250#define ahd_saved_lun_print(regvalue, cur_col, wrap) \ 1251 ahd_print_register(NULL, 0, "SAVED_LUN", 0x13b, regvalue, cur_col, wrap) 1252#endif 1253 1254#if AIC_DEBUG_REGISTERS 1255ahd_reg_print_t ahd_lastphase_print; 1256#else 1257#define ahd_lastphase_print(regvalue, cur_col, wrap) \ 1258 ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap) 1259#endif 1260 1261#if AIC_DEBUG_REGISTERS 1262ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print; 1263#else 1264#define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \ 1265 ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x13d, regvalue, cur_col, wrap) 1266#endif 1267 1268#if AIC_DEBUG_REGISTERS 1269ahd_reg_print_t ahd_kernel_tqinpos_print; 1270#else 1271#define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \ 1272 ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x13e, regvalue, cur_col, wrap) 1273#endif 1274 1275#if AIC_DEBUG_REGISTERS 1276ahd_reg_print_t ahd_tqinpos_print; 1277#else 1278#define ahd_tqinpos_print(regvalue, cur_col, wrap) \ 1279 ahd_print_register(NULL, 0, "TQINPOS", 0x13f, regvalue, cur_col, wrap) 1280#endif 1281 1282#if AIC_DEBUG_REGISTERS 1283ahd_reg_print_t ahd_shared_data_addr_print; 1284#else 1285#define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \ 1286 ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x140, regvalue, cur_col, wrap) 1287#endif 1288 1289#if AIC_DEBUG_REGISTERS 1290ahd_reg_print_t ahd_qoutfifo_next_addr_print; 1291#else 1292#define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \ 1293 ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x144, regvalue, cur_col, wrap) 1294#endif 1295 1296#if AIC_DEBUG_REGISTERS 1297ahd_reg_print_t ahd_arg_1_print; 1298#else 1299#define ahd_arg_1_print(regvalue, cur_col, wrap) \ 1300 ahd_print_register(NULL, 0, "ARG_1", 0x148, regvalue, cur_col, wrap) 1301#endif 1302 1303#if AIC_DEBUG_REGISTERS 1304ahd_reg_print_t ahd_arg_2_print; 1305#else 1306#define ahd_arg_2_print(regvalue, cur_col, wrap) \ 1307 ahd_print_register(NULL, 0, "ARG_2", 0x149, regvalue, cur_col, wrap) 1308#endif 1309 1310#if AIC_DEBUG_REGISTERS 1311ahd_reg_print_t ahd_last_msg_print; 1312#else 1313#define ahd_last_msg_print(regvalue, cur_col, wrap) \ 1314 ahd_print_register(NULL, 0, "LAST_MSG", 0x14a, regvalue, cur_col, wrap) 1315#endif 1316 1317#if AIC_DEBUG_REGISTERS 1318ahd_reg_print_t ahd_scsiseq_template_print; 1319#else 1320#define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \ 1321 ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x14b, regvalue, cur_col, wrap) 1322#endif 1323 1324#if AIC_DEBUG_REGISTERS 1325ahd_reg_print_t ahd_initiator_tag_print; 1326#else 1327#define ahd_initiator_tag_print(regvalue, cur_col, wrap) \ 1328 ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x14c, regvalue, cur_col, wrap) 1329#endif 1330 1331#if AIC_DEBUG_REGISTERS 1332ahd_reg_print_t ahd_seq_flags2_print; 1333#else 1334#define ahd_seq_flags2_print(regvalue, cur_col, wrap) \ 1335 ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap) 1336#endif 1337 1338#if AIC_DEBUG_REGISTERS 1339ahd_reg_print_t ahd_allocfifo_scbptr_print; 1340#else 1341#define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \ 1342 ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x14e, regvalue, cur_col, wrap) 1343#endif 1344 1345#if AIC_DEBUG_REGISTERS 1346ahd_reg_print_t ahd_int_coalescing_timer_print; 1347#else 1348#define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \ 1349 ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x150, regvalue, cur_col, wrap) 1350#endif 1351 1352#if AIC_DEBUG_REGISTERS 1353ahd_reg_print_t ahd_int_coalescing_maxcmds_print; 1354#else 1355#define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \ 1356 ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x152, regvalue, cur_col, wrap) 1357#endif 1358 1359#if AIC_DEBUG_REGISTERS 1360ahd_reg_print_t ahd_int_coalescing_mincmds_print; 1361#else 1362#define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \ 1363 ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x153, regvalue, cur_col, wrap) 1364#endif 1365 1366#if AIC_DEBUG_REGISTERS 1367ahd_reg_print_t ahd_cmds_pending_print; 1368#else 1369#define ahd_cmds_pending_print(regvalue, cur_col, wrap) \ 1370 ahd_print_register(NULL, 0, "CMDS_PENDING", 0x154, regvalue, cur_col, wrap) 1371#endif 1372 1373#if AIC_DEBUG_REGISTERS 1374ahd_reg_print_t ahd_int_coalescing_cmdcount_print; 1375#else 1376#define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \ 1377 ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x156, regvalue, cur_col, wrap) 1378#endif 1379 1380#if AIC_DEBUG_REGISTERS 1381ahd_reg_print_t ahd_local_hs_mailbox_print; 1382#else 1383#define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \ 1384 ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x157, regvalue, cur_col, wrap) 1385#endif 1386 1387#if AIC_DEBUG_REGISTERS 1388ahd_reg_print_t ahd_cmdsize_table_print; 1389#else 1390#define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \ 1391 ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x158, regvalue, cur_col, wrap) 1392#endif 1393 1394#if AIC_DEBUG_REGISTERS 1395ahd_reg_print_t ahd_mk_message_scb_print; 1396#else 1397#define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \ 1398 ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap) 1399#endif 1400 1401#if AIC_DEBUG_REGISTERS 1402ahd_reg_print_t ahd_mk_message_scsiid_print; 1403#else 1404#define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \ 1405 ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap) 1406#endif 1407 1408#if AIC_DEBUG_REGISTERS 1409ahd_reg_print_t ahd_scb_residual_datacnt_print; 1410#else 1411#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \ 1412 ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap) 1413#endif 1414 1415#if AIC_DEBUG_REGISTERS 1416ahd_reg_print_t ahd_scb_base_print; 1417#else 1418#define ahd_scb_base_print(regvalue, cur_col, wrap) \ 1419 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap) 1420#endif 1421 1422#if AIC_DEBUG_REGISTERS 1423ahd_reg_print_t ahd_scb_residual_sgptr_print; 1424#else 1425#define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \ 1426 ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap) 1427#endif 1428 1429#if AIC_DEBUG_REGISTERS 1430ahd_reg_print_t ahd_scb_scsi_status_print; 1431#else 1432#define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \ 1433 ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap) 1434#endif 1435 1436#if AIC_DEBUG_REGISTERS 1437ahd_reg_print_t ahd_scb_sense_busaddr_print; 1438#else 1439#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \ 1440 ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap) 1441#endif 1442 1443#if AIC_DEBUG_REGISTERS 1444ahd_reg_print_t ahd_scb_tag_print; 1445#else 1446#define ahd_scb_tag_print(regvalue, cur_col, wrap) \ 1447 ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap) 1448#endif 1449 1450#if AIC_DEBUG_REGISTERS 1451ahd_reg_print_t ahd_scb_control_print; 1452#else 1453#define ahd_scb_control_print(regvalue, cur_col, wrap) \ 1454 ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap) 1455#endif 1456 1457#if AIC_DEBUG_REGISTERS 1458ahd_reg_print_t ahd_scb_scsiid_print; 1459#else 1460#define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \ 1461 ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap) 1462#endif 1463 1464#if AIC_DEBUG_REGISTERS 1465ahd_reg_print_t ahd_scb_lun_print; 1466#else 1467#define ahd_scb_lun_print(regvalue, cur_col, wrap) \ 1468 ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap) 1469#endif 1470 1471#if AIC_DEBUG_REGISTERS 1472ahd_reg_print_t ahd_scb_task_attribute_print; 1473#else 1474#define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \ 1475 ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap) 1476#endif 1477 1478#if AIC_DEBUG_REGISTERS 1479ahd_reg_print_t ahd_scb_cdb_len_print; 1480#else 1481#define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \ 1482 ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap) 1483#endif 1484 1485#if AIC_DEBUG_REGISTERS 1486ahd_reg_print_t ahd_scb_task_management_print; 1487#else 1488#define ahd_scb_task_management_print(regvalue, cur_col, wrap) \ 1489 ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap) 1490#endif 1491 1492#if AIC_DEBUG_REGISTERS 1493ahd_reg_print_t ahd_scb_dataptr_print; 1494#else 1495#define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \ 1496 ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap) 1497#endif 1498 1499#if AIC_DEBUG_REGISTERS 1500ahd_reg_print_t ahd_scb_datacnt_print; 1501#else 1502#define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \ 1503 ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap) 1504#endif 1505 1506#if AIC_DEBUG_REGISTERS 1507ahd_reg_print_t ahd_scb_sgptr_print; 1508#else 1509#define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \ 1510 ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap) 1511#endif 1512 1513#if AIC_DEBUG_REGISTERS 1514ahd_reg_print_t ahd_scb_busaddr_print; 1515#else 1516#define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \ 1517 ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap) 1518#endif 1519 1520#if AIC_DEBUG_REGISTERS 1521ahd_reg_print_t ahd_scb_next_print; 1522#else 1523#define ahd_scb_next_print(regvalue, cur_col, wrap) \ 1524 ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap) 1525#endif 1526 1527#if AIC_DEBUG_REGISTERS 1528ahd_reg_print_t ahd_scb_next2_print; 1529#else 1530#define ahd_scb_next2_print(regvalue, cur_col, wrap) \ 1531 ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap) 1532#endif 1533 1534#if AIC_DEBUG_REGISTERS 1535ahd_reg_print_t ahd_scb_disconnected_lists_print; 1536#else 1537#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \ 1538 ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap) 1539#endif 1540 1541 1542#define MODE_PTR 0x00 1543#define DST_MODE 0x70 1544#define SRC_MODE 0x07 1545 1546#define INTSTAT 0x01 1547#define INT_PEND 0xff 1548#define HWERRINT 0x80 1549#define BRKADRINT 0x40 1550#define SWTMINT 0x20 1551#define PCIINT 0x10 1552#define SCSIINT 0x08 1553#define SEQINT 0x04 1554#define CMDCMPLT 0x02 1555#define SPLTINT 0x01 1556 1557#define SEQINTCODE 0x02 1558#define BAD_SCB_STATUS 0x1a 1559#define SAW_HWERR 0x19 1560#define TRACEPOINT3 0x18 1561#define TRACEPOINT2 0x17 1562#define TRACEPOINT1 0x16 1563#define TRACEPOINT0 0x15 1564#define TASKMGMT_CMD_CMPLT_OKAY 0x14 1565#define TASKMGMT_FUNC_COMPLETE 0x13 1566#define ENTERING_NONPACK 0x12 1567#define CFG4OVERRUN 0x11 1568#define STATUS_OVERRUN 0x10 1569#define CFG4ISTAT_INTR 0x0f 1570#define INVALID_SEQINT 0x0e 1571#define ILLEGAL_PHASE 0x0d 1572#define DUMP_CARD_STATE 0x0c 1573#define MISSED_BUSFREE 0x0b 1574#define MKMSG_FAILED 0x0a 1575#define DATA_OVERRUN 0x09 1576#define BAD_STATUS 0x08 1577#define HOST_MSG_LOOP 0x07 1578#define PDATA_REINIT 0x06 1579#define IGN_WIDE_RES 0x05 1580#define NO_MATCH 0x04 1581#define PROTO_VIOLATION 0x03 1582#define SEND_REJECT 0x02 1583#define BAD_PHASE 0x01 1584#define NO_SEQINT 0x00 1585 1586#define CLRINT 0x03 1587#define CLRHWERRINT 0x80 1588#define CLRBRKADRINT 0x40 1589#define CLRSWTMINT 0x20 1590#define CLRPCIINT 0x10 1591#define CLRSCSIINT 0x08 1592#define CLRSEQINT 0x04 1593#define CLRCMDINT 0x02 1594#define CLRSPLTINT 0x01 1595 1596#define ERROR 0x04 1597#define CIOPARERR 0x80 1598#define CIOACCESFAIL 0x40 1599#define MPARERR 0x20 1600#define DPARERR 0x10 1601#define SQPARERR 0x08 1602#define ILLOPCODE 0x04 1603#define DSCTMOUT 0x02 1604 1605#define CLRERR 0x04 1606#define CLRCIOPARERR 0x80 1607#define CLRCIOACCESFAIL 0x40 1608#define CLRMPARERR 0x20 1609#define CLRDPARERR 0x10 1610#define CLRSQPARERR 0x08 1611#define CLRILLOPCODE 0x04 1612#define CLRDSCTMOUT 0x02 1613 1614#define HCNTRL 0x05 1615#define SEQ_RESET 0x80 1616#define POWRDN 0x40 1617#define SWINT 0x10 1618#define SWTIMER_START_B 0x08 1619#define PAUSE 0x04 1620#define INTEN 0x02 1621#define CHIPRST 0x01 1622#define CHIPRSTACK 0x01 1623 1624#define HNSCB_QOFF 0x06 1625 1626#define HESCB_QOFF 0x08 1627 1628#define HS_MAILBOX 0x0b 1629#define HOST_TQINPOS 0x80 1630#define ENINT_COALESCE 0x40 1631 1632#define SEQINTSTAT 0x0c 1633#define SEQ_SWTMRTO 0x10 1634#define SEQ_SEQINT 0x08 1635#define SEQ_SCSIINT 0x04 1636#define SEQ_PCIINT 0x02 1637#define SEQ_SPLTINT 0x01 1638 1639#define CLRSEQINTSTAT 0x0c 1640#define CLRSEQ_SWTMRTO 0x10 1641#define CLRSEQ_SEQINT 0x08 1642#define CLRSEQ_SCSIINT 0x04 1643#define CLRSEQ_PCIINT 0x02 1644#define CLRSEQ_SPLTINT 0x01 1645 1646#define SWTIMER 0x0e 1647 1648#define SNSCB_QOFF 0x10 1649 1650#define SESCB_QOFF 0x12 1651 1652#define SDSCB_QOFF 0x14 1653 1654#define QOFF_CTLSTA 0x16 1655#define EMPTY_SCB_AVAIL 0x80 1656#define NEW_SCB_AVAIL 0x40 1657#define SDSCB_ROLLOVR 0x20 1658#define HS_MAILBOX_ACT 0x10 1659#define SCB_QSIZE 0x0f 1660#define SCB_QSIZE_16384 0x0c 1661#define SCB_QSIZE_8192 0x0b 1662#define SCB_QSIZE_4096 0x0a 1663#define SCB_QSIZE_2048 0x09 1664#define SCB_QSIZE_1024 0x08 1665#define SCB_QSIZE_512 0x07 1666#define SCB_QSIZE_256 0x06 1667#define SCB_QSIZE_128 0x05 1668#define SCB_QSIZE_64 0x04 1669#define SCB_QSIZE_32 0x03 1670#define SCB_QSIZE_16 0x02 1671#define SCB_QSIZE_8 0x01 1672#define SCB_QSIZE_4 0x00 1673 1674#define INTCTL 0x18 1675#define SWTMINTMASK 0x80 1676#define SWTMINTEN 0x40 1677#define SWTIMER_START 0x20 1678#define AUTOCLRCMDINT 0x10 1679#define PCIINTEN 0x08 1680#define SCSIINTEN 0x04 1681#define SEQINTEN 0x02 1682#define SPLTINTEN 0x01 1683 1684#define DFCNTRL 0x19 1685#define SCSIENWRDIS 0x40 1686#define SCSIENACK 0x20 1687#define DIRECTIONACK 0x04 1688#define FIFOFLUSHACK 0x02 1689#define DIRECTIONEN 0x01 1690 1691#define DSCOMMAND0 0x19 1692#define CACHETHEN 0x80 1693#define DPARCKEN 0x40 1694#define MPARCKEN 0x20 1695#define EXTREQLCK 0x10 1696#define DISABLE_TWATE 0x02 1697#define CIOPARCKEN 0x01 1698 1699#define DFSTATUS 0x1a 1700#define PRELOAD_AVAIL 0x80 1701#define PKT_PRELOAD_AVAIL 0x40 1702#define MREQPEND 0x10 1703#define HDONE 0x08 1704#define DFTHRESH 0x04 1705#define FIFOFULL 0x02 1706#define FIFOEMP 0x01 1707 1708#define SG_CACHE_SHADOW 0x1b 1709#define ODD_SEG 0x04 1710#define LAST_SEG 0x02 1711#define LAST_SEG_DONE 0x01 1712 1713#define ARBCTL 0x1b 1714#define RESET_HARB 0x80 1715#define RETRY_SWEN 0x08 1716#define USE_TIME 0x07 1717 1718#define SG_CACHE_PRE 0x1b 1719 1720#define TYPEPTR 0x20 1721 1722#define LQIN 0x20 1723 1724#define TAGPTR 0x21 1725 1726#define LUNPTR 0x22 1727 1728#define DATALENPTR 0x23 1729 1730#define STATLENPTR 0x24 1731 1732#define CMDLENPTR 0x25 1733 1734#define ATTRPTR 0x26 1735 1736#define FLAGPTR 0x27 1737 1738#define CMDPTR 0x28 1739 1740#define QNEXTPTR 0x29 1741 1742#define IDPTR 0x2a 1743 1744#define ABRTBYTEPTR 0x2b 1745 1746#define ABRTBITPTR 0x2c 1747 1748#define MAXCMDBYTES 0x2d 1749 1750#define MAXCMD2RCV 0x2e 1751 1752#define SHORTTHRESH 0x2f 1753 1754#define LUNLEN 0x30 1755#define TLUNLEN 0xf0 1756#define ILUNLEN 0x0f 1757 1758#define CDBLIMIT 0x31 1759 1760#define MAXCMD 0x32 1761 1762#define MAXCMDCNT 0x33 1763 1764#define LQRSVD01 0x34 1765 1766#define LQRSVD16 0x35 1767 1768#define LQRSVD17 0x36 1769 1770#define CMDRSVD0 0x37 1771 1772#define LQCTL0 0x38 1773#define LQITARGCLT 0xc0 1774#define LQIINITGCLT 0x30 1775#define LQ0TARGCLT 0x0c 1776#define LQ0INITGCLT 0x03 1777 1778#define LQCTL1 0x38 1779#define PCI2PCI 0x04 1780#define SINGLECMD 0x02 1781#define ABORTPENDING 0x01 1782 1783#define LQCTL2 0x39 1784#define LQIRETRY 0x80 1785#define LQICONTINUE 0x40 1786#define LQITOIDLE 0x20 1787#define LQIPAUSE 0x10 1788#define LQORETRY 0x08 1789#define LQOCONTINUE 0x04 1790#define LQOTOIDLE 0x02 1791#define LQOPAUSE 0x01 1792 1793#define SCSBIST0 0x39 1794#define GSBISTERR 0x40 1795#define GSBISTDONE 0x20 1796#define GSBISTRUN 0x10 1797#define OSBISTERR 0x04 1798#define OSBISTDONE 0x02 1799#define OSBISTRUN 0x01 1800 1801#define SCSISEQ0 0x3a 1802#define TEMODEO 0x80 1803#define ENSELO 0x40 1804#define ENARBO 0x20 1805#define FORCEBUSFREE 0x10 1806#define SCSIRSTO 0x01 1807 1808#define SCSBIST1 0x3a 1809#define NTBISTERR 0x04 1810#define NTBISTDONE 0x02 1811#define NTBISTRUN 0x01 1812 1813#define SCSISEQ1 0x3b 1814 1815#define BUSINITID 0x3c 1816 1817#define SXFRCTL0 0x3c 1818#define DFON 0x80 1819#define DFPEXP 0x40 1820#define BIOSCANCELEN 0x10 1821#define SPIOEN 0x08 1822 1823#define DLCOUNT 0x3c 1824 1825#define SXFRCTL1 0x3d 1826#define BITBUCKET 0x80 1827#define ENSACHK 0x40 1828#define ENSPCHK 0x20 1829#define STIMESEL 0x18 1830#define ENSTIMER 0x04 1831#define ACTNEGEN 0x02 1832#define STPWEN 0x01 1833 1834#define BUSTARGID 0x3e 1835 1836#define SXFRCTL2 0x3e 1837#define AUTORSTDIS 0x10 1838#define CMDDMAEN 0x08 1839#define ASU 0x07 1840 1841#define DFFSTAT 0x3f 1842#define CURRFIFO 0x03 1843#define FIFO1FREE 0x20 1844#define FIFO0FREE 0x10 1845#define CURRFIFO_NONE 0x03 1846#define CURRFIFO_1 0x01 1847#define CURRFIFO_0 0x00 1848 1849#define MULTARGID 0x40 1850 1851#define SCSISIGO 0x40 1852#define CDO 0x80 1853#define IOO 0x40 1854#define MSGO 0x20 1855#define ATNO 0x10 1856#define SELO 0x08 1857#define BSYO 0x04 1858#define REQO 0x02 1859#define ACKO 0x01 1860 1861#define SCSISIGI 0x41 1862#define ATNI 0x10 1863#define SELI 0x08 1864#define BSYI 0x04 1865#define REQI 0x02 1866#define ACKI 0x01 1867 1868#define SCSIPHASE 0x42 1869#define STATUS_PHASE 0x20 1870#define COMMAND_PHASE 0x10 1871#define MSG_IN_PHASE 0x08 1872#define MSG_OUT_PHASE 0x04 1873#define DATA_PHASE_MASK 0x03 1874#define DATA_IN_PHASE 0x02 1875#define DATA_OUT_PHASE 0x01 1876 1877#define SCSIDAT0_IMG 0x43 1878 1879#define SCSIDAT 0x44 1880 1881#define SCSIBUS 0x46 1882 1883#define TARGIDIN 0x48 1884#define CLKOUT 0x80 1885#define TARGID 0x0f 1886 1887#define SELID 0x49 1888#define SELID_MASK 0xf0 1889#define ONEBIT 0x08 1890 1891#define OPTIONMODE 0x4a 1892#define OPTIONMODE_DEFAULTS 0x02 1893#define BIOSCANCTL 0x80 1894#define AUTOACKEN 0x40 1895#define BIASCANCTL 0x20 1896#define BUSFREEREV 0x10 1897#define ENDGFORMCHK 0x04 1898#define AUTO_MSGOUT_DE 0x02 1899 1900#define SBLKCTL 0x4a 1901#define DIAGLEDEN 0x80 1902#define DIAGLEDON 0x40 1903#define ENAB40 0x08 1904#define ENAB20 0x04 1905#define SELWIDE 0x02 1906 1907#define SSTAT0 0x4b 1908#define TARGET 0x80 1909#define SELDO 0x40 1910#define SELDI 0x20 1911#define SELINGO 0x10 1912#define IOERR 0x08 1913#define OVERRUN 0x04 1914#define SPIORDY 0x02 1915#define ARBDO 0x01 1916 1917#define SIMODE0 0x4b 1918#define ENSELDO 0x40 1919#define ENSELDI 0x20 1920#define ENSELINGO 0x10 1921#define ENIOERR 0x08 1922#define ENOVERRUN 0x04 1923#define ENSPIORDY 0x02 1924#define ENARBDO 0x01 1925 1926#define CLRSINT0 0x4b 1927#define CLRSELDO 0x40 1928#define CLRSELDI 0x20 1929#define CLRSELINGO 0x10 1930#define CLRIOERR 0x08 1931#define CLROVERRUN 0x04 1932#define CLRSPIORDY 0x02 1933#define CLRARBDO 0x01 1934 1935#define SSTAT1 0x4c 1936#define SELTO 0x80 1937#define ATNTARG 0x40 1938#define SCSIRSTI 0x20 1939#define PHASEMIS 0x10 1940#define BUSFREE 0x08 1941#define SCSIPERR 0x04 1942#define STRB2FAST 0x02 1943#define REQINIT 0x01 1944 1945#define CLRSINT1 0x4c 1946#define CLRSELTIMEO 0x80 1947#define CLRATNO 0x40 1948#define CLRSCSIRSTI 0x20 1949#define CLRBUSFREE 0x08 1950#define CLRSCSIPERR 0x04 1951#define CLRSTRB2FAST 0x02 1952#define CLRREQINIT 0x01 1953 1954#define SSTAT2 0x4d 1955#define BUSFREETIME 0xc0 1956#define NONPACKREQ 0x20 1957#define EXP_ACTIVE 0x10 1958#define BSYX 0x08 1959#define WIDE_RES 0x04 1960#define SDONE 0x02 1961#define DMADONE 0x01 1962#define BUSFREE_DFF1 0xc0 1963#define BUSFREE_DFF0 0x80 1964#define BUSFREE_LQO 0x40 1965 1966#define SIMODE2 0x4d 1967#define ENWIDE_RES 0x04 1968#define ENSDONE 0x02 1969#define ENDMADONE 0x01 1970 1971#define CLRSINT2 0x4d 1972#define CLRNONPACKREQ 0x20 1973#define CLRWIDE_RES 0x04 1974#define CLRSDONE 0x02 1975#define CLRDMADONE 0x01 1976 1977#define PERRDIAG 0x4e 1978#define HIZERO 0x80 1979#define HIPERR 0x40 1980#define PREVPHASE 0x20 1981#define PARITYERR 0x10 1982#define AIPERR 0x08 1983#define CRCERR 0x04 1984#define DGFORMERR 0x02 1985#define DTERR 0x01 1986 1987#define LQISTATE 0x4e 1988 1989#define SOFFCNT 0x4f 1990 1991#define LQOSTATE 0x4f 1992 1993#define LQISTAT0 0x50 1994#define LQIATNQAS 0x20 1995#define LQICRCT1 0x10 1996#define LQICRCT2 0x08 1997#define LQIBADLQT 0x04 1998#define LQIATNLQ 0x02 1999#define LQIATNCMD 0x01 2000 2001#define LQIMODE0 0x50 2002#define ENLQIATNQASK 0x20 2003#define ENLQICRCT1 0x10 2004#define ENLQICRCT2 0x08 2005#define ENLQIBADLQT 0x04 2006#define ENLQIATNLQ 0x02 2007#define ENLQIATNCMD 0x01 2008 2009#define CLRLQIINT0 0x50 2010#define CLRLQIATNQAS 0x20 2011#define CLRLQICRCT1 0x10 2012#define CLRLQICRCT2 0x08 2013#define CLRLQIBADLQT 0x04 2014#define CLRLQIATNLQ 0x02 2015#define CLRLQIATNCMD 0x01 2016 2017#define LQIMODE1 0x51 2018#define ENLQIPHASE_LQ 0x80 2019#define ENLQIPHASE_NLQ 0x40 2020#define ENLIQABORT 0x20 2021#define ENLQICRCI_LQ 0x10 2022#define ENLQICRCI_NLQ 0x08 2023#define ENLQIBADLQI 0x04 2024#define ENLQIOVERI_LQ 0x02 2025#define ENLQIOVERI_NLQ 0x01 2026 2027#define LQISTAT1 0x51 2028#define LQIPHASE_LQ 0x80 2029#define LQIPHASE_NLQ 0x40 2030#define LQIABORT 0x20 2031#define LQICRCI_LQ 0x10 2032#define LQICRCI_NLQ 0x08 2033#define LQIBADLQI 0x04 2034#define LQIOVERI_LQ 0x02 2035#define LQIOVERI_NLQ 0x01 2036 2037#define CLRLQIINT1 0x51 2038#define CLRLQIPHASE_LQ 0x80 2039#define CLRLQIPHASE_NLQ 0x40 2040#define CLRLIQABORT 0x20 2041#define CLRLQICRCI_LQ 0x10 2042#define CLRLQICRCI_NLQ 0x08 2043#define CLRLQIBADLQI 0x04 2044#define CLRLQIOVERI_LQ 0x02 2045#define CLRLQIOVERI_NLQ 0x01 2046 2047#define LQISTAT2 0x52 2048#define PACKETIZED 0x80 2049#define LQIPHASE_OUTPKT 0x40 2050#define LQIWORKONLQ 0x20 2051#define LQIWAITFIFO 0x10 2052#define LQISTOPPKT 0x08 2053#define LQISTOPLQ 0x04 2054#define LQISTOPCMD 0x02 2055#define LQIGSAVAIL 0x01 2056 2057#define SSTAT3 0x53 2058#define NTRAMPERR 0x02 2059#define OSRAMPERR 0x01 2060 2061#define SIMODE3 0x53 2062#define ENNTRAMPERR 0x02 2063#define ENOSRAMPERR 0x01 2064 2065#define CLRSINT3 0x53 2066#define CLRNTRAMPERR 0x02 2067#define CLROSRAMPERR 0x01 2068 2069#define LQOSTAT0 0x54 2070#define LQOTARGSCBPERR 0x10 2071#define LQOSTOPT2 0x08 2072#define LQOATNLQ 0x04 2073#define LQOATNPKT 0x02 2074#define LQOTCRC 0x01 2075 2076#define CLRLQOINT0 0x54 2077#define CLRLQOTARGSCBPERR 0x10 2078#define CLRLQOSTOPT2 0x08 2079#define CLRLQOATNLQ 0x04 2080#define CLRLQOATNPKT 0x02 2081#define CLRLQOTCRC 0x01 2082 2083#define LQOMODE0 0x54 2084#define ENLQOTARGSCBPERR 0x10 2085#define ENLQOSTOPT2 0x08 2086#define ENLQOATNLQ 0x04 2087#define ENLQOATNPKT 0x02 2088#define ENLQOTCRC 0x01 2089 2090#define LQOMODE1 0x55 2091#define ENLQOINITSCBPERR 0x10 2092#define ENLQOSTOPI2 0x08 2093#define ENLQOBADQAS 0x04 2094#define ENLQOBUSFREE 0x02 2095#define ENLQOPHACHGINPKT 0x01 2096 2097#define LQOSTAT1 0x55 2098#define LQOINITSCBPERR 0x10 2099#define LQOSTOPI2 0x08 2100#define LQOBADQAS 0x04 2101#define LQOBUSFREE 0x02 2102#define LQOPHACHGINPKT 0x01 2103 2104#define CLRLQOINT1 0x55 2105#define CLRLQOINITSCBPERR 0x10 2106#define CLRLQOSTOPI2 0x08 2107#define CLRLQOBADQAS 0x04 2108#define CLRLQOBUSFREE 0x02 2109#define CLRLQOPHACHGINPKT 0x01 2110 2111#define LQOSTAT2 0x56 2112#define LQOPKT 0xe0 2113#define LQOWAITFIFO 0x10 2114#define LQOPHACHGOUTPKT 0x02 2115#define LQOSTOP0 0x01 2116 2117#define OS_SPACE_CNT 0x56 2118 2119#define SIMODE1 0x57 2120#define ENSELTIMO 0x80 2121#define ENATNTARG 0x40 2122#define ENSCSIRST 0x20 2123#define ENPHASEMIS 0x10 2124#define ENBUSFREE 0x08 2125#define ENSCSIPERR 0x04 2126#define ENSTRB2FAST 0x02 2127#define ENREQINIT 0x01 2128 2129#define GSFIFO 0x58 2130 2131#define DFFSXFRCTL 0x5a 2132#define DFFBITBUCKET 0x08 2133#define CLRSHCNT 0x04 2134#define CLRCHN 0x02 2135#define RSTCHN 0x01 2136 2137#define LQOSCSCTL 0x5a 2138#define LQOH2A_VERSION 0x80 2139#define LQOBUSETDLY 0x40 2140#define LQONOHOLDLACK 0x02 2141#define LQONOCHKOVER 0x01 2142 2143#define NEXTSCB 0x5a 2144 2145#define CLRSEQINTSRC 0x5b 2146#define CLRCTXTDONE 0x40 2147#define CLRSAVEPTRS 0x20 2148#define CLRCFG4DATA 0x10 2149#define CLRCFG4ISTAT 0x08 2150#define CLRCFG4TSTAT 0x04 2151#define CLRCFG4ICMD 0x02 2152#define CLRCFG4TCMD 0x01 2153 2154#define SEQINTSRC 0x5b 2155#define CTXTDONE 0x40 2156#define SAVEPTRS 0x20 2157#define CFG4DATA 0x10 2158#define CFG4ISTAT 0x08 2159#define CFG4TSTAT 0x04 2160#define CFG4ICMD 0x02 2161#define CFG4TCMD 0x01 2162 2163#define SEQIMODE 0x5c 2164#define ENCTXTDONE 0x40 2165#define ENSAVEPTRS 0x20 2166#define ENCFG4DATA 0x10 2167#define ENCFG4ISTAT 0x08 2168#define ENCFG4TSTAT 0x04 2169#define ENCFG4ICMD 0x02 2170#define ENCFG4TCMD 0x01 2171 2172#define CURRSCB 0x5c 2173 2174#define MDFFSTAT 0x5d 2175#define SHCNTNEGATIVE 0x40 2176#define SHCNTMINUS1 0x20 2177#define LASTSDONE 0x10 2178#define SHVALID 0x08 2179#define DLZERO 0x04 2180#define DATAINFIFO 0x02 2181#define FIFOFREE 0x01 2182 2183#define CRCCONTROL 0x5d 2184#define CRCVALCHKEN 0x40 2185 2186#define DFFTAG 0x5e 2187 2188#define SCSITEST 0x5e 2189#define CNTRTEST 0x08 2190#define SEL_TXPLL_DEBUG 0x04 2191 2192#define LASTSCB 0x5e 2193 2194#define IOPDNCTL 0x5f 2195#define DISABLE_OE 0x80 2196#define PDN_IDIST 0x04 2197#define PDN_DIFFSENSE 0x01 2198 2199#define DGRPCRCI 0x60 2200 2201#define SHADDR 0x60 2202 2203#define NEGOADDR 0x60 2204 2205#define NEGPERIOD 0x61 2206 2207#define NEGOFFSET 0x62 2208 2209#define PACKCRCI 0x62 2210 2211#define NEGPPROPTS 0x63 2212#define PPROPT_PACE 0x08 2213#define PPROPT_QAS 0x04 2214#define PPROPT_DT 0x02 2215#define PPROPT_IUT 0x01 2216 2217#define NEGCONOPTS 0x64 2218#define ENSNAPSHOT 0x40 2219#define RTI_WRTDIS 0x20 2220#define RTI_OVRDTRN 0x10 2221#define ENSLOWCRC 0x08 2222#define ENAUTOATNI 0x04 2223#define ENAUTOATNO 0x02 2224#define WIDEXFER 0x01 2225 2226#define ANNEXCOL 0x65 2227 2228#define ANNEXDAT 0x66 2229 2230#define SCSCHKN 0x66 2231#define BIDICHKDIS 0x80 2232#define STSELSKIDDIS 0x40 2233#define CURRFIFODEF 0x20 2234#define WIDERESEN 0x10 2235#define SDONEMSKDIS 0x08 2236#define DFFACTCLR 0x04 2237#define SHVALIDSTDIS 0x02 2238#define LSTSGCLRDIS 0x01 2239 2240#define IOWNID 0x67 2241 2242#define PLL960CTL0 0x68 2243 2244#define SHCNT 0x68 2245 2246#define TOWNID 0x69 2247 2248#define PLL960CTL1 0x69 2249 2250#define PLL960CNT0 0x6a 2251 2252#define XSIG 0x6a 2253 2254#define SELOID 0x6b 2255 2256#define FAIRNESS 0x6c 2257 2258#define PLL400CTL0 0x6c 2259#define PLL_VCOSEL 0x80 2260#define PLL_PWDN 0x40 2261#define PLL_NS 0x30 2262#define PLL_ENLUD 0x08 2263#define PLL_ENLPF 0x04 2264#define PLL_DLPF 0x02 2265#define PLL_ENFBM 0x01 2266 2267#define PLL400CTL1 0x6d 2268#define PLL_CNTEN 0x80 2269#define PLL_CNTCLR 0x40 2270#define PLL_RST 0x01 2271 2272#define UNFAIRNESS 0x6e 2273 2274#define PLL400CNT0 0x6e 2275 2276#define HADDR 0x70 2277 2278#define HODMAADR 0x70 2279 2280#define PLLDELAY 0x70 2281#define SPLIT_DROP_REQ 0x80 2282 2283#define HCNT 0x78 2284 2285#define HODMACNT 0x78 2286 2287#define HODMAEN 0x7a 2288 2289#define SGHADDR 0x7c 2290 2291#define SCBHADDR 0x7c 2292 2293#define SGHCNT 0x84 2294 2295#define SCBHCNT 0x84 2296 2297#define DFF_THRSH 0x88 2298#define WR_DFTHRSH 0x70 2299#define RD_DFTHRSH 0x07 2300#define WR_DFTHRSH_MAX 0x70 2301#define WR_DFTHRSH_90 0x60 2302#define WR_DFTHRSH_85 0x50 2303#define WR_DFTHRSH_75 0x40 2304#define WR_DFTHRSH_63 0x30 2305#define WR_DFTHRSH_50 0x20 2306#define WR_DFTHRSH_25 0x10 2307#define RD_DFTHRSH_MAX 0x07 2308#define RD_DFTHRSH_90 0x06 2309#define RD_DFTHRSH_85 0x05 2310#define RD_DFTHRSH_75 0x04 2311#define RD_DFTHRSH_63 0x03 2312#define RD_DFTHRSH_50 0x02 2313#define RD_DFTHRSH_25 0x01 2314#define RD_DFTHRSH_MIN 0x00 2315#define WR_DFTHRSH_MIN 0x00 2316 2317#define ROMADDR 0x8a 2318 2319#define ROMCNTRL 0x8d 2320#define ROMOP 0xe0 2321#define ROMSPD 0x18 2322#define REPEAT 0x02 2323#define RDY 0x01 2324 2325#define ROMDATA 0x8e 2326 2327#define CMCRXMSG0 0x90 2328 2329#define OVLYRXMSG0 0x90 2330 2331#define DCHRXMSG0 0x90 2332 2333#define ROENABLE 0x90 2334#define MSIROEN 0x20 2335#define OVLYROEN 0x10 2336#define CMCROEN 0x08 2337#define SGROEN 0x04 2338#define DCH1ROEN 0x02 2339#define DCH0ROEN 0x01 2340 2341#define OVLYRXMSG1 0x91 2342 2343#define CMCRXMSG1 0x91 2344 2345#define DCHRXMSG1 0x91 2346 2347#define NSENABLE 0x91 2348#define MSINSEN 0x20 2349#define OVLYNSEN 0x10 2350#define CMCNSEN 0x08 2351#define SGNSEN 0x04 2352#define DCH1NSEN 0x02 2353#define DCH0NSEN 0x01 2354 2355#define DCHRXMSG2 0x92 2356 2357#define CMCRXMSG2 0x92 2358 2359#define OST 0x92 2360 2361#define OVLYRXMSG2 0x92 2362 2363#define DCHRXMSG3 0x93 2364 2365#define OVLYRXMSG3 0x93 2366 2367#define CMCRXMSG3 0x93 2368 2369#define PCIXCTL 0x93 2370#define SERRPULSE 0x80 2371#define UNEXPSCIEN 0x20 2372#define SPLTSMADIS 0x10 2373#define SPLTSTADIS 0x08 2374#define SRSPDPEEN 0x04 2375#define TSCSERREN 0x02 2376#define CMPABCDIS 0x01 2377 2378#define CMCSEQBCNT 0x94 2379 2380#define OVLYSEQBCNT 0x94 2381 2382#define DCHSEQBCNT 0x94 2383 2384#define DCHSPLTSTAT0 0x96 2385 2386#define OVLYSPLTSTAT0 0x96 2387 2388#define CMCSPLTSTAT0 0x96 2389 2390#define OVLYSPLTSTAT1 0x97 2391 2392#define DCHSPLTSTAT1 0x97 2393 2394#define CMCSPLTSTAT1 0x97 2395 2396#define SGRXMSG0 0x98 2397#define CDNUM 0xf8 2398#define CFNUM 0x07 2399 2400#define SLVSPLTOUTADR0 0x98 2401#define LOWER_ADDR 0x7f 2402 2403#define SGRXMSG1 0x99 2404#define CBNUM 0xff 2405 2406#define SLVSPLTOUTADR1 0x99 2407#define REQ_DNUM 0xf8 2408#define REQ_FNUM 0x07 2409 2410#define SGRXMSG2 0x9a 2411#define MINDEX 0xff 2412 2413#define SLVSPLTOUTADR2 0x9a 2414#define REQ_BNUM 0xff 2415 2416#define SGRXMSG3 0x9b 2417#define MCLASS 0x0f 2418 2419#define SLVSPLTOUTADR3 0x9b 2420#define TAG_NUM 0x1f 2421#define RLXORD 0x10 2422 2423#define SLVSPLTOUTATTR0 0x9c 2424#define LOWER_BCNT 0xff 2425 2426#define SGSEQBCNT 0x9c 2427 2428#define SLVSPLTOUTATTR1 0x9d 2429#define CMPLT_DNUM 0xf8 2430#define CMPLT_FNUM 0x07 2431 2432#define SGSPLTSTAT0 0x9e 2433#define STAETERM 0x80 2434#define SCBCERR 0x40 2435#define SCADERR 0x20 2436#define SCDATBUCKET 0x10 2437#define CNTNOTCMPLT 0x08 2438#define RXOVRUN 0x04 2439#define RXSCEMSG 0x02 2440#define RXSPLTRSP 0x01 2441 2442#define SLVSPLTOUTATTR2 0x9e 2443#define CMPLT_BNUM 0xff 2444 2445#define SGSPLTSTAT1 0x9f 2446#define RXDATABUCKET 0x01 2447 2448#define SFUNCT 0x9f 2449#define TEST_GROUP 0xf0 2450#define TEST_NUM 0x0f 2451 2452#define DF0PCISTAT 0xa0 2453 2454#define REG0 0xa0 2455 2456#define DF1PCISTAT 0xa1 2457 2458#define SGPCISTAT 0xa2 2459 2460#define REG1 0xa2 2461 2462#define CMCPCISTAT 0xa3 2463 2464#define OVLYPCISTAT 0xa4 2465#define SCAAPERR 0x08 2466#define RDPERR 0x04 2467 2468#define REG_ISR 0xa4 2469 2470#define SG_STATE 0xa6 2471#define FETCH_INPROG 0x04 2472#define LOADING_NEEDED 0x02 2473#define SEGS_AVAIL 0x01 2474 2475#define MSIPCISTAT 0xa6 2476#define RMA 0x20 2477#define RTA 0x10 2478#define CLRPENDMSI 0x08 2479#define DPR 0x01 2480 2481#define TARGPCISTAT 0xa7 2482#define DPE 0x80 2483#define SSE 0x40 2484#define STA 0x08 2485#define TWATERR 0x02 2486 2487#define DATA_COUNT_ODD 0xa7 2488 2489#define SCBPTR 0xa8 2490 2491#define CCSCBACNT 0xab 2492 2493#define SCBAUTOPTR 0xab 2494#define AUSCBPTR_EN 0x80 2495#define SCBPTR_ADDR 0x38 2496#define SCBPTR_OFF 0x07 2497 2498#define CCSGADDR 0xac 2499 2500#define CCSCBADDR 0xac 2501 2502#define CCSCBADR_BK 0xac 2503 2504#define CMC_RAMBIST 0xad 2505#define SG_ELEMENT_SIZE 0x80 2506#define SCBRAMBIST_FAIL 0x40 2507#define SG_BIST_FAIL 0x20 2508#define SG_BIST_EN 0x10 2509#define CMC_BUFFER_BIST_FAIL 0x02 2510#define CMC_BUFFER_BIST_EN 0x01 2511 2512#define CCSCBCTL 0xad 2513#define CCSCBDONE 0x80 2514#define ARRDONE 0x40 2515#define CCARREN 0x10 2516#define CCSCBEN 0x08 2517#define CCSCBDIR 0x04 2518#define CCSCBRESET 0x01 2519 2520#define CCSGCTL 0xad 2521#define CCSGEN 0x0c 2522#define CCSGDONE 0x80 2523#define SG_CACHE_AVAIL 0x10 2524#define CCSGENACK 0x08 2525#define SG_FETCH_REQ 0x02 2526#define CCSGRESET 0x01 2527 2528#define CCSGRAM 0xb0 2529 2530#define FLEXADR 0xb0 2531 2532#define CCSCBRAM 0xb0 2533 2534#define FLEXCNT 0xb3 2535 2536#define FLEXDMASTAT 0xb5 2537#define FLEXDMAERR 0x02 2538#define FLEXDMADONE 0x01 2539 2540#define FLEXDATA 0xb6 2541 2542#define BRDDAT 0xb8 2543 2544#define BRDCTL 0xb9 2545#define FLXARBACK 0x80 2546#define FLXARBREQ 0x40 2547#define BRDADDR 0x38 2548#define BRDEN 0x04 2549#define BRDRW 0x02 2550#define BRDSTB 0x01 2551 2552#define SEEADR 0xba 2553 2554#define SEEDAT 0xbc 2555 2556#define SEECTL 0xbe 2557#define SEEOP_EWDS 0x40 2558#define SEEOP_WALL 0x40 2559#define SEEOP_EWEN 0x40 2560#define SEEOPCODE 0x70 2561#define SEERST 0x02 2562#define SEESTART 0x01 2563#define SEEOP_ERASE 0x70 2564#define SEEOP_READ 0x60 2565#define SEEOP_WRITE 0x50 2566#define SEEOP_ERAL 0x40 2567 2568#define SEESTAT 0xbe 2569#define INIT_DONE 0x80 2570#define LDALTID_L 0x08 2571#define SEEARBACK 0x04 2572#define SEEBUSY 0x02 2573 2574#define SCBCNT 0xbf 2575 2576#define DSPFLTRCTL 0xc0 2577#define FLTRDISABLE 0x20 2578#define EDGESENSE 0x10 2579#define DSPFCNTSEL 0x0f 2580 2581#define DFWADDR 0xc0 2582 2583#define DSPDATACTL 0xc1 2584#define BYPASSENAB 0x80 2585#define DESQDIS 0x10 2586#define RCVROFFSTDIS 0x04 2587#define XMITOFFSTDIS 0x02 2588 2589#define DSPREQCTL 0xc2 2590#define MANREQCTL 0xc0 2591#define MANREQDLY 0x3f 2592 2593#define DFRADDR 0xc2 2594 2595#define DSPACKCTL 0xc3 2596#define MANACKCTL 0xc0 2597#define MANACKDLY 0x3f 2598 2599#define DFDAT 0xc4 2600 2601#define DSPSELECT 0xc4 2602#define AUTOINCEN 0x80 2603#define DSPSEL 0x1f 2604 2605#define WRTBIASCTL 0xc5 2606#define AUTOXBCDIS 0x80 2607#define XMITMANVAL 0x3f 2608 2609#define RCVRBIOSCTL 0xc6 2610#define AUTORBCDIS 0x80 2611#define RCVRMANVAL 0x3f 2612 2613#define WRTBIASCALC 0xc7 2614 2615#define DFPTRS 0xc8 2616 2617#define RCVRBIASCALC 0xc8 2618 2619#define DFBKPTR 0xc9 2620 2621#define SKEWCALC 0xc9 2622 2623#define DFDBCTL 0xcb 2624#define DFF_CIO_WR_RDY 0x20 2625#define DFF_CIO_RD_RDY 0x10 2626#define DFF_DIR_ERR 0x08 2627#define DFF_RAMBIST_FAIL 0x04 2628#define DFF_RAMBIST_DONE 0x02 2629#define DFF_RAMBIST_EN 0x01 2630 2631#define DFSCNT 0xcc 2632 2633#define DFBCNT 0xce 2634 2635#define OVLYADDR 0xd4 2636 2637#define SEQCTL0 0xd6 2638#define PERRORDIS 0x80 2639#define PAUSEDIS 0x40 2640#define FAILDIS 0x20 2641#define FASTMODE 0x10 2642#define BRKADRINTEN 0x08 2643#define STEP 0x04 2644#define SEQRESET 0x02 2645#define LOADRAM 0x01 2646 2647#define SEQCTL1 0xd7 2648#define OVRLAY_DATA_CHK 0x08 2649#define RAMBIST_DONE 0x04 2650#define RAMBIST_FAIL 0x02 2651#define RAMBIST_EN 0x01 2652 2653#define FLAGS 0xd8 2654#define ZERO 0x02 2655#define CARRY 0x01 2656 2657#define SEQINTCTL 0xd9 2658#define INTVEC1DSL 0x80 2659#define INT1_CONTEXT 0x20 2660#define SCS_SEQ_INT1M1 0x10 2661#define SCS_SEQ_INT1M0 0x08 2662#define INTMASK2 0x04 2663#define INTMASK1 0x02 2664#define IRET 0x01 2665 2666#define SEQRAM 0xda 2667 2668#define PRGMCNT 0xde 2669 2670#define ACCUM 0xe0 2671 2672#define SINDEX 0xe2 2673 2674#define DINDEX 0xe4 2675 2676#define BRKADDR0 0xe6 2677 2678#define BRKADDR1 0xe6 2679#define BRKDIS 0x80 2680 2681#define ALLONES 0xe8 2682 2683#define ALLZEROS 0xea 2684 2685#define NONE 0xea 2686 2687#define SINDIR 0xec 2688 2689#define DINDIR 0xed 2690 2691#define FUNCTION1 0xf0 2692 2693#define STACK 0xf2 2694 2695#define INTVEC1_ADDR 0xf4 2696 2697#define CURADDR 0xf4 2698 2699#define LASTADDR 0xf6 2700 2701#define INTVEC2_ADDR 0xf6 2702 2703#define LONGJMP_ADDR 0xf8 2704 2705#define ACCUM_SAVE 0xfa 2706 2707#define AHD_PCI_CONFIG_BASE 0x100 2708 2709#define SRAM_BASE 0x100 2710 2711#define WAITING_SCB_TAILS 0x100 2712 2713#define WAITING_TID_HEAD 0x120 2714 2715#define WAITING_TID_TAIL 0x122 2716 2717#define NEXT_QUEUED_SCB_ADDR 0x124 2718 2719#define COMPLETE_SCB_HEAD 0x128 2720 2721#define COMPLETE_SCB_DMAINPROG_HEAD 0x12a 2722 2723#define COMPLETE_DMA_SCB_HEAD 0x12c 2724 2725#define COMPLETE_DMA_SCB_TAIL 0x12e 2726 2727#define COMPLETE_ON_QFREEZE_HEAD 0x130 2728 2729#define QFREEZE_COUNT 0x132 2730 2731#define KERNEL_QFREEZE_COUNT 0x134 2732 2733#define SAVED_MODE 0x136 2734 2735#define MSG_OUT 0x137 2736 2737#define DMAPARAMS 0x138 2738#define PRELOADEN 0x80 2739#define WIDEODD 0x40 2740#define SCSIEN 0x20 2741#define SDMAENACK 0x10 2742#define SDMAEN 0x10 2743#define HDMAEN 0x08 2744#define HDMAENACK 0x08 2745#define DIRECTION 0x04 2746#define FIFOFLUSH 0x02 2747#define FIFORESET 0x01 2748 2749#define SEQ_FLAGS 0x139 2750#define NOT_IDENTIFIED 0x80 2751#define NO_CDB_SENT 0x40 2752#define TARGET_CMD_IS_TAGGED 0x40 2753#define DPHASE 0x20 2754#define TARG_CMD_PENDING 0x10 2755#define CMDPHASE_PENDING 0x08 2756#define DPHASE_PENDING 0x04 2757#define SPHASE_PENDING 0x02 2758#define NO_DISCONNECT 0x01 2759 2760#define SAVED_SCSIID 0x13a 2761 2762#define SAVED_LUN 0x13b 2763 2764#define LASTPHASE 0x13c 2765#define PHASE_MASK 0xe0 2766#define CDI 0x80 2767#define IOI 0x40 2768#define MSGI 0x20 2769#define P_BUSFREE 0x01 2770#define P_MESGIN 0xe0 2771#define P_STATUS 0xc0 2772#define P_MESGOUT 0xa0 2773#define P_COMMAND 0x80 2774#define P_DATAIN_DT 0x60 2775#define P_DATAIN 0x40 2776#define P_DATAOUT_DT 0x20 2777#define P_DATAOUT 0x00 2778 2779#define QOUTFIFO_ENTRY_VALID_TAG 0x13d 2780 2781#define KERNEL_TQINPOS 0x13e 2782 2783#define TQINPOS 0x13f 2784 2785#define SHARED_DATA_ADDR 0x140 2786 2787#define QOUTFIFO_NEXT_ADDR 0x144 2788 2789#define ARG_1 0x148 2790#define RETURN_1 0x148 2791#define SEND_MSG 0x80 2792#define SEND_SENSE 0x40 2793#define SEND_REJ 0x20 2794#define MSGOUT_PHASEMIS 0x10 2795#define EXIT_MSG_LOOP 0x08 2796#define CONT_MSG_LOOP_WRITE 0x04 2797#define CONT_MSG_LOOP_READ 0x03 2798#define CONT_MSG_LOOP_TARG 0x02 2799 2800#define ARG_2 0x149 2801#define RETURN_2 0x149 2802 2803#define LAST_MSG 0x14a 2804 2805#define SCSISEQ_TEMPLATE 0x14b 2806#define MANUALCTL 0x40 2807#define ENSELI 0x20 2808#define ENRSELI 0x10 2809#define MANUALP 0x0c 2810#define ENAUTOATNP 0x02 2811#define ALTSTIM 0x01 2812 2813#define INITIATOR_TAG 0x14c 2814 2815#define SEQ_FLAGS2 0x14d 2816#define SELECTOUT_QFROZEN 0x04 2817#define TARGET_MSG_PENDING 0x02 2818#define PENDING_MK_MESSAGE 0x01 2819 2820#define ALLOCFIFO_SCBPTR 0x14e 2821 2822#define INT_COALESCING_TIMER 0x150 2823 2824#define INT_COALESCING_MAXCMDS 0x152 2825 2826#define INT_COALESCING_MINCMDS 0x153 2827 2828#define CMDS_PENDING 0x154 2829 2830#define INT_COALESCING_CMDCOUNT 0x156 2831 2832#define LOCAL_HS_MAILBOX 0x157 2833 2834#define CMDSIZE_TABLE 0x158 2835 2836#define MK_MESSAGE_SCB 0x160 2837 2838#define MK_MESSAGE_SCSIID 0x162 2839 2840#define SCB_RESIDUAL_DATACNT 0x180 2841#define SCB_CDB_STORE 0x180 2842#define SCB_HOST_CDB_PTR 0x180 2843 2844#define SCB_BASE 0x180 2845 2846#define SCB_RESIDUAL_SGPTR 0x184 2847#define SG_ADDR_MASK 0xf8 2848#define SG_OVERRUN_RESID 0x02 2849 2850#define SCB_SCSI_STATUS 0x188 2851#define SCB_HOST_CDB_LEN 0x188 2852 2853#define SCB_TARGET_PHASES 0x189 2854 2855#define SCB_TARGET_DATA_DIR 0x18a 2856 2857#define SCB_TARGET_ITAG 0x18b 2858 2859#define SCB_SENSE_BUSADDR 0x18c 2860#define SCB_NEXT_COMPLETE 0x18c 2861 2862#define SCB_TAG 0x190 2863#define SCB_FIFO_USE_COUNT 0x190 2864 2865#define SCB_CONTROL 0x192 2866#define TARGET_SCB 0x80 2867#define DISCENB 0x40 2868#define TAG_ENB 0x20 2869#define MK_MESSAGE 0x10 2870#define STATUS_RCVD 0x08 2871#define DISCONNECTED 0x04 2872#define SCB_TAG_TYPE 0x03 2873 2874#define SCB_SCSIID 0x193 2875#define TID 0xf0 2876#define OID 0x0f 2877 2878#define SCB_LUN 0x194 2879#define LID 0xff 2880 2881#define SCB_TASK_ATTRIBUTE 0x195 2882#define SCB_XFERLEN_ODD 0x01 2883 2884#define SCB_CDB_LEN 0x196 2885#define SCB_CDB_LEN_PTR 0x80 2886 2887#define SCB_TASK_MANAGEMENT 0x197 2888 2889#define SCB_DATAPTR 0x198 2890 2891#define SCB_DATACNT 0x1a0 2892#define SG_LAST_SEG 0x80 2893#define SG_HIGH_ADDR_BITS 0x7f 2894 2895#define SCB_SGPTR 0x1a4 2896#define SG_STATUS_VALID 0x04 2897#define SG_FULL_RESID 0x02 2898#define SG_LIST_NULL 0x01 2899 2900#define SCB_BUSADDR 0x1a8 2901 2902#define SCB_NEXT 0x1ac 2903#define SCB_NEXT_SCB_BUSADDR 0x1ac 2904 2905#define SCB_NEXT2 0x1ae 2906 2907#define SCB_SPARE 0x1b0 2908#define SCB_PKT_LUN 0x1b0 2909 2910#define SCB_DISCONNECTED_LISTS 0x1b8 2911 2912 2913#define CMD_GROUP_CODE_SHIFT 0x05 2914#define STIMESEL_MIN 0x18 2915#define STIMESEL_SHIFT 0x03 2916#define INVALID_ADDR 0x80 2917#define AHD_PRECOMP_MASK 0x07 2918#define TARGET_DATA_IN 0x01 2919#define CCSCBADDR_MAX 0x80 2920#define NUMDSPS 0x14 2921#define SEEOP_EWEN_ADDR 0xc0 2922#define AHD_ANNEXCOL_PER_DEV0 0x04 2923#define DST_MODE_SHIFT 0x04 2924#define AHD_TIMER_MAX_US 0x18ffe7 2925#define AHD_TIMER_MAX_TICKS 0xffff 2926#define AHD_SENSE_BUFSIZE 0x100 2927#define BUS_8_BIT 0x00 2928#define TARGET_CMD_CMPLT 0xfe 2929#define SEEOP_WRAL_ADDR 0x40 2930#define AHD_AMPLITUDE_DEF 0x07 2931#define AHD_PRECOMP_CUTBACK_37 0x07 2932#define AHD_PRECOMP_SHIFT 0x00 2933#define AHD_ANNEXCOL_PRECOMP_SLEW 0x04 2934#define AHD_TIMER_US_PER_TICK 0x19 2935#define SCB_TRANSFER_SIZE_FULL_LUN 0x38 2936#define STATUS_QUEUE_FULL 0x28 2937#define STATUS_BUSY 0x08 2938#define MAX_OFFSET_NON_PACED 0x7f 2939#define MAX_OFFSET_PACED 0xfe 2940#define BUS_32_BIT 0x02 2941#define CCSGADDR_MAX 0x80 2942#define TID_SHIFT 0x04 2943#define MK_MESSAGE_BIT_OFFSET 0x04 2944#define WRTBIASCTL_HP_DEFAULT 0x00 2945#define SEEOP_EWDS_ADDR 0x00 2946#define AHD_AMPLITUDE_SHIFT 0x00 2947#define AHD_AMPLITUDE_MASK 0x07 2948#define AHD_ANNEXCOL_AMPLITUDE 0x06 2949#define AHD_SLEWRATE_DEF_REVA 0x08 2950#define AHD_SLEWRATE_SHIFT 0x03 2951#define AHD_SLEWRATE_MASK 0x78 2952#define AHD_PRECOMP_CUTBACK_29 0x06 2953#define AHD_NUM_PER_DEV_ANNEXCOLS 0x04 2954#define B_CURRFIFO_0 0x02 2955#define LUNLEN_SINGLE_LEVEL_LUN 0x0f 2956#define NVRAM_SCB_OFFSET 0x2c 2957#define STATUS_PKT_SENSE 0xff 2958#define MAX_OFFSET_PACED_BUG 0x7f 2959#define STIMESEL_BUG_ADJ 0x08 2960#define CCSGRAM_MAXSEGS 0x10 2961#define SEEOP_ERAL_ADDR 0x80 2962#define AHD_SLEWRATE_DEF_REVB 0x08 2963#define AHD_PRECOMP_CUTBACK_17 0x04 2964#define SRC_MODE_SHIFT 0x00 2965#define PKT_OVERRUN_BUFSIZE 0x200 2966#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x30 2967#define HOST_MSG 0xff 2968#define MAX_OFFSET 0xfe 2969#define BUS_16_BIT 0x01 2970 2971 2972/* Downloaded Constant Definitions */ 2973#define SG_SIZEOF 0x04 2974#define SG_PREFETCH_ALIGN_MASK 0x02 2975#define SG_PREFETCH_CNT_LIMIT 0x01 2976#define CACHELINE_MASK 0x07 2977#define SCB_TRANSFER_SIZE 0x06 2978#define PKT_OVERRUN_BUFOFFSET 0x05 2979#define SG_PREFETCH_ADDR_MASK 0x03 2980#define SG_PREFETCH_CNT 0x00 2981#define DOWNLOAD_CONST_COUNT 0x08 2982 2983 2984/* Exported Labels */ 2985#define LABEL_timer_isr 0x28b 2986#define LABEL_seq_isr 0x28f 2987