1/*
2 * DO NOT EDIT - This file is automatically generated
3 *		 from the following source files:
4 *
5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#94 $
6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $
7 */
8typedef int (ahd_reg_print_t)(u_int, u_int *, u_int);
9typedef struct ahd_reg_parse_entry {
10	char	*name;
11	uint8_t	 value;
12	uint8_t	 mask;
13} ahd_reg_parse_entry_t;
14
15#if AIC_DEBUG_REGISTERS
16ahd_reg_print_t ahd_mode_ptr_print;
17#else
18#define ahd_mode_ptr_print(regvalue, cur_col, wrap) \
19    ahd_print_register(NULL, 0, "MODE_PTR", 0x00, regvalue, cur_col, wrap)
20#endif
21
22#if AIC_DEBUG_REGISTERS
23ahd_reg_print_t ahd_intstat_print;
24#else
25#define ahd_intstat_print(regvalue, cur_col, wrap) \
26    ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)
27#endif
28
29#if AIC_DEBUG_REGISTERS
30ahd_reg_print_t ahd_seqintcode_print;
31#else
32#define ahd_seqintcode_print(regvalue, cur_col, wrap) \
33    ahd_print_register(NULL, 0, "SEQINTCODE", 0x02, regvalue, cur_col, wrap)
34#endif
35
36#if AIC_DEBUG_REGISTERS
37ahd_reg_print_t ahd_clrint_print;
38#else
39#define ahd_clrint_print(regvalue, cur_col, wrap) \
40    ahd_print_register(NULL, 0, "CLRINT", 0x03, regvalue, cur_col, wrap)
41#endif
42
43#if AIC_DEBUG_REGISTERS
44ahd_reg_print_t ahd_error_print;
45#else
46#define ahd_error_print(regvalue, cur_col, wrap) \
47    ahd_print_register(NULL, 0, "ERROR", 0x04, regvalue, cur_col, wrap)
48#endif
49
50#if AIC_DEBUG_REGISTERS
51ahd_reg_print_t ahd_clrerr_print;
52#else
53#define ahd_clrerr_print(regvalue, cur_col, wrap) \
54    ahd_print_register(NULL, 0, "CLRERR", 0x04, regvalue, cur_col, wrap)
55#endif
56
57#if AIC_DEBUG_REGISTERS
58ahd_reg_print_t ahd_hcntrl_print;
59#else
60#define ahd_hcntrl_print(regvalue, cur_col, wrap) \
61    ahd_print_register(NULL, 0, "HCNTRL", 0x05, regvalue, cur_col, wrap)
62#endif
63
64#if AIC_DEBUG_REGISTERS
65ahd_reg_print_t ahd_hnscb_qoff_print;
66#else
67#define ahd_hnscb_qoff_print(regvalue, cur_col, wrap) \
68    ahd_print_register(NULL, 0, "HNSCB_QOFF", 0x06, regvalue, cur_col, wrap)
69#endif
70
71#if AIC_DEBUG_REGISTERS
72ahd_reg_print_t ahd_hescb_qoff_print;
73#else
74#define ahd_hescb_qoff_print(regvalue, cur_col, wrap) \
75    ahd_print_register(NULL, 0, "HESCB_QOFF", 0x08, regvalue, cur_col, wrap)
76#endif
77
78#if AIC_DEBUG_REGISTERS
79ahd_reg_print_t ahd_hs_mailbox_print;
80#else
81#define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \
82    ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap)
83#endif
84
85#if AIC_DEBUG_REGISTERS
86ahd_reg_print_t ahd_clrseqintstat_print;
87#else
88#define ahd_clrseqintstat_print(regvalue, cur_col, wrap) \
89    ahd_print_register(NULL, 0, "CLRSEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
90#endif
91
92#if AIC_DEBUG_REGISTERS
93ahd_reg_print_t ahd_seqintstat_print;
94#else
95#define ahd_seqintstat_print(regvalue, cur_col, wrap) \
96    ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
97#endif
98
99#if AIC_DEBUG_REGISTERS
100ahd_reg_print_t ahd_swtimer_print;
101#else
102#define ahd_swtimer_print(regvalue, cur_col, wrap) \
103    ahd_print_register(NULL, 0, "SWTIMER", 0x0e, regvalue, cur_col, wrap)
104#endif
105
106#if AIC_DEBUG_REGISTERS
107ahd_reg_print_t ahd_snscb_qoff_print;
108#else
109#define ahd_snscb_qoff_print(regvalue, cur_col, wrap) \
110    ahd_print_register(NULL, 0, "SNSCB_QOFF", 0x10, regvalue, cur_col, wrap)
111#endif
112
113#if AIC_DEBUG_REGISTERS
114ahd_reg_print_t ahd_sescb_qoff_print;
115#else
116#define ahd_sescb_qoff_print(regvalue, cur_col, wrap) \
117    ahd_print_register(NULL, 0, "SESCB_QOFF", 0x12, regvalue, cur_col, wrap)
118#endif
119
120#if AIC_DEBUG_REGISTERS
121ahd_reg_print_t ahd_sdscb_qoff_print;
122#else
123#define ahd_sdscb_qoff_print(regvalue, cur_col, wrap) \
124    ahd_print_register(NULL, 0, "SDSCB_QOFF", 0x14, regvalue, cur_col, wrap)
125#endif
126
127#if AIC_DEBUG_REGISTERS
128ahd_reg_print_t ahd_qoff_ctlsta_print;
129#else
130#define ahd_qoff_ctlsta_print(regvalue, cur_col, wrap) \
131    ahd_print_register(NULL, 0, "QOFF_CTLSTA", 0x16, regvalue, cur_col, wrap)
132#endif
133
134#if AIC_DEBUG_REGISTERS
135ahd_reg_print_t ahd_intctl_print;
136#else
137#define ahd_intctl_print(regvalue, cur_col, wrap) \
138    ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap)
139#endif
140
141#if AIC_DEBUG_REGISTERS
142ahd_reg_print_t ahd_dfcntrl_print;
143#else
144#define ahd_dfcntrl_print(regvalue, cur_col, wrap) \
145    ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap)
146#endif
147
148#if AIC_DEBUG_REGISTERS
149ahd_reg_print_t ahd_dscommand0_print;
150#else
151#define ahd_dscommand0_print(regvalue, cur_col, wrap) \
152    ahd_print_register(NULL, 0, "DSCOMMAND0", 0x19, regvalue, cur_col, wrap)
153#endif
154
155#if AIC_DEBUG_REGISTERS
156ahd_reg_print_t ahd_dfstatus_print;
157#else
158#define ahd_dfstatus_print(regvalue, cur_col, wrap) \
159    ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap)
160#endif
161
162#if AIC_DEBUG_REGISTERS
163ahd_reg_print_t ahd_sg_cache_shadow_print;
164#else
165#define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \
166    ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap)
167#endif
168
169#if AIC_DEBUG_REGISTERS
170ahd_reg_print_t ahd_arbctl_print;
171#else
172#define ahd_arbctl_print(regvalue, cur_col, wrap) \
173    ahd_print_register(NULL, 0, "ARBCTL", 0x1b, regvalue, cur_col, wrap)
174#endif
175
176#if AIC_DEBUG_REGISTERS
177ahd_reg_print_t ahd_sg_cache_pre_print;
178#else
179#define ahd_sg_cache_pre_print(regvalue, cur_col, wrap) \
180    ahd_print_register(NULL, 0, "SG_CACHE_PRE", 0x1b, regvalue, cur_col, wrap)
181#endif
182
183#if AIC_DEBUG_REGISTERS
184ahd_reg_print_t ahd_lqin_print;
185#else
186#define ahd_lqin_print(regvalue, cur_col, wrap) \
187    ahd_print_register(NULL, 0, "LQIN", 0x20, regvalue, cur_col, wrap)
188#endif
189
190#if AIC_DEBUG_REGISTERS
191ahd_reg_print_t ahd_typeptr_print;
192#else
193#define ahd_typeptr_print(regvalue, cur_col, wrap) \
194    ahd_print_register(NULL, 0, "TYPEPTR", 0x20, regvalue, cur_col, wrap)
195#endif
196
197#if AIC_DEBUG_REGISTERS
198ahd_reg_print_t ahd_tagptr_print;
199#else
200#define ahd_tagptr_print(regvalue, cur_col, wrap) \
201    ahd_print_register(NULL, 0, "TAGPTR", 0x21, regvalue, cur_col, wrap)
202#endif
203
204#if AIC_DEBUG_REGISTERS
205ahd_reg_print_t ahd_lunptr_print;
206#else
207#define ahd_lunptr_print(regvalue, cur_col, wrap) \
208    ahd_print_register(NULL, 0, "LUNPTR", 0x22, regvalue, cur_col, wrap)
209#endif
210
211#if AIC_DEBUG_REGISTERS
212ahd_reg_print_t ahd_datalenptr_print;
213#else
214#define ahd_datalenptr_print(regvalue, cur_col, wrap) \
215    ahd_print_register(NULL, 0, "DATALENPTR", 0x23, regvalue, cur_col, wrap)
216#endif
217
218#if AIC_DEBUG_REGISTERS
219ahd_reg_print_t ahd_statlenptr_print;
220#else
221#define ahd_statlenptr_print(regvalue, cur_col, wrap) \
222    ahd_print_register(NULL, 0, "STATLENPTR", 0x24, regvalue, cur_col, wrap)
223#endif
224
225#if AIC_DEBUG_REGISTERS
226ahd_reg_print_t ahd_cmdlenptr_print;
227#else
228#define ahd_cmdlenptr_print(regvalue, cur_col, wrap) \
229    ahd_print_register(NULL, 0, "CMDLENPTR", 0x25, regvalue, cur_col, wrap)
230#endif
231
232#if AIC_DEBUG_REGISTERS
233ahd_reg_print_t ahd_attrptr_print;
234#else
235#define ahd_attrptr_print(regvalue, cur_col, wrap) \
236    ahd_print_register(NULL, 0, "ATTRPTR", 0x26, regvalue, cur_col, wrap)
237#endif
238
239#if AIC_DEBUG_REGISTERS
240ahd_reg_print_t ahd_flagptr_print;
241#else
242#define ahd_flagptr_print(regvalue, cur_col, wrap) \
243    ahd_print_register(NULL, 0, "FLAGPTR", 0x27, regvalue, cur_col, wrap)
244#endif
245
246#if AIC_DEBUG_REGISTERS
247ahd_reg_print_t ahd_cmdptr_print;
248#else
249#define ahd_cmdptr_print(regvalue, cur_col, wrap) \
250    ahd_print_register(NULL, 0, "CMDPTR", 0x28, regvalue, cur_col, wrap)
251#endif
252
253#if AIC_DEBUG_REGISTERS
254ahd_reg_print_t ahd_qnextptr_print;
255#else
256#define ahd_qnextptr_print(regvalue, cur_col, wrap) \
257    ahd_print_register(NULL, 0, "QNEXTPTR", 0x29, regvalue, cur_col, wrap)
258#endif
259
260#if AIC_DEBUG_REGISTERS
261ahd_reg_print_t ahd_idptr_print;
262#else
263#define ahd_idptr_print(regvalue, cur_col, wrap) \
264    ahd_print_register(NULL, 0, "IDPTR", 0x2a, regvalue, cur_col, wrap)
265#endif
266
267#if AIC_DEBUG_REGISTERS
268ahd_reg_print_t ahd_abrtbyteptr_print;
269#else
270#define ahd_abrtbyteptr_print(regvalue, cur_col, wrap) \
271    ahd_print_register(NULL, 0, "ABRTBYTEPTR", 0x2b, regvalue, cur_col, wrap)
272#endif
273
274#if AIC_DEBUG_REGISTERS
275ahd_reg_print_t ahd_abrtbitptr_print;
276#else
277#define ahd_abrtbitptr_print(regvalue, cur_col, wrap) \
278    ahd_print_register(NULL, 0, "ABRTBITPTR", 0x2c, regvalue, cur_col, wrap)
279#endif
280
281#if AIC_DEBUG_REGISTERS
282ahd_reg_print_t ahd_maxcmdbytes_print;
283#else
284#define ahd_maxcmdbytes_print(regvalue, cur_col, wrap) \
285    ahd_print_register(NULL, 0, "MAXCMDBYTES", 0x2d, regvalue, cur_col, wrap)
286#endif
287
288#if AIC_DEBUG_REGISTERS
289ahd_reg_print_t ahd_maxcmd2rcv_print;
290#else
291#define ahd_maxcmd2rcv_print(regvalue, cur_col, wrap) \
292    ahd_print_register(NULL, 0, "MAXCMD2RCV", 0x2e, regvalue, cur_col, wrap)
293#endif
294
295#if AIC_DEBUG_REGISTERS
296ahd_reg_print_t ahd_shortthresh_print;
297#else
298#define ahd_shortthresh_print(regvalue, cur_col, wrap) \
299    ahd_print_register(NULL, 0, "SHORTTHRESH", 0x2f, regvalue, cur_col, wrap)
300#endif
301
302#if AIC_DEBUG_REGISTERS
303ahd_reg_print_t ahd_lunlen_print;
304#else
305#define ahd_lunlen_print(regvalue, cur_col, wrap) \
306    ahd_print_register(NULL, 0, "LUNLEN", 0x30, regvalue, cur_col, wrap)
307#endif
308
309#if AIC_DEBUG_REGISTERS
310ahd_reg_print_t ahd_cdblimit_print;
311#else
312#define ahd_cdblimit_print(regvalue, cur_col, wrap) \
313    ahd_print_register(NULL, 0, "CDBLIMIT", 0x31, regvalue, cur_col, wrap)
314#endif
315
316#if AIC_DEBUG_REGISTERS
317ahd_reg_print_t ahd_maxcmd_print;
318#else
319#define ahd_maxcmd_print(regvalue, cur_col, wrap) \
320    ahd_print_register(NULL, 0, "MAXCMD", 0x32, regvalue, cur_col, wrap)
321#endif
322
323#if AIC_DEBUG_REGISTERS
324ahd_reg_print_t ahd_maxcmdcnt_print;
325#else
326#define ahd_maxcmdcnt_print(regvalue, cur_col, wrap) \
327    ahd_print_register(NULL, 0, "MAXCMDCNT", 0x33, regvalue, cur_col, wrap)
328#endif
329
330#if AIC_DEBUG_REGISTERS
331ahd_reg_print_t ahd_lqrsvd01_print;
332#else
333#define ahd_lqrsvd01_print(regvalue, cur_col, wrap) \
334    ahd_print_register(NULL, 0, "LQRSVD01", 0x34, regvalue, cur_col, wrap)
335#endif
336
337#if AIC_DEBUG_REGISTERS
338ahd_reg_print_t ahd_lqrsvd16_print;
339#else
340#define ahd_lqrsvd16_print(regvalue, cur_col, wrap) \
341    ahd_print_register(NULL, 0, "LQRSVD16", 0x35, regvalue, cur_col, wrap)
342#endif
343
344#if AIC_DEBUG_REGISTERS
345ahd_reg_print_t ahd_lqrsvd17_print;
346#else
347#define ahd_lqrsvd17_print(regvalue, cur_col, wrap) \
348    ahd_print_register(NULL, 0, "LQRSVD17", 0x36, regvalue, cur_col, wrap)
349#endif
350
351#if AIC_DEBUG_REGISTERS
352ahd_reg_print_t ahd_cmdrsvd0_print;
353#else
354#define ahd_cmdrsvd0_print(regvalue, cur_col, wrap) \
355    ahd_print_register(NULL, 0, "CMDRSVD0", 0x37, regvalue, cur_col, wrap)
356#endif
357
358#if AIC_DEBUG_REGISTERS
359ahd_reg_print_t ahd_lqctl0_print;
360#else
361#define ahd_lqctl0_print(regvalue, cur_col, wrap) \
362    ahd_print_register(NULL, 0, "LQCTL0", 0x38, regvalue, cur_col, wrap)
363#endif
364
365#if AIC_DEBUG_REGISTERS
366ahd_reg_print_t ahd_lqctl1_print;
367#else
368#define ahd_lqctl1_print(regvalue, cur_col, wrap) \
369    ahd_print_register(NULL, 0, "LQCTL1", 0x38, regvalue, cur_col, wrap)
370#endif
371
372#if AIC_DEBUG_REGISTERS
373ahd_reg_print_t ahd_scsbist0_print;
374#else
375#define ahd_scsbist0_print(regvalue, cur_col, wrap) \
376    ahd_print_register(NULL, 0, "SCSBIST0", 0x39, regvalue, cur_col, wrap)
377#endif
378
379#if AIC_DEBUG_REGISTERS
380ahd_reg_print_t ahd_lqctl2_print;
381#else
382#define ahd_lqctl2_print(regvalue, cur_col, wrap) \
383    ahd_print_register(NULL, 0, "LQCTL2", 0x39, regvalue, cur_col, wrap)
384#endif
385
386#if AIC_DEBUG_REGISTERS
387ahd_reg_print_t ahd_scsbist1_print;
388#else
389#define ahd_scsbist1_print(regvalue, cur_col, wrap) \
390    ahd_print_register(NULL, 0, "SCSBIST1", 0x3a, regvalue, cur_col, wrap)
391#endif
392
393#if AIC_DEBUG_REGISTERS
394ahd_reg_print_t ahd_scsiseq0_print;
395#else
396#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \
397    ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap)
398#endif
399
400#if AIC_DEBUG_REGISTERS
401ahd_reg_print_t ahd_scsiseq1_print;
402#else
403#define ahd_scsiseq1_print(regvalue, cur_col, wrap) \
404    ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap)
405#endif
406
407#if AIC_DEBUG_REGISTERS
408ahd_reg_print_t ahd_sxfrctl0_print;
409#else
410#define ahd_sxfrctl0_print(regvalue, cur_col, wrap) \
411    ahd_print_register(NULL, 0, "SXFRCTL0", 0x3c, regvalue, cur_col, wrap)
412#endif
413
414#if AIC_DEBUG_REGISTERS
415ahd_reg_print_t ahd_businitid_print;
416#else
417#define ahd_businitid_print(regvalue, cur_col, wrap) \
418    ahd_print_register(NULL, 0, "BUSINITID", 0x3c, regvalue, cur_col, wrap)
419#endif
420
421#if AIC_DEBUG_REGISTERS
422ahd_reg_print_t ahd_dlcount_print;
423#else
424#define ahd_dlcount_print(regvalue, cur_col, wrap) \
425    ahd_print_register(NULL, 0, "DLCOUNT", 0x3c, regvalue, cur_col, wrap)
426#endif
427
428#if AIC_DEBUG_REGISTERS
429ahd_reg_print_t ahd_sxfrctl1_print;
430#else
431#define ahd_sxfrctl1_print(regvalue, cur_col, wrap) \
432    ahd_print_register(NULL, 0, "SXFRCTL1", 0x3d, regvalue, cur_col, wrap)
433#endif
434
435#if AIC_DEBUG_REGISTERS
436ahd_reg_print_t ahd_bustargid_print;
437#else
438#define ahd_bustargid_print(regvalue, cur_col, wrap) \
439    ahd_print_register(NULL, 0, "BUSTARGID", 0x3e, regvalue, cur_col, wrap)
440#endif
441
442#if AIC_DEBUG_REGISTERS
443ahd_reg_print_t ahd_sxfrctl2_print;
444#else
445#define ahd_sxfrctl2_print(regvalue, cur_col, wrap) \
446    ahd_print_register(NULL, 0, "SXFRCTL2", 0x3e, regvalue, cur_col, wrap)
447#endif
448
449#if AIC_DEBUG_REGISTERS
450ahd_reg_print_t ahd_dffstat_print;
451#else
452#define ahd_dffstat_print(regvalue, cur_col, wrap) \
453    ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
454#endif
455
456#if AIC_DEBUG_REGISTERS
457ahd_reg_print_t ahd_scsisigo_print;
458#else
459#define ahd_scsisigo_print(regvalue, cur_col, wrap) \
460    ahd_print_register(NULL, 0, "SCSISIGO", 0x40, regvalue, cur_col, wrap)
461#endif
462
463#if AIC_DEBUG_REGISTERS
464ahd_reg_print_t ahd_multargid_print;
465#else
466#define ahd_multargid_print(regvalue, cur_col, wrap) \
467    ahd_print_register(NULL, 0, "MULTARGID", 0x40, regvalue, cur_col, wrap)
468#endif
469
470#if AIC_DEBUG_REGISTERS
471ahd_reg_print_t ahd_scsisigi_print;
472#else
473#define ahd_scsisigi_print(regvalue, cur_col, wrap) \
474    ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap)
475#endif
476
477#if AIC_DEBUG_REGISTERS
478ahd_reg_print_t ahd_scsiphase_print;
479#else
480#define ahd_scsiphase_print(regvalue, cur_col, wrap) \
481    ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap)
482#endif
483
484#if AIC_DEBUG_REGISTERS
485ahd_reg_print_t ahd_scsidat0_img_print;
486#else
487#define ahd_scsidat0_img_print(regvalue, cur_col, wrap) \
488    ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 0x43, regvalue, cur_col, wrap)
489#endif
490
491#if AIC_DEBUG_REGISTERS
492ahd_reg_print_t ahd_scsidat_print;
493#else
494#define ahd_scsidat_print(regvalue, cur_col, wrap) \
495    ahd_print_register(NULL, 0, "SCSIDAT", 0x44, regvalue, cur_col, wrap)
496#endif
497
498#if AIC_DEBUG_REGISTERS
499ahd_reg_print_t ahd_scsibus_print;
500#else
501#define ahd_scsibus_print(regvalue, cur_col, wrap) \
502    ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap)
503#endif
504
505#if AIC_DEBUG_REGISTERS
506ahd_reg_print_t ahd_targidin_print;
507#else
508#define ahd_targidin_print(regvalue, cur_col, wrap) \
509    ahd_print_register(NULL, 0, "TARGIDIN", 0x48, regvalue, cur_col, wrap)
510#endif
511
512#if AIC_DEBUG_REGISTERS
513ahd_reg_print_t ahd_selid_print;
514#else
515#define ahd_selid_print(regvalue, cur_col, wrap) \
516    ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap)
517#endif
518
519#if AIC_DEBUG_REGISTERS
520ahd_reg_print_t ahd_sblkctl_print;
521#else
522#define ahd_sblkctl_print(regvalue, cur_col, wrap) \
523    ahd_print_register(NULL, 0, "SBLKCTL", 0x4a, regvalue, cur_col, wrap)
524#endif
525
526#if AIC_DEBUG_REGISTERS
527ahd_reg_print_t ahd_optionmode_print;
528#else
529#define ahd_optionmode_print(regvalue, cur_col, wrap) \
530    ahd_print_register(NULL, 0, "OPTIONMODE", 0x4a, regvalue, cur_col, wrap)
531#endif
532
533#if AIC_DEBUG_REGISTERS
534ahd_reg_print_t ahd_sstat0_print;
535#else
536#define ahd_sstat0_print(regvalue, cur_col, wrap) \
537    ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap)
538#endif
539
540#if AIC_DEBUG_REGISTERS
541ahd_reg_print_t ahd_clrsint0_print;
542#else
543#define ahd_clrsint0_print(regvalue, cur_col, wrap) \
544    ahd_print_register(NULL, 0, "CLRSINT0", 0x4b, regvalue, cur_col, wrap)
545#endif
546
547#if AIC_DEBUG_REGISTERS
548ahd_reg_print_t ahd_simode0_print;
549#else
550#define ahd_simode0_print(regvalue, cur_col, wrap) \
551    ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap)
552#endif
553
554#if AIC_DEBUG_REGISTERS
555ahd_reg_print_t ahd_clrsint1_print;
556#else
557#define ahd_clrsint1_print(regvalue, cur_col, wrap) \
558    ahd_print_register(NULL, 0, "CLRSINT1", 0x4c, regvalue, cur_col, wrap)
559#endif
560
561#if AIC_DEBUG_REGISTERS
562ahd_reg_print_t ahd_sstat1_print;
563#else
564#define ahd_sstat1_print(regvalue, cur_col, wrap) \
565    ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap)
566#endif
567
568#if AIC_DEBUG_REGISTERS
569ahd_reg_print_t ahd_sstat2_print;
570#else
571#define ahd_sstat2_print(regvalue, cur_col, wrap) \
572    ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)
573#endif
574
575#if AIC_DEBUG_REGISTERS
576ahd_reg_print_t ahd_clrsint2_print;
577#else
578#define ahd_clrsint2_print(regvalue, cur_col, wrap) \
579    ahd_print_register(NULL, 0, "CLRSINT2", 0x4d, regvalue, cur_col, wrap)
580#endif
581
582#if AIC_DEBUG_REGISTERS
583ahd_reg_print_t ahd_simode2_print;
584#else
585#define ahd_simode2_print(regvalue, cur_col, wrap) \
586    ahd_print_register(NULL, 0, "SIMODE2", 0x4d, regvalue, cur_col, wrap)
587#endif
588
589#if AIC_DEBUG_REGISTERS
590ahd_reg_print_t ahd_perrdiag_print;
591#else
592#define ahd_perrdiag_print(regvalue, cur_col, wrap) \
593    ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap)
594#endif
595
596#if AIC_DEBUG_REGISTERS
597ahd_reg_print_t ahd_lqistate_print;
598#else
599#define ahd_lqistate_print(regvalue, cur_col, wrap) \
600    ahd_print_register(NULL, 0, "LQISTATE", 0x4e, regvalue, cur_col, wrap)
601#endif
602
603#if AIC_DEBUG_REGISTERS
604ahd_reg_print_t ahd_soffcnt_print;
605#else
606#define ahd_soffcnt_print(regvalue, cur_col, wrap) \
607    ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap)
608#endif
609
610#if AIC_DEBUG_REGISTERS
611ahd_reg_print_t ahd_lqostate_print;
612#else
613#define ahd_lqostate_print(regvalue, cur_col, wrap) \
614    ahd_print_register(NULL, 0, "LQOSTATE", 0x4f, regvalue, cur_col, wrap)
615#endif
616
617#if AIC_DEBUG_REGISTERS
618ahd_reg_print_t ahd_lqistat0_print;
619#else
620#define ahd_lqistat0_print(regvalue, cur_col, wrap) \
621    ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap)
622#endif
623
624#if AIC_DEBUG_REGISTERS
625ahd_reg_print_t ahd_clrlqiint0_print;
626#else
627#define ahd_clrlqiint0_print(regvalue, cur_col, wrap) \
628    ahd_print_register(NULL, 0, "CLRLQIINT0", 0x50, regvalue, cur_col, wrap)
629#endif
630
631#if AIC_DEBUG_REGISTERS
632ahd_reg_print_t ahd_lqimode0_print;
633#else
634#define ahd_lqimode0_print(regvalue, cur_col, wrap) \
635    ahd_print_register(NULL, 0, "LQIMODE0", 0x50, regvalue, cur_col, wrap)
636#endif
637
638#if AIC_DEBUG_REGISTERS
639ahd_reg_print_t ahd_lqimode1_print;
640#else
641#define ahd_lqimode1_print(regvalue, cur_col, wrap) \
642    ahd_print_register(NULL, 0, "LQIMODE1", 0x51, regvalue, cur_col, wrap)
643#endif
644
645#if AIC_DEBUG_REGISTERS
646ahd_reg_print_t ahd_lqistat1_print;
647#else
648#define ahd_lqistat1_print(regvalue, cur_col, wrap) \
649    ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap)
650#endif
651
652#if AIC_DEBUG_REGISTERS
653ahd_reg_print_t ahd_clrlqiint1_print;
654#else
655#define ahd_clrlqiint1_print(regvalue, cur_col, wrap) \
656    ahd_print_register(NULL, 0, "CLRLQIINT1", 0x51, regvalue, cur_col, wrap)
657#endif
658
659#if AIC_DEBUG_REGISTERS
660ahd_reg_print_t ahd_lqistat2_print;
661#else
662#define ahd_lqistat2_print(regvalue, cur_col, wrap) \
663    ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap)
664#endif
665
666#if AIC_DEBUG_REGISTERS
667ahd_reg_print_t ahd_sstat3_print;
668#else
669#define ahd_sstat3_print(regvalue, cur_col, wrap) \
670    ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap)
671#endif
672
673#if AIC_DEBUG_REGISTERS
674ahd_reg_print_t ahd_simode3_print;
675#else
676#define ahd_simode3_print(regvalue, cur_col, wrap) \
677    ahd_print_register(NULL, 0, "SIMODE3", 0x53, regvalue, cur_col, wrap)
678#endif
679
680#if AIC_DEBUG_REGISTERS
681ahd_reg_print_t ahd_clrsint3_print;
682#else
683#define ahd_clrsint3_print(regvalue, cur_col, wrap) \
684    ahd_print_register(NULL, 0, "CLRSINT3", 0x53, regvalue, cur_col, wrap)
685#endif
686
687#if AIC_DEBUG_REGISTERS
688ahd_reg_print_t ahd_lqomode0_print;
689#else
690#define ahd_lqomode0_print(regvalue, cur_col, wrap) \
691    ahd_print_register(NULL, 0, "LQOMODE0", 0x54, regvalue, cur_col, wrap)
692#endif
693
694#if AIC_DEBUG_REGISTERS
695ahd_reg_print_t ahd_lqostat0_print;
696#else
697#define ahd_lqostat0_print(regvalue, cur_col, wrap) \
698    ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap)
699#endif
700
701#if AIC_DEBUG_REGISTERS
702ahd_reg_print_t ahd_clrlqoint0_print;
703#else
704#define ahd_clrlqoint0_print(regvalue, cur_col, wrap) \
705    ahd_print_register(NULL, 0, "CLRLQOINT0", 0x54, regvalue, cur_col, wrap)
706#endif
707
708#if AIC_DEBUG_REGISTERS
709ahd_reg_print_t ahd_lqostat1_print;
710#else
711#define ahd_lqostat1_print(regvalue, cur_col, wrap) \
712    ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap)
713#endif
714
715#if AIC_DEBUG_REGISTERS
716ahd_reg_print_t ahd_clrlqoint1_print;
717#else
718#define ahd_clrlqoint1_print(regvalue, cur_col, wrap) \
719    ahd_print_register(NULL, 0, "CLRLQOINT1", 0x55, regvalue, cur_col, wrap)
720#endif
721
722#if AIC_DEBUG_REGISTERS
723ahd_reg_print_t ahd_lqomode1_print;
724#else
725#define ahd_lqomode1_print(regvalue, cur_col, wrap) \
726    ahd_print_register(NULL, 0, "LQOMODE1", 0x55, regvalue, cur_col, wrap)
727#endif
728
729#if AIC_DEBUG_REGISTERS
730ahd_reg_print_t ahd_lqostat2_print;
731#else
732#define ahd_lqostat2_print(regvalue, cur_col, wrap) \
733    ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap)
734#endif
735
736#if AIC_DEBUG_REGISTERS
737ahd_reg_print_t ahd_os_space_cnt_print;
738#else
739#define ahd_os_space_cnt_print(regvalue, cur_col, wrap) \
740    ahd_print_register(NULL, 0, "OS_SPACE_CNT", 0x56, regvalue, cur_col, wrap)
741#endif
742
743#if AIC_DEBUG_REGISTERS
744ahd_reg_print_t ahd_simode1_print;
745#else
746#define ahd_simode1_print(regvalue, cur_col, wrap) \
747    ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap)
748#endif
749
750#if AIC_DEBUG_REGISTERS
751ahd_reg_print_t ahd_gsfifo_print;
752#else
753#define ahd_gsfifo_print(regvalue, cur_col, wrap) \
754    ahd_print_register(NULL, 0, "GSFIFO", 0x58, regvalue, cur_col, wrap)
755#endif
756
757#if AIC_DEBUG_REGISTERS
758ahd_reg_print_t ahd_dffsxfrctl_print;
759#else
760#define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \
761    ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap)
762#endif
763
764#if AIC_DEBUG_REGISTERS
765ahd_reg_print_t ahd_lqoscsctl_print;
766#else
767#define ahd_lqoscsctl_print(regvalue, cur_col, wrap) \
768    ahd_print_register(NULL, 0, "LQOSCSCTL", 0x5a, regvalue, cur_col, wrap)
769#endif
770
771#if AIC_DEBUG_REGISTERS
772ahd_reg_print_t ahd_nextscb_print;
773#else
774#define ahd_nextscb_print(regvalue, cur_col, wrap) \
775    ahd_print_register(NULL, 0, "NEXTSCB", 0x5a, regvalue, cur_col, wrap)
776#endif
777
778#if AIC_DEBUG_REGISTERS
779ahd_reg_print_t ahd_clrseqintsrc_print;
780#else
781#define ahd_clrseqintsrc_print(regvalue, cur_col, wrap) \
782    ahd_print_register(NULL, 0, "CLRSEQINTSRC", 0x5b, regvalue, cur_col, wrap)
783#endif
784
785#if AIC_DEBUG_REGISTERS
786ahd_reg_print_t ahd_seqintsrc_print;
787#else
788#define ahd_seqintsrc_print(regvalue, cur_col, wrap) \
789    ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap)
790#endif
791
792#if AIC_DEBUG_REGISTERS
793ahd_reg_print_t ahd_currscb_print;
794#else
795#define ahd_currscb_print(regvalue, cur_col, wrap) \
796    ahd_print_register(NULL, 0, "CURRSCB", 0x5c, regvalue, cur_col, wrap)
797#endif
798
799#if AIC_DEBUG_REGISTERS
800ahd_reg_print_t ahd_seqimode_print;
801#else
802#define ahd_seqimode_print(regvalue, cur_col, wrap) \
803    ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)
804#endif
805
806#if AIC_DEBUG_REGISTERS
807ahd_reg_print_t ahd_mdffstat_print;
808#else
809#define ahd_mdffstat_print(regvalue, cur_col, wrap) \
810    ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)
811#endif
812
813#if AIC_DEBUG_REGISTERS
814ahd_reg_print_t ahd_crccontrol_print;
815#else
816#define ahd_crccontrol_print(regvalue, cur_col, wrap) \
817    ahd_print_register(NULL, 0, "CRCCONTROL", 0x5d, regvalue, cur_col, wrap)
818#endif
819
820#if AIC_DEBUG_REGISTERS
821ahd_reg_print_t ahd_dfftag_print;
822#else
823#define ahd_dfftag_print(regvalue, cur_col, wrap) \
824    ahd_print_register(NULL, 0, "DFFTAG", 0x5e, regvalue, cur_col, wrap)
825#endif
826
827#if AIC_DEBUG_REGISTERS
828ahd_reg_print_t ahd_lastscb_print;
829#else
830#define ahd_lastscb_print(regvalue, cur_col, wrap) \
831    ahd_print_register(NULL, 0, "LASTSCB", 0x5e, regvalue, cur_col, wrap)
832#endif
833
834#if AIC_DEBUG_REGISTERS
835ahd_reg_print_t ahd_scsitest_print;
836#else
837#define ahd_scsitest_print(regvalue, cur_col, wrap) \
838    ahd_print_register(NULL, 0, "SCSITEST", 0x5e, regvalue, cur_col, wrap)
839#endif
840
841#if AIC_DEBUG_REGISTERS
842ahd_reg_print_t ahd_iopdnctl_print;
843#else
844#define ahd_iopdnctl_print(regvalue, cur_col, wrap) \
845    ahd_print_register(NULL, 0, "IOPDNCTL", 0x5f, regvalue, cur_col, wrap)
846#endif
847
848#if AIC_DEBUG_REGISTERS
849ahd_reg_print_t ahd_shaddr_print;
850#else
851#define ahd_shaddr_print(regvalue, cur_col, wrap) \
852    ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap)
853#endif
854
855#if AIC_DEBUG_REGISTERS
856ahd_reg_print_t ahd_negoaddr_print;
857#else
858#define ahd_negoaddr_print(regvalue, cur_col, wrap) \
859    ahd_print_register(NULL, 0, "NEGOADDR", 0x60, regvalue, cur_col, wrap)
860#endif
861
862#if AIC_DEBUG_REGISTERS
863ahd_reg_print_t ahd_dgrpcrci_print;
864#else
865#define ahd_dgrpcrci_print(regvalue, cur_col, wrap) \
866    ahd_print_register(NULL, 0, "DGRPCRCI", 0x60, regvalue, cur_col, wrap)
867#endif
868
869#if AIC_DEBUG_REGISTERS
870ahd_reg_print_t ahd_negperiod_print;
871#else
872#define ahd_negperiod_print(regvalue, cur_col, wrap) \
873    ahd_print_register(NULL, 0, "NEGPERIOD", 0x61, regvalue, cur_col, wrap)
874#endif
875
876#if AIC_DEBUG_REGISTERS
877ahd_reg_print_t ahd_packcrci_print;
878#else
879#define ahd_packcrci_print(regvalue, cur_col, wrap) \
880    ahd_print_register(NULL, 0, "PACKCRCI", 0x62, regvalue, cur_col, wrap)
881#endif
882
883#if AIC_DEBUG_REGISTERS
884ahd_reg_print_t ahd_negoffset_print;
885#else
886#define ahd_negoffset_print(regvalue, cur_col, wrap) \
887    ahd_print_register(NULL, 0, "NEGOFFSET", 0x62, regvalue, cur_col, wrap)
888#endif
889
890#if AIC_DEBUG_REGISTERS
891ahd_reg_print_t ahd_negppropts_print;
892#else
893#define ahd_negppropts_print(regvalue, cur_col, wrap) \
894    ahd_print_register(NULL, 0, "NEGPPROPTS", 0x63, regvalue, cur_col, wrap)
895#endif
896
897#if AIC_DEBUG_REGISTERS
898ahd_reg_print_t ahd_negconopts_print;
899#else
900#define ahd_negconopts_print(regvalue, cur_col, wrap) \
901    ahd_print_register(NULL, 0, "NEGCONOPTS", 0x64, regvalue, cur_col, wrap)
902#endif
903
904#if AIC_DEBUG_REGISTERS
905ahd_reg_print_t ahd_annexcol_print;
906#else
907#define ahd_annexcol_print(regvalue, cur_col, wrap) \
908    ahd_print_register(NULL, 0, "ANNEXCOL", 0x65, regvalue, cur_col, wrap)
909#endif
910
911#if AIC_DEBUG_REGISTERS
912ahd_reg_print_t ahd_scschkn_print;
913#else
914#define ahd_scschkn_print(regvalue, cur_col, wrap) \
915    ahd_print_register(NULL, 0, "SCSCHKN", 0x66, regvalue, cur_col, wrap)
916#endif
917
918#if AIC_DEBUG_REGISTERS
919ahd_reg_print_t ahd_annexdat_print;
920#else
921#define ahd_annexdat_print(regvalue, cur_col, wrap) \
922    ahd_print_register(NULL, 0, "ANNEXDAT", 0x66, regvalue, cur_col, wrap)
923#endif
924
925#if AIC_DEBUG_REGISTERS
926ahd_reg_print_t ahd_iownid_print;
927#else
928#define ahd_iownid_print(regvalue, cur_col, wrap) \
929    ahd_print_register(NULL, 0, "IOWNID", 0x67, regvalue, cur_col, wrap)
930#endif
931
932#if AIC_DEBUG_REGISTERS
933ahd_reg_print_t ahd_pll960ctl0_print;
934#else
935#define ahd_pll960ctl0_print(regvalue, cur_col, wrap) \
936    ahd_print_register(NULL, 0, "PLL960CTL0", 0x68, regvalue, cur_col, wrap)
937#endif
938
939#if AIC_DEBUG_REGISTERS
940ahd_reg_print_t ahd_shcnt_print;
941#else
942#define ahd_shcnt_print(regvalue, cur_col, wrap) \
943    ahd_print_register(NULL, 0, "SHCNT", 0x68, regvalue, cur_col, wrap)
944#endif
945
946#if AIC_DEBUG_REGISTERS
947ahd_reg_print_t ahd_townid_print;
948#else
949#define ahd_townid_print(regvalue, cur_col, wrap) \
950    ahd_print_register(NULL, 0, "TOWNID", 0x69, regvalue, cur_col, wrap)
951#endif
952
953#if AIC_DEBUG_REGISTERS
954ahd_reg_print_t ahd_pll960ctl1_print;
955#else
956#define ahd_pll960ctl1_print(regvalue, cur_col, wrap) \
957    ahd_print_register(NULL, 0, "PLL960CTL1", 0x69, regvalue, cur_col, wrap)
958#endif
959
960#if AIC_DEBUG_REGISTERS
961ahd_reg_print_t ahd_pll960cnt0_print;
962#else
963#define ahd_pll960cnt0_print(regvalue, cur_col, wrap) \
964    ahd_print_register(NULL, 0, "PLL960CNT0", 0x6a, regvalue, cur_col, wrap)
965#endif
966
967#if AIC_DEBUG_REGISTERS
968ahd_reg_print_t ahd_xsig_print;
969#else
970#define ahd_xsig_print(regvalue, cur_col, wrap) \
971    ahd_print_register(NULL, 0, "XSIG", 0x6a, regvalue, cur_col, wrap)
972#endif
973
974#if AIC_DEBUG_REGISTERS
975ahd_reg_print_t ahd_seloid_print;
976#else
977#define ahd_seloid_print(regvalue, cur_col, wrap) \
978    ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap)
979#endif
980
981#if AIC_DEBUG_REGISTERS
982ahd_reg_print_t ahd_pll400ctl0_print;
983#else
984#define ahd_pll400ctl0_print(regvalue, cur_col, wrap) \
985    ahd_print_register(NULL, 0, "PLL400CTL0", 0x6c, regvalue, cur_col, wrap)
986#endif
987
988#if AIC_DEBUG_REGISTERS
989ahd_reg_print_t ahd_fairness_print;
990#else
991#define ahd_fairness_print(regvalue, cur_col, wrap) \
992    ahd_print_register(NULL, 0, "FAIRNESS", 0x6c, regvalue, cur_col, wrap)
993#endif
994
995#if AIC_DEBUG_REGISTERS
996ahd_reg_print_t ahd_pll400ctl1_print;
997#else
998#define ahd_pll400ctl1_print(regvalue, cur_col, wrap) \
999    ahd_print_register(NULL, 0, "PLL400CTL1", 0x6d, regvalue, cur_col, wrap)
1000#endif
1001
1002#if AIC_DEBUG_REGISTERS
1003ahd_reg_print_t ahd_pll400cnt0_print;
1004#else
1005#define ahd_pll400cnt0_print(regvalue, cur_col, wrap) \
1006    ahd_print_register(NULL, 0, "PLL400CNT0", 0x6e, regvalue, cur_col, wrap)
1007#endif
1008
1009#if AIC_DEBUG_REGISTERS
1010ahd_reg_print_t ahd_unfairness_print;
1011#else
1012#define ahd_unfairness_print(regvalue, cur_col, wrap) \
1013    ahd_print_register(NULL, 0, "UNFAIRNESS", 0x6e, regvalue, cur_col, wrap)
1014#endif
1015
1016#if AIC_DEBUG_REGISTERS
1017ahd_reg_print_t ahd_haddr_print;
1018#else
1019#define ahd_haddr_print(regvalue, cur_col, wrap) \
1020    ahd_print_register(NULL, 0, "HADDR", 0x70, regvalue, cur_col, wrap)
1021#endif
1022
1023#if AIC_DEBUG_REGISTERS
1024ahd_reg_print_t ahd_plldelay_print;
1025#else
1026#define ahd_plldelay_print(regvalue, cur_col, wrap) \
1027    ahd_print_register(NULL, 0, "PLLDELAY", 0x70, regvalue, cur_col, wrap)
1028#endif
1029
1030#if AIC_DEBUG_REGISTERS
1031ahd_reg_print_t ahd_hodmaadr_print;
1032#else
1033#define ahd_hodmaadr_print(regvalue, cur_col, wrap) \
1034    ahd_print_register(NULL, 0, "HODMAADR", 0x70, regvalue, cur_col, wrap)
1035#endif
1036
1037#if AIC_DEBUG_REGISTERS
1038ahd_reg_print_t ahd_hodmacnt_print;
1039#else
1040#define ahd_hodmacnt_print(regvalue, cur_col, wrap) \
1041    ahd_print_register(NULL, 0, "HODMACNT", 0x78, regvalue, cur_col, wrap)
1042#endif
1043
1044#if AIC_DEBUG_REGISTERS
1045ahd_reg_print_t ahd_hcnt_print;
1046#else
1047#define ahd_hcnt_print(regvalue, cur_col, wrap) \
1048    ahd_print_register(NULL, 0, "HCNT", 0x78, regvalue, cur_col, wrap)
1049#endif
1050
1051#if AIC_DEBUG_REGISTERS
1052ahd_reg_print_t ahd_hodmaen_print;
1053#else
1054#define ahd_hodmaen_print(regvalue, cur_col, wrap) \
1055    ahd_print_register(NULL, 0, "HODMAEN", 0x7a, regvalue, cur_col, wrap)
1056#endif
1057
1058#if AIC_DEBUG_REGISTERS
1059ahd_reg_print_t ahd_sghaddr_print;
1060#else
1061#define ahd_sghaddr_print(regvalue, cur_col, wrap) \
1062    ahd_print_register(NULL, 0, "SGHADDR", 0x7c, regvalue, cur_col, wrap)
1063#endif
1064
1065#if AIC_DEBUG_REGISTERS
1066ahd_reg_print_t ahd_scbhaddr_print;
1067#else
1068#define ahd_scbhaddr_print(regvalue, cur_col, wrap) \
1069    ahd_print_register(NULL, 0, "SCBHADDR", 0x7c, regvalue, cur_col, wrap)
1070#endif
1071
1072#if AIC_DEBUG_REGISTERS
1073ahd_reg_print_t ahd_sghcnt_print;
1074#else
1075#define ahd_sghcnt_print(regvalue, cur_col, wrap) \
1076    ahd_print_register(NULL, 0, "SGHCNT", 0x84, regvalue, cur_col, wrap)
1077#endif
1078
1079#if AIC_DEBUG_REGISTERS
1080ahd_reg_print_t ahd_scbhcnt_print;
1081#else
1082#define ahd_scbhcnt_print(regvalue, cur_col, wrap) \
1083    ahd_print_register(NULL, 0, "SCBHCNT", 0x84, regvalue, cur_col, wrap)
1084#endif
1085
1086#if AIC_DEBUG_REGISTERS
1087ahd_reg_print_t ahd_dff_thrsh_print;
1088#else
1089#define ahd_dff_thrsh_print(regvalue, cur_col, wrap) \
1090    ahd_print_register(NULL, 0, "DFF_THRSH", 0x88, regvalue, cur_col, wrap)
1091#endif
1092
1093#if AIC_DEBUG_REGISTERS
1094ahd_reg_print_t ahd_romaddr_print;
1095#else
1096#define ahd_romaddr_print(regvalue, cur_col, wrap) \
1097    ahd_print_register(NULL, 0, "ROMADDR", 0x8a, regvalue, cur_col, wrap)
1098#endif
1099
1100#if AIC_DEBUG_REGISTERS
1101ahd_reg_print_t ahd_romcntrl_print;
1102#else
1103#define ahd_romcntrl_print(regvalue, cur_col, wrap) \
1104    ahd_print_register(NULL, 0, "ROMCNTRL", 0x8d, regvalue, cur_col, wrap)
1105#endif
1106
1107#if AIC_DEBUG_REGISTERS
1108ahd_reg_print_t ahd_romdata_print;
1109#else
1110#define ahd_romdata_print(regvalue, cur_col, wrap) \
1111    ahd_print_register(NULL, 0, "ROMDATA", 0x8e, regvalue, cur_col, wrap)
1112#endif
1113
1114#if AIC_DEBUG_REGISTERS
1115ahd_reg_print_t ahd_cmcrxmsg0_print;
1116#else
1117#define ahd_cmcrxmsg0_print(regvalue, cur_col, wrap) \
1118    ahd_print_register(NULL, 0, "CMCRXMSG0", 0x90, regvalue, cur_col, wrap)
1119#endif
1120
1121#if AIC_DEBUG_REGISTERS
1122ahd_reg_print_t ahd_roenable_print;
1123#else
1124#define ahd_roenable_print(regvalue, cur_col, wrap) \
1125    ahd_print_register(NULL, 0, "ROENABLE", 0x90, regvalue, cur_col, wrap)
1126#endif
1127
1128#if AIC_DEBUG_REGISTERS
1129ahd_reg_print_t ahd_ovlyrxmsg0_print;
1130#else
1131#define ahd_ovlyrxmsg0_print(regvalue, cur_col, wrap) \
1132    ahd_print_register(NULL, 0, "OVLYRXMSG0", 0x90, regvalue, cur_col, wrap)
1133#endif
1134
1135#if AIC_DEBUG_REGISTERS
1136ahd_reg_print_t ahd_dchrxmsg0_print;
1137#else
1138#define ahd_dchrxmsg0_print(regvalue, cur_col, wrap) \
1139    ahd_print_register(NULL, 0, "DCHRXMSG0", 0x90, regvalue, cur_col, wrap)
1140#endif
1141
1142#if AIC_DEBUG_REGISTERS
1143ahd_reg_print_t ahd_ovlyrxmsg1_print;
1144#else
1145#define ahd_ovlyrxmsg1_print(regvalue, cur_col, wrap) \
1146    ahd_print_register(NULL, 0, "OVLYRXMSG1", 0x91, regvalue, cur_col, wrap)
1147#endif
1148
1149#if AIC_DEBUG_REGISTERS
1150ahd_reg_print_t ahd_nsenable_print;
1151#else
1152#define ahd_nsenable_print(regvalue, cur_col, wrap) \
1153    ahd_print_register(NULL, 0, "NSENABLE", 0x91, regvalue, cur_col, wrap)
1154#endif
1155
1156#if AIC_DEBUG_REGISTERS
1157ahd_reg_print_t ahd_dchrxmsg1_print;
1158#else
1159#define ahd_dchrxmsg1_print(regvalue, cur_col, wrap) \
1160    ahd_print_register(NULL, 0, "DCHRXMSG1", 0x91, regvalue, cur_col, wrap)
1161#endif
1162
1163#if AIC_DEBUG_REGISTERS
1164ahd_reg_print_t ahd_cmcrxmsg1_print;
1165#else
1166#define ahd_cmcrxmsg1_print(regvalue, cur_col, wrap) \
1167    ahd_print_register(NULL, 0, "CMCRXMSG1", 0x91, regvalue, cur_col, wrap)
1168#endif
1169
1170#if AIC_DEBUG_REGISTERS
1171ahd_reg_print_t ahd_dchrxmsg2_print;
1172#else
1173#define ahd_dchrxmsg2_print(regvalue, cur_col, wrap) \
1174    ahd_print_register(NULL, 0, "DCHRXMSG2", 0x92, regvalue, cur_col, wrap)
1175#endif
1176
1177#if AIC_DEBUG_REGISTERS
1178ahd_reg_print_t ahd_ovlyrxmsg2_print;
1179#else
1180#define ahd_ovlyrxmsg2_print(regvalue, cur_col, wrap) \
1181    ahd_print_register(NULL, 0, "OVLYRXMSG2", 0x92, regvalue, cur_col, wrap)
1182#endif
1183
1184#if AIC_DEBUG_REGISTERS
1185ahd_reg_print_t ahd_cmcrxmsg2_print;
1186#else
1187#define ahd_cmcrxmsg2_print(regvalue, cur_col, wrap) \
1188    ahd_print_register(NULL, 0, "CMCRXMSG2", 0x92, regvalue, cur_col, wrap)
1189#endif
1190
1191#if AIC_DEBUG_REGISTERS
1192ahd_reg_print_t ahd_ost_print;
1193#else
1194#define ahd_ost_print(regvalue, cur_col, wrap) \
1195    ahd_print_register(NULL, 0, "OST", 0x92, regvalue, cur_col, wrap)
1196#endif
1197
1198#if AIC_DEBUG_REGISTERS
1199ahd_reg_print_t ahd_dchrxmsg3_print;
1200#else
1201#define ahd_dchrxmsg3_print(regvalue, cur_col, wrap) \
1202    ahd_print_register(NULL, 0, "DCHRXMSG3", 0x93, regvalue, cur_col, wrap)
1203#endif
1204
1205#if AIC_DEBUG_REGISTERS
1206ahd_reg_print_t ahd_cmcrxmsg3_print;
1207#else
1208#define ahd_cmcrxmsg3_print(regvalue, cur_col, wrap) \
1209    ahd_print_register(NULL, 0, "CMCRXMSG3", 0x93, regvalue, cur_col, wrap)
1210#endif
1211
1212#if AIC_DEBUG_REGISTERS
1213ahd_reg_print_t ahd_pcixctl_print;
1214#else
1215#define ahd_pcixctl_print(regvalue, cur_col, wrap) \
1216    ahd_print_register(NULL, 0, "PCIXCTL", 0x93, regvalue, cur_col, wrap)
1217#endif
1218
1219#if AIC_DEBUG_REGISTERS
1220ahd_reg_print_t ahd_ovlyrxmsg3_print;
1221#else
1222#define ahd_ovlyrxmsg3_print(regvalue, cur_col, wrap) \
1223    ahd_print_register(NULL, 0, "OVLYRXMSG3", 0x93, regvalue, cur_col, wrap)
1224#endif
1225
1226#if AIC_DEBUG_REGISTERS
1227ahd_reg_print_t ahd_ovlyseqbcnt_print;
1228#else
1229#define ahd_ovlyseqbcnt_print(regvalue, cur_col, wrap) \
1230    ahd_print_register(NULL, 0, "OVLYSEQBCNT", 0x94, regvalue, cur_col, wrap)
1231#endif
1232
1233#if AIC_DEBUG_REGISTERS
1234ahd_reg_print_t ahd_cmcseqbcnt_print;
1235#else
1236#define ahd_cmcseqbcnt_print(regvalue, cur_col, wrap) \
1237    ahd_print_register(NULL, 0, "CMCSEQBCNT", 0x94, regvalue, cur_col, wrap)
1238#endif
1239
1240#if AIC_DEBUG_REGISTERS
1241ahd_reg_print_t ahd_dchseqbcnt_print;
1242#else
1243#define ahd_dchseqbcnt_print(regvalue, cur_col, wrap) \
1244    ahd_print_register(NULL, 0, "DCHSEQBCNT", 0x94, regvalue, cur_col, wrap)
1245#endif
1246
1247#if AIC_DEBUG_REGISTERS
1248ahd_reg_print_t ahd_cmcspltstat0_print;
1249#else
1250#define ahd_cmcspltstat0_print(regvalue, cur_col, wrap) \
1251    ahd_print_register(NULL, 0, "CMCSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1252#endif
1253
1254#if AIC_DEBUG_REGISTERS
1255ahd_reg_print_t ahd_ovlyspltstat0_print;
1256#else
1257#define ahd_ovlyspltstat0_print(regvalue, cur_col, wrap) \
1258    ahd_print_register(NULL, 0, "OVLYSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1259#endif
1260
1261#if AIC_DEBUG_REGISTERS
1262ahd_reg_print_t ahd_dchspltstat0_print;
1263#else
1264#define ahd_dchspltstat0_print(regvalue, cur_col, wrap) \
1265    ahd_print_register(NULL, 0, "DCHSPLTSTAT0", 0x96, regvalue, cur_col, wrap)
1266#endif
1267
1268#if AIC_DEBUG_REGISTERS
1269ahd_reg_print_t ahd_dchspltstat1_print;
1270#else
1271#define ahd_dchspltstat1_print(regvalue, cur_col, wrap) \
1272    ahd_print_register(NULL, 0, "DCHSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1273#endif
1274
1275#if AIC_DEBUG_REGISTERS
1276ahd_reg_print_t ahd_cmcspltstat1_print;
1277#else
1278#define ahd_cmcspltstat1_print(regvalue, cur_col, wrap) \
1279    ahd_print_register(NULL, 0, "CMCSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1280#endif
1281
1282#if AIC_DEBUG_REGISTERS
1283ahd_reg_print_t ahd_ovlyspltstat1_print;
1284#else
1285#define ahd_ovlyspltstat1_print(regvalue, cur_col, wrap) \
1286    ahd_print_register(NULL, 0, "OVLYSPLTSTAT1", 0x97, regvalue, cur_col, wrap)
1287#endif
1288
1289#if AIC_DEBUG_REGISTERS
1290ahd_reg_print_t ahd_sgrxmsg0_print;
1291#else
1292#define ahd_sgrxmsg0_print(regvalue, cur_col, wrap) \
1293    ahd_print_register(NULL, 0, "SGRXMSG0", 0x98, regvalue, cur_col, wrap)
1294#endif
1295
1296#if AIC_DEBUG_REGISTERS
1297ahd_reg_print_t ahd_slvspltoutadr0_print;
1298#else
1299#define ahd_slvspltoutadr0_print(regvalue, cur_col, wrap) \
1300    ahd_print_register(NULL, 0, "SLVSPLTOUTADR0", 0x98, regvalue, cur_col, wrap)
1301#endif
1302
1303#if AIC_DEBUG_REGISTERS
1304ahd_reg_print_t ahd_sgrxmsg1_print;
1305#else
1306#define ahd_sgrxmsg1_print(regvalue, cur_col, wrap) \
1307    ahd_print_register(NULL, 0, "SGRXMSG1", 0x99, regvalue, cur_col, wrap)
1308#endif
1309
1310#if AIC_DEBUG_REGISTERS
1311ahd_reg_print_t ahd_slvspltoutadr1_print;
1312#else
1313#define ahd_slvspltoutadr1_print(regvalue, cur_col, wrap) \
1314    ahd_print_register(NULL, 0, "SLVSPLTOUTADR1", 0x99, regvalue, cur_col, wrap)
1315#endif
1316
1317#if AIC_DEBUG_REGISTERS
1318ahd_reg_print_t ahd_sgrxmsg2_print;
1319#else
1320#define ahd_sgrxmsg2_print(regvalue, cur_col, wrap) \
1321    ahd_print_register(NULL, 0, "SGRXMSG2", 0x9a, regvalue, cur_col, wrap)
1322#endif
1323
1324#if AIC_DEBUG_REGISTERS
1325ahd_reg_print_t ahd_slvspltoutadr2_print;
1326#else
1327#define ahd_slvspltoutadr2_print(regvalue, cur_col, wrap) \
1328    ahd_print_register(NULL, 0, "SLVSPLTOUTADR2", 0x9a, regvalue, cur_col, wrap)
1329#endif
1330
1331#if AIC_DEBUG_REGISTERS
1332ahd_reg_print_t ahd_sgrxmsg3_print;
1333#else
1334#define ahd_sgrxmsg3_print(regvalue, cur_col, wrap) \
1335    ahd_print_register(NULL, 0, "SGRXMSG3", 0x9b, regvalue, cur_col, wrap)
1336#endif
1337
1338#if AIC_DEBUG_REGISTERS
1339ahd_reg_print_t ahd_slvspltoutadr3_print;
1340#else
1341#define ahd_slvspltoutadr3_print(regvalue, cur_col, wrap) \
1342    ahd_print_register(NULL, 0, "SLVSPLTOUTADR3", 0x9b, regvalue, cur_col, wrap)
1343#endif
1344
1345#if AIC_DEBUG_REGISTERS
1346ahd_reg_print_t ahd_sgseqbcnt_print;
1347#else
1348#define ahd_sgseqbcnt_print(regvalue, cur_col, wrap) \
1349    ahd_print_register(NULL, 0, "SGSEQBCNT", 0x9c, regvalue, cur_col, wrap)
1350#endif
1351
1352#if AIC_DEBUG_REGISTERS
1353ahd_reg_print_t ahd_slvspltoutattr0_print;
1354#else
1355#define ahd_slvspltoutattr0_print(regvalue, cur_col, wrap) \
1356    ahd_print_register(NULL, 0, "SLVSPLTOUTATTR0", 0x9c, regvalue, cur_col, wrap)
1357#endif
1358
1359#if AIC_DEBUG_REGISTERS
1360ahd_reg_print_t ahd_slvspltoutattr1_print;
1361#else
1362#define ahd_slvspltoutattr1_print(regvalue, cur_col, wrap) \
1363    ahd_print_register(NULL, 0, "SLVSPLTOUTATTR1", 0x9d, regvalue, cur_col, wrap)
1364#endif
1365
1366#if AIC_DEBUG_REGISTERS
1367ahd_reg_print_t ahd_slvspltoutattr2_print;
1368#else
1369#define ahd_slvspltoutattr2_print(regvalue, cur_col, wrap) \
1370    ahd_print_register(NULL, 0, "SLVSPLTOUTATTR2", 0x9e, regvalue, cur_col, wrap)
1371#endif
1372
1373#if AIC_DEBUG_REGISTERS
1374ahd_reg_print_t ahd_sgspltstat0_print;
1375#else
1376#define ahd_sgspltstat0_print(regvalue, cur_col, wrap) \
1377    ahd_print_register(NULL, 0, "SGSPLTSTAT0", 0x9e, regvalue, cur_col, wrap)
1378#endif
1379
1380#if AIC_DEBUG_REGISTERS
1381ahd_reg_print_t ahd_sfunct_print;
1382#else
1383#define ahd_sfunct_print(regvalue, cur_col, wrap) \
1384    ahd_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
1385#endif
1386
1387#if AIC_DEBUG_REGISTERS
1388ahd_reg_print_t ahd_sgspltstat1_print;
1389#else
1390#define ahd_sgspltstat1_print(regvalue, cur_col, wrap) \
1391    ahd_print_register(NULL, 0, "SGSPLTSTAT1", 0x9f, regvalue, cur_col, wrap)
1392#endif
1393
1394#if AIC_DEBUG_REGISTERS
1395ahd_reg_print_t ahd_df0pcistat_print;
1396#else
1397#define ahd_df0pcistat_print(regvalue, cur_col, wrap) \
1398    ahd_print_register(NULL, 0, "DF0PCISTAT", 0xa0, regvalue, cur_col, wrap)
1399#endif
1400
1401#if AIC_DEBUG_REGISTERS
1402ahd_reg_print_t ahd_reg0_print;
1403#else
1404#define ahd_reg0_print(regvalue, cur_col, wrap) \
1405    ahd_print_register(NULL, 0, "REG0", 0xa0, regvalue, cur_col, wrap)
1406#endif
1407
1408#if AIC_DEBUG_REGISTERS
1409ahd_reg_print_t ahd_df1pcistat_print;
1410#else
1411#define ahd_df1pcistat_print(regvalue, cur_col, wrap) \
1412    ahd_print_register(NULL, 0, "DF1PCISTAT", 0xa1, regvalue, cur_col, wrap)
1413#endif
1414
1415#if AIC_DEBUG_REGISTERS
1416ahd_reg_print_t ahd_sgpcistat_print;
1417#else
1418#define ahd_sgpcistat_print(regvalue, cur_col, wrap) \
1419    ahd_print_register(NULL, 0, "SGPCISTAT", 0xa2, regvalue, cur_col, wrap)
1420#endif
1421
1422#if AIC_DEBUG_REGISTERS
1423ahd_reg_print_t ahd_reg1_print;
1424#else
1425#define ahd_reg1_print(regvalue, cur_col, wrap) \
1426    ahd_print_register(NULL, 0, "REG1", 0xa2, regvalue, cur_col, wrap)
1427#endif
1428
1429#if AIC_DEBUG_REGISTERS
1430ahd_reg_print_t ahd_cmcpcistat_print;
1431#else
1432#define ahd_cmcpcistat_print(regvalue, cur_col, wrap) \
1433    ahd_print_register(NULL, 0, "CMCPCISTAT", 0xa3, regvalue, cur_col, wrap)
1434#endif
1435
1436#if AIC_DEBUG_REGISTERS
1437ahd_reg_print_t ahd_ovlypcistat_print;
1438#else
1439#define ahd_ovlypcistat_print(regvalue, cur_col, wrap) \
1440    ahd_print_register(NULL, 0, "OVLYPCISTAT", 0xa4, regvalue, cur_col, wrap)
1441#endif
1442
1443#if AIC_DEBUG_REGISTERS
1444ahd_reg_print_t ahd_reg_isr_print;
1445#else
1446#define ahd_reg_isr_print(regvalue, cur_col, wrap) \
1447    ahd_print_register(NULL, 0, "REG_ISR", 0xa4, regvalue, cur_col, wrap)
1448#endif
1449
1450#if AIC_DEBUG_REGISTERS
1451ahd_reg_print_t ahd_sg_state_print;
1452#else
1453#define ahd_sg_state_print(regvalue, cur_col, wrap) \
1454    ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap)
1455#endif
1456
1457#if AIC_DEBUG_REGISTERS
1458ahd_reg_print_t ahd_msipcistat_print;
1459#else
1460#define ahd_msipcistat_print(regvalue, cur_col, wrap) \
1461    ahd_print_register(NULL, 0, "MSIPCISTAT", 0xa6, regvalue, cur_col, wrap)
1462#endif
1463
1464#if AIC_DEBUG_REGISTERS
1465ahd_reg_print_t ahd_targpcistat_print;
1466#else
1467#define ahd_targpcistat_print(regvalue, cur_col, wrap) \
1468    ahd_print_register(NULL, 0, "TARGPCISTAT", 0xa7, regvalue, cur_col, wrap)
1469#endif
1470
1471#if AIC_DEBUG_REGISTERS
1472ahd_reg_print_t ahd_data_count_odd_print;
1473#else
1474#define ahd_data_count_odd_print(regvalue, cur_col, wrap) \
1475    ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 0xa7, regvalue, cur_col, wrap)
1476#endif
1477
1478#if AIC_DEBUG_REGISTERS
1479ahd_reg_print_t ahd_scbptr_print;
1480#else
1481#define ahd_scbptr_print(regvalue, cur_col, wrap) \
1482    ahd_print_register(NULL, 0, "SCBPTR", 0xa8, regvalue, cur_col, wrap)
1483#endif
1484
1485#if AIC_DEBUG_REGISTERS
1486ahd_reg_print_t ahd_ccscbacnt_print;
1487#else
1488#define ahd_ccscbacnt_print(regvalue, cur_col, wrap) \
1489    ahd_print_register(NULL, 0, "CCSCBACNT", 0xab, regvalue, cur_col, wrap)
1490#endif
1491
1492#if AIC_DEBUG_REGISTERS
1493ahd_reg_print_t ahd_scbautoptr_print;
1494#else
1495#define ahd_scbautoptr_print(regvalue, cur_col, wrap) \
1496    ahd_print_register(NULL, 0, "SCBAUTOPTR", 0xab, regvalue, cur_col, wrap)
1497#endif
1498
1499#if AIC_DEBUG_REGISTERS
1500ahd_reg_print_t ahd_ccsgaddr_print;
1501#else
1502#define ahd_ccsgaddr_print(regvalue, cur_col, wrap) \
1503    ahd_print_register(NULL, 0, "CCSGADDR", 0xac, regvalue, cur_col, wrap)
1504#endif
1505
1506#if AIC_DEBUG_REGISTERS
1507ahd_reg_print_t ahd_ccscbaddr_print;
1508#else
1509#define ahd_ccscbaddr_print(regvalue, cur_col, wrap) \
1510    ahd_print_register(NULL, 0, "CCSCBADDR", 0xac, regvalue, cur_col, wrap)
1511#endif
1512
1513#if AIC_DEBUG_REGISTERS
1514ahd_reg_print_t ahd_ccscbadr_bk_print;
1515#else
1516#define ahd_ccscbadr_bk_print(regvalue, cur_col, wrap) \
1517    ahd_print_register(NULL, 0, "CCSCBADR_BK", 0xac, regvalue, cur_col, wrap)
1518#endif
1519
1520#if AIC_DEBUG_REGISTERS
1521ahd_reg_print_t ahd_cmc_rambist_print;
1522#else
1523#define ahd_cmc_rambist_print(regvalue, cur_col, wrap) \
1524    ahd_print_register(NULL, 0, "CMC_RAMBIST", 0xad, regvalue, cur_col, wrap)
1525#endif
1526
1527#if AIC_DEBUG_REGISTERS
1528ahd_reg_print_t ahd_ccsgctl_print;
1529#else
1530#define ahd_ccsgctl_print(regvalue, cur_col, wrap) \
1531    ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap)
1532#endif
1533
1534#if AIC_DEBUG_REGISTERS
1535ahd_reg_print_t ahd_ccscbctl_print;
1536#else
1537#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \
1538    ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap)
1539#endif
1540
1541#if AIC_DEBUG_REGISTERS
1542ahd_reg_print_t ahd_ccsgram_print;
1543#else
1544#define ahd_ccsgram_print(regvalue, cur_col, wrap) \
1545    ahd_print_register(NULL, 0, "CCSGRAM", 0xb0, regvalue, cur_col, wrap)
1546#endif
1547
1548#if AIC_DEBUG_REGISTERS
1549ahd_reg_print_t ahd_flexadr_print;
1550#else
1551#define ahd_flexadr_print(regvalue, cur_col, wrap) \
1552    ahd_print_register(NULL, 0, "FLEXADR", 0xb0, regvalue, cur_col, wrap)
1553#endif
1554
1555#if AIC_DEBUG_REGISTERS
1556ahd_reg_print_t ahd_ccscbram_print;
1557#else
1558#define ahd_ccscbram_print(regvalue, cur_col, wrap) \
1559    ahd_print_register(NULL, 0, "CCSCBRAM", 0xb0, regvalue, cur_col, wrap)
1560#endif
1561
1562#if AIC_DEBUG_REGISTERS
1563ahd_reg_print_t ahd_flexcnt_print;
1564#else
1565#define ahd_flexcnt_print(regvalue, cur_col, wrap) \
1566    ahd_print_register(NULL, 0, "FLEXCNT", 0xb3, regvalue, cur_col, wrap)
1567#endif
1568
1569#if AIC_DEBUG_REGISTERS
1570ahd_reg_print_t ahd_flexdmastat_print;
1571#else
1572#define ahd_flexdmastat_print(regvalue, cur_col, wrap) \
1573    ahd_print_register(NULL, 0, "FLEXDMASTAT", 0xb5, regvalue, cur_col, wrap)
1574#endif
1575
1576#if AIC_DEBUG_REGISTERS
1577ahd_reg_print_t ahd_flexdata_print;
1578#else
1579#define ahd_flexdata_print(regvalue, cur_col, wrap) \
1580    ahd_print_register(NULL, 0, "FLEXDATA", 0xb6, regvalue, cur_col, wrap)
1581#endif
1582
1583#if AIC_DEBUG_REGISTERS
1584ahd_reg_print_t ahd_brddat_print;
1585#else
1586#define ahd_brddat_print(regvalue, cur_col, wrap) \
1587    ahd_print_register(NULL, 0, "BRDDAT", 0xb8, regvalue, cur_col, wrap)
1588#endif
1589
1590#if AIC_DEBUG_REGISTERS
1591ahd_reg_print_t ahd_brdctl_print;
1592#else
1593#define ahd_brdctl_print(regvalue, cur_col, wrap) \
1594    ahd_print_register(NULL, 0, "BRDCTL", 0xb9, regvalue, cur_col, wrap)
1595#endif
1596
1597#if AIC_DEBUG_REGISTERS
1598ahd_reg_print_t ahd_seeadr_print;
1599#else
1600#define ahd_seeadr_print(regvalue, cur_col, wrap) \
1601    ahd_print_register(NULL, 0, "SEEADR", 0xba, regvalue, cur_col, wrap)
1602#endif
1603
1604#if AIC_DEBUG_REGISTERS
1605ahd_reg_print_t ahd_seedat_print;
1606#else
1607#define ahd_seedat_print(regvalue, cur_col, wrap) \
1608    ahd_print_register(NULL, 0, "SEEDAT", 0xbc, regvalue, cur_col, wrap)
1609#endif
1610
1611#if AIC_DEBUG_REGISTERS
1612ahd_reg_print_t ahd_seectl_print;
1613#else
1614#define ahd_seectl_print(regvalue, cur_col, wrap) \
1615    ahd_print_register(NULL, 0, "SEECTL", 0xbe, regvalue, cur_col, wrap)
1616#endif
1617
1618#if AIC_DEBUG_REGISTERS
1619ahd_reg_print_t ahd_seestat_print;
1620#else
1621#define ahd_seestat_print(regvalue, cur_col, wrap) \
1622    ahd_print_register(NULL, 0, "SEESTAT", 0xbe, regvalue, cur_col, wrap)
1623#endif
1624
1625#if AIC_DEBUG_REGISTERS
1626ahd_reg_print_t ahd_scbcnt_print;
1627#else
1628#define ahd_scbcnt_print(regvalue, cur_col, wrap) \
1629    ahd_print_register(NULL, 0, "SCBCNT", 0xbf, regvalue, cur_col, wrap)
1630#endif
1631
1632#if AIC_DEBUG_REGISTERS
1633ahd_reg_print_t ahd_dfwaddr_print;
1634#else
1635#define ahd_dfwaddr_print(regvalue, cur_col, wrap) \
1636    ahd_print_register(NULL, 0, "DFWADDR", 0xc0, regvalue, cur_col, wrap)
1637#endif
1638
1639#if AIC_DEBUG_REGISTERS
1640ahd_reg_print_t ahd_dspfltrctl_print;
1641#else
1642#define ahd_dspfltrctl_print(regvalue, cur_col, wrap) \
1643    ahd_print_register(NULL, 0, "DSPFLTRCTL", 0xc0, regvalue, cur_col, wrap)
1644#endif
1645
1646#if AIC_DEBUG_REGISTERS
1647ahd_reg_print_t ahd_dspdatactl_print;
1648#else
1649#define ahd_dspdatactl_print(regvalue, cur_col, wrap) \
1650    ahd_print_register(NULL, 0, "DSPDATACTL", 0xc1, regvalue, cur_col, wrap)
1651#endif
1652
1653#if AIC_DEBUG_REGISTERS
1654ahd_reg_print_t ahd_dfraddr_print;
1655#else
1656#define ahd_dfraddr_print(regvalue, cur_col, wrap) \
1657    ahd_print_register(NULL, 0, "DFRADDR", 0xc2, regvalue, cur_col, wrap)
1658#endif
1659
1660#if AIC_DEBUG_REGISTERS
1661ahd_reg_print_t ahd_dspreqctl_print;
1662#else
1663#define ahd_dspreqctl_print(regvalue, cur_col, wrap) \
1664    ahd_print_register(NULL, 0, "DSPREQCTL", 0xc2, regvalue, cur_col, wrap)
1665#endif
1666
1667#if AIC_DEBUG_REGISTERS
1668ahd_reg_print_t ahd_dspackctl_print;
1669#else
1670#define ahd_dspackctl_print(regvalue, cur_col, wrap) \
1671    ahd_print_register(NULL, 0, "DSPACKCTL", 0xc3, regvalue, cur_col, wrap)
1672#endif
1673
1674#if AIC_DEBUG_REGISTERS
1675ahd_reg_print_t ahd_dfdat_print;
1676#else
1677#define ahd_dfdat_print(regvalue, cur_col, wrap) \
1678    ahd_print_register(NULL, 0, "DFDAT", 0xc4, regvalue, cur_col, wrap)
1679#endif
1680
1681#if AIC_DEBUG_REGISTERS
1682ahd_reg_print_t ahd_dspselect_print;
1683#else
1684#define ahd_dspselect_print(regvalue, cur_col, wrap) \
1685    ahd_print_register(NULL, 0, "DSPSELECT", 0xc4, regvalue, cur_col, wrap)
1686#endif
1687
1688#if AIC_DEBUG_REGISTERS
1689ahd_reg_print_t ahd_wrtbiasctl_print;
1690#else
1691#define ahd_wrtbiasctl_print(regvalue, cur_col, wrap) \
1692    ahd_print_register(NULL, 0, "WRTBIASCTL", 0xc5, regvalue, cur_col, wrap)
1693#endif
1694
1695#if AIC_DEBUG_REGISTERS
1696ahd_reg_print_t ahd_rcvrbiosctl_print;
1697#else
1698#define ahd_rcvrbiosctl_print(regvalue, cur_col, wrap) \
1699    ahd_print_register(NULL, 0, "RCVRBIOSCTL", 0xc6, regvalue, cur_col, wrap)
1700#endif
1701
1702#if AIC_DEBUG_REGISTERS
1703ahd_reg_print_t ahd_wrtbiascalc_print;
1704#else
1705#define ahd_wrtbiascalc_print(regvalue, cur_col, wrap) \
1706    ahd_print_register(NULL, 0, "WRTBIASCALC", 0xc7, regvalue, cur_col, wrap)
1707#endif
1708
1709#if AIC_DEBUG_REGISTERS
1710ahd_reg_print_t ahd_dfptrs_print;
1711#else
1712#define ahd_dfptrs_print(regvalue, cur_col, wrap) \
1713    ahd_print_register(NULL, 0, "DFPTRS", 0xc8, regvalue, cur_col, wrap)
1714#endif
1715
1716#if AIC_DEBUG_REGISTERS
1717ahd_reg_print_t ahd_rcvrbiascalc_print;
1718#else
1719#define ahd_rcvrbiascalc_print(regvalue, cur_col, wrap) \
1720    ahd_print_register(NULL, 0, "RCVRBIASCALC", 0xc8, regvalue, cur_col, wrap)
1721#endif
1722
1723#if AIC_DEBUG_REGISTERS
1724ahd_reg_print_t ahd_dfbkptr_print;
1725#else
1726#define ahd_dfbkptr_print(regvalue, cur_col, wrap) \
1727    ahd_print_register(NULL, 0, "DFBKPTR", 0xc9, regvalue, cur_col, wrap)
1728#endif
1729
1730#if AIC_DEBUG_REGISTERS
1731ahd_reg_print_t ahd_skewcalc_print;
1732#else
1733#define ahd_skewcalc_print(regvalue, cur_col, wrap) \
1734    ahd_print_register(NULL, 0, "SKEWCALC", 0xc9, regvalue, cur_col, wrap)
1735#endif
1736
1737#if AIC_DEBUG_REGISTERS
1738ahd_reg_print_t ahd_dfdbctl_print;
1739#else
1740#define ahd_dfdbctl_print(regvalue, cur_col, wrap) \
1741    ahd_print_register(NULL, 0, "DFDBCTL", 0xcb, regvalue, cur_col, wrap)
1742#endif
1743
1744#if AIC_DEBUG_REGISTERS
1745ahd_reg_print_t ahd_dfscnt_print;
1746#else
1747#define ahd_dfscnt_print(regvalue, cur_col, wrap) \
1748    ahd_print_register(NULL, 0, "DFSCNT", 0xcc, regvalue, cur_col, wrap)
1749#endif
1750
1751#if AIC_DEBUG_REGISTERS
1752ahd_reg_print_t ahd_dfbcnt_print;
1753#else
1754#define ahd_dfbcnt_print(regvalue, cur_col, wrap) \
1755    ahd_print_register(NULL, 0, "DFBCNT", 0xce, regvalue, cur_col, wrap)
1756#endif
1757
1758#if AIC_DEBUG_REGISTERS
1759ahd_reg_print_t ahd_ovlyaddr_print;
1760#else
1761#define ahd_ovlyaddr_print(regvalue, cur_col, wrap) \
1762    ahd_print_register(NULL, 0, "OVLYADDR", 0xd4, regvalue, cur_col, wrap)
1763#endif
1764
1765#if AIC_DEBUG_REGISTERS
1766ahd_reg_print_t ahd_seqctl0_print;
1767#else
1768#define ahd_seqctl0_print(regvalue, cur_col, wrap) \
1769    ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap)
1770#endif
1771
1772#if AIC_DEBUG_REGISTERS
1773ahd_reg_print_t ahd_seqctl1_print;
1774#else
1775#define ahd_seqctl1_print(regvalue, cur_col, wrap) \
1776    ahd_print_register(NULL, 0, "SEQCTL1", 0xd7, regvalue, cur_col, wrap)
1777#endif
1778
1779#if AIC_DEBUG_REGISTERS
1780ahd_reg_print_t ahd_flags_print;
1781#else
1782#define ahd_flags_print(regvalue, cur_col, wrap) \
1783    ahd_print_register(NULL, 0, "FLAGS", 0xd8, regvalue, cur_col, wrap)
1784#endif
1785
1786#if AIC_DEBUG_REGISTERS
1787ahd_reg_print_t ahd_seqintctl_print;
1788#else
1789#define ahd_seqintctl_print(regvalue, cur_col, wrap) \
1790    ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap)
1791#endif
1792
1793#if AIC_DEBUG_REGISTERS
1794ahd_reg_print_t ahd_seqram_print;
1795#else
1796#define ahd_seqram_print(regvalue, cur_col, wrap) \
1797    ahd_print_register(NULL, 0, "SEQRAM", 0xda, regvalue, cur_col, wrap)
1798#endif
1799
1800#if AIC_DEBUG_REGISTERS
1801ahd_reg_print_t ahd_prgmcnt_print;
1802#else
1803#define ahd_prgmcnt_print(regvalue, cur_col, wrap) \
1804    ahd_print_register(NULL, 0, "PRGMCNT", 0xde, regvalue, cur_col, wrap)
1805#endif
1806
1807#if AIC_DEBUG_REGISTERS
1808ahd_reg_print_t ahd_accum_print;
1809#else
1810#define ahd_accum_print(regvalue, cur_col, wrap) \
1811    ahd_print_register(NULL, 0, "ACCUM", 0xe0, regvalue, cur_col, wrap)
1812#endif
1813
1814#if AIC_DEBUG_REGISTERS
1815ahd_reg_print_t ahd_sindex_print;
1816#else
1817#define ahd_sindex_print(regvalue, cur_col, wrap) \
1818    ahd_print_register(NULL, 0, "SINDEX", 0xe2, regvalue, cur_col, wrap)
1819#endif
1820
1821#if AIC_DEBUG_REGISTERS
1822ahd_reg_print_t ahd_dindex_print;
1823#else
1824#define ahd_dindex_print(regvalue, cur_col, wrap) \
1825    ahd_print_register(NULL, 0, "DINDEX", 0xe4, regvalue, cur_col, wrap)
1826#endif
1827
1828#if AIC_DEBUG_REGISTERS
1829ahd_reg_print_t ahd_brkaddr1_print;
1830#else
1831#define ahd_brkaddr1_print(regvalue, cur_col, wrap) \
1832    ahd_print_register(NULL, 0, "BRKADDR1", 0xe6, regvalue, cur_col, wrap)
1833#endif
1834
1835#if AIC_DEBUG_REGISTERS
1836ahd_reg_print_t ahd_brkaddr0_print;
1837#else
1838#define ahd_brkaddr0_print(regvalue, cur_col, wrap) \
1839    ahd_print_register(NULL, 0, "BRKADDR0", 0xe6, regvalue, cur_col, wrap)
1840#endif
1841
1842#if AIC_DEBUG_REGISTERS
1843ahd_reg_print_t ahd_allones_print;
1844#else
1845#define ahd_allones_print(regvalue, cur_col, wrap) \
1846    ahd_print_register(NULL, 0, "ALLONES", 0xe8, regvalue, cur_col, wrap)
1847#endif
1848
1849#if AIC_DEBUG_REGISTERS
1850ahd_reg_print_t ahd_allzeros_print;
1851#else
1852#define ahd_allzeros_print(regvalue, cur_col, wrap) \
1853    ahd_print_register(NULL, 0, "ALLZEROS", 0xea, regvalue, cur_col, wrap)
1854#endif
1855
1856#if AIC_DEBUG_REGISTERS
1857ahd_reg_print_t ahd_none_print;
1858#else
1859#define ahd_none_print(regvalue, cur_col, wrap) \
1860    ahd_print_register(NULL, 0, "NONE", 0xea, regvalue, cur_col, wrap)
1861#endif
1862
1863#if AIC_DEBUG_REGISTERS
1864ahd_reg_print_t ahd_sindir_print;
1865#else
1866#define ahd_sindir_print(regvalue, cur_col, wrap) \
1867    ahd_print_register(NULL, 0, "SINDIR", 0xec, regvalue, cur_col, wrap)
1868#endif
1869
1870#if AIC_DEBUG_REGISTERS
1871ahd_reg_print_t ahd_dindir_print;
1872#else
1873#define ahd_dindir_print(regvalue, cur_col, wrap) \
1874    ahd_print_register(NULL, 0, "DINDIR", 0xed, regvalue, cur_col, wrap)
1875#endif
1876
1877#if AIC_DEBUG_REGISTERS
1878ahd_reg_print_t ahd_function1_print;
1879#else
1880#define ahd_function1_print(regvalue, cur_col, wrap) \
1881    ahd_print_register(NULL, 0, "FUNCTION1", 0xf0, regvalue, cur_col, wrap)
1882#endif
1883
1884#if AIC_DEBUG_REGISTERS
1885ahd_reg_print_t ahd_stack_print;
1886#else
1887#define ahd_stack_print(regvalue, cur_col, wrap) \
1888    ahd_print_register(NULL, 0, "STACK", 0xf2, regvalue, cur_col, wrap)
1889#endif
1890
1891#if AIC_DEBUG_REGISTERS
1892ahd_reg_print_t ahd_curaddr_print;
1893#else
1894#define ahd_curaddr_print(regvalue, cur_col, wrap) \
1895    ahd_print_register(NULL, 0, "CURADDR", 0xf4, regvalue, cur_col, wrap)
1896#endif
1897
1898#if AIC_DEBUG_REGISTERS
1899ahd_reg_print_t ahd_intvec1_addr_print;
1900#else
1901#define ahd_intvec1_addr_print(regvalue, cur_col, wrap) \
1902    ahd_print_register(NULL, 0, "INTVEC1_ADDR", 0xf4, regvalue, cur_col, wrap)
1903#endif
1904
1905#if AIC_DEBUG_REGISTERS
1906ahd_reg_print_t ahd_intvec2_addr_print;
1907#else
1908#define ahd_intvec2_addr_print(regvalue, cur_col, wrap) \
1909    ahd_print_register(NULL, 0, "INTVEC2_ADDR", 0xf6, regvalue, cur_col, wrap)
1910#endif
1911
1912#if AIC_DEBUG_REGISTERS
1913ahd_reg_print_t ahd_lastaddr_print;
1914#else
1915#define ahd_lastaddr_print(regvalue, cur_col, wrap) \
1916    ahd_print_register(NULL, 0, "LASTADDR", 0xf6, regvalue, cur_col, wrap)
1917#endif
1918
1919#if AIC_DEBUG_REGISTERS
1920ahd_reg_print_t ahd_longjmp_addr_print;
1921#else
1922#define ahd_longjmp_addr_print(regvalue, cur_col, wrap) \
1923    ahd_print_register(NULL, 0, "LONGJMP_ADDR", 0xf8, regvalue, cur_col, wrap)
1924#endif
1925
1926#if AIC_DEBUG_REGISTERS
1927ahd_reg_print_t ahd_accum_save_print;
1928#else
1929#define ahd_accum_save_print(regvalue, cur_col, wrap) \
1930    ahd_print_register(NULL, 0, "ACCUM_SAVE", 0xfa, regvalue, cur_col, wrap)
1931#endif
1932
1933#if AIC_DEBUG_REGISTERS
1934ahd_reg_print_t ahd_waiting_scb_tails_print;
1935#else
1936#define ahd_waiting_scb_tails_print(regvalue, cur_col, wrap) \
1937    ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 0x100, regvalue, cur_col, wrap)
1938#endif
1939
1940#if AIC_DEBUG_REGISTERS
1941ahd_reg_print_t ahd_ahd_pci_config_base_print;
1942#else
1943#define ahd_ahd_pci_config_base_print(regvalue, cur_col, wrap) \
1944    ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 0x100, regvalue, cur_col, wrap)
1945#endif
1946
1947#if AIC_DEBUG_REGISTERS
1948ahd_reg_print_t ahd_sram_base_print;
1949#else
1950#define ahd_sram_base_print(regvalue, cur_col, wrap) \
1951    ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)
1952#endif
1953
1954#if AIC_DEBUG_REGISTERS
1955ahd_reg_print_t ahd_waiting_tid_head_print;
1956#else
1957#define ahd_waiting_tid_head_print(regvalue, cur_col, wrap) \
1958    ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 0x120, regvalue, cur_col, wrap)
1959#endif
1960
1961#if AIC_DEBUG_REGISTERS
1962ahd_reg_print_t ahd_waiting_tid_tail_print;
1963#else
1964#define ahd_waiting_tid_tail_print(regvalue, cur_col, wrap) \
1965    ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 0x122, regvalue, cur_col, wrap)
1966#endif
1967
1968#if AIC_DEBUG_REGISTERS
1969ahd_reg_print_t ahd_next_queued_scb_addr_print;
1970#else
1971#define ahd_next_queued_scb_addr_print(regvalue, cur_col, wrap) \
1972    ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 0x124, regvalue, cur_col, wrap)
1973#endif
1974
1975#if AIC_DEBUG_REGISTERS
1976ahd_reg_print_t ahd_complete_scb_head_print;
1977#else
1978#define ahd_complete_scb_head_print(regvalue, cur_col, wrap) \
1979    ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 0x128, regvalue, cur_col, wrap)
1980#endif
1981
1982#if AIC_DEBUG_REGISTERS
1983ahd_reg_print_t ahd_complete_scb_dmainprog_head_print;
1984#else
1985#define ahd_complete_scb_dmainprog_head_print(regvalue, cur_col, wrap) \
1986    ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 0x12a, regvalue, cur_col, wrap)
1987#endif
1988
1989#if AIC_DEBUG_REGISTERS
1990ahd_reg_print_t ahd_complete_dma_scb_head_print;
1991#else
1992#define ahd_complete_dma_scb_head_print(regvalue, cur_col, wrap) \
1993    ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 0x12c, regvalue, cur_col, wrap)
1994#endif
1995
1996#if AIC_DEBUG_REGISTERS
1997ahd_reg_print_t ahd_qfreeze_count_print;
1998#else
1999#define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \
2000    ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x12e, regvalue, cur_col, wrap)
2001#endif
2002
2003#if AIC_DEBUG_REGISTERS
2004ahd_reg_print_t ahd_saved_mode_print;
2005#else
2006#define ahd_saved_mode_print(regvalue, cur_col, wrap) \
2007    ahd_print_register(NULL, 0, "SAVED_MODE", 0x130, regvalue, cur_col, wrap)
2008#endif
2009
2010#if AIC_DEBUG_REGISTERS
2011ahd_reg_print_t ahd_msg_out_print;
2012#else
2013#define ahd_msg_out_print(regvalue, cur_col, wrap) \
2014    ahd_print_register(NULL, 0, "MSG_OUT", 0x131, regvalue, cur_col, wrap)
2015#endif
2016
2017#if AIC_DEBUG_REGISTERS
2018ahd_reg_print_t ahd_dmaparams_print;
2019#else
2020#define ahd_dmaparams_print(regvalue, cur_col, wrap) \
2021    ahd_print_register(NULL, 0, "DMAPARAMS", 0x132, regvalue, cur_col, wrap)
2022#endif
2023
2024#if AIC_DEBUG_REGISTERS
2025ahd_reg_print_t ahd_seq_flags_print;
2026#else
2027#define ahd_seq_flags_print(regvalue, cur_col, wrap) \
2028    ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x133, regvalue, cur_col, wrap)
2029#endif
2030
2031#if AIC_DEBUG_REGISTERS
2032ahd_reg_print_t ahd_saved_scsiid_print;
2033#else
2034#define ahd_saved_scsiid_print(regvalue, cur_col, wrap) \
2035    ahd_print_register(NULL, 0, "SAVED_SCSIID", 0x134, regvalue, cur_col, wrap)
2036#endif
2037
2038#if AIC_DEBUG_REGISTERS
2039ahd_reg_print_t ahd_saved_lun_print;
2040#else
2041#define ahd_saved_lun_print(regvalue, cur_col, wrap) \
2042    ahd_print_register(NULL, 0, "SAVED_LUN", 0x135, regvalue, cur_col, wrap)
2043#endif
2044
2045#if AIC_DEBUG_REGISTERS
2046ahd_reg_print_t ahd_lastphase_print;
2047#else
2048#define ahd_lastphase_print(regvalue, cur_col, wrap) \
2049    ahd_print_register(NULL, 0, "LASTPHASE", 0x136, regvalue, cur_col, wrap)
2050#endif
2051
2052#if AIC_DEBUG_REGISTERS
2053ahd_reg_print_t ahd_qoutfifo_entry_valid_tag_print;
2054#else
2055#define ahd_qoutfifo_entry_valid_tag_print(regvalue, cur_col, wrap) \
2056    ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 0x137, regvalue, cur_col, wrap)
2057#endif
2058
2059#if AIC_DEBUG_REGISTERS
2060ahd_reg_print_t ahd_shared_data_addr_print;
2061#else
2062#define ahd_shared_data_addr_print(regvalue, cur_col, wrap) \
2063    ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x138, regvalue, cur_col, wrap)
2064#endif
2065
2066#if AIC_DEBUG_REGISTERS
2067ahd_reg_print_t ahd_qoutfifo_next_addr_print;
2068#else
2069#define ahd_qoutfifo_next_addr_print(regvalue, cur_col, wrap) \
2070    ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 0x13c, regvalue, cur_col, wrap)
2071#endif
2072
2073#if AIC_DEBUG_REGISTERS
2074ahd_reg_print_t ahd_kernel_tqinpos_print;
2075#else
2076#define ahd_kernel_tqinpos_print(regvalue, cur_col, wrap) \
2077    ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 0x140, regvalue, cur_col, wrap)
2078#endif
2079
2080#if AIC_DEBUG_REGISTERS
2081ahd_reg_print_t ahd_tqinpos_print;
2082#else
2083#define ahd_tqinpos_print(regvalue, cur_col, wrap) \
2084    ahd_print_register(NULL, 0, "TQINPOS", 0x141, regvalue, cur_col, wrap)
2085#endif
2086
2087#if AIC_DEBUG_REGISTERS
2088ahd_reg_print_t ahd_arg_1_print;
2089#else
2090#define ahd_arg_1_print(regvalue, cur_col, wrap) \
2091    ahd_print_register(NULL, 0, "ARG_1", 0x142, regvalue, cur_col, wrap)
2092#endif
2093
2094#if AIC_DEBUG_REGISTERS
2095ahd_reg_print_t ahd_arg_2_print;
2096#else
2097#define ahd_arg_2_print(regvalue, cur_col, wrap) \
2098    ahd_print_register(NULL, 0, "ARG_2", 0x143, regvalue, cur_col, wrap)
2099#endif
2100
2101#if AIC_DEBUG_REGISTERS
2102ahd_reg_print_t ahd_last_msg_print;
2103#else
2104#define ahd_last_msg_print(regvalue, cur_col, wrap) \
2105    ahd_print_register(NULL, 0, "LAST_MSG", 0x144, regvalue, cur_col, wrap)
2106#endif
2107
2108#if AIC_DEBUG_REGISTERS
2109ahd_reg_print_t ahd_scsiseq_template_print;
2110#else
2111#define ahd_scsiseq_template_print(regvalue, cur_col, wrap) \
2112    ahd_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x145, regvalue, cur_col, wrap)
2113#endif
2114
2115#if AIC_DEBUG_REGISTERS
2116ahd_reg_print_t ahd_initiator_tag_print;
2117#else
2118#define ahd_initiator_tag_print(regvalue, cur_col, wrap) \
2119    ahd_print_register(NULL, 0, "INITIATOR_TAG", 0x146, regvalue, cur_col, wrap)
2120#endif
2121
2122#if AIC_DEBUG_REGISTERS
2123ahd_reg_print_t ahd_seq_flags2_print;
2124#else
2125#define ahd_seq_flags2_print(regvalue, cur_col, wrap) \
2126    ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x147, regvalue, cur_col, wrap)
2127#endif
2128
2129#if AIC_DEBUG_REGISTERS
2130ahd_reg_print_t ahd_allocfifo_scbptr_print;
2131#else
2132#define ahd_allocfifo_scbptr_print(regvalue, cur_col, wrap) \
2133    ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 0x148, regvalue, cur_col, wrap)
2134#endif
2135
2136#if AIC_DEBUG_REGISTERS
2137ahd_reg_print_t ahd_int_coalescing_timer_print;
2138#else
2139#define ahd_int_coalescing_timer_print(regvalue, cur_col, wrap) \
2140    ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 0x14a, regvalue, cur_col, wrap)
2141#endif
2142
2143#if AIC_DEBUG_REGISTERS
2144ahd_reg_print_t ahd_int_coalescing_maxcmds_print;
2145#else
2146#define ahd_int_coalescing_maxcmds_print(regvalue, cur_col, wrap) \
2147    ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 0x14c, regvalue, cur_col, wrap)
2148#endif
2149
2150#if AIC_DEBUG_REGISTERS
2151ahd_reg_print_t ahd_int_coalescing_mincmds_print;
2152#else
2153#define ahd_int_coalescing_mincmds_print(regvalue, cur_col, wrap) \
2154    ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 0x14d, regvalue, cur_col, wrap)
2155#endif
2156
2157#if AIC_DEBUG_REGISTERS
2158ahd_reg_print_t ahd_cmds_pending_print;
2159#else
2160#define ahd_cmds_pending_print(regvalue, cur_col, wrap) \
2161    ahd_print_register(NULL, 0, "CMDS_PENDING", 0x14e, regvalue, cur_col, wrap)
2162#endif
2163
2164#if AIC_DEBUG_REGISTERS
2165ahd_reg_print_t ahd_int_coalescing_cmdcount_print;
2166#else
2167#define ahd_int_coalescing_cmdcount_print(regvalue, cur_col, wrap) \
2168    ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 0x150, regvalue, cur_col, wrap)
2169#endif
2170
2171#if AIC_DEBUG_REGISTERS
2172ahd_reg_print_t ahd_local_hs_mailbox_print;
2173#else
2174#define ahd_local_hs_mailbox_print(regvalue, cur_col, wrap) \
2175    ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 0x151, regvalue, cur_col, wrap)
2176#endif
2177
2178#if AIC_DEBUG_REGISTERS
2179ahd_reg_print_t ahd_cmdsize_table_print;
2180#else
2181#define ahd_cmdsize_table_print(regvalue, cur_col, wrap) \
2182    ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 0x152, regvalue, cur_col, wrap)
2183#endif
2184
2185#if AIC_DEBUG_REGISTERS
2186ahd_reg_print_t ahd_scb_base_print;
2187#else
2188#define ahd_scb_base_print(regvalue, cur_col, wrap) \
2189    ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)
2190#endif
2191
2192#if AIC_DEBUG_REGISTERS
2193ahd_reg_print_t ahd_scb_residual_datacnt_print;
2194#else
2195#define ahd_scb_residual_datacnt_print(regvalue, cur_col, wrap) \
2196    ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 0x180, regvalue, cur_col, wrap)
2197#endif
2198
2199#if AIC_DEBUG_REGISTERS
2200ahd_reg_print_t ahd_scb_residual_sgptr_print;
2201#else
2202#define ahd_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
2203    ahd_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0x184, regvalue, cur_col, wrap)
2204#endif
2205
2206#if AIC_DEBUG_REGISTERS
2207ahd_reg_print_t ahd_scb_scsi_status_print;
2208#else
2209#define ahd_scb_scsi_status_print(regvalue, cur_col, wrap) \
2210    ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 0x188, regvalue, cur_col, wrap)
2211#endif
2212
2213#if AIC_DEBUG_REGISTERS
2214ahd_reg_print_t ahd_scb_target_phases_print;
2215#else
2216#define ahd_scb_target_phases_print(regvalue, cur_col, wrap) \
2217    ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 0x189, regvalue, cur_col, wrap)
2218#endif
2219
2220#if AIC_DEBUG_REGISTERS
2221ahd_reg_print_t ahd_scb_target_data_dir_print;
2222#else
2223#define ahd_scb_target_data_dir_print(regvalue, cur_col, wrap) \
2224    ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0x18a, regvalue, cur_col, wrap)
2225#endif
2226
2227#if AIC_DEBUG_REGISTERS
2228ahd_reg_print_t ahd_scb_target_itag_print;
2229#else
2230#define ahd_scb_target_itag_print(regvalue, cur_col, wrap) \
2231    ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 0x18b, regvalue, cur_col, wrap)
2232#endif
2233
2234#if AIC_DEBUG_REGISTERS
2235ahd_reg_print_t ahd_scb_sense_busaddr_print;
2236#else
2237#define ahd_scb_sense_busaddr_print(regvalue, cur_col, wrap) \
2238    ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 0x18c, regvalue, cur_col, wrap)
2239#endif
2240
2241#if AIC_DEBUG_REGISTERS
2242ahd_reg_print_t ahd_scb_tag_print;
2243#else
2244#define ahd_scb_tag_print(regvalue, cur_col, wrap) \
2245    ahd_print_register(NULL, 0, "SCB_TAG", 0x190, regvalue, cur_col, wrap)
2246#endif
2247
2248#if AIC_DEBUG_REGISTERS
2249ahd_reg_print_t ahd_scb_control_print;
2250#else
2251#define ahd_scb_control_print(regvalue, cur_col, wrap) \
2252    ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap)
2253#endif
2254
2255#if AIC_DEBUG_REGISTERS
2256ahd_reg_print_t ahd_scb_scsiid_print;
2257#else
2258#define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \
2259    ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap)
2260#endif
2261
2262#if AIC_DEBUG_REGISTERS
2263ahd_reg_print_t ahd_scb_lun_print;
2264#else
2265#define ahd_scb_lun_print(regvalue, cur_col, wrap) \
2266    ahd_print_register(NULL, 0, "SCB_LUN", 0x194, regvalue, cur_col, wrap)
2267#endif
2268
2269#if AIC_DEBUG_REGISTERS
2270ahd_reg_print_t ahd_scb_task_attribute_print;
2271#else
2272#define ahd_scb_task_attribute_print(regvalue, cur_col, wrap) \
2273    ahd_print_register(NULL, 0, "SCB_TASK_ATTRIBUTE", 0x195, regvalue, cur_col, wrap)
2274#endif
2275
2276#if AIC_DEBUG_REGISTERS
2277ahd_reg_print_t ahd_scb_cdb_len_print;
2278#else
2279#define ahd_scb_cdb_len_print(regvalue, cur_col, wrap) \
2280    ahd_print_register(NULL, 0, "SCB_CDB_LEN", 0x196, regvalue, cur_col, wrap)
2281#endif
2282
2283#if AIC_DEBUG_REGISTERS
2284ahd_reg_print_t ahd_scb_task_management_print;
2285#else
2286#define ahd_scb_task_management_print(regvalue, cur_col, wrap) \
2287    ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 0x197, regvalue, cur_col, wrap)
2288#endif
2289
2290#if AIC_DEBUG_REGISTERS
2291ahd_reg_print_t ahd_scb_dataptr_print;
2292#else
2293#define ahd_scb_dataptr_print(regvalue, cur_col, wrap) \
2294    ahd_print_register(NULL, 0, "SCB_DATAPTR", 0x198, regvalue, cur_col, wrap)
2295#endif
2296
2297#if AIC_DEBUG_REGISTERS
2298ahd_reg_print_t ahd_scb_datacnt_print;
2299#else
2300#define ahd_scb_datacnt_print(regvalue, cur_col, wrap) \
2301    ahd_print_register(NULL, 0, "SCB_DATACNT", 0x1a0, regvalue, cur_col, wrap)
2302#endif
2303
2304#if AIC_DEBUG_REGISTERS
2305ahd_reg_print_t ahd_scb_sgptr_print;
2306#else
2307#define ahd_scb_sgptr_print(regvalue, cur_col, wrap) \
2308    ahd_print_register(NULL, 0, "SCB_SGPTR", 0x1a4, regvalue, cur_col, wrap)
2309#endif
2310
2311#if AIC_DEBUG_REGISTERS
2312ahd_reg_print_t ahd_scb_busaddr_print;
2313#else
2314#define ahd_scb_busaddr_print(regvalue, cur_col, wrap) \
2315    ahd_print_register(NULL, 0, "SCB_BUSADDR", 0x1a8, regvalue, cur_col, wrap)
2316#endif
2317
2318#if AIC_DEBUG_REGISTERS
2319ahd_reg_print_t ahd_scb_next_print;
2320#else
2321#define ahd_scb_next_print(regvalue, cur_col, wrap) \
2322    ahd_print_register(NULL, 0, "SCB_NEXT", 0x1ac, regvalue, cur_col, wrap)
2323#endif
2324
2325#if AIC_DEBUG_REGISTERS
2326ahd_reg_print_t ahd_scb_next2_print;
2327#else
2328#define ahd_scb_next2_print(regvalue, cur_col, wrap) \
2329    ahd_print_register(NULL, 0, "SCB_NEXT2", 0x1ae, regvalue, cur_col, wrap)
2330#endif
2331
2332#if AIC_DEBUG_REGISTERS
2333ahd_reg_print_t ahd_scb_spare_print;
2334#else
2335#define ahd_scb_spare_print(regvalue, cur_col, wrap) \
2336    ahd_print_register(NULL, 0, "SCB_SPARE", 0x1b0, regvalue, cur_col, wrap)
2337#endif
2338
2339#if AIC_DEBUG_REGISTERS
2340ahd_reg_print_t ahd_scb_disconnected_lists_print;
2341#else
2342#define ahd_scb_disconnected_lists_print(regvalue, cur_col, wrap) \
2343    ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 0x1b8, regvalue, cur_col, wrap)
2344#endif
2345
2346
2347#define	MODE_PTR        		0x00
2348#define		DST_MODE        	0x70
2349#define		SRC_MODE        	0x07
2350
2351#define	INTSTAT         		0x01
2352#define		INT_PEND        	0xff
2353#define		HWERRINT        	0x80
2354#define		BRKADRINT       	0x40
2355#define		SWTMINT         	0x20
2356#define		PCIINT          	0x10
2357#define		SCSIINT         	0x08
2358#define		SEQINT          	0x04
2359#define		CMDCMPLT        	0x02
2360#define		SPLTINT         	0x01
2361
2362#define	SEQINTCODE      		0x02
2363#define		BAD_SCB_STATUS  	0x1a
2364#define		SAW_HWERR       	0x19
2365#define		TRACEPOINT3     	0x18
2366#define		TRACEPOINT2     	0x17
2367#define		TRACEPOINT1     	0x16
2368#define		TRACEPOINT0     	0x15
2369#define		TASKMGMT_CMD_CMPLT_OKAY	0x14
2370#define		TASKMGMT_FUNC_COMPLETE	0x13
2371#define		ENTERING_NONPACK	0x12
2372#define		CFG4OVERRUN     	0x11
2373#define		STATUS_OVERRUN  	0x10
2374#define		CFG4ISTAT_INTR  	0x0f
2375#define		INVALID_SEQINT  	0x0e
2376#define		ILLEGAL_PHASE   	0x0d
2377#define		DUMP_CARD_STATE 	0x0c
2378#define		MISSED_BUSFREE  	0x0b
2379#define		MKMSG_FAILED    	0x0a
2380#define		DATA_OVERRUN    	0x09
2381#define		BAD_STATUS      	0x08
2382#define		HOST_MSG_LOOP   	0x07
2383#define		PDATA_REINIT    	0x06
2384#define		IGN_WIDE_RES    	0x05
2385#define		NO_MATCH        	0x04
2386#define		PROTO_VIOLATION 	0x03
2387#define		SEND_REJECT     	0x02
2388#define		BAD_PHASE       	0x01
2389#define		NO_SEQINT       	0x00
2390
2391#define	CLRINT          		0x03
2392#define		CLRHWERRINT     	0x80
2393#define		CLRBRKADRINT    	0x40
2394#define		CLRSWTMINT      	0x20
2395#define		CLRPCIINT       	0x10
2396#define		CLRSCSIINT      	0x08
2397#define		CLRSEQINT       	0x04
2398#define		CLRCMDINT       	0x02
2399#define		CLRSPLTINT      	0x01
2400
2401#define	ERROR           		0x04
2402#define		CIOPARERR       	0x80
2403#define		CIOACCESFAIL    	0x40
2404#define		MPARERR         	0x20
2405#define		DPARERR         	0x10
2406#define		SQPARERR        	0x08
2407#define		ILLOPCODE       	0x04
2408#define		DSCTMOUT        	0x02
2409
2410#define	CLRERR          		0x04
2411#define		CLRCIOPARERR    	0x80
2412#define		CLRCIOACCESFAIL 	0x40
2413#define		CLRMPARERR      	0x20
2414#define		CLRDPARERR      	0x10
2415#define		CLRSQPARERR     	0x08
2416#define		CLRILLOPCODE    	0x04
2417#define		CLRDSCTMOUT     	0x02
2418
2419#define	HCNTRL          		0x05
2420#define		SEQ_RESET       	0x80
2421#define		POWRDN          	0x40
2422#define		SWINT           	0x10
2423#define		SWTIMER_START_B 	0x08
2424#define		PAUSE           	0x04
2425#define		INTEN           	0x02
2426#define		CHIPRST         	0x01
2427#define		CHIPRSTACK      	0x01
2428
2429#define	HNSCB_QOFF      		0x06
2430
2431#define	HESCB_QOFF      		0x08
2432
2433#define	HS_MAILBOX      		0x0b
2434#define		HOST_TQINPOS    	0x80
2435#define		ENINT_COALESCE  	0x40
2436
2437#define	CLRSEQINTSTAT   		0x0c
2438#define		CLRSEQ_SWTMRTO  	0x10
2439#define		CLRSEQ_SEQINT   	0x08
2440#define		CLRSEQ_SCSIINT  	0x04
2441#define		CLRSEQ_PCIINT   	0x02
2442#define		CLRSEQ_SPLTINT  	0x01
2443
2444#define	SEQINTSTAT      		0x0c
2445#define		SEQ_SWTMRTO     	0x10
2446#define		SEQ_SEQINT      	0x08
2447#define		SEQ_SCSIINT     	0x04
2448#define		SEQ_PCIINT      	0x02
2449#define		SEQ_SPLTINT     	0x01
2450
2451#define	SWTIMER         		0x0e
2452
2453#define	SNSCB_QOFF      		0x10
2454
2455#define	SESCB_QOFF      		0x12
2456
2457#define	SDSCB_QOFF      		0x14
2458
2459#define	QOFF_CTLSTA     		0x16
2460#define		EMPTY_SCB_AVAIL 	0x80
2461#define		NEW_SCB_AVAIL   	0x40
2462#define		SDSCB_ROLLOVR   	0x20
2463#define		HS_MAILBOX_ACT  	0x10
2464#define		SCB_QSIZE       	0x0f
2465#define		SCB_QSIZE_16384 	0x0c
2466#define		SCB_QSIZE_8192  	0x0b
2467#define		SCB_QSIZE_4096  	0x0a
2468#define		SCB_QSIZE_2048  	0x09
2469#define		SCB_QSIZE_1024  	0x08
2470#define		SCB_QSIZE_512   	0x07
2471#define		SCB_QSIZE_256   	0x06
2472#define		SCB_QSIZE_128   	0x05
2473#define		SCB_QSIZE_64    	0x04
2474#define		SCB_QSIZE_32    	0x03
2475#define		SCB_QSIZE_16    	0x02
2476#define		SCB_QSIZE_8     	0x01
2477#define		SCB_QSIZE_4     	0x00
2478
2479#define	INTCTL          		0x18
2480#define		SWTMINTMASK     	0x80
2481#define		SWTMINTEN       	0x40
2482#define		SWTIMER_START   	0x20
2483#define		AUTOCLRCMDINT   	0x10
2484#define		PCIINTEN        	0x08
2485#define		SCSIINTEN       	0x04
2486#define		SEQINTEN        	0x02
2487#define		SPLTINTEN       	0x01
2488
2489#define	DFCNTRL         		0x19
2490#define		SCSIENWRDIS     	0x40
2491#define		SCSIENACK       	0x20
2492#define		DIRECTIONACK    	0x04
2493#define		FIFOFLUSHACK    	0x02
2494#define		DIRECTIONEN     	0x01
2495
2496#define	DSCOMMAND0      		0x19
2497#define		CACHETHEN       	0x80
2498#define		DPARCKEN        	0x40
2499#define		MPARCKEN        	0x20
2500#define		EXTREQLCK       	0x10
2501#define		DISABLE_TWATE   	0x02
2502#define		CIOPARCKEN      	0x01
2503
2504#define	DFSTATUS        		0x1a
2505#define		PRELOAD_AVAIL   	0x80
2506#define		PKT_PRELOAD_AVAIL	0x40
2507#define		MREQPEND        	0x10
2508#define		HDONE           	0x08
2509#define		DFTHRESH        	0x04
2510#define		FIFOFULL        	0x02
2511#define		FIFOEMP         	0x01
2512
2513#define	SG_CACHE_SHADOW 		0x1b
2514#define		ODD_SEG         	0x04
2515#define		LAST_SEG        	0x02
2516#define		LAST_SEG_DONE   	0x01
2517
2518#define	ARBCTL          		0x1b
2519#define		RESET_HARB      	0x80
2520#define		RETRY_SWEN      	0x08
2521#define		USE_TIME        	0x07
2522
2523#define	SG_CACHE_PRE    		0x1b
2524
2525#define	LQIN            		0x20
2526
2527#define	TYPEPTR         		0x20
2528
2529#define	TAGPTR          		0x21
2530
2531#define	LUNPTR          		0x22
2532
2533#define	DATALENPTR      		0x23
2534
2535#define	STATLENPTR      		0x24
2536
2537#define	CMDLENPTR       		0x25
2538
2539#define	ATTRPTR         		0x26
2540
2541#define	FLAGPTR         		0x27
2542
2543#define	CMDPTR          		0x28
2544
2545#define	QNEXTPTR        		0x29
2546
2547#define	IDPTR           		0x2a
2548
2549#define	ABRTBYTEPTR     		0x2b
2550
2551#define	ABRTBITPTR      		0x2c
2552
2553#define	MAXCMDBYTES     		0x2d
2554
2555#define	MAXCMD2RCV      		0x2e
2556
2557#define	SHORTTHRESH     		0x2f
2558
2559#define	LUNLEN          		0x30
2560#define		TLUNLEN         	0xf0
2561#define		ILUNLEN         	0x0f
2562
2563#define	CDBLIMIT        		0x31
2564
2565#define	MAXCMD          		0x32
2566
2567#define	MAXCMDCNT       		0x33
2568
2569#define	LQRSVD01        		0x34
2570
2571#define	LQRSVD16        		0x35
2572
2573#define	LQRSVD17        		0x36
2574
2575#define	CMDRSVD0        		0x37
2576
2577#define	LQCTL0          		0x38
2578#define		LQITARGCLT      	0xc0
2579#define		LQIINITGCLT     	0x30
2580#define		LQ0TARGCLT      	0x0c
2581#define		LQ0INITGCLT     	0x03
2582
2583#define	LQCTL1          		0x38
2584#define		PCI2PCI         	0x04
2585#define		SINGLECMD       	0x02
2586#define		ABORTPENDING    	0x01
2587
2588#define	SCSBIST0        		0x39
2589#define		GSBISTERR       	0x40
2590#define		GSBISTDONE      	0x20
2591#define		GSBISTRUN       	0x10
2592#define		OSBISTERR       	0x04
2593#define		OSBISTDONE      	0x02
2594#define		OSBISTRUN       	0x01
2595
2596#define	LQCTL2          		0x39
2597#define		LQIRETRY        	0x80
2598#define		LQICONTINUE     	0x40
2599#define		LQITOIDLE       	0x20
2600#define		LQIPAUSE        	0x10
2601#define		LQORETRY        	0x08
2602#define		LQOCONTINUE     	0x04
2603#define		LQOTOIDLE       	0x02
2604#define		LQOPAUSE        	0x01
2605
2606#define	SCSBIST1        		0x3a
2607#define		NTBISTERR       	0x04
2608#define		NTBISTDONE      	0x02
2609#define		NTBISTRUN       	0x01
2610
2611#define	SCSISEQ0        		0x3a
2612#define		TEMODEO         	0x80
2613#define		ENSELO          	0x40
2614#define		ENARBO          	0x20
2615#define		FORCEBUSFREE    	0x10
2616#define		SCSIRSTO        	0x01
2617
2618#define	SCSISEQ1        		0x3b
2619
2620#define	SXFRCTL0        		0x3c
2621#define		DFON            	0x80
2622#define		DFPEXP          	0x40
2623#define		BIOSCANCELEN    	0x10
2624#define		SPIOEN          	0x08
2625
2626#define	BUSINITID       		0x3c
2627
2628#define	DLCOUNT         		0x3c
2629
2630#define	SXFRCTL1        		0x3d
2631#define		BITBUCKET       	0x80
2632#define		ENSACHK         	0x40
2633#define		ENSPCHK         	0x20
2634#define		STIMESEL        	0x18
2635#define		ENSTIMER        	0x04
2636#define		ACTNEGEN        	0x02
2637#define		STPWEN          	0x01
2638
2639#define	BUSTARGID       		0x3e
2640
2641#define	SXFRCTL2        		0x3e
2642#define		AUTORSTDIS      	0x10
2643#define		CMDDMAEN        	0x08
2644#define		ASU             	0x07
2645
2646#define	DFFSTAT         		0x3f
2647#define		CURRFIFO        	0x03
2648#define		FIFO1FREE       	0x20
2649#define		FIFO0FREE       	0x10
2650#define		CURRFIFO_NONE   	0x03
2651#define		CURRFIFO_1      	0x01
2652#define		CURRFIFO_0      	0x00
2653
2654#define	SCSISIGO        		0x40
2655#define		CDO             	0x80
2656#define		IOO             	0x40
2657#define		MSGO            	0x20
2658#define		ATNO            	0x10
2659#define		SELO            	0x08
2660#define		BSYO            	0x04
2661#define		REQO            	0x02
2662#define		ACKO            	0x01
2663
2664#define	MULTARGID       		0x40
2665
2666#define	SCSISIGI        		0x41
2667#define		ATNI            	0x10
2668#define		SELI            	0x08
2669#define		BSYI            	0x04
2670#define		REQI            	0x02
2671#define		ACKI            	0x01
2672
2673#define	SCSIPHASE       		0x42
2674#define		STATUS_PHASE    	0x20
2675#define		COMMAND_PHASE   	0x10
2676#define		MSG_IN_PHASE    	0x08
2677#define		MSG_OUT_PHASE   	0x04
2678#define		DATA_PHASE_MASK 	0x03
2679#define		DATA_IN_PHASE   	0x02
2680#define		DATA_OUT_PHASE  	0x01
2681
2682#define	SCSIDAT0_IMG    		0x43
2683
2684#define	SCSIDAT         		0x44
2685
2686#define	SCSIBUS         		0x46
2687
2688#define	TARGIDIN        		0x48
2689#define		CLKOUT          	0x80
2690#define		TARGID          	0x0f
2691
2692#define	SELID           		0x49
2693#define		SELID_MASK      	0xf0
2694#define		ONEBIT          	0x08
2695
2696#define	SBLKCTL         		0x4a
2697#define		DIAGLEDEN       	0x80
2698#define		DIAGLEDON       	0x40
2699#define		ENAB40          	0x08
2700#define		ENAB20          	0x04
2701#define		SELWIDE         	0x02
2702
2703#define	OPTIONMODE      		0x4a
2704#define		OPTIONMODE_DEFAULTS	0x02
2705#define		BIOSCANCTL      	0x80
2706#define		AUTOACKEN       	0x40
2707#define		BIASCANCTL      	0x20
2708#define		BUSFREEREV      	0x10
2709#define		ENDGFORMCHK     	0x04
2710#define		AUTO_MSGOUT_DE  	0x02
2711
2712#define	SSTAT0          		0x4b
2713#define		TARGET          	0x80
2714#define		SELDO           	0x40
2715#define		SELDI           	0x20
2716#define		SELINGO         	0x10
2717#define		IOERR           	0x08
2718#define		OVERRUN         	0x04
2719#define		SPIORDY         	0x02
2720#define		ARBDO           	0x01
2721
2722#define	CLRSINT0        		0x4b
2723#define		CLRSELDO        	0x40
2724#define		CLRSELDI        	0x20
2725#define		CLRSELINGO      	0x10
2726#define		CLRIOERR        	0x08
2727#define		CLROVERRUN      	0x04
2728#define		CLRSPIORDY      	0x02
2729#define		CLRARBDO        	0x01
2730
2731#define	SIMODE0         		0x4b
2732#define		ENSELDO         	0x40
2733#define		ENSELDI         	0x20
2734#define		ENSELINGO       	0x10
2735#define		ENIOERR         	0x08
2736#define		ENOVERRUN       	0x04
2737#define		ENSPIORDY       	0x02
2738#define		ENARBDO         	0x01
2739
2740#define	CLRSINT1        		0x4c
2741#define		CLRSELTIMEO     	0x80
2742#define		CLRATNO         	0x40
2743#define		CLRSCSIRSTI     	0x20
2744#define		CLRBUSFREE      	0x08
2745#define		CLRSCSIPERR     	0x04
2746#define		CLRSTRB2FAST    	0x02
2747#define		CLRREQINIT      	0x01
2748
2749#define	SSTAT1          		0x4c
2750#define		SELTO           	0x80
2751#define		ATNTARG         	0x40
2752#define		SCSIRSTI        	0x20
2753#define		PHASEMIS        	0x10
2754#define		BUSFREE         	0x08
2755#define		SCSIPERR        	0x04
2756#define		STRB2FAST       	0x02
2757#define		REQINIT         	0x01
2758
2759#define	SSTAT2          		0x4d
2760#define		BUSFREETIME     	0xc0
2761#define		NONPACKREQ      	0x20
2762#define		EXP_ACTIVE      	0x10
2763#define		BSYX            	0x08
2764#define		WIDE_RES        	0x04
2765#define		SDONE           	0x02
2766#define		DMADONE         	0x01
2767#define		BUSFREE_DFF1    	0xc0
2768#define		BUSFREE_DFF0    	0x80
2769#define		BUSFREE_LQO     	0x40
2770
2771#define	CLRSINT2        		0x4d
2772#define		CLRNONPACKREQ   	0x20
2773#define		CLRWIDE_RES     	0x04
2774#define		CLRSDONE        	0x02
2775#define		CLRDMADONE      	0x01
2776
2777#define	SIMODE2         		0x4d
2778#define		ENWIDE_RES      	0x04
2779#define		ENSDONE         	0x02
2780#define		ENDMADONE       	0x01
2781
2782#define	PERRDIAG        		0x4e
2783#define		HIZERO          	0x80
2784#define		HIPERR          	0x40
2785#define		PREVPHASE       	0x20
2786#define		PARITYERR       	0x10
2787#define		AIPERR          	0x08
2788#define		CRCERR          	0x04
2789#define		DGFORMERR       	0x02
2790#define		DTERR           	0x01
2791
2792#define	LQISTATE        		0x4e
2793
2794#define	SOFFCNT         		0x4f
2795
2796#define	LQOSTATE        		0x4f
2797
2798#define	LQISTAT0        		0x50
2799#define		LQIATNQAS       	0x20
2800#define		LQICRCT1        	0x10
2801#define		LQICRCT2        	0x08
2802#define		LQIBADLQT       	0x04
2803#define		LQIATNLQ        	0x02
2804#define		LQIATNCMD       	0x01
2805
2806#define	CLRLQIINT0      		0x50
2807#define		CLRLQIATNQAS    	0x20
2808#define		CLRLQICRCT1     	0x10
2809#define		CLRLQICRCT2     	0x08
2810#define		CLRLQIBADLQT    	0x04
2811#define		CLRLQIATNLQ     	0x02
2812#define		CLRLQIATNCMD    	0x01
2813
2814#define	LQIMODE0        		0x50
2815#define		ENLQIATNQASK    	0x20
2816#define		ENLQICRCT1      	0x10
2817#define		ENLQICRCT2      	0x08
2818#define		ENLQIBADLQT     	0x04
2819#define		ENLQIATNLQ      	0x02
2820#define		ENLQIATNCMD     	0x01
2821
2822#define	LQIMODE1        		0x51
2823#define		ENLQIPHASE_LQ   	0x80
2824#define		ENLQIPHASE_NLQ  	0x40
2825#define		ENLIQABORT      	0x20
2826#define		ENLQICRCI_LQ    	0x10
2827#define		ENLQICRCI_NLQ   	0x08
2828#define		ENLQIBADLQI     	0x04
2829#define		ENLQIOVERI_LQ   	0x02
2830#define		ENLQIOVERI_NLQ  	0x01
2831
2832#define	LQISTAT1        		0x51
2833#define		LQIPHASE_LQ     	0x80
2834#define		LQIPHASE_NLQ    	0x40
2835#define		LQIABORT        	0x20
2836#define		LQICRCI_LQ      	0x10
2837#define		LQICRCI_NLQ     	0x08
2838#define		LQIBADLQI       	0x04
2839#define		LQIOVERI_LQ     	0x02
2840#define		LQIOVERI_NLQ    	0x01
2841
2842#define	CLRLQIINT1      		0x51
2843#define		CLRLQIPHASE_LQ  	0x80
2844#define		CLRLQIPHASE_NLQ 	0x40
2845#define		CLRLIQABORT     	0x20
2846#define		CLRLQICRCI_LQ   	0x10
2847#define		CLRLQICRCI_NLQ  	0x08
2848#define		CLRLQIBADLQI    	0x04
2849#define		CLRLQIOVERI_LQ  	0x02
2850#define		CLRLQIOVERI_NLQ 	0x01
2851
2852#define	LQISTAT2        		0x52
2853#define		PACKETIZED      	0x80
2854#define		LQIPHASE_OUTPKT 	0x40
2855#define		LQIWORKONLQ     	0x20
2856#define		LQIWAITFIFO     	0x10
2857#define		LQISTOPPKT      	0x08
2858#define		LQISTOPLQ       	0x04
2859#define		LQISTOPCMD      	0x02
2860#define		LQIGSAVAIL      	0x01
2861
2862#define	SSTAT3          		0x53
2863#define		NTRAMPERR       	0x02
2864#define		OSRAMPERR       	0x01
2865
2866#define	SIMODE3         		0x53
2867#define		ENNTRAMPERR     	0x02
2868#define		ENOSRAMPERR     	0x01
2869
2870#define	CLRSINT3        		0x53
2871#define		CLRNTRAMPERR    	0x02
2872#define		CLROSRAMPERR    	0x01
2873
2874#define	LQOMODE0        		0x54
2875#define		ENLQOTARGSCBPERR	0x10
2876#define		ENLQOSTOPT2     	0x08
2877#define		ENLQOATNLQ      	0x04
2878#define		ENLQOATNPKT     	0x02
2879#define		ENLQOTCRC       	0x01
2880
2881#define	LQOSTAT0        		0x54
2882#define		LQOTARGSCBPERR  	0x10
2883#define		LQOSTOPT2       	0x08
2884#define		LQOATNLQ        	0x04
2885#define		LQOATNPKT       	0x02
2886#define		LQOTCRC         	0x01
2887
2888#define	CLRLQOINT0      		0x54
2889#define		CLRLQOTARGSCBPERR	0x10
2890#define		CLRLQOSTOPT2    	0x08
2891#define		CLRLQOATNLQ     	0x04
2892#define		CLRLQOATNPKT    	0x02
2893#define		CLRLQOTCRC      	0x01
2894
2895#define	LQOSTAT1        		0x55
2896#define		LQOINITSCBPERR  	0x10
2897#define		LQOSTOPI2       	0x08
2898#define		LQOBADQAS       	0x04
2899#define		LQOBUSFREE      	0x02
2900#define		LQOPHACHGINPKT  	0x01
2901
2902#define	CLRLQOINT1      		0x55
2903#define		CLRLQOINITSCBPERR	0x10
2904#define		CLRLQOSTOPI2    	0x08
2905#define		CLRLQOBADQAS    	0x04
2906#define		CLRLQOBUSFREE   	0x02
2907#define		CLRLQOPHACHGINPKT	0x01
2908
2909#define	LQOMODE1        		0x55
2910#define		ENLQOINITSCBPERR	0x10
2911#define		ENLQOSTOPI2     	0x08
2912#define		ENLQOBADQAS     	0x04
2913#define		ENLQOBUSFREE    	0x02
2914#define		ENLQOPHACHGINPKT	0x01
2915
2916#define	LQOSTAT2        		0x56
2917#define		LQOPKT          	0xe0
2918#define		LQOWAITFIFO     	0x10
2919#define		LQOPHACHGOUTPKT 	0x02
2920#define		LQOSTOP0        	0x01
2921
2922#define	OS_SPACE_CNT    		0x56
2923
2924#define	SIMODE1         		0x57
2925#define		ENSELTIMO       	0x80
2926#define		ENATNTARG       	0x40
2927#define		ENSCSIRST       	0x20
2928#define		ENPHASEMIS      	0x10
2929#define		ENBUSFREE       	0x08
2930#define		ENSCSIPERR      	0x04
2931#define		ENSTRB2FAST     	0x02
2932#define		ENREQINIT       	0x01
2933
2934#define	GSFIFO          		0x58
2935
2936#define	DFFSXFRCTL      		0x5a
2937#define		DFFBITBUCKET    	0x08
2938#define		CLRSHCNT        	0x04
2939#define		CLRCHN          	0x02
2940#define		RSTCHN          	0x01
2941
2942#define	LQOSCSCTL       		0x5a
2943#define		LQOH2A_VERSION  	0x80
2944#define		LQONOCHKOVER    	0x01
2945
2946#define	NEXTSCB         		0x5a
2947
2948#define	CLRSEQINTSRC    		0x5b
2949#define		CLRCTXTDONE     	0x40
2950#define		CLRSAVEPTRS     	0x20
2951#define		CLRCFG4DATA     	0x10
2952#define		CLRCFG4ISTAT    	0x08
2953#define		CLRCFG4TSTAT    	0x04
2954#define		CLRCFG4ICMD     	0x02
2955#define		CLRCFG4TCMD     	0x01
2956
2957#define	SEQINTSRC       		0x5b
2958#define		CTXTDONE        	0x40
2959#define		SAVEPTRS        	0x20
2960#define		CFG4DATA        	0x10
2961#define		CFG4ISTAT       	0x08
2962#define		CFG4TSTAT       	0x04
2963#define		CFG4ICMD        	0x02
2964#define		CFG4TCMD        	0x01
2965
2966#define	CURRSCB         		0x5c
2967
2968#define	SEQIMODE        		0x5c
2969#define		ENCTXTDONE      	0x40
2970#define		ENSAVEPTRS      	0x20
2971#define		ENCFG4DATA      	0x10
2972#define		ENCFG4ISTAT     	0x08
2973#define		ENCFG4TSTAT     	0x04
2974#define		ENCFG4ICMD      	0x02
2975#define		ENCFG4TCMD      	0x01
2976
2977#define	MDFFSTAT        		0x5d
2978#define		SHCNTNEGATIVE   	0x40
2979#define		SHCNTMINUS1     	0x20
2980#define		LASTSDONE       	0x10
2981#define		SHVALID         	0x08
2982#define		DLZERO          	0x04
2983#define		DATAINFIFO      	0x02
2984#define		FIFOFREE        	0x01
2985
2986#define	CRCCONTROL      		0x5d
2987#define		CRCVALCHKEN     	0x40
2988
2989#define	DFFTAG          		0x5e
2990
2991#define	LASTSCB         		0x5e
2992
2993#define	SCSITEST        		0x5e
2994#define		CNTRTEST        	0x08
2995#define		SEL_TXPLL_DEBUG 	0x04
2996
2997#define	IOPDNCTL        		0x5f
2998#define		DISABLE_OE      	0x80
2999#define		PDN_IDIST       	0x04
3000#define		PDN_DIFFSENSE   	0x01
3001
3002#define	SHADDR          		0x60
3003
3004#define	NEGOADDR        		0x60
3005
3006#define	DGRPCRCI        		0x60
3007
3008#define	NEGPERIOD       		0x61
3009
3010#define	PACKCRCI        		0x62
3011
3012#define	NEGOFFSET       		0x62
3013
3014#define	NEGPPROPTS      		0x63
3015#define		PPROPT_PACE     	0x08
3016#define		PPROPT_QAS      	0x04
3017#define		PPROPT_DT       	0x02
3018#define		PPROPT_IUT      	0x01
3019
3020#define	NEGCONOPTS      		0x64
3021#define		ENSNAPSHOT      	0x40
3022#define		RTI_WRTDIS      	0x20
3023#define		RTI_OVRDTRN     	0x10
3024#define		ENSLOWCRC       	0x08
3025#define		ENAUTOATNI      	0x04
3026#define		ENAUTOATNO      	0x02
3027#define		WIDEXFER        	0x01
3028
3029#define	ANNEXCOL        		0x65
3030
3031#define	SCSCHKN         		0x66
3032#define		STSELSKIDDIS    	0x40
3033#define		CURRFIFODEF     	0x20
3034#define		WIDERESEN       	0x10
3035#define		SDONEMSKDIS     	0x08
3036#define		DFFACTCLR       	0x04
3037#define		SHVALIDSTDIS    	0x02
3038#define		LSTSGCLRDIS     	0x01
3039
3040#define	ANNEXDAT        		0x66
3041
3042#define	IOWNID          		0x67
3043
3044#define	PLL960CTL0      		0x68
3045
3046#define	SHCNT           		0x68
3047
3048#define	TOWNID          		0x69
3049
3050#define	PLL960CTL1      		0x69
3051
3052#define	PLL960CNT0      		0x6a
3053
3054#define	XSIG            		0x6a
3055
3056#define	SELOID          		0x6b
3057
3058#define	PLL400CTL0      		0x6c
3059#define		PLL_VCOSEL      	0x80
3060#define		PLL_PWDN        	0x40
3061#define		PLL_NS          	0x30
3062#define		PLL_ENLUD       	0x08
3063#define		PLL_ENLPF       	0x04
3064#define		PLL_DLPF        	0x02
3065#define		PLL_ENFBM       	0x01
3066
3067#define	FAIRNESS        		0x6c
3068
3069#define	PLL400CTL1      		0x6d
3070#define		PLL_CNTEN       	0x80
3071#define		PLL_CNTCLR      	0x40
3072#define		PLL_RST         	0x01
3073
3074#define	PLL400CNT0      		0x6e
3075
3076#define	UNFAIRNESS      		0x6e
3077
3078#define	HADDR           		0x70
3079
3080#define	PLLDELAY        		0x70
3081#define		SPLIT_DROP_REQ  	0x80
3082
3083#define	HODMAADR        		0x70
3084
3085#define	HODMACNT        		0x78
3086
3087#define	HCNT            		0x78
3088
3089#define	HODMAEN         		0x7a
3090
3091#define	SGHADDR         		0x7c
3092
3093#define	SCBHADDR        		0x7c
3094
3095#define	SGHCNT          		0x84
3096
3097#define	SCBHCNT         		0x84
3098
3099#define	DFF_THRSH       		0x88
3100#define		WR_DFTHRSH      	0x70
3101#define		RD_DFTHRSH      	0x07
3102#define		WR_DFTHRSH_MAX  	0x70
3103#define		WR_DFTHRSH_90   	0x60
3104#define		WR_DFTHRSH_85   	0x50
3105#define		WR_DFTHRSH_75   	0x40
3106#define		WR_DFTHRSH_63   	0x30
3107#define		WR_DFTHRSH_50   	0x20
3108#define		WR_DFTHRSH_25   	0x10
3109#define		RD_DFTHRSH_MAX  	0x07
3110#define		RD_DFTHRSH_90   	0x06
3111#define		RD_DFTHRSH_85   	0x05
3112#define		RD_DFTHRSH_75   	0x04
3113#define		RD_DFTHRSH_63   	0x03
3114#define		RD_DFTHRSH_50   	0x02
3115#define		RD_DFTHRSH_25   	0x01
3116#define		WR_DFTHRSH_MIN  	0x00
3117#define		RD_DFTHRSH_MIN  	0x00
3118
3119#define	ROMADDR         		0x8a
3120
3121#define	ROMCNTRL        		0x8d
3122#define		ROMOP           	0xe0
3123#define		ROMSPD          	0x18
3124#define		REPEAT          	0x02
3125#define		RDY             	0x01
3126
3127#define	ROMDATA         		0x8e
3128
3129#define	CMCRXMSG0       		0x90
3130
3131#define	ROENABLE        		0x90
3132#define		MSIROEN         	0x20
3133#define		OVLYROEN        	0x10
3134#define		CMCROEN         	0x08
3135#define		SGROEN          	0x04
3136#define		DCH1ROEN        	0x02
3137#define		DCH0ROEN        	0x01
3138
3139#define	OVLYRXMSG0      		0x90
3140
3141#define	DCHRXMSG0       		0x90
3142
3143#define	OVLYRXMSG1      		0x91
3144
3145#define	NSENABLE        		0x91
3146#define		MSINSEN         	0x20
3147#define		OVLYNSEN        	0x10
3148#define		CMCNSEN         	0x08
3149#define		SGNSEN          	0x04
3150#define		DCH1NSEN        	0x02
3151#define		DCH0NSEN        	0x01
3152
3153#define	DCHRXMSG1       		0x91
3154
3155#define	CMCRXMSG1       		0x91
3156
3157#define	DCHRXMSG2       		0x92
3158
3159#define	OVLYRXMSG2      		0x92
3160
3161#define	CMCRXMSG2       		0x92
3162
3163#define	OST             		0x92
3164
3165#define	DCHRXMSG3       		0x93
3166
3167#define	CMCRXMSG3       		0x93
3168
3169#define	PCIXCTL         		0x93
3170#define		SERRPULSE       	0x80
3171#define		UNEXPSCIEN      	0x20
3172#define		SPLTSMADIS      	0x10
3173#define		SPLTSTADIS      	0x08
3174#define		SRSPDPEEN       	0x04
3175#define		TSCSERREN       	0x02
3176#define		CMPABCDIS       	0x01
3177
3178#define	OVLYRXMSG3      		0x93
3179
3180#define	OVLYSEQBCNT     		0x94
3181
3182#define	CMCSEQBCNT      		0x94
3183
3184#define	DCHSEQBCNT      		0x94
3185
3186#define	CMCSPLTSTAT0    		0x96
3187
3188#define	OVLYSPLTSTAT0   		0x96
3189
3190#define	DCHSPLTSTAT0    		0x96
3191
3192#define	DCHSPLTSTAT1    		0x97
3193
3194#define	CMCSPLTSTAT1    		0x97
3195
3196#define	OVLYSPLTSTAT1   		0x97
3197
3198#define	SGRXMSG0        		0x98
3199#define		CDNUM           	0xf8
3200#define		CFNUM           	0x07
3201
3202#define	SLVSPLTOUTADR0  		0x98
3203#define		LOWER_ADDR      	0x7f
3204
3205#define	SGRXMSG1        		0x99
3206#define		CBNUM           	0xff
3207
3208#define	SLVSPLTOUTADR1  		0x99
3209#define		REQ_DNUM        	0xf8
3210#define		REQ_FNUM        	0x07
3211
3212#define	SGRXMSG2        		0x9a
3213#define		MINDEX          	0xff
3214
3215#define	SLVSPLTOUTADR2  		0x9a
3216#define		REQ_BNUM        	0xff
3217
3218#define	SGRXMSG3        		0x9b
3219#define		MCLASS          	0x0f
3220
3221#define	SLVSPLTOUTADR3  		0x9b
3222#define		TAG_NUM         	0x1f
3223#define		RLXORD          	0x10
3224
3225#define	SGSEQBCNT       		0x9c
3226
3227#define	SLVSPLTOUTATTR0 		0x9c
3228#define		LOWER_BCNT      	0xff
3229
3230#define	SLVSPLTOUTATTR1 		0x9d
3231#define		CMPLT_DNUM      	0xf8
3232#define		CMPLT_FNUM      	0x07
3233
3234#define	SLVSPLTOUTATTR2 		0x9e
3235#define		CMPLT_BNUM      	0xff
3236
3237#define	SGSPLTSTAT0     		0x9e
3238#define		STAETERM        	0x80
3239#define		SCBCERR         	0x40
3240#define		SCADERR         	0x20
3241#define		SCDATBUCKET     	0x10
3242#define		CNTNOTCMPLT     	0x08
3243#define		RXOVRUN         	0x04
3244#define		RXSCEMSG        	0x02
3245#define		RXSPLTRSP       	0x01
3246
3247#define	SFUNCT          		0x9f
3248#define		TEST_GROUP      	0xf0
3249#define		TEST_NUM        	0x0f
3250
3251#define	SGSPLTSTAT1     		0x9f
3252#define		RXDATABUCKET    	0x01
3253
3254#define	DF0PCISTAT      		0xa0
3255
3256#define	REG0            		0xa0
3257
3258#define	DF1PCISTAT      		0xa1
3259
3260#define	SGPCISTAT       		0xa2
3261
3262#define	REG1            		0xa2
3263
3264#define	CMCPCISTAT      		0xa3
3265
3266#define	OVLYPCISTAT     		0xa4
3267#define		SCAAPERR        	0x08
3268#define		RDPERR          	0x04
3269
3270#define	REG_ISR         		0xa4
3271
3272#define	SG_STATE        		0xa6
3273#define		FETCH_INPROG    	0x04
3274#define		LOADING_NEEDED  	0x02
3275#define		SEGS_AVAIL      	0x01
3276
3277#define	MSIPCISTAT      		0xa6
3278#define		RMA             	0x20
3279#define		RTA             	0x10
3280#define		CLRPENDMSI      	0x08
3281#define		DPR             	0x01
3282
3283#define	TARGPCISTAT     		0xa7
3284#define		DPE             	0x80
3285#define		SSE             	0x40
3286#define		STA             	0x08
3287#define		TWATERR         	0x02
3288
3289#define	DATA_COUNT_ODD  		0xa7
3290
3291#define	SCBPTR          		0xa8
3292
3293#define	CCSCBACNT       		0xab
3294
3295#define	SCBAUTOPTR      		0xab
3296#define		AUSCBPTR_EN     	0x80
3297#define		SCBPTR_ADDR     	0x38
3298#define		SCBPTR_OFF      	0x07
3299
3300#define	CCSGADDR        		0xac
3301
3302#define	CCSCBADDR       		0xac
3303
3304#define	CCSCBADR_BK     		0xac
3305
3306#define	CMC_RAMBIST     		0xad
3307#define		SG_ELEMENT_SIZE 	0x80
3308#define		SCBRAMBIST_FAIL 	0x40
3309#define		SG_BIST_FAIL    	0x20
3310#define		SG_BIST_EN      	0x10
3311#define		CMC_BUFFER_BIST_FAIL	0x02
3312#define		CMC_BUFFER_BIST_EN	0x01
3313
3314#define	CCSGCTL         		0xad
3315#define		CCSGEN          	0x0c
3316#define		CCSGDONE        	0x80
3317#define		SG_CACHE_AVAIL  	0x10
3318#define		CCSGENACK       	0x08
3319#define		SG_FETCH_REQ    	0x02
3320#define		CCSGRESET       	0x01
3321
3322#define	CCSCBCTL        		0xad
3323#define		CCSCBDONE       	0x80
3324#define		ARRDONE         	0x40
3325#define		CCARREN         	0x10
3326#define		CCSCBEN         	0x08
3327#define		CCSCBDIR        	0x04
3328#define		CCSCBRESET      	0x01
3329
3330#define	CCSGRAM         		0xb0
3331
3332#define	FLEXADR         		0xb0
3333
3334#define	CCSCBRAM        		0xb0
3335
3336#define	FLEXCNT         		0xb3
3337
3338#define	FLEXDMASTAT     		0xb5
3339#define		FLEXDMAERR      	0x02
3340#define		FLEXDMADONE     	0x01
3341
3342#define	FLEXDATA        		0xb6
3343
3344#define	BRDDAT          		0xb8
3345
3346#define	BRDCTL          		0xb9
3347#define		FLXARBACK       	0x80
3348#define		FLXARBREQ       	0x40
3349#define		BRDADDR         	0x38
3350#define		BRDEN           	0x04
3351#define		BRDRW           	0x02
3352#define		BRDSTB          	0x01
3353
3354#define	SEEADR          		0xba
3355
3356#define	SEEDAT          		0xbc
3357
3358#define	SEECTL          		0xbe
3359#define		SEEOP_EWEN      	0x40
3360#define		SEEOP_WALL      	0x40
3361#define		SEEOP_EWDS      	0x40
3362#define		SEEOPCODE       	0x70
3363#define		SEERST          	0x02
3364#define		SEESTART        	0x01
3365#define		SEEOP_ERASE     	0x70
3366#define		SEEOP_READ      	0x60
3367#define		SEEOP_WRITE     	0x50
3368#define		SEEOP_ERAL      	0x40
3369
3370#define	SEESTAT         		0xbe
3371#define		INIT_DONE       	0x80
3372#define		LDALTID_L       	0x08
3373#define		SEEARBACK       	0x04
3374#define		SEEBUSY         	0x02
3375
3376#define	SCBCNT          		0xbf
3377
3378#define	DFWADDR         		0xc0
3379
3380#define	DSPFLTRCTL      		0xc0
3381#define		FLTRDISABLE     	0x20
3382#define		EDGESENSE       	0x10
3383#define		DSPFCNTSEL      	0x0f
3384
3385#define	DSPDATACTL      		0xc1
3386#define		BYPASSENAB      	0x80
3387#define		DESQDIS         	0x10
3388#define		RCVROFFSTDIS    	0x04
3389#define		XMITOFFSTDIS    	0x02
3390
3391#define	DFRADDR         		0xc2
3392
3393#define	DSPREQCTL       		0xc2
3394#define		MANREQCTL       	0xc0
3395#define		MANREQDLY       	0x3f
3396
3397#define	DSPACKCTL       		0xc3
3398#define		MANACKCTL       	0xc0
3399#define		MANACKDLY       	0x3f
3400
3401#define	DFDAT           		0xc4
3402
3403#define	DSPSELECT       		0xc4
3404#define		AUTOINCEN       	0x80
3405#define		DSPSEL          	0x1f
3406
3407#define	WRTBIASCTL      		0xc5
3408#define		AUTOXBCDIS      	0x80
3409#define		XMITMANVAL      	0x3f
3410
3411#define	RCVRBIOSCTL     		0xc6
3412#define		AUTORBCDIS      	0x80
3413#define		RCVRMANVAL      	0x3f
3414
3415#define	WRTBIASCALC     		0xc7
3416
3417#define	DFPTRS          		0xc8
3418
3419#define	RCVRBIASCALC    		0xc8
3420
3421#define	DFBKPTR         		0xc9
3422
3423#define	SKEWCALC        		0xc9
3424
3425#define	DFDBCTL         		0xcb
3426#define		DFF_CIO_WR_RDY  	0x20
3427#define		DFF_CIO_RD_RDY  	0x10
3428#define		DFF_DIR_ERR     	0x08
3429#define		DFF_RAMBIST_FAIL	0x04
3430#define		DFF_RAMBIST_DONE	0x02
3431#define		DFF_RAMBIST_EN  	0x01
3432
3433#define	DFSCNT          		0xcc
3434
3435#define	DFBCNT          		0xce
3436
3437#define	OVLYADDR        		0xd4
3438
3439#define	SEQCTL0         		0xd6
3440#define		PERRORDIS       	0x80
3441#define		PAUSEDIS        	0x40
3442#define		FAILDIS         	0x20
3443#define		FASTMODE        	0x10
3444#define		BRKADRINTEN     	0x08
3445#define		STEP            	0x04
3446#define		SEQRESET        	0x02
3447#define		LOADRAM         	0x01
3448
3449#define	SEQCTL1         		0xd7
3450#define		OVRLAY_DATA_CHK 	0x08
3451#define		RAMBIST_DONE    	0x04
3452#define		RAMBIST_FAIL    	0x02
3453#define		RAMBIST_EN      	0x01
3454
3455#define	FLAGS           		0xd8
3456#define		ZERO            	0x02
3457#define		CARRY           	0x01
3458
3459#define	SEQINTCTL       		0xd9
3460#define		INTVEC1DSL      	0x80
3461#define		INT1_CONTEXT    	0x20
3462#define		SCS_SEQ_INT1M1  	0x10
3463#define		SCS_SEQ_INT1M0  	0x08
3464#define		INTMASK2        	0x04
3465#define		INTMASK1        	0x02
3466#define		IRET            	0x01
3467
3468#define	SEQRAM          		0xda
3469
3470#define	PRGMCNT         		0xde
3471
3472#define	ACCUM           		0xe0
3473
3474#define	SINDEX          		0xe2
3475
3476#define	DINDEX          		0xe4
3477
3478#define	BRKADDR1        		0xe6
3479#define		BRKDIS          	0x80
3480
3481#define	BRKADDR0        		0xe6
3482
3483#define	ALLONES         		0xe8
3484
3485#define	ALLZEROS        		0xea
3486
3487#define	NONE            		0xea
3488
3489#define	SINDIR          		0xec
3490
3491#define	DINDIR          		0xed
3492
3493#define	FUNCTION1       		0xf0
3494
3495#define	STACK           		0xf2
3496
3497#define	CURADDR         		0xf4
3498
3499#define	INTVEC1_ADDR    		0xf4
3500
3501#define	INTVEC2_ADDR    		0xf6
3502
3503#define	LASTADDR        		0xf6
3504
3505#define	LONGJMP_ADDR    		0xf8
3506
3507#define	ACCUM_SAVE      		0xfa
3508
3509#define	WAITING_SCB_TAILS		0x100
3510
3511#define	AHD_PCI_CONFIG_BASE		0x100
3512
3513#define	SRAM_BASE       		0x100
3514
3515#define	WAITING_TID_HEAD		0x120
3516
3517#define	WAITING_TID_TAIL		0x122
3518
3519#define	NEXT_QUEUED_SCB_ADDR		0x124
3520
3521#define	COMPLETE_SCB_HEAD		0x128
3522
3523#define	COMPLETE_SCB_DMAINPROG_HEAD		0x12a
3524
3525#define	COMPLETE_DMA_SCB_HEAD		0x12c
3526
3527#define	QFREEZE_COUNT   		0x12e
3528
3529#define	SAVED_MODE      		0x130
3530
3531#define	MSG_OUT         		0x131
3532
3533#define	DMAPARAMS       		0x132
3534#define		PRELOADEN       	0x80
3535#define		WIDEODD         	0x40
3536#define		SCSIEN          	0x20
3537#define		SDMAEN          	0x10
3538#define		SDMAENACK       	0x10
3539#define		HDMAENACK       	0x08
3540#define		HDMAEN          	0x08
3541#define		DIRECTION       	0x04
3542#define		FIFOFLUSH       	0x02
3543#define		FIFORESET       	0x01
3544
3545#define	SEQ_FLAGS       		0x133
3546#define		NOT_IDENTIFIED  	0x80
3547#define		NO_CDB_SENT     	0x40
3548#define		TARGET_CMD_IS_TAGGED	0x40
3549#define		DPHASE          	0x20
3550#define		TARG_CMD_PENDING	0x10
3551#define		CMDPHASE_PENDING	0x08
3552#define		DPHASE_PENDING  	0x04
3553#define		SPHASE_PENDING  	0x02
3554#define		NO_DISCONNECT   	0x01
3555
3556#define	SAVED_SCSIID    		0x134
3557
3558#define	SAVED_LUN       		0x135
3559
3560#define	LASTPHASE       		0x136
3561#define		PHASE_MASK      	0xe0
3562#define		CDI             	0x80
3563#define		IOI             	0x40
3564#define		MSGI            	0x20
3565#define		P_BUSFREE       	0x01
3566#define		P_MESGIN        	0xe0
3567#define		P_STATUS        	0xc0
3568#define		P_MESGOUT       	0xa0
3569#define		P_COMMAND       	0x80
3570#define		P_DATAIN_DT     	0x60
3571#define		P_DATAIN        	0x40
3572#define		P_DATAOUT_DT    	0x20
3573#define		P_DATAOUT       	0x00
3574
3575#define	QOUTFIFO_ENTRY_VALID_TAG		0x137
3576
3577#define	SHARED_DATA_ADDR		0x138
3578
3579#define	QOUTFIFO_NEXT_ADDR		0x13c
3580
3581#define	KERNEL_TQINPOS  		0x140
3582
3583#define	TQINPOS         		0x141
3584
3585#define	ARG_1           		0x142
3586#define	RETURN_1        		0x142
3587#define		SEND_MSG        	0x80
3588#define		SEND_SENSE      	0x40
3589#define		SEND_REJ        	0x20
3590#define		MSGOUT_PHASEMIS 	0x10
3591#define		EXIT_MSG_LOOP   	0x08
3592#define		CONT_MSG_LOOP_WRITE	0x04
3593#define		CONT_MSG_LOOP_READ	0x03
3594#define		CONT_MSG_LOOP_TARG	0x02
3595
3596#define	ARG_2           		0x143
3597#define	RETURN_2        		0x143
3598
3599#define	LAST_MSG        		0x144
3600
3601#define	SCSISEQ_TEMPLATE		0x145
3602#define		MANUALCTL       	0x40
3603#define		ENSELI          	0x20
3604#define		ENRSELI         	0x10
3605#define		MANUALP         	0x0c
3606#define		ENAUTOATNP      	0x02
3607#define		ALTSTIM         	0x01
3608
3609#define	INITIATOR_TAG   		0x146
3610
3611#define	SEQ_FLAGS2      		0x147
3612#define		SELECTOUT_QFROZEN	0x04
3613#define		TARGET_MSG_PENDING	0x02
3614
3615#define	ALLOCFIFO_SCBPTR		0x148
3616
3617#define	INT_COALESCING_TIMER		0x14a
3618
3619#define	INT_COALESCING_MAXCMDS		0x14c
3620
3621#define	INT_COALESCING_MINCMDS		0x14d
3622
3623#define	CMDS_PENDING    		0x14e
3624
3625#define	INT_COALESCING_CMDCOUNT		0x150
3626
3627#define	LOCAL_HS_MAILBOX		0x151
3628
3629#define	CMDSIZE_TABLE   		0x152
3630
3631#define	SCB_BASE        		0x180
3632
3633#define	SCB_RESIDUAL_DATACNT		0x180
3634#define	SCB_CDB_STORE   		0x180
3635#define	SCB_HOST_CDB_PTR		0x180
3636
3637#define	SCB_RESIDUAL_SGPTR		0x184
3638#define		SG_ADDR_MASK    	0xf8
3639#define		SG_OVERRUN_RESID	0x02
3640
3641#define	SCB_SCSI_STATUS 		0x188
3642#define	SCB_HOST_CDB_LEN		0x188
3643
3644#define	SCB_TARGET_PHASES		0x189
3645
3646#define	SCB_TARGET_DATA_DIR		0x18a
3647
3648#define	SCB_TARGET_ITAG 		0x18b
3649
3650#define	SCB_SENSE_BUSADDR		0x18c
3651#define	SCB_NEXT_COMPLETE		0x18c
3652
3653#define	SCB_TAG         		0x190
3654#define	SCB_FIFO_USE_COUNT		0x190
3655
3656#define	SCB_CONTROL     		0x192
3657#define		TARGET_SCB      	0x80
3658#define		DISCENB         	0x40
3659#define		TAG_ENB         	0x20
3660#define		MK_MESSAGE      	0x10
3661#define		STATUS_RCVD     	0x08
3662#define		DISCONNECTED    	0x04
3663#define		SCB_TAG_TYPE    	0x03
3664
3665#define	SCB_SCSIID      		0x193
3666#define		TID             	0xf0
3667#define		OID             	0x0f
3668
3669#define	SCB_LUN         		0x194
3670#define		LID             	0xff
3671
3672#define	SCB_TASK_ATTRIBUTE		0x195
3673#define		SCB_XFERLEN_ODD 	0x01
3674
3675#define	SCB_CDB_LEN     		0x196
3676#define		SCB_CDB_LEN_PTR 	0x80
3677
3678#define	SCB_TASK_MANAGEMENT		0x197
3679
3680#define	SCB_DATAPTR     		0x198
3681
3682#define	SCB_DATACNT     		0x1a0
3683#define		SG_LAST_SEG     	0x80
3684#define		SG_HIGH_ADDR_BITS	0x7f
3685
3686#define	SCB_SGPTR       		0x1a4
3687#define		SG_STATUS_VALID 	0x04
3688#define		SG_FULL_RESID   	0x02
3689#define		SG_LIST_NULL    	0x01
3690
3691#define	SCB_BUSADDR     		0x1a8
3692
3693#define	SCB_NEXT        		0x1ac
3694#define	SCB_NEXT_SCB_BUSADDR		0x1ac
3695
3696#define	SCB_NEXT2       		0x1ae
3697
3698#define	SCB_SPARE       		0x1b0
3699#define	SCB_PKT_LUN     		0x1b0
3700
3701#define	SCB_DISCONNECTED_LISTS		0x1b8
3702
3703
3704#define	AHD_TIMER_US_PER_TICK	0x19
3705#define	SCB_TRANSFER_SIZE_FULL_LUN	0x38
3706#define	STATUS_QUEUE_FULL	0x28
3707#define	STATUS_BUSY	0x08
3708#define	MAX_OFFSET_NON_PACED	0x7f
3709#define	MAX_OFFSET_PACED	0xfe
3710#define	BUS_32_BIT	0x02
3711#define	CCSGADDR_MAX	0x80
3712#define	TID_SHIFT	0x04
3713#define	MK_MESSAGE_BIT_OFFSET	0x04
3714#define	WRTBIASCTL_HP_DEFAULT	0x00
3715#define	SEEOP_EWDS_ADDR	0x00
3716#define	AHD_AMPLITUDE_SHIFT	0x00
3717#define	AHD_AMPLITUDE_MASK	0x07
3718#define	AHD_ANNEXCOL_AMPLITUDE	0x06
3719#define	AHD_SLEWRATE_DEF_REVA	0x08
3720#define	AHD_SLEWRATE_SHIFT	0x03
3721#define	AHD_SLEWRATE_MASK	0x78
3722#define	AHD_PRECOMP_CUTBACK_29	0x06
3723#define	AHD_NUM_PER_DEV_ANNEXCOLS	0x04
3724#define	B_CURRFIFO_0	0x02
3725#define	LUNLEN_SINGLE_LEVEL_LUN	0x0f
3726#define	NVRAM_SCB_OFFSET	0x2c
3727#define	AHD_TIMER_MAX_US	0x18ffe7
3728#define	AHD_TIMER_MAX_TICKS	0xffff
3729#define	STATUS_PKT_SENSE	0xff
3730#define	CMD_GROUP_CODE_SHIFT	0x05
3731#define	AHD_SENSE_BUFSIZE	0x100
3732#define	MAX_OFFSET_PACED_BUG	0x7f
3733#define	BUS_8_BIT	0x00
3734#define	STIMESEL_BUG_ADJ	0x08
3735#define	STIMESEL_MIN	0x18
3736#define	STIMESEL_SHIFT	0x03
3737#define	CCSGRAM_MAXSEGS	0x10
3738#define	INVALID_ADDR	0x80
3739#define	TARGET_CMD_CMPLT	0xfe
3740#define	SEEOP_WRAL_ADDR	0x40
3741#define	SEEOP_ERAL_ADDR	0x80
3742#define	AHD_AMPLITUDE_DEF	0x07
3743#define	AHD_SLEWRATE_DEF_REVB	0x08
3744#define	AHD_PRECOMP_CUTBACK_37	0x07
3745#define	AHD_PRECOMP_CUTBACK_17	0x04
3746#define	AHD_PRECOMP_SHIFT	0x00
3747#define	AHD_PRECOMP_MASK	0x07
3748#define	AHD_ANNEXCOL_PRECOMP_SLEW	0x04
3749#define	SRC_MODE_SHIFT	0x00
3750#define	PKT_OVERRUN_BUFSIZE	0x200
3751#define	SCB_TRANSFER_SIZE_1BYTE_LUN	0x30
3752#define	TARGET_DATA_IN	0x01
3753#define	HOST_MSG	0xff
3754#define	MAX_OFFSET	0xfe
3755#define	BUS_16_BIT	0x01
3756#define	CCSCBADDR_MAX	0x80
3757#define	NUMDSPS 	0x14
3758#define	SEEOP_EWEN_ADDR	0xc0
3759#define	AHD_ANNEXCOL_PER_DEV0	0x04
3760#define	DST_MODE_SHIFT	0x04
3761
3762
3763/* Downloaded Constant Definitions */
3764#define	SCB_TRANSFER_SIZE	0x06
3765#define	PKT_OVERRUN_BUFOFFSET	0x05
3766#define	SG_SIZEOF	0x04
3767#define	SG_PREFETCH_ADDR_MASK	0x03
3768#define	SG_PREFETCH_ALIGN_MASK	0x02
3769#define	SG_PREFETCH_CNT_LIMIT	0x01
3770#define	SG_PREFETCH_CNT	0x00
3771#define	DOWNLOAD_CONST_COUNT	0x07
3772
3773
3774/* Exported Labels */
3775#define	LABEL_seq_isr 	0x269
3776#define	LABEL_timer_isr	0x265
3777