1 /* 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#92 $ 42 */ 43 44 #ifdef __linux__ 45 #include "aic79xx_osm.h" 46 #include "aic79xx_inline.h" 47 #else 48 #include <dev/aic7xxx/aic79xx_osm.h> 49 #include <dev/aic7xxx/aic79xx_inline.h> 50 #endif 51 52 #include "aic79xx_pci.h" 53 54 static __inline uint64_t 55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 56 { 57 uint64_t id; 58 59 id = subvendor 60 | (subdevice << 16) 61 | ((uint64_t)vendor << 32) 62 | ((uint64_t)device << 48); 63 64 return (id); 65 } 66 67 #define ID_AIC7902_PCI_REV_A4 0x3 68 #define ID_AIC7902_PCI_REV_B0 0x10 69 #define SUBID_HP 0x0E11 70 71 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 72 73 #define DEVID_9005_TYPE(id) ((id) & 0xF) 74 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 75 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 76 #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */ 77 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 78 79 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 80 81 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 82 83 #define SUBID_9005_TYPE(id) ((id) & 0xF) 84 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 85 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 86 87 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 88 89 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 90 91 #define SUBID_9005_SEEPTYPE(id) (((id) & 0x0C0) >> 6) 92 #define SUBID_9005_SEEPTYPE_NONE 0x0 93 #define SUBID_9005_SEEPTYPE_4K 0x1 94 95 static ahd_device_setup_t ahd_aic7901_setup; 96 static ahd_device_setup_t ahd_aic7901A_setup; 97 static ahd_device_setup_t ahd_aic7902_setup; 98 static ahd_device_setup_t ahd_aic790X_setup; 99 100 static const struct ahd_pci_identity ahd_pci_ident_table[] = 101 { 102 /* aic7901 based controllers */ 103 { 104 ID_AHA_29320A, 105 ID_ALL_MASK, 106 "Adaptec 29320A Ultra320 SCSI adapter", 107 ahd_aic7901_setup 108 }, 109 { 110 ID_AHA_29320ALP, 111 ID_ALL_MASK, 112 "Adaptec 29320ALP PCIx Ultra320 SCSI adapter", 113 ahd_aic7901_setup 114 }, 115 { 116 ID_AHA_29320LPE, 117 ID_ALL_MASK, 118 "Adaptec 29320LPE PCIe Ultra320 SCSI adapter", 119 ahd_aic7901_setup 120 }, 121 /* aic7901A based controllers */ 122 { 123 ID_AHA_29320LP, 124 ID_ALL_MASK, 125 "Adaptec 29320LP Ultra320 SCSI adapter", 126 ahd_aic7901A_setup 127 }, 128 /* aic7902 based controllers */ 129 { 130 ID_AHA_29320, 131 ID_ALL_MASK, 132 "Adaptec 29320 Ultra320 SCSI adapter", 133 ahd_aic7902_setup 134 }, 135 { 136 ID_AHA_29320B, 137 ID_ALL_MASK, 138 "Adaptec 29320B Ultra320 SCSI adapter", 139 ahd_aic7902_setup 140 }, 141 { 142 ID_AHA_39320, 143 ID_ALL_MASK, 144 "Adaptec 39320 Ultra320 SCSI adapter", 145 ahd_aic7902_setup 146 }, 147 { 148 ID_AHA_39320_B, 149 ID_ALL_MASK, 150 "Adaptec 39320 Ultra320 SCSI adapter", 151 ahd_aic7902_setup 152 }, 153 { 154 ID_AHA_39320_B_DELL, 155 ID_ALL_MASK, 156 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_39320A, 161 ID_ALL_MASK, 162 "Adaptec 39320A Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320D, 167 ID_ALL_MASK, 168 "Adaptec 39320D Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_39320D_HP, 173 ID_ALL_MASK, 174 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_39320D_B, 179 ID_ALL_MASK, 180 "Adaptec 39320D Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 { 184 ID_AHA_39320D_B_HP, 185 ID_ALL_MASK, 186 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 187 ahd_aic7902_setup 188 }, 189 /* Generic chip probes for devices we don't know 'exactly' */ 190 { 191 ID_AIC7901 & ID_9005_GENERIC_MASK, 192 ID_9005_GENERIC_MASK, 193 "Adaptec AIC7901 Ultra320 SCSI adapter", 194 ahd_aic7901_setup 195 }, 196 { 197 ID_AIC7901A & ID_DEV_VENDOR_MASK, 198 ID_DEV_VENDOR_MASK, 199 "Adaptec AIC7901A Ultra320 SCSI adapter", 200 ahd_aic7901A_setup 201 }, 202 { 203 ID_AIC7902 & ID_9005_GENERIC_MASK, 204 ID_9005_GENERIC_MASK, 205 "Adaptec AIC7902 Ultra320 SCSI adapter", 206 ahd_aic7902_setup 207 } 208 }; 209 210 static const u_int ahd_num_pci_devs = ARRAY_SIZE(ahd_pci_ident_table); 211 212 #define DEVCONFIG 0x40 213 #define PCIXINITPAT 0x0000E000ul 214 #define PCIXINIT_PCI33_66 0x0000E000ul 215 #define PCIXINIT_PCIX50_66 0x0000C000ul 216 #define PCIXINIT_PCIX66_100 0x0000A000ul 217 #define PCIXINIT_PCIX100_133 0x00008000ul 218 #define PCI_BUS_MODES_INDEX(devconfig) \ 219 (((devconfig) & PCIXINITPAT) >> 13) 220 static const char *pci_bus_modes[] = 221 { 222 "PCI bus mode unknown", 223 "PCI bus mode unknown", 224 "PCI bus mode unknown", 225 "PCI bus mode unknown", 226 "PCI-X 101-133MHz", 227 "PCI-X 67-100MHz", 228 "PCI-X 50-66MHz", 229 "PCI 33 or 66MHz" 230 }; 231 232 #define TESTMODE 0x00000800ul 233 #define IRDY_RST 0x00000200ul 234 #define FRAME_RST 0x00000100ul 235 #define PCI64BIT 0x00000080ul 236 #define MRDCEN 0x00000040ul 237 #define ENDIANSEL 0x00000020ul 238 #define MIXQWENDIANEN 0x00000008ul 239 #define DACEN 0x00000004ul 240 #define STPWLEVEL 0x00000002ul 241 #define QWENDIANSEL 0x00000001ul 242 243 #define DEVCONFIG1 0x44 244 #define PREQDIS 0x01 245 246 #define CSIZE_LATTIME 0x0c 247 #define CACHESIZE 0x000000fful 248 #define LATTIME 0x0000ff00ul 249 250 static int ahd_check_extport(struct ahd_softc *ahd); 251 static void ahd_configure_termination(struct ahd_softc *ahd, 252 u_int adapter_control); 253 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 254 static void ahd_pci_intr(struct ahd_softc *ahd); 255 256 const struct ahd_pci_identity * 257 ahd_find_pci_device(ahd_dev_softc_t pci) 258 { 259 uint64_t full_id; 260 uint16_t device; 261 uint16_t vendor; 262 uint16_t subdevice; 263 uint16_t subvendor; 264 const struct ahd_pci_identity *entry; 265 u_int i; 266 267 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 268 device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 269 subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 270 subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 271 full_id = ahd_compose_id(device, 272 vendor, 273 subdevice, 274 subvendor); 275 276 /* 277 * Controllers, mask out the IROC/HostRAID bit 278 */ 279 280 full_id &= ID_ALL_IROC_MASK; 281 282 for (i = 0; i < ahd_num_pci_devs; i++) { 283 entry = &ahd_pci_ident_table[i]; 284 if (entry->full_id == (full_id & entry->id_mask)) { 285 /* Honor exclusion entries. */ 286 if (entry->name == NULL) 287 return (NULL); 288 return (entry); 289 } 290 } 291 return (NULL); 292 } 293 294 int 295 ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry) 296 { 297 struct scb_data *shared_scb_data; 298 u_int command; 299 uint32_t devconfig; 300 uint16_t subvendor; 301 int error; 302 303 shared_scb_data = NULL; 304 ahd->description = entry->name; 305 /* 306 * Record if this is an HP board. 307 */ 308 subvendor = ahd_pci_read_config(ahd->dev_softc, 309 PCIR_SUBVEND_0, /*bytes*/2); 310 if (subvendor == SUBID_HP) 311 ahd->flags |= AHD_HP_BOARD; 312 313 error = entry->setup(ahd); 314 if (error != 0) 315 return (error); 316 317 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 318 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 319 ahd->chip |= AHD_PCI; 320 /* Disable PCIX workarounds when running in PCI mode. */ 321 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 322 } else { 323 ahd->chip |= AHD_PCIX; 324 } 325 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 326 327 ahd_power_state_change(ahd, AHD_POWER_STATE_D0); 328 329 error = ahd_pci_map_registers(ahd); 330 if (error != 0) 331 return (error); 332 333 /* 334 * If we need to support high memory, enable dual 335 * address cycles. This bit must be set to enable 336 * high address bit generation even if we are on a 337 * 64bit bus (PCI64BIT set in devconfig). 338 */ 339 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 340 if (bootverbose) 341 printf("%s: Enabling 39Bit Addressing\n", 342 ahd_name(ahd)); 343 devconfig = ahd_pci_read_config(ahd->dev_softc, 344 DEVCONFIG, /*bytes*/4); 345 devconfig |= DACEN; 346 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, 347 devconfig, /*bytes*/4); 348 } 349 350 /* Ensure busmastering is enabled */ 351 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 352 command |= PCIM_CMD_BUSMASTEREN; 353 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 354 355 error = ahd_softc_init(ahd); 356 if (error != 0) 357 return (error); 358 359 ahd->bus_intr = ahd_pci_intr; 360 361 error = ahd_reset(ahd, /*reinit*/FALSE); 362 if (error != 0) 363 return (ENXIO); 364 365 ahd->pci_cachesize = 366 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 367 /*bytes*/1) & CACHESIZE; 368 ahd->pci_cachesize *= 4; 369 370 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 371 /* See if we have a SEEPROM and perform auto-term */ 372 error = ahd_check_extport(ahd); 373 if (error != 0) 374 return (error); 375 376 /* Core initialization */ 377 error = ahd_init(ahd); 378 if (error != 0) 379 return (error); 380 381 /* 382 * Allow interrupts now that we are completely setup. 383 */ 384 error = ahd_pci_map_int(ahd); 385 if (!error) 386 ahd->init_level++; 387 return error; 388 } 389 390 #ifdef CONFIG_PM 391 void 392 ahd_pci_suspend(struct ahd_softc *ahd) 393 { 394 /* 395 * Save chip register configuration data for chip resets 396 * that occur during runtime and resume events. 397 */ 398 ahd->suspend_state.pci_state.devconfig = 399 ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 400 ahd->suspend_state.pci_state.command = 401 ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1); 402 ahd->suspend_state.pci_state.csize_lattime = 403 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, /*bytes*/1); 404 405 } 406 407 void 408 ahd_pci_resume(struct ahd_softc *ahd) 409 { 410 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, 411 ahd->suspend_state.pci_state.devconfig, /*bytes*/4); 412 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 413 ahd->suspend_state.pci_state.command, /*bytes*/1); 414 ahd_pci_write_config(ahd->dev_softc, CSIZE_LATTIME, 415 ahd->suspend_state.pci_state.csize_lattime, /*bytes*/1); 416 } 417 #endif 418 419 /* 420 * Perform some simple tests that should catch situations where 421 * our registers are invalidly mapped. 422 */ 423 int 424 ahd_pci_test_register_access(struct ahd_softc *ahd) 425 { 426 uint32_t cmd; 427 u_int targpcistat; 428 u_int pci_status1; 429 int error; 430 uint8_t hcntrl; 431 432 error = EIO; 433 434 /* 435 * Enable PCI error interrupt status, but suppress NMIs 436 * generated by SERR raised due to target aborts. 437 */ 438 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 439 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 440 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 441 442 /* 443 * First a simple test to see if any 444 * registers can be read. Reading 445 * HCNTRL has no side effects and has 446 * at least one bit that is guaranteed to 447 * be zero so it is a good register to 448 * use for this test. 449 */ 450 hcntrl = ahd_inb(ahd, HCNTRL); 451 if (hcntrl == 0xFF) 452 goto fail; 453 454 /* 455 * Next create a situation where write combining 456 * or read prefetching could be initiated by the 457 * CPU or host bridge. Our device does not support 458 * either, so look for data corruption and/or flaged 459 * PCI errors. First pause without causing another 460 * chip reset. 461 */ 462 hcntrl &= ~CHIPRST; 463 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 464 while (ahd_is_paused(ahd) == 0) 465 ; 466 467 /* Clear any PCI errors that occurred before our driver attached. */ 468 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 469 targpcistat = ahd_inb(ahd, TARGPCISTAT); 470 ahd_outb(ahd, TARGPCISTAT, targpcistat); 471 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 472 PCIR_STATUS + 1, /*bytes*/1); 473 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 474 pci_status1, /*bytes*/1); 475 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 476 ahd_outb(ahd, CLRINT, CLRPCIINT); 477 478 ahd_outb(ahd, SEQCTL0, PERRORDIS); 479 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 480 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 481 goto fail; 482 483 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 484 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 485 targpcistat = ahd_inb(ahd, TARGPCISTAT); 486 if ((targpcistat & STA) != 0) 487 goto fail; 488 } 489 490 error = 0; 491 492 fail: 493 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 494 495 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 496 targpcistat = ahd_inb(ahd, TARGPCISTAT); 497 498 /* Silently clear any latched errors. */ 499 ahd_outb(ahd, TARGPCISTAT, targpcistat); 500 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 501 PCIR_STATUS + 1, /*bytes*/1); 502 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 503 pci_status1, /*bytes*/1); 504 ahd_outb(ahd, CLRINT, CLRPCIINT); 505 } 506 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 507 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 508 return (error); 509 } 510 511 /* 512 * Check the external port logic for a serial eeprom 513 * and termination/cable detection contrls. 514 */ 515 static int 516 ahd_check_extport(struct ahd_softc *ahd) 517 { 518 struct vpd_config vpd; 519 struct seeprom_config *sc; 520 u_int adapter_control; 521 int have_seeprom; 522 int error; 523 524 sc = ahd->seep_config; 525 have_seeprom = ahd_acquire_seeprom(ahd); 526 if (have_seeprom) { 527 u_int start_addr; 528 529 /* 530 * Fetch VPD for this function and parse it. 531 */ 532 if (bootverbose) 533 printf("%s: Reading VPD from SEEPROM...", 534 ahd_name(ahd)); 535 536 /* Address is always in units of 16bit words */ 537 start_addr = ((2 * sizeof(*sc)) 538 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 539 540 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 541 start_addr, sizeof(vpd)/2, 542 /*bytestream*/TRUE); 543 if (error == 0) 544 error = ahd_parse_vpddata(ahd, &vpd); 545 if (bootverbose) 546 printf("%s: VPD parsing %s\n", 547 ahd_name(ahd), 548 error == 0 ? "successful" : "failed"); 549 550 if (bootverbose) 551 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 552 553 /* Address is always in units of 16bit words */ 554 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 555 556 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 557 start_addr, sizeof(*sc)/2, 558 /*bytestream*/FALSE); 559 560 if (error != 0) { 561 printf("Unable to read SEEPROM\n"); 562 have_seeprom = 0; 563 } else { 564 have_seeprom = ahd_verify_cksum(sc); 565 566 if (bootverbose) { 567 if (have_seeprom == 0) 568 printf ("checksum error\n"); 569 else 570 printf ("done.\n"); 571 } 572 } 573 ahd_release_seeprom(ahd); 574 } 575 576 if (!have_seeprom) { 577 u_int nvram_scb; 578 579 /* 580 * Pull scratch ram settings and treat them as 581 * if they are the contents of an seeprom if 582 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 583 * in SCB 0xFF. We manually compose the data as 16bit 584 * values to avoid endian issues. 585 */ 586 ahd_set_scbptr(ahd, 0xFF); 587 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 588 if (nvram_scb != 0xFF 589 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 590 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 591 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 592 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 593 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 594 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 595 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 596 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 597 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 598 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 599 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 600 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 601 uint16_t *sc_data; 602 int i; 603 604 ahd_set_scbptr(ahd, nvram_scb); 605 sc_data = (uint16_t *)sc; 606 for (i = 0; i < 64; i += 2) 607 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 608 have_seeprom = ahd_verify_cksum(sc); 609 if (have_seeprom) 610 ahd->flags |= AHD_SCB_CONFIG_USED; 611 } 612 } 613 614 #ifdef AHD_DEBUG 615 if (have_seeprom != 0 616 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 617 uint16_t *sc_data; 618 int i; 619 620 printf("%s: Seeprom Contents:", ahd_name(ahd)); 621 sc_data = (uint16_t *)sc; 622 for (i = 0; i < (sizeof(*sc)); i += 2) 623 printf("\n\t0x%.4x", sc_data[i]); 624 printf("\n"); 625 } 626 #endif 627 628 if (!have_seeprom) { 629 if (bootverbose) 630 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 631 ahd->flags |= AHD_USEDEFAULTS; 632 error = ahd_default_config(ahd); 633 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 634 free(ahd->seep_config, M_DEVBUF); 635 ahd->seep_config = NULL; 636 } else { 637 error = ahd_parse_cfgdata(ahd, sc); 638 adapter_control = sc->adapter_control; 639 } 640 if (error != 0) 641 return (error); 642 643 ahd_configure_termination(ahd, adapter_control); 644 645 return (0); 646 } 647 648 static void 649 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 650 { 651 int error; 652 u_int sxfrctl1; 653 uint8_t termctl; 654 uint32_t devconfig; 655 656 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 657 devconfig &= ~STPWLEVEL; 658 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 659 devconfig |= STPWLEVEL; 660 if (bootverbose) 661 printf("%s: STPWLEVEL is %s\n", 662 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 663 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 664 665 /* Make sure current sensing is off. */ 666 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 667 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 668 } 669 670 /* 671 * Read to sense. Write to set. 672 */ 673 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 674 if ((adapter_control & CFAUTOTERM) == 0) { 675 if (bootverbose) 676 printf("%s: Manual Primary Termination\n", 677 ahd_name(ahd)); 678 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 679 if ((adapter_control & CFSTERM) != 0) 680 termctl |= FLX_TERMCTL_ENPRILOW; 681 if ((adapter_control & CFWSTERM) != 0) 682 termctl |= FLX_TERMCTL_ENPRIHIGH; 683 } else if (error != 0) { 684 printf("%s: Primary Auto-Term Sensing failed! " 685 "Using Defaults.\n", ahd_name(ahd)); 686 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 687 } 688 689 if ((adapter_control & CFSEAUTOTERM) == 0) { 690 if (bootverbose) 691 printf("%s: Manual Secondary Termination\n", 692 ahd_name(ahd)); 693 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 694 if ((adapter_control & CFSELOWTERM) != 0) 695 termctl |= FLX_TERMCTL_ENSECLOW; 696 if ((adapter_control & CFSEHIGHTERM) != 0) 697 termctl |= FLX_TERMCTL_ENSECHIGH; 698 } else if (error != 0) { 699 printf("%s: Secondary Auto-Term Sensing failed! " 700 "Using Defaults.\n", ahd_name(ahd)); 701 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 702 } 703 704 /* 705 * Now set the termination based on what we found. 706 */ 707 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 708 ahd->flags &= ~AHD_TERM_ENB_A; 709 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 710 ahd->flags |= AHD_TERM_ENB_A; 711 sxfrctl1 |= STPWEN; 712 } 713 /* Must set the latch once in order to be effective. */ 714 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 715 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 716 717 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 718 if (error != 0) { 719 printf("%s: Unable to set termination settings!\n", 720 ahd_name(ahd)); 721 } else if (bootverbose) { 722 printf("%s: Primary High byte termination %sabled\n", 723 ahd_name(ahd), 724 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 725 726 printf("%s: Primary Low byte termination %sabled\n", 727 ahd_name(ahd), 728 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 729 730 printf("%s: Secondary High byte termination %sabled\n", 731 ahd_name(ahd), 732 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 733 734 printf("%s: Secondary Low byte termination %sabled\n", 735 ahd_name(ahd), 736 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 737 } 738 return; 739 } 740 741 #define DPE 0x80 742 #define SSE 0x40 743 #define RMA 0x20 744 #define RTA 0x10 745 #define STA 0x08 746 #define DPR 0x01 747 748 static const char *split_status_source[] = 749 { 750 "DFF0", 751 "DFF1", 752 "OVLY", 753 "CMC", 754 }; 755 756 static const char *pci_status_source[] = 757 { 758 "DFF0", 759 "DFF1", 760 "SG", 761 "CMC", 762 "OVLY", 763 "NONE", 764 "MSI", 765 "TARG" 766 }; 767 768 static const char *split_status_strings[] = 769 { 770 "%s: Received split response in %s.\n", 771 "%s: Received split completion error message in %s\n", 772 "%s: Receive overrun in %s\n", 773 "%s: Count not complete in %s\n", 774 "%s: Split completion data bucket in %s\n", 775 "%s: Split completion address error in %s\n", 776 "%s: Split completion byte count error in %s\n", 777 "%s: Signaled Target-abort to early terminate a split in %s\n" 778 }; 779 780 static const char *pci_status_strings[] = 781 { 782 "%s: Data Parity Error has been reported via PERR# in %s\n", 783 "%s: Target initial wait state error in %s\n", 784 "%s: Split completion read data parity error in %s\n", 785 "%s: Split completion address attribute parity error in %s\n", 786 "%s: Received a Target Abort in %s\n", 787 "%s: Received a Master Abort in %s\n", 788 "%s: Signal System Error Detected in %s\n", 789 "%s: Address or Write Phase Parity Error Detected in %s.\n" 790 }; 791 792 static void 793 ahd_pci_intr(struct ahd_softc *ahd) 794 { 795 uint8_t pci_status[8]; 796 ahd_mode_state saved_modes; 797 u_int pci_status1; 798 u_int intstat; 799 u_int i; 800 u_int reg; 801 802 intstat = ahd_inb(ahd, INTSTAT); 803 804 if ((intstat & SPLTINT) != 0) 805 ahd_pci_split_intr(ahd, intstat); 806 807 if ((intstat & PCIINT) == 0) 808 return; 809 810 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 811 saved_modes = ahd_save_modes(ahd); 812 ahd_dump_card_state(ahd); 813 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 814 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 815 816 if (i == 5) 817 continue; 818 pci_status[i] = ahd_inb(ahd, reg); 819 /* Clear latched errors. So our interrupt deasserts. */ 820 ahd_outb(ahd, reg, pci_status[i]); 821 } 822 823 for (i = 0; i < 8; i++) { 824 u_int bit; 825 826 if (i == 5) 827 continue; 828 829 for (bit = 0; bit < 8; bit++) { 830 831 if ((pci_status[i] & (0x1 << bit)) != 0) { 832 static const char *s; 833 834 s = pci_status_strings[bit]; 835 if (i == 7/*TARG*/ && bit == 3) 836 s = "%s: Signaled Target Abort\n"; 837 printf(s, ahd_name(ahd), pci_status_source[i]); 838 } 839 } 840 } 841 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 842 PCIR_STATUS + 1, /*bytes*/1); 843 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 844 pci_status1, /*bytes*/1); 845 ahd_restore_modes(ahd, saved_modes); 846 ahd_outb(ahd, CLRINT, CLRPCIINT); 847 ahd_unpause(ahd); 848 } 849 850 static void 851 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 852 { 853 uint8_t split_status[4]; 854 uint8_t split_status1[4]; 855 uint8_t sg_split_status[2]; 856 uint8_t sg_split_status1[2]; 857 ahd_mode_state saved_modes; 858 u_int i; 859 uint16_t pcix_status; 860 861 /* 862 * Check for splits in all modes. Modes 0 and 1 863 * additionally have SG engine splits to look at. 864 */ 865 pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS, 866 /*bytes*/2); 867 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 868 ahd_name(ahd), pcix_status); 869 saved_modes = ahd_save_modes(ahd); 870 for (i = 0; i < 4; i++) { 871 ahd_set_modes(ahd, i, i); 872 873 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 874 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 875 /* Clear latched errors. So our interrupt deasserts. */ 876 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 877 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 878 if (i > 1) 879 continue; 880 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 881 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 882 /* Clear latched errors. So our interrupt deasserts. */ 883 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 884 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 885 } 886 887 for (i = 0; i < 4; i++) { 888 u_int bit; 889 890 for (bit = 0; bit < 8; bit++) { 891 892 if ((split_status[i] & (0x1 << bit)) != 0) { 893 static const char *s; 894 895 s = split_status_strings[bit]; 896 printf(s, ahd_name(ahd), 897 split_status_source[i]); 898 } 899 900 if (i > 1) 901 continue; 902 903 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 904 static const char *s; 905 906 s = split_status_strings[bit]; 907 printf(s, ahd_name(ahd), "SG"); 908 } 909 } 910 } 911 /* 912 * Clear PCI-X status bits. 913 */ 914 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS, 915 pcix_status, /*bytes*/2); 916 ahd_outb(ahd, CLRINT, CLRSPLTINT); 917 ahd_restore_modes(ahd, saved_modes); 918 } 919 920 static int 921 ahd_aic7901_setup(struct ahd_softc *ahd) 922 { 923 924 ahd->chip = AHD_AIC7901; 925 ahd->features = AHD_AIC7901_FE; 926 return (ahd_aic790X_setup(ahd)); 927 } 928 929 static int 930 ahd_aic7901A_setup(struct ahd_softc *ahd) 931 { 932 933 ahd->chip = AHD_AIC7901A; 934 ahd->features = AHD_AIC7901A_FE; 935 return (ahd_aic790X_setup(ahd)); 936 } 937 938 static int 939 ahd_aic7902_setup(struct ahd_softc *ahd) 940 { 941 ahd->chip = AHD_AIC7902; 942 ahd->features = AHD_AIC7902_FE; 943 return (ahd_aic790X_setup(ahd)); 944 } 945 946 static int 947 ahd_aic790X_setup(struct ahd_softc *ahd) 948 { 949 ahd_dev_softc_t pci; 950 u_int rev; 951 952 pci = ahd->dev_softc; 953 rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 954 if (rev < ID_AIC7902_PCI_REV_A4) { 955 printf("%s: Unable to attach to unsupported chip revision %d\n", 956 ahd_name(ahd), rev); 957 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 958 return (ENXIO); 959 } 960 ahd->channel = ahd_get_pci_function(pci) + 'A'; 961 if (rev < ID_AIC7902_PCI_REV_B0) { 962 /* 963 * Enable A series workarounds. 964 */ 965 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 966 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 967 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 968 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 969 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 970 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 971 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 972 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 973 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 974 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 975 | AHD_FAINT_LED_BUG; 976 977 /* 978 * IO Cell parameter setup. 979 */ 980 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 981 982 if ((ahd->flags & AHD_HP_BOARD) == 0) 983 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 984 } else { 985 /* This is revision B and newer. */ 986 extern uint32_t aic79xx_slowcrc; 987 u_int devconfig1; 988 989 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 990 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY 991 | AHD_BUSFREEREV_BUG; 992 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 993 994 /* If the user requested that the SLOWCRC bit to be set. */ 995 if (aic79xx_slowcrc) 996 ahd->features |= AHD_AIC79XXB_SLOWCRC; 997 998 /* 999 * Some issues have been resolved in the 7901B. 1000 */ 1001 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1002 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; 1003 1004 /* 1005 * IO Cell parameter setup. 1006 */ 1007 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1008 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1009 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1010 1011 /* 1012 * Set the PREQDIS bit for H2B which disables some workaround 1013 * that doesn't work on regular PCI busses. 1014 * XXX - Find out exactly what this does from the hardware 1015 * folks! 1016 */ 1017 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1018 ahd_pci_write_config(pci, DEVCONFIG1, 1019 devconfig1|PREQDIS, /*bytes*/1); 1020 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1021 } 1022 1023 return (0); 1024 } 1025