1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2003 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#250 $ 41 */ 42 43 #include "aic79xx_osm.h" 44 #include "aic79xx_inline.h" 45 #include "aicasm/aicasm_insformat.h" 46 47 /***************************** Lookup Tables **********************************/ 48 static const char *const ahd_chip_names[] = 49 { 50 "NONE", 51 "aic7901", 52 "aic7902", 53 "aic7901A" 54 }; 55 56 /* 57 * Hardware error codes. 58 */ 59 struct ahd_hard_error_entry { 60 uint8_t errno; 61 const char *errmesg; 62 }; 63 64 static const struct ahd_hard_error_entry ahd_hard_errors[] = { 65 { DSCTMOUT, "Discard Timer has timed out" }, 66 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 67 { SQPARERR, "Sequencer Parity Error" }, 68 { DPARERR, "Data-path Parity Error" }, 69 { MPARERR, "Scratch or SCB Memory Parity Error" }, 70 { CIOPARERR, "CIOBUS Parity Error" }, 71 }; 72 static const u_int num_errors = ARRAY_SIZE(ahd_hard_errors); 73 74 static const struct ahd_phase_table_entry ahd_phase_table[] = 75 { 76 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 77 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 78 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 79 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 80 { P_COMMAND, MSG_NOOP, "in Command phase" }, 81 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 82 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 83 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 84 { P_BUSFREE, MSG_NOOP, "while idle" }, 85 { 0, MSG_NOOP, "in unknown phase" } 86 }; 87 88 /* 89 * In most cases we only wish to itterate over real phases, so 90 * exclude the last element from the count. 91 */ 92 static const u_int num_phases = ARRAY_SIZE(ahd_phase_table) - 1; 93 94 /* Our Sequencer Program */ 95 #include "aic79xx_seq.h" 96 97 /**************************** Function Declarations ***************************/ 98 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 99 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 100 u_int lqistat1); 101 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 102 u_int busfreetime); 103 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 104 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 105 static void ahd_force_renegotiation(struct ahd_softc *ahd, 106 struct ahd_devinfo *devinfo); 107 108 static struct ahd_tmode_tstate* 109 ahd_alloc_tstate(struct ahd_softc *ahd, 110 u_int scsi_id, char channel); 111 #ifdef AHD_TARGET_MODE 112 static void ahd_free_tstate(struct ahd_softc *ahd, 113 u_int scsi_id, char channel, int force); 114 #endif 115 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 116 struct ahd_initiator_tinfo *, 117 u_int *period, 118 u_int *ppr_options, 119 role_t role); 120 static void ahd_update_neg_table(struct ahd_softc *ahd, 121 struct ahd_devinfo *devinfo, 122 struct ahd_transinfo *tinfo); 123 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 124 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 125 struct ahd_devinfo *devinfo); 126 static void ahd_scb_devinfo(struct ahd_softc *ahd, 127 struct ahd_devinfo *devinfo, 128 struct scb *scb); 129 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 130 struct ahd_devinfo *devinfo, 131 struct scb *scb); 132 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 133 struct ahd_devinfo *devinfo); 134 static void ahd_construct_sdtr(struct ahd_softc *ahd, 135 struct ahd_devinfo *devinfo, 136 u_int period, u_int offset); 137 static void ahd_construct_wdtr(struct ahd_softc *ahd, 138 struct ahd_devinfo *devinfo, 139 u_int bus_width); 140 static void ahd_construct_ppr(struct ahd_softc *ahd, 141 struct ahd_devinfo *devinfo, 142 u_int period, u_int offset, 143 u_int bus_width, u_int ppr_options); 144 static void ahd_clear_msg_state(struct ahd_softc *ahd); 145 static void ahd_handle_message_phase(struct ahd_softc *ahd); 146 typedef enum { 147 AHDMSG_1B, 148 AHDMSG_2B, 149 AHDMSG_EXT 150 } ahd_msgtype; 151 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 152 u_int msgval, int full); 153 static int ahd_parse_msg(struct ahd_softc *ahd, 154 struct ahd_devinfo *devinfo); 155 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 156 struct ahd_devinfo *devinfo); 157 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 158 struct ahd_devinfo *devinfo); 159 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 160 static void ahd_handle_devreset(struct ahd_softc *ahd, 161 struct ahd_devinfo *devinfo, 162 u_int lun, cam_status status, 163 char *message, int verbose_level); 164 #ifdef AHD_TARGET_MODE 165 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 166 struct ahd_devinfo *devinfo, 167 struct scb *scb); 168 #endif 169 170 static u_int ahd_sglist_size(struct ahd_softc *ahd); 171 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 172 static bus_dmamap_callback_t 173 ahd_dmamap_cb; 174 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 175 static int ahd_init_scbdata(struct ahd_softc *ahd); 176 static void ahd_fini_scbdata(struct ahd_softc *ahd); 177 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 178 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 179 static void ahd_add_col_list(struct ahd_softc *ahd, 180 struct scb *scb, u_int col_idx); 181 static void ahd_rem_col_list(struct ahd_softc *ahd, 182 struct scb *scb); 183 static void ahd_chip_init(struct ahd_softc *ahd); 184 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 185 struct scb *prev_scb, 186 struct scb *scb); 187 static int ahd_qinfifo_count(struct ahd_softc *ahd); 188 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 189 char channel, int lun, u_int tag, 190 role_t role, uint32_t status, 191 ahd_search_action action, 192 u_int *list_head, u_int *list_tail, 193 u_int tid); 194 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 195 u_int tid_prev, u_int tid_cur, 196 u_int tid_next); 197 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 198 u_int scbid); 199 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 200 u_int prev, u_int next, u_int tid); 201 static void ahd_reset_current_bus(struct ahd_softc *ahd); 202 static void ahd_stat_timer(struct timer_list *t); 203 #ifdef AHD_DUMP_SEQ 204 static void ahd_dumpseq(struct ahd_softc *ahd); 205 #endif 206 static void ahd_loadseq(struct ahd_softc *ahd); 207 static int ahd_check_patch(struct ahd_softc *ahd, 208 const struct patch **start_patch, 209 u_int start_instr, u_int *skip_addr); 210 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 211 u_int address); 212 static void ahd_download_instr(struct ahd_softc *ahd, 213 u_int instrptr, uint8_t *dconsts); 214 static int ahd_probe_stack_size(struct ahd_softc *ahd); 215 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd, 216 struct scb *scb); 217 static void ahd_run_data_fifo(struct ahd_softc *ahd, 218 struct scb *scb); 219 220 #ifdef AHD_TARGET_MODE 221 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 222 struct ahd_tmode_lstate *lstate, 223 u_int initiator_id, 224 u_int event_type, 225 u_int event_arg); 226 static void ahd_update_scsiid(struct ahd_softc *ahd, 227 u_int targid_mask); 228 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 229 struct target_cmd *cmd); 230 #endif 231 232 static int ahd_abort_scbs(struct ahd_softc *ahd, int target, 233 char channel, int lun, u_int tag, 234 role_t role, uint32_t status); 235 static void ahd_alloc_scbs(struct ahd_softc *ahd); 236 static void ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, 237 u_int scbid); 238 static void ahd_calc_residual(struct ahd_softc *ahd, 239 struct scb *scb); 240 static void ahd_clear_critical_section(struct ahd_softc *ahd); 241 static void ahd_clear_intstat(struct ahd_softc *ahd); 242 static void ahd_enable_coalescing(struct ahd_softc *ahd, 243 int enable); 244 static u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 245 static void ahd_freeze_devq(struct ahd_softc *ahd, 246 struct scb *scb); 247 static void ahd_handle_scb_status(struct ahd_softc *ahd, 248 struct scb *scb); 249 static const struct ahd_phase_table_entry* ahd_lookup_phase_entry(int phase); 250 static void ahd_shutdown(void *arg); 251 static void ahd_update_coalescing_values(struct ahd_softc *ahd, 252 u_int timer, 253 u_int maxcmds, 254 u_int mincmds); 255 static int ahd_verify_vpd_cksum(struct vpd_config *vpd); 256 static int ahd_wait_seeprom(struct ahd_softc *ahd); 257 static int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 258 int target, char channel, int lun, 259 u_int tag, role_t role); 260 261 static void ahd_reset_cmds_pending(struct ahd_softc *ahd); 262 263 /*************************** Interrupt Services *******************************/ 264 static void ahd_run_qoutfifo(struct ahd_softc *ahd); 265 #ifdef AHD_TARGET_MODE 266 static void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 267 #endif 268 static void ahd_handle_hwerrint(struct ahd_softc *ahd); 269 static void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 270 static void ahd_handle_scsiint(struct ahd_softc *ahd, 271 u_int intstat); 272 273 /************************ Sequencer Execution Control *************************/ 274 void 275 ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst) 276 { 277 if (ahd->src_mode == src && ahd->dst_mode == dst) 278 return; 279 #ifdef AHD_DEBUG 280 if (ahd->src_mode == AHD_MODE_UNKNOWN 281 || ahd->dst_mode == AHD_MODE_UNKNOWN) 282 panic("Setting mode prior to saving it.\n"); 283 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0) 284 printk("%s: Setting mode 0x%x\n", ahd_name(ahd), 285 ahd_build_mode_state(ahd, src, dst)); 286 #endif 287 ahd_outb(ahd, MODE_PTR, ahd_build_mode_state(ahd, src, dst)); 288 ahd->src_mode = src; 289 ahd->dst_mode = dst; 290 } 291 292 static void 293 ahd_update_modes(struct ahd_softc *ahd) 294 { 295 ahd_mode_state mode_ptr; 296 ahd_mode src; 297 ahd_mode dst; 298 299 mode_ptr = ahd_inb(ahd, MODE_PTR); 300 #ifdef AHD_DEBUG 301 if ((ahd_debug & AHD_SHOW_MODEPTR) != 0) 302 printk("Reading mode 0x%x\n", mode_ptr); 303 #endif 304 ahd_extract_mode_state(ahd, mode_ptr, &src, &dst); 305 ahd_known_modes(ahd, src, dst); 306 } 307 308 static void 309 ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode, 310 ahd_mode dstmode, const char *file, int line) 311 { 312 #ifdef AHD_DEBUG 313 if ((srcmode & AHD_MK_MSK(ahd->src_mode)) == 0 314 || (dstmode & AHD_MK_MSK(ahd->dst_mode)) == 0) { 315 panic("%s:%s:%d: Mode assertion failed.\n", 316 ahd_name(ahd), file, line); 317 } 318 #endif 319 } 320 321 #define AHD_ASSERT_MODES(ahd, source, dest) \ 322 ahd_assert_modes(ahd, source, dest, __FILE__, __LINE__); 323 324 ahd_mode_state 325 ahd_save_modes(struct ahd_softc *ahd) 326 { 327 if (ahd->src_mode == AHD_MODE_UNKNOWN 328 || ahd->dst_mode == AHD_MODE_UNKNOWN) 329 ahd_update_modes(ahd); 330 331 return (ahd_build_mode_state(ahd, ahd->src_mode, ahd->dst_mode)); 332 } 333 334 void 335 ahd_restore_modes(struct ahd_softc *ahd, ahd_mode_state state) 336 { 337 ahd_mode src; 338 ahd_mode dst; 339 340 ahd_extract_mode_state(ahd, state, &src, &dst); 341 ahd_set_modes(ahd, src, dst); 342 } 343 344 /* 345 * Determine whether the sequencer has halted code execution. 346 * Returns non-zero status if the sequencer is stopped. 347 */ 348 int 349 ahd_is_paused(struct ahd_softc *ahd) 350 { 351 return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0); 352 } 353 354 /* 355 * Request that the sequencer stop and wait, indefinitely, for it 356 * to stop. The sequencer will only acknowledge that it is paused 357 * once it has reached an instruction boundary and PAUSEDIS is 358 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS 359 * for critical sections. 360 */ 361 void 362 ahd_pause(struct ahd_softc *ahd) 363 { 364 ahd_outb(ahd, HCNTRL, ahd->pause); 365 366 /* 367 * Since the sequencer can disable pausing in a critical section, we 368 * must loop until it actually stops. 369 */ 370 while (ahd_is_paused(ahd) == 0) 371 ; 372 } 373 374 /* 375 * Allow the sequencer to continue program execution. 376 * We check here to ensure that no additional interrupt 377 * sources that would cause the sequencer to halt have been 378 * asserted. If, for example, a SCSI bus reset is detected 379 * while we are fielding a different, pausing, interrupt type, 380 * we don't want to release the sequencer before going back 381 * into our interrupt handler and dealing with this new 382 * condition. 383 */ 384 void 385 ahd_unpause(struct ahd_softc *ahd) 386 { 387 /* 388 * Automatically restore our modes to those saved 389 * prior to the first change of the mode. 390 */ 391 if (ahd->saved_src_mode != AHD_MODE_UNKNOWN 392 && ahd->saved_dst_mode != AHD_MODE_UNKNOWN) { 393 if ((ahd->flags & AHD_UPDATE_PEND_CMDS) != 0) 394 ahd_reset_cmds_pending(ahd); 395 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 396 } 397 398 if ((ahd_inb(ahd, INTSTAT) & ~CMDCMPLT) == 0) 399 ahd_outb(ahd, HCNTRL, ahd->unpause); 400 401 ahd_known_modes(ahd, AHD_MODE_UNKNOWN, AHD_MODE_UNKNOWN); 402 } 403 404 /*********************** Scatter Gather List Handling *************************/ 405 void * 406 ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb, 407 void *sgptr, dma_addr_t addr, bus_size_t len, int last) 408 { 409 scb->sg_count++; 410 if (sizeof(dma_addr_t) > 4 411 && (ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 412 struct ahd_dma64_seg *sg; 413 414 sg = (struct ahd_dma64_seg *)sgptr; 415 sg->addr = ahd_htole64(addr); 416 sg->len = ahd_htole32(len | (last ? AHD_DMA_LAST_SEG : 0)); 417 return (sg + 1); 418 } else { 419 struct ahd_dma_seg *sg; 420 421 sg = (struct ahd_dma_seg *)sgptr; 422 sg->addr = ahd_htole32(addr & 0xFFFFFFFF); 423 sg->len = ahd_htole32(len | ((addr >> 8) & 0x7F000000) 424 | (last ? AHD_DMA_LAST_SEG : 0)); 425 return (sg + 1); 426 } 427 } 428 429 static void 430 ahd_setup_scb_common(struct ahd_softc *ahd, struct scb *scb) 431 { 432 /* XXX Handle target mode SCBs. */ 433 scb->crc_retry_count = 0; 434 if ((scb->flags & SCB_PACKETIZED) != 0) { 435 /* XXX what about ACA?? It is type 4, but TAG_TYPE == 0x3. */ 436 scb->hscb->task_attribute = scb->hscb->control & SCB_TAG_TYPE; 437 } else { 438 if (ahd_get_transfer_length(scb) & 0x01) 439 scb->hscb->task_attribute = SCB_XFERLEN_ODD; 440 else 441 scb->hscb->task_attribute = 0; 442 } 443 444 if (scb->hscb->cdb_len <= MAX_CDB_LEN_WITH_SENSE_ADDR 445 || (scb->hscb->cdb_len & SCB_CDB_LEN_PTR) != 0) 446 scb->hscb->shared_data.idata.cdb_plus_saddr.sense_addr = 447 ahd_htole32(scb->sense_busaddr); 448 } 449 450 static void 451 ahd_setup_data_scb(struct ahd_softc *ahd, struct scb *scb) 452 { 453 /* 454 * Copy the first SG into the "current" data ponter area. 455 */ 456 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 457 struct ahd_dma64_seg *sg; 458 459 sg = (struct ahd_dma64_seg *)scb->sg_list; 460 scb->hscb->dataptr = sg->addr; 461 scb->hscb->datacnt = sg->len; 462 } else { 463 struct ahd_dma_seg *sg; 464 uint32_t *dataptr_words; 465 466 sg = (struct ahd_dma_seg *)scb->sg_list; 467 dataptr_words = (uint32_t*)&scb->hscb->dataptr; 468 dataptr_words[0] = sg->addr; 469 dataptr_words[1] = 0; 470 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) { 471 uint64_t high_addr; 472 473 high_addr = ahd_le32toh(sg->len) & 0x7F000000; 474 scb->hscb->dataptr |= ahd_htole64(high_addr << 8); 475 } 476 scb->hscb->datacnt = sg->len; 477 } 478 /* 479 * Note where to find the SG entries in bus space. 480 * We also set the full residual flag which the 481 * sequencer will clear as soon as a data transfer 482 * occurs. 483 */ 484 scb->hscb->sgptr = ahd_htole32(scb->sg_list_busaddr|SG_FULL_RESID); 485 } 486 487 static void 488 ahd_setup_noxfer_scb(struct ahd_softc *ahd, struct scb *scb) 489 { 490 scb->hscb->sgptr = ahd_htole32(SG_LIST_NULL); 491 scb->hscb->dataptr = 0; 492 scb->hscb->datacnt = 0; 493 } 494 495 /************************** Memory mapping routines ***************************/ 496 static void * 497 ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr) 498 { 499 dma_addr_t sg_offset; 500 501 /* sg_list_phys points to entry 1, not 0 */ 502 sg_offset = sg_busaddr - (scb->sg_list_busaddr - ahd_sg_size(ahd)); 503 return ((uint8_t *)scb->sg_list + sg_offset); 504 } 505 506 static uint32_t 507 ahd_sg_virt_to_bus(struct ahd_softc *ahd, struct scb *scb, void *sg) 508 { 509 dma_addr_t sg_offset; 510 511 /* sg_list_phys points to entry 1, not 0 */ 512 sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list) 513 - ahd_sg_size(ahd); 514 515 return (scb->sg_list_busaddr + sg_offset); 516 } 517 518 static void 519 ahd_sync_scb(struct ahd_softc *ahd, struct scb *scb, int op) 520 { 521 ahd_dmamap_sync(ahd, ahd->scb_data.hscb_dmat, 522 scb->hscb_map->dmamap, 523 /*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr, 524 /*len*/sizeof(*scb->hscb), op); 525 } 526 527 void 528 ahd_sync_sglist(struct ahd_softc *ahd, struct scb *scb, int op) 529 { 530 if (scb->sg_count == 0) 531 return; 532 533 ahd_dmamap_sync(ahd, ahd->scb_data.sg_dmat, 534 scb->sg_map->dmamap, 535 /*offset*/scb->sg_list_busaddr - ahd_sg_size(ahd), 536 /*len*/ahd_sg_size(ahd) * scb->sg_count, op); 537 } 538 539 static void 540 ahd_sync_sense(struct ahd_softc *ahd, struct scb *scb, int op) 541 { 542 ahd_dmamap_sync(ahd, ahd->scb_data.sense_dmat, 543 scb->sense_map->dmamap, 544 /*offset*/scb->sense_busaddr, 545 /*len*/AHD_SENSE_BUFSIZE, op); 546 } 547 548 #ifdef AHD_TARGET_MODE 549 static uint32_t 550 ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index) 551 { 552 return (((uint8_t *)&ahd->targetcmds[index]) 553 - (uint8_t *)ahd->qoutfifo); 554 } 555 #endif 556 557 /*********************** Miscellaneous Support Functions ***********************/ 558 /* 559 * Return pointers to the transfer negotiation information 560 * for the specified our_id/remote_id pair. 561 */ 562 struct ahd_initiator_tinfo * 563 ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id, 564 u_int remote_id, struct ahd_tmode_tstate **tstate) 565 { 566 /* 567 * Transfer data structures are stored from the perspective 568 * of the target role. Since the parameters for a connection 569 * in the initiator role to a given target are the same as 570 * when the roles are reversed, we pretend we are the target. 571 */ 572 if (channel == 'B') 573 our_id += 8; 574 *tstate = ahd->enabled_targets[our_id]; 575 return (&(*tstate)->transinfo[remote_id]); 576 } 577 578 uint16_t 579 ahd_inw(struct ahd_softc *ahd, u_int port) 580 { 581 /* 582 * Read high byte first as some registers increment 583 * or have other side effects when the low byte is 584 * read. 585 */ 586 uint16_t r = ahd_inb(ahd, port+1) << 8; 587 return r | ahd_inb(ahd, port); 588 } 589 590 void 591 ahd_outw(struct ahd_softc *ahd, u_int port, u_int value) 592 { 593 /* 594 * Write low byte first to accommodate registers 595 * such as PRGMCNT where the order maters. 596 */ 597 ahd_outb(ahd, port, value & 0xFF); 598 ahd_outb(ahd, port+1, (value >> 8) & 0xFF); 599 } 600 601 uint32_t 602 ahd_inl(struct ahd_softc *ahd, u_int port) 603 { 604 return ((ahd_inb(ahd, port)) 605 | (ahd_inb(ahd, port+1) << 8) 606 | (ahd_inb(ahd, port+2) << 16) 607 | (ahd_inb(ahd, port+3) << 24)); 608 } 609 610 void 611 ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value) 612 { 613 ahd_outb(ahd, port, (value) & 0xFF); 614 ahd_outb(ahd, port+1, ((value) >> 8) & 0xFF); 615 ahd_outb(ahd, port+2, ((value) >> 16) & 0xFF); 616 ahd_outb(ahd, port+3, ((value) >> 24) & 0xFF); 617 } 618 619 uint64_t 620 ahd_inq(struct ahd_softc *ahd, u_int port) 621 { 622 return ((ahd_inb(ahd, port)) 623 | (ahd_inb(ahd, port+1) << 8) 624 | (ahd_inb(ahd, port+2) << 16) 625 | (ahd_inb(ahd, port+3) << 24) 626 | (((uint64_t)ahd_inb(ahd, port+4)) << 32) 627 | (((uint64_t)ahd_inb(ahd, port+5)) << 40) 628 | (((uint64_t)ahd_inb(ahd, port+6)) << 48) 629 | (((uint64_t)ahd_inb(ahd, port+7)) << 56)); 630 } 631 632 void 633 ahd_outq(struct ahd_softc *ahd, u_int port, uint64_t value) 634 { 635 ahd_outb(ahd, port, value & 0xFF); 636 ahd_outb(ahd, port+1, (value >> 8) & 0xFF); 637 ahd_outb(ahd, port+2, (value >> 16) & 0xFF); 638 ahd_outb(ahd, port+3, (value >> 24) & 0xFF); 639 ahd_outb(ahd, port+4, (value >> 32) & 0xFF); 640 ahd_outb(ahd, port+5, (value >> 40) & 0xFF); 641 ahd_outb(ahd, port+6, (value >> 48) & 0xFF); 642 ahd_outb(ahd, port+7, (value >> 56) & 0xFF); 643 } 644 645 u_int 646 ahd_get_scbptr(struct ahd_softc *ahd) 647 { 648 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 649 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 650 return (ahd_inb(ahd, SCBPTR) | (ahd_inb(ahd, SCBPTR + 1) << 8)); 651 } 652 653 void 654 ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr) 655 { 656 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 657 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 658 ahd_outb(ahd, SCBPTR, scbptr & 0xFF); 659 ahd_outb(ahd, SCBPTR+1, (scbptr >> 8) & 0xFF); 660 } 661 662 #if 0 /* unused */ 663 static u_int 664 ahd_get_hnscb_qoff(struct ahd_softc *ahd) 665 { 666 return (ahd_inw_atomic(ahd, HNSCB_QOFF)); 667 } 668 #endif 669 670 static void 671 ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value) 672 { 673 ahd_outw_atomic(ahd, HNSCB_QOFF, value); 674 } 675 676 #if 0 /* unused */ 677 static u_int 678 ahd_get_hescb_qoff(struct ahd_softc *ahd) 679 { 680 return (ahd_inb(ahd, HESCB_QOFF)); 681 } 682 #endif 683 684 static void 685 ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value) 686 { 687 ahd_outb(ahd, HESCB_QOFF, value); 688 } 689 690 static u_int 691 ahd_get_snscb_qoff(struct ahd_softc *ahd) 692 { 693 u_int oldvalue; 694 695 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 696 oldvalue = ahd_inw(ahd, SNSCB_QOFF); 697 ahd_outw(ahd, SNSCB_QOFF, oldvalue); 698 return (oldvalue); 699 } 700 701 static void 702 ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value) 703 { 704 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 705 ahd_outw(ahd, SNSCB_QOFF, value); 706 } 707 708 #if 0 /* unused */ 709 static u_int 710 ahd_get_sescb_qoff(struct ahd_softc *ahd) 711 { 712 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 713 return (ahd_inb(ahd, SESCB_QOFF)); 714 } 715 #endif 716 717 static void 718 ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value) 719 { 720 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 721 ahd_outb(ahd, SESCB_QOFF, value); 722 } 723 724 #if 0 /* unused */ 725 static u_int 726 ahd_get_sdscb_qoff(struct ahd_softc *ahd) 727 { 728 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 729 return (ahd_inb(ahd, SDSCB_QOFF) | (ahd_inb(ahd, SDSCB_QOFF + 1) << 8)); 730 } 731 #endif 732 733 static void 734 ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value) 735 { 736 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 737 ahd_outb(ahd, SDSCB_QOFF, value & 0xFF); 738 ahd_outb(ahd, SDSCB_QOFF+1, (value >> 8) & 0xFF); 739 } 740 741 u_int 742 ahd_inb_scbram(struct ahd_softc *ahd, u_int offset) 743 { 744 u_int value; 745 746 /* 747 * Workaround PCI-X Rev A. hardware bug. 748 * After a host read of SCB memory, the chip 749 * may become confused into thinking prefetch 750 * was required. This starts the discard timer 751 * running and can cause an unexpected discard 752 * timer interrupt. The work around is to read 753 * a normal register prior to the exhaustion of 754 * the discard timer. The mode pointer register 755 * has no side effects and so serves well for 756 * this purpose. 757 * 758 * Razor #528 759 */ 760 value = ahd_inb(ahd, offset); 761 if ((ahd->bugs & AHD_PCIX_SCBRAM_RD_BUG) != 0) 762 ahd_inb(ahd, MODE_PTR); 763 return (value); 764 } 765 766 u_int 767 ahd_inw_scbram(struct ahd_softc *ahd, u_int offset) 768 { 769 return (ahd_inb_scbram(ahd, offset) 770 | (ahd_inb_scbram(ahd, offset+1) << 8)); 771 } 772 773 static uint32_t 774 ahd_inl_scbram(struct ahd_softc *ahd, u_int offset) 775 { 776 return (ahd_inw_scbram(ahd, offset) 777 | (ahd_inw_scbram(ahd, offset+2) << 16)); 778 } 779 780 static uint64_t 781 ahd_inq_scbram(struct ahd_softc *ahd, u_int offset) 782 { 783 return (ahd_inl_scbram(ahd, offset) 784 | ((uint64_t)ahd_inl_scbram(ahd, offset+4)) << 32); 785 } 786 787 struct scb * 788 ahd_lookup_scb(struct ahd_softc *ahd, u_int tag) 789 { 790 struct scb* scb; 791 792 if (tag >= AHD_SCB_MAX) 793 return (NULL); 794 scb = ahd->scb_data.scbindex[tag]; 795 if (scb != NULL) 796 ahd_sync_scb(ahd, scb, 797 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 798 return (scb); 799 } 800 801 static void 802 ahd_swap_with_next_hscb(struct ahd_softc *ahd, struct scb *scb) 803 { 804 struct hardware_scb *q_hscb; 805 struct map_node *q_hscb_map; 806 uint32_t saved_hscb_busaddr; 807 808 /* 809 * Our queuing method is a bit tricky. The card 810 * knows in advance which HSCB (by address) to download, 811 * and we can't disappoint it. To achieve this, the next 812 * HSCB to download is saved off in ahd->next_queued_hscb. 813 * When we are called to queue "an arbitrary scb", 814 * we copy the contents of the incoming HSCB to the one 815 * the sequencer knows about, swap HSCB pointers and 816 * finally assign the SCB to the tag indexed location 817 * in the scb_array. This makes sure that we can still 818 * locate the correct SCB by SCB_TAG. 819 */ 820 q_hscb = ahd->next_queued_hscb; 821 q_hscb_map = ahd->next_queued_hscb_map; 822 saved_hscb_busaddr = q_hscb->hscb_busaddr; 823 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb)); 824 q_hscb->hscb_busaddr = saved_hscb_busaddr; 825 q_hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 826 827 /* Now swap HSCB pointers. */ 828 ahd->next_queued_hscb = scb->hscb; 829 ahd->next_queued_hscb_map = scb->hscb_map; 830 scb->hscb = q_hscb; 831 scb->hscb_map = q_hscb_map; 832 833 /* Now define the mapping from tag to SCB in the scbindex */ 834 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = scb; 835 } 836 837 /* 838 * Tell the sequencer about a new transaction to execute. 839 */ 840 void 841 ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb) 842 { 843 ahd_swap_with_next_hscb(ahd, scb); 844 845 if (SCBID_IS_NULL(SCB_GET_TAG(scb))) 846 panic("Attempt to queue invalid SCB tag %x\n", 847 SCB_GET_TAG(scb)); 848 849 /* 850 * Keep a history of SCBs we've downloaded in the qinfifo. 851 */ 852 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 853 ahd->qinfifonext++; 854 855 if (scb->sg_count != 0) 856 ahd_setup_data_scb(ahd, scb); 857 else 858 ahd_setup_noxfer_scb(ahd, scb); 859 ahd_setup_scb_common(ahd, scb); 860 861 /* 862 * Make sure our data is consistent from the 863 * perspective of the adapter. 864 */ 865 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 866 867 #ifdef AHD_DEBUG 868 if ((ahd_debug & AHD_SHOW_QUEUE) != 0) { 869 uint64_t host_dataptr; 870 871 host_dataptr = ahd_le64toh(scb->hscb->dataptr); 872 printk("%s: Queueing SCB %d:0x%x bus addr 0x%x - 0x%x%x/0x%x\n", 873 ahd_name(ahd), 874 SCB_GET_TAG(scb), scb->hscb->scsiid, 875 ahd_le32toh(scb->hscb->hscb_busaddr), 876 (u_int)((host_dataptr >> 32) & 0xFFFFFFFF), 877 (u_int)(host_dataptr & 0xFFFFFFFF), 878 ahd_le32toh(scb->hscb->datacnt)); 879 } 880 #endif 881 /* Tell the adapter about the newly queued SCB */ 882 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 883 } 884 885 /************************** Interrupt Processing ******************************/ 886 static void 887 ahd_sync_qoutfifo(struct ahd_softc *ahd, int op) 888 { 889 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap, 890 /*offset*/0, 891 /*len*/AHD_SCB_MAX * sizeof(struct ahd_completion), op); 892 } 893 894 static void 895 ahd_sync_tqinfifo(struct ahd_softc *ahd, int op) 896 { 897 #ifdef AHD_TARGET_MODE 898 if ((ahd->flags & AHD_TARGETROLE) != 0) { 899 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, 900 ahd->shared_data_map.dmamap, 901 ahd_targetcmd_offset(ahd, 0), 902 sizeof(struct target_cmd) * AHD_TMODE_CMDS, 903 op); 904 } 905 #endif 906 } 907 908 /* 909 * See if the firmware has posted any completed commands 910 * into our in-core command complete fifos. 911 */ 912 #define AHD_RUN_QOUTFIFO 0x1 913 #define AHD_RUN_TQINFIFO 0x2 914 static u_int 915 ahd_check_cmdcmpltqueues(struct ahd_softc *ahd) 916 { 917 u_int retval; 918 919 retval = 0; 920 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap, 921 /*offset*/ahd->qoutfifonext * sizeof(*ahd->qoutfifo), 922 /*len*/sizeof(*ahd->qoutfifo), BUS_DMASYNC_POSTREAD); 923 if (ahd->qoutfifo[ahd->qoutfifonext].valid_tag 924 == ahd->qoutfifonext_valid_tag) 925 retval |= AHD_RUN_QOUTFIFO; 926 #ifdef AHD_TARGET_MODE 927 if ((ahd->flags & AHD_TARGETROLE) != 0 928 && (ahd->flags & AHD_TQINFIFO_BLOCKED) == 0) { 929 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, 930 ahd->shared_data_map.dmamap, 931 ahd_targetcmd_offset(ahd, ahd->tqinfifofnext), 932 /*len*/sizeof(struct target_cmd), 933 BUS_DMASYNC_POSTREAD); 934 if (ahd->targetcmds[ahd->tqinfifonext].cmd_valid != 0) 935 retval |= AHD_RUN_TQINFIFO; 936 } 937 #endif 938 return (retval); 939 } 940 941 /* 942 * Catch an interrupt from the adapter 943 */ 944 int 945 ahd_intr(struct ahd_softc *ahd) 946 { 947 u_int intstat; 948 949 if ((ahd->pause & INTEN) == 0) { 950 /* 951 * Our interrupt is not enabled on the chip 952 * and may be disabled for re-entrancy reasons, 953 * so just return. This is likely just a shared 954 * interrupt. 955 */ 956 return (0); 957 } 958 959 /* 960 * Instead of directly reading the interrupt status register, 961 * infer the cause of the interrupt by checking our in-core 962 * completion queues. This avoids a costly PCI bus read in 963 * most cases. 964 */ 965 if ((ahd->flags & AHD_ALL_INTERRUPTS) == 0 966 && (ahd_check_cmdcmpltqueues(ahd) != 0)) 967 intstat = CMDCMPLT; 968 else 969 intstat = ahd_inb(ahd, INTSTAT); 970 971 if ((intstat & INT_PEND) == 0) 972 return (0); 973 974 if (intstat & CMDCMPLT) { 975 ahd_outb(ahd, CLRINT, CLRCMDINT); 976 977 /* 978 * Ensure that the chip sees that we've cleared 979 * this interrupt before we walk the output fifo. 980 * Otherwise, we may, due to posted bus writes, 981 * clear the interrupt after we finish the scan, 982 * and after the sequencer has added new entries 983 * and asserted the interrupt again. 984 */ 985 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 986 if (ahd_is_paused(ahd)) { 987 /* 988 * Potentially lost SEQINT. 989 * If SEQINTCODE is non-zero, 990 * simulate the SEQINT. 991 */ 992 if (ahd_inb(ahd, SEQINTCODE) != NO_SEQINT) 993 intstat |= SEQINT; 994 } 995 } else { 996 ahd_flush_device_writes(ahd); 997 } 998 ahd_run_qoutfifo(ahd); 999 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]++; 1000 ahd->cmdcmplt_total++; 1001 #ifdef AHD_TARGET_MODE 1002 if ((ahd->flags & AHD_TARGETROLE) != 0) 1003 ahd_run_tqinfifo(ahd, /*paused*/FALSE); 1004 #endif 1005 } 1006 1007 /* 1008 * Handle statuses that may invalidate our cached 1009 * copy of INTSTAT separately. 1010 */ 1011 if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0) { 1012 /* Hot eject. Do nothing */ 1013 } else if (intstat & HWERRINT) { 1014 ahd_handle_hwerrint(ahd); 1015 } else if ((intstat & (PCIINT|SPLTINT)) != 0) { 1016 ahd->bus_intr(ahd); 1017 } else { 1018 1019 if ((intstat & SEQINT) != 0) 1020 ahd_handle_seqint(ahd, intstat); 1021 1022 if ((intstat & SCSIINT) != 0) 1023 ahd_handle_scsiint(ahd, intstat); 1024 } 1025 return (1); 1026 } 1027 1028 /******************************** Private Inlines *****************************/ 1029 static inline void 1030 ahd_assert_atn(struct ahd_softc *ahd) 1031 { 1032 ahd_outb(ahd, SCSISIGO, ATNO); 1033 } 1034 1035 /* 1036 * Determine if the current connection has a packetized 1037 * agreement. This does not necessarily mean that we 1038 * are currently in a packetized transfer. We could 1039 * just as easily be sending or receiving a message. 1040 */ 1041 static int 1042 ahd_currently_packetized(struct ahd_softc *ahd) 1043 { 1044 ahd_mode_state saved_modes; 1045 int packetized; 1046 1047 saved_modes = ahd_save_modes(ahd); 1048 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 1049 /* 1050 * The packetized bit refers to the last 1051 * connection, not the current one. Check 1052 * for non-zero LQISTATE instead. 1053 */ 1054 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1055 packetized = ahd_inb(ahd, LQISTATE) != 0; 1056 } else { 1057 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1058 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 1059 } 1060 ahd_restore_modes(ahd, saved_modes); 1061 return (packetized); 1062 } 1063 1064 static inline int 1065 ahd_set_active_fifo(struct ahd_softc *ahd) 1066 { 1067 u_int active_fifo; 1068 1069 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 1070 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 1071 switch (active_fifo) { 1072 case 0: 1073 case 1: 1074 ahd_set_modes(ahd, active_fifo, active_fifo); 1075 return (1); 1076 default: 1077 return (0); 1078 } 1079 } 1080 1081 static inline void 1082 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1083 { 1084 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1085 } 1086 1087 /* 1088 * Determine whether the sequencer reported a residual 1089 * for this SCB/transaction. 1090 */ 1091 static inline void 1092 ahd_update_residual(struct ahd_softc *ahd, struct scb *scb) 1093 { 1094 uint32_t sgptr; 1095 1096 sgptr = ahd_le32toh(scb->hscb->sgptr); 1097 if ((sgptr & SG_STATUS_VALID) != 0) 1098 ahd_calc_residual(ahd, scb); 1099 } 1100 1101 static inline void 1102 ahd_complete_scb(struct ahd_softc *ahd, struct scb *scb) 1103 { 1104 uint32_t sgptr; 1105 1106 sgptr = ahd_le32toh(scb->hscb->sgptr); 1107 if ((sgptr & SG_STATUS_VALID) != 0) 1108 ahd_handle_scb_status(ahd, scb); 1109 else 1110 ahd_done(ahd, scb); 1111 } 1112 1113 1114 /************************* Sequencer Execution Control ************************/ 1115 /* 1116 * Restart the sequencer program from address zero 1117 */ 1118 static void 1119 ahd_restart(struct ahd_softc *ahd) 1120 { 1121 1122 ahd_pause(ahd); 1123 1124 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1125 1126 /* No more pending messages */ 1127 ahd_clear_msg_state(ahd); 1128 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 1129 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 1130 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 1131 ahd_outb(ahd, SEQINTCTL, 0); 1132 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 1133 ahd_outb(ahd, SEQ_FLAGS, 0); 1134 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 1135 ahd_outb(ahd, SAVED_LUN, 0xFF); 1136 1137 /* 1138 * Ensure that the sequencer's idea of TQINPOS 1139 * matches our own. The sequencer increments TQINPOS 1140 * only after it sees a DMA complete and a reset could 1141 * occur before the increment leaving the kernel to believe 1142 * the command arrived but the sequencer to not. 1143 */ 1144 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 1145 1146 /* Always allow reselection */ 1147 ahd_outb(ahd, SCSISEQ1, 1148 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 1149 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 1150 1151 /* 1152 * Clear any pending sequencer interrupt. It is no 1153 * longer relevant since we're resetting the Program 1154 * Counter. 1155 */ 1156 ahd_outb(ahd, CLRINT, CLRSEQINT); 1157 1158 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 1159 ahd_unpause(ahd); 1160 } 1161 1162 static void 1163 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 1164 { 1165 ahd_mode_state saved_modes; 1166 1167 #ifdef AHD_DEBUG 1168 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 1169 printk("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 1170 #endif 1171 saved_modes = ahd_save_modes(ahd); 1172 ahd_set_modes(ahd, fifo, fifo); 1173 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 1174 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 1175 ahd_outb(ahd, CCSGCTL, CCSGRESET); 1176 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 1177 ahd_outb(ahd, SG_STATE, 0); 1178 ahd_restore_modes(ahd, saved_modes); 1179 } 1180 1181 /************************* Input/Output Queues ********************************/ 1182 /* 1183 * Flush and completed commands that are sitting in the command 1184 * complete queues down on the chip but have yet to be dma'ed back up. 1185 */ 1186 static void 1187 ahd_flush_qoutfifo(struct ahd_softc *ahd) 1188 { 1189 struct scb *scb; 1190 ahd_mode_state saved_modes; 1191 u_int saved_scbptr; 1192 u_int ccscbctl; 1193 u_int scbid; 1194 u_int next_scbid; 1195 1196 saved_modes = ahd_save_modes(ahd); 1197 1198 /* 1199 * Flush the good status FIFO for completed packetized commands. 1200 */ 1201 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1202 saved_scbptr = ahd_get_scbptr(ahd); 1203 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 1204 u_int fifo_mode; 1205 u_int i; 1206 1207 scbid = ahd_inw(ahd, GSFIFO); 1208 scb = ahd_lookup_scb(ahd, scbid); 1209 if (scb == NULL) { 1210 printk("%s: Warning - GSFIFO SCB %d invalid\n", 1211 ahd_name(ahd), scbid); 1212 continue; 1213 } 1214 /* 1215 * Determine if this transaction is still active in 1216 * any FIFO. If it is, we must flush that FIFO to 1217 * the host before completing the command. 1218 */ 1219 fifo_mode = 0; 1220 rescan_fifos: 1221 for (i = 0; i < 2; i++) { 1222 /* Toggle to the other mode. */ 1223 fifo_mode ^= 1; 1224 ahd_set_modes(ahd, fifo_mode, fifo_mode); 1225 1226 if (ahd_scb_active_in_fifo(ahd, scb) == 0) 1227 continue; 1228 1229 ahd_run_data_fifo(ahd, scb); 1230 1231 /* 1232 * Running this FIFO may cause a CFG4DATA for 1233 * this same transaction to assert in the other 1234 * FIFO or a new snapshot SAVEPTRS interrupt 1235 * in this FIFO. Even running a FIFO may not 1236 * clear the transaction if we are still waiting 1237 * for data to drain to the host. We must loop 1238 * until the transaction is not active in either 1239 * FIFO just to be sure. Reset our loop counter 1240 * so we will visit both FIFOs again before 1241 * declaring this transaction finished. We 1242 * also delay a bit so that status has a chance 1243 * to change before we look at this FIFO again. 1244 */ 1245 ahd_delay(200); 1246 goto rescan_fifos; 1247 } 1248 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1249 ahd_set_scbptr(ahd, scbid); 1250 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0 1251 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0 1252 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR) 1253 & SG_LIST_NULL) != 0)) { 1254 u_int comp_head; 1255 1256 /* 1257 * The transfer completed with a residual. 1258 * Place this SCB on the complete DMA list 1259 * so that we update our in-core copy of the 1260 * SCB before completing the command. 1261 */ 1262 ahd_outb(ahd, SCB_SCSI_STATUS, 0); 1263 ahd_outb(ahd, SCB_SGPTR, 1264 ahd_inb_scbram(ahd, SCB_SGPTR) 1265 | SG_STATUS_VALID); 1266 ahd_outw(ahd, SCB_TAG, scbid); 1267 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL); 1268 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 1269 if (SCBID_IS_NULL(comp_head)) { 1270 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid); 1271 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid); 1272 } else { 1273 u_int tail; 1274 1275 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL); 1276 ahd_set_scbptr(ahd, tail); 1277 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid); 1278 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid); 1279 ahd_set_scbptr(ahd, scbid); 1280 } 1281 } else 1282 ahd_complete_scb(ahd, scb); 1283 } 1284 ahd_set_scbptr(ahd, saved_scbptr); 1285 1286 /* 1287 * Setup for command channel portion of flush. 1288 */ 1289 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 1290 1291 /* 1292 * Wait for any inprogress DMA to complete and clear DMA state 1293 * if this is for an SCB in the qinfifo. 1294 */ 1295 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { 1296 1297 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 1298 if ((ccscbctl & ARRDONE) != 0) 1299 break; 1300 } else if ((ccscbctl & CCSCBDONE) != 0) 1301 break; 1302 ahd_delay(200); 1303 } 1304 /* 1305 * We leave the sequencer to cleanup in the case of DMA's to 1306 * update the qoutfifo. In all other cases (DMA's to the 1307 * chip or a push of an SCB from the COMPLETE_DMA_SCB list), 1308 * we disable the DMA engine so that the sequencer will not 1309 * attempt to handle the DMA completion. 1310 */ 1311 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0) 1312 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 1313 1314 /* 1315 * Complete any SCBs that just finished 1316 * being DMA'ed into the qoutfifo. 1317 */ 1318 ahd_run_qoutfifo(ahd); 1319 1320 saved_scbptr = ahd_get_scbptr(ahd); 1321 /* 1322 * Manually update/complete any completed SCBs that are waiting to be 1323 * DMA'ed back up to the host. 1324 */ 1325 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 1326 while (!SCBID_IS_NULL(scbid)) { 1327 uint8_t *hscb_ptr; 1328 u_int i; 1329 1330 ahd_set_scbptr(ahd, scbid); 1331 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 1332 scb = ahd_lookup_scb(ahd, scbid); 1333 if (scb == NULL) { 1334 printk("%s: Warning - DMA-up and complete " 1335 "SCB %d invalid\n", ahd_name(ahd), scbid); 1336 continue; 1337 } 1338 hscb_ptr = (uint8_t *)scb->hscb; 1339 for (i = 0; i < sizeof(struct hardware_scb); i++) 1340 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 1341 1342 ahd_complete_scb(ahd, scb); 1343 scbid = next_scbid; 1344 } 1345 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 1346 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL); 1347 1348 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD); 1349 while (!SCBID_IS_NULL(scbid)) { 1350 1351 ahd_set_scbptr(ahd, scbid); 1352 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 1353 scb = ahd_lookup_scb(ahd, scbid); 1354 if (scb == NULL) { 1355 printk("%s: Warning - Complete Qfrz SCB %d invalid\n", 1356 ahd_name(ahd), scbid); 1357 continue; 1358 } 1359 1360 ahd_complete_scb(ahd, scb); 1361 scbid = next_scbid; 1362 } 1363 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL); 1364 1365 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 1366 while (!SCBID_IS_NULL(scbid)) { 1367 1368 ahd_set_scbptr(ahd, scbid); 1369 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 1370 scb = ahd_lookup_scb(ahd, scbid); 1371 if (scb == NULL) { 1372 printk("%s: Warning - Complete SCB %d invalid\n", 1373 ahd_name(ahd), scbid); 1374 continue; 1375 } 1376 1377 ahd_complete_scb(ahd, scb); 1378 scbid = next_scbid; 1379 } 1380 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 1381 1382 /* 1383 * Restore state. 1384 */ 1385 ahd_set_scbptr(ahd, saved_scbptr); 1386 ahd_restore_modes(ahd, saved_modes); 1387 ahd->flags |= AHD_UPDATE_PEND_CMDS; 1388 } 1389 1390 /* 1391 * Determine if an SCB for a packetized transaction 1392 * is active in a FIFO. 1393 */ 1394 static int 1395 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb) 1396 { 1397 1398 /* 1399 * The FIFO is only active for our transaction if 1400 * the SCBPTR matches the SCB's ID and the firmware 1401 * has installed a handler for the FIFO or we have 1402 * a pending SAVEPTRS or CFG4DATA interrupt. 1403 */ 1404 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb) 1405 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0 1406 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0)) 1407 return (0); 1408 1409 return (1); 1410 } 1411 1412 /* 1413 * Run a data fifo to completion for a transaction we know 1414 * has completed across the SCSI bus (good status has been 1415 * received). We are already set to the correct FIFO mode 1416 * on entry to this routine. 1417 * 1418 * This function attempts to operate exactly as the firmware 1419 * would when running this FIFO. Care must be taken to update 1420 * this routine any time the firmware's FIFO algorithm is 1421 * changed. 1422 */ 1423 static void 1424 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb) 1425 { 1426 u_int seqintsrc; 1427 1428 seqintsrc = ahd_inb(ahd, SEQINTSRC); 1429 if ((seqintsrc & CFG4DATA) != 0) { 1430 uint32_t datacnt; 1431 uint32_t sgptr; 1432 1433 /* 1434 * Clear full residual flag. 1435 */ 1436 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID; 1437 ahd_outb(ahd, SCB_SGPTR, sgptr); 1438 1439 /* 1440 * Load datacnt and address. 1441 */ 1442 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT); 1443 if ((datacnt & AHD_DMA_LAST_SEG) != 0) { 1444 sgptr |= LAST_SEG; 1445 ahd_outb(ahd, SG_STATE, 0); 1446 } else 1447 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 1448 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR)); 1449 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK); 1450 ahd_outb(ahd, SG_CACHE_PRE, sgptr); 1451 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 1452 1453 /* 1454 * Initialize Residual Fields. 1455 */ 1456 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24); 1457 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK); 1458 1459 /* 1460 * Mark the SCB as having a FIFO in use. 1461 */ 1462 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 1463 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1); 1464 1465 /* 1466 * Install a "fake" handler for this FIFO. 1467 */ 1468 ahd_outw(ahd, LONGJMP_ADDR, 0); 1469 1470 /* 1471 * Notify the hardware that we have satisfied 1472 * this sequencer interrupt. 1473 */ 1474 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA); 1475 } else if ((seqintsrc & SAVEPTRS) != 0) { 1476 uint32_t sgptr; 1477 uint32_t resid; 1478 1479 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) { 1480 /* 1481 * Snapshot Save Pointers. All that 1482 * is necessary to clear the snapshot 1483 * is a CLRCHN. 1484 */ 1485 goto clrchn; 1486 } 1487 1488 /* 1489 * Disable S/G fetch so the DMA engine 1490 * is available to future users. 1491 */ 1492 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 1493 ahd_outb(ahd, CCSGCTL, 0); 1494 ahd_outb(ahd, SG_STATE, 0); 1495 1496 /* 1497 * Flush the data FIFO. Strickly only 1498 * necessary for Rev A parts. 1499 */ 1500 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH); 1501 1502 /* 1503 * Calculate residual. 1504 */ 1505 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 1506 resid = ahd_inl(ahd, SHCNT); 1507 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24; 1508 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid); 1509 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) { 1510 /* 1511 * Must back up to the correct S/G element. 1512 * Typically this just means resetting our 1513 * low byte to the offset in the SG_CACHE, 1514 * but if we wrapped, we have to correct 1515 * the other bytes of the sgptr too. 1516 */ 1517 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0 1518 && (sgptr & 0x80) == 0) 1519 sgptr -= 0x100; 1520 sgptr &= ~0xFF; 1521 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW) 1522 & SG_ADDR_MASK; 1523 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 1524 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0); 1525 } else if ((resid & AHD_SG_LEN_MASK) == 0) { 1526 ahd_outb(ahd, SCB_RESIDUAL_SGPTR, 1527 sgptr | SG_LIST_NULL); 1528 } 1529 /* 1530 * Save Pointers. 1531 */ 1532 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR)); 1533 ahd_outl(ahd, SCB_DATACNT, resid); 1534 ahd_outl(ahd, SCB_SGPTR, sgptr); 1535 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS); 1536 ahd_outb(ahd, SEQIMODE, 1537 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS); 1538 /* 1539 * If the data is to the SCSI bus, we are 1540 * done, otherwise wait for FIFOEMP. 1541 */ 1542 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0) 1543 goto clrchn; 1544 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) { 1545 uint32_t sgptr; 1546 uint64_t data_addr; 1547 uint32_t data_len; 1548 u_int dfcntrl; 1549 1550 /* 1551 * Disable S/G fetch so the DMA engine 1552 * is available to future users. We won't 1553 * be using the DMA engine to load segments. 1554 */ 1555 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) { 1556 ahd_outb(ahd, CCSGCTL, 0); 1557 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 1558 } 1559 1560 /* 1561 * Wait for the DMA engine to notice that the 1562 * host transfer is enabled and that there is 1563 * space in the S/G FIFO for new segments before 1564 * loading more segments. 1565 */ 1566 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0 1567 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) { 1568 1569 /* 1570 * Determine the offset of the next S/G 1571 * element to load. 1572 */ 1573 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 1574 sgptr &= SG_PTR_MASK; 1575 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 1576 struct ahd_dma64_seg *sg; 1577 1578 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 1579 data_addr = sg->addr; 1580 data_len = sg->len; 1581 sgptr += sizeof(*sg); 1582 } else { 1583 struct ahd_dma_seg *sg; 1584 1585 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 1586 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK; 1587 data_addr <<= 8; 1588 data_addr |= sg->addr; 1589 data_len = sg->len; 1590 sgptr += sizeof(*sg); 1591 } 1592 1593 /* 1594 * Update residual information. 1595 */ 1596 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24); 1597 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 1598 1599 /* 1600 * Load the S/G. 1601 */ 1602 if (data_len & AHD_DMA_LAST_SEG) { 1603 sgptr |= LAST_SEG; 1604 ahd_outb(ahd, SG_STATE, 0); 1605 } 1606 ahd_outq(ahd, HADDR, data_addr); 1607 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK); 1608 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF); 1609 1610 /* 1611 * Advertise the segment to the hardware. 1612 */ 1613 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN; 1614 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) { 1615 /* 1616 * Use SCSIENWRDIS so that SCSIEN 1617 * is never modified by this 1618 * operation. 1619 */ 1620 dfcntrl |= SCSIENWRDIS; 1621 } 1622 ahd_outb(ahd, DFCNTRL, dfcntrl); 1623 } 1624 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) { 1625 1626 /* 1627 * Transfer completed to the end of SG list 1628 * and has flushed to the host. 1629 */ 1630 ahd_outb(ahd, SCB_SGPTR, 1631 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL); 1632 goto clrchn; 1633 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) { 1634 clrchn: 1635 /* 1636 * Clear any handler for this FIFO, decrement 1637 * the FIFO use count for the SCB, and release 1638 * the FIFO. 1639 */ 1640 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 1641 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 1642 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1); 1643 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 1644 } 1645 } 1646 1647 /* 1648 * Look for entries in the QoutFIFO that have completed. 1649 * The valid_tag completion field indicates the validity 1650 * of the entry - the valid value toggles each time through 1651 * the queue. We use the sg_status field in the completion 1652 * entry to avoid referencing the hscb if the completion 1653 * occurred with no errors and no residual. sg_status is 1654 * a copy of the first byte (little endian) of the sgptr 1655 * hscb field. 1656 */ 1657 static void 1658 ahd_run_qoutfifo(struct ahd_softc *ahd) 1659 { 1660 struct ahd_completion *completion; 1661 struct scb *scb; 1662 u_int scb_index; 1663 1664 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 1665 panic("ahd_run_qoutfifo recursion"); 1666 ahd->flags |= AHD_RUNNING_QOUTFIFO; 1667 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 1668 for (;;) { 1669 completion = &ahd->qoutfifo[ahd->qoutfifonext]; 1670 1671 if (completion->valid_tag != ahd->qoutfifonext_valid_tag) 1672 break; 1673 1674 scb_index = ahd_le16toh(completion->tag); 1675 scb = ahd_lookup_scb(ahd, scb_index); 1676 if (scb == NULL) { 1677 printk("%s: WARNING no command for scb %d " 1678 "(cmdcmplt)\nQOUTPOS = %d\n", 1679 ahd_name(ahd), scb_index, 1680 ahd->qoutfifonext); 1681 ahd_dump_card_state(ahd); 1682 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) { 1683 ahd_handle_scb_status(ahd, scb); 1684 } else { 1685 ahd_done(ahd, scb); 1686 } 1687 1688 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 1689 if (ahd->qoutfifonext == 0) 1690 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID; 1691 } 1692 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 1693 } 1694 1695 /************************* Interrupt Handling *********************************/ 1696 static void 1697 ahd_handle_hwerrint(struct ahd_softc *ahd) 1698 { 1699 /* 1700 * Some catastrophic hardware error has occurred. 1701 * Print it for the user and disable the controller. 1702 */ 1703 int i; 1704 int error; 1705 1706 error = ahd_inb(ahd, ERROR); 1707 for (i = 0; i < num_errors; i++) { 1708 if ((error & ahd_hard_errors[i].errno) != 0) 1709 printk("%s: hwerrint, %s\n", 1710 ahd_name(ahd), ahd_hard_errors[i].errmesg); 1711 } 1712 1713 ahd_dump_card_state(ahd); 1714 panic("BRKADRINT"); 1715 1716 /* Tell everyone that this HBA is no longer available */ 1717 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 1718 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 1719 CAM_NO_HBA); 1720 1721 /* Tell the system that this controller has gone away. */ 1722 ahd_free(ahd); 1723 } 1724 1725 #ifdef AHD_DEBUG 1726 static void 1727 ahd_dump_sglist(struct scb *scb) 1728 { 1729 int i; 1730 1731 if (scb->sg_count > 0) { 1732 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 1733 struct ahd_dma64_seg *sg_list; 1734 1735 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 1736 for (i = 0; i < scb->sg_count; i++) { 1737 uint64_t addr; 1738 uint32_t len; 1739 1740 addr = ahd_le64toh(sg_list[i].addr); 1741 len = ahd_le32toh(sg_list[i].len); 1742 printk("sg[%d] - Addr 0x%x%x : Length %d%s\n", 1743 i, 1744 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 1745 (uint32_t)(addr & 0xFFFFFFFF), 1746 sg_list[i].len & AHD_SG_LEN_MASK, 1747 (sg_list[i].len & AHD_DMA_LAST_SEG) 1748 ? " Last" : ""); 1749 } 1750 } else { 1751 struct ahd_dma_seg *sg_list; 1752 1753 sg_list = (struct ahd_dma_seg*)scb->sg_list; 1754 for (i = 0; i < scb->sg_count; i++) { 1755 uint32_t len; 1756 1757 len = ahd_le32toh(sg_list[i].len); 1758 printk("sg[%d] - Addr 0x%x%x : Length %d%s\n", 1759 i, 1760 (len & AHD_SG_HIGH_ADDR_MASK) >> 24, 1761 ahd_le32toh(sg_list[i].addr), 1762 len & AHD_SG_LEN_MASK, 1763 len & AHD_DMA_LAST_SEG ? " Last" : ""); 1764 } 1765 } 1766 } 1767 } 1768 #endif /* AHD_DEBUG */ 1769 1770 static void 1771 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 1772 { 1773 u_int seqintcode; 1774 1775 /* 1776 * Save the sequencer interrupt code and clear the SEQINT 1777 * bit. We will unpause the sequencer, if appropriate, 1778 * after servicing the request. 1779 */ 1780 seqintcode = ahd_inb(ahd, SEQINTCODE); 1781 ahd_outb(ahd, CLRINT, CLRSEQINT); 1782 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 1783 /* 1784 * Unpause the sequencer and let it clear 1785 * SEQINT by writing NO_SEQINT to it. This 1786 * will cause the sequencer to be paused again, 1787 * which is the expected state of this routine. 1788 */ 1789 ahd_unpause(ahd); 1790 while (!ahd_is_paused(ahd)) 1791 ; 1792 ahd_outb(ahd, CLRINT, CLRSEQINT); 1793 } 1794 ahd_update_modes(ahd); 1795 #ifdef AHD_DEBUG 1796 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1797 printk("%s: Handle Seqint Called for code %d\n", 1798 ahd_name(ahd), seqintcode); 1799 #endif 1800 switch (seqintcode) { 1801 case ENTERING_NONPACK: 1802 { 1803 struct scb *scb; 1804 u_int scbid; 1805 1806 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 1807 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 1808 scbid = ahd_get_scbptr(ahd); 1809 scb = ahd_lookup_scb(ahd, scbid); 1810 if (scb == NULL) { 1811 /* 1812 * Somehow need to know if this 1813 * is from a selection or reselection. 1814 * From that, we can determine target 1815 * ID so we at least have an I_T nexus. 1816 */ 1817 } else { 1818 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 1819 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 1820 ahd_outb(ahd, SEQ_FLAGS, 0x0); 1821 } 1822 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 1823 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 1824 /* 1825 * Phase change after read stream with 1826 * CRC error with P0 asserted on last 1827 * packet. 1828 */ 1829 #ifdef AHD_DEBUG 1830 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 1831 printk("%s: Assuming LQIPHASE_NLQ with " 1832 "P0 assertion\n", ahd_name(ahd)); 1833 #endif 1834 } 1835 #ifdef AHD_DEBUG 1836 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 1837 printk("%s: Entering NONPACK\n", ahd_name(ahd)); 1838 #endif 1839 break; 1840 } 1841 case INVALID_SEQINT: 1842 printk("%s: Invalid Sequencer interrupt occurred, " 1843 "resetting channel.\n", 1844 ahd_name(ahd)); 1845 #ifdef AHD_DEBUG 1846 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 1847 ahd_dump_card_state(ahd); 1848 #endif 1849 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1850 break; 1851 case STATUS_OVERRUN: 1852 { 1853 struct scb *scb; 1854 u_int scbid; 1855 1856 scbid = ahd_get_scbptr(ahd); 1857 scb = ahd_lookup_scb(ahd, scbid); 1858 if (scb != NULL) 1859 ahd_print_path(ahd, scb); 1860 else 1861 printk("%s: ", ahd_name(ahd)); 1862 printk("SCB %d Packetized Status Overrun", scbid); 1863 ahd_dump_card_state(ahd); 1864 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1865 break; 1866 } 1867 case CFG4ISTAT_INTR: 1868 { 1869 struct scb *scb; 1870 u_int scbid; 1871 1872 scbid = ahd_get_scbptr(ahd); 1873 scb = ahd_lookup_scb(ahd, scbid); 1874 if (scb == NULL) { 1875 ahd_dump_card_state(ahd); 1876 printk("CFG4ISTAT: Free SCB %d referenced", scbid); 1877 panic("For safety"); 1878 } 1879 ahd_outq(ahd, HADDR, scb->sense_busaddr); 1880 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 1881 ahd_outb(ahd, HCNT + 2, 0); 1882 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 1883 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 1884 break; 1885 } 1886 case ILLEGAL_PHASE: 1887 { 1888 u_int bus_phase; 1889 1890 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1891 printk("%s: ILLEGAL_PHASE 0x%x\n", 1892 ahd_name(ahd), bus_phase); 1893 1894 switch (bus_phase) { 1895 case P_DATAOUT: 1896 case P_DATAIN: 1897 case P_DATAOUT_DT: 1898 case P_DATAIN_DT: 1899 case P_MESGOUT: 1900 case P_STATUS: 1901 case P_MESGIN: 1902 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1903 printk("%s: Issued Bus Reset.\n", ahd_name(ahd)); 1904 break; 1905 case P_COMMAND: 1906 { 1907 struct ahd_devinfo devinfo; 1908 struct scb *scb; 1909 struct ahd_initiator_tinfo *targ_info; 1910 struct ahd_tmode_tstate *tstate; 1911 struct ahd_transinfo *tinfo; 1912 u_int scbid; 1913 1914 /* 1915 * If a target takes us into the command phase 1916 * assume that it has been externally reset and 1917 * has thus lost our previous packetized negotiation 1918 * agreement. Since we have not sent an identify 1919 * message and may not have fully qualified the 1920 * connection, we change our command to TUR, assert 1921 * ATN and ABORT the task when we go to message in 1922 * phase. The OSM will see the REQUEUE_REQUEST 1923 * status and retry the command. 1924 */ 1925 scbid = ahd_get_scbptr(ahd); 1926 scb = ahd_lookup_scb(ahd, scbid); 1927 if (scb == NULL) { 1928 printk("Invalid phase with no valid SCB. " 1929 "Resetting bus.\n"); 1930 ahd_reset_channel(ahd, 'A', 1931 /*Initiate Reset*/TRUE); 1932 break; 1933 } 1934 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 1935 SCB_GET_TARGET(ahd, scb), 1936 SCB_GET_LUN(scb), 1937 SCB_GET_CHANNEL(ahd, scb), 1938 ROLE_INITIATOR); 1939 targ_info = ahd_fetch_transinfo(ahd, 1940 devinfo.channel, 1941 devinfo.our_scsiid, 1942 devinfo.target, 1943 &tstate); 1944 tinfo = &targ_info->curr; 1945 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 1946 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1947 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 1948 /*offset*/0, /*ppr_options*/0, 1949 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1950 /* Hand-craft TUR command */ 1951 ahd_outb(ahd, SCB_CDB_STORE, 0); 1952 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 1953 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 1954 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 1955 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 1956 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 1957 ahd_outb(ahd, SCB_CDB_LEN, 6); 1958 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 1959 scb->hscb->control |= MK_MESSAGE; 1960 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 1961 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1962 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 1963 /* 1964 * The lun is 0, regardless of the SCB's lun 1965 * as we have not sent an identify message. 1966 */ 1967 ahd_outb(ahd, SAVED_LUN, 0); 1968 ahd_outb(ahd, SEQ_FLAGS, 0); 1969 ahd_assert_atn(ahd); 1970 scb->flags &= ~SCB_PACKETIZED; 1971 scb->flags |= SCB_ABORT|SCB_EXTERNAL_RESET; 1972 ahd_freeze_devq(ahd, scb); 1973 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1974 ahd_freeze_scb(scb); 1975 1976 /* Notify XPT */ 1977 ahd_send_async(ahd, devinfo.channel, devinfo.target, 1978 CAM_LUN_WILDCARD, AC_SENT_BDR); 1979 1980 /* 1981 * Allow the sequencer to continue with 1982 * non-pack processing. 1983 */ 1984 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1985 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 1986 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1987 ahd_outb(ahd, CLRLQOINT1, 0); 1988 } 1989 #ifdef AHD_DEBUG 1990 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1991 ahd_print_path(ahd, scb); 1992 printk("Unexpected command phase from " 1993 "packetized target\n"); 1994 } 1995 #endif 1996 break; 1997 } 1998 } 1999 break; 2000 } 2001 case CFG4OVERRUN: 2002 { 2003 struct scb *scb; 2004 u_int scb_index; 2005 2006 #ifdef AHD_DEBUG 2007 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 2008 printk("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 2009 ahd_inb(ahd, MODE_PTR)); 2010 } 2011 #endif 2012 scb_index = ahd_get_scbptr(ahd); 2013 scb = ahd_lookup_scb(ahd, scb_index); 2014 if (scb == NULL) { 2015 /* 2016 * Attempt to transfer to an SCB that is 2017 * not outstanding. 2018 */ 2019 ahd_assert_atn(ahd); 2020 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2021 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2022 ahd->msgout_len = 1; 2023 ahd->msgout_index = 0; 2024 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2025 /* 2026 * Clear status received flag to prevent any 2027 * attempt to complete this bogus SCB. 2028 */ 2029 ahd_outb(ahd, SCB_CONTROL, 2030 ahd_inb_scbram(ahd, SCB_CONTROL) 2031 & ~STATUS_RCVD); 2032 } 2033 break; 2034 } 2035 case DUMP_CARD_STATE: 2036 { 2037 ahd_dump_card_state(ahd); 2038 break; 2039 } 2040 case PDATA_REINIT: 2041 { 2042 #ifdef AHD_DEBUG 2043 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 2044 printk("%s: PDATA_REINIT - DFCNTRL = 0x%x " 2045 "SG_CACHE_SHADOW = 0x%x\n", 2046 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 2047 ahd_inb(ahd, SG_CACHE_SHADOW)); 2048 } 2049 #endif 2050 ahd_reinitialize_dataptrs(ahd); 2051 break; 2052 } 2053 case HOST_MSG_LOOP: 2054 { 2055 struct ahd_devinfo devinfo; 2056 2057 /* 2058 * The sequencer has encountered a message phase 2059 * that requires host assistance for completion. 2060 * While handling the message phase(s), we will be 2061 * notified by the sequencer after each byte is 2062 * transferred so we can track bus phase changes. 2063 * 2064 * If this is the first time we've seen a HOST_MSG_LOOP 2065 * interrupt, initialize the state of the host message 2066 * loop. 2067 */ 2068 ahd_fetch_devinfo(ahd, &devinfo); 2069 if (ahd->msg_type == MSG_TYPE_NONE) { 2070 struct scb *scb; 2071 u_int scb_index; 2072 u_int bus_phase; 2073 2074 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2075 if (bus_phase != P_MESGIN 2076 && bus_phase != P_MESGOUT) { 2077 printk("ahd_intr: HOST_MSG_LOOP bad " 2078 "phase 0x%x\n", bus_phase); 2079 /* 2080 * Probably transitioned to bus free before 2081 * we got here. Just punt the message. 2082 */ 2083 ahd_dump_card_state(ahd); 2084 ahd_clear_intstat(ahd); 2085 ahd_restart(ahd); 2086 return; 2087 } 2088 2089 scb_index = ahd_get_scbptr(ahd); 2090 scb = ahd_lookup_scb(ahd, scb_index); 2091 if (devinfo.role == ROLE_INITIATOR) { 2092 if (bus_phase == P_MESGOUT) 2093 ahd_setup_initiator_msgout(ahd, 2094 &devinfo, 2095 scb); 2096 else { 2097 ahd->msg_type = 2098 MSG_TYPE_INITIATOR_MSGIN; 2099 ahd->msgin_index = 0; 2100 } 2101 } 2102 #ifdef AHD_TARGET_MODE 2103 else { 2104 if (bus_phase == P_MESGOUT) { 2105 ahd->msg_type = 2106 MSG_TYPE_TARGET_MSGOUT; 2107 ahd->msgin_index = 0; 2108 } 2109 else 2110 ahd_setup_target_msgin(ahd, 2111 &devinfo, 2112 scb); 2113 } 2114 #endif 2115 } 2116 2117 ahd_handle_message_phase(ahd); 2118 break; 2119 } 2120 case NO_MATCH: 2121 { 2122 /* Ensure we don't leave the selection hardware on */ 2123 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 2124 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2125 2126 printk("%s:%c:%d: no active SCB for reconnecting " 2127 "target - issuing BUS DEVICE RESET\n", 2128 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 2129 printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 2130 "REG0 == 0x%x ACCUM = 0x%x\n", 2131 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 2132 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 2133 printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 2134 "SINDEX == 0x%x\n", 2135 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 2136 ahd_find_busy_tcl(ahd, 2137 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 2138 ahd_inb(ahd, SAVED_LUN))), 2139 ahd_inw(ahd, SINDEX)); 2140 printk("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 2141 "SCB_CONTROL == 0x%x\n", 2142 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 2143 ahd_inb_scbram(ahd, SCB_LUN), 2144 ahd_inb_scbram(ahd, SCB_CONTROL)); 2145 printk("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 2146 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 2147 printk("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 2148 printk("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 2149 ahd_dump_card_state(ahd); 2150 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 2151 ahd->msgout_len = 1; 2152 ahd->msgout_index = 0; 2153 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2154 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2155 ahd_assert_atn(ahd); 2156 break; 2157 } 2158 case PROTO_VIOLATION: 2159 { 2160 ahd_handle_proto_violation(ahd); 2161 break; 2162 } 2163 case IGN_WIDE_RES: 2164 { 2165 struct ahd_devinfo devinfo; 2166 2167 ahd_fetch_devinfo(ahd, &devinfo); 2168 ahd_handle_ign_wide_residue(ahd, &devinfo); 2169 break; 2170 } 2171 case BAD_PHASE: 2172 { 2173 u_int lastphase; 2174 2175 lastphase = ahd_inb(ahd, LASTPHASE); 2176 printk("%s:%c:%d: unknown scsi bus phase %x, " 2177 "lastphase = 0x%x. Attempting to continue\n", 2178 ahd_name(ahd), 'A', 2179 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 2180 lastphase, ahd_inb(ahd, SCSISIGI)); 2181 break; 2182 } 2183 case MISSED_BUSFREE: 2184 { 2185 u_int lastphase; 2186 2187 lastphase = ahd_inb(ahd, LASTPHASE); 2188 printk("%s:%c:%d: Missed busfree. " 2189 "Lastphase = 0x%x, Curphase = 0x%x\n", 2190 ahd_name(ahd), 'A', 2191 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 2192 lastphase, ahd_inb(ahd, SCSISIGI)); 2193 ahd_restart(ahd); 2194 return; 2195 } 2196 case DATA_OVERRUN: 2197 { 2198 /* 2199 * When the sequencer detects an overrun, it 2200 * places the controller in "BITBUCKET" mode 2201 * and allows the target to complete its transfer. 2202 * Unfortunately, none of the counters get updated 2203 * when the controller is in this mode, so we have 2204 * no way of knowing how large the overrun was. 2205 */ 2206 struct scb *scb; 2207 u_int scbindex; 2208 #ifdef AHD_DEBUG 2209 u_int lastphase; 2210 #endif 2211 2212 scbindex = ahd_get_scbptr(ahd); 2213 scb = ahd_lookup_scb(ahd, scbindex); 2214 #ifdef AHD_DEBUG 2215 lastphase = ahd_inb(ahd, LASTPHASE); 2216 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 2217 ahd_print_path(ahd, scb); 2218 printk("data overrun detected %s. Tag == 0x%x.\n", 2219 ahd_lookup_phase_entry(lastphase)->phasemsg, 2220 SCB_GET_TAG(scb)); 2221 ahd_print_path(ahd, scb); 2222 printk("%s seen Data Phase. Length = %ld. " 2223 "NumSGs = %d.\n", 2224 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 2225 ? "Have" : "Haven't", 2226 ahd_get_transfer_length(scb), scb->sg_count); 2227 ahd_dump_sglist(scb); 2228 } 2229 #endif 2230 2231 /* 2232 * Set this and it will take effect when the 2233 * target does a command complete. 2234 */ 2235 ahd_freeze_devq(ahd, scb); 2236 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 2237 ahd_freeze_scb(scb); 2238 break; 2239 } 2240 case MKMSG_FAILED: 2241 { 2242 struct ahd_devinfo devinfo; 2243 struct scb *scb; 2244 u_int scbid; 2245 2246 ahd_fetch_devinfo(ahd, &devinfo); 2247 printk("%s:%c:%d:%d: Attempt to issue message failed\n", 2248 ahd_name(ahd), devinfo.channel, devinfo.target, 2249 devinfo.lun); 2250 scbid = ahd_get_scbptr(ahd); 2251 scb = ahd_lookup_scb(ahd, scbid); 2252 if (scb != NULL 2253 && (scb->flags & SCB_RECOVERY_SCB) != 0) 2254 /* 2255 * Ensure that we didn't put a second instance of this 2256 * SCB into the QINFIFO. 2257 */ 2258 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 2259 SCB_GET_CHANNEL(ahd, scb), 2260 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 2261 ROLE_INITIATOR, /*status*/0, 2262 SEARCH_REMOVE); 2263 ahd_outb(ahd, SCB_CONTROL, 2264 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 2265 break; 2266 } 2267 case TASKMGMT_FUNC_COMPLETE: 2268 { 2269 u_int scbid; 2270 struct scb *scb; 2271 2272 scbid = ahd_get_scbptr(ahd); 2273 scb = ahd_lookup_scb(ahd, scbid); 2274 if (scb != NULL) { 2275 u_int lun; 2276 u_int tag; 2277 cam_status error; 2278 2279 ahd_print_path(ahd, scb); 2280 printk("Task Management Func 0x%x Complete\n", 2281 scb->hscb->task_management); 2282 lun = CAM_LUN_WILDCARD; 2283 tag = SCB_LIST_NULL; 2284 2285 switch (scb->hscb->task_management) { 2286 case SIU_TASKMGMT_ABORT_TASK: 2287 tag = SCB_GET_TAG(scb); 2288 /* fall through */ 2289 case SIU_TASKMGMT_ABORT_TASK_SET: 2290 case SIU_TASKMGMT_CLEAR_TASK_SET: 2291 lun = scb->hscb->lun; 2292 error = CAM_REQ_ABORTED; 2293 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 2294 'A', lun, tag, ROLE_INITIATOR, 2295 error); 2296 break; 2297 case SIU_TASKMGMT_LUN_RESET: 2298 lun = scb->hscb->lun; 2299 /* fall through */ 2300 case SIU_TASKMGMT_TARGET_RESET: 2301 { 2302 struct ahd_devinfo devinfo; 2303 2304 ahd_scb_devinfo(ahd, &devinfo, scb); 2305 error = CAM_BDR_SENT; 2306 ahd_handle_devreset(ahd, &devinfo, lun, 2307 CAM_BDR_SENT, 2308 lun != CAM_LUN_WILDCARD 2309 ? "Lun Reset" 2310 : "Target Reset", 2311 /*verbose_level*/0); 2312 break; 2313 } 2314 default: 2315 panic("Unexpected TaskMgmt Func\n"); 2316 break; 2317 } 2318 } 2319 break; 2320 } 2321 case TASKMGMT_CMD_CMPLT_OKAY: 2322 { 2323 u_int scbid; 2324 struct scb *scb; 2325 2326 /* 2327 * An ABORT TASK TMF failed to be delivered before 2328 * the targeted command completed normally. 2329 */ 2330 scbid = ahd_get_scbptr(ahd); 2331 scb = ahd_lookup_scb(ahd, scbid); 2332 if (scb != NULL) { 2333 /* 2334 * Remove the second instance of this SCB from 2335 * the QINFIFO if it is still there. 2336 */ 2337 ahd_print_path(ahd, scb); 2338 printk("SCB completes before TMF\n"); 2339 /* 2340 * Handle losing the race. Wait until any 2341 * current selection completes. We will then 2342 * set the TMF back to zero in this SCB so that 2343 * the sequencer doesn't bother to issue another 2344 * sequencer interrupt for its completion. 2345 */ 2346 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 2347 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 2348 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 2349 ; 2350 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 2351 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 2352 SCB_GET_CHANNEL(ahd, scb), 2353 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 2354 ROLE_INITIATOR, /*status*/0, 2355 SEARCH_REMOVE); 2356 } 2357 break; 2358 } 2359 case TRACEPOINT0: 2360 case TRACEPOINT1: 2361 case TRACEPOINT2: 2362 case TRACEPOINT3: 2363 printk("%s: Tracepoint %d\n", ahd_name(ahd), 2364 seqintcode - TRACEPOINT0); 2365 break; 2366 case NO_SEQINT: 2367 break; 2368 case SAW_HWERR: 2369 ahd_handle_hwerrint(ahd); 2370 break; 2371 default: 2372 printk("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 2373 seqintcode); 2374 break; 2375 } 2376 /* 2377 * The sequencer is paused immediately on 2378 * a SEQINT, so we should restart it when 2379 * we're done. 2380 */ 2381 ahd_unpause(ahd); 2382 } 2383 2384 static void 2385 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 2386 { 2387 struct scb *scb; 2388 u_int status0; 2389 u_int status3; 2390 u_int status; 2391 u_int lqistat1; 2392 u_int lqostat0; 2393 u_int scbid; 2394 u_int busfreetime; 2395 2396 ahd_update_modes(ahd); 2397 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2398 2399 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 2400 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 2401 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 2402 lqistat1 = ahd_inb(ahd, LQISTAT1); 2403 lqostat0 = ahd_inb(ahd, LQOSTAT0); 2404 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 2405 2406 /* 2407 * Ignore external resets after a bus reset. 2408 */ 2409 if (((status & SCSIRSTI) != 0) && (ahd->flags & AHD_BUS_RESET_ACTIVE)) { 2410 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 2411 return; 2412 } 2413 2414 /* 2415 * Clear bus reset flag 2416 */ 2417 ahd->flags &= ~AHD_BUS_RESET_ACTIVE; 2418 2419 if ((status0 & (SELDI|SELDO)) != 0) { 2420 u_int simode0; 2421 2422 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2423 simode0 = ahd_inb(ahd, SIMODE0); 2424 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 2425 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2426 } 2427 scbid = ahd_get_scbptr(ahd); 2428 scb = ahd_lookup_scb(ahd, scbid); 2429 if (scb != NULL 2430 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 2431 scb = NULL; 2432 2433 if ((status0 & IOERR) != 0) { 2434 u_int now_lvd; 2435 2436 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 2437 printk("%s: Transceiver State Has Changed to %s mode\n", 2438 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 2439 ahd_outb(ahd, CLRSINT0, CLRIOERR); 2440 /* 2441 * A change in I/O mode is equivalent to a bus reset. 2442 */ 2443 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 2444 ahd_pause(ahd); 2445 ahd_setup_iocell_workaround(ahd); 2446 ahd_unpause(ahd); 2447 } else if ((status0 & OVERRUN) != 0) { 2448 2449 printk("%s: SCSI offset overrun detected. Resetting bus.\n", 2450 ahd_name(ahd)); 2451 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 2452 } else if ((status & SCSIRSTI) != 0) { 2453 2454 printk("%s: Someone reset channel A\n", ahd_name(ahd)); 2455 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 2456 } else if ((status & SCSIPERR) != 0) { 2457 2458 /* Make sure the sequencer is in a safe location. */ 2459 ahd_clear_critical_section(ahd); 2460 2461 ahd_handle_transmission_error(ahd); 2462 } else if (lqostat0 != 0) { 2463 2464 printk("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 2465 ahd_outb(ahd, CLRLQOINT0, lqostat0); 2466 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 2467 ahd_outb(ahd, CLRLQOINT1, 0); 2468 } else if ((status & SELTO) != 0) { 2469 /* Stop the selection */ 2470 ahd_outb(ahd, SCSISEQ0, 0); 2471 2472 /* Make sure the sequencer is in a safe location. */ 2473 ahd_clear_critical_section(ahd); 2474 2475 /* No more pending messages */ 2476 ahd_clear_msg_state(ahd); 2477 2478 /* Clear interrupt state */ 2479 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 2480 2481 /* 2482 * Although the driver does not care about the 2483 * 'Selection in Progress' status bit, the busy 2484 * LED does. SELINGO is only cleared by a successful 2485 * selection, so we must manually clear it to insure 2486 * the LED turns off just incase no future successful 2487 * selections occur (e.g. no devices on the bus). 2488 */ 2489 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 2490 2491 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 2492 scb = ahd_lookup_scb(ahd, scbid); 2493 if (scb == NULL) { 2494 printk("%s: ahd_intr - referenced scb not " 2495 "valid during SELTO scb(0x%x)\n", 2496 ahd_name(ahd), scbid); 2497 ahd_dump_card_state(ahd); 2498 } else { 2499 struct ahd_devinfo devinfo; 2500 #ifdef AHD_DEBUG 2501 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 2502 ahd_print_path(ahd, scb); 2503 printk("Saw Selection Timeout for SCB 0x%x\n", 2504 scbid); 2505 } 2506 #endif 2507 ahd_scb_devinfo(ahd, &devinfo, scb); 2508 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 2509 ahd_freeze_devq(ahd, scb); 2510 2511 /* 2512 * Cancel any pending transactions on the device 2513 * now that it seems to be missing. This will 2514 * also revert us to async/narrow transfers until 2515 * we can renegotiate with the device. 2516 */ 2517 ahd_handle_devreset(ahd, &devinfo, 2518 CAM_LUN_WILDCARD, 2519 CAM_SEL_TIMEOUT, 2520 "Selection Timeout", 2521 /*verbose_level*/1); 2522 } 2523 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2524 ahd_iocell_first_selection(ahd); 2525 ahd_unpause(ahd); 2526 } else if ((status0 & (SELDI|SELDO)) != 0) { 2527 2528 ahd_iocell_first_selection(ahd); 2529 ahd_unpause(ahd); 2530 } else if (status3 != 0) { 2531 printk("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 2532 ahd_name(ahd), status3); 2533 ahd_outb(ahd, CLRSINT3, status3); 2534 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 2535 2536 /* Make sure the sequencer is in a safe location. */ 2537 ahd_clear_critical_section(ahd); 2538 2539 ahd_handle_lqiphase_error(ahd, lqistat1); 2540 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 2541 /* 2542 * This status can be delayed during some 2543 * streaming operations. The SCSIPHASE 2544 * handler has already dealt with this case 2545 * so just clear the error. 2546 */ 2547 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 2548 } else if ((status & BUSFREE) != 0 2549 || (lqistat1 & LQOBUSFREE) != 0) { 2550 u_int lqostat1; 2551 int restart; 2552 int clear_fifo; 2553 int packetized; 2554 u_int mode; 2555 2556 /* 2557 * Clear our selection hardware as soon as possible. 2558 * We may have an entry in the waiting Q for this target, 2559 * that is affected by this busfree and we don't want to 2560 * go about selecting the target while we handle the event. 2561 */ 2562 ahd_outb(ahd, SCSISEQ0, 0); 2563 2564 /* Make sure the sequencer is in a safe location. */ 2565 ahd_clear_critical_section(ahd); 2566 2567 /* 2568 * Determine what we were up to at the time of 2569 * the busfree. 2570 */ 2571 mode = AHD_MODE_SCSI; 2572 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 2573 lqostat1 = ahd_inb(ahd, LQOSTAT1); 2574 switch (busfreetime) { 2575 case BUSFREE_DFF0: 2576 case BUSFREE_DFF1: 2577 { 2578 mode = busfreetime == BUSFREE_DFF0 2579 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 2580 ahd_set_modes(ahd, mode, mode); 2581 scbid = ahd_get_scbptr(ahd); 2582 scb = ahd_lookup_scb(ahd, scbid); 2583 if (scb == NULL) { 2584 printk("%s: Invalid SCB %d in DFF%d " 2585 "during unexpected busfree\n", 2586 ahd_name(ahd), scbid, mode); 2587 packetized = 0; 2588 } else 2589 packetized = (scb->flags & SCB_PACKETIZED) != 0; 2590 clear_fifo = 1; 2591 break; 2592 } 2593 case BUSFREE_LQO: 2594 clear_fifo = 0; 2595 packetized = 1; 2596 break; 2597 default: 2598 clear_fifo = 0; 2599 packetized = (lqostat1 & LQOBUSFREE) != 0; 2600 if (!packetized 2601 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE 2602 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0 2603 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0 2604 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0)) 2605 /* 2606 * Assume packetized if we are not 2607 * on the bus in a non-packetized 2608 * capacity and any pending selection 2609 * was a packetized selection. 2610 */ 2611 packetized = 1; 2612 break; 2613 } 2614 2615 #ifdef AHD_DEBUG 2616 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2617 printk("Saw Busfree. Busfreetime = 0x%x.\n", 2618 busfreetime); 2619 #endif 2620 /* 2621 * Busfrees that occur in non-packetized phases are 2622 * handled by the nonpkt_busfree handler. 2623 */ 2624 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 2625 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 2626 } else { 2627 packetized = 0; 2628 restart = ahd_handle_nonpkt_busfree(ahd); 2629 } 2630 /* 2631 * Clear the busfree interrupt status. The setting of 2632 * the interrupt is a pulse, so in a perfect world, we 2633 * would not need to muck with the ENBUSFREE logic. This 2634 * would ensure that if the bus moves on to another 2635 * connection, busfree protection is still in force. If 2636 * BUSFREEREV is broken, however, we must manually clear 2637 * the ENBUSFREE if the busfree occurred during a non-pack 2638 * connection so that we don't get false positives during 2639 * future, packetized, connections. 2640 */ 2641 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2642 if (packetized == 0 2643 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 2644 ahd_outb(ahd, SIMODE1, 2645 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 2646 2647 if (clear_fifo) 2648 ahd_clear_fifo(ahd, mode); 2649 2650 ahd_clear_msg_state(ahd); 2651 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2652 if (restart) { 2653 ahd_restart(ahd); 2654 } else { 2655 ahd_unpause(ahd); 2656 } 2657 } else { 2658 printk("%s: Missing case in ahd_handle_scsiint. status = %x\n", 2659 ahd_name(ahd), status); 2660 ahd_dump_card_state(ahd); 2661 ahd_clear_intstat(ahd); 2662 ahd_unpause(ahd); 2663 } 2664 } 2665 2666 static void 2667 ahd_handle_transmission_error(struct ahd_softc *ahd) 2668 { 2669 struct scb *scb; 2670 u_int scbid; 2671 u_int lqistat1; 2672 u_int lqistat2; 2673 u_int msg_out; 2674 u_int curphase; 2675 u_int lastphase; 2676 u_int perrdiag; 2677 u_int cur_col; 2678 int silent; 2679 2680 scb = NULL; 2681 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2682 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 2683 lqistat2 = ahd_inb(ahd, LQISTAT2); 2684 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 2685 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 2686 u_int lqistate; 2687 2688 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2689 lqistate = ahd_inb(ahd, LQISTATE); 2690 if ((lqistate >= 0x1E && lqistate <= 0x24) 2691 || (lqistate == 0x29)) { 2692 #ifdef AHD_DEBUG 2693 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 2694 printk("%s: NLQCRC found via LQISTATE\n", 2695 ahd_name(ahd)); 2696 } 2697 #endif 2698 lqistat1 |= LQICRCI_NLQ; 2699 } 2700 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2701 } 2702 2703 ahd_outb(ahd, CLRLQIINT1, lqistat1); 2704 lastphase = ahd_inb(ahd, LASTPHASE); 2705 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2706 perrdiag = ahd_inb(ahd, PERRDIAG); 2707 msg_out = MSG_INITIATOR_DET_ERR; 2708 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 2709 2710 /* 2711 * Try to find the SCB associated with this error. 2712 */ 2713 silent = FALSE; 2714 if (lqistat1 == 0 2715 || (lqistat1 & LQICRCI_NLQ) != 0) { 2716 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 2717 ahd_set_active_fifo(ahd); 2718 scbid = ahd_get_scbptr(ahd); 2719 scb = ahd_lookup_scb(ahd, scbid); 2720 if (scb != NULL && SCB_IS_SILENT(scb)) 2721 silent = TRUE; 2722 } 2723 2724 cur_col = 0; 2725 if (silent == FALSE) { 2726 printk("%s: Transmission error detected\n", ahd_name(ahd)); 2727 ahd_lqistat1_print(lqistat1, &cur_col, 50); 2728 ahd_lastphase_print(lastphase, &cur_col, 50); 2729 ahd_scsisigi_print(curphase, &cur_col, 50); 2730 ahd_perrdiag_print(perrdiag, &cur_col, 50); 2731 printk("\n"); 2732 ahd_dump_card_state(ahd); 2733 } 2734 2735 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 2736 if (silent == FALSE) { 2737 printk("%s: Gross protocol error during incoming " 2738 "packet. lqistat1 == 0x%x. Resetting bus.\n", 2739 ahd_name(ahd), lqistat1); 2740 } 2741 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 2742 return; 2743 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 2744 /* 2745 * A CRC error has been detected on an incoming LQ. 2746 * The bus is currently hung on the last ACK. 2747 * Hit LQIRETRY to release the last ack, and 2748 * wait for the sequencer to determine that ATNO 2749 * is asserted while in message out to take us 2750 * to our host message loop. No NONPACKREQ or 2751 * LQIPHASE type errors will occur in this 2752 * scenario. After this first LQIRETRY, the LQI 2753 * manager will be in ISELO where it will 2754 * happily sit until another packet phase begins. 2755 * Unexpected bus free detection is enabled 2756 * through any phases that occur after we release 2757 * this last ack until the LQI manager sees a 2758 * packet phase. This implies we may have to 2759 * ignore a perfectly valid "unexected busfree" 2760 * after our "initiator detected error" message is 2761 * sent. A busfree is the expected response after 2762 * we tell the target that it's L_Q was corrupted. 2763 * (SPI4R09 10.7.3.3.3) 2764 */ 2765 ahd_outb(ahd, LQCTL2, LQIRETRY); 2766 printk("LQIRetry for LQICRCI_LQ to release ACK\n"); 2767 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 2768 /* 2769 * We detected a CRC error in a NON-LQ packet. 2770 * The hardware has varying behavior in this situation 2771 * depending on whether this packet was part of a 2772 * stream or not. 2773 * 2774 * PKT by PKT mode: 2775 * The hardware has already acked the complete packet. 2776 * If the target honors our outstanding ATN condition, 2777 * we should be (or soon will be) in MSGOUT phase. 2778 * This will trigger the LQIPHASE_LQ status bit as the 2779 * hardware was expecting another LQ. Unexpected 2780 * busfree detection is enabled. Once LQIPHASE_LQ is 2781 * true (first entry into host message loop is much 2782 * the same), we must clear LQIPHASE_LQ and hit 2783 * LQIRETRY so the hardware is ready to handle 2784 * a future LQ. NONPACKREQ will not be asserted again 2785 * once we hit LQIRETRY until another packet is 2786 * processed. The target may either go busfree 2787 * or start another packet in response to our message. 2788 * 2789 * Read Streaming P0 asserted: 2790 * If we raise ATN and the target completes the entire 2791 * stream (P0 asserted during the last packet), the 2792 * hardware will ack all data and return to the ISTART 2793 * state. When the target reponds to our ATN condition, 2794 * LQIPHASE_LQ will be asserted. We should respond to 2795 * this with an LQIRETRY to prepare for any future 2796 * packets. NONPACKREQ will not be asserted again 2797 * once we hit LQIRETRY until another packet is 2798 * processed. The target may either go busfree or 2799 * start another packet in response to our message. 2800 * Busfree detection is enabled. 2801 * 2802 * Read Streaming P0 not asserted: 2803 * If we raise ATN and the target transitions to 2804 * MSGOUT in or after a packet where P0 is not 2805 * asserted, the hardware will assert LQIPHASE_NLQ. 2806 * We should respond to the LQIPHASE_NLQ with an 2807 * LQIRETRY. Should the target stay in a non-pkt 2808 * phase after we send our message, the hardware 2809 * will assert LQIPHASE_LQ. Recovery is then just as 2810 * listed above for the read streaming with P0 asserted. 2811 * Busfree detection is enabled. 2812 */ 2813 if (silent == FALSE) 2814 printk("LQICRC_NLQ\n"); 2815 if (scb == NULL) { 2816 printk("%s: No SCB valid for LQICRC_NLQ. " 2817 "Resetting bus\n", ahd_name(ahd)); 2818 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 2819 return; 2820 } 2821 } else if ((lqistat1 & LQIBADLQI) != 0) { 2822 printk("Need to handle BADLQI!\n"); 2823 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 2824 return; 2825 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 2826 if ((curphase & ~P_DATAIN_DT) != 0) { 2827 /* Ack the byte. So we can continue. */ 2828 if (silent == FALSE) 2829 printk("Acking %s to clear perror\n", 2830 ahd_lookup_phase_entry(curphase)->phasemsg); 2831 ahd_inb(ahd, SCSIDAT); 2832 } 2833 2834 if (curphase == P_MESGIN) 2835 msg_out = MSG_PARITY_ERROR; 2836 } 2837 2838 /* 2839 * We've set the hardware to assert ATN if we 2840 * get a parity error on "in" phases, so all we 2841 * need to do is stuff the message buffer with 2842 * the appropriate message. "In" phases have set 2843 * mesg_out to something other than MSG_NOP. 2844 */ 2845 ahd->send_msg_perror = msg_out; 2846 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 2847 scb->flags |= SCB_TRANSMISSION_ERROR; 2848 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2849 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2850 ahd_unpause(ahd); 2851 } 2852 2853 static void 2854 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 2855 { 2856 /* 2857 * Clear the sources of the interrupts. 2858 */ 2859 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2860 ahd_outb(ahd, CLRLQIINT1, lqistat1); 2861 2862 /* 2863 * If the "illegal" phase changes were in response 2864 * to our ATN to flag a CRC error, AND we ended up 2865 * on packet boundaries, clear the error, restart the 2866 * LQI manager as appropriate, and go on our merry 2867 * way toward sending the message. Otherwise, reset 2868 * the bus to clear the error. 2869 */ 2870 ahd_set_active_fifo(ahd); 2871 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 2872 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 2873 if ((lqistat1 & LQIPHASE_LQ) != 0) { 2874 printk("LQIRETRY for LQIPHASE_LQ\n"); 2875 ahd_outb(ahd, LQCTL2, LQIRETRY); 2876 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 2877 printk("LQIRETRY for LQIPHASE_NLQ\n"); 2878 ahd_outb(ahd, LQCTL2, LQIRETRY); 2879 } else 2880 panic("ahd_handle_lqiphase_error: No phase errors\n"); 2881 ahd_dump_card_state(ahd); 2882 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2883 ahd_unpause(ahd); 2884 } else { 2885 printk("Resetting Channel for LQI Phase error\n"); 2886 ahd_dump_card_state(ahd); 2887 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 2888 } 2889 } 2890 2891 /* 2892 * Packetized unexpected or expected busfree. 2893 * Entered in mode based on busfreetime. 2894 */ 2895 static int 2896 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 2897 { 2898 u_int lqostat1; 2899 2900 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2901 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2902 lqostat1 = ahd_inb(ahd, LQOSTAT1); 2903 if ((lqostat1 & LQOBUSFREE) != 0) { 2904 struct scb *scb; 2905 u_int scbid; 2906 u_int saved_scbptr; 2907 u_int waiting_h; 2908 u_int waiting_t; 2909 u_int next; 2910 2911 /* 2912 * The LQO manager detected an unexpected busfree 2913 * either: 2914 * 2915 * 1) During an outgoing LQ. 2916 * 2) After an outgoing LQ but before the first 2917 * REQ of the command packet. 2918 * 3) During an outgoing command packet. 2919 * 2920 * In all cases, CURRSCB is pointing to the 2921 * SCB that encountered the failure. Clean 2922 * up the queue, clear SELDO and LQOBUSFREE, 2923 * and allow the sequencer to restart the select 2924 * out at its lesure. 2925 */ 2926 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2927 scbid = ahd_inw(ahd, CURRSCB); 2928 scb = ahd_lookup_scb(ahd, scbid); 2929 if (scb == NULL) 2930 panic("SCB not valid during LQOBUSFREE"); 2931 /* 2932 * Clear the status. 2933 */ 2934 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 2935 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 2936 ahd_outb(ahd, CLRLQOINT1, 0); 2937 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2938 ahd_flush_device_writes(ahd); 2939 ahd_outb(ahd, CLRSINT0, CLRSELDO); 2940 2941 /* 2942 * Return the LQO manager to its idle loop. It will 2943 * not do this automatically if the busfree occurs 2944 * after the first REQ of either the LQ or command 2945 * packet or between the LQ and command packet. 2946 */ 2947 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 2948 2949 /* 2950 * Update the waiting for selection queue so 2951 * we restart on the correct SCB. 2952 */ 2953 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 2954 saved_scbptr = ahd_get_scbptr(ahd); 2955 if (waiting_h != scbid) { 2956 2957 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 2958 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 2959 if (waiting_t == waiting_h) { 2960 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 2961 next = SCB_LIST_NULL; 2962 } else { 2963 ahd_set_scbptr(ahd, waiting_h); 2964 next = ahd_inw_scbram(ahd, SCB_NEXT2); 2965 } 2966 ahd_set_scbptr(ahd, scbid); 2967 ahd_outw(ahd, SCB_NEXT2, next); 2968 } 2969 ahd_set_scbptr(ahd, saved_scbptr); 2970 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 2971 if (SCB_IS_SILENT(scb) == FALSE) { 2972 ahd_print_path(ahd, scb); 2973 printk("Probable outgoing LQ CRC error. " 2974 "Retrying command\n"); 2975 } 2976 scb->crc_retry_count++; 2977 } else { 2978 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 2979 ahd_freeze_scb(scb); 2980 ahd_freeze_devq(ahd, scb); 2981 } 2982 /* Return unpausing the sequencer. */ 2983 return (0); 2984 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 2985 /* 2986 * Ignore what are really parity errors that 2987 * occur on the last REQ of a free running 2988 * clock prior to going busfree. Some drives 2989 * do not properly active negate just before 2990 * going busfree resulting in a parity glitch. 2991 */ 2992 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 2993 #ifdef AHD_DEBUG 2994 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 2995 printk("%s: Parity on last REQ detected " 2996 "during busfree phase.\n", 2997 ahd_name(ahd)); 2998 #endif 2999 /* Return unpausing the sequencer. */ 3000 return (0); 3001 } 3002 if (ahd->src_mode != AHD_MODE_SCSI) { 3003 u_int scbid; 3004 struct scb *scb; 3005 3006 scbid = ahd_get_scbptr(ahd); 3007 scb = ahd_lookup_scb(ahd, scbid); 3008 ahd_print_path(ahd, scb); 3009 printk("Unexpected PKT busfree condition\n"); 3010 ahd_dump_card_state(ahd); 3011 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 3012 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 3013 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 3014 3015 /* Return restarting the sequencer. */ 3016 return (1); 3017 } 3018 printk("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 3019 ahd_dump_card_state(ahd); 3020 /* Restart the sequencer. */ 3021 return (1); 3022 } 3023 3024 /* 3025 * Non-packetized unexpected or expected busfree. 3026 */ 3027 static int 3028 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 3029 { 3030 struct ahd_devinfo devinfo; 3031 struct scb *scb; 3032 u_int lastphase; 3033 u_int saved_scsiid; 3034 u_int saved_lun; 3035 u_int target; 3036 u_int initiator_role_id; 3037 u_int scbid; 3038 u_int ppr_busfree; 3039 int printerror; 3040 3041 /* 3042 * Look at what phase we were last in. If its message out, 3043 * chances are pretty good that the busfree was in response 3044 * to one of our abort requests. 3045 */ 3046 lastphase = ahd_inb(ahd, LASTPHASE); 3047 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3048 saved_lun = ahd_inb(ahd, SAVED_LUN); 3049 target = SCSIID_TARGET(ahd, saved_scsiid); 3050 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 3051 ahd_compile_devinfo(&devinfo, initiator_role_id, 3052 target, saved_lun, 'A', ROLE_INITIATOR); 3053 printerror = 1; 3054 3055 scbid = ahd_get_scbptr(ahd); 3056 scb = ahd_lookup_scb(ahd, scbid); 3057 if (scb != NULL 3058 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 3059 scb = NULL; 3060 3061 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 3062 if (lastphase == P_MESGOUT) { 3063 u_int tag; 3064 3065 tag = SCB_LIST_NULL; 3066 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 3067 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 3068 int found; 3069 int sent_msg; 3070 3071 if (scb == NULL) { 3072 ahd_print_devinfo(ahd, &devinfo); 3073 printk("Abort for unidentified " 3074 "connection completed.\n"); 3075 /* restart the sequencer. */ 3076 return (1); 3077 } 3078 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 3079 ahd_print_path(ahd, scb); 3080 printk("SCB %d - Abort%s Completed.\n", 3081 SCB_GET_TAG(scb), 3082 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 3083 3084 if (sent_msg == MSG_ABORT_TAG) 3085 tag = SCB_GET_TAG(scb); 3086 3087 if ((scb->flags & SCB_EXTERNAL_RESET) != 0) { 3088 /* 3089 * This abort is in response to an 3090 * unexpected switch to command phase 3091 * for a packetized connection. Since 3092 * the identify message was never sent, 3093 * "saved lun" is 0. We really want to 3094 * abort only the SCB that encountered 3095 * this error, which could have a different 3096 * lun. The SCB will be retried so the OS 3097 * will see the UA after renegotiating to 3098 * packetized. 3099 */ 3100 tag = SCB_GET_TAG(scb); 3101 saved_lun = scb->hscb->lun; 3102 } 3103 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 3104 tag, ROLE_INITIATOR, 3105 CAM_REQ_ABORTED); 3106 printk("found == 0x%x\n", found); 3107 printerror = 0; 3108 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 3109 MSG_BUS_DEV_RESET, TRUE)) { 3110 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 3111 CAM_BDR_SENT, "Bus Device Reset", 3112 /*verbose_level*/0); 3113 printerror = 0; 3114 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 3115 && ppr_busfree == 0) { 3116 struct ahd_initiator_tinfo *tinfo; 3117 struct ahd_tmode_tstate *tstate; 3118 3119 /* 3120 * PPR Rejected. 3121 * 3122 * If the previous negotiation was packetized, 3123 * this could be because the device has been 3124 * reset without our knowledge. Force our 3125 * current negotiation to async and retry the 3126 * negotiation. Otherwise retry the command 3127 * with non-ppr negotiation. 3128 */ 3129 #ifdef AHD_DEBUG 3130 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3131 printk("PPR negotiation rejected busfree.\n"); 3132 #endif 3133 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 3134 devinfo.our_scsiid, 3135 devinfo.target, &tstate); 3136 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) { 3137 ahd_set_width(ahd, &devinfo, 3138 MSG_EXT_WDTR_BUS_8_BIT, 3139 AHD_TRANS_CUR, 3140 /*paused*/TRUE); 3141 ahd_set_syncrate(ahd, &devinfo, 3142 /*period*/0, /*offset*/0, 3143 /*ppr_options*/0, 3144 AHD_TRANS_CUR, 3145 /*paused*/TRUE); 3146 /* 3147 * The expect PPR busfree handler below 3148 * will effect the retry and necessary 3149 * abort. 3150 */ 3151 } else { 3152 tinfo->curr.transport_version = 2; 3153 tinfo->goal.transport_version = 2; 3154 tinfo->goal.ppr_options = 0; 3155 if (scb != NULL) { 3156 /* 3157 * Remove any SCBs in the waiting 3158 * for selection queue that may 3159 * also be for this target so that 3160 * command ordering is preserved. 3161 */ 3162 ahd_freeze_devq(ahd, scb); 3163 ahd_qinfifo_requeue_tail(ahd, scb); 3164 } 3165 printerror = 0; 3166 } 3167 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 3168 && ppr_busfree == 0) { 3169 /* 3170 * Negotiation Rejected. Go-narrow and 3171 * retry command. 3172 */ 3173 #ifdef AHD_DEBUG 3174 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3175 printk("WDTR negotiation rejected busfree.\n"); 3176 #endif 3177 ahd_set_width(ahd, &devinfo, 3178 MSG_EXT_WDTR_BUS_8_BIT, 3179 AHD_TRANS_CUR|AHD_TRANS_GOAL, 3180 /*paused*/TRUE); 3181 if (scb != NULL) { 3182 /* 3183 * Remove any SCBs in the waiting for 3184 * selection queue that may also be for 3185 * this target so that command ordering 3186 * is preserved. 3187 */ 3188 ahd_freeze_devq(ahd, scb); 3189 ahd_qinfifo_requeue_tail(ahd, scb); 3190 } 3191 printerror = 0; 3192 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE) 3193 && ppr_busfree == 0) { 3194 /* 3195 * Negotiation Rejected. Go-async and 3196 * retry command. 3197 */ 3198 #ifdef AHD_DEBUG 3199 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3200 printk("SDTR negotiation rejected busfree.\n"); 3201 #endif 3202 ahd_set_syncrate(ahd, &devinfo, 3203 /*period*/0, /*offset*/0, 3204 /*ppr_options*/0, 3205 AHD_TRANS_CUR|AHD_TRANS_GOAL, 3206 /*paused*/TRUE); 3207 if (scb != NULL) { 3208 /* 3209 * Remove any SCBs in the waiting for 3210 * selection queue that may also be for 3211 * this target so that command ordering 3212 * is preserved. 3213 */ 3214 ahd_freeze_devq(ahd, scb); 3215 ahd_qinfifo_requeue_tail(ahd, scb); 3216 } 3217 printerror = 0; 3218 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 3219 && ahd_sent_msg(ahd, AHDMSG_1B, 3220 MSG_INITIATOR_DET_ERR, TRUE)) { 3221 3222 #ifdef AHD_DEBUG 3223 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3224 printk("Expected IDE Busfree\n"); 3225 #endif 3226 printerror = 0; 3227 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 3228 && ahd_sent_msg(ahd, AHDMSG_1B, 3229 MSG_MESSAGE_REJECT, TRUE)) { 3230 3231 #ifdef AHD_DEBUG 3232 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3233 printk("Expected QAS Reject Busfree\n"); 3234 #endif 3235 printerror = 0; 3236 } 3237 } 3238 3239 /* 3240 * The busfree required flag is honored at the end of 3241 * the message phases. We check it last in case we 3242 * had to send some other message that caused a busfree. 3243 */ 3244 if (scb != NULL && printerror != 0 3245 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 3246 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 3247 3248 ahd_freeze_devq(ahd, scb); 3249 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 3250 ahd_freeze_scb(scb); 3251 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 3252 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 3253 SCB_GET_CHANNEL(ahd, scb), 3254 SCB_GET_LUN(scb), SCB_LIST_NULL, 3255 ROLE_INITIATOR, CAM_REQ_ABORTED); 3256 } else { 3257 #ifdef AHD_DEBUG 3258 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3259 printk("PPR Negotiation Busfree.\n"); 3260 #endif 3261 ahd_done(ahd, scb); 3262 } 3263 printerror = 0; 3264 } 3265 if (printerror != 0) { 3266 int aborted; 3267 3268 aborted = 0; 3269 if (scb != NULL) { 3270 u_int tag; 3271 3272 if ((scb->hscb->control & TAG_ENB) != 0) 3273 tag = SCB_GET_TAG(scb); 3274 else 3275 tag = SCB_LIST_NULL; 3276 ahd_print_path(ahd, scb); 3277 aborted = ahd_abort_scbs(ahd, target, 'A', 3278 SCB_GET_LUN(scb), tag, 3279 ROLE_INITIATOR, 3280 CAM_UNEXP_BUSFREE); 3281 } else { 3282 /* 3283 * We had not fully identified this connection, 3284 * so we cannot abort anything. 3285 */ 3286 printk("%s: ", ahd_name(ahd)); 3287 } 3288 printk("Unexpected busfree %s, %d SCBs aborted, " 3289 "PRGMCNT == 0x%x\n", 3290 ahd_lookup_phase_entry(lastphase)->phasemsg, 3291 aborted, 3292 ahd_inw(ahd, PRGMCNT)); 3293 ahd_dump_card_state(ahd); 3294 if (lastphase != P_BUSFREE) 3295 ahd_force_renegotiation(ahd, &devinfo); 3296 } 3297 /* Always restart the sequencer. */ 3298 return (1); 3299 } 3300 3301 static void 3302 ahd_handle_proto_violation(struct ahd_softc *ahd) 3303 { 3304 struct ahd_devinfo devinfo; 3305 struct scb *scb; 3306 u_int scbid; 3307 u_int seq_flags; 3308 u_int curphase; 3309 u_int lastphase; 3310 int found; 3311 3312 ahd_fetch_devinfo(ahd, &devinfo); 3313 scbid = ahd_get_scbptr(ahd); 3314 scb = ahd_lookup_scb(ahd, scbid); 3315 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 3316 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 3317 lastphase = ahd_inb(ahd, LASTPHASE); 3318 if ((seq_flags & NOT_IDENTIFIED) != 0) { 3319 3320 /* 3321 * The reconnecting target either did not send an 3322 * identify message, or did, but we didn't find an SCB 3323 * to match. 3324 */ 3325 ahd_print_devinfo(ahd, &devinfo); 3326 printk("Target did not send an IDENTIFY message. " 3327 "LASTPHASE = 0x%x.\n", lastphase); 3328 scb = NULL; 3329 } else if (scb == NULL) { 3330 /* 3331 * We don't seem to have an SCB active for this 3332 * transaction. Print an error and reset the bus. 3333 */ 3334 ahd_print_devinfo(ahd, &devinfo); 3335 printk("No SCB found during protocol violation\n"); 3336 goto proto_violation_reset; 3337 } else { 3338 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 3339 if ((seq_flags & NO_CDB_SENT) != 0) { 3340 ahd_print_path(ahd, scb); 3341 printk("No or incomplete CDB sent to device.\n"); 3342 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 3343 & STATUS_RCVD) == 0) { 3344 /* 3345 * The target never bothered to provide status to 3346 * us prior to completing the command. Since we don't 3347 * know the disposition of this command, we must attempt 3348 * to abort it. Assert ATN and prepare to send an abort 3349 * message. 3350 */ 3351 ahd_print_path(ahd, scb); 3352 printk("Completed command without status.\n"); 3353 } else { 3354 ahd_print_path(ahd, scb); 3355 printk("Unknown protocol violation.\n"); 3356 ahd_dump_card_state(ahd); 3357 } 3358 } 3359 if ((lastphase & ~P_DATAIN_DT) == 0 3360 || lastphase == P_COMMAND) { 3361 proto_violation_reset: 3362 /* 3363 * Target either went directly to data 3364 * phase or didn't respond to our ATN. 3365 * The only safe thing to do is to blow 3366 * it away with a bus reset. 3367 */ 3368 found = ahd_reset_channel(ahd, 'A', TRUE); 3369 printk("%s: Issued Channel %c Bus Reset. " 3370 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 3371 } else { 3372 /* 3373 * Leave the selection hardware off in case 3374 * this abort attempt will affect yet to 3375 * be sent commands. 3376 */ 3377 ahd_outb(ahd, SCSISEQ0, 3378 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 3379 ahd_assert_atn(ahd); 3380 ahd_outb(ahd, MSG_OUT, HOST_MSG); 3381 if (scb == NULL) { 3382 ahd_print_devinfo(ahd, &devinfo); 3383 ahd->msgout_buf[0] = MSG_ABORT_TASK; 3384 ahd->msgout_len = 1; 3385 ahd->msgout_index = 0; 3386 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3387 } else { 3388 ahd_print_path(ahd, scb); 3389 scb->flags |= SCB_ABORT; 3390 } 3391 printk("Protocol violation %s. Attempting to abort.\n", 3392 ahd_lookup_phase_entry(curphase)->phasemsg); 3393 } 3394 } 3395 3396 /* 3397 * Force renegotiation to occur the next time we initiate 3398 * a command to the current device. 3399 */ 3400 static void 3401 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3402 { 3403 struct ahd_initiator_tinfo *targ_info; 3404 struct ahd_tmode_tstate *tstate; 3405 3406 #ifdef AHD_DEBUG 3407 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3408 ahd_print_devinfo(ahd, devinfo); 3409 printk("Forcing renegotiation\n"); 3410 } 3411 #endif 3412 targ_info = ahd_fetch_transinfo(ahd, 3413 devinfo->channel, 3414 devinfo->our_scsiid, 3415 devinfo->target, 3416 &tstate); 3417 ahd_update_neg_request(ahd, devinfo, tstate, 3418 targ_info, AHD_NEG_IF_NON_ASYNC); 3419 } 3420 3421 #define AHD_MAX_STEPS 2000 3422 static void 3423 ahd_clear_critical_section(struct ahd_softc *ahd) 3424 { 3425 ahd_mode_state saved_modes; 3426 int stepping; 3427 int steps; 3428 int first_instr; 3429 u_int simode0; 3430 u_int simode1; 3431 u_int simode3; 3432 u_int lqimode0; 3433 u_int lqimode1; 3434 u_int lqomode0; 3435 u_int lqomode1; 3436 3437 if (ahd->num_critical_sections == 0) 3438 return; 3439 3440 stepping = FALSE; 3441 steps = 0; 3442 first_instr = 0; 3443 simode0 = 0; 3444 simode1 = 0; 3445 simode3 = 0; 3446 lqimode0 = 0; 3447 lqimode1 = 0; 3448 lqomode0 = 0; 3449 lqomode1 = 0; 3450 saved_modes = ahd_save_modes(ahd); 3451 for (;;) { 3452 struct cs *cs; 3453 u_int seqaddr; 3454 u_int i; 3455 3456 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3457 seqaddr = ahd_inw(ahd, CURADDR); 3458 3459 cs = ahd->critical_sections; 3460 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 3461 3462 if (cs->begin < seqaddr && cs->end >= seqaddr) 3463 break; 3464 } 3465 3466 if (i == ahd->num_critical_sections) 3467 break; 3468 3469 if (steps > AHD_MAX_STEPS) { 3470 printk("%s: Infinite loop in critical section\n" 3471 "%s: First Instruction 0x%x now 0x%x\n", 3472 ahd_name(ahd), ahd_name(ahd), first_instr, 3473 seqaddr); 3474 ahd_dump_card_state(ahd); 3475 panic("critical section loop"); 3476 } 3477 3478 steps++; 3479 #ifdef AHD_DEBUG 3480 if ((ahd_debug & AHD_SHOW_MISC) != 0) 3481 printk("%s: Single stepping at 0x%x\n", ahd_name(ahd), 3482 seqaddr); 3483 #endif 3484 if (stepping == FALSE) { 3485 3486 first_instr = seqaddr; 3487 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 3488 simode0 = ahd_inb(ahd, SIMODE0); 3489 simode3 = ahd_inb(ahd, SIMODE3); 3490 lqimode0 = ahd_inb(ahd, LQIMODE0); 3491 lqimode1 = ahd_inb(ahd, LQIMODE1); 3492 lqomode0 = ahd_inb(ahd, LQOMODE0); 3493 lqomode1 = ahd_inb(ahd, LQOMODE1); 3494 ahd_outb(ahd, SIMODE0, 0); 3495 ahd_outb(ahd, SIMODE3, 0); 3496 ahd_outb(ahd, LQIMODE0, 0); 3497 ahd_outb(ahd, LQIMODE1, 0); 3498 ahd_outb(ahd, LQOMODE0, 0); 3499 ahd_outb(ahd, LQOMODE1, 0); 3500 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3501 simode1 = ahd_inb(ahd, SIMODE1); 3502 /* 3503 * We don't clear ENBUSFREE. Unfortunately 3504 * we cannot re-enable busfree detection within 3505 * the current connection, so we must leave it 3506 * on while single stepping. 3507 */ 3508 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE); 3509 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 3510 stepping = TRUE; 3511 } 3512 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 3513 ahd_outb(ahd, CLRINT, CLRSCSIINT); 3514 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 3515 ahd_outb(ahd, HCNTRL, ahd->unpause); 3516 while (!ahd_is_paused(ahd)) 3517 ahd_delay(200); 3518 ahd_update_modes(ahd); 3519 } 3520 if (stepping) { 3521 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 3522 ahd_outb(ahd, SIMODE0, simode0); 3523 ahd_outb(ahd, SIMODE3, simode3); 3524 ahd_outb(ahd, LQIMODE0, lqimode0); 3525 ahd_outb(ahd, LQIMODE1, lqimode1); 3526 ahd_outb(ahd, LQOMODE0, lqomode0); 3527 ahd_outb(ahd, LQOMODE1, lqomode1); 3528 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3529 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 3530 ahd_outb(ahd, SIMODE1, simode1); 3531 /* 3532 * SCSIINT seems to glitch occasionally when 3533 * the interrupt masks are restored. Clear SCSIINT 3534 * one more time so that only persistent errors 3535 * are seen as a real interrupt. 3536 */ 3537 ahd_outb(ahd, CLRINT, CLRSCSIINT); 3538 } 3539 ahd_restore_modes(ahd, saved_modes); 3540 } 3541 3542 /* 3543 * Clear any pending interrupt status. 3544 */ 3545 static void 3546 ahd_clear_intstat(struct ahd_softc *ahd) 3547 { 3548 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 3549 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 3550 /* Clear any interrupt conditions this may have caused */ 3551 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 3552 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 3553 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 3554 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 3555 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 3556 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 3557 |CLRLQOATNPKT|CLRLQOTCRC); 3558 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 3559 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 3560 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 3561 ahd_outb(ahd, CLRLQOINT0, 0); 3562 ahd_outb(ahd, CLRLQOINT1, 0); 3563 } 3564 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 3565 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 3566 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 3567 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 3568 |CLRIOERR|CLROVERRUN); 3569 ahd_outb(ahd, CLRINT, CLRSCSIINT); 3570 } 3571 3572 /**************************** Debugging Routines ******************************/ 3573 #ifdef AHD_DEBUG 3574 uint32_t ahd_debug = AHD_DEBUG_OPTS; 3575 #endif 3576 3577 #if 0 3578 void 3579 ahd_print_scb(struct scb *scb) 3580 { 3581 struct hardware_scb *hscb; 3582 int i; 3583 3584 hscb = scb->hscb; 3585 printk("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 3586 (void *)scb, 3587 hscb->control, 3588 hscb->scsiid, 3589 hscb->lun, 3590 hscb->cdb_len); 3591 printk("Shared Data: "); 3592 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 3593 printk("%#02x", hscb->shared_data.idata.cdb[i]); 3594 printk(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 3595 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 3596 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 3597 ahd_le32toh(hscb->datacnt), 3598 ahd_le32toh(hscb->sgptr), 3599 SCB_GET_TAG(scb)); 3600 ahd_dump_sglist(scb); 3601 } 3602 #endif /* 0 */ 3603 3604 /************************* Transfer Negotiation *******************************/ 3605 /* 3606 * Allocate per target mode instance (ID we respond to as a target) 3607 * transfer negotiation data structures. 3608 */ 3609 static struct ahd_tmode_tstate * 3610 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 3611 { 3612 struct ahd_tmode_tstate *master_tstate; 3613 struct ahd_tmode_tstate *tstate; 3614 int i; 3615 3616 master_tstate = ahd->enabled_targets[ahd->our_id]; 3617 if (ahd->enabled_targets[scsi_id] != NULL 3618 && ahd->enabled_targets[scsi_id] != master_tstate) 3619 panic("%s: ahd_alloc_tstate - Target already allocated", 3620 ahd_name(ahd)); 3621 tstate = kmalloc(sizeof(*tstate), GFP_ATOMIC); 3622 if (tstate == NULL) 3623 return (NULL); 3624 3625 /* 3626 * If we have allocated a master tstate, copy user settings from 3627 * the master tstate (taken from SRAM or the EEPROM) for this 3628 * channel, but reset our current and goal settings to async/narrow 3629 * until an initiator talks to us. 3630 */ 3631 if (master_tstate != NULL) { 3632 memcpy(tstate, master_tstate, sizeof(*tstate)); 3633 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 3634 for (i = 0; i < 16; i++) { 3635 memset(&tstate->transinfo[i].curr, 0, 3636 sizeof(tstate->transinfo[i].curr)); 3637 memset(&tstate->transinfo[i].goal, 0, 3638 sizeof(tstate->transinfo[i].goal)); 3639 } 3640 } else 3641 memset(tstate, 0, sizeof(*tstate)); 3642 ahd->enabled_targets[scsi_id] = tstate; 3643 return (tstate); 3644 } 3645 3646 #ifdef AHD_TARGET_MODE 3647 /* 3648 * Free per target mode instance (ID we respond to as a target) 3649 * transfer negotiation data structures. 3650 */ 3651 static void 3652 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 3653 { 3654 struct ahd_tmode_tstate *tstate; 3655 3656 /* 3657 * Don't clean up our "master" tstate. 3658 * It has our default user settings. 3659 */ 3660 if (scsi_id == ahd->our_id 3661 && force == FALSE) 3662 return; 3663 3664 tstate = ahd->enabled_targets[scsi_id]; 3665 if (tstate != NULL) 3666 kfree(tstate); 3667 ahd->enabled_targets[scsi_id] = NULL; 3668 } 3669 #endif 3670 3671 /* 3672 * Called when we have an active connection to a target on the bus, 3673 * this function finds the nearest period to the input period limited 3674 * by the capabilities of the bus connectivity of and sync settings for 3675 * the target. 3676 */ 3677 static void 3678 ahd_devlimited_syncrate(struct ahd_softc *ahd, 3679 struct ahd_initiator_tinfo *tinfo, 3680 u_int *period, u_int *ppr_options, role_t role) 3681 { 3682 struct ahd_transinfo *transinfo; 3683 u_int maxsync; 3684 3685 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 3686 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 3687 maxsync = AHD_SYNCRATE_PACED; 3688 } else { 3689 maxsync = AHD_SYNCRATE_ULTRA; 3690 /* Can't do DT related options on an SE bus */ 3691 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 3692 } 3693 /* 3694 * Never allow a value higher than our current goal 3695 * period otherwise we may allow a target initiated 3696 * negotiation to go above the limit as set by the 3697 * user. In the case of an initiator initiated 3698 * sync negotiation, we limit based on the user 3699 * setting. This allows the system to still accept 3700 * incoming negotiations even if target initiated 3701 * negotiation is not performed. 3702 */ 3703 if (role == ROLE_TARGET) 3704 transinfo = &tinfo->user; 3705 else 3706 transinfo = &tinfo->goal; 3707 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 3708 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 3709 maxsync = max(maxsync, (u_int)AHD_SYNCRATE_ULTRA2); 3710 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 3711 } 3712 if (transinfo->period == 0) { 3713 *period = 0; 3714 *ppr_options = 0; 3715 } else { 3716 *period = max(*period, (u_int)transinfo->period); 3717 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 3718 } 3719 } 3720 3721 /* 3722 * Look up the valid period to SCSIRATE conversion in our table. 3723 * Return the period and offset that should be sent to the target 3724 * if this was the beginning of an SDTR. 3725 */ 3726 void 3727 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 3728 u_int *ppr_options, u_int maxsync) 3729 { 3730 if (*period < maxsync) 3731 *period = maxsync; 3732 3733 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 3734 && *period > AHD_SYNCRATE_MIN_DT) 3735 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 3736 3737 if (*period > AHD_SYNCRATE_MIN) 3738 *period = 0; 3739 3740 /* Honor PPR option conformance rules. */ 3741 if (*period > AHD_SYNCRATE_PACED) 3742 *ppr_options &= ~MSG_EXT_PPR_RTI; 3743 3744 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 3745 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 3746 3747 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 3748 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 3749 3750 /* Skip all PACED only entries if IU is not available */ 3751 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 3752 && *period < AHD_SYNCRATE_DT) 3753 *period = AHD_SYNCRATE_DT; 3754 3755 /* Skip all DT only entries if DT is not available */ 3756 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3757 && *period < AHD_SYNCRATE_ULTRA2) 3758 *period = AHD_SYNCRATE_ULTRA2; 3759 } 3760 3761 /* 3762 * Truncate the given synchronous offset to a value the 3763 * current adapter type and syncrate are capable of. 3764 */ 3765 static void 3766 ahd_validate_offset(struct ahd_softc *ahd, 3767 struct ahd_initiator_tinfo *tinfo, 3768 u_int period, u_int *offset, int wide, 3769 role_t role) 3770 { 3771 u_int maxoffset; 3772 3773 /* Limit offset to what we can do */ 3774 if (period == 0) 3775 maxoffset = 0; 3776 else if (period <= AHD_SYNCRATE_PACED) { 3777 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 3778 maxoffset = MAX_OFFSET_PACED_BUG; 3779 else 3780 maxoffset = MAX_OFFSET_PACED; 3781 } else 3782 maxoffset = MAX_OFFSET_NON_PACED; 3783 *offset = min(*offset, maxoffset); 3784 if (tinfo != NULL) { 3785 if (role == ROLE_TARGET) 3786 *offset = min(*offset, (u_int)tinfo->user.offset); 3787 else 3788 *offset = min(*offset, (u_int)tinfo->goal.offset); 3789 } 3790 } 3791 3792 /* 3793 * Truncate the given transfer width parameter to a value the 3794 * current adapter type is capable of. 3795 */ 3796 static void 3797 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 3798 u_int *bus_width, role_t role) 3799 { 3800 switch (*bus_width) { 3801 default: 3802 if (ahd->features & AHD_WIDE) { 3803 /* Respond Wide */ 3804 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3805 break; 3806 } 3807 /* FALLTHROUGH */ 3808 case MSG_EXT_WDTR_BUS_8_BIT: 3809 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3810 break; 3811 } 3812 if (tinfo != NULL) { 3813 if (role == ROLE_TARGET) 3814 *bus_width = min((u_int)tinfo->user.width, *bus_width); 3815 else 3816 *bus_width = min((u_int)tinfo->goal.width, *bus_width); 3817 } 3818 } 3819 3820 /* 3821 * Update the bitmask of targets for which the controller should 3822 * negotiate with at the next convenient opportunity. This currently 3823 * means the next time we send the initial identify messages for 3824 * a new transaction. 3825 */ 3826 int 3827 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3828 struct ahd_tmode_tstate *tstate, 3829 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 3830 { 3831 u_int auto_negotiate_orig; 3832 3833 auto_negotiate_orig = tstate->auto_negotiate; 3834 if (neg_type == AHD_NEG_ALWAYS) { 3835 /* 3836 * Force our "current" settings to be 3837 * unknown so that unless a bus reset 3838 * occurs the need to renegotiate is 3839 * recorded persistently. 3840 */ 3841 if ((ahd->features & AHD_WIDE) != 0) 3842 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 3843 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 3844 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 3845 } 3846 if (tinfo->curr.period != tinfo->goal.period 3847 || tinfo->curr.width != tinfo->goal.width 3848 || tinfo->curr.offset != tinfo->goal.offset 3849 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 3850 || (neg_type == AHD_NEG_IF_NON_ASYNC 3851 && (tinfo->goal.offset != 0 3852 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 3853 || tinfo->goal.ppr_options != 0))) 3854 tstate->auto_negotiate |= devinfo->target_mask; 3855 else 3856 tstate->auto_negotiate &= ~devinfo->target_mask; 3857 3858 return (auto_negotiate_orig != tstate->auto_negotiate); 3859 } 3860 3861 /* 3862 * Update the user/goal/curr tables of synchronous negotiation 3863 * parameters as well as, in the case of a current or active update, 3864 * any data structures on the host controller. In the case of an 3865 * active update, the specified target is currently talking to us on 3866 * the bus, so the transfer parameter update must take effect 3867 * immediately. 3868 */ 3869 void 3870 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3871 u_int period, u_int offset, u_int ppr_options, 3872 u_int type, int paused) 3873 { 3874 struct ahd_initiator_tinfo *tinfo; 3875 struct ahd_tmode_tstate *tstate; 3876 u_int old_period; 3877 u_int old_offset; 3878 u_int old_ppr; 3879 int active; 3880 int update_needed; 3881 3882 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 3883 update_needed = 0; 3884 3885 if (period == 0 || offset == 0) { 3886 period = 0; 3887 offset = 0; 3888 } 3889 3890 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3891 devinfo->target, &tstate); 3892 3893 if ((type & AHD_TRANS_USER) != 0) { 3894 tinfo->user.period = period; 3895 tinfo->user.offset = offset; 3896 tinfo->user.ppr_options = ppr_options; 3897 } 3898 3899 if ((type & AHD_TRANS_GOAL) != 0) { 3900 tinfo->goal.period = period; 3901 tinfo->goal.offset = offset; 3902 tinfo->goal.ppr_options = ppr_options; 3903 } 3904 3905 old_period = tinfo->curr.period; 3906 old_offset = tinfo->curr.offset; 3907 old_ppr = tinfo->curr.ppr_options; 3908 3909 if ((type & AHD_TRANS_CUR) != 0 3910 && (old_period != period 3911 || old_offset != offset 3912 || old_ppr != ppr_options)) { 3913 3914 update_needed++; 3915 3916 tinfo->curr.period = period; 3917 tinfo->curr.offset = offset; 3918 tinfo->curr.ppr_options = ppr_options; 3919 3920 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3921 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 3922 if (bootverbose) { 3923 if (offset != 0) { 3924 int options; 3925 3926 printk("%s: target %d synchronous with " 3927 "period = 0x%x, offset = 0x%x", 3928 ahd_name(ahd), devinfo->target, 3929 period, offset); 3930 options = 0; 3931 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 3932 printk("(RDSTRM"); 3933 options++; 3934 } 3935 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 3936 printk("%s", options ? "|DT" : "(DT"); 3937 options++; 3938 } 3939 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 3940 printk("%s", options ? "|IU" : "(IU"); 3941 options++; 3942 } 3943 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 3944 printk("%s", options ? "|RTI" : "(RTI"); 3945 options++; 3946 } 3947 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 3948 printk("%s", options ? "|QAS" : "(QAS"); 3949 options++; 3950 } 3951 if (options != 0) 3952 printk(")\n"); 3953 else 3954 printk("\n"); 3955 } else { 3956 printk("%s: target %d using " 3957 "asynchronous transfers%s\n", 3958 ahd_name(ahd), devinfo->target, 3959 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 3960 ? "(QAS)" : ""); 3961 } 3962 } 3963 } 3964 /* 3965 * Always refresh the neg-table to handle the case of the 3966 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 3967 * We will always renegotiate in that case if this is a 3968 * packetized request. Also manage the busfree expected flag 3969 * from this common routine so that we catch changes due to 3970 * WDTR or SDTR messages. 3971 */ 3972 if ((type & AHD_TRANS_CUR) != 0) { 3973 if (!paused) 3974 ahd_pause(ahd); 3975 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3976 if (!paused) 3977 ahd_unpause(ahd); 3978 if (ahd->msg_type != MSG_TYPE_NONE) { 3979 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 3980 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 3981 #ifdef AHD_DEBUG 3982 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3983 ahd_print_devinfo(ahd, devinfo); 3984 printk("Expecting IU Change busfree\n"); 3985 } 3986 #endif 3987 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 3988 | MSG_FLAG_IU_REQ_CHANGED; 3989 } 3990 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 3991 #ifdef AHD_DEBUG 3992 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3993 printk("PPR with IU_REQ outstanding\n"); 3994 #endif 3995 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 3996 } 3997 } 3998 } 3999 4000 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 4001 tinfo, AHD_NEG_TO_GOAL); 4002 4003 if (update_needed && active) 4004 ahd_update_pending_scbs(ahd); 4005 } 4006 4007 /* 4008 * Update the user/goal/curr tables of wide negotiation 4009 * parameters as well as, in the case of a current or active update, 4010 * any data structures on the host controller. In the case of an 4011 * active update, the specified target is currently talking to us on 4012 * the bus, so the transfer parameter update must take effect 4013 * immediately. 4014 */ 4015 void 4016 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4017 u_int width, u_int type, int paused) 4018 { 4019 struct ahd_initiator_tinfo *tinfo; 4020 struct ahd_tmode_tstate *tstate; 4021 u_int oldwidth; 4022 int active; 4023 int update_needed; 4024 4025 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 4026 update_needed = 0; 4027 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 4028 devinfo->target, &tstate); 4029 4030 if ((type & AHD_TRANS_USER) != 0) 4031 tinfo->user.width = width; 4032 4033 if ((type & AHD_TRANS_GOAL) != 0) 4034 tinfo->goal.width = width; 4035 4036 oldwidth = tinfo->curr.width; 4037 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 4038 4039 update_needed++; 4040 4041 tinfo->curr.width = width; 4042 ahd_send_async(ahd, devinfo->channel, devinfo->target, 4043 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 4044 if (bootverbose) { 4045 printk("%s: target %d using %dbit transfers\n", 4046 ahd_name(ahd), devinfo->target, 4047 8 * (0x01 << width)); 4048 } 4049 } 4050 4051 if ((type & AHD_TRANS_CUR) != 0) { 4052 if (!paused) 4053 ahd_pause(ahd); 4054 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 4055 if (!paused) 4056 ahd_unpause(ahd); 4057 } 4058 4059 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 4060 tinfo, AHD_NEG_TO_GOAL); 4061 if (update_needed && active) 4062 ahd_update_pending_scbs(ahd); 4063 4064 } 4065 4066 /* 4067 * Update the current state of tagged queuing for a given target. 4068 */ 4069 static void 4070 ahd_set_tags(struct ahd_softc *ahd, struct scsi_cmnd *cmd, 4071 struct ahd_devinfo *devinfo, ahd_queue_alg alg) 4072 { 4073 struct scsi_device *sdev = cmd->device; 4074 4075 ahd_platform_set_tags(ahd, sdev, devinfo, alg); 4076 ahd_send_async(ahd, devinfo->channel, devinfo->target, 4077 devinfo->lun, AC_TRANSFER_NEG); 4078 } 4079 4080 static void 4081 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4082 struct ahd_transinfo *tinfo) 4083 { 4084 ahd_mode_state saved_modes; 4085 u_int period; 4086 u_int ppr_opts; 4087 u_int con_opts; 4088 u_int offset; 4089 u_int saved_negoaddr; 4090 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 4091 4092 saved_modes = ahd_save_modes(ahd); 4093 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4094 4095 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 4096 ahd_outb(ahd, NEGOADDR, devinfo->target); 4097 period = tinfo->period; 4098 offset = tinfo->offset; 4099 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 4100 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 4101 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 4102 con_opts = 0; 4103 if (period == 0) 4104 period = AHD_SYNCRATE_ASYNC; 4105 if (period == AHD_SYNCRATE_160) { 4106 4107 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 4108 /* 4109 * When the SPI4 spec was finalized, PACE transfers 4110 * was not made a configurable option in the PPR 4111 * message. Instead it is assumed to be enabled for 4112 * any syncrate faster than 80MHz. Nevertheless, 4113 * Harpoon2A4 allows this to be configurable. 4114 * 4115 * Harpoon2A4 also assumes at most 2 data bytes per 4116 * negotiated REQ/ACK offset. Paced transfers take 4117 * 4, so we must adjust our offset. 4118 */ 4119 ppr_opts |= PPROPT_PACE; 4120 offset *= 2; 4121 4122 /* 4123 * Harpoon2A assumed that there would be a 4124 * fallback rate between 160MHz and 80MHz, 4125 * so 7 is used as the period factor rather 4126 * than 8 for 160MHz. 4127 */ 4128 period = AHD_SYNCRATE_REVA_160; 4129 } 4130 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 4131 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 4132 ~AHD_PRECOMP_MASK; 4133 } else { 4134 /* 4135 * Precomp should be disabled for non-paced transfers. 4136 */ 4137 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 4138 4139 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 4140 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0 4141 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) { 4142 /* 4143 * Slow down our CRC interval to be 4144 * compatible with non-packetized 4145 * U160 devices that can't handle a 4146 * CRC at full speed. 4147 */ 4148 con_opts |= ENSLOWCRC; 4149 } 4150 4151 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 4152 /* 4153 * On H2A4, revert to a slower slewrate 4154 * on non-paced transfers. 4155 */ 4156 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 4157 ~AHD_SLEWRATE_MASK; 4158 } 4159 } 4160 4161 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 4162 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 4163 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 4164 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 4165 4166 ahd_outb(ahd, NEGPERIOD, period); 4167 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 4168 ahd_outb(ahd, NEGOFFSET, offset); 4169 4170 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 4171 con_opts |= WIDEXFER; 4172 4173 /* 4174 * Slow down our CRC interval to be 4175 * compatible with packetized U320 devices 4176 * that can't handle a CRC at full speed 4177 */ 4178 if (ahd->features & AHD_AIC79XXB_SLOWCRC) { 4179 con_opts |= ENSLOWCRC; 4180 } 4181 4182 /* 4183 * During packetized transfers, the target will 4184 * give us the opportunity to send command packets 4185 * without us asserting attention. 4186 */ 4187 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 4188 con_opts |= ENAUTOATNO; 4189 ahd_outb(ahd, NEGCONOPTS, con_opts); 4190 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 4191 ahd_restore_modes(ahd, saved_modes); 4192 } 4193 4194 /* 4195 * When the transfer settings for a connection change, setup for 4196 * negotiation in pending SCBs to effect the change as quickly as 4197 * possible. We also cancel any negotiations that are scheduled 4198 * for inflight SCBs that have not been started yet. 4199 */ 4200 static void 4201 ahd_update_pending_scbs(struct ahd_softc *ahd) 4202 { 4203 struct scb *pending_scb; 4204 int pending_scb_count; 4205 int paused; 4206 u_int saved_scbptr; 4207 ahd_mode_state saved_modes; 4208 4209 /* 4210 * Traverse the pending SCB list and ensure that all of the 4211 * SCBs there have the proper settings. We can only safely 4212 * clear the negotiation required flag (setting requires the 4213 * execution queue to be modified) and this is only possible 4214 * if we are not already attempting to select out for this 4215 * SCB. For this reason, all callers only call this routine 4216 * if we are changing the negotiation settings for the currently 4217 * active transaction on the bus. 4218 */ 4219 pending_scb_count = 0; 4220 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 4221 struct ahd_devinfo devinfo; 4222 struct ahd_initiator_tinfo *tinfo; 4223 struct ahd_tmode_tstate *tstate; 4224 4225 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 4226 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 4227 devinfo.our_scsiid, 4228 devinfo.target, &tstate); 4229 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 4230 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 4231 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 4232 pending_scb->hscb->control &= ~MK_MESSAGE; 4233 } 4234 ahd_sync_scb(ahd, pending_scb, 4235 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4236 pending_scb_count++; 4237 } 4238 4239 if (pending_scb_count == 0) 4240 return; 4241 4242 if (ahd_is_paused(ahd)) { 4243 paused = 1; 4244 } else { 4245 paused = 0; 4246 ahd_pause(ahd); 4247 } 4248 4249 /* 4250 * Force the sequencer to reinitialize the selection for 4251 * the command at the head of the execution queue if it 4252 * has already been setup. The negotiation changes may 4253 * effect whether we select-out with ATN. It is only 4254 * safe to clear ENSELO when the bus is not free and no 4255 * selection is in progres or completed. 4256 */ 4257 saved_modes = ahd_save_modes(ahd); 4258 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4259 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0 4260 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 4261 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 4262 saved_scbptr = ahd_get_scbptr(ahd); 4263 /* Ensure that the hscbs down on the card match the new information */ 4264 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 4265 u_int scb_tag; 4266 u_int control; 4267 4268 scb_tag = SCB_GET_TAG(pending_scb); 4269 ahd_set_scbptr(ahd, scb_tag); 4270 control = ahd_inb_scbram(ahd, SCB_CONTROL); 4271 control &= ~MK_MESSAGE; 4272 control |= pending_scb->hscb->control & MK_MESSAGE; 4273 ahd_outb(ahd, SCB_CONTROL, control); 4274 } 4275 ahd_set_scbptr(ahd, saved_scbptr); 4276 ahd_restore_modes(ahd, saved_modes); 4277 4278 if (paused == 0) 4279 ahd_unpause(ahd); 4280 } 4281 4282 /**************************** Pathing Information *****************************/ 4283 static void 4284 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4285 { 4286 ahd_mode_state saved_modes; 4287 u_int saved_scsiid; 4288 role_t role; 4289 int our_id; 4290 4291 saved_modes = ahd_save_modes(ahd); 4292 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4293 4294 if (ahd_inb(ahd, SSTAT0) & TARGET) 4295 role = ROLE_TARGET; 4296 else 4297 role = ROLE_INITIATOR; 4298 4299 if (role == ROLE_TARGET 4300 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 4301 /* We were selected, so pull our id from TARGIDIN */ 4302 our_id = ahd_inb(ahd, TARGIDIN) & OID; 4303 } else if (role == ROLE_TARGET) 4304 our_id = ahd_inb(ahd, TOWNID); 4305 else 4306 our_id = ahd_inb(ahd, IOWNID); 4307 4308 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 4309 ahd_compile_devinfo(devinfo, 4310 our_id, 4311 SCSIID_TARGET(ahd, saved_scsiid), 4312 ahd_inb(ahd, SAVED_LUN), 4313 SCSIID_CHANNEL(ahd, saved_scsiid), 4314 role); 4315 ahd_restore_modes(ahd, saved_modes); 4316 } 4317 4318 void 4319 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4320 { 4321 printk("%s:%c:%d:%d: ", ahd_name(ahd), 'A', 4322 devinfo->target, devinfo->lun); 4323 } 4324 4325 static const struct ahd_phase_table_entry* 4326 ahd_lookup_phase_entry(int phase) 4327 { 4328 const struct ahd_phase_table_entry *entry; 4329 const struct ahd_phase_table_entry *last_entry; 4330 4331 /* 4332 * num_phases doesn't include the default entry which 4333 * will be returned if the phase doesn't match. 4334 */ 4335 last_entry = &ahd_phase_table[num_phases]; 4336 for (entry = ahd_phase_table; entry < last_entry; entry++) { 4337 if (phase == entry->phase) 4338 break; 4339 } 4340 return (entry); 4341 } 4342 4343 void 4344 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 4345 u_int lun, char channel, role_t role) 4346 { 4347 devinfo->our_scsiid = our_id; 4348 devinfo->target = target; 4349 devinfo->lun = lun; 4350 devinfo->target_offset = target; 4351 devinfo->channel = channel; 4352 devinfo->role = role; 4353 if (channel == 'B') 4354 devinfo->target_offset += 8; 4355 devinfo->target_mask = (0x01 << devinfo->target_offset); 4356 } 4357 4358 static void 4359 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4360 struct scb *scb) 4361 { 4362 role_t role; 4363 int our_id; 4364 4365 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 4366 role = ROLE_INITIATOR; 4367 if ((scb->hscb->control & TARGET_SCB) != 0) 4368 role = ROLE_TARGET; 4369 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 4370 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 4371 } 4372 4373 4374 /************************ Message Phase Processing ****************************/ 4375 /* 4376 * When an initiator transaction with the MK_MESSAGE flag either reconnects 4377 * or enters the initial message out phase, we are interrupted. Fill our 4378 * outgoing message buffer with the appropriate message and beging handing 4379 * the message phase(s) manually. 4380 */ 4381 static void 4382 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4383 struct scb *scb) 4384 { 4385 /* 4386 * To facilitate adding multiple messages together, 4387 * each routine should increment the index and len 4388 * variables instead of setting them explicitly. 4389 */ 4390 ahd->msgout_index = 0; 4391 ahd->msgout_len = 0; 4392 4393 if (ahd_currently_packetized(ahd)) 4394 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 4395 4396 if (ahd->send_msg_perror 4397 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 4398 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 4399 ahd->msgout_len++; 4400 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 4401 #ifdef AHD_DEBUG 4402 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4403 printk("Setting up for Parity Error delivery\n"); 4404 #endif 4405 return; 4406 } else if (scb == NULL) { 4407 printk("%s: WARNING. No pending message for " 4408 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 4409 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 4410 ahd->msgout_len++; 4411 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 4412 return; 4413 } 4414 4415 if ((scb->flags & SCB_DEVICE_RESET) == 0 4416 && (scb->flags & SCB_PACKETIZED) == 0 4417 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 4418 u_int identify_msg; 4419 4420 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 4421 if ((scb->hscb->control & DISCENB) != 0) 4422 identify_msg |= MSG_IDENTIFY_DISCFLAG; 4423 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 4424 ahd->msgout_len++; 4425 4426 if ((scb->hscb->control & TAG_ENB) != 0) { 4427 ahd->msgout_buf[ahd->msgout_index++] = 4428 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 4429 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 4430 ahd->msgout_len += 2; 4431 } 4432 } 4433 4434 if (scb->flags & SCB_DEVICE_RESET) { 4435 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 4436 ahd->msgout_len++; 4437 ahd_print_path(ahd, scb); 4438 printk("Bus Device Reset Message Sent\n"); 4439 /* 4440 * Clear our selection hardware in advance of 4441 * the busfree. We may have an entry in the waiting 4442 * Q for this target, and we don't want to go about 4443 * selecting while we handle the busfree and blow it 4444 * away. 4445 */ 4446 ahd_outb(ahd, SCSISEQ0, 0); 4447 } else if ((scb->flags & SCB_ABORT) != 0) { 4448 4449 if ((scb->hscb->control & TAG_ENB) != 0) { 4450 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 4451 } else { 4452 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 4453 } 4454 ahd->msgout_len++; 4455 ahd_print_path(ahd, scb); 4456 printk("Abort%s Message Sent\n", 4457 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 4458 /* 4459 * Clear our selection hardware in advance of 4460 * the busfree. We may have an entry in the waiting 4461 * Q for this target, and we don't want to go about 4462 * selecting while we handle the busfree and blow it 4463 * away. 4464 */ 4465 ahd_outb(ahd, SCSISEQ0, 0); 4466 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 4467 ahd_build_transfer_msg(ahd, devinfo); 4468 /* 4469 * Clear our selection hardware in advance of potential 4470 * PPR IU status change busfree. We may have an entry in 4471 * the waiting Q for this target, and we don't want to go 4472 * about selecting while we handle the busfree and blow 4473 * it away. 4474 */ 4475 ahd_outb(ahd, SCSISEQ0, 0); 4476 } else { 4477 printk("ahd_intr: AWAITING_MSG for an SCB that " 4478 "does not have a waiting message\n"); 4479 printk("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 4480 devinfo->target_mask); 4481 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 4482 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 4483 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 4484 scb->flags); 4485 } 4486 4487 /* 4488 * Clear the MK_MESSAGE flag from the SCB so we aren't 4489 * asked to send this message again. 4490 */ 4491 ahd_outb(ahd, SCB_CONTROL, 4492 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 4493 scb->hscb->control &= ~MK_MESSAGE; 4494 ahd->msgout_index = 0; 4495 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 4496 } 4497 4498 /* 4499 * Build an appropriate transfer negotiation message for the 4500 * currently active target. 4501 */ 4502 static void 4503 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4504 { 4505 /* 4506 * We need to initiate transfer negotiations. 4507 * If our current and goal settings are identical, 4508 * we want to renegotiate due to a check condition. 4509 */ 4510 struct ahd_initiator_tinfo *tinfo; 4511 struct ahd_tmode_tstate *tstate; 4512 int dowide; 4513 int dosync; 4514 int doppr; 4515 u_int period; 4516 u_int ppr_options; 4517 u_int offset; 4518 4519 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 4520 devinfo->target, &tstate); 4521 /* 4522 * Filter our period based on the current connection. 4523 * If we can't perform DT transfers on this segment (not in LVD 4524 * mode for instance), then our decision to issue a PPR message 4525 * may change. 4526 */ 4527 period = tinfo->goal.period; 4528 offset = tinfo->goal.offset; 4529 ppr_options = tinfo->goal.ppr_options; 4530 /* Target initiated PPR is not allowed in the SCSI spec */ 4531 if (devinfo->role == ROLE_TARGET) 4532 ppr_options = 0; 4533 ahd_devlimited_syncrate(ahd, tinfo, &period, 4534 &ppr_options, devinfo->role); 4535 dowide = tinfo->curr.width != tinfo->goal.width; 4536 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 4537 /* 4538 * Only use PPR if we have options that need it, even if the device 4539 * claims to support it. There might be an expander in the way 4540 * that doesn't. 4541 */ 4542 doppr = ppr_options != 0; 4543 4544 if (!dowide && !dosync && !doppr) { 4545 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 4546 dosync = tinfo->goal.offset != 0; 4547 } 4548 4549 if (!dowide && !dosync && !doppr) { 4550 /* 4551 * Force async with a WDTR message if we have a wide bus, 4552 * or just issue an SDTR with a 0 offset. 4553 */ 4554 if ((ahd->features & AHD_WIDE) != 0) 4555 dowide = 1; 4556 else 4557 dosync = 1; 4558 4559 if (bootverbose) { 4560 ahd_print_devinfo(ahd, devinfo); 4561 printk("Ensuring async\n"); 4562 } 4563 } 4564 /* Target initiated PPR is not allowed in the SCSI spec */ 4565 if (devinfo->role == ROLE_TARGET) 4566 doppr = 0; 4567 4568 /* 4569 * Both the PPR message and SDTR message require the 4570 * goal syncrate to be limited to what the target device 4571 * is capable of handling (based on whether an LVD->SE 4572 * expander is on the bus), so combine these two cases. 4573 * Regardless, guarantee that if we are using WDTR and SDTR 4574 * messages that WDTR comes first. 4575 */ 4576 if (doppr || (dosync && !dowide)) { 4577 4578 offset = tinfo->goal.offset; 4579 ahd_validate_offset(ahd, tinfo, period, &offset, 4580 doppr ? tinfo->goal.width 4581 : tinfo->curr.width, 4582 devinfo->role); 4583 if (doppr) { 4584 ahd_construct_ppr(ahd, devinfo, period, offset, 4585 tinfo->goal.width, ppr_options); 4586 } else { 4587 ahd_construct_sdtr(ahd, devinfo, period, offset); 4588 } 4589 } else { 4590 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 4591 } 4592 } 4593 4594 /* 4595 * Build a synchronous negotiation message in our message 4596 * buffer based on the input parameters. 4597 */ 4598 static void 4599 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4600 u_int period, u_int offset) 4601 { 4602 if (offset == 0) 4603 period = AHD_ASYNC_XFER_PERIOD; 4604 ahd->msgout_index += spi_populate_sync_msg( 4605 ahd->msgout_buf + ahd->msgout_index, period, offset); 4606 ahd->msgout_len += 5; 4607 if (bootverbose) { 4608 printk("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 4609 ahd_name(ahd), devinfo->channel, devinfo->target, 4610 devinfo->lun, period, offset); 4611 } 4612 } 4613 4614 /* 4615 * Build a wide negotiateion message in our message 4616 * buffer based on the input parameters. 4617 */ 4618 static void 4619 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4620 u_int bus_width) 4621 { 4622 ahd->msgout_index += spi_populate_width_msg( 4623 ahd->msgout_buf + ahd->msgout_index, bus_width); 4624 ahd->msgout_len += 4; 4625 if (bootverbose) { 4626 printk("(%s:%c:%d:%d): Sending WDTR %x\n", 4627 ahd_name(ahd), devinfo->channel, devinfo->target, 4628 devinfo->lun, bus_width); 4629 } 4630 } 4631 4632 /* 4633 * Build a parallel protocol request message in our message 4634 * buffer based on the input parameters. 4635 */ 4636 static void 4637 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4638 u_int period, u_int offset, u_int bus_width, 4639 u_int ppr_options) 4640 { 4641 /* 4642 * Always request precompensation from 4643 * the other target if we are running 4644 * at paced syncrates. 4645 */ 4646 if (period <= AHD_SYNCRATE_PACED) 4647 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 4648 if (offset == 0) 4649 period = AHD_ASYNC_XFER_PERIOD; 4650 ahd->msgout_index += spi_populate_ppr_msg( 4651 ahd->msgout_buf + ahd->msgout_index, period, offset, 4652 bus_width, ppr_options); 4653 ahd->msgout_len += 8; 4654 if (bootverbose) { 4655 printk("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 4656 "offset %x, ppr_options %x\n", ahd_name(ahd), 4657 devinfo->channel, devinfo->target, devinfo->lun, 4658 bus_width, period, offset, ppr_options); 4659 } 4660 } 4661 4662 /* 4663 * Clear any active message state. 4664 */ 4665 static void 4666 ahd_clear_msg_state(struct ahd_softc *ahd) 4667 { 4668 ahd_mode_state saved_modes; 4669 4670 saved_modes = ahd_save_modes(ahd); 4671 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4672 ahd->send_msg_perror = 0; 4673 ahd->msg_flags = MSG_FLAG_NONE; 4674 ahd->msgout_len = 0; 4675 ahd->msgin_index = 0; 4676 ahd->msg_type = MSG_TYPE_NONE; 4677 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 4678 /* 4679 * The target didn't care to respond to our 4680 * message request, so clear ATN. 4681 */ 4682 ahd_outb(ahd, CLRSINT1, CLRATNO); 4683 } 4684 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 4685 ahd_outb(ahd, SEQ_FLAGS2, 4686 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 4687 ahd_restore_modes(ahd, saved_modes); 4688 } 4689 4690 /* 4691 * Manual message loop handler. 4692 */ 4693 static void 4694 ahd_handle_message_phase(struct ahd_softc *ahd) 4695 { 4696 struct ahd_devinfo devinfo; 4697 u_int bus_phase; 4698 int end_session; 4699 4700 ahd_fetch_devinfo(ahd, &devinfo); 4701 end_session = FALSE; 4702 bus_phase = ahd_inb(ahd, LASTPHASE); 4703 4704 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 4705 printk("LQIRETRY for LQIPHASE_OUTPKT\n"); 4706 ahd_outb(ahd, LQCTL2, LQIRETRY); 4707 } 4708 reswitch: 4709 switch (ahd->msg_type) { 4710 case MSG_TYPE_INITIATOR_MSGOUT: 4711 { 4712 int lastbyte; 4713 int phasemis; 4714 int msgdone; 4715 4716 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 4717 panic("HOST_MSG_LOOP interrupt with no active message"); 4718 4719 #ifdef AHD_DEBUG 4720 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 4721 ahd_print_devinfo(ahd, &devinfo); 4722 printk("INITIATOR_MSG_OUT"); 4723 } 4724 #endif 4725 phasemis = bus_phase != P_MESGOUT; 4726 if (phasemis) { 4727 #ifdef AHD_DEBUG 4728 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 4729 printk(" PHASEMIS %s\n", 4730 ahd_lookup_phase_entry(bus_phase) 4731 ->phasemsg); 4732 } 4733 #endif 4734 if (bus_phase == P_MESGIN) { 4735 /* 4736 * Change gears and see if 4737 * this messages is of interest to 4738 * us or should be passed back to 4739 * the sequencer. 4740 */ 4741 ahd_outb(ahd, CLRSINT1, CLRATNO); 4742 ahd->send_msg_perror = 0; 4743 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 4744 ahd->msgin_index = 0; 4745 goto reswitch; 4746 } 4747 end_session = TRUE; 4748 break; 4749 } 4750 4751 if (ahd->send_msg_perror) { 4752 ahd_outb(ahd, CLRSINT1, CLRATNO); 4753 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 4754 #ifdef AHD_DEBUG 4755 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4756 printk(" byte 0x%x\n", ahd->send_msg_perror); 4757 #endif 4758 /* 4759 * If we are notifying the target of a CRC error 4760 * during packetized operations, the target is 4761 * within its rights to acknowledge our message 4762 * with a busfree. 4763 */ 4764 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 4765 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 4766 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 4767 4768 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 4769 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 4770 break; 4771 } 4772 4773 msgdone = ahd->msgout_index == ahd->msgout_len; 4774 if (msgdone) { 4775 /* 4776 * The target has requested a retry. 4777 * Re-assert ATN, reset our message index to 4778 * 0, and try again. 4779 */ 4780 ahd->msgout_index = 0; 4781 ahd_assert_atn(ahd); 4782 } 4783 4784 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 4785 if (lastbyte) { 4786 /* Last byte is signified by dropping ATN */ 4787 ahd_outb(ahd, CLRSINT1, CLRATNO); 4788 } 4789 4790 /* 4791 * Clear our interrupt status and present 4792 * the next byte on the bus. 4793 */ 4794 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 4795 #ifdef AHD_DEBUG 4796 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4797 printk(" byte 0x%x\n", 4798 ahd->msgout_buf[ahd->msgout_index]); 4799 #endif 4800 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 4801 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 4802 break; 4803 } 4804 case MSG_TYPE_INITIATOR_MSGIN: 4805 { 4806 int phasemis; 4807 int message_done; 4808 4809 #ifdef AHD_DEBUG 4810 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 4811 ahd_print_devinfo(ahd, &devinfo); 4812 printk("INITIATOR_MSG_IN"); 4813 } 4814 #endif 4815 phasemis = bus_phase != P_MESGIN; 4816 if (phasemis) { 4817 #ifdef AHD_DEBUG 4818 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 4819 printk(" PHASEMIS %s\n", 4820 ahd_lookup_phase_entry(bus_phase) 4821 ->phasemsg); 4822 } 4823 #endif 4824 ahd->msgin_index = 0; 4825 if (bus_phase == P_MESGOUT 4826 && (ahd->send_msg_perror != 0 4827 || (ahd->msgout_len != 0 4828 && ahd->msgout_index == 0))) { 4829 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 4830 goto reswitch; 4831 } 4832 end_session = TRUE; 4833 break; 4834 } 4835 4836 /* Pull the byte in without acking it */ 4837 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 4838 #ifdef AHD_DEBUG 4839 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4840 printk(" byte 0x%x\n", 4841 ahd->msgin_buf[ahd->msgin_index]); 4842 #endif 4843 4844 message_done = ahd_parse_msg(ahd, &devinfo); 4845 4846 if (message_done) { 4847 /* 4848 * Clear our incoming message buffer in case there 4849 * is another message following this one. 4850 */ 4851 ahd->msgin_index = 0; 4852 4853 /* 4854 * If this message illicited a response, 4855 * assert ATN so the target takes us to the 4856 * message out phase. 4857 */ 4858 if (ahd->msgout_len != 0) { 4859 #ifdef AHD_DEBUG 4860 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 4861 ahd_print_devinfo(ahd, &devinfo); 4862 printk("Asserting ATN for response\n"); 4863 } 4864 #endif 4865 ahd_assert_atn(ahd); 4866 } 4867 } else 4868 ahd->msgin_index++; 4869 4870 if (message_done == MSGLOOP_TERMINATED) { 4871 end_session = TRUE; 4872 } else { 4873 /* Ack the byte */ 4874 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 4875 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 4876 } 4877 break; 4878 } 4879 case MSG_TYPE_TARGET_MSGIN: 4880 { 4881 int msgdone; 4882 int msgout_request; 4883 4884 /* 4885 * By default, the message loop will continue. 4886 */ 4887 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4888 4889 if (ahd->msgout_len == 0) 4890 panic("Target MSGIN with no active message"); 4891 4892 /* 4893 * If we interrupted a mesgout session, the initiator 4894 * will not know this until our first REQ. So, we 4895 * only honor mesgout requests after we've sent our 4896 * first byte. 4897 */ 4898 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 4899 && ahd->msgout_index > 0) 4900 msgout_request = TRUE; 4901 else 4902 msgout_request = FALSE; 4903 4904 if (msgout_request) { 4905 4906 /* 4907 * Change gears and see if 4908 * this messages is of interest to 4909 * us or should be passed back to 4910 * the sequencer. 4911 */ 4912 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 4913 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 4914 ahd->msgin_index = 0; 4915 /* Dummy read to REQ for first byte */ 4916 ahd_inb(ahd, SCSIDAT); 4917 ahd_outb(ahd, SXFRCTL0, 4918 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4919 break; 4920 } 4921 4922 msgdone = ahd->msgout_index == ahd->msgout_len; 4923 if (msgdone) { 4924 ahd_outb(ahd, SXFRCTL0, 4925 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4926 end_session = TRUE; 4927 break; 4928 } 4929 4930 /* 4931 * Present the next byte on the bus. 4932 */ 4933 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4934 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 4935 break; 4936 } 4937 case MSG_TYPE_TARGET_MSGOUT: 4938 { 4939 int lastbyte; 4940 int msgdone; 4941 4942 /* 4943 * By default, the message loop will continue. 4944 */ 4945 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4946 4947 /* 4948 * The initiator signals that this is 4949 * the last byte by dropping ATN. 4950 */ 4951 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 4952 4953 /* 4954 * Read the latched byte, but turn off SPIOEN first 4955 * so that we don't inadvertently cause a REQ for the 4956 * next byte. 4957 */ 4958 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4959 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 4960 msgdone = ahd_parse_msg(ahd, &devinfo); 4961 if (msgdone == MSGLOOP_TERMINATED) { 4962 /* 4963 * The message is *really* done in that it caused 4964 * us to go to bus free. The sequencer has already 4965 * been reset at this point, so pull the ejection 4966 * handle. 4967 */ 4968 return; 4969 } 4970 4971 ahd->msgin_index++; 4972 4973 /* 4974 * XXX Read spec about initiator dropping ATN too soon 4975 * and use msgdone to detect it. 4976 */ 4977 if (msgdone == MSGLOOP_MSGCOMPLETE) { 4978 ahd->msgin_index = 0; 4979 4980 /* 4981 * If this message illicited a response, transition 4982 * to the Message in phase and send it. 4983 */ 4984 if (ahd->msgout_len != 0) { 4985 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 4986 ahd_outb(ahd, SXFRCTL0, 4987 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4988 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4989 ahd->msgin_index = 0; 4990 break; 4991 } 4992 } 4993 4994 if (lastbyte) 4995 end_session = TRUE; 4996 else { 4997 /* Ask for the next byte. */ 4998 ahd_outb(ahd, SXFRCTL0, 4999 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 5000 } 5001 5002 break; 5003 } 5004 default: 5005 panic("Unknown REQINIT message type"); 5006 } 5007 5008 if (end_session) { 5009 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 5010 printk("%s: Returning to Idle Loop\n", 5011 ahd_name(ahd)); 5012 ahd_clear_msg_state(ahd); 5013 5014 /* 5015 * Perform the equivalent of a clear_target_state. 5016 */ 5017 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 5018 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT); 5019 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 5020 } else { 5021 ahd_clear_msg_state(ahd); 5022 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 5023 } 5024 } 5025 } 5026 5027 /* 5028 * See if we sent a particular extended message to the target. 5029 * If "full" is true, return true only if the target saw the full 5030 * message. If "full" is false, return true if the target saw at 5031 * least the first byte of the message. 5032 */ 5033 static int 5034 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 5035 { 5036 int found; 5037 u_int index; 5038 5039 found = FALSE; 5040 index = 0; 5041 5042 while (index < ahd->msgout_len) { 5043 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 5044 u_int end_index; 5045 5046 end_index = index + 1 + ahd->msgout_buf[index + 1]; 5047 if (ahd->msgout_buf[index+2] == msgval 5048 && type == AHDMSG_EXT) { 5049 5050 if (full) { 5051 if (ahd->msgout_index > end_index) 5052 found = TRUE; 5053 } else if (ahd->msgout_index > index) 5054 found = TRUE; 5055 } 5056 index = end_index; 5057 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 5058 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 5059 5060 /* Skip tag type and tag id or residue param*/ 5061 index += 2; 5062 } else { 5063 /* Single byte message */ 5064 if (type == AHDMSG_1B 5065 && ahd->msgout_index > index 5066 && (ahd->msgout_buf[index] == msgval 5067 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 5068 && msgval == MSG_IDENTIFYFLAG))) 5069 found = TRUE; 5070 index++; 5071 } 5072 5073 if (found) 5074 break; 5075 } 5076 return (found); 5077 } 5078 5079 /* 5080 * Wait for a complete incoming message, parse it, and respond accordingly. 5081 */ 5082 static int 5083 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 5084 { 5085 struct ahd_initiator_tinfo *tinfo; 5086 struct ahd_tmode_tstate *tstate; 5087 int reject; 5088 int done; 5089 int response; 5090 5091 done = MSGLOOP_IN_PROG; 5092 response = FALSE; 5093 reject = FALSE; 5094 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 5095 devinfo->target, &tstate); 5096 5097 /* 5098 * Parse as much of the message as is available, 5099 * rejecting it if we don't support it. When 5100 * the entire message is available and has been 5101 * handled, return MSGLOOP_MSGCOMPLETE, indicating 5102 * that we have parsed an entire message. 5103 * 5104 * In the case of extended messages, we accept the length 5105 * byte outright and perform more checking once we know the 5106 * extended message type. 5107 */ 5108 switch (ahd->msgin_buf[0]) { 5109 case MSG_DISCONNECT: 5110 case MSG_SAVEDATAPOINTER: 5111 case MSG_CMDCOMPLETE: 5112 case MSG_RESTOREPOINTERS: 5113 case MSG_IGN_WIDE_RESIDUE: 5114 /* 5115 * End our message loop as these are messages 5116 * the sequencer handles on its own. 5117 */ 5118 done = MSGLOOP_TERMINATED; 5119 break; 5120 case MSG_MESSAGE_REJECT: 5121 response = ahd_handle_msg_reject(ahd, devinfo); 5122 /* FALLTHROUGH */ 5123 case MSG_NOOP: 5124 done = MSGLOOP_MSGCOMPLETE; 5125 break; 5126 case MSG_EXTENDED: 5127 { 5128 /* Wait for enough of the message to begin validation */ 5129 if (ahd->msgin_index < 2) 5130 break; 5131 switch (ahd->msgin_buf[2]) { 5132 case MSG_EXT_SDTR: 5133 { 5134 u_int period; 5135 u_int ppr_options; 5136 u_int offset; 5137 u_int saved_offset; 5138 5139 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 5140 reject = TRUE; 5141 break; 5142 } 5143 5144 /* 5145 * Wait until we have both args before validating 5146 * and acting on this message. 5147 * 5148 * Add one to MSG_EXT_SDTR_LEN to account for 5149 * the extended message preamble. 5150 */ 5151 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 5152 break; 5153 5154 period = ahd->msgin_buf[3]; 5155 ppr_options = 0; 5156 saved_offset = offset = ahd->msgin_buf[4]; 5157 ahd_devlimited_syncrate(ahd, tinfo, &period, 5158 &ppr_options, devinfo->role); 5159 ahd_validate_offset(ahd, tinfo, period, &offset, 5160 tinfo->curr.width, devinfo->role); 5161 if (bootverbose) { 5162 printk("(%s:%c:%d:%d): Received " 5163 "SDTR period %x, offset %x\n\t" 5164 "Filtered to period %x, offset %x\n", 5165 ahd_name(ahd), devinfo->channel, 5166 devinfo->target, devinfo->lun, 5167 ahd->msgin_buf[3], saved_offset, 5168 period, offset); 5169 } 5170 ahd_set_syncrate(ahd, devinfo, period, 5171 offset, ppr_options, 5172 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 5173 /*paused*/TRUE); 5174 5175 /* 5176 * See if we initiated Sync Negotiation 5177 * and didn't have to fall down to async 5178 * transfers. 5179 */ 5180 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 5181 /* We started it */ 5182 if (saved_offset != offset) { 5183 /* Went too low - force async */ 5184 reject = TRUE; 5185 } 5186 } else { 5187 /* 5188 * Send our own SDTR in reply 5189 */ 5190 if (bootverbose 5191 && devinfo->role == ROLE_INITIATOR) { 5192 printk("(%s:%c:%d:%d): Target " 5193 "Initiated SDTR\n", 5194 ahd_name(ahd), devinfo->channel, 5195 devinfo->target, devinfo->lun); 5196 } 5197 ahd->msgout_index = 0; 5198 ahd->msgout_len = 0; 5199 ahd_construct_sdtr(ahd, devinfo, 5200 period, offset); 5201 ahd->msgout_index = 0; 5202 response = TRUE; 5203 } 5204 done = MSGLOOP_MSGCOMPLETE; 5205 break; 5206 } 5207 case MSG_EXT_WDTR: 5208 { 5209 u_int bus_width; 5210 u_int saved_width; 5211 u_int sending_reply; 5212 5213 sending_reply = FALSE; 5214 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 5215 reject = TRUE; 5216 break; 5217 } 5218 5219 /* 5220 * Wait until we have our arg before validating 5221 * and acting on this message. 5222 * 5223 * Add one to MSG_EXT_WDTR_LEN to account for 5224 * the extended message preamble. 5225 */ 5226 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 5227 break; 5228 5229 bus_width = ahd->msgin_buf[3]; 5230 saved_width = bus_width; 5231 ahd_validate_width(ahd, tinfo, &bus_width, 5232 devinfo->role); 5233 if (bootverbose) { 5234 printk("(%s:%c:%d:%d): Received WDTR " 5235 "%x filtered to %x\n", 5236 ahd_name(ahd), devinfo->channel, 5237 devinfo->target, devinfo->lun, 5238 saved_width, bus_width); 5239 } 5240 5241 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 5242 /* 5243 * Don't send a WDTR back to the 5244 * target, since we asked first. 5245 * If the width went higher than our 5246 * request, reject it. 5247 */ 5248 if (saved_width > bus_width) { 5249 reject = TRUE; 5250 printk("(%s:%c:%d:%d): requested %dBit " 5251 "transfers. Rejecting...\n", 5252 ahd_name(ahd), devinfo->channel, 5253 devinfo->target, devinfo->lun, 5254 8 * (0x01 << bus_width)); 5255 bus_width = 0; 5256 } 5257 } else { 5258 /* 5259 * Send our own WDTR in reply 5260 */ 5261 if (bootverbose 5262 && devinfo->role == ROLE_INITIATOR) { 5263 printk("(%s:%c:%d:%d): Target " 5264 "Initiated WDTR\n", 5265 ahd_name(ahd), devinfo->channel, 5266 devinfo->target, devinfo->lun); 5267 } 5268 ahd->msgout_index = 0; 5269 ahd->msgout_len = 0; 5270 ahd_construct_wdtr(ahd, devinfo, bus_width); 5271 ahd->msgout_index = 0; 5272 response = TRUE; 5273 sending_reply = TRUE; 5274 } 5275 /* 5276 * After a wide message, we are async, but 5277 * some devices don't seem to honor this portion 5278 * of the spec. Force a renegotiation of the 5279 * sync component of our transfer agreement even 5280 * if our goal is async. By updating our width 5281 * after forcing the negotiation, we avoid 5282 * renegotiating for width. 5283 */ 5284 ahd_update_neg_request(ahd, devinfo, tstate, 5285 tinfo, AHD_NEG_ALWAYS); 5286 ahd_set_width(ahd, devinfo, bus_width, 5287 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 5288 /*paused*/TRUE); 5289 if (sending_reply == FALSE && reject == FALSE) { 5290 5291 /* 5292 * We will always have an SDTR to send. 5293 */ 5294 ahd->msgout_index = 0; 5295 ahd->msgout_len = 0; 5296 ahd_build_transfer_msg(ahd, devinfo); 5297 ahd->msgout_index = 0; 5298 response = TRUE; 5299 } 5300 done = MSGLOOP_MSGCOMPLETE; 5301 break; 5302 } 5303 case MSG_EXT_PPR: 5304 { 5305 u_int period; 5306 u_int offset; 5307 u_int bus_width; 5308 u_int ppr_options; 5309 u_int saved_width; 5310 u_int saved_offset; 5311 u_int saved_ppr_options; 5312 5313 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 5314 reject = TRUE; 5315 break; 5316 } 5317 5318 /* 5319 * Wait until we have all args before validating 5320 * and acting on this message. 5321 * 5322 * Add one to MSG_EXT_PPR_LEN to account for 5323 * the extended message preamble. 5324 */ 5325 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 5326 break; 5327 5328 period = ahd->msgin_buf[3]; 5329 offset = ahd->msgin_buf[5]; 5330 bus_width = ahd->msgin_buf[6]; 5331 saved_width = bus_width; 5332 ppr_options = ahd->msgin_buf[7]; 5333 /* 5334 * According to the spec, a DT only 5335 * period factor with no DT option 5336 * set implies async. 5337 */ 5338 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 5339 && period <= 9) 5340 offset = 0; 5341 saved_ppr_options = ppr_options; 5342 saved_offset = offset; 5343 5344 /* 5345 * Transfer options are only available if we 5346 * are negotiating wide. 5347 */ 5348 if (bus_width == 0) 5349 ppr_options &= MSG_EXT_PPR_QAS_REQ; 5350 5351 ahd_validate_width(ahd, tinfo, &bus_width, 5352 devinfo->role); 5353 ahd_devlimited_syncrate(ahd, tinfo, &period, 5354 &ppr_options, devinfo->role); 5355 ahd_validate_offset(ahd, tinfo, period, &offset, 5356 bus_width, devinfo->role); 5357 5358 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 5359 /* 5360 * If we are unable to do any of the 5361 * requested options (we went too low), 5362 * then we'll have to reject the message. 5363 */ 5364 if (saved_width > bus_width 5365 || saved_offset != offset 5366 || saved_ppr_options != ppr_options) { 5367 reject = TRUE; 5368 period = 0; 5369 offset = 0; 5370 bus_width = 0; 5371 ppr_options = 0; 5372 } 5373 } else { 5374 if (devinfo->role != ROLE_TARGET) 5375 printk("(%s:%c:%d:%d): Target " 5376 "Initiated PPR\n", 5377 ahd_name(ahd), devinfo->channel, 5378 devinfo->target, devinfo->lun); 5379 else 5380 printk("(%s:%c:%d:%d): Initiator " 5381 "Initiated PPR\n", 5382 ahd_name(ahd), devinfo->channel, 5383 devinfo->target, devinfo->lun); 5384 ahd->msgout_index = 0; 5385 ahd->msgout_len = 0; 5386 ahd_construct_ppr(ahd, devinfo, period, offset, 5387 bus_width, ppr_options); 5388 ahd->msgout_index = 0; 5389 response = TRUE; 5390 } 5391 if (bootverbose) { 5392 printk("(%s:%c:%d:%d): Received PPR width %x, " 5393 "period %x, offset %x,options %x\n" 5394 "\tFiltered to width %x, period %x, " 5395 "offset %x, options %x\n", 5396 ahd_name(ahd), devinfo->channel, 5397 devinfo->target, devinfo->lun, 5398 saved_width, ahd->msgin_buf[3], 5399 saved_offset, saved_ppr_options, 5400 bus_width, period, offset, ppr_options); 5401 } 5402 ahd_set_width(ahd, devinfo, bus_width, 5403 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 5404 /*paused*/TRUE); 5405 ahd_set_syncrate(ahd, devinfo, period, 5406 offset, ppr_options, 5407 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 5408 /*paused*/TRUE); 5409 5410 done = MSGLOOP_MSGCOMPLETE; 5411 break; 5412 } 5413 default: 5414 /* Unknown extended message. Reject it. */ 5415 reject = TRUE; 5416 break; 5417 } 5418 break; 5419 } 5420 #ifdef AHD_TARGET_MODE 5421 case MSG_BUS_DEV_RESET: 5422 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 5423 CAM_BDR_SENT, 5424 "Bus Device Reset Received", 5425 /*verbose_level*/0); 5426 ahd_restart(ahd); 5427 done = MSGLOOP_TERMINATED; 5428 break; 5429 case MSG_ABORT_TAG: 5430 case MSG_ABORT: 5431 case MSG_CLEAR_QUEUE: 5432 { 5433 int tag; 5434 5435 /* Target mode messages */ 5436 if (devinfo->role != ROLE_TARGET) { 5437 reject = TRUE; 5438 break; 5439 } 5440 tag = SCB_LIST_NULL; 5441 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 5442 tag = ahd_inb(ahd, INITIATOR_TAG); 5443 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 5444 devinfo->lun, tag, ROLE_TARGET, 5445 CAM_REQ_ABORTED); 5446 5447 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 5448 if (tstate != NULL) { 5449 struct ahd_tmode_lstate* lstate; 5450 5451 lstate = tstate->enabled_luns[devinfo->lun]; 5452 if (lstate != NULL) { 5453 ahd_queue_lstate_event(ahd, lstate, 5454 devinfo->our_scsiid, 5455 ahd->msgin_buf[0], 5456 /*arg*/tag); 5457 ahd_send_lstate_events(ahd, lstate); 5458 } 5459 } 5460 ahd_restart(ahd); 5461 done = MSGLOOP_TERMINATED; 5462 break; 5463 } 5464 #endif 5465 case MSG_QAS_REQUEST: 5466 #ifdef AHD_DEBUG 5467 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 5468 printk("%s: QAS request. SCSISIGI == 0x%x\n", 5469 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 5470 #endif 5471 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 5472 /* FALLTHROUGH */ 5473 case MSG_TERM_IO_PROC: 5474 default: 5475 reject = TRUE; 5476 break; 5477 } 5478 5479 if (reject) { 5480 /* 5481 * Setup to reject the message. 5482 */ 5483 ahd->msgout_index = 0; 5484 ahd->msgout_len = 1; 5485 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 5486 done = MSGLOOP_MSGCOMPLETE; 5487 response = TRUE; 5488 } 5489 5490 if (done != MSGLOOP_IN_PROG && !response) 5491 /* Clear the outgoing message buffer */ 5492 ahd->msgout_len = 0; 5493 5494 return (done); 5495 } 5496 5497 /* 5498 * Process a message reject message. 5499 */ 5500 static int 5501 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 5502 { 5503 /* 5504 * What we care about here is if we had an 5505 * outstanding SDTR or WDTR message for this 5506 * target. If we did, this is a signal that 5507 * the target is refusing negotiation. 5508 */ 5509 struct scb *scb; 5510 struct ahd_initiator_tinfo *tinfo; 5511 struct ahd_tmode_tstate *tstate; 5512 u_int scb_index; 5513 u_int last_msg; 5514 int response = 0; 5515 5516 scb_index = ahd_get_scbptr(ahd); 5517 scb = ahd_lookup_scb(ahd, scb_index); 5518 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 5519 devinfo->our_scsiid, 5520 devinfo->target, &tstate); 5521 /* Might be necessary */ 5522 last_msg = ahd_inb(ahd, LAST_MSG); 5523 5524 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 5525 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 5526 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 5527 /* 5528 * Target may not like our SPI-4 PPR Options. 5529 * Attempt to negotiate 80MHz which will turn 5530 * off these options. 5531 */ 5532 if (bootverbose) { 5533 printk("(%s:%c:%d:%d): PPR Rejected. " 5534 "Trying simple U160 PPR\n", 5535 ahd_name(ahd), devinfo->channel, 5536 devinfo->target, devinfo->lun); 5537 } 5538 tinfo->goal.period = AHD_SYNCRATE_DT; 5539 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 5540 | MSG_EXT_PPR_QAS_REQ 5541 | MSG_EXT_PPR_DT_REQ; 5542 } else { 5543 /* 5544 * Target does not support the PPR message. 5545 * Attempt to negotiate SPI-2 style. 5546 */ 5547 if (bootverbose) { 5548 printk("(%s:%c:%d:%d): PPR Rejected. " 5549 "Trying WDTR/SDTR\n", 5550 ahd_name(ahd), devinfo->channel, 5551 devinfo->target, devinfo->lun); 5552 } 5553 tinfo->goal.ppr_options = 0; 5554 tinfo->curr.transport_version = 2; 5555 tinfo->goal.transport_version = 2; 5556 } 5557 ahd->msgout_index = 0; 5558 ahd->msgout_len = 0; 5559 ahd_build_transfer_msg(ahd, devinfo); 5560 ahd->msgout_index = 0; 5561 response = 1; 5562 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 5563 5564 /* note 8bit xfers */ 5565 printk("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 5566 "8bit transfers\n", ahd_name(ahd), 5567 devinfo->channel, devinfo->target, devinfo->lun); 5568 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 5569 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 5570 /*paused*/TRUE); 5571 /* 5572 * No need to clear the sync rate. If the target 5573 * did not accept the command, our syncrate is 5574 * unaffected. If the target started the negotiation, 5575 * but rejected our response, we already cleared the 5576 * sync rate before sending our WDTR. 5577 */ 5578 if (tinfo->goal.offset != tinfo->curr.offset) { 5579 5580 /* Start the sync negotiation */ 5581 ahd->msgout_index = 0; 5582 ahd->msgout_len = 0; 5583 ahd_build_transfer_msg(ahd, devinfo); 5584 ahd->msgout_index = 0; 5585 response = 1; 5586 } 5587 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 5588 /* note asynch xfers and clear flag */ 5589 ahd_set_syncrate(ahd, devinfo, /*period*/0, 5590 /*offset*/0, /*ppr_options*/0, 5591 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 5592 /*paused*/TRUE); 5593 printk("(%s:%c:%d:%d): refuses synchronous negotiation. " 5594 "Using asynchronous transfers\n", 5595 ahd_name(ahd), devinfo->channel, 5596 devinfo->target, devinfo->lun); 5597 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 5598 int tag_type; 5599 int mask; 5600 5601 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 5602 5603 if (tag_type == MSG_SIMPLE_TASK) { 5604 printk("(%s:%c:%d:%d): refuses tagged commands. " 5605 "Performing non-tagged I/O\n", ahd_name(ahd), 5606 devinfo->channel, devinfo->target, devinfo->lun); 5607 ahd_set_tags(ahd, scb->io_ctx, devinfo, AHD_QUEUE_NONE); 5608 mask = ~0x23; 5609 } else { 5610 printk("(%s:%c:%d:%d): refuses %s tagged commands. " 5611 "Performing simple queue tagged I/O only\n", 5612 ahd_name(ahd), devinfo->channel, devinfo->target, 5613 devinfo->lun, tag_type == MSG_ORDERED_TASK 5614 ? "ordered" : "head of queue"); 5615 ahd_set_tags(ahd, scb->io_ctx, devinfo, AHD_QUEUE_BASIC); 5616 mask = ~0x03; 5617 } 5618 5619 /* 5620 * Resend the identify for this CCB as the target 5621 * may believe that the selection is invalid otherwise. 5622 */ 5623 ahd_outb(ahd, SCB_CONTROL, 5624 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 5625 scb->hscb->control &= mask; 5626 ahd_set_transaction_tag(scb, /*enabled*/FALSE, 5627 /*type*/MSG_SIMPLE_TASK); 5628 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 5629 ahd_assert_atn(ahd); 5630 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 5631 SCB_GET_TAG(scb)); 5632 5633 /* 5634 * Requeue all tagged commands for this target 5635 * currently in our possession so they can be 5636 * converted to untagged commands. 5637 */ 5638 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 5639 SCB_GET_CHANNEL(ahd, scb), 5640 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 5641 ROLE_INITIATOR, CAM_REQUEUE_REQ, 5642 SEARCH_COMPLETE); 5643 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 5644 /* 5645 * Most likely the device believes that we had 5646 * previously negotiated packetized. 5647 */ 5648 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 5649 | MSG_FLAG_IU_REQ_CHANGED; 5650 5651 ahd_force_renegotiation(ahd, devinfo); 5652 ahd->msgout_index = 0; 5653 ahd->msgout_len = 0; 5654 ahd_build_transfer_msg(ahd, devinfo); 5655 ahd->msgout_index = 0; 5656 response = 1; 5657 } else { 5658 /* 5659 * Otherwise, we ignore it. 5660 */ 5661 printk("%s:%c:%d: Message reject for %x -- ignored\n", 5662 ahd_name(ahd), devinfo->channel, devinfo->target, 5663 last_msg); 5664 } 5665 return (response); 5666 } 5667 5668 /* 5669 * Process an ingnore wide residue message. 5670 */ 5671 static void 5672 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 5673 { 5674 u_int scb_index; 5675 struct scb *scb; 5676 5677 scb_index = ahd_get_scbptr(ahd); 5678 scb = ahd_lookup_scb(ahd, scb_index); 5679 /* 5680 * XXX Actually check data direction in the sequencer? 5681 * Perhaps add datadir to some spare bits in the hscb? 5682 */ 5683 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 5684 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 5685 /* 5686 * Ignore the message if we haven't 5687 * seen an appropriate data phase yet. 5688 */ 5689 } else { 5690 /* 5691 * If the residual occurred on the last 5692 * transfer and the transfer request was 5693 * expected to end on an odd count, do 5694 * nothing. Otherwise, subtract a byte 5695 * and update the residual count accordingly. 5696 */ 5697 uint32_t sgptr; 5698 5699 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 5700 if ((sgptr & SG_LIST_NULL) != 0 5701 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 5702 & SCB_XFERLEN_ODD) != 0) { 5703 /* 5704 * If the residual occurred on the last 5705 * transfer and the transfer request was 5706 * expected to end on an odd count, do 5707 * nothing. 5708 */ 5709 } else { 5710 uint32_t data_cnt; 5711 uint64_t data_addr; 5712 uint32_t sglen; 5713 5714 /* Pull in the rest of the sgptr */ 5715 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 5716 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); 5717 if ((sgptr & SG_LIST_NULL) != 0) { 5718 /* 5719 * The residual data count is not updated 5720 * for the command run to completion case. 5721 * Explicitly zero the count. 5722 */ 5723 data_cnt &= ~AHD_SG_LEN_MASK; 5724 } 5725 data_addr = ahd_inq(ahd, SHADDR); 5726 data_cnt += 1; 5727 data_addr -= 1; 5728 sgptr &= SG_PTR_MASK; 5729 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 5730 struct ahd_dma64_seg *sg; 5731 5732 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5733 5734 /* 5735 * The residual sg ptr points to the next S/G 5736 * to load so we must go back one. 5737 */ 5738 sg--; 5739 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 5740 if (sg != scb->sg_list 5741 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 5742 5743 sg--; 5744 sglen = ahd_le32toh(sg->len); 5745 /* 5746 * Preserve High Address and SG_LIST 5747 * bits while setting the count to 1. 5748 */ 5749 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 5750 data_addr = ahd_le64toh(sg->addr) 5751 + (sglen & AHD_SG_LEN_MASK) 5752 - 1; 5753 5754 /* 5755 * Increment sg so it points to the 5756 * "next" sg. 5757 */ 5758 sg++; 5759 sgptr = ahd_sg_virt_to_bus(ahd, scb, 5760 sg); 5761 } 5762 } else { 5763 struct ahd_dma_seg *sg; 5764 5765 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5766 5767 /* 5768 * The residual sg ptr points to the next S/G 5769 * to load so we must go back one. 5770 */ 5771 sg--; 5772 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 5773 if (sg != scb->sg_list 5774 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 5775 5776 sg--; 5777 sglen = ahd_le32toh(sg->len); 5778 /* 5779 * Preserve High Address and SG_LIST 5780 * bits while setting the count to 1. 5781 */ 5782 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 5783 data_addr = ahd_le32toh(sg->addr) 5784 + (sglen & AHD_SG_LEN_MASK) 5785 - 1; 5786 5787 /* 5788 * Increment sg so it points to the 5789 * "next" sg. 5790 */ 5791 sg++; 5792 sgptr = ahd_sg_virt_to_bus(ahd, scb, 5793 sg); 5794 } 5795 } 5796 /* 5797 * Toggle the "oddness" of the transfer length 5798 * to handle this mid-transfer ignore wide 5799 * residue. This ensures that the oddness is 5800 * correct for subsequent data transfers. 5801 */ 5802 ahd_outb(ahd, SCB_TASK_ATTRIBUTE, 5803 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 5804 ^ SCB_XFERLEN_ODD); 5805 5806 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 5807 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 5808 /* 5809 * The FIFO's pointers will be updated if/when the 5810 * sequencer re-enters a data phase. 5811 */ 5812 } 5813 } 5814 } 5815 5816 5817 /* 5818 * Reinitialize the data pointers for the active transfer 5819 * based on its current residual. 5820 */ 5821 static void 5822 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 5823 { 5824 struct scb *scb; 5825 ahd_mode_state saved_modes; 5826 u_int scb_index; 5827 u_int wait; 5828 uint32_t sgptr; 5829 uint32_t resid; 5830 uint64_t dataptr; 5831 5832 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 5833 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 5834 5835 scb_index = ahd_get_scbptr(ahd); 5836 scb = ahd_lookup_scb(ahd, scb_index); 5837 5838 /* 5839 * Release and reacquire the FIFO so we 5840 * have a clean slate. 5841 */ 5842 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 5843 wait = 1000; 5844 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)) 5845 ahd_delay(100); 5846 if (wait == 0) { 5847 ahd_print_path(ahd, scb); 5848 printk("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 5849 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 5850 } 5851 saved_modes = ahd_save_modes(ahd); 5852 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5853 ahd_outb(ahd, DFFSTAT, 5854 ahd_inb(ahd, DFFSTAT) 5855 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 5856 5857 /* 5858 * Determine initial values for data_addr and data_cnt 5859 * for resuming the data phase. 5860 */ 5861 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 5862 sgptr &= SG_PTR_MASK; 5863 5864 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 5865 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 5866 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 5867 5868 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 5869 struct ahd_dma64_seg *sg; 5870 5871 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5872 5873 /* The residual sg_ptr always points to the next sg */ 5874 sg--; 5875 5876 dataptr = ahd_le64toh(sg->addr) 5877 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 5878 - resid; 5879 ahd_outl(ahd, HADDR + 4, dataptr >> 32); 5880 } else { 5881 struct ahd_dma_seg *sg; 5882 5883 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5884 5885 /* The residual sg_ptr always points to the next sg */ 5886 sg--; 5887 5888 dataptr = ahd_le32toh(sg->addr) 5889 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 5890 - resid; 5891 ahd_outb(ahd, HADDR + 4, 5892 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 5893 } 5894 ahd_outl(ahd, HADDR, dataptr); 5895 ahd_outb(ahd, HCNT + 2, resid >> 16); 5896 ahd_outb(ahd, HCNT + 1, resid >> 8); 5897 ahd_outb(ahd, HCNT, resid); 5898 } 5899 5900 /* 5901 * Handle the effects of issuing a bus device reset message. 5902 */ 5903 static void 5904 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5905 u_int lun, cam_status status, char *message, 5906 int verbose_level) 5907 { 5908 #ifdef AHD_TARGET_MODE 5909 struct ahd_tmode_tstate* tstate; 5910 #endif 5911 int found; 5912 5913 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 5914 lun, SCB_LIST_NULL, devinfo->role, 5915 status); 5916 5917 #ifdef AHD_TARGET_MODE 5918 /* 5919 * Send an immediate notify ccb to all target mord peripheral 5920 * drivers affected by this action. 5921 */ 5922 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 5923 if (tstate != NULL) { 5924 u_int cur_lun; 5925 u_int max_lun; 5926 5927 if (lun != CAM_LUN_WILDCARD) { 5928 cur_lun = 0; 5929 max_lun = AHD_NUM_LUNS - 1; 5930 } else { 5931 cur_lun = lun; 5932 max_lun = lun; 5933 } 5934 for (;cur_lun <= max_lun; cur_lun++) { 5935 struct ahd_tmode_lstate* lstate; 5936 5937 lstate = tstate->enabled_luns[cur_lun]; 5938 if (lstate == NULL) 5939 continue; 5940 5941 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 5942 MSG_BUS_DEV_RESET, /*arg*/0); 5943 ahd_send_lstate_events(ahd, lstate); 5944 } 5945 } 5946 #endif 5947 5948 /* 5949 * Go back to async/narrow transfers and renegotiate. 5950 */ 5951 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 5952 AHD_TRANS_CUR, /*paused*/TRUE); 5953 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 5954 /*ppr_options*/0, AHD_TRANS_CUR, 5955 /*paused*/TRUE); 5956 5957 if (status != CAM_SEL_TIMEOUT) 5958 ahd_send_async(ahd, devinfo->channel, devinfo->target, 5959 CAM_LUN_WILDCARD, AC_SENT_BDR); 5960 5961 if (message != NULL && bootverbose) 5962 printk("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 5963 message, devinfo->channel, devinfo->target, found); 5964 } 5965 5966 #ifdef AHD_TARGET_MODE 5967 static void 5968 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5969 struct scb *scb) 5970 { 5971 5972 /* 5973 * To facilitate adding multiple messages together, 5974 * each routine should increment the index and len 5975 * variables instead of setting them explicitly. 5976 */ 5977 ahd->msgout_index = 0; 5978 ahd->msgout_len = 0; 5979 5980 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 5981 ahd_build_transfer_msg(ahd, devinfo); 5982 else 5983 panic("ahd_intr: AWAITING target message with no message"); 5984 5985 ahd->msgout_index = 0; 5986 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 5987 } 5988 #endif 5989 /**************************** Initialization **********************************/ 5990 static u_int 5991 ahd_sglist_size(struct ahd_softc *ahd) 5992 { 5993 bus_size_t list_size; 5994 5995 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 5996 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5997 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 5998 return (list_size); 5999 } 6000 6001 /* 6002 * Calculate the optimum S/G List allocation size. S/G elements used 6003 * for a given transaction must be physically contiguous. Assume the 6004 * OS will allocate full pages to us, so it doesn't make sense to request 6005 * less than a page. 6006 */ 6007 static u_int 6008 ahd_sglist_allocsize(struct ahd_softc *ahd) 6009 { 6010 bus_size_t sg_list_increment; 6011 bus_size_t sg_list_size; 6012 bus_size_t max_list_size; 6013 bus_size_t best_list_size; 6014 6015 /* Start out with the minimum required for AHD_NSEG. */ 6016 sg_list_increment = ahd_sglist_size(ahd); 6017 sg_list_size = sg_list_increment; 6018 6019 /* Get us as close as possible to a page in size. */ 6020 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 6021 sg_list_size += sg_list_increment; 6022 6023 /* 6024 * Try to reduce the amount of wastage by allocating 6025 * multiple pages. 6026 */ 6027 best_list_size = sg_list_size; 6028 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 6029 if (max_list_size < 4 * PAGE_SIZE) 6030 max_list_size = 4 * PAGE_SIZE; 6031 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 6032 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 6033 while ((sg_list_size + sg_list_increment) <= max_list_size 6034 && (sg_list_size % PAGE_SIZE) != 0) { 6035 bus_size_t new_mod; 6036 bus_size_t best_mod; 6037 6038 sg_list_size += sg_list_increment; 6039 new_mod = sg_list_size % PAGE_SIZE; 6040 best_mod = best_list_size % PAGE_SIZE; 6041 if (new_mod > best_mod || new_mod == 0) { 6042 best_list_size = sg_list_size; 6043 } 6044 } 6045 return (best_list_size); 6046 } 6047 6048 /* 6049 * Allocate a controller structure for a new device 6050 * and perform initial initializion. 6051 */ 6052 struct ahd_softc * 6053 ahd_alloc(void *platform_arg, char *name) 6054 { 6055 struct ahd_softc *ahd; 6056 6057 ahd = kmalloc(sizeof(*ahd), GFP_ATOMIC); 6058 if (!ahd) { 6059 printk("aic7xxx: cannot malloc softc!\n"); 6060 kfree(name); 6061 return NULL; 6062 } 6063 6064 memset(ahd, 0, sizeof(*ahd)); 6065 ahd->seep_config = kmalloc(sizeof(*ahd->seep_config), GFP_ATOMIC); 6066 if (ahd->seep_config == NULL) { 6067 kfree(ahd); 6068 kfree(name); 6069 return (NULL); 6070 } 6071 LIST_INIT(&ahd->pending_scbs); 6072 /* We don't know our unit number until the OSM sets it */ 6073 ahd->name = name; 6074 ahd->unit = -1; 6075 ahd->description = NULL; 6076 ahd->bus_description = NULL; 6077 ahd->channel = 'A'; 6078 ahd->chip = AHD_NONE; 6079 ahd->features = AHD_FENONE; 6080 ahd->bugs = AHD_BUGNONE; 6081 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 6082 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 6083 timer_setup(&ahd->stat_timer, ahd_stat_timer, 0); 6084 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 6085 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 6086 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 6087 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 6088 ahd->int_coalescing_stop_threshold = 6089 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 6090 6091 #ifdef AHD_DEBUG 6092 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) { 6093 printk("%s: scb size = 0x%x, hscb size = 0x%x\n", 6094 ahd_name(ahd), (u_int)sizeof(struct scb), 6095 (u_int)sizeof(struct hardware_scb)); 6096 } 6097 #endif 6098 if (ahd_platform_alloc(ahd, platform_arg) != 0) { 6099 ahd_free(ahd); 6100 ahd = NULL; 6101 } 6102 return (ahd); 6103 } 6104 6105 int 6106 ahd_softc_init(struct ahd_softc *ahd) 6107 { 6108 6109 ahd->unpause = 0; 6110 ahd->pause = PAUSE; 6111 return (0); 6112 } 6113 6114 void 6115 ahd_set_unit(struct ahd_softc *ahd, int unit) 6116 { 6117 ahd->unit = unit; 6118 } 6119 6120 void 6121 ahd_set_name(struct ahd_softc *ahd, char *name) 6122 { 6123 if (ahd->name != NULL) 6124 kfree(ahd->name); 6125 ahd->name = name; 6126 } 6127 6128 void 6129 ahd_free(struct ahd_softc *ahd) 6130 { 6131 int i; 6132 6133 switch (ahd->init_level) { 6134 default: 6135 case 5: 6136 ahd_shutdown(ahd); 6137 /* FALLTHROUGH */ 6138 case 4: 6139 ahd_dmamap_unload(ahd, ahd->shared_data_dmat, 6140 ahd->shared_data_map.dmamap); 6141 /* FALLTHROUGH */ 6142 case 3: 6143 ahd_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo, 6144 ahd->shared_data_map.dmamap); 6145 ahd_dmamap_destroy(ahd, ahd->shared_data_dmat, 6146 ahd->shared_data_map.dmamap); 6147 /* FALLTHROUGH */ 6148 case 2: 6149 ahd_dma_tag_destroy(ahd, ahd->shared_data_dmat); 6150 case 1: 6151 break; 6152 case 0: 6153 break; 6154 } 6155 6156 ahd_platform_free(ahd); 6157 ahd_fini_scbdata(ahd); 6158 for (i = 0; i < AHD_NUM_TARGETS; i++) { 6159 struct ahd_tmode_tstate *tstate; 6160 6161 tstate = ahd->enabled_targets[i]; 6162 if (tstate != NULL) { 6163 #ifdef AHD_TARGET_MODE 6164 int j; 6165 6166 for (j = 0; j < AHD_NUM_LUNS; j++) { 6167 struct ahd_tmode_lstate *lstate; 6168 6169 lstate = tstate->enabled_luns[j]; 6170 if (lstate != NULL) { 6171 xpt_free_path(lstate->path); 6172 kfree(lstate); 6173 } 6174 } 6175 #endif 6176 kfree(tstate); 6177 } 6178 } 6179 #ifdef AHD_TARGET_MODE 6180 if (ahd->black_hole != NULL) { 6181 xpt_free_path(ahd->black_hole->path); 6182 kfree(ahd->black_hole); 6183 } 6184 #endif 6185 if (ahd->name != NULL) 6186 kfree(ahd->name); 6187 if (ahd->seep_config != NULL) 6188 kfree(ahd->seep_config); 6189 if (ahd->saved_stack != NULL) 6190 kfree(ahd->saved_stack); 6191 kfree(ahd); 6192 return; 6193 } 6194 6195 static void 6196 ahd_shutdown(void *arg) 6197 { 6198 struct ahd_softc *ahd; 6199 6200 ahd = (struct ahd_softc *)arg; 6201 6202 /* 6203 * Stop periodic timer callbacks. 6204 */ 6205 del_timer_sync(&ahd->stat_timer); 6206 6207 /* This will reset most registers to 0, but not all */ 6208 ahd_reset(ahd, /*reinit*/FALSE); 6209 } 6210 6211 /* 6212 * Reset the controller and record some information about it 6213 * that is only available just after a reset. If "reinit" is 6214 * non-zero, this reset occurred after initial configuration 6215 * and the caller requests that the chip be fully reinitialized 6216 * to a runable state. Chip interrupts are *not* enabled after 6217 * a reinitialization. The caller must enable interrupts via 6218 * ahd_intr_enable(). 6219 */ 6220 int 6221 ahd_reset(struct ahd_softc *ahd, int reinit) 6222 { 6223 u_int sxfrctl1; 6224 int wait; 6225 uint32_t cmd; 6226 6227 /* 6228 * Preserve the value of the SXFRCTL1 register for all channels. 6229 * It contains settings that affect termination and we don't want 6230 * to disturb the integrity of the bus. 6231 */ 6232 ahd_pause(ahd); 6233 ahd_update_modes(ahd); 6234 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6235 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 6236 6237 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 6238 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 6239 uint32_t mod_cmd; 6240 6241 /* 6242 * A4 Razor #632 6243 * During the assertion of CHIPRST, the chip 6244 * does not disable its parity logic prior to 6245 * the start of the reset. This may cause a 6246 * parity error to be detected and thus a 6247 * spurious SERR or PERR assertion. Disable 6248 * PERR and SERR responses during the CHIPRST. 6249 */ 6250 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN); 6251 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 6252 mod_cmd, /*bytes*/2); 6253 } 6254 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 6255 6256 /* 6257 * Ensure that the reset has finished. We delay 1000us 6258 * prior to reading the register to make sure the chip 6259 * has sufficiently completed its reset to handle register 6260 * accesses. 6261 */ 6262 wait = 1000; 6263 do { 6264 ahd_delay(1000); 6265 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 6266 6267 if (wait == 0) { 6268 printk("%s: WARNING - Failed chip reset! " 6269 "Trying to initialize anyway.\n", ahd_name(ahd)); 6270 } 6271 ahd_outb(ahd, HCNTRL, ahd->pause); 6272 6273 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 6274 /* 6275 * Clear any latched PCI error status and restore 6276 * previous SERR and PERR response enables. 6277 */ 6278 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 6279 0xFF, /*bytes*/1); 6280 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 6281 cmd, /*bytes*/2); 6282 } 6283 6284 /* 6285 * Mode should be SCSI after a chip reset, but lets 6286 * set it just to be safe. We touch the MODE_PTR 6287 * register directly so as to bypass the lazy update 6288 * code in ahd_set_modes(). 6289 */ 6290 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6291 ahd_outb(ahd, MODE_PTR, 6292 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 6293 6294 /* 6295 * Restore SXFRCTL1. 6296 * 6297 * We must always initialize STPWEN to 1 before we 6298 * restore the saved values. STPWEN is initialized 6299 * to a tri-state condition which can only be cleared 6300 * by turning it on. 6301 */ 6302 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 6303 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 6304 6305 /* Determine chip configuration */ 6306 ahd->features &= ~AHD_WIDE; 6307 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 6308 ahd->features |= AHD_WIDE; 6309 6310 /* 6311 * If a recovery action has forced a chip reset, 6312 * re-initialize the chip to our liking. 6313 */ 6314 if (reinit != 0) 6315 ahd_chip_init(ahd); 6316 6317 return (0); 6318 } 6319 6320 /* 6321 * Determine the number of SCBs available on the controller 6322 */ 6323 static int 6324 ahd_probe_scbs(struct ahd_softc *ahd) { 6325 int i; 6326 6327 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 6328 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 6329 for (i = 0; i < AHD_SCB_MAX; i++) { 6330 int j; 6331 6332 ahd_set_scbptr(ahd, i); 6333 ahd_outw(ahd, SCB_BASE, i); 6334 for (j = 2; j < 64; j++) 6335 ahd_outb(ahd, SCB_BASE+j, 0); 6336 /* Start out life as unallocated (needing an abort) */ 6337 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 6338 if (ahd_inw_scbram(ahd, SCB_BASE) != i) 6339 break; 6340 ahd_set_scbptr(ahd, 0); 6341 if (ahd_inw_scbram(ahd, SCB_BASE) != 0) 6342 break; 6343 } 6344 return (i); 6345 } 6346 6347 static void 6348 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 6349 { 6350 dma_addr_t *baddr; 6351 6352 baddr = (dma_addr_t *)arg; 6353 *baddr = segs->ds_addr; 6354 } 6355 6356 static void 6357 ahd_initialize_hscbs(struct ahd_softc *ahd) 6358 { 6359 int i; 6360 6361 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 6362 ahd_set_scbptr(ahd, i); 6363 6364 /* Clear the control byte. */ 6365 ahd_outb(ahd, SCB_CONTROL, 0); 6366 6367 /* Set the next pointer */ 6368 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 6369 } 6370 } 6371 6372 static int 6373 ahd_init_scbdata(struct ahd_softc *ahd) 6374 { 6375 struct scb_data *scb_data; 6376 int i; 6377 6378 scb_data = &ahd->scb_data; 6379 TAILQ_INIT(&scb_data->free_scbs); 6380 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 6381 LIST_INIT(&scb_data->free_scb_lists[i]); 6382 LIST_INIT(&scb_data->any_dev_free_scb_list); 6383 SLIST_INIT(&scb_data->hscb_maps); 6384 SLIST_INIT(&scb_data->sg_maps); 6385 SLIST_INIT(&scb_data->sense_maps); 6386 6387 /* Determine the number of hardware SCBs and initialize them */ 6388 scb_data->maxhscbs = ahd_probe_scbs(ahd); 6389 if (scb_data->maxhscbs == 0) { 6390 printk("%s: No SCB space found\n", ahd_name(ahd)); 6391 return (ENXIO); 6392 } 6393 6394 ahd_initialize_hscbs(ahd); 6395 6396 /* 6397 * Create our DMA tags. These tags define the kinds of device 6398 * accessible memory allocations and memory mappings we will 6399 * need to perform during normal operation. 6400 * 6401 * Unless we need to further restrict the allocation, we rely 6402 * on the restrictions of the parent dmat, hence the common 6403 * use of MAXADDR and MAXSIZE. 6404 */ 6405 6406 /* DMA tag for our hardware scb structures */ 6407 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 6408 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 6409 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 6410 /*highaddr*/BUS_SPACE_MAXADDR, 6411 /*filter*/NULL, /*filterarg*/NULL, 6412 PAGE_SIZE, /*nsegments*/1, 6413 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 6414 /*flags*/0, &scb_data->hscb_dmat) != 0) { 6415 goto error_exit; 6416 } 6417 6418 scb_data->init_level++; 6419 6420 /* DMA tag for our S/G structures. */ 6421 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8, 6422 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 6423 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 6424 /*highaddr*/BUS_SPACE_MAXADDR, 6425 /*filter*/NULL, /*filterarg*/NULL, 6426 ahd_sglist_allocsize(ahd), /*nsegments*/1, 6427 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 6428 /*flags*/0, &scb_data->sg_dmat) != 0) { 6429 goto error_exit; 6430 } 6431 #ifdef AHD_DEBUG 6432 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) 6433 printk("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd), 6434 ahd_sglist_allocsize(ahd)); 6435 #endif 6436 6437 scb_data->init_level++; 6438 6439 /* DMA tag for our sense buffers. We allocate in page sized chunks */ 6440 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 6441 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 6442 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 6443 /*highaddr*/BUS_SPACE_MAXADDR, 6444 /*filter*/NULL, /*filterarg*/NULL, 6445 PAGE_SIZE, /*nsegments*/1, 6446 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 6447 /*flags*/0, &scb_data->sense_dmat) != 0) { 6448 goto error_exit; 6449 } 6450 6451 scb_data->init_level++; 6452 6453 /* Perform initial CCB allocation */ 6454 ahd_alloc_scbs(ahd); 6455 6456 if (scb_data->numscbs == 0) { 6457 printk("%s: ahd_init_scbdata - " 6458 "Unable to allocate initial scbs\n", 6459 ahd_name(ahd)); 6460 goto error_exit; 6461 } 6462 6463 /* 6464 * Note that we were successful 6465 */ 6466 return (0); 6467 6468 error_exit: 6469 6470 return (ENOMEM); 6471 } 6472 6473 static struct scb * 6474 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 6475 { 6476 struct scb *scb; 6477 6478 /* 6479 * Look on the pending list. 6480 */ 6481 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6482 if (SCB_GET_TAG(scb) == tag) 6483 return (scb); 6484 } 6485 6486 /* 6487 * Then on all of the collision free lists. 6488 */ 6489 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 6490 struct scb *list_scb; 6491 6492 list_scb = scb; 6493 do { 6494 if (SCB_GET_TAG(list_scb) == tag) 6495 return (list_scb); 6496 list_scb = LIST_NEXT(list_scb, collision_links); 6497 } while (list_scb); 6498 } 6499 6500 /* 6501 * And finally on the generic free list. 6502 */ 6503 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 6504 if (SCB_GET_TAG(scb) == tag) 6505 return (scb); 6506 } 6507 6508 return (NULL); 6509 } 6510 6511 static void 6512 ahd_fini_scbdata(struct ahd_softc *ahd) 6513 { 6514 struct scb_data *scb_data; 6515 6516 scb_data = &ahd->scb_data; 6517 if (scb_data == NULL) 6518 return; 6519 6520 switch (scb_data->init_level) { 6521 default: 6522 case 7: 6523 { 6524 struct map_node *sns_map; 6525 6526 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 6527 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 6528 ahd_dmamap_unload(ahd, scb_data->sense_dmat, 6529 sns_map->dmamap); 6530 ahd_dmamem_free(ahd, scb_data->sense_dmat, 6531 sns_map->vaddr, sns_map->dmamap); 6532 kfree(sns_map); 6533 } 6534 ahd_dma_tag_destroy(ahd, scb_data->sense_dmat); 6535 } 6536 /* fall through */ 6537 case 6: 6538 { 6539 struct map_node *sg_map; 6540 6541 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 6542 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 6543 ahd_dmamap_unload(ahd, scb_data->sg_dmat, 6544 sg_map->dmamap); 6545 ahd_dmamem_free(ahd, scb_data->sg_dmat, 6546 sg_map->vaddr, sg_map->dmamap); 6547 kfree(sg_map); 6548 } 6549 ahd_dma_tag_destroy(ahd, scb_data->sg_dmat); 6550 } 6551 /* fall through */ 6552 case 5: 6553 { 6554 struct map_node *hscb_map; 6555 6556 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 6557 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 6558 ahd_dmamap_unload(ahd, scb_data->hscb_dmat, 6559 hscb_map->dmamap); 6560 ahd_dmamem_free(ahd, scb_data->hscb_dmat, 6561 hscb_map->vaddr, hscb_map->dmamap); 6562 kfree(hscb_map); 6563 } 6564 ahd_dma_tag_destroy(ahd, scb_data->hscb_dmat); 6565 /* FALLTHROUGH */ 6566 } 6567 case 4: 6568 case 3: 6569 case 2: 6570 case 1: 6571 case 0: 6572 break; 6573 } 6574 } 6575 6576 /* 6577 * DSP filter Bypass must be enabled until the first selection 6578 * after a change in bus mode (Razor #491 and #493). 6579 */ 6580 static void 6581 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 6582 { 6583 ahd_mode_state saved_modes; 6584 6585 saved_modes = ahd_save_modes(ahd); 6586 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 6587 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 6588 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 6589 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 6590 #ifdef AHD_DEBUG 6591 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6592 printk("%s: Setting up iocell workaround\n", ahd_name(ahd)); 6593 #endif 6594 ahd_restore_modes(ahd, saved_modes); 6595 ahd->flags &= ~AHD_HAD_FIRST_SEL; 6596 } 6597 6598 static void 6599 ahd_iocell_first_selection(struct ahd_softc *ahd) 6600 { 6601 ahd_mode_state saved_modes; 6602 u_int sblkctl; 6603 6604 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0) 6605 return; 6606 saved_modes = ahd_save_modes(ahd); 6607 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6608 sblkctl = ahd_inb(ahd, SBLKCTL); 6609 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 6610 #ifdef AHD_DEBUG 6611 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6612 printk("%s: iocell first selection\n", ahd_name(ahd)); 6613 #endif 6614 if ((sblkctl & ENAB40) != 0) { 6615 ahd_outb(ahd, DSPDATACTL, 6616 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 6617 #ifdef AHD_DEBUG 6618 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6619 printk("%s: BYPASS now disabled\n", ahd_name(ahd)); 6620 #endif 6621 } 6622 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 6623 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6624 ahd_restore_modes(ahd, saved_modes); 6625 ahd->flags |= AHD_HAD_FIRST_SEL; 6626 } 6627 6628 /*************************** SCB Management ***********************************/ 6629 static void 6630 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 6631 { 6632 struct scb_list *free_list; 6633 struct scb_tailq *free_tailq; 6634 struct scb *first_scb; 6635 6636 scb->flags |= SCB_ON_COL_LIST; 6637 AHD_SET_SCB_COL_IDX(scb, col_idx); 6638 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 6639 free_tailq = &ahd->scb_data.free_scbs; 6640 first_scb = LIST_FIRST(free_list); 6641 if (first_scb != NULL) { 6642 LIST_INSERT_AFTER(first_scb, scb, collision_links); 6643 } else { 6644 LIST_INSERT_HEAD(free_list, scb, collision_links); 6645 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 6646 } 6647 } 6648 6649 static void 6650 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 6651 { 6652 struct scb_list *free_list; 6653 struct scb_tailq *free_tailq; 6654 struct scb *first_scb; 6655 u_int col_idx; 6656 6657 scb->flags &= ~SCB_ON_COL_LIST; 6658 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 6659 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 6660 free_tailq = &ahd->scb_data.free_scbs; 6661 first_scb = LIST_FIRST(free_list); 6662 if (first_scb == scb) { 6663 struct scb *next_scb; 6664 6665 /* 6666 * Maintain order in the collision free 6667 * lists for fairness if this device has 6668 * other colliding tags active. 6669 */ 6670 next_scb = LIST_NEXT(scb, collision_links); 6671 if (next_scb != NULL) { 6672 TAILQ_INSERT_AFTER(free_tailq, scb, 6673 next_scb, links.tqe); 6674 } 6675 TAILQ_REMOVE(free_tailq, scb, links.tqe); 6676 } 6677 LIST_REMOVE(scb, collision_links); 6678 } 6679 6680 /* 6681 * Get a free scb. If there are none, see if we can allocate a new SCB. 6682 */ 6683 struct scb * 6684 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 6685 { 6686 struct scb *scb; 6687 int tries; 6688 6689 tries = 0; 6690 look_again: 6691 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 6692 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 6693 ahd_rem_col_list(ahd, scb); 6694 goto found; 6695 } 6696 } 6697 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 6698 6699 if (tries++ != 0) 6700 return (NULL); 6701 ahd_alloc_scbs(ahd); 6702 goto look_again; 6703 } 6704 LIST_REMOVE(scb, links.le); 6705 if (col_idx != AHD_NEVER_COL_IDX 6706 && (scb->col_scb != NULL) 6707 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 6708 LIST_REMOVE(scb->col_scb, links.le); 6709 ahd_add_col_list(ahd, scb->col_scb, col_idx); 6710 } 6711 found: 6712 scb->flags |= SCB_ACTIVE; 6713 return (scb); 6714 } 6715 6716 /* 6717 * Return an SCB resource to the free list. 6718 */ 6719 void 6720 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 6721 { 6722 /* Clean up for the next user */ 6723 scb->flags = SCB_FLAG_NONE; 6724 scb->hscb->control = 0; 6725 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; 6726 6727 if (scb->col_scb == NULL) { 6728 6729 /* 6730 * No collision possible. Just free normally. 6731 */ 6732 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 6733 scb, links.le); 6734 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 6735 6736 /* 6737 * The SCB we might have collided with is on 6738 * a free collision list. Put both SCBs on 6739 * the generic list. 6740 */ 6741 ahd_rem_col_list(ahd, scb->col_scb); 6742 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 6743 scb, links.le); 6744 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 6745 scb->col_scb, links.le); 6746 } else if ((scb->col_scb->flags 6747 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 6748 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 6749 6750 /* 6751 * The SCB we might collide with on the next allocation 6752 * is still active in a non-packetized, tagged, context. 6753 * Put us on the SCB collision list. 6754 */ 6755 ahd_add_col_list(ahd, scb, 6756 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 6757 } else { 6758 /* 6759 * The SCB we might collide with on the next allocation 6760 * is either active in a packetized context, or free. 6761 * Since we can't collide, put this SCB on the generic 6762 * free list. 6763 */ 6764 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 6765 scb, links.le); 6766 } 6767 6768 ahd_platform_scb_free(ahd, scb); 6769 } 6770 6771 static void 6772 ahd_alloc_scbs(struct ahd_softc *ahd) 6773 { 6774 struct scb_data *scb_data; 6775 struct scb *next_scb; 6776 struct hardware_scb *hscb; 6777 struct map_node *hscb_map; 6778 struct map_node *sg_map; 6779 struct map_node *sense_map; 6780 uint8_t *segs; 6781 uint8_t *sense_data; 6782 dma_addr_t hscb_busaddr; 6783 dma_addr_t sg_busaddr; 6784 dma_addr_t sense_busaddr; 6785 int newcount; 6786 int i; 6787 6788 scb_data = &ahd->scb_data; 6789 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 6790 /* Can't allocate any more */ 6791 return; 6792 6793 if (scb_data->scbs_left != 0) { 6794 int offset; 6795 6796 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 6797 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 6798 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 6799 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 6800 } else { 6801 hscb_map = kmalloc(sizeof(*hscb_map), GFP_ATOMIC); 6802 6803 if (hscb_map == NULL) 6804 return; 6805 6806 /* Allocate the next batch of hardware SCBs */ 6807 if (ahd_dmamem_alloc(ahd, scb_data->hscb_dmat, 6808 (void **)&hscb_map->vaddr, 6809 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) { 6810 kfree(hscb_map); 6811 return; 6812 } 6813 6814 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 6815 6816 ahd_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap, 6817 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 6818 &hscb_map->physaddr, /*flags*/0); 6819 6820 hscb = (struct hardware_scb *)hscb_map->vaddr; 6821 hscb_busaddr = hscb_map->physaddr; 6822 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 6823 } 6824 6825 if (scb_data->sgs_left != 0) { 6826 int offset; 6827 6828 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) 6829 - scb_data->sgs_left) * ahd_sglist_size(ahd); 6830 sg_map = SLIST_FIRST(&scb_data->sg_maps); 6831 segs = sg_map->vaddr + offset; 6832 sg_busaddr = sg_map->physaddr + offset; 6833 } else { 6834 sg_map = kmalloc(sizeof(*sg_map), GFP_ATOMIC); 6835 6836 if (sg_map == NULL) 6837 return; 6838 6839 /* Allocate the next batch of S/G lists */ 6840 if (ahd_dmamem_alloc(ahd, scb_data->sg_dmat, 6841 (void **)&sg_map->vaddr, 6842 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) { 6843 kfree(sg_map); 6844 return; 6845 } 6846 6847 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 6848 6849 ahd_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap, 6850 sg_map->vaddr, ahd_sglist_allocsize(ahd), 6851 ahd_dmamap_cb, &sg_map->physaddr, /*flags*/0); 6852 6853 segs = sg_map->vaddr; 6854 sg_busaddr = sg_map->physaddr; 6855 scb_data->sgs_left = 6856 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 6857 #ifdef AHD_DEBUG 6858 if (ahd_debug & AHD_SHOW_MEMORY) 6859 printk("Mapped SG data\n"); 6860 #endif 6861 } 6862 6863 if (scb_data->sense_left != 0) { 6864 int offset; 6865 6866 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 6867 sense_map = SLIST_FIRST(&scb_data->sense_maps); 6868 sense_data = sense_map->vaddr + offset; 6869 sense_busaddr = sense_map->physaddr + offset; 6870 } else { 6871 sense_map = kmalloc(sizeof(*sense_map), GFP_ATOMIC); 6872 6873 if (sense_map == NULL) 6874 return; 6875 6876 /* Allocate the next batch of sense buffers */ 6877 if (ahd_dmamem_alloc(ahd, scb_data->sense_dmat, 6878 (void **)&sense_map->vaddr, 6879 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) { 6880 kfree(sense_map); 6881 return; 6882 } 6883 6884 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 6885 6886 ahd_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap, 6887 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 6888 &sense_map->physaddr, /*flags*/0); 6889 6890 sense_data = sense_map->vaddr; 6891 sense_busaddr = sense_map->physaddr; 6892 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 6893 #ifdef AHD_DEBUG 6894 if (ahd_debug & AHD_SHOW_MEMORY) 6895 printk("Mapped sense data\n"); 6896 #endif 6897 } 6898 6899 newcount = min(scb_data->sense_left, scb_data->scbs_left); 6900 newcount = min(newcount, scb_data->sgs_left); 6901 newcount = min(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 6902 for (i = 0; i < newcount; i++) { 6903 struct scb_platform_data *pdata; 6904 u_int col_tag; 6905 6906 next_scb = kmalloc(sizeof(*next_scb), GFP_ATOMIC); 6907 if (next_scb == NULL) 6908 break; 6909 6910 pdata = kmalloc(sizeof(*pdata), GFP_ATOMIC); 6911 if (pdata == NULL) { 6912 kfree(next_scb); 6913 break; 6914 } 6915 next_scb->platform_data = pdata; 6916 next_scb->hscb_map = hscb_map; 6917 next_scb->sg_map = sg_map; 6918 next_scb->sense_map = sense_map; 6919 next_scb->sg_list = segs; 6920 next_scb->sense_data = sense_data; 6921 next_scb->sense_busaddr = sense_busaddr; 6922 memset(hscb, 0, sizeof(*hscb)); 6923 next_scb->hscb = hscb; 6924 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 6925 6926 /* 6927 * The sequencer always starts with the second entry. 6928 * The first entry is embedded in the scb. 6929 */ 6930 next_scb->sg_list_busaddr = sg_busaddr; 6931 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 6932 next_scb->sg_list_busaddr 6933 += sizeof(struct ahd_dma64_seg); 6934 else 6935 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 6936 next_scb->ahd_softc = ahd; 6937 next_scb->flags = SCB_FLAG_NONE; 6938 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 6939 col_tag = scb_data->numscbs ^ 0x100; 6940 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 6941 if (next_scb->col_scb != NULL) 6942 next_scb->col_scb->col_scb = next_scb; 6943 ahd_free_scb(ahd, next_scb); 6944 hscb++; 6945 hscb_busaddr += sizeof(*hscb); 6946 segs += ahd_sglist_size(ahd); 6947 sg_busaddr += ahd_sglist_size(ahd); 6948 sense_data += AHD_SENSE_BUFSIZE; 6949 sense_busaddr += AHD_SENSE_BUFSIZE; 6950 scb_data->numscbs++; 6951 scb_data->sense_left--; 6952 scb_data->scbs_left--; 6953 scb_data->sgs_left--; 6954 } 6955 } 6956 6957 void 6958 ahd_controller_info(struct ahd_softc *ahd, char *buf) 6959 { 6960 const char *speed; 6961 const char *type; 6962 int len; 6963 6964 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 6965 buf += len; 6966 6967 speed = "Ultra320 "; 6968 if ((ahd->features & AHD_WIDE) != 0) { 6969 type = "Wide "; 6970 } else { 6971 type = "Single "; 6972 } 6973 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 6974 speed, type, ahd->channel, ahd->our_id); 6975 buf += len; 6976 6977 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 6978 ahd->scb_data.maxhscbs); 6979 } 6980 6981 static const char *channel_strings[] = { 6982 "Primary Low", 6983 "Primary High", 6984 "Secondary Low", 6985 "Secondary High" 6986 }; 6987 6988 static const char *termstat_strings[] = { 6989 "Terminated Correctly", 6990 "Over Terminated", 6991 "Under Terminated", 6992 "Not Configured" 6993 }; 6994 6995 /***************************** Timer Facilities *******************************/ 6996 static void 6997 ahd_timer_reset(struct timer_list *timer, int usec) 6998 { 6999 del_timer(timer); 7000 timer->expires = jiffies + (usec * HZ)/1000000; 7001 add_timer(timer); 7002 } 7003 7004 /* 7005 * Start the board, ready for normal operation 7006 */ 7007 int 7008 ahd_init(struct ahd_softc *ahd) 7009 { 7010 uint8_t *next_vaddr; 7011 dma_addr_t next_baddr; 7012 size_t driver_data_size; 7013 int i; 7014 int error; 7015 u_int warn_user; 7016 uint8_t current_sensing; 7017 uint8_t fstat; 7018 7019 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7020 7021 ahd->stack_size = ahd_probe_stack_size(ahd); 7022 ahd->saved_stack = kmalloc_array(ahd->stack_size, sizeof(uint16_t), 7023 GFP_ATOMIC); 7024 if (ahd->saved_stack == NULL) 7025 return (ENOMEM); 7026 7027 /* 7028 * Verify that the compiler hasn't over-aggressively 7029 * padded important structures. 7030 */ 7031 if (sizeof(struct hardware_scb) != 64) 7032 panic("Hardware SCB size is incorrect"); 7033 7034 #ifdef AHD_DEBUG 7035 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 7036 ahd->flags |= AHD_SEQUENCER_DEBUG; 7037 #endif 7038 7039 /* 7040 * Default to allowing initiator operations. 7041 */ 7042 ahd->flags |= AHD_INITIATORROLE; 7043 7044 /* 7045 * Only allow target mode features if this unit has them enabled. 7046 */ 7047 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 7048 ahd->features &= ~AHD_TARGETMODE; 7049 7050 ahd->init_level++; 7051 7052 /* 7053 * DMA tag for our command fifos and other data in system memory 7054 * the card's sequencer must be able to access. For initiator 7055 * roles, we need to allocate space for the qoutfifo. When providing 7056 * for the target mode role, we must additionally provide space for 7057 * the incoming target command fifo. 7058 */ 7059 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo) 7060 + sizeof(struct hardware_scb); 7061 if ((ahd->features & AHD_TARGETMODE) != 0) 7062 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 7063 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 7064 driver_data_size += PKT_OVERRUN_BUFSIZE; 7065 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 7066 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 7067 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 7068 /*highaddr*/BUS_SPACE_MAXADDR, 7069 /*filter*/NULL, /*filterarg*/NULL, 7070 driver_data_size, 7071 /*nsegments*/1, 7072 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 7073 /*flags*/0, &ahd->shared_data_dmat) != 0) { 7074 return (ENOMEM); 7075 } 7076 7077 ahd->init_level++; 7078 7079 /* Allocation of driver data */ 7080 if (ahd_dmamem_alloc(ahd, ahd->shared_data_dmat, 7081 (void **)&ahd->shared_data_map.vaddr, 7082 BUS_DMA_NOWAIT, 7083 &ahd->shared_data_map.dmamap) != 0) { 7084 return (ENOMEM); 7085 } 7086 7087 ahd->init_level++; 7088 7089 /* And permanently map it in */ 7090 ahd_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap, 7091 ahd->shared_data_map.vaddr, driver_data_size, 7092 ahd_dmamap_cb, &ahd->shared_data_map.physaddr, 7093 /*flags*/0); 7094 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr; 7095 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 7096 next_baddr = ahd->shared_data_map.physaddr 7097 + AHD_QOUT_SIZE*sizeof(struct ahd_completion); 7098 if ((ahd->features & AHD_TARGETMODE) != 0) { 7099 ahd->targetcmds = (struct target_cmd *)next_vaddr; 7100 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 7101 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 7102 } 7103 7104 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 7105 ahd->overrun_buf = next_vaddr; 7106 next_vaddr += PKT_OVERRUN_BUFSIZE; 7107 next_baddr += PKT_OVERRUN_BUFSIZE; 7108 } 7109 7110 /* 7111 * We need one SCB to serve as the "next SCB". Since the 7112 * tag identifier in this SCB will never be used, there is 7113 * no point in using a valid HSCB tag from an SCB pulled from 7114 * the standard free pool. So, we allocate this "sentinel" 7115 * specially from the DMA safe memory chunk used for the QOUTFIFO. 7116 */ 7117 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 7118 ahd->next_queued_hscb_map = &ahd->shared_data_map; 7119 ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr); 7120 7121 ahd->init_level++; 7122 7123 /* Allocate SCB data now that buffer_dmat is initialized */ 7124 if (ahd_init_scbdata(ahd) != 0) 7125 return (ENOMEM); 7126 7127 if ((ahd->flags & AHD_INITIATORROLE) == 0) 7128 ahd->flags &= ~AHD_RESET_BUS_A; 7129 7130 /* 7131 * Before committing these settings to the chip, give 7132 * the OSM one last chance to modify our configuration. 7133 */ 7134 ahd_platform_init(ahd); 7135 7136 /* Bring up the chip. */ 7137 ahd_chip_init(ahd); 7138 7139 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7140 7141 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 7142 goto init_done; 7143 7144 /* 7145 * Verify termination based on current draw and 7146 * warn user if the bus is over/under terminated. 7147 */ 7148 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 7149 CURSENSE_ENB); 7150 if (error != 0) { 7151 printk("%s: current sensing timeout 1\n", ahd_name(ahd)); 7152 goto init_done; 7153 } 7154 for (i = 20, fstat = FLX_FSTAT_BUSY; 7155 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 7156 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 7157 if (error != 0) { 7158 printk("%s: current sensing timeout 2\n", 7159 ahd_name(ahd)); 7160 goto init_done; 7161 } 7162 } 7163 if (i == 0) { 7164 printk("%s: Timedout during current-sensing test\n", 7165 ahd_name(ahd)); 7166 goto init_done; 7167 } 7168 7169 /* Latch Current Sensing status. */ 7170 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 7171 if (error != 0) { 7172 printk("%s: current sensing timeout 3\n", ahd_name(ahd)); 7173 goto init_done; 7174 } 7175 7176 /* Diable current sensing. */ 7177 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 7178 7179 #ifdef AHD_DEBUG 7180 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 7181 printk("%s: current_sensing == 0x%x\n", 7182 ahd_name(ahd), current_sensing); 7183 } 7184 #endif 7185 warn_user = 0; 7186 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 7187 u_int term_stat; 7188 7189 term_stat = (current_sensing & FLX_CSTAT_MASK); 7190 switch (term_stat) { 7191 case FLX_CSTAT_OVER: 7192 case FLX_CSTAT_UNDER: 7193 warn_user++; 7194 /* fall through */ 7195 case FLX_CSTAT_INVALID: 7196 case FLX_CSTAT_OKAY: 7197 if (warn_user == 0 && bootverbose == 0) 7198 break; 7199 printk("%s: %s Channel %s\n", ahd_name(ahd), 7200 channel_strings[i], termstat_strings[term_stat]); 7201 break; 7202 } 7203 } 7204 if (warn_user) { 7205 printk("%s: WARNING. Termination is not configured correctly.\n" 7206 "%s: WARNING. SCSI bus operations may FAIL.\n", 7207 ahd_name(ahd), ahd_name(ahd)); 7208 } 7209 init_done: 7210 ahd_restart(ahd); 7211 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US); 7212 return (0); 7213 } 7214 7215 /* 7216 * (Re)initialize chip state after a chip reset. 7217 */ 7218 static void 7219 ahd_chip_init(struct ahd_softc *ahd) 7220 { 7221 uint32_t busaddr; 7222 u_int sxfrctl1; 7223 u_int scsiseq_template; 7224 u_int wait; 7225 u_int i; 7226 u_int target; 7227 7228 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7229 /* 7230 * Take the LED out of diagnostic mode 7231 */ 7232 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 7233 7234 /* 7235 * Return HS_MAILBOX to its default value. 7236 */ 7237 ahd->hs_mailbox = 0; 7238 ahd_outb(ahd, HS_MAILBOX, 0); 7239 7240 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 7241 ahd_outb(ahd, IOWNID, ahd->our_id); 7242 ahd_outb(ahd, TOWNID, ahd->our_id); 7243 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 7244 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 7245 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 7246 && (ahd->seltime != STIMESEL_MIN)) { 7247 /* 7248 * The selection timer duration is twice as long 7249 * as it should be. Halve it by adding "1" to 7250 * the user specified setting. 7251 */ 7252 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 7253 } else { 7254 sxfrctl1 |= ahd->seltime; 7255 } 7256 7257 ahd_outb(ahd, SXFRCTL0, DFON); 7258 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 7259 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 7260 7261 /* 7262 * Now that termination is set, wait for up 7263 * to 500ms for our transceivers to settle. If 7264 * the adapter does not have a cable attached, 7265 * the transceivers may never settle, so don't 7266 * complain if we fail here. 7267 */ 7268 for (wait = 10000; 7269 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 7270 wait--) 7271 ahd_delay(100); 7272 7273 /* Clear any false bus resets due to the transceivers settling */ 7274 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7275 ahd_outb(ahd, CLRINT, CLRSCSIINT); 7276 7277 /* Initialize mode specific S/G state. */ 7278 for (i = 0; i < 2; i++) { 7279 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 7280 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 7281 ahd_outb(ahd, SG_STATE, 0); 7282 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 7283 ahd_outb(ahd, SEQIMODE, 7284 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 7285 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 7286 } 7287 7288 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 7289 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 7290 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 7291 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 7292 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 7293 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 7294 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 7295 } else { 7296 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 7297 } 7298 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 7299 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 7300 /* 7301 * Do not issue a target abort when a split completion 7302 * error occurs. Let our PCIX interrupt handler deal 7303 * with it instead. H2A4 Razor #625 7304 */ 7305 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 7306 7307 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 7308 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 7309 7310 /* 7311 * Tweak IOCELL settings. 7312 */ 7313 if ((ahd->flags & AHD_HP_BOARD) != 0) { 7314 for (i = 0; i < NUMDSPS; i++) { 7315 ahd_outb(ahd, DSPSELECT, i); 7316 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 7317 } 7318 #ifdef AHD_DEBUG 7319 if ((ahd_debug & AHD_SHOW_MISC) != 0) 7320 printk("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 7321 WRTBIASCTL_HP_DEFAULT); 7322 #endif 7323 } 7324 ahd_setup_iocell_workaround(ahd); 7325 7326 /* 7327 * Enable LQI Manager interrupts. 7328 */ 7329 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 7330 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 7331 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 7332 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 7333 /* 7334 * We choose to have the sequencer catch LQOPHCHGINPKT errors 7335 * manually for the command phase at the start of a packetized 7336 * selection case. ENLQOBUSFREE should be made redundant by 7337 * the BUSFREE interrupt, but it seems that some LQOBUSFREE 7338 * events fail to assert the BUSFREE interrupt so we must 7339 * also enable LQOBUSFREE interrupts. 7340 */ 7341 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE); 7342 7343 /* 7344 * Setup sequencer interrupt handlers. 7345 */ 7346 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 7347 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 7348 7349 /* 7350 * Setup SCB Offset registers. 7351 */ 7352 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 7353 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 7354 pkt_long_lun)); 7355 } else { 7356 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 7357 } 7358 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 7359 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 7360 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 7361 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 7362 shared_data.idata.cdb)); 7363 ahd_outb(ahd, QNEXTPTR, 7364 offsetof(struct hardware_scb, next_hscb_busaddr)); 7365 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 7366 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 7367 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 7368 ahd_outb(ahd, LUNLEN, 7369 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 7370 } else { 7371 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN); 7372 } 7373 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 7374 ahd_outb(ahd, MAXCMD, 0xFF); 7375 ahd_outb(ahd, SCBAUTOPTR, 7376 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 7377 7378 /* We haven't been enabled for target mode yet. */ 7379 ahd_outb(ahd, MULTARGID, 0); 7380 ahd_outb(ahd, MULTARGID + 1, 0); 7381 7382 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7383 /* Initialize the negotiation table. */ 7384 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 7385 /* 7386 * Clear the spare bytes in the neg table to avoid 7387 * spurious parity errors. 7388 */ 7389 for (target = 0; target < AHD_NUM_TARGETS; target++) { 7390 ahd_outb(ahd, NEGOADDR, target); 7391 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 7392 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 7393 ahd_outb(ahd, ANNEXDAT, 0); 7394 } 7395 } 7396 for (target = 0; target < AHD_NUM_TARGETS; target++) { 7397 struct ahd_devinfo devinfo; 7398 struct ahd_initiator_tinfo *tinfo; 7399 struct ahd_tmode_tstate *tstate; 7400 7401 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 7402 target, &tstate); 7403 ahd_compile_devinfo(&devinfo, ahd->our_id, 7404 target, CAM_LUN_WILDCARD, 7405 'A', ROLE_INITIATOR); 7406 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 7407 } 7408 7409 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 7410 ahd_outb(ahd, CLRINT, CLRSCSIINT); 7411 7412 #ifdef NEEDS_MORE_TESTING 7413 /* 7414 * Always enable abort on incoming L_Qs if this feature is 7415 * supported. We use this to catch invalid SCB references. 7416 */ 7417 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 7418 ahd_outb(ahd, LQCTL1, ABORTPENDING); 7419 else 7420 #endif 7421 ahd_outb(ahd, LQCTL1, 0); 7422 7423 /* All of our queues are empty */ 7424 ahd->qoutfifonext = 0; 7425 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID; 7426 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID); 7427 for (i = 0; i < AHD_QOUT_SIZE; i++) 7428 ahd->qoutfifo[i].valid_tag = 0; 7429 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 7430 7431 ahd->qinfifonext = 0; 7432 for (i = 0; i < AHD_QIN_SIZE; i++) 7433 ahd->qinfifo[i] = SCB_LIST_NULL; 7434 7435 if ((ahd->features & AHD_TARGETMODE) != 0) { 7436 /* All target command blocks start out invalid. */ 7437 for (i = 0; i < AHD_TMODE_CMDS; i++) 7438 ahd->targetcmds[i].cmd_valid = 0; 7439 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 7440 ahd->tqinfifonext = 1; 7441 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 7442 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 7443 } 7444 7445 /* Initialize Scratch Ram. */ 7446 ahd_outb(ahd, SEQ_FLAGS, 0); 7447 ahd_outb(ahd, SEQ_FLAGS2, 0); 7448 7449 /* We don't have any waiting selections */ 7450 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 7451 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 7452 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL); 7453 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF); 7454 for (i = 0; i < AHD_NUM_TARGETS; i++) 7455 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 7456 7457 /* 7458 * Nobody is waiting to be DMAed into the QOUTFIFO. 7459 */ 7460 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 7461 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 7462 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 7463 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL); 7464 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL); 7465 7466 /* 7467 * The Freeze Count is 0. 7468 */ 7469 ahd->qfreeze_cnt = 0; 7470 ahd_outw(ahd, QFREEZE_COUNT, 0); 7471 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0); 7472 7473 /* 7474 * Tell the sequencer where it can find our arrays in memory. 7475 */ 7476 busaddr = ahd->shared_data_map.physaddr; 7477 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr); 7478 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr); 7479 7480 /* 7481 * Setup the allowed SCSI Sequences based on operational mode. 7482 * If we are a target, we'll enable select in operations once 7483 * we've had a lun enabled. 7484 */ 7485 scsiseq_template = ENAUTOATNP; 7486 if ((ahd->flags & AHD_INITIATORROLE) != 0) 7487 scsiseq_template |= ENRSELI; 7488 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 7489 7490 /* There are no busy SCBs yet. */ 7491 for (target = 0; target < AHD_NUM_TARGETS; target++) { 7492 int lun; 7493 7494 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 7495 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 7496 } 7497 7498 /* 7499 * Initialize the group code to command length table. 7500 * Vendor Unique codes are set to 0 so we only capture 7501 * the first byte of the cdb. These can be overridden 7502 * when target mode is enabled. 7503 */ 7504 ahd_outb(ahd, CMDSIZE_TABLE, 5); 7505 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 7506 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 7507 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 7508 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 7509 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 7510 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 7511 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 7512 7513 /* Tell the sequencer of our initial queue positions */ 7514 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7515 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 7516 ahd->qinfifonext = 0; 7517 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7518 ahd_set_hescb_qoff(ahd, 0); 7519 ahd_set_snscb_qoff(ahd, 0); 7520 ahd_set_sescb_qoff(ahd, 0); 7521 ahd_set_sdscb_qoff(ahd, 0); 7522 7523 /* 7524 * Tell the sequencer which SCB will be the next one it receives. 7525 */ 7526 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 7527 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 7528 7529 /* 7530 * Default to coalescing disabled. 7531 */ 7532 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); 7533 ahd_outw(ahd, CMDS_PENDING, 0); 7534 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, 7535 ahd->int_coalescing_maxcmds, 7536 ahd->int_coalescing_mincmds); 7537 ahd_enable_coalescing(ahd, FALSE); 7538 7539 ahd_loadseq(ahd); 7540 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7541 7542 if (ahd->features & AHD_AIC79XXB_SLOWCRC) { 7543 u_int negodat3 = ahd_inb(ahd, NEGCONOPTS); 7544 7545 negodat3 |= ENSLOWCRC; 7546 ahd_outb(ahd, NEGCONOPTS, negodat3); 7547 negodat3 = ahd_inb(ahd, NEGCONOPTS); 7548 if (!(negodat3 & ENSLOWCRC)) 7549 printk("aic79xx: failed to set the SLOWCRC bit\n"); 7550 else 7551 printk("aic79xx: SLOWCRC bit set\n"); 7552 } 7553 } 7554 7555 /* 7556 * Setup default device and controller settings. 7557 * This should only be called if our probe has 7558 * determined that no configuration data is available. 7559 */ 7560 int 7561 ahd_default_config(struct ahd_softc *ahd) 7562 { 7563 int targ; 7564 7565 ahd->our_id = 7; 7566 7567 /* 7568 * Allocate a tstate to house information for our 7569 * initiator presence on the bus as well as the user 7570 * data for any target mode initiator. 7571 */ 7572 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 7573 printk("%s: unable to allocate ahd_tmode_tstate. " 7574 "Failing attach\n", ahd_name(ahd)); 7575 return (ENOMEM); 7576 } 7577 7578 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 7579 struct ahd_devinfo devinfo; 7580 struct ahd_initiator_tinfo *tinfo; 7581 struct ahd_tmode_tstate *tstate; 7582 uint16_t target_mask; 7583 7584 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 7585 targ, &tstate); 7586 /* 7587 * We support SPC2 and SPI4. 7588 */ 7589 tinfo->user.protocol_version = 4; 7590 tinfo->user.transport_version = 4; 7591 7592 target_mask = 0x01 << targ; 7593 ahd->user_discenable |= target_mask; 7594 tstate->discenable |= target_mask; 7595 ahd->user_tagenable |= target_mask; 7596 #ifdef AHD_FORCE_160 7597 tinfo->user.period = AHD_SYNCRATE_DT; 7598 #else 7599 tinfo->user.period = AHD_SYNCRATE_160; 7600 #endif 7601 tinfo->user.offset = MAX_OFFSET; 7602 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM 7603 | MSG_EXT_PPR_WR_FLOW 7604 | MSG_EXT_PPR_HOLD_MCS 7605 | MSG_EXT_PPR_IU_REQ 7606 | MSG_EXT_PPR_QAS_REQ 7607 | MSG_EXT_PPR_DT_REQ; 7608 if ((ahd->features & AHD_RTI) != 0) 7609 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 7610 7611 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 7612 7613 /* 7614 * Start out Async/Narrow/Untagged and with 7615 * conservative protocol support. 7616 */ 7617 tinfo->goal.protocol_version = 2; 7618 tinfo->goal.transport_version = 2; 7619 tinfo->curr.protocol_version = 2; 7620 tinfo->curr.transport_version = 2; 7621 ahd_compile_devinfo(&devinfo, ahd->our_id, 7622 targ, CAM_LUN_WILDCARD, 7623 'A', ROLE_INITIATOR); 7624 tstate->tagenable &= ~target_mask; 7625 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7626 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 7627 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 7628 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 7629 /*paused*/TRUE); 7630 } 7631 return (0); 7632 } 7633 7634 /* 7635 * Parse device configuration information. 7636 */ 7637 int 7638 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 7639 { 7640 int targ; 7641 int max_targ; 7642 7643 max_targ = sc->max_targets & CFMAXTARG; 7644 ahd->our_id = sc->brtime_id & CFSCSIID; 7645 7646 /* 7647 * Allocate a tstate to house information for our 7648 * initiator presence on the bus as well as the user 7649 * data for any target mode initiator. 7650 */ 7651 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 7652 printk("%s: unable to allocate ahd_tmode_tstate. " 7653 "Failing attach\n", ahd_name(ahd)); 7654 return (ENOMEM); 7655 } 7656 7657 for (targ = 0; targ < max_targ; targ++) { 7658 struct ahd_devinfo devinfo; 7659 struct ahd_initiator_tinfo *tinfo; 7660 struct ahd_transinfo *user_tinfo; 7661 struct ahd_tmode_tstate *tstate; 7662 uint16_t target_mask; 7663 7664 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 7665 targ, &tstate); 7666 user_tinfo = &tinfo->user; 7667 7668 /* 7669 * We support SPC2 and SPI4. 7670 */ 7671 tinfo->user.protocol_version = 4; 7672 tinfo->user.transport_version = 4; 7673 7674 target_mask = 0x01 << targ; 7675 ahd->user_discenable &= ~target_mask; 7676 tstate->discenable &= ~target_mask; 7677 ahd->user_tagenable &= ~target_mask; 7678 if (sc->device_flags[targ] & CFDISC) { 7679 tstate->discenable |= target_mask; 7680 ahd->user_discenable |= target_mask; 7681 ahd->user_tagenable |= target_mask; 7682 } else { 7683 /* 7684 * Cannot be packetized without disconnection. 7685 */ 7686 sc->device_flags[targ] &= ~CFPACKETIZED; 7687 } 7688 7689 user_tinfo->ppr_options = 0; 7690 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 7691 if (user_tinfo->period < CFXFER_ASYNC) { 7692 if (user_tinfo->period <= AHD_PERIOD_10MHz) 7693 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 7694 user_tinfo->offset = MAX_OFFSET; 7695 } else { 7696 user_tinfo->offset = 0; 7697 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 7698 } 7699 #ifdef AHD_FORCE_160 7700 if (user_tinfo->period <= AHD_SYNCRATE_160) 7701 user_tinfo->period = AHD_SYNCRATE_DT; 7702 #endif 7703 7704 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 7705 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM 7706 | MSG_EXT_PPR_WR_FLOW 7707 | MSG_EXT_PPR_HOLD_MCS 7708 | MSG_EXT_PPR_IU_REQ; 7709 if ((ahd->features & AHD_RTI) != 0) 7710 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 7711 } 7712 7713 if ((sc->device_flags[targ] & CFQAS) != 0) 7714 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 7715 7716 if ((sc->device_flags[targ] & CFWIDEB) != 0) 7717 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 7718 else 7719 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 7720 #ifdef AHD_DEBUG 7721 if ((ahd_debug & AHD_SHOW_MISC) != 0) 7722 printk("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 7723 user_tinfo->period, user_tinfo->offset, 7724 user_tinfo->ppr_options); 7725 #endif 7726 /* 7727 * Start out Async/Narrow/Untagged and with 7728 * conservative protocol support. 7729 */ 7730 tstate->tagenable &= ~target_mask; 7731 tinfo->goal.protocol_version = 2; 7732 tinfo->goal.transport_version = 2; 7733 tinfo->curr.protocol_version = 2; 7734 tinfo->curr.transport_version = 2; 7735 ahd_compile_devinfo(&devinfo, ahd->our_id, 7736 targ, CAM_LUN_WILDCARD, 7737 'A', ROLE_INITIATOR); 7738 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7739 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 7740 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 7741 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 7742 /*paused*/TRUE); 7743 } 7744 7745 ahd->flags &= ~AHD_SPCHK_ENB_A; 7746 if (sc->bios_control & CFSPARITY) 7747 ahd->flags |= AHD_SPCHK_ENB_A; 7748 7749 ahd->flags &= ~AHD_RESET_BUS_A; 7750 if (sc->bios_control & CFRESETB) 7751 ahd->flags |= AHD_RESET_BUS_A; 7752 7753 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 7754 if (sc->bios_control & CFEXTEND) 7755 ahd->flags |= AHD_EXTENDED_TRANS_A; 7756 7757 ahd->flags &= ~AHD_BIOS_ENABLED; 7758 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 7759 ahd->flags |= AHD_BIOS_ENABLED; 7760 7761 ahd->flags &= ~AHD_STPWLEVEL_A; 7762 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 7763 ahd->flags |= AHD_STPWLEVEL_A; 7764 7765 return (0); 7766 } 7767 7768 /* 7769 * Parse device configuration information. 7770 */ 7771 int 7772 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) 7773 { 7774 int error; 7775 7776 error = ahd_verify_vpd_cksum(vpd); 7777 if (error == 0) 7778 return (EINVAL); 7779 if ((vpd->bios_flags & VPDBOOTHOST) != 0) 7780 ahd->flags |= AHD_BOOT_CHANNEL; 7781 return (0); 7782 } 7783 7784 void 7785 ahd_intr_enable(struct ahd_softc *ahd, int enable) 7786 { 7787 u_int hcntrl; 7788 7789 hcntrl = ahd_inb(ahd, HCNTRL); 7790 hcntrl &= ~INTEN; 7791 ahd->pause &= ~INTEN; 7792 ahd->unpause &= ~INTEN; 7793 if (enable) { 7794 hcntrl |= INTEN; 7795 ahd->pause |= INTEN; 7796 ahd->unpause |= INTEN; 7797 } 7798 ahd_outb(ahd, HCNTRL, hcntrl); 7799 } 7800 7801 static void 7802 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 7803 u_int mincmds) 7804 { 7805 if (timer > AHD_TIMER_MAX_US) 7806 timer = AHD_TIMER_MAX_US; 7807 ahd->int_coalescing_timer = timer; 7808 7809 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) 7810 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; 7811 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) 7812 mincmds = AHD_INT_COALESCING_MINCMDS_MAX; 7813 ahd->int_coalescing_maxcmds = maxcmds; 7814 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); 7815 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); 7816 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); 7817 } 7818 7819 static void 7820 ahd_enable_coalescing(struct ahd_softc *ahd, int enable) 7821 { 7822 7823 ahd->hs_mailbox &= ~ENINT_COALESCE; 7824 if (enable) 7825 ahd->hs_mailbox |= ENINT_COALESCE; 7826 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 7827 ahd_flush_device_writes(ahd); 7828 ahd_run_qoutfifo(ahd); 7829 } 7830 7831 /* 7832 * Ensure that the card is paused in a location 7833 * outside of all critical sections and that all 7834 * pending work is completed prior to returning. 7835 * This routine should only be called from outside 7836 * an interrupt context. 7837 */ 7838 void 7839 ahd_pause_and_flushwork(struct ahd_softc *ahd) 7840 { 7841 u_int intstat; 7842 u_int maxloops; 7843 7844 maxloops = 1000; 7845 ahd->flags |= AHD_ALL_INTERRUPTS; 7846 ahd_pause(ahd); 7847 /* 7848 * Freeze the outgoing selections. We do this only 7849 * until we are safely paused without further selections 7850 * pending. 7851 */ 7852 ahd->qfreeze_cnt--; 7853 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 7854 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); 7855 do { 7856 7857 ahd_unpause(ahd); 7858 /* 7859 * Give the sequencer some time to service 7860 * any active selections. 7861 */ 7862 ahd_delay(500); 7863 7864 ahd_intr(ahd); 7865 ahd_pause(ahd); 7866 intstat = ahd_inb(ahd, INTSTAT); 7867 if ((intstat & INT_PEND) == 0) { 7868 ahd_clear_critical_section(ahd); 7869 intstat = ahd_inb(ahd, INTSTAT); 7870 } 7871 } while (--maxloops 7872 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 7873 && ((intstat & INT_PEND) != 0 7874 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 7875 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); 7876 7877 if (maxloops == 0) { 7878 printk("Infinite interrupt loop, INTSTAT = %x", 7879 ahd_inb(ahd, INTSTAT)); 7880 } 7881 ahd->qfreeze_cnt++; 7882 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 7883 7884 ahd_flush_qoutfifo(ahd); 7885 7886 ahd->flags &= ~AHD_ALL_INTERRUPTS; 7887 } 7888 7889 #ifdef CONFIG_PM 7890 int 7891 ahd_suspend(struct ahd_softc *ahd) 7892 { 7893 7894 ahd_pause_and_flushwork(ahd); 7895 7896 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 7897 ahd_unpause(ahd); 7898 return (EBUSY); 7899 } 7900 ahd_shutdown(ahd); 7901 return (0); 7902 } 7903 7904 void 7905 ahd_resume(struct ahd_softc *ahd) 7906 { 7907 7908 ahd_reset(ahd, /*reinit*/TRUE); 7909 ahd_intr_enable(ahd, TRUE); 7910 ahd_restart(ahd); 7911 } 7912 #endif 7913 7914 /************************** Busy Target Table *********************************/ 7915 /* 7916 * Set SCBPTR to the SCB that contains the busy 7917 * table entry for TCL. Return the offset into 7918 * the SCB that contains the entry for TCL. 7919 * saved_scbid is dereferenced and set to the 7920 * scbid that should be restored once manipualtion 7921 * of the TCL entry is complete. 7922 */ 7923 static inline u_int 7924 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 7925 { 7926 /* 7927 * Index to the SCB that contains the busy entry. 7928 */ 7929 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7930 *saved_scbid = ahd_get_scbptr(ahd); 7931 ahd_set_scbptr(ahd, TCL_LUN(tcl) 7932 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 7933 7934 /* 7935 * And now calculate the SCB offset to the entry. 7936 * Each entry is 2 bytes wide, hence the 7937 * multiplication by 2. 7938 */ 7939 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 7940 } 7941 7942 /* 7943 * Return the untagged transaction id for a given target/channel lun. 7944 */ 7945 static u_int 7946 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 7947 { 7948 u_int scbid; 7949 u_int scb_offset; 7950 u_int saved_scbptr; 7951 7952 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 7953 scbid = ahd_inw_scbram(ahd, scb_offset); 7954 ahd_set_scbptr(ahd, saved_scbptr); 7955 return (scbid); 7956 } 7957 7958 static void 7959 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 7960 { 7961 u_int scb_offset; 7962 u_int saved_scbptr; 7963 7964 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 7965 ahd_outw(ahd, scb_offset, scbid); 7966 ahd_set_scbptr(ahd, saved_scbptr); 7967 } 7968 7969 /************************** SCB and SCB queue management **********************/ 7970 static int 7971 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 7972 char channel, int lun, u_int tag, role_t role) 7973 { 7974 int targ = SCB_GET_TARGET(ahd, scb); 7975 char chan = SCB_GET_CHANNEL(ahd, scb); 7976 int slun = SCB_GET_LUN(scb); 7977 int match; 7978 7979 match = ((chan == channel) || (channel == ALL_CHANNELS)); 7980 if (match != 0) 7981 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 7982 if (match != 0) 7983 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 7984 if (match != 0) { 7985 #ifdef AHD_TARGET_MODE 7986 int group; 7987 7988 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 7989 if (role == ROLE_INITIATOR) { 7990 match = (group != XPT_FC_GROUP_TMODE) 7991 && ((tag == SCB_GET_TAG(scb)) 7992 || (tag == SCB_LIST_NULL)); 7993 } else if (role == ROLE_TARGET) { 7994 match = (group == XPT_FC_GROUP_TMODE) 7995 && ((tag == scb->io_ctx->csio.tag_id) 7996 || (tag == SCB_LIST_NULL)); 7997 } 7998 #else /* !AHD_TARGET_MODE */ 7999 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 8000 #endif /* AHD_TARGET_MODE */ 8001 } 8002 8003 return match; 8004 } 8005 8006 static void 8007 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 8008 { 8009 int target; 8010 char channel; 8011 int lun; 8012 8013 target = SCB_GET_TARGET(ahd, scb); 8014 lun = SCB_GET_LUN(scb); 8015 channel = SCB_GET_CHANNEL(ahd, scb); 8016 8017 ahd_search_qinfifo(ahd, target, channel, lun, 8018 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 8019 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 8020 8021 ahd_platform_freeze_devq(ahd, scb); 8022 } 8023 8024 void 8025 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 8026 { 8027 struct scb *prev_scb; 8028 ahd_mode_state saved_modes; 8029 8030 saved_modes = ahd_save_modes(ahd); 8031 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8032 prev_scb = NULL; 8033 if (ahd_qinfifo_count(ahd) != 0) { 8034 u_int prev_tag; 8035 u_int prev_pos; 8036 8037 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 8038 prev_tag = ahd->qinfifo[prev_pos]; 8039 prev_scb = ahd_lookup_scb(ahd, prev_tag); 8040 } 8041 ahd_qinfifo_requeue(ahd, prev_scb, scb); 8042 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 8043 ahd_restore_modes(ahd, saved_modes); 8044 } 8045 8046 static void 8047 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 8048 struct scb *scb) 8049 { 8050 if (prev_scb == NULL) { 8051 uint32_t busaddr; 8052 8053 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 8054 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 8055 } else { 8056 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 8057 ahd_sync_scb(ahd, prev_scb, 8058 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 8059 } 8060 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 8061 ahd->qinfifonext++; 8062 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 8063 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 8064 } 8065 8066 static int 8067 ahd_qinfifo_count(struct ahd_softc *ahd) 8068 { 8069 u_int qinpos; 8070 u_int wrap_qinpos; 8071 u_int wrap_qinfifonext; 8072 8073 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 8074 qinpos = ahd_get_snscb_qoff(ahd); 8075 wrap_qinpos = AHD_QIN_WRAP(qinpos); 8076 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 8077 if (wrap_qinfifonext >= wrap_qinpos) 8078 return (wrap_qinfifonext - wrap_qinpos); 8079 else 8080 return (wrap_qinfifonext 8081 + ARRAY_SIZE(ahd->qinfifo) - wrap_qinpos); 8082 } 8083 8084 static void 8085 ahd_reset_cmds_pending(struct ahd_softc *ahd) 8086 { 8087 struct scb *scb; 8088 ahd_mode_state saved_modes; 8089 u_int pending_cmds; 8090 8091 saved_modes = ahd_save_modes(ahd); 8092 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8093 8094 /* 8095 * Don't count any commands as outstanding that the 8096 * sequencer has already marked for completion. 8097 */ 8098 ahd_flush_qoutfifo(ahd); 8099 8100 pending_cmds = 0; 8101 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8102 pending_cmds++; 8103 } 8104 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 8105 ahd_restore_modes(ahd, saved_modes); 8106 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 8107 } 8108 8109 static void 8110 ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status) 8111 { 8112 cam_status ostat; 8113 cam_status cstat; 8114 8115 ostat = ahd_get_transaction_status(scb); 8116 if (ostat == CAM_REQ_INPROG) 8117 ahd_set_transaction_status(scb, status); 8118 cstat = ahd_get_transaction_status(scb); 8119 if (cstat != CAM_REQ_CMP) 8120 ahd_freeze_scb(scb); 8121 ahd_done(ahd, scb); 8122 } 8123 8124 int 8125 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 8126 int lun, u_int tag, role_t role, uint32_t status, 8127 ahd_search_action action) 8128 { 8129 struct scb *scb; 8130 struct scb *mk_msg_scb; 8131 struct scb *prev_scb; 8132 ahd_mode_state saved_modes; 8133 u_int qinstart; 8134 u_int qinpos; 8135 u_int qintail; 8136 u_int tid_next; 8137 u_int tid_prev; 8138 u_int scbid; 8139 u_int seq_flags2; 8140 u_int savedscbptr; 8141 uint32_t busaddr; 8142 int found; 8143 int targets; 8144 8145 /* Must be in CCHAN mode */ 8146 saved_modes = ahd_save_modes(ahd); 8147 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8148 8149 /* 8150 * Halt any pending SCB DMA. The sequencer will reinitiate 8151 * this dma if the qinfifo is not empty once we unpause. 8152 */ 8153 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 8154 == (CCARREN|CCSCBEN|CCSCBDIR)) { 8155 ahd_outb(ahd, CCSCBCTL, 8156 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 8157 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 8158 ; 8159 } 8160 /* Determine sequencer's position in the qinfifo. */ 8161 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 8162 qinstart = ahd_get_snscb_qoff(ahd); 8163 qinpos = AHD_QIN_WRAP(qinstart); 8164 found = 0; 8165 prev_scb = NULL; 8166 8167 if (action == SEARCH_PRINT) { 8168 printk("qinstart = %d qinfifonext = %d\nQINFIFO:", 8169 qinstart, ahd->qinfifonext); 8170 } 8171 8172 /* 8173 * Start with an empty queue. Entries that are not chosen 8174 * for removal will be re-added to the queue as we go. 8175 */ 8176 ahd->qinfifonext = qinstart; 8177 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 8178 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 8179 8180 while (qinpos != qintail) { 8181 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 8182 if (scb == NULL) { 8183 printk("qinpos = %d, SCB index = %d\n", 8184 qinpos, ahd->qinfifo[qinpos]); 8185 panic("Loop 1\n"); 8186 } 8187 8188 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 8189 /* 8190 * We found an scb that needs to be acted on. 8191 */ 8192 found++; 8193 switch (action) { 8194 case SEARCH_COMPLETE: 8195 if ((scb->flags & SCB_ACTIVE) == 0) 8196 printk("Inactive SCB in qinfifo\n"); 8197 ahd_done_with_status(ahd, scb, status); 8198 /* FALLTHROUGH */ 8199 case SEARCH_REMOVE: 8200 break; 8201 case SEARCH_PRINT: 8202 printk(" 0x%x", ahd->qinfifo[qinpos]); 8203 /* FALLTHROUGH */ 8204 case SEARCH_COUNT: 8205 ahd_qinfifo_requeue(ahd, prev_scb, scb); 8206 prev_scb = scb; 8207 break; 8208 } 8209 } else { 8210 ahd_qinfifo_requeue(ahd, prev_scb, scb); 8211 prev_scb = scb; 8212 } 8213 qinpos = AHD_QIN_WRAP(qinpos+1); 8214 } 8215 8216 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 8217 8218 if (action == SEARCH_PRINT) 8219 printk("\nWAITING_TID_QUEUES:\n"); 8220 8221 /* 8222 * Search waiting for selection lists. We traverse the 8223 * list of "their ids" waiting for selection and, if 8224 * appropriate, traverse the SCBs of each "their id" 8225 * looking for matches. 8226 */ 8227 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8228 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2); 8229 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) { 8230 scbid = ahd_inw(ahd, MK_MESSAGE_SCB); 8231 mk_msg_scb = ahd_lookup_scb(ahd, scbid); 8232 } else 8233 mk_msg_scb = NULL; 8234 savedscbptr = ahd_get_scbptr(ahd); 8235 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 8236 tid_prev = SCB_LIST_NULL; 8237 targets = 0; 8238 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 8239 u_int tid_head; 8240 u_int tid_tail; 8241 8242 targets++; 8243 if (targets > AHD_NUM_TARGETS) 8244 panic("TID LIST LOOP"); 8245 8246 if (scbid >= ahd->scb_data.numscbs) { 8247 printk("%s: Waiting TID List inconsistency. " 8248 "SCB index == 0x%x, yet numscbs == 0x%x.", 8249 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 8250 ahd_dump_card_state(ahd); 8251 panic("for safety"); 8252 } 8253 scb = ahd_lookup_scb(ahd, scbid); 8254 if (scb == NULL) { 8255 printk("%s: SCB = 0x%x Not Active!\n", 8256 ahd_name(ahd), scbid); 8257 panic("Waiting TID List traversal\n"); 8258 } 8259 ahd_set_scbptr(ahd, scbid); 8260 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 8261 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 8262 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 8263 tid_prev = scbid; 8264 continue; 8265 } 8266 8267 /* 8268 * We found a list of scbs that needs to be searched. 8269 */ 8270 if (action == SEARCH_PRINT) 8271 printk(" %d ( ", SCB_GET_TARGET(ahd, scb)); 8272 tid_head = scbid; 8273 found += ahd_search_scb_list(ahd, target, channel, 8274 lun, tag, role, status, 8275 action, &tid_head, &tid_tail, 8276 SCB_GET_TARGET(ahd, scb)); 8277 /* 8278 * Check any MK_MESSAGE SCB that is still waiting to 8279 * enter this target's waiting for selection queue. 8280 */ 8281 if (mk_msg_scb != NULL 8282 && ahd_match_scb(ahd, mk_msg_scb, target, channel, 8283 lun, tag, role)) { 8284 8285 /* 8286 * We found an scb that needs to be acted on. 8287 */ 8288 found++; 8289 switch (action) { 8290 case SEARCH_COMPLETE: 8291 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0) 8292 printk("Inactive SCB pending MK_MSG\n"); 8293 ahd_done_with_status(ahd, mk_msg_scb, status); 8294 /* FALLTHROUGH */ 8295 case SEARCH_REMOVE: 8296 { 8297 u_int tail_offset; 8298 8299 printk("Removing MK_MSG scb\n"); 8300 8301 /* 8302 * Reset our tail to the tail of the 8303 * main per-target list. 8304 */ 8305 tail_offset = WAITING_SCB_TAILS 8306 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb)); 8307 ahd_outw(ahd, tail_offset, tid_tail); 8308 8309 seq_flags2 &= ~PENDING_MK_MESSAGE; 8310 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2); 8311 ahd_outw(ahd, CMDS_PENDING, 8312 ahd_inw(ahd, CMDS_PENDING)-1); 8313 mk_msg_scb = NULL; 8314 break; 8315 } 8316 case SEARCH_PRINT: 8317 printk(" 0x%x", SCB_GET_TAG(scb)); 8318 /* FALLTHROUGH */ 8319 case SEARCH_COUNT: 8320 break; 8321 } 8322 } 8323 8324 if (mk_msg_scb != NULL 8325 && SCBID_IS_NULL(tid_head) 8326 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 8327 SCB_LIST_NULL, ROLE_UNKNOWN)) { 8328 8329 /* 8330 * When removing the last SCB for a target 8331 * queue with a pending MK_MESSAGE scb, we 8332 * must queue the MK_MESSAGE scb. 8333 */ 8334 printk("Queueing mk_msg_scb\n"); 8335 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB); 8336 seq_flags2 &= ~PENDING_MK_MESSAGE; 8337 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2); 8338 mk_msg_scb = NULL; 8339 } 8340 if (tid_head != scbid) 8341 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 8342 if (!SCBID_IS_NULL(tid_head)) 8343 tid_prev = tid_head; 8344 if (action == SEARCH_PRINT) 8345 printk(")\n"); 8346 } 8347 8348 /* Restore saved state. */ 8349 ahd_set_scbptr(ahd, savedscbptr); 8350 ahd_restore_modes(ahd, saved_modes); 8351 return (found); 8352 } 8353 8354 static int 8355 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 8356 int lun, u_int tag, role_t role, uint32_t status, 8357 ahd_search_action action, u_int *list_head, 8358 u_int *list_tail, u_int tid) 8359 { 8360 struct scb *scb; 8361 u_int scbid; 8362 u_int next; 8363 u_int prev; 8364 int found; 8365 8366 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8367 found = 0; 8368 prev = SCB_LIST_NULL; 8369 next = *list_head; 8370 *list_tail = SCB_LIST_NULL; 8371 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 8372 if (scbid >= ahd->scb_data.numscbs) { 8373 printk("%s:SCB List inconsistency. " 8374 "SCB == 0x%x, yet numscbs == 0x%x.", 8375 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 8376 ahd_dump_card_state(ahd); 8377 panic("for safety"); 8378 } 8379 scb = ahd_lookup_scb(ahd, scbid); 8380 if (scb == NULL) { 8381 printk("%s: SCB = %d Not Active!\n", 8382 ahd_name(ahd), scbid); 8383 panic("Waiting List traversal\n"); 8384 } 8385 ahd_set_scbptr(ahd, scbid); 8386 *list_tail = scbid; 8387 next = ahd_inw_scbram(ahd, SCB_NEXT); 8388 if (ahd_match_scb(ahd, scb, target, channel, 8389 lun, SCB_LIST_NULL, role) == 0) { 8390 prev = scbid; 8391 continue; 8392 } 8393 found++; 8394 switch (action) { 8395 case SEARCH_COMPLETE: 8396 if ((scb->flags & SCB_ACTIVE) == 0) 8397 printk("Inactive SCB in Waiting List\n"); 8398 ahd_done_with_status(ahd, scb, status); 8399 /* fall through */ 8400 case SEARCH_REMOVE: 8401 ahd_rem_wscb(ahd, scbid, prev, next, tid); 8402 *list_tail = prev; 8403 if (SCBID_IS_NULL(prev)) 8404 *list_head = next; 8405 break; 8406 case SEARCH_PRINT: 8407 printk("0x%x ", scbid); 8408 /* fall through */ 8409 case SEARCH_COUNT: 8410 prev = scbid; 8411 break; 8412 } 8413 if (found > AHD_SCB_MAX) 8414 panic("SCB LIST LOOP"); 8415 } 8416 if (action == SEARCH_COMPLETE 8417 || action == SEARCH_REMOVE) 8418 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 8419 return (found); 8420 } 8421 8422 static void 8423 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 8424 u_int tid_cur, u_int tid_next) 8425 { 8426 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8427 8428 if (SCBID_IS_NULL(tid_cur)) { 8429 8430 /* Bypass current TID list */ 8431 if (SCBID_IS_NULL(tid_prev)) { 8432 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 8433 } else { 8434 ahd_set_scbptr(ahd, tid_prev); 8435 ahd_outw(ahd, SCB_NEXT2, tid_next); 8436 } 8437 if (SCBID_IS_NULL(tid_next)) 8438 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 8439 } else { 8440 8441 /* Stitch through tid_cur */ 8442 if (SCBID_IS_NULL(tid_prev)) { 8443 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 8444 } else { 8445 ahd_set_scbptr(ahd, tid_prev); 8446 ahd_outw(ahd, SCB_NEXT2, tid_cur); 8447 } 8448 ahd_set_scbptr(ahd, tid_cur); 8449 ahd_outw(ahd, SCB_NEXT2, tid_next); 8450 8451 if (SCBID_IS_NULL(tid_next)) 8452 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 8453 } 8454 } 8455 8456 /* 8457 * Manipulate the waiting for selection list and return the 8458 * scb that follows the one that we remove. 8459 */ 8460 static u_int 8461 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 8462 u_int prev, u_int next, u_int tid) 8463 { 8464 u_int tail_offset; 8465 8466 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8467 if (!SCBID_IS_NULL(prev)) { 8468 ahd_set_scbptr(ahd, prev); 8469 ahd_outw(ahd, SCB_NEXT, next); 8470 } 8471 8472 /* 8473 * SCBs that have MK_MESSAGE set in them may 8474 * cause the tail pointer to be updated without 8475 * setting the next pointer of the previous tail. 8476 * Only clear the tail if the removed SCB was 8477 * the tail. 8478 */ 8479 tail_offset = WAITING_SCB_TAILS + (2 * tid); 8480 if (SCBID_IS_NULL(next) 8481 && ahd_inw(ahd, tail_offset) == scbid) 8482 ahd_outw(ahd, tail_offset, prev); 8483 8484 ahd_add_scb_to_free_list(ahd, scbid); 8485 return (next); 8486 } 8487 8488 /* 8489 * Add the SCB as selected by SCBPTR onto the on chip list of 8490 * free hardware SCBs. This list is empty/unused if we are not 8491 * performing SCB paging. 8492 */ 8493 static void 8494 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 8495 { 8496 /* XXX Need some other mechanism to designate "free". */ 8497 /* 8498 * Invalidate the tag so that our abort 8499 * routines don't think it's active. 8500 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 8501 */ 8502 } 8503 8504 /******************************** Error Handling ******************************/ 8505 /* 8506 * Abort all SCBs that match the given description (target/channel/lun/tag), 8507 * setting their status to the passed in status if the status has not already 8508 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 8509 * is paused before it is called. 8510 */ 8511 static int 8512 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 8513 int lun, u_int tag, role_t role, uint32_t status) 8514 { 8515 struct scb *scbp; 8516 struct scb *scbp_next; 8517 u_int i, j; 8518 u_int maxtarget; 8519 u_int minlun; 8520 u_int maxlun; 8521 int found; 8522 ahd_mode_state saved_modes; 8523 8524 /* restore this when we're done */ 8525 saved_modes = ahd_save_modes(ahd); 8526 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8527 8528 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 8529 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 8530 8531 /* 8532 * Clean out the busy target table for any untagged commands. 8533 */ 8534 i = 0; 8535 maxtarget = 16; 8536 if (target != CAM_TARGET_WILDCARD) { 8537 i = target; 8538 if (channel == 'B') 8539 i += 8; 8540 maxtarget = i + 1; 8541 } 8542 8543 if (lun == CAM_LUN_WILDCARD) { 8544 minlun = 0; 8545 maxlun = AHD_NUM_LUNS_NONPKT; 8546 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 8547 minlun = maxlun = 0; 8548 } else { 8549 minlun = lun; 8550 maxlun = lun + 1; 8551 } 8552 8553 if (role != ROLE_TARGET) { 8554 for (;i < maxtarget; i++) { 8555 for (j = minlun;j < maxlun; j++) { 8556 u_int scbid; 8557 u_int tcl; 8558 8559 tcl = BUILD_TCL_RAW(i, 'A', j); 8560 scbid = ahd_find_busy_tcl(ahd, tcl); 8561 scbp = ahd_lookup_scb(ahd, scbid); 8562 if (scbp == NULL 8563 || ahd_match_scb(ahd, scbp, target, channel, 8564 lun, tag, role) == 0) 8565 continue; 8566 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 8567 } 8568 } 8569 } 8570 8571 /* 8572 * Don't abort commands that have already completed, 8573 * but haven't quite made it up to the host yet. 8574 */ 8575 ahd_flush_qoutfifo(ahd); 8576 8577 /* 8578 * Go through the pending CCB list and look for 8579 * commands for this target that are still active. 8580 * These are other tagged commands that were 8581 * disconnected when the reset occurred. 8582 */ 8583 scbp_next = LIST_FIRST(&ahd->pending_scbs); 8584 while (scbp_next != NULL) { 8585 scbp = scbp_next; 8586 scbp_next = LIST_NEXT(scbp, pending_links); 8587 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 8588 cam_status ostat; 8589 8590 ostat = ahd_get_transaction_status(scbp); 8591 if (ostat == CAM_REQ_INPROG) 8592 ahd_set_transaction_status(scbp, status); 8593 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 8594 ahd_freeze_scb(scbp); 8595 if ((scbp->flags & SCB_ACTIVE) == 0) 8596 printk("Inactive SCB on pending list\n"); 8597 ahd_done(ahd, scbp); 8598 found++; 8599 } 8600 } 8601 ahd_restore_modes(ahd, saved_modes); 8602 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 8603 ahd->flags |= AHD_UPDATE_PEND_CMDS; 8604 return found; 8605 } 8606 8607 static void 8608 ahd_reset_current_bus(struct ahd_softc *ahd) 8609 { 8610 uint8_t scsiseq; 8611 8612 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8613 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 8614 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 8615 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 8616 ahd_flush_device_writes(ahd); 8617 ahd_delay(AHD_BUSRESET_DELAY); 8618 /* Turn off the bus reset */ 8619 ahd_outb(ahd, SCSISEQ0, scsiseq); 8620 ahd_flush_device_writes(ahd); 8621 ahd_delay(AHD_BUSRESET_DELAY); 8622 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 8623 /* 8624 * 2A Razor #474 8625 * Certain chip state is not cleared for 8626 * SCSI bus resets that we initiate, so 8627 * we must reset the chip. 8628 */ 8629 ahd_reset(ahd, /*reinit*/TRUE); 8630 ahd_intr_enable(ahd, /*enable*/TRUE); 8631 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8632 } 8633 8634 ahd_clear_intstat(ahd); 8635 } 8636 8637 int 8638 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 8639 { 8640 struct ahd_devinfo caminfo; 8641 u_int initiator; 8642 u_int target; 8643 u_int max_scsiid; 8644 int found; 8645 u_int fifo; 8646 u_int next_fifo; 8647 uint8_t scsiseq; 8648 8649 /* 8650 * Check if the last bus reset is cleared 8651 */ 8652 if (ahd->flags & AHD_BUS_RESET_ACTIVE) { 8653 printk("%s: bus reset still active\n", 8654 ahd_name(ahd)); 8655 return 0; 8656 } 8657 ahd->flags |= AHD_BUS_RESET_ACTIVE; 8658 8659 ahd->pending_device = NULL; 8660 8661 ahd_compile_devinfo(&caminfo, 8662 CAM_TARGET_WILDCARD, 8663 CAM_TARGET_WILDCARD, 8664 CAM_LUN_WILDCARD, 8665 channel, ROLE_UNKNOWN); 8666 ahd_pause(ahd); 8667 8668 /* Make sure the sequencer is in a safe location. */ 8669 ahd_clear_critical_section(ahd); 8670 8671 /* 8672 * Run our command complete fifos to ensure that we perform 8673 * completion processing on any commands that 'completed' 8674 * before the reset occurred. 8675 */ 8676 ahd_run_qoutfifo(ahd); 8677 #ifdef AHD_TARGET_MODE 8678 if ((ahd->flags & AHD_TARGETROLE) != 0) { 8679 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 8680 } 8681 #endif 8682 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8683 8684 /* 8685 * Disable selections so no automatic hardware 8686 * functions will modify chip state. 8687 */ 8688 ahd_outb(ahd, SCSISEQ0, 0); 8689 ahd_outb(ahd, SCSISEQ1, 0); 8690 8691 /* 8692 * Safely shut down our DMA engines. Always start with 8693 * the FIFO that is not currently active (if any are 8694 * actively connected). 8695 */ 8696 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 8697 if (next_fifo > CURRFIFO_1) 8698 /* If disconneced, arbitrarily start with FIFO1. */ 8699 next_fifo = fifo = 0; 8700 do { 8701 next_fifo ^= CURRFIFO_1; 8702 ahd_set_modes(ahd, next_fifo, next_fifo); 8703 ahd_outb(ahd, DFCNTRL, 8704 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 8705 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 8706 ahd_delay(10); 8707 /* 8708 * Set CURRFIFO to the now inactive channel. 8709 */ 8710 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8711 ahd_outb(ahd, DFFSTAT, next_fifo); 8712 } while (next_fifo != fifo); 8713 8714 /* 8715 * Reset the bus if we are initiating this reset 8716 */ 8717 ahd_clear_msg_state(ahd); 8718 ahd_outb(ahd, SIMODE1, 8719 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST)); 8720 8721 if (initiate_reset) 8722 ahd_reset_current_bus(ahd); 8723 8724 ahd_clear_intstat(ahd); 8725 8726 /* 8727 * Clean up all the state information for the 8728 * pending transactions on this bus. 8729 */ 8730 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 8731 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8732 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 8733 8734 /* 8735 * Cleanup anything left in the FIFOs. 8736 */ 8737 ahd_clear_fifo(ahd, 0); 8738 ahd_clear_fifo(ahd, 1); 8739 8740 /* 8741 * Clear SCSI interrupt status 8742 */ 8743 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 8744 8745 /* 8746 * Reenable selections 8747 */ 8748 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 8749 scsiseq = ahd_inb(ahd, SCSISEQ_TEMPLATE); 8750 ahd_outb(ahd, SCSISEQ1, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 8751 8752 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 8753 #ifdef AHD_TARGET_MODE 8754 /* 8755 * Send an immediate notify ccb to all target more peripheral 8756 * drivers affected by this action. 8757 */ 8758 for (target = 0; target <= max_scsiid; target++) { 8759 struct ahd_tmode_tstate* tstate; 8760 u_int lun; 8761 8762 tstate = ahd->enabled_targets[target]; 8763 if (tstate == NULL) 8764 continue; 8765 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 8766 struct ahd_tmode_lstate* lstate; 8767 8768 lstate = tstate->enabled_luns[lun]; 8769 if (lstate == NULL) 8770 continue; 8771 8772 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 8773 EVENT_TYPE_BUS_RESET, /*arg*/0); 8774 ahd_send_lstate_events(ahd, lstate); 8775 } 8776 } 8777 #endif 8778 /* 8779 * Revert to async/narrow transfers until we renegotiate. 8780 */ 8781 for (target = 0; target <= max_scsiid; target++) { 8782 8783 if (ahd->enabled_targets[target] == NULL) 8784 continue; 8785 for (initiator = 0; initiator <= max_scsiid; initiator++) { 8786 struct ahd_devinfo devinfo; 8787 8788 ahd_compile_devinfo(&devinfo, target, initiator, 8789 CAM_LUN_WILDCARD, 8790 'A', ROLE_UNKNOWN); 8791 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 8792 AHD_TRANS_CUR, /*paused*/TRUE); 8793 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 8794 /*offset*/0, /*ppr_options*/0, 8795 AHD_TRANS_CUR, /*paused*/TRUE); 8796 } 8797 } 8798 8799 /* Notify the XPT that a bus reset occurred */ 8800 ahd_send_async(ahd, caminfo.channel, CAM_TARGET_WILDCARD, 8801 CAM_LUN_WILDCARD, AC_BUS_RESET); 8802 8803 ahd_restart(ahd); 8804 8805 return (found); 8806 } 8807 8808 /**************************** Statistics Processing ***************************/ 8809 static void 8810 ahd_stat_timer(struct timer_list *t) 8811 { 8812 struct ahd_softc *ahd = from_timer(ahd, t, stat_timer); 8813 u_long s; 8814 int enint_coal; 8815 8816 ahd_lock(ahd, &s); 8817 8818 enint_coal = ahd->hs_mailbox & ENINT_COALESCE; 8819 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) 8820 enint_coal |= ENINT_COALESCE; 8821 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) 8822 enint_coal &= ~ENINT_COALESCE; 8823 8824 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { 8825 ahd_enable_coalescing(ahd, enint_coal); 8826 #ifdef AHD_DEBUG 8827 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) 8828 printk("%s: Interrupt coalescing " 8829 "now %sabled. Cmds %d\n", 8830 ahd_name(ahd), 8831 (enint_coal & ENINT_COALESCE) ? "en" : "dis", 8832 ahd->cmdcmplt_total); 8833 #endif 8834 } 8835 8836 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 8837 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 8838 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 8839 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US); 8840 ahd_unlock(ahd, &s); 8841 } 8842 8843 /****************************** Status Processing *****************************/ 8844 8845 static void 8846 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 8847 { 8848 struct hardware_scb *hscb; 8849 int paused; 8850 8851 /* 8852 * The sequencer freezes its select-out queue 8853 * anytime a SCSI status error occurs. We must 8854 * handle the error and increment our qfreeze count 8855 * to allow the sequencer to continue. We don't 8856 * bother clearing critical sections here since all 8857 * operations are on data structures that the sequencer 8858 * is not touching once the queue is frozen. 8859 */ 8860 hscb = scb->hscb; 8861 8862 if (ahd_is_paused(ahd)) { 8863 paused = 1; 8864 } else { 8865 paused = 0; 8866 ahd_pause(ahd); 8867 } 8868 8869 /* Freeze the queue until the client sees the error. */ 8870 ahd_freeze_devq(ahd, scb); 8871 ahd_freeze_scb(scb); 8872 ahd->qfreeze_cnt++; 8873 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 8874 8875 if (paused == 0) 8876 ahd_unpause(ahd); 8877 8878 /* Don't want to clobber the original sense code */ 8879 if ((scb->flags & SCB_SENSE) != 0) { 8880 /* 8881 * Clear the SCB_SENSE Flag and perform 8882 * a normal command completion. 8883 */ 8884 scb->flags &= ~SCB_SENSE; 8885 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 8886 ahd_done(ahd, scb); 8887 return; 8888 } 8889 ahd_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 8890 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 8891 switch (hscb->shared_data.istatus.scsi_status) { 8892 case STATUS_PKT_SENSE: 8893 { 8894 struct scsi_status_iu_header *siu; 8895 8896 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 8897 siu = (struct scsi_status_iu_header *)scb->sense_data; 8898 ahd_set_scsi_status(scb, siu->status); 8899 #ifdef AHD_DEBUG 8900 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 8901 ahd_print_path(ahd, scb); 8902 printk("SCB 0x%x Received PKT Status of 0x%x\n", 8903 SCB_GET_TAG(scb), siu->status); 8904 printk("\tflags = 0x%x, sense len = 0x%x, " 8905 "pktfail = 0x%x\n", 8906 siu->flags, scsi_4btoul(siu->sense_length), 8907 scsi_4btoul(siu->pkt_failures_length)); 8908 } 8909 #endif 8910 if ((siu->flags & SIU_RSPVALID) != 0) { 8911 ahd_print_path(ahd, scb); 8912 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 8913 printk("Unable to parse pkt_failures\n"); 8914 } else { 8915 8916 switch (SIU_PKTFAIL_CODE(siu)) { 8917 case SIU_PFC_NONE: 8918 printk("No packet failure found\n"); 8919 break; 8920 case SIU_PFC_CIU_FIELDS_INVALID: 8921 printk("Invalid Command IU Field\n"); 8922 break; 8923 case SIU_PFC_TMF_NOT_SUPPORTED: 8924 printk("TMF not supported\n"); 8925 break; 8926 case SIU_PFC_TMF_FAILED: 8927 printk("TMF failed\n"); 8928 break; 8929 case SIU_PFC_INVALID_TYPE_CODE: 8930 printk("Invalid L_Q Type code\n"); 8931 break; 8932 case SIU_PFC_ILLEGAL_REQUEST: 8933 printk("Illegal request\n"); 8934 default: 8935 break; 8936 } 8937 } 8938 if (siu->status == SCSI_STATUS_OK) 8939 ahd_set_transaction_status(scb, 8940 CAM_REQ_CMP_ERR); 8941 } 8942 if ((siu->flags & SIU_SNSVALID) != 0) { 8943 scb->flags |= SCB_PKT_SENSE; 8944 #ifdef AHD_DEBUG 8945 if ((ahd_debug & AHD_SHOW_SENSE) != 0) 8946 printk("Sense data available\n"); 8947 #endif 8948 } 8949 ahd_done(ahd, scb); 8950 break; 8951 } 8952 case SCSI_STATUS_CMD_TERMINATED: 8953 case SCSI_STATUS_CHECK_COND: 8954 { 8955 struct ahd_devinfo devinfo; 8956 struct ahd_dma_seg *sg; 8957 struct scsi_sense *sc; 8958 struct ahd_initiator_tinfo *targ_info; 8959 struct ahd_tmode_tstate *tstate; 8960 struct ahd_transinfo *tinfo; 8961 #ifdef AHD_DEBUG 8962 if (ahd_debug & AHD_SHOW_SENSE) { 8963 ahd_print_path(ahd, scb); 8964 printk("SCB %d: requests Check Status\n", 8965 SCB_GET_TAG(scb)); 8966 } 8967 #endif 8968 8969 if (ahd_perform_autosense(scb) == 0) 8970 break; 8971 8972 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 8973 SCB_GET_TARGET(ahd, scb), 8974 SCB_GET_LUN(scb), 8975 SCB_GET_CHANNEL(ahd, scb), 8976 ROLE_INITIATOR); 8977 targ_info = ahd_fetch_transinfo(ahd, 8978 devinfo.channel, 8979 devinfo.our_scsiid, 8980 devinfo.target, 8981 &tstate); 8982 tinfo = &targ_info->curr; 8983 sg = scb->sg_list; 8984 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb; 8985 /* 8986 * Save off the residual if there is one. 8987 */ 8988 ahd_update_residual(ahd, scb); 8989 #ifdef AHD_DEBUG 8990 if (ahd_debug & AHD_SHOW_SENSE) { 8991 ahd_print_path(ahd, scb); 8992 printk("Sending Sense\n"); 8993 } 8994 #endif 8995 scb->sg_count = 0; 8996 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 8997 ahd_get_sense_bufsize(ahd, scb), 8998 /*last*/TRUE); 8999 sc->opcode = REQUEST_SENSE; 9000 sc->byte2 = 0; 9001 if (tinfo->protocol_version <= SCSI_REV_2 9002 && SCB_GET_LUN(scb) < 8) 9003 sc->byte2 = SCB_GET_LUN(scb) << 5; 9004 sc->unused[0] = 0; 9005 sc->unused[1] = 0; 9006 sc->length = ahd_get_sense_bufsize(ahd, scb); 9007 sc->control = 0; 9008 9009 /* 9010 * We can't allow the target to disconnect. 9011 * This will be an untagged transaction and 9012 * having the target disconnect will make this 9013 * transaction indestinguishable from outstanding 9014 * tagged transactions. 9015 */ 9016 hscb->control = 0; 9017 9018 /* 9019 * This request sense could be because the 9020 * the device lost power or in some other 9021 * way has lost our transfer negotiations. 9022 * Renegotiate if appropriate. Unit attention 9023 * errors will be reported before any data 9024 * phases occur. 9025 */ 9026 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 9027 ahd_update_neg_request(ahd, &devinfo, 9028 tstate, targ_info, 9029 AHD_NEG_IF_NON_ASYNC); 9030 } 9031 if (tstate->auto_negotiate & devinfo.target_mask) { 9032 hscb->control |= MK_MESSAGE; 9033 scb->flags &= 9034 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 9035 scb->flags |= SCB_AUTO_NEGOTIATE; 9036 } 9037 hscb->cdb_len = sizeof(*sc); 9038 ahd_setup_data_scb(ahd, scb); 9039 scb->flags |= SCB_SENSE; 9040 ahd_queue_scb(ahd, scb); 9041 break; 9042 } 9043 case SCSI_STATUS_OK: 9044 printk("%s: Interrupted for status of 0???\n", 9045 ahd_name(ahd)); 9046 /* FALLTHROUGH */ 9047 default: 9048 ahd_done(ahd, scb); 9049 break; 9050 } 9051 } 9052 9053 static void 9054 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 9055 { 9056 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 9057 ahd_handle_scsi_status(ahd, scb); 9058 } else { 9059 ahd_calc_residual(ahd, scb); 9060 ahd_done(ahd, scb); 9061 } 9062 } 9063 9064 /* 9065 * Calculate the residual for a just completed SCB. 9066 */ 9067 static void 9068 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 9069 { 9070 struct hardware_scb *hscb; 9071 struct initiator_status *spkt; 9072 uint32_t sgptr; 9073 uint32_t resid_sgptr; 9074 uint32_t resid; 9075 9076 /* 9077 * 5 cases. 9078 * 1) No residual. 9079 * SG_STATUS_VALID clear in sgptr. 9080 * 2) Transferless command 9081 * 3) Never performed any transfers. 9082 * sgptr has SG_FULL_RESID set. 9083 * 4) No residual but target did not 9084 * save data pointers after the 9085 * last transfer, so sgptr was 9086 * never updated. 9087 * 5) We have a partial residual. 9088 * Use residual_sgptr to determine 9089 * where we are. 9090 */ 9091 9092 hscb = scb->hscb; 9093 sgptr = ahd_le32toh(hscb->sgptr); 9094 if ((sgptr & SG_STATUS_VALID) == 0) 9095 /* Case 1 */ 9096 return; 9097 sgptr &= ~SG_STATUS_VALID; 9098 9099 if ((sgptr & SG_LIST_NULL) != 0) 9100 /* Case 2 */ 9101 return; 9102 9103 /* 9104 * Residual fields are the same in both 9105 * target and initiator status packets, 9106 * so we can always use the initiator fields 9107 * regardless of the role for this SCB. 9108 */ 9109 spkt = &hscb->shared_data.istatus; 9110 resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 9111 if ((sgptr & SG_FULL_RESID) != 0) { 9112 /* Case 3 */ 9113 resid = ahd_get_transfer_length(scb); 9114 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 9115 /* Case 4 */ 9116 return; 9117 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 9118 ahd_print_path(ahd, scb); 9119 printk("data overrun detected Tag == 0x%x.\n", 9120 SCB_GET_TAG(scb)); 9121 ahd_freeze_devq(ahd, scb); 9122 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 9123 ahd_freeze_scb(scb); 9124 return; 9125 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 9126 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 9127 /* NOTREACHED */ 9128 } else { 9129 struct ahd_dma_seg *sg; 9130 9131 /* 9132 * Remainder of the SG where the transfer 9133 * stopped. 9134 */ 9135 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 9136 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 9137 9138 /* The residual sg_ptr always points to the next sg */ 9139 sg--; 9140 9141 /* 9142 * Add up the contents of all residual 9143 * SG segments that are after the SG where 9144 * the transfer stopped. 9145 */ 9146 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 9147 sg++; 9148 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 9149 } 9150 } 9151 if ((scb->flags & SCB_SENSE) == 0) 9152 ahd_set_residual(scb, resid); 9153 else 9154 ahd_set_sense_residual(scb, resid); 9155 9156 #ifdef AHD_DEBUG 9157 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 9158 ahd_print_path(ahd, scb); 9159 printk("Handled %sResidual of %d bytes\n", 9160 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 9161 } 9162 #endif 9163 } 9164 9165 /******************************* Target Mode **********************************/ 9166 #ifdef AHD_TARGET_MODE 9167 /* 9168 * Add a target mode event to this lun's queue 9169 */ 9170 static void 9171 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 9172 u_int initiator_id, u_int event_type, u_int event_arg) 9173 { 9174 struct ahd_tmode_event *event; 9175 int pending; 9176 9177 xpt_freeze_devq(lstate->path, /*count*/1); 9178 if (lstate->event_w_idx >= lstate->event_r_idx) 9179 pending = lstate->event_w_idx - lstate->event_r_idx; 9180 else 9181 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 9182 - (lstate->event_r_idx - lstate->event_w_idx); 9183 9184 if (event_type == EVENT_TYPE_BUS_RESET 9185 || event_type == MSG_BUS_DEV_RESET) { 9186 /* 9187 * Any earlier events are irrelevant, so reset our buffer. 9188 * This has the effect of allowing us to deal with reset 9189 * floods (an external device holding down the reset line) 9190 * without losing the event that is really interesting. 9191 */ 9192 lstate->event_r_idx = 0; 9193 lstate->event_w_idx = 0; 9194 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 9195 } 9196 9197 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 9198 xpt_print_path(lstate->path); 9199 printk("immediate event %x:%x lost\n", 9200 lstate->event_buffer[lstate->event_r_idx].event_type, 9201 lstate->event_buffer[lstate->event_r_idx].event_arg); 9202 lstate->event_r_idx++; 9203 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 9204 lstate->event_r_idx = 0; 9205 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 9206 } 9207 9208 event = &lstate->event_buffer[lstate->event_w_idx]; 9209 event->initiator_id = initiator_id; 9210 event->event_type = event_type; 9211 event->event_arg = event_arg; 9212 lstate->event_w_idx++; 9213 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 9214 lstate->event_w_idx = 0; 9215 } 9216 9217 /* 9218 * Send any target mode events queued up waiting 9219 * for immediate notify resources. 9220 */ 9221 void 9222 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 9223 { 9224 struct ccb_hdr *ccbh; 9225 struct ccb_immed_notify *inot; 9226 9227 while (lstate->event_r_idx != lstate->event_w_idx 9228 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 9229 struct ahd_tmode_event *event; 9230 9231 event = &lstate->event_buffer[lstate->event_r_idx]; 9232 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 9233 inot = (struct ccb_immed_notify *)ccbh; 9234 switch (event->event_type) { 9235 case EVENT_TYPE_BUS_RESET: 9236 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 9237 break; 9238 default: 9239 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 9240 inot->message_args[0] = event->event_type; 9241 inot->message_args[1] = event->event_arg; 9242 break; 9243 } 9244 inot->initiator_id = event->initiator_id; 9245 inot->sense_len = 0; 9246 xpt_done((union ccb *)inot); 9247 lstate->event_r_idx++; 9248 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 9249 lstate->event_r_idx = 0; 9250 } 9251 } 9252 #endif 9253 9254 /******************** Sequencer Program Patching/Download *********************/ 9255 9256 #ifdef AHD_DUMP_SEQ 9257 void 9258 ahd_dumpseq(struct ahd_softc* ahd) 9259 { 9260 int i; 9261 int max_prog; 9262 9263 max_prog = 2048; 9264 9265 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 9266 ahd_outw(ahd, PRGMCNT, 0); 9267 for (i = 0; i < max_prog; i++) { 9268 uint8_t ins_bytes[4]; 9269 9270 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 9271 printk("0x%08x\n", ins_bytes[0] << 24 9272 | ins_bytes[1] << 16 9273 | ins_bytes[2] << 8 9274 | ins_bytes[3]); 9275 } 9276 } 9277 #endif 9278 9279 static void 9280 ahd_loadseq(struct ahd_softc *ahd) 9281 { 9282 struct cs cs_table[NUM_CRITICAL_SECTIONS]; 9283 u_int begin_set[NUM_CRITICAL_SECTIONS]; 9284 u_int end_set[NUM_CRITICAL_SECTIONS]; 9285 const struct patch *cur_patch; 9286 u_int cs_count; 9287 u_int cur_cs; 9288 u_int i; 9289 int downloaded; 9290 u_int skip_addr; 9291 u_int sg_prefetch_cnt; 9292 u_int sg_prefetch_cnt_limit; 9293 u_int sg_prefetch_align; 9294 u_int sg_size; 9295 u_int cacheline_mask; 9296 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 9297 9298 if (bootverbose) 9299 printk("%s: Downloading Sequencer Program...", 9300 ahd_name(ahd)); 9301 9302 #if DOWNLOAD_CONST_COUNT != 8 9303 #error "Download Const Mismatch" 9304 #endif 9305 /* 9306 * Start out with 0 critical sections 9307 * that apply to this firmware load. 9308 */ 9309 cs_count = 0; 9310 cur_cs = 0; 9311 memset(begin_set, 0, sizeof(begin_set)); 9312 memset(end_set, 0, sizeof(end_set)); 9313 9314 /* 9315 * Setup downloadable constant table. 9316 * 9317 * The computation for the S/G prefetch variables is 9318 * a bit complicated. We would like to always fetch 9319 * in terms of cachelined sized increments. However, 9320 * if the cacheline is not an even multiple of the 9321 * SG element size or is larger than our SG RAM, using 9322 * just the cache size might leave us with only a portion 9323 * of an SG element at the tail of a prefetch. If the 9324 * cacheline is larger than our S/G prefetch buffer less 9325 * the size of an SG element, we may round down to a cacheline 9326 * that doesn't contain any or all of the S/G of interest 9327 * within the bounds of our S/G ram. Provide variables to 9328 * the sequencer that will allow it to handle these edge 9329 * cases. 9330 */ 9331 /* Start by aligning to the nearest cacheline. */ 9332 sg_prefetch_align = ahd->pci_cachesize; 9333 if (sg_prefetch_align == 0) 9334 sg_prefetch_align = 8; 9335 /* Round down to the nearest power of 2. */ 9336 while (powerof2(sg_prefetch_align) == 0) 9337 sg_prefetch_align--; 9338 9339 cacheline_mask = sg_prefetch_align - 1; 9340 9341 /* 9342 * If the cacheline boundary is greater than half our prefetch RAM 9343 * we risk not being able to fetch even a single complete S/G 9344 * segment if we align to that boundary. 9345 */ 9346 if (sg_prefetch_align > CCSGADDR_MAX/2) 9347 sg_prefetch_align = CCSGADDR_MAX/2; 9348 /* Start by fetching a single cacheline. */ 9349 sg_prefetch_cnt = sg_prefetch_align; 9350 /* 9351 * Increment the prefetch count by cachelines until 9352 * at least one S/G element will fit. 9353 */ 9354 sg_size = sizeof(struct ahd_dma_seg); 9355 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 9356 sg_size = sizeof(struct ahd_dma64_seg); 9357 while (sg_prefetch_cnt < sg_size) 9358 sg_prefetch_cnt += sg_prefetch_align; 9359 /* 9360 * If the cacheline is not an even multiple of 9361 * the S/G size, we may only get a partial S/G when 9362 * we align. Add a cacheline if this is the case. 9363 */ 9364 if ((sg_prefetch_align % sg_size) != 0 9365 && (sg_prefetch_cnt < CCSGADDR_MAX)) 9366 sg_prefetch_cnt += sg_prefetch_align; 9367 /* 9368 * Lastly, compute a value that the sequencer can use 9369 * to determine if the remainder of the CCSGRAM buffer 9370 * has a full S/G element in it. 9371 */ 9372 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 9373 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 9374 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 9375 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 9376 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 9377 download_consts[SG_SIZEOF] = sg_size; 9378 download_consts[PKT_OVERRUN_BUFOFFSET] = 9379 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 9380 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 9381 download_consts[CACHELINE_MASK] = cacheline_mask; 9382 cur_patch = patches; 9383 downloaded = 0; 9384 skip_addr = 0; 9385 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 9386 ahd_outw(ahd, PRGMCNT, 0); 9387 9388 for (i = 0; i < sizeof(seqprog)/4; i++) { 9389 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 9390 /* 9391 * Don't download this instruction as it 9392 * is in a patch that was removed. 9393 */ 9394 continue; 9395 } 9396 /* 9397 * Move through the CS table until we find a CS 9398 * that might apply to this instruction. 9399 */ 9400 for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) { 9401 if (critical_sections[cur_cs].end <= i) { 9402 if (begin_set[cs_count] == TRUE 9403 && end_set[cs_count] == FALSE) { 9404 cs_table[cs_count].end = downloaded; 9405 end_set[cs_count] = TRUE; 9406 cs_count++; 9407 } 9408 continue; 9409 } 9410 if (critical_sections[cur_cs].begin <= i 9411 && begin_set[cs_count] == FALSE) { 9412 cs_table[cs_count].begin = downloaded; 9413 begin_set[cs_count] = TRUE; 9414 } 9415 break; 9416 } 9417 ahd_download_instr(ahd, i, download_consts); 9418 downloaded++; 9419 } 9420 9421 ahd->num_critical_sections = cs_count; 9422 if (cs_count != 0) { 9423 9424 cs_count *= sizeof(struct cs); 9425 ahd->critical_sections = kmalloc(cs_count, GFP_ATOMIC); 9426 if (ahd->critical_sections == NULL) 9427 panic("ahd_loadseq: Could not malloc"); 9428 memcpy(ahd->critical_sections, cs_table, cs_count); 9429 } 9430 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 9431 9432 if (bootverbose) { 9433 printk(" %d instructions downloaded\n", downloaded); 9434 printk("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 9435 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 9436 } 9437 } 9438 9439 static int 9440 ahd_check_patch(struct ahd_softc *ahd, const struct patch **start_patch, 9441 u_int start_instr, u_int *skip_addr) 9442 { 9443 const struct patch *cur_patch; 9444 const struct patch *last_patch; 9445 u_int num_patches; 9446 9447 num_patches = ARRAY_SIZE(patches); 9448 last_patch = &patches[num_patches]; 9449 cur_patch = *start_patch; 9450 9451 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 9452 9453 if (cur_patch->patch_func(ahd) == 0) { 9454 9455 /* Start rejecting code */ 9456 *skip_addr = start_instr + cur_patch->skip_instr; 9457 cur_patch += cur_patch->skip_patch; 9458 } else { 9459 /* Accepted this patch. Advance to the next 9460 * one and wait for our intruction pointer to 9461 * hit this point. 9462 */ 9463 cur_patch++; 9464 } 9465 } 9466 9467 *start_patch = cur_patch; 9468 if (start_instr < *skip_addr) 9469 /* Still skipping */ 9470 return (0); 9471 9472 return (1); 9473 } 9474 9475 static u_int 9476 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 9477 { 9478 const struct patch *cur_patch; 9479 int address_offset; 9480 u_int skip_addr; 9481 u_int i; 9482 9483 address_offset = 0; 9484 cur_patch = patches; 9485 skip_addr = 0; 9486 9487 for (i = 0; i < address;) { 9488 9489 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 9490 9491 if (skip_addr > i) { 9492 int end_addr; 9493 9494 end_addr = min(address, skip_addr); 9495 address_offset += end_addr - i; 9496 i = skip_addr; 9497 } else { 9498 i++; 9499 } 9500 } 9501 return (address - address_offset); 9502 } 9503 9504 static void 9505 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 9506 { 9507 union ins_formats instr; 9508 struct ins_format1 *fmt1_ins; 9509 struct ins_format3 *fmt3_ins; 9510 u_int opcode; 9511 9512 /* 9513 * The firmware is always compiled into a little endian format. 9514 */ 9515 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 9516 9517 fmt1_ins = &instr.format1; 9518 fmt3_ins = NULL; 9519 9520 /* Pull the opcode */ 9521 opcode = instr.format1.opcode; 9522 switch (opcode) { 9523 case AIC_OP_JMP: 9524 case AIC_OP_JC: 9525 case AIC_OP_JNC: 9526 case AIC_OP_CALL: 9527 case AIC_OP_JNE: 9528 case AIC_OP_JNZ: 9529 case AIC_OP_JE: 9530 case AIC_OP_JZ: 9531 { 9532 fmt3_ins = &instr.format3; 9533 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 9534 } 9535 /* fall through */ 9536 case AIC_OP_OR: 9537 case AIC_OP_AND: 9538 case AIC_OP_XOR: 9539 case AIC_OP_ADD: 9540 case AIC_OP_ADC: 9541 case AIC_OP_BMOV: 9542 if (fmt1_ins->parity != 0) { 9543 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 9544 } 9545 fmt1_ins->parity = 0; 9546 /* fall through */ 9547 case AIC_OP_ROL: 9548 { 9549 int i, count; 9550 9551 /* Calculate odd parity for the instruction */ 9552 for (i = 0, count = 0; i < 31; i++) { 9553 uint32_t mask; 9554 9555 mask = 0x01 << i; 9556 if ((instr.integer & mask) != 0) 9557 count++; 9558 } 9559 if ((count & 0x01) == 0) 9560 instr.format1.parity = 1; 9561 9562 /* The sequencer is a little endian cpu */ 9563 instr.integer = ahd_htole32(instr.integer); 9564 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 9565 break; 9566 } 9567 default: 9568 panic("Unknown opcode encountered in seq program"); 9569 break; 9570 } 9571 } 9572 9573 static int 9574 ahd_probe_stack_size(struct ahd_softc *ahd) 9575 { 9576 int last_probe; 9577 9578 last_probe = 0; 9579 while (1) { 9580 int i; 9581 9582 /* 9583 * We avoid using 0 as a pattern to avoid 9584 * confusion if the stack implementation 9585 * "back-fills" with zeros when "poping' 9586 * entries. 9587 */ 9588 for (i = 1; i <= last_probe+1; i++) { 9589 ahd_outb(ahd, STACK, i & 0xFF); 9590 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 9591 } 9592 9593 /* Verify */ 9594 for (i = last_probe+1; i > 0; i--) { 9595 u_int stack_entry; 9596 9597 stack_entry = ahd_inb(ahd, STACK) 9598 |(ahd_inb(ahd, STACK) << 8); 9599 if (stack_entry != i) 9600 goto sized; 9601 } 9602 last_probe++; 9603 } 9604 sized: 9605 return (last_probe); 9606 } 9607 9608 int 9609 ahd_print_register(const ahd_reg_parse_entry_t *table, u_int num_entries, 9610 const char *name, u_int address, u_int value, 9611 u_int *cur_column, u_int wrap_point) 9612 { 9613 int printed; 9614 u_int printed_mask; 9615 9616 if (cur_column != NULL && *cur_column >= wrap_point) { 9617 printk("\n"); 9618 *cur_column = 0; 9619 } 9620 printed = printk("%s[0x%x]", name, value); 9621 if (table == NULL) { 9622 printed += printk(" "); 9623 *cur_column += printed; 9624 return (printed); 9625 } 9626 printed_mask = 0; 9627 while (printed_mask != 0xFF) { 9628 int entry; 9629 9630 for (entry = 0; entry < num_entries; entry++) { 9631 if (((value & table[entry].mask) 9632 != table[entry].value) 9633 || ((printed_mask & table[entry].mask) 9634 == table[entry].mask)) 9635 continue; 9636 9637 printed += printk("%s%s", 9638 printed_mask == 0 ? ":(" : "|", 9639 table[entry].name); 9640 printed_mask |= table[entry].mask; 9641 9642 break; 9643 } 9644 if (entry >= num_entries) 9645 break; 9646 } 9647 if (printed_mask != 0) 9648 printed += printk(") "); 9649 else 9650 printed += printk(" "); 9651 if (cur_column != NULL) 9652 *cur_column += printed; 9653 return (printed); 9654 } 9655 9656 void 9657 ahd_dump_card_state(struct ahd_softc *ahd) 9658 { 9659 struct scb *scb; 9660 ahd_mode_state saved_modes; 9661 u_int dffstat; 9662 int paused; 9663 u_int scb_index; 9664 u_int saved_scb_index; 9665 u_int cur_col; 9666 int i; 9667 9668 if (ahd_is_paused(ahd)) { 9669 paused = 1; 9670 } else { 9671 paused = 0; 9672 ahd_pause(ahd); 9673 } 9674 saved_modes = ahd_save_modes(ahd); 9675 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 9676 printk(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 9677 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 9678 ahd_name(ahd), 9679 ahd_inw(ahd, CURADDR), 9680 ahd_build_mode_state(ahd, ahd->saved_src_mode, 9681 ahd->saved_dst_mode)); 9682 if (paused) 9683 printk("Card was paused\n"); 9684 9685 if (ahd_check_cmdcmpltqueues(ahd)) 9686 printk("Completions are pending\n"); 9687 9688 /* 9689 * Mode independent registers. 9690 */ 9691 cur_col = 0; 9692 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50); 9693 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50); 9694 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50); 9695 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 9696 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 9697 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 9698 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 9699 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 9700 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 9701 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 9702 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 9703 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 9704 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 9705 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 9706 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 9707 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 9708 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 9709 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 9710 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50); 9711 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT), 9712 &cur_col, 50); 9713 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50); 9714 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID), 9715 &cur_col, 50); 9716 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 9717 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 9718 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 9719 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 9720 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 9721 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 9722 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 9723 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 9724 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 9725 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 9726 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 9727 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 9728 printk("\n"); 9729 printk("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 9730 "CURRSCB 0x%x NEXTSCB 0x%x\n", 9731 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 9732 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 9733 ahd_inw(ahd, NEXTSCB)); 9734 cur_col = 0; 9735 /* QINFIFO */ 9736 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 9737 CAM_LUN_WILDCARD, SCB_LIST_NULL, 9738 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 9739 saved_scb_index = ahd_get_scbptr(ahd); 9740 printk("Pending list:"); 9741 i = 0; 9742 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9743 if (i++ > AHD_SCB_MAX) 9744 break; 9745 cur_col = printk("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb), 9746 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT)); 9747 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 9748 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL), 9749 &cur_col, 60); 9750 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID), 9751 &cur_col, 60); 9752 } 9753 printk("\nTotal %d\n", i); 9754 9755 printk("Kernel Free SCB list: "); 9756 i = 0; 9757 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 9758 struct scb *list_scb; 9759 9760 list_scb = scb; 9761 do { 9762 printk("%d ", SCB_GET_TAG(list_scb)); 9763 list_scb = LIST_NEXT(list_scb, collision_links); 9764 } while (list_scb && i++ < AHD_SCB_MAX); 9765 } 9766 9767 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 9768 if (i++ > AHD_SCB_MAX) 9769 break; 9770 printk("%d ", SCB_GET_TAG(scb)); 9771 } 9772 printk("\n"); 9773 9774 printk("Sequencer Complete DMA-inprog list: "); 9775 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 9776 i = 0; 9777 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9778 ahd_set_scbptr(ahd, scb_index); 9779 printk("%d ", scb_index); 9780 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9781 } 9782 printk("\n"); 9783 9784 printk("Sequencer Complete list: "); 9785 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 9786 i = 0; 9787 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9788 ahd_set_scbptr(ahd, scb_index); 9789 printk("%d ", scb_index); 9790 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9791 } 9792 printk("\n"); 9793 9794 9795 printk("Sequencer DMA-Up and Complete list: "); 9796 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 9797 i = 0; 9798 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9799 ahd_set_scbptr(ahd, scb_index); 9800 printk("%d ", scb_index); 9801 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9802 } 9803 printk("\n"); 9804 printk("Sequencer On QFreeze and Complete list: "); 9805 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD); 9806 i = 0; 9807 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9808 ahd_set_scbptr(ahd, scb_index); 9809 printk("%d ", scb_index); 9810 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9811 } 9812 printk("\n"); 9813 ahd_set_scbptr(ahd, saved_scb_index); 9814 dffstat = ahd_inb(ahd, DFFSTAT); 9815 for (i = 0; i < 2; i++) { 9816 #ifdef AHD_DEBUG 9817 struct scb *fifo_scb; 9818 #endif 9819 u_int fifo_scbptr; 9820 9821 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 9822 fifo_scbptr = ahd_get_scbptr(ahd); 9823 printk("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n", 9824 ahd_name(ahd), i, 9825 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 9826 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); 9827 cur_col = 0; 9828 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 9829 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 9830 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 9831 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 9832 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 9833 &cur_col, 50); 9834 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 9835 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 9836 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 9837 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 9838 if (cur_col > 50) { 9839 printk("\n"); 9840 cur_col = 0; 9841 } 9842 cur_col += printk("SHADDR = 0x%x%x, SHCNT = 0x%x ", 9843 ahd_inl(ahd, SHADDR+4), 9844 ahd_inl(ahd, SHADDR), 9845 (ahd_inb(ahd, SHCNT) 9846 | (ahd_inb(ahd, SHCNT + 1) << 8) 9847 | (ahd_inb(ahd, SHCNT + 2) << 16))); 9848 if (cur_col > 50) { 9849 printk("\n"); 9850 cur_col = 0; 9851 } 9852 cur_col += printk("HADDR = 0x%x%x, HCNT = 0x%x ", 9853 ahd_inl(ahd, HADDR+4), 9854 ahd_inl(ahd, HADDR), 9855 (ahd_inb(ahd, HCNT) 9856 | (ahd_inb(ahd, HCNT + 1) << 8) 9857 | (ahd_inb(ahd, HCNT + 2) << 16))); 9858 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 9859 #ifdef AHD_DEBUG 9860 if ((ahd_debug & AHD_SHOW_SG) != 0) { 9861 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 9862 if (fifo_scb != NULL) 9863 ahd_dump_sglist(fifo_scb); 9864 } 9865 #endif 9866 } 9867 printk("\nLQIN: "); 9868 for (i = 0; i < 20; i++) 9869 printk("0x%x ", ahd_inb(ahd, LQIN + i)); 9870 printk("\n"); 9871 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 9872 printk("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 9873 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 9874 ahd_inb(ahd, OPTIONMODE)); 9875 printk("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 9876 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 9877 ahd_inb(ahd, MAXCMDCNT)); 9878 printk("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n", 9879 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID), 9880 ahd_inb(ahd, SAVED_LUN)); 9881 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 9882 printk("\n"); 9883 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 9884 cur_col = 0; 9885 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50); 9886 printk("\n"); 9887 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 9888 printk("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 9889 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 9890 ahd_inw(ahd, DINDEX)); 9891 printk("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 9892 ahd_name(ahd), ahd_get_scbptr(ahd), 9893 ahd_inw_scbram(ahd, SCB_NEXT), 9894 ahd_inw_scbram(ahd, SCB_NEXT2)); 9895 printk("CDB %x %x %x %x %x %x\n", 9896 ahd_inb_scbram(ahd, SCB_CDB_STORE), 9897 ahd_inb_scbram(ahd, SCB_CDB_STORE+1), 9898 ahd_inb_scbram(ahd, SCB_CDB_STORE+2), 9899 ahd_inb_scbram(ahd, SCB_CDB_STORE+3), 9900 ahd_inb_scbram(ahd, SCB_CDB_STORE+4), 9901 ahd_inb_scbram(ahd, SCB_CDB_STORE+5)); 9902 printk("STACK:"); 9903 for (i = 0; i < ahd->stack_size; i++) { 9904 ahd->saved_stack[i] = 9905 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 9906 printk(" 0x%x", ahd->saved_stack[i]); 9907 } 9908 for (i = ahd->stack_size-1; i >= 0; i--) { 9909 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 9910 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 9911 } 9912 printk("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 9913 ahd_restore_modes(ahd, saved_modes); 9914 if (paused == 0) 9915 ahd_unpause(ahd); 9916 } 9917 9918 #if 0 9919 void 9920 ahd_dump_scbs(struct ahd_softc *ahd) 9921 { 9922 ahd_mode_state saved_modes; 9923 u_int saved_scb_index; 9924 int i; 9925 9926 saved_modes = ahd_save_modes(ahd); 9927 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 9928 saved_scb_index = ahd_get_scbptr(ahd); 9929 for (i = 0; i < AHD_SCB_MAX; i++) { 9930 ahd_set_scbptr(ahd, i); 9931 printk("%3d", i); 9932 printk("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 9933 ahd_inb_scbram(ahd, SCB_CONTROL), 9934 ahd_inb_scbram(ahd, SCB_SCSIID), 9935 ahd_inw_scbram(ahd, SCB_NEXT), 9936 ahd_inw_scbram(ahd, SCB_NEXT2), 9937 ahd_inl_scbram(ahd, SCB_SGPTR), 9938 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR)); 9939 } 9940 printk("\n"); 9941 ahd_set_scbptr(ahd, saved_scb_index); 9942 ahd_restore_modes(ahd, saved_modes); 9943 } 9944 #endif /* 0 */ 9945 9946 /**************************** Flexport Logic **********************************/ 9947 /* 9948 * Read count 16bit words from 16bit word address start_addr from the 9949 * SEEPROM attached to the controller, into buf, using the controller's 9950 * SEEPROM reading state machine. Optionally treat the data as a byte 9951 * stream in terms of byte order. 9952 */ 9953 int 9954 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 9955 u_int start_addr, u_int count, int bytestream) 9956 { 9957 u_int cur_addr; 9958 u_int end_addr; 9959 int error; 9960 9961 /* 9962 * If we never make it through the loop even once, 9963 * we were passed invalid arguments. 9964 */ 9965 error = EINVAL; 9966 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9967 end_addr = start_addr + count; 9968 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 9969 9970 ahd_outb(ahd, SEEADR, cur_addr); 9971 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 9972 9973 error = ahd_wait_seeprom(ahd); 9974 if (error) 9975 break; 9976 if (bytestream != 0) { 9977 uint8_t *bytestream_ptr; 9978 9979 bytestream_ptr = (uint8_t *)buf; 9980 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); 9981 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); 9982 } else { 9983 /* 9984 * ahd_inw() already handles machine byte order. 9985 */ 9986 *buf = ahd_inw(ahd, SEEDAT); 9987 } 9988 buf++; 9989 } 9990 return (error); 9991 } 9992 9993 /* 9994 * Write count 16bit words from buf, into SEEPROM attache to the 9995 * controller starting at 16bit word address start_addr, using the 9996 * controller's SEEPROM writing state machine. 9997 */ 9998 int 9999 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 10000 u_int start_addr, u_int count) 10001 { 10002 u_int cur_addr; 10003 u_int end_addr; 10004 int error; 10005 int retval; 10006 10007 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 10008 error = ENOENT; 10009 10010 /* Place the chip into write-enable mode */ 10011 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 10012 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 10013 error = ahd_wait_seeprom(ahd); 10014 if (error) 10015 return (error); 10016 10017 /* 10018 * Write the data. If we don't get through the loop at 10019 * least once, the arguments were invalid. 10020 */ 10021 retval = EINVAL; 10022 end_addr = start_addr + count; 10023 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 10024 ahd_outw(ahd, SEEDAT, *buf++); 10025 ahd_outb(ahd, SEEADR, cur_addr); 10026 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 10027 10028 retval = ahd_wait_seeprom(ahd); 10029 if (retval) 10030 break; 10031 } 10032 10033 /* 10034 * Disable writes. 10035 */ 10036 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 10037 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 10038 error = ahd_wait_seeprom(ahd); 10039 if (error) 10040 return (error); 10041 return (retval); 10042 } 10043 10044 /* 10045 * Wait ~100us for the serial eeprom to satisfy our request. 10046 */ 10047 static int 10048 ahd_wait_seeprom(struct ahd_softc *ahd) 10049 { 10050 int cnt; 10051 10052 cnt = 5000; 10053 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 10054 ahd_delay(5); 10055 10056 if (cnt == 0) 10057 return (ETIMEDOUT); 10058 return (0); 10059 } 10060 10061 /* 10062 * Validate the two checksums in the per_channel 10063 * vital product data struct. 10064 */ 10065 static int 10066 ahd_verify_vpd_cksum(struct vpd_config *vpd) 10067 { 10068 int i; 10069 int maxaddr; 10070 uint32_t checksum; 10071 uint8_t *vpdarray; 10072 10073 vpdarray = (uint8_t *)vpd; 10074 maxaddr = offsetof(struct vpd_config, vpd_checksum); 10075 checksum = 0; 10076 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) 10077 checksum = checksum + vpdarray[i]; 10078 if (checksum == 0 10079 || (-checksum & 0xFF) != vpd->vpd_checksum) 10080 return (0); 10081 10082 checksum = 0; 10083 maxaddr = offsetof(struct vpd_config, checksum); 10084 for (i = offsetof(struct vpd_config, default_target_flags); 10085 i < maxaddr; i++) 10086 checksum = checksum + vpdarray[i]; 10087 if (checksum == 0 10088 || (-checksum & 0xFF) != vpd->checksum) 10089 return (0); 10090 return (1); 10091 } 10092 10093 int 10094 ahd_verify_cksum(struct seeprom_config *sc) 10095 { 10096 int i; 10097 int maxaddr; 10098 uint32_t checksum; 10099 uint16_t *scarray; 10100 10101 maxaddr = (sizeof(*sc)/2) - 1; 10102 checksum = 0; 10103 scarray = (uint16_t *)sc; 10104 10105 for (i = 0; i < maxaddr; i++) 10106 checksum = checksum + scarray[i]; 10107 if (checksum == 0 10108 || (checksum & 0xFFFF) != sc->checksum) { 10109 return (0); 10110 } else { 10111 return (1); 10112 } 10113 } 10114 10115 int 10116 ahd_acquire_seeprom(struct ahd_softc *ahd) 10117 { 10118 /* 10119 * We should be able to determine the SEEPROM type 10120 * from the flexport logic, but unfortunately not 10121 * all implementations have this logic and there is 10122 * no programatic method for determining if the logic 10123 * is present. 10124 */ 10125 return (1); 10126 #if 0 10127 uint8_t seetype; 10128 int error; 10129 10130 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 10131 if (error != 0 10132 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 10133 return (0); 10134 return (1); 10135 #endif 10136 } 10137 10138 void 10139 ahd_release_seeprom(struct ahd_softc *ahd) 10140 { 10141 /* Currently a no-op */ 10142 } 10143 10144 /* 10145 * Wait at most 2 seconds for flexport arbitration to succeed. 10146 */ 10147 static int 10148 ahd_wait_flexport(struct ahd_softc *ahd) 10149 { 10150 int cnt; 10151 10152 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 10153 cnt = 1000000 * 2 / 5; 10154 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 10155 ahd_delay(5); 10156 10157 if (cnt == 0) 10158 return (ETIMEDOUT); 10159 return (0); 10160 } 10161 10162 int 10163 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 10164 { 10165 int error; 10166 10167 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 10168 if (addr > 7) 10169 panic("ahd_write_flexport: address out of range"); 10170 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 10171 error = ahd_wait_flexport(ahd); 10172 if (error != 0) 10173 return (error); 10174 ahd_outb(ahd, BRDDAT, value); 10175 ahd_flush_device_writes(ahd); 10176 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 10177 ahd_flush_device_writes(ahd); 10178 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 10179 ahd_flush_device_writes(ahd); 10180 ahd_outb(ahd, BRDCTL, 0); 10181 ahd_flush_device_writes(ahd); 10182 return (0); 10183 } 10184 10185 int 10186 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 10187 { 10188 int error; 10189 10190 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 10191 if (addr > 7) 10192 panic("ahd_read_flexport: address out of range"); 10193 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 10194 error = ahd_wait_flexport(ahd); 10195 if (error != 0) 10196 return (error); 10197 *value = ahd_inb(ahd, BRDDAT); 10198 ahd_outb(ahd, BRDCTL, 0); 10199 ahd_flush_device_writes(ahd); 10200 return (0); 10201 } 10202 10203 /************************* Target Mode ****************************************/ 10204 #ifdef AHD_TARGET_MODE 10205 cam_status 10206 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 10207 struct ahd_tmode_tstate **tstate, 10208 struct ahd_tmode_lstate **lstate, 10209 int notfound_failure) 10210 { 10211 10212 if ((ahd->features & AHD_TARGETMODE) == 0) 10213 return (CAM_REQ_INVALID); 10214 10215 /* 10216 * Handle the 'black hole' device that sucks up 10217 * requests to unattached luns on enabled targets. 10218 */ 10219 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 10220 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 10221 *tstate = NULL; 10222 *lstate = ahd->black_hole; 10223 } else { 10224 u_int max_id; 10225 10226 max_id = (ahd->features & AHD_WIDE) ? 16 : 8; 10227 if (ccb->ccb_h.target_id >= max_id) 10228 return (CAM_TID_INVALID); 10229 10230 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 10231 return (CAM_LUN_INVALID); 10232 10233 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 10234 *lstate = NULL; 10235 if (*tstate != NULL) 10236 *lstate = 10237 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 10238 } 10239 10240 if (notfound_failure != 0 && *lstate == NULL) 10241 return (CAM_PATH_INVALID); 10242 10243 return (CAM_REQ_CMP); 10244 } 10245 10246 void 10247 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 10248 { 10249 #if NOT_YET 10250 struct ahd_tmode_tstate *tstate; 10251 struct ahd_tmode_lstate *lstate; 10252 struct ccb_en_lun *cel; 10253 cam_status status; 10254 u_int target; 10255 u_int lun; 10256 u_int target_mask; 10257 u_long s; 10258 char channel; 10259 10260 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 10261 /*notfound_failure*/FALSE); 10262 10263 if (status != CAM_REQ_CMP) { 10264 ccb->ccb_h.status = status; 10265 return; 10266 } 10267 10268 if ((ahd->features & AHD_MULTIROLE) != 0) { 10269 u_int our_id; 10270 10271 our_id = ahd->our_id; 10272 if (ccb->ccb_h.target_id != our_id) { 10273 if ((ahd->features & AHD_MULTI_TID) != 0 10274 && (ahd->flags & AHD_INITIATORROLE) != 0) { 10275 /* 10276 * Only allow additional targets if 10277 * the initiator role is disabled. 10278 * The hardware cannot handle a re-select-in 10279 * on the initiator id during a re-select-out 10280 * on a different target id. 10281 */ 10282 status = CAM_TID_INVALID; 10283 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 10284 || ahd->enabled_luns > 0) { 10285 /* 10286 * Only allow our target id to change 10287 * if the initiator role is not configured 10288 * and there are no enabled luns which 10289 * are attached to the currently registered 10290 * scsi id. 10291 */ 10292 status = CAM_TID_INVALID; 10293 } 10294 } 10295 } 10296 10297 if (status != CAM_REQ_CMP) { 10298 ccb->ccb_h.status = status; 10299 return; 10300 } 10301 10302 /* 10303 * We now have an id that is valid. 10304 * If we aren't in target mode, switch modes. 10305 */ 10306 if ((ahd->flags & AHD_TARGETROLE) == 0 10307 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 10308 u_long s; 10309 10310 printk("Configuring Target Mode\n"); 10311 ahd_lock(ahd, &s); 10312 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 10313 ccb->ccb_h.status = CAM_BUSY; 10314 ahd_unlock(ahd, &s); 10315 return; 10316 } 10317 ahd->flags |= AHD_TARGETROLE; 10318 if ((ahd->features & AHD_MULTIROLE) == 0) 10319 ahd->flags &= ~AHD_INITIATORROLE; 10320 ahd_pause(ahd); 10321 ahd_loadseq(ahd); 10322 ahd_restart(ahd); 10323 ahd_unlock(ahd, &s); 10324 } 10325 cel = &ccb->cel; 10326 target = ccb->ccb_h.target_id; 10327 lun = ccb->ccb_h.target_lun; 10328 channel = SIM_CHANNEL(ahd, sim); 10329 target_mask = 0x01 << target; 10330 if (channel == 'B') 10331 target_mask <<= 8; 10332 10333 if (cel->enable != 0) { 10334 u_int scsiseq1; 10335 10336 /* Are we already enabled?? */ 10337 if (lstate != NULL) { 10338 xpt_print_path(ccb->ccb_h.path); 10339 printk("Lun already enabled\n"); 10340 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 10341 return; 10342 } 10343 10344 if (cel->grp6_len != 0 10345 || cel->grp7_len != 0) { 10346 /* 10347 * Don't (yet?) support vendor 10348 * specific commands. 10349 */ 10350 ccb->ccb_h.status = CAM_REQ_INVALID; 10351 printk("Non-zero Group Codes\n"); 10352 return; 10353 } 10354 10355 /* 10356 * Seems to be okay. 10357 * Setup our data structures. 10358 */ 10359 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 10360 tstate = ahd_alloc_tstate(ahd, target, channel); 10361 if (tstate == NULL) { 10362 xpt_print_path(ccb->ccb_h.path); 10363 printk("Couldn't allocate tstate\n"); 10364 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 10365 return; 10366 } 10367 } 10368 lstate = kzalloc(sizeof(*lstate), GFP_ATOMIC); 10369 if (lstate == NULL) { 10370 xpt_print_path(ccb->ccb_h.path); 10371 printk("Couldn't allocate lstate\n"); 10372 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 10373 return; 10374 } 10375 status = xpt_create_path(&lstate->path, /*periph*/NULL, 10376 xpt_path_path_id(ccb->ccb_h.path), 10377 xpt_path_target_id(ccb->ccb_h.path), 10378 xpt_path_lun_id(ccb->ccb_h.path)); 10379 if (status != CAM_REQ_CMP) { 10380 kfree(lstate); 10381 xpt_print_path(ccb->ccb_h.path); 10382 printk("Couldn't allocate path\n"); 10383 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 10384 return; 10385 } 10386 SLIST_INIT(&lstate->accept_tios); 10387 SLIST_INIT(&lstate->immed_notifies); 10388 ahd_lock(ahd, &s); 10389 ahd_pause(ahd); 10390 if (target != CAM_TARGET_WILDCARD) { 10391 tstate->enabled_luns[lun] = lstate; 10392 ahd->enabled_luns++; 10393 10394 if ((ahd->features & AHD_MULTI_TID) != 0) { 10395 u_int targid_mask; 10396 10397 targid_mask = ahd_inw(ahd, TARGID); 10398 targid_mask |= target_mask; 10399 ahd_outw(ahd, TARGID, targid_mask); 10400 ahd_update_scsiid(ahd, targid_mask); 10401 } else { 10402 u_int our_id; 10403 char channel; 10404 10405 channel = SIM_CHANNEL(ahd, sim); 10406 our_id = SIM_SCSI_ID(ahd, sim); 10407 10408 /* 10409 * This can only happen if selections 10410 * are not enabled 10411 */ 10412 if (target != our_id) { 10413 u_int sblkctl; 10414 char cur_channel; 10415 int swap; 10416 10417 sblkctl = ahd_inb(ahd, SBLKCTL); 10418 cur_channel = (sblkctl & SELBUSB) 10419 ? 'B' : 'A'; 10420 if ((ahd->features & AHD_TWIN) == 0) 10421 cur_channel = 'A'; 10422 swap = cur_channel != channel; 10423 ahd->our_id = target; 10424 10425 if (swap) 10426 ahd_outb(ahd, SBLKCTL, 10427 sblkctl ^ SELBUSB); 10428 10429 ahd_outb(ahd, SCSIID, target); 10430 10431 if (swap) 10432 ahd_outb(ahd, SBLKCTL, sblkctl); 10433 } 10434 } 10435 } else 10436 ahd->black_hole = lstate; 10437 /* Allow select-in operations */ 10438 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 10439 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 10440 scsiseq1 |= ENSELI; 10441 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 10442 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 10443 scsiseq1 |= ENSELI; 10444 ahd_outb(ahd, SCSISEQ1, scsiseq1); 10445 } 10446 ahd_unpause(ahd); 10447 ahd_unlock(ahd, &s); 10448 ccb->ccb_h.status = CAM_REQ_CMP; 10449 xpt_print_path(ccb->ccb_h.path); 10450 printk("Lun now enabled for target mode\n"); 10451 } else { 10452 struct scb *scb; 10453 int i, empty; 10454 10455 if (lstate == NULL) { 10456 ccb->ccb_h.status = CAM_LUN_INVALID; 10457 return; 10458 } 10459 10460 ahd_lock(ahd, &s); 10461 10462 ccb->ccb_h.status = CAM_REQ_CMP; 10463 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 10464 struct ccb_hdr *ccbh; 10465 10466 ccbh = &scb->io_ctx->ccb_h; 10467 if (ccbh->func_code == XPT_CONT_TARGET_IO 10468 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 10469 printk("CTIO pending\n"); 10470 ccb->ccb_h.status = CAM_REQ_INVALID; 10471 ahd_unlock(ahd, &s); 10472 return; 10473 } 10474 } 10475 10476 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 10477 printk("ATIOs pending\n"); 10478 ccb->ccb_h.status = CAM_REQ_INVALID; 10479 } 10480 10481 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 10482 printk("INOTs pending\n"); 10483 ccb->ccb_h.status = CAM_REQ_INVALID; 10484 } 10485 10486 if (ccb->ccb_h.status != CAM_REQ_CMP) { 10487 ahd_unlock(ahd, &s); 10488 return; 10489 } 10490 10491 xpt_print_path(ccb->ccb_h.path); 10492 printk("Target mode disabled\n"); 10493 xpt_free_path(lstate->path); 10494 kfree(lstate); 10495 10496 ahd_pause(ahd); 10497 /* Can we clean up the target too? */ 10498 if (target != CAM_TARGET_WILDCARD) { 10499 tstate->enabled_luns[lun] = NULL; 10500 ahd->enabled_luns--; 10501 for (empty = 1, i = 0; i < 8; i++) 10502 if (tstate->enabled_luns[i] != NULL) { 10503 empty = 0; 10504 break; 10505 } 10506 10507 if (empty) { 10508 ahd_free_tstate(ahd, target, channel, 10509 /*force*/FALSE); 10510 if (ahd->features & AHD_MULTI_TID) { 10511 u_int targid_mask; 10512 10513 targid_mask = ahd_inw(ahd, TARGID); 10514 targid_mask &= ~target_mask; 10515 ahd_outw(ahd, TARGID, targid_mask); 10516 ahd_update_scsiid(ahd, targid_mask); 10517 } 10518 } 10519 } else { 10520 10521 ahd->black_hole = NULL; 10522 10523 /* 10524 * We can't allow selections without 10525 * our black hole device. 10526 */ 10527 empty = TRUE; 10528 } 10529 if (ahd->enabled_luns == 0) { 10530 /* Disallow select-in */ 10531 u_int scsiseq1; 10532 10533 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 10534 scsiseq1 &= ~ENSELI; 10535 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 10536 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 10537 scsiseq1 &= ~ENSELI; 10538 ahd_outb(ahd, SCSISEQ1, scsiseq1); 10539 10540 if ((ahd->features & AHD_MULTIROLE) == 0) { 10541 printk("Configuring Initiator Mode\n"); 10542 ahd->flags &= ~AHD_TARGETROLE; 10543 ahd->flags |= AHD_INITIATORROLE; 10544 ahd_pause(ahd); 10545 ahd_loadseq(ahd); 10546 ahd_restart(ahd); 10547 /* 10548 * Unpaused. The extra unpause 10549 * that follows is harmless. 10550 */ 10551 } 10552 } 10553 ahd_unpause(ahd); 10554 ahd_unlock(ahd, &s); 10555 } 10556 #endif 10557 } 10558 10559 static void 10560 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 10561 { 10562 #if NOT_YET 10563 u_int scsiid_mask; 10564 u_int scsiid; 10565 10566 if ((ahd->features & AHD_MULTI_TID) == 0) 10567 panic("ahd_update_scsiid called on non-multitid unit\n"); 10568 10569 /* 10570 * Since we will rely on the TARGID mask 10571 * for selection enables, ensure that OID 10572 * in SCSIID is not set to some other ID 10573 * that we don't want to allow selections on. 10574 */ 10575 if ((ahd->features & AHD_ULTRA2) != 0) 10576 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 10577 else 10578 scsiid = ahd_inb(ahd, SCSIID); 10579 scsiid_mask = 0x1 << (scsiid & OID); 10580 if ((targid_mask & scsiid_mask) == 0) { 10581 u_int our_id; 10582 10583 /* ffs counts from 1 */ 10584 our_id = ffs(targid_mask); 10585 if (our_id == 0) 10586 our_id = ahd->our_id; 10587 else 10588 our_id--; 10589 scsiid &= TID; 10590 scsiid |= our_id; 10591 } 10592 if ((ahd->features & AHD_ULTRA2) != 0) 10593 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 10594 else 10595 ahd_outb(ahd, SCSIID, scsiid); 10596 #endif 10597 } 10598 10599 static void 10600 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 10601 { 10602 struct target_cmd *cmd; 10603 10604 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 10605 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 10606 10607 /* 10608 * Only advance through the queue if we 10609 * have the resources to process the command. 10610 */ 10611 if (ahd_handle_target_cmd(ahd, cmd) != 0) 10612 break; 10613 10614 cmd->cmd_valid = 0; 10615 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, 10616 ahd->shared_data_map.dmamap, 10617 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 10618 sizeof(struct target_cmd), 10619 BUS_DMASYNC_PREREAD); 10620 ahd->tqinfifonext++; 10621 10622 /* 10623 * Lazily update our position in the target mode incoming 10624 * command queue as seen by the sequencer. 10625 */ 10626 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 10627 u_int hs_mailbox; 10628 10629 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 10630 hs_mailbox &= ~HOST_TQINPOS; 10631 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 10632 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 10633 } 10634 } 10635 } 10636 10637 static int 10638 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 10639 { 10640 struct ahd_tmode_tstate *tstate; 10641 struct ahd_tmode_lstate *lstate; 10642 struct ccb_accept_tio *atio; 10643 uint8_t *byte; 10644 int initiator; 10645 int target; 10646 int lun; 10647 10648 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 10649 target = SCSIID_OUR_ID(cmd->scsiid); 10650 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 10651 10652 byte = cmd->bytes; 10653 tstate = ahd->enabled_targets[target]; 10654 lstate = NULL; 10655 if (tstate != NULL) 10656 lstate = tstate->enabled_luns[lun]; 10657 10658 /* 10659 * Commands for disabled luns go to the black hole driver. 10660 */ 10661 if (lstate == NULL) 10662 lstate = ahd->black_hole; 10663 10664 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 10665 if (atio == NULL) { 10666 ahd->flags |= AHD_TQINFIFO_BLOCKED; 10667 /* 10668 * Wait for more ATIOs from the peripheral driver for this lun. 10669 */ 10670 return (1); 10671 } else 10672 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 10673 #ifdef AHD_DEBUG 10674 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 10675 printk("Incoming command from %d for %d:%d%s\n", 10676 initiator, target, lun, 10677 lstate == ahd->black_hole ? "(Black Holed)" : ""); 10678 #endif 10679 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 10680 10681 if (lstate == ahd->black_hole) { 10682 /* Fill in the wildcards */ 10683 atio->ccb_h.target_id = target; 10684 atio->ccb_h.target_lun = lun; 10685 } 10686 10687 /* 10688 * Package it up and send it off to 10689 * whomever has this lun enabled. 10690 */ 10691 atio->sense_len = 0; 10692 atio->init_id = initiator; 10693 if (byte[0] != 0xFF) { 10694 /* Tag was included */ 10695 atio->tag_action = *byte++; 10696 atio->tag_id = *byte++; 10697 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 10698 } else { 10699 atio->ccb_h.flags = 0; 10700 } 10701 byte++; 10702 10703 /* Okay. Now determine the cdb size based on the command code */ 10704 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 10705 case 0: 10706 atio->cdb_len = 6; 10707 break; 10708 case 1: 10709 case 2: 10710 atio->cdb_len = 10; 10711 break; 10712 case 4: 10713 atio->cdb_len = 16; 10714 break; 10715 case 5: 10716 atio->cdb_len = 12; 10717 break; 10718 case 3: 10719 default: 10720 /* Only copy the opcode. */ 10721 atio->cdb_len = 1; 10722 printk("Reserved or VU command code type encountered\n"); 10723 break; 10724 } 10725 10726 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 10727 10728 atio->ccb_h.status |= CAM_CDB_RECVD; 10729 10730 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 10731 /* 10732 * We weren't allowed to disconnect. 10733 * We're hanging on the bus until a 10734 * continue target I/O comes in response 10735 * to this accept tio. 10736 */ 10737 #ifdef AHD_DEBUG 10738 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 10739 printk("Received Immediate Command %d:%d:%d - %p\n", 10740 initiator, target, lun, ahd->pending_device); 10741 #endif 10742 ahd->pending_device = lstate; 10743 ahd_freeze_ccb((union ccb *)atio); 10744 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 10745 } 10746 xpt_done((union ccb*)atio); 10747 return (0); 10748 } 10749 10750 #endif 10751