1/* 2 * Aic79xx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $FreeBSD$ 41 */ 42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $" 43 44/* 45 * This file is processed by the aic7xxx_asm utility for use in assembling 46 * firmware for the aic79xx family of SCSI host adapters as well as to generate 47 * a C header file for use in the kernel portion of the Aic79xx driver. 48 */ 49 50/* Register window Modes */ 51#define M_DFF0 0 52#define M_DFF1 1 53#define M_CCHAN 2 54#define M_SCSI 3 55#define M_CFG 4 56#define M_DST_SHIFT 4 57 58#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 59#define SET_MODE(src, dst) \ 60 SET_SRC_MODE src; \ 61 SET_DST_MODE dst; \ 62 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 63 mvi MK_MODE(src, dst) call set_mode_work_around; \ 64 } else { \ 65 mvi MODE_PTR, MK_MODE(src, dst); \ 66 } 67 68#define RESTORE_MODE(mode) \ 69 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 70 mov mode call set_mode_work_around; \ 71 } else { \ 72 mov MODE_PTR, mode; \ 73 } 74 75#define SET_SEQINTCODE(code) \ 76 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ 77 mvi code call set_seqint_work_around; \ 78 } else { \ 79 mvi SEQINTCODE, code; \ 80 } 81 82/* 83 * Mode Pointer 84 * Controls which of the 5, 512byte, address spaces should be used 85 * as the source and destination of any register accesses in our 86 * register window. 87 */ 88register MODE_PTR { 89 address 0x000 90 access_mode RW 91 field DST_MODE 0x70 92 field SRC_MODE 0x07 93 mode_pointer 94} 95 96const SRC_MODE_SHIFT 0 97const DST_MODE_SHIFT 4 98 99/* 100 * Host Interrupt Status 101 */ 102register INTSTAT { 103 address 0x001 104 access_mode RW 105 field HWERRINT 0x80 106 field BRKADRINT 0x40 107 field SWTMINT 0x20 108 field PCIINT 0x10 109 field SCSIINT 0x08 110 field SEQINT 0x04 111 field CMDCMPLT 0x02 112 field SPLTINT 0x01 113 mask INT_PEND 0xFF 114} 115 116/* 117 * Sequencer Interrupt Code 118 */ 119register SEQINTCODE { 120 address 0x002 121 access_mode RW 122 field { 123 NO_SEQINT, /* No seqint pending. */ 124 BAD_PHASE, /* unknown scsi bus phase */ 125 SEND_REJECT, /* sending a message reject */ 126 PROTO_VIOLATION, /* Protocol Violation */ 127 NO_MATCH, /* no cmd match for reconnect */ 128 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 129 PDATA_REINIT, /* 130 * Returned to data phase 131 * that requires data 132 * transfer pointers to be 133 * recalculated from the 134 * transfer residual. 135 */ 136 HOST_MSG_LOOP, /* 137 * The bus is ready for the 138 * host to perform another 139 * message transaction. This 140 * mechanism is used for things 141 * like sync/wide negotiation 142 * that require a kernel based 143 * message state engine. 144 */ 145 BAD_STATUS, /* Bad status from target */ 146 DATA_OVERRUN, /* 147 * Target attempted to write 148 * beyond the bounds of its 149 * command. 150 */ 151 MKMSG_FAILED, /* 152 * Target completed command 153 * without honoring our ATN 154 * request to issue a message. 155 */ 156 MISSED_BUSFREE, /* 157 * The sequencer never saw 158 * the bus go free after 159 * either a command complete 160 * or disconnect message. 161 */ 162 DUMP_CARD_STATE, 163 ILLEGAL_PHASE, 164 INVALID_SEQINT, 165 CFG4ISTAT_INTR, 166 STATUS_OVERRUN, 167 CFG4OVERRUN, 168 ENTERING_NONPACK, 169 TASKMGMT_FUNC_COMPLETE, /* 170 * Task management function 171 * request completed with 172 * an expected busfree. 173 */ 174 TASKMGMT_CMD_CMPLT_OKAY, /* 175 * A command with a non-zero 176 * task management function 177 * has completed via the normal 178 * command completion method 179 * for commands with a zero 180 * task management function. 181 * This happens when an attempt 182 * to abort a command loses 183 * the race for the command to 184 * complete normally. 185 */ 186 TRACEPOINT0, 187 TRACEPOINT1, 188 TRACEPOINT2, 189 TRACEPOINT3, 190 SAW_HWERR, 191 BAD_SCB_STATUS 192 } 193} 194 195/* 196 * Clear Host Interrupt 197 */ 198register CLRINT { 199 address 0x003 200 access_mode WO 201 count 19 202 field CLRHWERRINT 0x80 /* Rev B or greater */ 203 field CLRBRKADRINT 0x40 204 field CLRSWTMINT 0x20 205 field CLRPCIINT 0x10 206 field CLRSCSIINT 0x08 207 field CLRSEQINT 0x04 208 field CLRCMDINT 0x02 209 field CLRSPLTINT 0x01 210} 211 212/* 213 * Error Register 214 */ 215register ERROR { 216 address 0x004 217 access_mode RO 218 field CIOPARERR 0x80 219 field CIOACCESFAIL 0x40 /* Rev B or greater */ 220 field MPARERR 0x20 221 field DPARERR 0x10 222 field SQPARERR 0x08 223 field ILLOPCODE 0x04 224 field DSCTMOUT 0x02 225} 226 227/* 228 * Clear Error 229 */ 230register CLRERR { 231 address 0x004 232 access_mode WO 233 field CLRCIOPARERR 0x80 234 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 235 field CLRMPARERR 0x20 236 field CLRDPARERR 0x10 237 field CLRSQPARERR 0x08 238 field CLRILLOPCODE 0x04 239 field CLRDSCTMOUT 0x02 240} 241 242/* 243 * Host Control Register 244 * Overall host control of the device. 245 */ 246register HCNTRL { 247 address 0x005 248 access_mode RW 249 count 12 250 field SEQ_RESET 0x80 /* Rev B or greater */ 251 field POWRDN 0x40 252 field SWINT 0x10 253 field SWTIMER_START_B 0x08 /* Rev B or greater */ 254 field PAUSE 0x04 255 field INTEN 0x02 256 field CHIPRST 0x01 257 field CHIPRSTACK 0x01 258} 259 260/* 261 * Host New SCB Queue Offset 262 */ 263register HNSCB_QOFF { 264 address 0x006 265 access_mode RW 266 size 2 267 count 2 268} 269 270/* 271 * Host Empty SCB Queue Offset 272 */ 273register HESCB_QOFF { 274 address 0x008 275 access_mode RW 276 count 2 277} 278 279/* 280 * Host Mailbox 281 */ 282register HS_MAILBOX { 283 address 0x00B 284 access_mode RW 285 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 286 mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */ 287} 288 289/* 290 * Sequencer Interupt Status 291 */ 292register SEQINTSTAT { 293 address 0x00C 294 count 1 295 access_mode RO 296 field SEQ_SWTMRTO 0x10 297 field SEQ_SEQINT 0x08 298 field SEQ_SCSIINT 0x04 299 field SEQ_PCIINT 0x02 300 field SEQ_SPLTINT 0x01 301} 302 303/* 304 * Clear SEQ Interrupt 305 */ 306register CLRSEQINTSTAT { 307 address 0x00C 308 access_mode WO 309 field CLRSEQ_SWTMRTO 0x10 310 field CLRSEQ_SEQINT 0x08 311 field CLRSEQ_SCSIINT 0x04 312 field CLRSEQ_PCIINT 0x02 313 field CLRSEQ_SPLTINT 0x01 314} 315 316/* 317 * Software Timer 318 */ 319register SWTIMER { 320 address 0x00E 321 access_mode RW 322 size 2 323} 324 325/* 326 * SEQ New SCB Queue Offset 327 */ 328register SNSCB_QOFF { 329 address 0x010 330 access_mode RW 331 size 2 332 modes M_CCHAN 333} 334 335/* 336 * SEQ Empty SCB Queue Offset 337 */ 338register SESCB_QOFF { 339 address 0x012 340 count 2 341 access_mode RW 342 modes M_CCHAN 343} 344 345/* 346 * SEQ Done SCB Queue Offset 347 */ 348register SDSCB_QOFF { 349 address 0x014 350 access_mode RW 351 modes M_CCHAN 352 size 2 353} 354 355/* 356 * Queue Offset Control & Status 357 */ 358register QOFF_CTLSTA { 359 address 0x016 360 access_mode RW 361 modes M_CCHAN 362 field EMPTY_SCB_AVAIL 0x80 363 field NEW_SCB_AVAIL 0x40 364 field SDSCB_ROLLOVR 0x20 365 field HS_MAILBOX_ACT 0x10 366 field SCB_QSIZE 0x0F { 367 SCB_QSIZE_4, 368 SCB_QSIZE_8, 369 SCB_QSIZE_16, 370 SCB_QSIZE_32, 371 SCB_QSIZE_64, 372 SCB_QSIZE_128, 373 SCB_QSIZE_256, 374 SCB_QSIZE_512, 375 SCB_QSIZE_1024, 376 SCB_QSIZE_2048, 377 SCB_QSIZE_4096, 378 SCB_QSIZE_8192, 379 SCB_QSIZE_16384 380 } 381} 382 383/* 384 * Interrupt Control 385 */ 386register INTCTL { 387 address 0x018 388 access_mode RW 389 field SWTMINTMASK 0x80 390 field SWTMINTEN 0x40 391 field SWTIMER_START 0x20 392 field AUTOCLRCMDINT 0x10 393 field PCIINTEN 0x08 394 field SCSIINTEN 0x04 395 field SEQINTEN 0x02 396 field SPLTINTEN 0x01 397} 398 399/* 400 * Data FIFO Control 401 */ 402register DFCNTRL { 403 address 0x019 404 access_mode RW 405 modes M_DFF0, M_DFF1 406 count 11 407 field PRELOADEN 0x80 408 field SCSIENWRDIS 0x40 /* Rev B only. */ 409 field SCSIEN 0x20 410 field SCSIENACK 0x20 411 field HDMAEN 0x08 412 field HDMAENACK 0x08 413 field DIRECTION 0x04 414 field DIRECTIONACK 0x04 415 field FIFOFLUSH 0x02 416 field FIFOFLUSHACK 0x02 417 field DIRECTIONEN 0x01 418} 419 420/* 421 * Device Space Command 0 422 */ 423register DSCOMMAND0 { 424 address 0x019 425 count 1 426 access_mode RW 427 modes M_CFG 428 field CACHETHEN 0x80 /* Cache Threshold enable */ 429 field DPARCKEN 0x40 /* Data Parity Check Enable */ 430 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 431 field EXTREQLCK 0x10 /* External Request Lock */ 432 field DISABLE_TWATE 0x02 /* Rev B or greater */ 433 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 434} 435 436/* 437 * Data FIFO Status 438 */ 439register DFSTATUS { 440 address 0x01A 441 access_mode RO 442 modes M_DFF0, M_DFF1 443 field PRELOAD_AVAIL 0x80 444 field PKT_PRELOAD_AVAIL 0x40 445 field MREQPEND 0x10 446 field HDONE 0x08 447 field DFTHRESH 0x04 448 field FIFOFULL 0x02 449 field FIFOEMP 0x01 450} 451 452/* 453 * S/G Cache Pointer 454 */ 455register SG_CACHE_PRE { 456 address 0x01B 457 access_mode WO 458 modes M_DFF0, M_DFF1 459 field SG_ADDR_MASK 0xf8 460 field ODD_SEG 0x04 461 field LAST_SEG 0x02 462} 463 464register SG_CACHE_SHADOW { 465 address 0x01B 466 access_mode RO 467 modes M_DFF0, M_DFF1 468 field SG_ADDR_MASK 0xf8 469 field ODD_SEG 0x04 470 field LAST_SEG 0x02 471 field LAST_SEG_DONE 0x01 472} 473 474/* 475 * Arbiter Control 476 */ 477register ARBCTL { 478 address 0x01B 479 access_mode RW 480 modes M_CFG 481 field RESET_HARB 0x80 482 field RETRY_SWEN 0x08 483 field USE_TIME 0x07 484} 485 486/* 487 * Data Channel Host Address 488 */ 489register HADDR { 490 address 0x070 491 access_mode RW 492 size 8 493 modes M_DFF0, M_DFF1 494} 495 496/* 497 * Host Overlay DMA Address 498 */ 499register HODMAADR { 500 address 0x070 501 access_mode RW 502 size 8 503 modes M_SCSI 504} 505 506/* 507 * PCI PLL Delay. 508 */ 509register PLLDELAY { 510 address 0x070 511 access_mode RW 512 size 1 513 modes M_CFG 514 field SPLIT_DROP_REQ 0x80 515} 516 517/* 518 * Data Channel Host Count 519 */ 520register HCNT { 521 address 0x078 522 access_mode RW 523 size 3 524 modes M_DFF0, M_DFF1 525} 526 527/* 528 * Host Overlay DMA Count 529 */ 530register HODMACNT { 531 address 0x078 532 access_mode RW 533 size 2 534 modes M_SCSI 535} 536 537/* 538 * Host Overlay DMA Enable 539 */ 540register HODMAEN { 541 address 0x07A 542 access_mode RW 543 modes M_SCSI 544} 545 546/* 547 * Scatter/Gather Host Address 548 */ 549register SGHADDR { 550 address 0x07C 551 access_mode RW 552 size 8 553 modes M_DFF0, M_DFF1 554} 555 556/* 557 * SCB Host Address 558 */ 559register SCBHADDR { 560 address 0x07C 561 access_mode RW 562 size 8 563 modes M_CCHAN 564} 565 566/* 567 * Scatter/Gather Host Count 568 */ 569register SGHCNT { 570 address 0x084 571 access_mode RW 572 modes M_DFF0, M_DFF1 573} 574 575/* 576 * SCB Host Count 577 */ 578register SCBHCNT { 579 address 0x084 580 access_mode RW 581 modes M_CCHAN 582} 583 584/* 585 * Data FIFO Threshold 586 */ 587register DFF_THRSH { 588 address 0x088 589 access_mode RW 590 modes M_CFG 591 count 1 592 field WR_DFTHRSH 0x70 { 593 WR_DFTHRSH_MIN, 594 WR_DFTHRSH_25, 595 WR_DFTHRSH_50, 596 WR_DFTHRSH_63, 597 WR_DFTHRSH_75, 598 WR_DFTHRSH_85, 599 WR_DFTHRSH_90, 600 WR_DFTHRSH_MAX 601 } 602 field RD_DFTHRSH 0x07 { 603 RD_DFTHRSH_MIN, 604 RD_DFTHRSH_25, 605 RD_DFTHRSH_50, 606 RD_DFTHRSH_63, 607 RD_DFTHRSH_75, 608 RD_DFTHRSH_85, 609 RD_DFTHRSH_90, 610 RD_DFTHRSH_MAX 611 } 612} 613 614/* 615 * ROM Address 616 */ 617register ROMADDR { 618 address 0x08A 619 access_mode RW 620 size 3 621} 622 623/* 624 * ROM Control 625 */ 626register ROMCNTRL { 627 address 0x08D 628 access_mode RW 629 field ROMOP 0xE0 630 field ROMSPD 0x18 631 field REPEAT 0x02 632 field RDY 0x01 633} 634 635/* 636 * ROM Data 637 */ 638register ROMDATA { 639 address 0x08E 640 access_mode RW 641} 642 643/* 644 * Data Channel Receive Message 0 645 */ 646register DCHRXMSG0 { 647 address 0x090 648 access_mode RO 649 modes M_DFF0, M_DFF1 650 field CDNUM 0xF8 651 field CFNUM 0x07 652} 653 654/* 655 * CMC Recieve Message 0 656 */ 657register CMCRXMSG0 { 658 address 0x090 659 access_mode RO 660 modes M_CCHAN 661 field CDNUM 0xF8 662 field CFNUM 0x07 663} 664 665/* 666 * Overlay Recieve Message 0 667 */ 668register OVLYRXMSG0 { 669 address 0x090 670 access_mode RO 671 modes M_SCSI 672 field CDNUM 0xF8 673 field CFNUM 0x07 674} 675 676/* 677 * Relaxed Order Enable 678 */ 679register ROENABLE { 680 address 0x090 681 access_mode RW 682 modes M_CFG 683 field MSIROEN 0x20 684 field OVLYROEN 0x10 685 field CMCROEN 0x08 686 field SGROEN 0x04 687 field DCH1ROEN 0x02 688 field DCH0ROEN 0x01 689} 690 691/* 692 * Data Channel Receive Message 1 693 */ 694register DCHRXMSG1 { 695 address 0x091 696 access_mode RO 697 modes M_DFF0, M_DFF1 698 field CBNUM 0xFF 699} 700 701/* 702 * CMC Recieve Message 1 703 */ 704register CMCRXMSG1 { 705 address 0x091 706 access_mode RO 707 modes M_CCHAN 708 field CBNUM 0xFF 709} 710 711/* 712 * Overlay Recieve Message 1 713 */ 714register OVLYRXMSG1 { 715 address 0x091 716 access_mode RO 717 modes M_SCSI 718 field CBNUM 0xFF 719} 720 721/* 722 * No Snoop Enable 723 */ 724register NSENABLE { 725 address 0x091 726 access_mode RW 727 modes M_CFG 728 field MSINSEN 0x20 729 field OVLYNSEN 0x10 730 field CMCNSEN 0x08 731 field SGNSEN 0x04 732 field DCH1NSEN 0x02 733 field DCH0NSEN 0x01 734} 735 736/* 737 * Data Channel Receive Message 2 738 */ 739register DCHRXMSG2 { 740 address 0x092 741 access_mode RO 742 modes M_DFF0, M_DFF1 743 field MINDEX 0xFF 744} 745 746/* 747 * CMC Recieve Message 2 748 */ 749register CMCRXMSG2 { 750 address 0x092 751 access_mode RO 752 modes M_CCHAN 753 field MINDEX 0xFF 754} 755 756/* 757 * Overlay Recieve Message 2 758 */ 759register OVLYRXMSG2 { 760 address 0x092 761 access_mode RO 762 modes M_SCSI 763 field MINDEX 0xFF 764} 765 766/* 767 * Outstanding Split Transactions 768 */ 769register OST { 770 address 0x092 771 access_mode RW 772 modes M_CFG 773} 774 775/* 776 * Data Channel Receive Message 3 777 */ 778register DCHRXMSG3 { 779 address 0x093 780 access_mode RO 781 modes M_DFF0, M_DFF1 782 field MCLASS 0x0F 783} 784 785/* 786 * CMC Recieve Message 3 787 */ 788register CMCRXMSG3 { 789 address 0x093 790 access_mode RO 791 modes M_CCHAN 792 field MCLASS 0x0F 793} 794 795/* 796 * Overlay Recieve Message 3 797 */ 798register OVLYRXMSG3 { 799 address 0x093 800 access_mode RO 801 modes M_SCSI 802 field MCLASS 0x0F 803} 804 805/* 806 * PCI-X Control 807 */ 808register PCIXCTL { 809 address 0x093 810 access_mode RW 811 modes M_CFG 812 count 1 813 field SERRPULSE 0x80 814 field UNEXPSCIEN 0x20 815 field SPLTSMADIS 0x10 816 field SPLTSTADIS 0x08 817 field SRSPDPEEN 0x04 818 field TSCSERREN 0x02 819 field CMPABCDIS 0x01 820} 821 822/* 823 * CMC Sequencer Byte Count 824 */ 825register CMCSEQBCNT { 826 address 0x094 827 access_mode RO 828 modes M_CCHAN 829} 830 831/* 832 * Overlay Sequencer Byte Count 833 */ 834register OVLYSEQBCNT { 835 address 0x094 836 access_mode RO 837 modes M_SCSI 838} 839 840/* 841 * Data Channel Sequencer Byte Count 842 */ 843register DCHSEQBCNT { 844 address 0x094 845 access_mode RO 846 size 2 847 modes M_DFF0, M_DFF1 848} 849 850/* 851 * Data Channel Split Status 0 852 */ 853register DCHSPLTSTAT0 { 854 address 0x096 855 access_mode RW 856 modes M_DFF0, M_DFF1 857 count 2 858 field STAETERM 0x80 859 field SCBCERR 0x40 860 field SCADERR 0x20 861 field SCDATBUCKET 0x10 862 field CNTNOTCMPLT 0x08 863 field RXOVRUN 0x04 864 field RXSCEMSG 0x02 865 field RXSPLTRSP 0x01 866} 867 868/* 869 * CMC Split Status 0 870 */ 871register CMCSPLTSTAT0 { 872 address 0x096 873 access_mode RW 874 modes M_CCHAN 875 field STAETERM 0x80 876 field SCBCERR 0x40 877 field SCADERR 0x20 878 field SCDATBUCKET 0x10 879 field CNTNOTCMPLT 0x08 880 field RXOVRUN 0x04 881 field RXSCEMSG 0x02 882 field RXSPLTRSP 0x01 883} 884 885/* 886 * Overlay Split Status 0 887 */ 888register OVLYSPLTSTAT0 { 889 address 0x096 890 access_mode RW 891 modes M_SCSI 892 field STAETERM 0x80 893 field SCBCERR 0x40 894 field SCADERR 0x20 895 field SCDATBUCKET 0x10 896 field CNTNOTCMPLT 0x08 897 field RXOVRUN 0x04 898 field RXSCEMSG 0x02 899 field RXSPLTRSP 0x01 900} 901 902/* 903 * Data Channel Split Status 1 904 */ 905register DCHSPLTSTAT1 { 906 address 0x097 907 access_mode RW 908 modes M_DFF0, M_DFF1 909 count 2 910 field RXDATABUCKET 0x01 911} 912 913/* 914 * CMC Split Status 1 915 */ 916register CMCSPLTSTAT1 { 917 address 0x097 918 access_mode RW 919 modes M_CCHAN 920 field RXDATABUCKET 0x01 921} 922 923/* 924 * Overlay Split Status 1 925 */ 926register OVLYSPLTSTAT1 { 927 address 0x097 928 access_mode RW 929 modes M_SCSI 930 field RXDATABUCKET 0x01 931} 932 933/* 934 * S/G Receive Message 0 935 */ 936register SGRXMSG0 { 937 address 0x098 938 access_mode RO 939 modes M_DFF0, M_DFF1 940 field CDNUM 0xF8 941 field CFNUM 0x07 942} 943 944/* 945 * S/G Receive Message 1 946 */ 947register SGRXMSG1 { 948 address 0x099 949 access_mode RO 950 modes M_DFF0, M_DFF1 951 field CBNUM 0xFF 952} 953 954/* 955 * S/G Receive Message 2 956 */ 957register SGRXMSG2 { 958 address 0x09A 959 access_mode RO 960 modes M_DFF0, M_DFF1 961 field MINDEX 0xFF 962} 963 964/* 965 * S/G Receive Message 3 966 */ 967register SGRXMSG3 { 968 address 0x09B 969 access_mode RO 970 modes M_DFF0, M_DFF1 971 field MCLASS 0x0F 972} 973 974/* 975 * Slave Split Out Address 0 976 */ 977register SLVSPLTOUTADR0 { 978 address 0x098 979 access_mode RO 980 modes M_SCSI 981 field LOWER_ADDR 0x7F 982} 983 984/* 985 * Slave Split Out Address 1 986 */ 987register SLVSPLTOUTADR1 { 988 address 0x099 989 access_mode RO 990 modes M_SCSI 991 field REQ_DNUM 0xF8 992 field REQ_FNUM 0x07 993} 994 995/* 996 * Slave Split Out Address 2 997 */ 998register SLVSPLTOUTADR2 { 999 address 0x09A 1000 access_mode RO 1001 modes M_SCSI 1002 field REQ_BNUM 0xFF 1003} 1004 1005/* 1006 * Slave Split Out Address 3 1007 */ 1008register SLVSPLTOUTADR3 { 1009 address 0x09B 1010 access_mode RO 1011 modes M_SCSI 1012 field RLXORD 020 1013 field TAG_NUM 0x1F 1014} 1015 1016/* 1017 * SG Sequencer Byte Count 1018 */ 1019register SGSEQBCNT { 1020 address 0x09C 1021 access_mode RO 1022 modes M_DFF0, M_DFF1 1023} 1024 1025/* 1026 * Slave Split Out Attribute 0 1027 */ 1028register SLVSPLTOUTATTR0 { 1029 address 0x09C 1030 access_mode RO 1031 modes M_SCSI 1032 field LOWER_BCNT 0xFF 1033} 1034 1035/* 1036 * Slave Split Out Attribute 1 1037 */ 1038register SLVSPLTOUTATTR1 { 1039 address 0x09D 1040 access_mode RO 1041 modes M_SCSI 1042 field CMPLT_DNUM 0xF8 1043 field CMPLT_FNUM 0x07 1044} 1045 1046/* 1047 * Slave Split Out Attribute 2 1048 */ 1049register SLVSPLTOUTATTR2 { 1050 address 0x09E 1051 access_mode RO 1052 size 2 1053 modes M_SCSI 1054 field CMPLT_BNUM 0xFF 1055} 1056/* 1057 * S/G Split Status 0 1058 */ 1059register SGSPLTSTAT0 { 1060 address 0x09E 1061 access_mode RW 1062 modes M_DFF0, M_DFF1 1063 count 2 1064 field STAETERM 0x80 1065 field SCBCERR 0x40 1066 field SCADERR 0x20 1067 field SCDATBUCKET 0x10 1068 field CNTNOTCMPLT 0x08 1069 field RXOVRUN 0x04 1070 field RXSCEMSG 0x02 1071 field RXSPLTRSP 0x01 1072} 1073 1074/* 1075 * S/G Split Status 1 1076 */ 1077register SGSPLTSTAT1 { 1078 address 0x09F 1079 access_mode RW 1080 modes M_DFF0, M_DFF1 1081 count 2 1082 field RXDATABUCKET 0x01 1083} 1084 1085/* 1086 * Special Function 1087 */ 1088register SFUNCT { 1089 address 0x09f 1090 access_mode RW 1091 modes M_CFG 1092 field TEST_GROUP 0xF0 1093 field TEST_NUM 0x0F 1094} 1095 1096/* 1097 * Data FIFO 0 PCI Status 1098 */ 1099register DF0PCISTAT { 1100 address 0x0A0 1101 access_mode RW 1102 modes M_CFG 1103 count 1 1104 field DPE 0x80 1105 field SSE 0x40 1106 field RMA 0x20 1107 field RTA 0x10 1108 field SCAAPERR 0x08 1109 field RDPERR 0x04 1110 field TWATERR 0x02 1111 field DPR 0x01 1112} 1113 1114/* 1115 * Data FIFO 1 PCI Status 1116 */ 1117register DF1PCISTAT { 1118 address 0x0A1 1119 access_mode RW 1120 modes M_CFG 1121 field DPE 0x80 1122 field SSE 0x40 1123 field RMA 0x20 1124 field RTA 0x10 1125 field SCAAPERR 0x08 1126 field RDPERR 0x04 1127 field TWATERR 0x02 1128 field DPR 0x01 1129} 1130 1131/* 1132 * S/G PCI Status 1133 */ 1134register SGPCISTAT { 1135 address 0x0A2 1136 access_mode RW 1137 modes M_CFG 1138 field DPE 0x80 1139 field SSE 0x40 1140 field RMA 0x20 1141 field RTA 0x10 1142 field SCAAPERR 0x08 1143 field RDPERR 0x04 1144 field DPR 0x01 1145} 1146 1147/* 1148 * CMC PCI Status 1149 */ 1150register CMCPCISTAT { 1151 address 0x0A3 1152 access_mode RW 1153 modes M_CFG 1154 field DPE 0x80 1155 field SSE 0x40 1156 field RMA 0x20 1157 field RTA 0x10 1158 field SCAAPERR 0x08 1159 field RDPERR 0x04 1160 field TWATERR 0x02 1161 field DPR 0x01 1162} 1163 1164/* 1165 * Overlay PCI Status 1166 */ 1167register OVLYPCISTAT { 1168 address 0x0A4 1169 access_mode RW 1170 modes M_CFG 1171 field DPE 0x80 1172 field SSE 0x40 1173 field RMA 0x20 1174 field RTA 0x10 1175 field SCAAPERR 0x08 1176 field RDPERR 0x04 1177 field DPR 0x01 1178} 1179 1180/* 1181 * PCI Status for MSI Master DMA Transfer 1182 */ 1183register MSIPCISTAT { 1184 address 0x0A6 1185 access_mode RW 1186 modes M_CFG 1187 field SSE 0x40 1188 field RMA 0x20 1189 field RTA 0x10 1190 field CLRPENDMSI 0x08 1191 field TWATERR 0x02 1192 field DPR 0x01 1193} 1194 1195/* 1196 * PCI Status for Target 1197 */ 1198register TARGPCISTAT { 1199 address 0x0A7 1200 access_mode RW 1201 modes M_CFG 1202 count 5 1203 field DPE 0x80 1204 field SSE 0x40 1205 field STA 0x08 1206 field TWATERR 0x02 1207} 1208 1209/* 1210 * LQ Packet In 1211 * The last LQ Packet recieved 1212 */ 1213register LQIN { 1214 address 0x020 1215 access_mode RW 1216 size 20 1217 count 2 1218 modes M_DFF0, M_DFF1, M_SCSI 1219} 1220 1221/* 1222 * SCB Type Pointer 1223 * SCB offset for Target Mode SCB type information 1224 */ 1225register TYPEPTR { 1226 address 0x020 1227 access_mode RW 1228 modes M_CFG 1229} 1230 1231/* 1232 * Queue Tag Pointer 1233 * SCB offset to the Two Byte tag identifier used for target mode. 1234 */ 1235register TAGPTR { 1236 address 0x021 1237 access_mode RW 1238 modes M_CFG 1239} 1240 1241/* 1242 * Logical Unit Number Pointer 1243 * SCB offset to the LSB (little endian) of the lun field. 1244 */ 1245register LUNPTR { 1246 address 0x022 1247 access_mode RW 1248 modes M_CFG 1249 count 2 1250} 1251 1252/* 1253 * Data Length Pointer 1254 * SCB offset for the 4 byte data length field in target mode. 1255 */ 1256register DATALENPTR { 1257 address 0x023 1258 access_mode RW 1259 modes M_CFG 1260} 1261 1262/* 1263 * Status Length Pointer 1264 * SCB offset to the two byte status field in target SCBs. 1265 */ 1266register STATLENPTR { 1267 address 0x024 1268 access_mode RW 1269 modes M_CFG 1270} 1271 1272/* 1273 * Command Length Pointer 1274 * Scb offset for the CDB length field in initiator SCBs. 1275 */ 1276register CMDLENPTR { 1277 address 0x025 1278 access_mode RW 1279 modes M_CFG 1280 count 1 1281} 1282 1283/* 1284 * Task Attribute Pointer 1285 * Scb offset for the byte field specifying the attribute byte 1286 * to be used in command packets. 1287 */ 1288register ATTRPTR { 1289 address 0x026 1290 access_mode RW 1291 modes M_CFG 1292 count 1 1293} 1294 1295/* 1296 * Task Management Flags Pointer 1297 * Scb offset for the byte field specifying the attribute flags 1298 * byte to be used in command packets. 1299 */ 1300register FLAGPTR { 1301 address 0x027 1302 access_mode RW 1303 modes M_CFG 1304 count 1 1305} 1306 1307/* 1308 * Command Pointer 1309 * Scb offset for the first byte in the CDB for initiator SCBs. 1310 */ 1311register CMDPTR { 1312 address 0x028 1313 access_mode RW 1314 modes M_CFG 1315 count 1 1316} 1317 1318/* 1319 * Queue Next Pointer 1320 * Scb offset for the 2 byte "next scb link". 1321 */ 1322register QNEXTPTR { 1323 address 0x029 1324 access_mode RW 1325 modes M_CFG 1326 count 1 1327} 1328 1329/* 1330 * SCSI ID Pointer 1331 * Scb offset to the value to place in the SCSIID register 1332 * during target mode connections. 1333 */ 1334register IDPTR { 1335 address 0x02A 1336 access_mode RW 1337 modes M_CFG 1338} 1339 1340/* 1341 * Command Aborted Byte Pointer 1342 * Offset to the SCB flags field that includes the 1343 * "SCB aborted" status bit. 1344 */ 1345register ABRTBYTEPTR { 1346 address 0x02B 1347 access_mode RW 1348 modes M_CFG 1349 count 1 1350} 1351 1352/* 1353 * Command Aborted Bit Pointer 1354 * Bit offset in the SCB flags field for "SCB aborted" status. 1355 */ 1356register ABRTBITPTR { 1357 address 0x02C 1358 access_mode RW 1359 modes M_CFG 1360 count 1 1361} 1362 1363/* 1364 * Rev B or greater. 1365 */ 1366register MAXCMDBYTES { 1367 address 0x02D 1368 access_mode RW 1369 modes M_CFG 1370} 1371 1372/* 1373 * Rev B or greater. 1374 */ 1375register MAXCMD2RCV { 1376 address 0x02E 1377 access_mode RW 1378 modes M_CFG 1379} 1380 1381/* 1382 * Rev B or greater. 1383 */ 1384register SHORTTHRESH { 1385 address 0x02F 1386 access_mode RW 1387 modes M_CFG 1388} 1389 1390/* 1391 * Logical Unit Number Length 1392 * The length, in bytes, of the SCB lun field. 1393 */ 1394register LUNLEN { 1395 address 0x030 1396 access_mode RW 1397 modes M_CFG 1398 count 2 1399 mask ILUNLEN 0x0F 1400 mask TLUNLEN 0xF0 1401} 1402const LUNLEN_SINGLE_LEVEL_LUN 0xF 1403 1404/* 1405 * CDB Limit 1406 * The size, in bytes, of the embedded CDB field in initator SCBs. 1407 */ 1408register CDBLIMIT { 1409 address 0x031 1410 access_mode RW 1411 modes M_CFG 1412 count 1 1413} 1414 1415/* 1416 * Maximum Commands 1417 * The maximum number of commands to issue during a 1418 * single packetized connection. 1419 */ 1420register MAXCMD { 1421 address 0x032 1422 access_mode RW 1423 modes M_CFG 1424 count 9 1425} 1426 1427/* 1428 * Maximum Command Counter 1429 * The number of commands already sent during this connection 1430 */ 1431register MAXCMDCNT { 1432 address 0x033 1433 access_mode RW 1434 modes M_CFG 1435} 1436 1437/* 1438 * LQ Packet Reserved Bytes 1439 * The bytes to be sent in the currently reserved fileds 1440 * of all LQ packets. 1441 */ 1442register LQRSVD01 { 1443 address 0x034 1444 access_mode RW 1445 modes M_SCSI 1446} 1447register LQRSVD16 { 1448 address 0x035 1449 access_mode RW 1450 modes M_SCSI 1451} 1452register LQRSVD17 { 1453 address 0x036 1454 access_mode RW 1455 modes M_SCSI 1456} 1457 1458/* 1459 * Command Reserved 0 1460 * The byte to be sent for the reserved byte 0 of 1461 * outgoing command packets. 1462 */ 1463register CMDRSVD0 { 1464 address 0x037 1465 access_mode RW 1466 modes M_CFG 1467} 1468 1469/* 1470 * LQ Manager Control 0 1471 */ 1472register LQCTL0 { 1473 address 0x038 1474 access_mode RW 1475 modes M_CFG 1476 field LQITARGCLT 0xC0 1477 field LQIINITGCLT 0x30 1478 field LQ0TARGCLT 0x0C 1479 field LQ0INITGCLT 0x03 1480} 1481 1482/* 1483 * LQ Manager Control 1 1484 */ 1485register LQCTL1 { 1486 address 0x038 1487 access_mode RW 1488 modes M_DFF0, M_DFF1, M_SCSI 1489 count 2 1490 field PCI2PCI 0x04 1491 field SINGLECMD 0x02 1492 field ABORTPENDING 0x01 1493} 1494 1495/* 1496 * LQ Manager Control 2 1497 */ 1498register LQCTL2 { 1499 address 0x039 1500 access_mode RW 1501 modes M_DFF0, M_DFF1, M_SCSI 1502 count 5 1503 field LQIRETRY 0x80 1504 field LQICONTINUE 0x40 1505 field LQITOIDLE 0x20 1506 field LQIPAUSE 0x10 1507 field LQORETRY 0x08 1508 field LQOCONTINUE 0x04 1509 field LQOTOIDLE 0x02 1510 field LQOPAUSE 0x01 1511} 1512 1513/* 1514 * SCSI RAM BIST0 1515 */ 1516register SCSBIST0 { 1517 address 0x039 1518 access_mode RW 1519 modes M_CFG 1520 field GSBISTERR 0x40 1521 field GSBISTDONE 0x20 1522 field GSBISTRUN 0x10 1523 field OSBISTERR 0x04 1524 field OSBISTDONE 0x02 1525 field OSBISTRUN 0x01 1526} 1527 1528/* 1529 * SCSI Sequence Control0 1530 */ 1531register SCSISEQ0 { 1532 address 0x03A 1533 access_mode RW 1534 modes M_DFF0, M_DFF1, M_SCSI 1535 field TEMODEO 0x80 1536 field ENSELO 0x40 1537 field ENARBO 0x20 1538 field FORCEBUSFREE 0x10 1539 field SCSIRSTO 0x01 1540} 1541 1542/* 1543 * SCSI RAM BIST 1 1544 */ 1545register SCSBIST1 { 1546 address 0x03A 1547 access_mode RW 1548 modes M_CFG 1549 field NTBISTERR 0x04 1550 field NTBISTDONE 0x02 1551 field NTBISTRUN 0x01 1552} 1553 1554/* 1555 * SCSI Sequence Control 1 1556 */ 1557register SCSISEQ1 { 1558 address 0x03B 1559 access_mode RW 1560 modes M_DFF0, M_DFF1, M_SCSI 1561 count 8 1562 field MANUALCTL 0x40 1563 field ENSELI 0x20 1564 field ENRSELI 0x10 1565 field MANUALP 0x0C 1566 field ENAUTOATNP 0x02 1567 field ALTSTIM 0x01 1568} 1569 1570/* 1571 * SCSI Transfer Control 0 1572 */ 1573register SXFRCTL0 { 1574 address 0x03C 1575 access_mode RW 1576 modes M_SCSI 1577 field DFON 0x80 1578 field DFPEXP 0x40 1579 field BIOSCANCELEN 0x10 1580 field SPIOEN 0x08 1581} 1582 1583/* 1584 * SCSI Transfer Control 1 1585 */ 1586register SXFRCTL1 { 1587 address 0x03D 1588 access_mode RW 1589 modes M_SCSI 1590 field BITBUCKET 0x80 1591 field ENSACHK 0x40 1592 field ENSPCHK 0x20 1593 field STIMESEL 0x18 1594 field ENSTIMER 0x04 1595 field ACTNEGEN 0x02 1596 field STPWEN 0x01 1597} 1598 1599/* 1600 * SCSI Transfer Control 2 1601 */ 1602register SXFRCTL2 { 1603 address 0x03E 1604 access_mode RW 1605 modes M_SCSI 1606 field AUTORSTDIS 0x10 1607 field CMDDMAEN 0x08 1608 field ASU 0x07 1609} 1610 1611/* 1612 * SCSI Bus Initiator IDs 1613 * Bitmask of observed initiators on the bus. 1614 */ 1615register BUSINITID { 1616 address 0x03C 1617 access_mode RW 1618 modes M_CFG 1619 size 2 1620} 1621 1622/* 1623 * Data Length Counters 1624 * Packet byte counter. 1625 */ 1626register DLCOUNT { 1627 address 0x03C 1628 access_mode RW 1629 modes M_DFF0, M_DFF1 1630 size 3 1631} 1632 1633/* 1634 * Data FIFO Status 1635 */ 1636register DFFSTAT { 1637 address 0x03F 1638 access_mode RW 1639 modes M_SCSI 1640 field FIFO1FREE 0x20 1641 field FIFO0FREE 0x10 1642 /* 1643 * On the B, this enum only works 1644 * in the read direction. For writes, 1645 * you must use the B version of the 1646 * CURRFIFO_0 definition which is defined 1647 * as a constant outside of this register 1648 * definition to avoid confusing the 1649 * register pretty printing code. 1650 */ 1651 enum CURRFIFO 0x03 { 1652 CURRFIFO_0, 1653 CURRFIFO_1, 1654 CURRFIFO_NONE 0x3 1655 } 1656} 1657 1658const B_CURRFIFO_0 0x2 1659 1660/* 1661 * SCSI Bus Target IDs 1662 * Bitmask of observed targets on the bus. 1663 */ 1664register BUSTARGID { 1665 address 0x03E 1666 access_mode RW 1667 modes M_CFG 1668 size 2 1669} 1670 1671/* 1672 * SCSI Control Signal Out 1673 */ 1674register SCSISIGO { 1675 address 0x040 1676 access_mode RW 1677 modes M_DFF0, M_DFF1, M_SCSI 1678 field CDO 0x80 1679 field IOO 0x40 1680 field MSGO 0x20 1681 field ATNO 0x10 1682 field SELO 0x08 1683 field BSYO 0x04 1684 field REQO 0x02 1685 field ACKO 0x01 1686/* 1687 * Possible phases to write into SCSISIG0 1688 */ 1689 enum PHASE_MASK CDO|IOO|MSGO { 1690 P_DATAOUT 0x0, 1691 P_DATAIN IOO, 1692 P_DATAOUT_DT P_DATAOUT|MSGO, 1693 P_DATAIN_DT P_DATAIN|MSGO, 1694 P_COMMAND CDO, 1695 P_MESGOUT CDO|MSGO, 1696 P_STATUS CDO|IOO, 1697 P_MESGIN CDO|IOO|MSGO 1698 } 1699} 1700 1701/* 1702 * SCSI Control Signal In 1703 */ 1704register SCSISIGI { 1705 address 0x041 1706 access_mode RO 1707 modes M_DFF0, M_DFF1, M_SCSI 1708 field CDI 0x80 1709 field IOI 0x40 1710 field MSGI 0x20 1711 field ATNI 0x10 1712 field SELI 0x08 1713 field BSYI 0x04 1714 field REQI 0x02 1715 field ACKI 0x01 1716/* 1717 * Possible phases in SCSISIGI 1718 */ 1719 enum PHASE_MASK CDO|IOO|MSGO { 1720 P_DATAOUT 0x0, 1721 P_DATAIN IOO, 1722 P_DATAOUT_DT P_DATAOUT|MSGO, 1723 P_DATAIN_DT P_DATAIN|MSGO, 1724 P_COMMAND CDO, 1725 P_MESGOUT CDO|MSGO, 1726 P_STATUS CDO|IOO, 1727 P_MESGIN CDO|IOO|MSGO 1728 } 1729} 1730 1731/* 1732 * Multiple Target IDs 1733 * Bitmask of ids to respond as a target. 1734 */ 1735register MULTARGID { 1736 address 0x040 1737 access_mode RW 1738 modes M_CFG 1739 size 2 1740 count 2 1741} 1742 1743/* 1744 * SCSI Phase 1745 */ 1746register SCSIPHASE { 1747 address 0x042 1748 access_mode RO 1749 modes M_DFF0, M_DFF1, M_SCSI 1750 field STATUS_PHASE 0x20 1751 field COMMAND_PHASE 0x10 1752 field MSG_IN_PHASE 0x08 1753 field MSG_OUT_PHASE 0x04 1754 field DATA_PHASE_MASK 0x03 { 1755 DATA_OUT_PHASE 0x01, 1756 DATA_IN_PHASE 0x02 1757 } 1758} 1759 1760/* 1761 * SCSI Data 0 Image 1762 */ 1763register SCSIDAT0_IMG { 1764 address 0x043 1765 access_mode RW 1766 modes M_DFF0, M_DFF1, M_SCSI 1767} 1768 1769/* 1770 * SCSI Latched Data 1771 */ 1772register SCSIDAT { 1773 address 0x044 1774 access_mode RW 1775 modes M_DFF0, M_DFF1, M_SCSI 1776 size 2 1777} 1778 1779/* 1780 * SCSI Data Bus 1781 */ 1782register SCSIBUS { 1783 address 0x046 1784 access_mode RW 1785 modes M_DFF0, M_DFF1, M_SCSI 1786 size 2 1787} 1788 1789/* 1790 * Target ID In 1791 */ 1792register TARGIDIN { 1793 address 0x048 1794 access_mode RO 1795 modes M_DFF0, M_DFF1, M_SCSI 1796 count 2 1797 field CLKOUT 0x80 1798 field TARGID 0x0F 1799} 1800 1801/* 1802 * Selection/Reselection ID 1803 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 1804 * device did not set its own ID. 1805 */ 1806register SELID { 1807 address 0x049 1808 access_mode RW 1809 modes M_DFF0, M_DFF1, M_SCSI 1810 field SELID_MASK 0xf0 1811 field ONEBIT 0x08 1812} 1813 1814/* 1815 * SCSI Block Control 1816 * Controls Bus type and channel selection. SELWIDE allows for the 1817 * coexistence of 8bit and 16bit devices on a wide bus. 1818 */ 1819register SBLKCTL { 1820 address 0x04A 1821 access_mode RW 1822 modes M_DFF0, M_DFF1, M_SCSI 1823 field DIAGLEDEN 0x80 1824 field DIAGLEDON 0x40 1825 field ENAB40 0x08 /* LVD transceiver active */ 1826 field ENAB20 0x04 /* SE/HVD transceiver active */ 1827 field SELWIDE 0x02 1828} 1829 1830/* 1831 * Option Mode 1832 */ 1833register OPTIONMODE { 1834 address 0x04A 1835 access_mode RW 1836 modes M_CFG 1837 count 4 1838 field BIOSCANCTL 0x80 1839 field AUTOACKEN 0x40 1840 field BIASCANCTL 0x20 1841 field BUSFREEREV 0x10 1842 field ENDGFORMCHK 0x04 1843 field AUTO_MSGOUT_DE 0x02 1844 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 1845} 1846 1847/* 1848 * SCSI Status 0 1849 */ 1850register SSTAT0 { 1851 address 0x04B 1852 access_mode RO 1853 modes M_DFF0, M_DFF1, M_SCSI 1854 field TARGET 0x80 /* Board acting as target */ 1855 field SELDO 0x40 /* Selection Done */ 1856 field SELDI 0x20 /* Board has been selected */ 1857 field SELINGO 0x10 /* Selection In Progress */ 1858 field IOERR 0x08 /* LVD Tranceiver mode changed */ 1859 field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1860 field SPIORDY 0x02 /* SCSI PIO Ready */ 1861 field ARBDO 0x01 /* Arbitration Done Out */ 1862} 1863 1864/* 1865 * Clear SCSI Interrupt 0 1866 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 1867 */ 1868register CLRSINT0 { 1869 address 0x04B 1870 access_mode WO 1871 modes M_DFF0, M_DFF1, M_SCSI 1872 field CLRSELDO 0x40 1873 field CLRSELDI 0x20 1874 field CLRSELINGO 0x10 1875 field CLRIOERR 0x08 1876 field CLROVERRUN 0x04 1877 field CLRSPIORDY 0x02 1878 field CLRARBDO 0x01 1879} 1880 1881/* 1882 * SCSI Interrupt Mode 0 1883 * Setting any bit will enable the corresponding function 1884 * in SIMODE0 to interrupt via the IRQ pin. 1885 */ 1886register SIMODE0 { 1887 address 0x04B 1888 access_mode RW 1889 modes M_CFG 1890 count 8 1891 field ENSELDO 0x40 1892 field ENSELDI 0x20 1893 field ENSELINGO 0x10 1894 field ENIOERR 0x08 1895 field ENOVERRUN 0x04 1896 field ENSPIORDY 0x02 1897 field ENARBDO 0x01 1898} 1899 1900/* 1901 * SCSI Status 1 1902 */ 1903register SSTAT1 { 1904 address 0x04C 1905 access_mode RO 1906 modes M_DFF0, M_DFF1, M_SCSI 1907 field SELTO 0x80 1908 field ATNTARG 0x40 1909 field SCSIRSTI 0x20 1910 field PHASEMIS 0x10 1911 field BUSFREE 0x08 1912 field SCSIPERR 0x04 1913 field STRB2FAST 0x02 1914 field REQINIT 0x01 1915} 1916 1917/* 1918 * Clear SCSI Interrupt 1 1919 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 1920 */ 1921register CLRSINT1 { 1922 address 0x04C 1923 access_mode WO 1924 modes M_DFF0, M_DFF1, M_SCSI 1925 field CLRSELTIMEO 0x80 1926 field CLRATNO 0x40 1927 field CLRSCSIRSTI 0x20 1928 field CLRBUSFREE 0x08 1929 field CLRSCSIPERR 0x04 1930 field CLRSTRB2FAST 0x02 1931 field CLRREQINIT 0x01 1932} 1933 1934/* 1935 * SCSI Status 2 1936 */ 1937register SSTAT2 { 1938 address 0x04d 1939 access_mode RO 1940 modes M_DFF0, M_DFF1, M_SCSI 1941 field BUSFREETIME 0xc0 { 1942 BUSFREE_LQO 0x40, 1943 BUSFREE_DFF0 0x80, 1944 BUSFREE_DFF1 0xC0 1945 } 1946 field NONPACKREQ 0x20 1947 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1948 field BSYX 0x08 /* Busy Expander */ 1949 field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1950 field SDONE 0x02 /* Modes 0 and 1 only */ 1951 field DMADONE 0x01 /* Modes 0 and 1 only */ 1952} 1953 1954/* 1955 * Clear SCSI Interrupt 2 1956 */ 1957register CLRSINT2 { 1958 address 0x04D 1959 access_mode WO 1960 modes M_DFF0, M_DFF1, M_SCSI 1961 field CLRNONPACKREQ 0x20 1962 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1963 field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1964 field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 1965} 1966 1967/* 1968 * SCSI Interrupt Mode 2 1969 */ 1970register SIMODE2 { 1971 address 0x04D 1972 access_mode RW 1973 modes M_CFG 1974 field ENWIDE_RES 0x04 1975 field ENSDONE 0x02 1976 field ENDMADONE 0x01 1977} 1978 1979/* 1980 * Physical Error Diagnosis 1981 */ 1982register PERRDIAG { 1983 address 0x04E 1984 access_mode RO 1985 modes M_DFF0, M_DFF1, M_SCSI 1986 count 3 1987 field HIZERO 0x80 1988 field HIPERR 0x40 1989 field PREVPHASE 0x20 1990 field PARITYERR 0x10 1991 field AIPERR 0x08 1992 field CRCERR 0x04 1993 field DGFORMERR 0x02 1994 field DTERR 0x01 1995} 1996 1997/* 1998 * LQI Manager Current State 1999 */ 2000register LQISTATE { 2001 address 0x04E 2002 access_mode RO 2003 modes M_CFG 2004 count 6 2005} 2006 2007/* 2008 * SCSI Offset Count 2009 */ 2010register SOFFCNT { 2011 address 0x04F 2012 access_mode RO 2013 modes M_DFF0, M_DFF1, M_SCSI 2014 count 1 2015} 2016 2017/* 2018 * LQO Manager Current State 2019 */ 2020register LQOSTATE { 2021 address 0x04F 2022 access_mode RO 2023 modes M_CFG 2024 count 2 2025} 2026 2027/* 2028 * LQI Manager Status 2029 */ 2030register LQISTAT0 { 2031 address 0x050 2032 access_mode RO 2033 modes M_DFF0, M_DFF1, M_SCSI 2034 count 2 2035 field LQIATNQAS 0x20 2036 field LQICRCT1 0x10 2037 field LQICRCT2 0x08 2038 field LQIBADLQT 0x04 2039 field LQIATNLQ 0x02 2040 field LQIATNCMD 0x01 2041} 2042 2043/* 2044 * Clear LQI Interrupts 0 2045 */ 2046register CLRLQIINT0 { 2047 address 0x050 2048 access_mode WO 2049 modes M_DFF0, M_DFF1, M_SCSI 2050 count 1 2051 field CLRLQIATNQAS 0x20 2052 field CLRLQICRCT1 0x10 2053 field CLRLQICRCT2 0x08 2054 field CLRLQIBADLQT 0x04 2055 field CLRLQIATNLQ 0x02 2056 field CLRLQIATNCMD 0x01 2057} 2058 2059/* 2060 * LQI Manager Interrupt Mode 0 2061 */ 2062register LQIMODE0 { 2063 address 0x050 2064 access_mode RW 2065 modes M_CFG 2066 count 3 2067 field ENLQIATNQASK 0x20 2068 field ENLQICRCT1 0x10 2069 field ENLQICRCT2 0x08 2070 field ENLQIBADLQT 0x04 2071 field ENLQIATNLQ 0x02 2072 field ENLQIATNCMD 0x01 2073} 2074 2075/* 2076 * LQI Manager Status 1 2077 */ 2078register LQISTAT1 { 2079 address 0x051 2080 access_mode RO 2081 modes M_DFF0, M_DFF1, M_SCSI 2082 count 3 2083 field LQIPHASE_LQ 0x80 2084 field LQIPHASE_NLQ 0x40 2085 field LQIABORT 0x20 2086 field LQICRCI_LQ 0x10 2087 field LQICRCI_NLQ 0x08 2088 field LQIBADLQI 0x04 2089 field LQIOVERI_LQ 0x02 2090 field LQIOVERI_NLQ 0x01 2091} 2092 2093/* 2094 * Clear LQI Manager Interrupts1 2095 */ 2096register CLRLQIINT1 { 2097 address 0x051 2098 access_mode WO 2099 modes M_DFF0, M_DFF1, M_SCSI 2100 count 4 2101 field CLRLQIPHASE_LQ 0x80 2102 field CLRLQIPHASE_NLQ 0x40 2103 field CLRLIQABORT 0x20 2104 field CLRLQICRCI_LQ 0x10 2105 field CLRLQICRCI_NLQ 0x08 2106 field CLRLQIBADLQI 0x04 2107 field CLRLQIOVERI_LQ 0x02 2108 field CLRLQIOVERI_NLQ 0x01 2109} 2110 2111/* 2112 * LQI Manager Interrupt Mode 1 2113 */ 2114register LQIMODE1 { 2115 address 0x051 2116 access_mode RW 2117 modes M_CFG 2118 count 4 2119 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ 2120 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ 2121 field ENLIQABORT 0x20 2122 field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ 2123 field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ 2124 field ENLQIBADLQI 0x04 2125 field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ 2126 field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ 2127} 2128 2129/* 2130 * LQI Manager Status 2 2131 */ 2132register LQISTAT2 { 2133 address 0x052 2134 access_mode RO 2135 modes M_DFF0, M_DFF1, M_SCSI 2136 field PACKETIZED 0x80 2137 field LQIPHASE_OUTPKT 0x40 2138 field LQIWORKONLQ 0x20 2139 field LQIWAITFIFO 0x10 2140 field LQISTOPPKT 0x08 2141 field LQISTOPLQ 0x04 2142 field LQISTOPCMD 0x02 2143 field LQIGSAVAIL 0x01 2144} 2145 2146/* 2147 * SCSI Status 3 2148 */ 2149register SSTAT3 { 2150 address 0x053 2151 access_mode RO 2152 modes M_DFF0, M_DFF1, M_SCSI 2153 count 3 2154 field NTRAMPERR 0x02 2155 field OSRAMPERR 0x01 2156} 2157 2158/* 2159 * Clear SCSI Status 3 2160 */ 2161register CLRSINT3 { 2162 address 0x053 2163 access_mode WO 2164 modes M_DFF0, M_DFF1, M_SCSI 2165 count 3 2166 field CLRNTRAMPERR 0x02 2167 field CLROSRAMPERR 0x01 2168} 2169 2170/* 2171 * SCSI Interrupt Mode 3 2172 */ 2173register SIMODE3 { 2174 address 0x053 2175 access_mode RW 2176 modes M_CFG 2177 count 4 2178 field ENNTRAMPERR 0x02 2179 field ENOSRAMPERR 0x01 2180} 2181 2182/* 2183 * LQO Manager Status 0 2184 */ 2185register LQOSTAT0 { 2186 address 0x054 2187 access_mode RO 2188 modes M_DFF0, M_DFF1, M_SCSI 2189 count 2 2190 field LQOTARGSCBPERR 0x10 2191 field LQOSTOPT2 0x08 2192 field LQOATNLQ 0x04 2193 field LQOATNPKT 0x02 2194 field LQOTCRC 0x01 2195} 2196 2197/* 2198 * Clear LQO Manager interrupt 0 2199 */ 2200register CLRLQOINT0 { 2201 address 0x054 2202 access_mode WO 2203 modes M_DFF0, M_DFF1, M_SCSI 2204 count 3 2205 field CLRLQOTARGSCBPERR 0x10 2206 field CLRLQOSTOPT2 0x08 2207 field CLRLQOATNLQ 0x04 2208 field CLRLQOATNPKT 0x02 2209 field CLRLQOTCRC 0x01 2210} 2211 2212/* 2213 * LQO Manager Interrupt Mode 0 2214 */ 2215register LQOMODE0 { 2216 address 0x054 2217 access_mode RW 2218 modes M_CFG 2219 count 4 2220 field ENLQOTARGSCBPERR 0x10 2221 field ENLQOSTOPT2 0x08 2222 field ENLQOATNLQ 0x04 2223 field ENLQOATNPKT 0x02 2224 field ENLQOTCRC 0x01 2225} 2226 2227/* 2228 * LQO Manager Status 1 2229 */ 2230register LQOSTAT1 { 2231 address 0x055 2232 access_mode RO 2233 modes M_DFF0, M_DFF1, M_SCSI 2234 field LQOINITSCBPERR 0x10 2235 field LQOSTOPI2 0x08 2236 field LQOBADQAS 0x04 2237 field LQOBUSFREE 0x02 2238 field LQOPHACHGINPKT 0x01 2239} 2240 2241/* 2242 * Clear LOQ Interrupt 1 2243 */ 2244register CLRLQOINT1 { 2245 address 0x055 2246 access_mode WO 2247 modes M_DFF0, M_DFF1, M_SCSI 2248 count 7 2249 field CLRLQOINITSCBPERR 0x10 2250 field CLRLQOSTOPI2 0x08 2251 field CLRLQOBADQAS 0x04 2252 field CLRLQOBUSFREE 0x02 2253 field CLRLQOPHACHGINPKT 0x01 2254} 2255 2256/* 2257 * LQO Manager Interrupt Mode 1 2258 */ 2259register LQOMODE1 { 2260 address 0x055 2261 access_mode RW 2262 modes M_CFG 2263 count 4 2264 field ENLQOINITSCBPERR 0x10 2265 field ENLQOSTOPI2 0x08 2266 field ENLQOBADQAS 0x04 2267 field ENLQOBUSFREE 0x02 2268 field ENLQOPHACHGINPKT 0x01 2269} 2270 2271/* 2272 * LQO Manager Status 2 2273 */ 2274register LQOSTAT2 { 2275 address 0x056 2276 access_mode RO 2277 modes M_DFF0, M_DFF1, M_SCSI 2278 field LQOPKT 0xE0 2279 field LQOWAITFIFO 0x10 2280 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2281 field LQOSTOP0 0x01 /* Stopped after sending all packets */ 2282} 2283 2284/* 2285 * Output Synchronizer Space Count 2286 */ 2287register OS_SPACE_CNT { 2288 address 0x056 2289 access_mode RO 2290 modes M_CFG 2291 count 2 2292} 2293 2294/* 2295 * SCSI Interrupt Mode 1 2296 * Setting any bit will enable the corresponding function 2297 * in SIMODE1 to interrupt via the IRQ pin. 2298 */ 2299register SIMODE1 { 2300 address 0x057 2301 access_mode RW 2302 modes M_DFF0, M_DFF1, M_SCSI 2303 field ENSELTIMO 0x80 2304 field ENATNTARG 0x40 2305 field ENSCSIRST 0x20 2306 field ENPHASEMIS 0x10 2307 field ENBUSFREE 0x08 2308 field ENSCSIPERR 0x04 2309 field ENSTRB2FAST 0x02 2310 field ENREQINIT 0x01 2311} 2312 2313/* 2314 * Good Status FIFO 2315 */ 2316register GSFIFO { 2317 address 0x058 2318 access_mode RO 2319 size 2 2320 modes M_DFF0, M_DFF1, M_SCSI 2321} 2322 2323/* 2324 * Data FIFO SCSI Transfer Control 2325 */ 2326register DFFSXFRCTL { 2327 address 0x05A 2328 access_mode RW 2329 modes M_DFF0, M_DFF1 2330 field DFFBITBUCKET 0x08 2331 field CLRSHCNT 0x04 2332 field CLRCHN 0x02 2333 field RSTCHN 0x01 2334} 2335 2336/* 2337 * Next SCSI Control Block 2338 */ 2339register NEXTSCB { 2340 address 0x05A 2341 access_mode RW 2342 size 2 2343 modes M_SCSI 2344} 2345 2346/* 2347 * LQO SCSI Control 2348 * (Rev B only.) 2349 */ 2350register LQOSCSCTL { 2351 address 0x05A 2352 access_mode RW 2353 size 1 2354 modes M_CFG 2355 count 1 2356 field LQOH2A_VERSION 0x80 2357 field LQOBUSETDLY 0x40 2358 field LQONOHOLDLACK 0x02 2359 field LQONOCHKOVER 0x01 2360} 2361 2362/* 2363 * SEQ Interrupts 2364 */ 2365register SEQINTSRC { 2366 address 0x05B 2367 access_mode RO 2368 modes M_DFF0, M_DFF1 2369 field CTXTDONE 0x40 2370 field SAVEPTRS 0x20 2371 field CFG4DATA 0x10 2372 field CFG4ISTAT 0x08 2373 field CFG4TSTAT 0x04 2374 field CFG4ICMD 0x02 2375 field CFG4TCMD 0x01 2376} 2377 2378/* 2379 * Clear Arp Interrupts 2380 */ 2381register CLRSEQINTSRC { 2382 address 0x05B 2383 access_mode WO 2384 modes M_DFF0, M_DFF1 2385 field CLRCTXTDONE 0x40 2386 field CLRSAVEPTRS 0x20 2387 field CLRCFG4DATA 0x10 2388 field CLRCFG4ISTAT 0x08 2389 field CLRCFG4TSTAT 0x04 2390 field CLRCFG4ICMD 0x02 2391 field CLRCFG4TCMD 0x01 2392} 2393 2394/* 2395 * SEQ Interrupt Enabled (Shared) 2396 */ 2397register SEQIMODE { 2398 address 0x05C 2399 access_mode RW 2400 modes M_DFF0, M_DFF1 2401 field ENCTXTDONE 0x40 2402 field ENSAVEPTRS 0x20 2403 field ENCFG4DATA 0x10 2404 field ENCFG4ISTAT 0x08 2405 field ENCFG4TSTAT 0x04 2406 field ENCFG4ICMD 0x02 2407 field ENCFG4TCMD 0x01 2408} 2409 2410/* 2411 * Current SCSI Control Block 2412 */ 2413register CURRSCB { 2414 address 0x05C 2415 access_mode RW 2416 size 2 2417 modes M_SCSI 2418} 2419 2420/* 2421 * Data FIFO Status 2422 */ 2423register MDFFSTAT { 2424 address 0x05D 2425 access_mode RO 2426 modes M_DFF0, M_DFF1 2427 field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2428 field SHCNTMINUS1 0x20 /* Rev B or higher */ 2429 field LASTSDONE 0x10 2430 field SHVALID 0x08 2431 field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2432 field DATAINFIFO 0x02 2433 field FIFOFREE 0x01 2434} 2435 2436/* 2437 * CRC Control 2438 */ 2439register CRCCONTROL { 2440 address 0x05d 2441 access_mode RW 2442 modes M_CFG 2443 field CRCVALCHKEN 0x40 2444} 2445 2446/* 2447 * SCSI Test Control 2448 */ 2449register SCSITEST { 2450 address 0x05E 2451 access_mode RW 2452 modes M_CFG 2453 field CNTRTEST 0x08 2454 field SEL_TXPLL_DEBUG 0x04 2455} 2456 2457/* 2458 * Data FIFO Queue Tag 2459 */ 2460register DFFTAG { 2461 address 0x05E 2462 access_mode RW 2463 size 2 2464 modes M_DFF0, M_DFF1 2465} 2466 2467/* 2468 * Last SCSI Control Block 2469 */ 2470register LASTSCB { 2471 address 0x05E 2472 access_mode RW 2473 size 2 2474 modes M_SCSI 2475} 2476 2477/* 2478 * SCSI I/O Cell Power-down Control 2479 */ 2480register IOPDNCTL { 2481 address 0x05F 2482 access_mode RW 2483 modes M_CFG 2484 field DISABLE_OE 0x80 2485 field PDN_IDIST 0x04 2486 field PDN_DIFFSENSE 0x01 2487} 2488 2489/* 2490 * Shaddow Host Address. 2491 */ 2492register SHADDR { 2493 address 0x060 2494 access_mode RO 2495 size 8 2496 modes M_DFF0, M_DFF1 2497} 2498 2499/* 2500 * Data Group CRC Interval. 2501 */ 2502register DGRPCRCI { 2503 address 0x060 2504 access_mode RW 2505 size 2 2506 modes M_CFG 2507} 2508 2509/* 2510 * Data Transfer Negotiation Address 2511 */ 2512register NEGOADDR { 2513 address 0x060 2514 access_mode RW 2515 modes M_SCSI 2516} 2517 2518/* 2519 * Data Transfer Negotiation Data - Period Byte 2520 */ 2521register NEGPERIOD { 2522 address 0x061 2523 access_mode RW 2524 modes M_SCSI 2525 count 1 2526} 2527 2528/* 2529 * Packetized CRC Interval 2530 */ 2531register PACKCRCI { 2532 address 0x062 2533 access_mode RW 2534 size 2 2535 modes M_CFG 2536} 2537 2538/* 2539 * Data Transfer Negotiation Data - Offset Byte 2540 */ 2541register NEGOFFSET { 2542 address 0x062 2543 access_mode RW 2544 modes M_SCSI 2545 count 1 2546} 2547 2548/* 2549 * Data Transfer Negotiation Data - PPR Options 2550 */ 2551register NEGPPROPTS { 2552 address 0x063 2553 access_mode RW 2554 modes M_SCSI 2555 count 1 2556 field PPROPT_PACE 0x08 2557 field PPROPT_QAS 0x04 2558 field PPROPT_DT 0x02 2559 field PPROPT_IUT 0x01 2560} 2561 2562/* 2563 * Data Transfer Negotiation Data - Connection Options 2564 */ 2565register NEGCONOPTS { 2566 address 0x064 2567 access_mode RW 2568 modes M_SCSI 2569 field ENSNAPSHOT 0x40 2570 field RTI_WRTDIS 0x20 2571 field RTI_OVRDTRN 0x10 2572 field ENSLOWCRC 0x08 2573 field ENAUTOATNI 0x04 2574 field ENAUTOATNO 0x02 2575 field WIDEXFER 0x01 2576} 2577 2578/* 2579 * Negotiation Table Annex Column Index. 2580 */ 2581register ANNEXCOL { 2582 address 0x065 2583 access_mode RW 2584 modes M_SCSI 2585 count 7 2586} 2587 2588/* 2589 * SCSI Check 2590 * (Rev. B only) 2591 */ 2592register SCSCHKN { 2593 address 0x066 2594 access_mode RW 2595 modes M_CFG 2596 count 1 2597 field BIDICHKDIS 0x80 2598 field STSELSKIDDIS 0x40 2599 field CURRFIFODEF 0x20 2600 field WIDERESEN 0x10 2601 field SDONEMSKDIS 0x08 2602 field DFFACTCLR 0x04 2603 field SHVALIDSTDIS 0x02 2604 field LSTSGCLRDIS 0x01 2605} 2606 2607const AHD_ANNEXCOL_PER_DEV0 4 2608const AHD_NUM_PER_DEV_ANNEXCOLS 4 2609const AHD_ANNEXCOL_PRECOMP_SLEW 4 2610const AHD_PRECOMP_MASK 0x07 2611const AHD_PRECOMP_SHIFT 0 2612const AHD_PRECOMP_CUTBACK_17 0x04 2613const AHD_PRECOMP_CUTBACK_29 0x06 2614const AHD_PRECOMP_CUTBACK_37 0x07 2615const AHD_SLEWRATE_MASK 0x78 2616const AHD_SLEWRATE_SHIFT 3 2617/* 2618 * Rev A has only a single bit (high bit of field) of slew adjustment. 2619 * Rev B has 4 bits. The current default happens to be the same for both. 2620 */ 2621const AHD_SLEWRATE_DEF_REVA 0x08 2622const AHD_SLEWRATE_DEF_REVB 0x08 2623 2624/* Rev A does not have any amplitude setting. */ 2625const AHD_ANNEXCOL_AMPLITUDE 6 2626const AHD_AMPLITUDE_MASK 0x7 2627const AHD_AMPLITUDE_SHIFT 0 2628const AHD_AMPLITUDE_DEF 0x7 2629 2630/* 2631 * Negotiation Table Annex Data Port. 2632 */ 2633register ANNEXDAT { 2634 address 0x066 2635 access_mode RW 2636 modes M_SCSI 2637 count 3 2638} 2639 2640/* 2641 * Initiator's Own Id. 2642 * The SCSI ID to use for Selection Out and seen during a reselection.. 2643 */ 2644register IOWNID { 2645 address 0x067 2646 access_mode RW 2647 modes M_SCSI 2648} 2649 2650/* 2651 * 960MHz Phase-Locked Loop Control 0 2652 */ 2653register PLL960CTL0 { 2654 address 0x068 2655 access_mode RW 2656 modes M_CFG 2657 field PLL_VCOSEL 0x80 2658 field PLL_PWDN 0x40 2659 field PLL_NS 0x30 2660 field PLL_ENLUD 0x08 2661 field PLL_ENLPF 0x04 2662 field PLL_DLPF 0x02 2663 field PLL_ENFBM 0x01 2664} 2665 2666/* 2667 * Target Own Id 2668 */ 2669register TOWNID { 2670 address 0x069 2671 access_mode RW 2672 modes M_SCSI 2673 count 2 2674} 2675 2676/* 2677 * 960MHz Phase-Locked Loop Control 1 2678 */ 2679register PLL960CTL1 { 2680 address 0x069 2681 access_mode RW 2682 modes M_CFG 2683 field PLL_CNTEN 0x80 2684 field PLL_CNTCLR 0x40 2685 field PLL_RST 0x01 2686} 2687 2688/* 2689 * Expander Signature 2690 */ 2691register XSIG { 2692 address 0x06A 2693 access_mode RW 2694 modes M_SCSI 2695} 2696 2697/* 2698 * Shadow Byte Count 2699 */ 2700register SHCNT { 2701 address 0x068 2702 access_mode RW 2703 size 3 2704 modes M_DFF0, M_DFF1 2705} 2706 2707/* 2708 * Selection Out ID 2709 */ 2710register SELOID { 2711 address 0x06B 2712 access_mode RW 2713 modes M_SCSI 2714} 2715 2716/* 2717 * 960-MHz Phase-Locked Loop Test Count 2718 */ 2719register PLL960CNT0 { 2720 address 0x06A 2721 access_mode RO 2722 size 2 2723 modes M_CFG 2724} 2725 2726/* 2727 * 400-MHz Phase-Locked Loop Control 0 2728 */ 2729register PLL400CTL0 { 2730 address 0x06C 2731 access_mode RW 2732 modes M_CFG 2733 field PLL_VCOSEL 0x80 2734 field PLL_PWDN 0x40 2735 field PLL_NS 0x30 2736 field PLL_ENLUD 0x08 2737 field PLL_ENLPF 0x04 2738 field PLL_DLPF 0x02 2739 field PLL_ENFBM 0x01 2740} 2741 2742/* 2743 * Arbitration Fairness 2744 */ 2745register FAIRNESS { 2746 address 0x06C 2747 access_mode RW 2748 size 2 2749 modes M_SCSI 2750} 2751 2752/* 2753 * 400-MHz Phase-Locked Loop Control 1 2754 */ 2755register PLL400CTL1 { 2756 address 0x06D 2757 access_mode RW 2758 modes M_CFG 2759 field PLL_CNTEN 0x80 2760 field PLL_CNTCLR 0x40 2761 field PLL_RST 0x01 2762} 2763 2764/* 2765 * Arbitration Unfairness 2766 */ 2767register UNFAIRNESS { 2768 address 0x06E 2769 access_mode RW 2770 size 2 2771 modes M_SCSI 2772} 2773 2774/* 2775 * 400-MHz Phase-Locked Loop Test Count 2776 */ 2777register PLL400CNT0 { 2778 address 0x06E 2779 access_mode RO 2780 size 2 2781 modes M_CFG 2782} 2783 2784/* 2785 * SCB Page Pointer 2786 */ 2787register SCBPTR { 2788 address 0x0A8 2789 access_mode RW 2790 size 2 2791 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 2792} 2793 2794/* 2795 * CMC SCB Array Count 2796 * Number of bytes to transfer between CMC SCB memory and SCBRAM. 2797 * Transfers must be 8byte aligned and sized. 2798 */ 2799register CCSCBACNT { 2800 address 0x0AB 2801 access_mode RW 2802 modes M_CCHAN 2803} 2804 2805/* 2806 * SCB Autopointer 2807 * SCB-Next Address Snooping logic. When an SCB is transferred to 2808 * the card, the next SCB address to be used by the CMC array can 2809 * be autoloaded from that transfer. 2810 */ 2811register SCBAUTOPTR { 2812 address 0x0AB 2813 access_mode RW 2814 modes M_CFG 2815 count 1 2816 field AUSCBPTR_EN 0x80 2817 field SCBPTR_ADDR 0x38 2818 field SCBPTR_OFF 0x07 2819} 2820 2821/* 2822 * CMC SG Ram Address Pointer 2823 */ 2824register CCSGADDR { 2825 address 0x0AC 2826 access_mode RW 2827 modes M_DFF0, M_DFF1 2828} 2829 2830/* 2831 * CMC SCB RAM Address Pointer 2832 */ 2833register CCSCBADDR { 2834 address 0x0AC 2835 access_mode RW 2836 modes M_CCHAN 2837} 2838 2839/* 2840 * CMC SCB Ram Back-up Address Pointer 2841 * Indicates the true stop location of transfers halted prior 2842 * to SCBHCNT going to 0. 2843 */ 2844register CCSCBADR_BK { 2845 address 0x0AC 2846 access_mode RO 2847 modes M_CFG 2848} 2849 2850/* 2851 * CMC SG Control 2852 */ 2853register CCSGCTL { 2854 address 0x0AD 2855 access_mode RW 2856 modes M_DFF0, M_DFF1 2857 field CCSGDONE 0x80 2858 field SG_CACHE_AVAIL 0x10 2859 field CCSGENACK 0x08 2860 mask CCSGEN 0x0C 2861 field SG_FETCH_REQ 0x02 2862 field CCSGRESET 0x01 2863} 2864 2865/* 2866 * CMD SCB Control 2867 */ 2868register CCSCBCTL { 2869 address 0x0AD 2870 access_mode RW 2871 modes M_CCHAN 2872 field CCSCBDONE 0x80 2873 field ARRDONE 0x40 2874 field CCARREN 0x10 2875 field CCSCBEN 0x08 2876 field CCSCBDIR 0x04 2877 field CCSCBRESET 0x01 2878} 2879 2880/* 2881 * CMC Ram BIST 2882 */ 2883register CMC_RAMBIST { 2884 address 0x0AD 2885 access_mode RW 2886 modes M_CFG 2887 field SG_ELEMENT_SIZE 0x80 2888 field SCBRAMBIST_FAIL 0x40 2889 field SG_BIST_FAIL 0x20 2890 field SG_BIST_EN 0x10 2891 field CMC_BUFFER_BIST_FAIL 0x02 2892 field CMC_BUFFER_BIST_EN 0x01 2893} 2894 2895/* 2896 * CMC SG RAM Data Port 2897 */ 2898register CCSGRAM { 2899 address 0x0B0 2900 access_mode RW 2901 modes M_DFF0, M_DFF1 2902} 2903 2904/* 2905 * CMC SCB RAM Data Port 2906 */ 2907register CCSCBRAM { 2908 address 0x0B0 2909 access_mode RW 2910 modes M_CCHAN 2911} 2912 2913/* 2914 * Flex DMA Address. 2915 */ 2916register FLEXADR { 2917 address 0x0B0 2918 access_mode RW 2919 size 3 2920 modes M_SCSI 2921} 2922 2923/* 2924 * Flex DMA Byte Count 2925 */ 2926register FLEXCNT { 2927 address 0x0B3 2928 access_mode RW 2929 size 2 2930 modes M_SCSI 2931} 2932 2933/* 2934 * Flex DMA Status 2935 */ 2936register FLEXDMASTAT { 2937 address 0x0B5 2938 access_mode RW 2939 modes M_SCSI 2940 field FLEXDMAERR 0x02 2941 field FLEXDMADONE 0x01 2942} 2943 2944/* 2945 * Flex DMA Data Port 2946 */ 2947register FLEXDATA { 2948 address 0x0B6 2949 access_mode RW 2950 modes M_SCSI 2951} 2952 2953/* 2954 * Board Data 2955 */ 2956register BRDDAT { 2957 address 0x0B8 2958 access_mode RW 2959 modes M_SCSI 2960 count 2 2961} 2962 2963/* 2964 * Board Control 2965 */ 2966register BRDCTL { 2967 address 0x0B9 2968 access_mode RW 2969 modes M_SCSI 2970 count 7 2971 field FLXARBACK 0x80 2972 field FLXARBREQ 0x40 2973 field BRDADDR 0x38 2974 field BRDEN 0x04 2975 field BRDRW 0x02 2976 field BRDSTB 0x01 2977} 2978 2979/* 2980 * Serial EEPROM Address 2981 */ 2982register SEEADR { 2983 address 0x0BA 2984 access_mode RW 2985 modes M_SCSI 2986 count 4 2987} 2988 2989/* 2990 * Serial EEPROM Data 2991 */ 2992register SEEDAT { 2993 address 0x0BC 2994 access_mode RW 2995 size 2 2996 modes M_SCSI 2997 count 4 2998} 2999 3000/* 3001 * Serial EEPROM Status 3002 */ 3003register SEESTAT { 3004 address 0x0BE 3005 access_mode RO 3006 modes M_SCSI 3007 count 1 3008 field INIT_DONE 0x80 3009 field SEEOPCODE 0x70 3010 field LDALTID_L 0x08 3011 field SEEARBACK 0x04 3012 field SEEBUSY 0x02 3013 field SEESTART 0x01 3014} 3015 3016/* 3017 * Serial EEPROM Control 3018 */ 3019register SEECTL { 3020 address 0x0BE 3021 access_mode RW 3022 modes M_SCSI 3023 count 4 3024 field SEEOPCODE 0x70 { 3025 SEEOP_ERASE 0x70, 3026 SEEOP_READ 0x60, 3027 SEEOP_WRITE 0x50, 3028 /* 3029 * The following four commands use special 3030 * addresses for differentiation. 3031 */ 3032 SEEOP_ERAL 0x40 3033 } 3034 mask SEEOP_EWEN 0x40 3035 mask SEEOP_WALL 0x40 3036 mask SEEOP_EWDS 0x40 3037 field SEERST 0x02 3038 field SEESTART 0x01 3039} 3040 3041const SEEOP_ERAL_ADDR 0x80 3042const SEEOP_EWEN_ADDR 0xC0 3043const SEEOP_WRAL_ADDR 0x40 3044const SEEOP_EWDS_ADDR 0x00 3045 3046/* 3047 * SCB Counter 3048 */ 3049register SCBCNT { 3050 address 0x0BF 3051 access_mode RW 3052 modes M_SCSI 3053} 3054 3055/* 3056 * Data FIFO Write Address 3057 * Pointer to the next QWD location to be written to the data FIFO. 3058 */ 3059register DFWADDR { 3060 address 0x0C0 3061 access_mode RW 3062 size 2 3063 modes M_DFF0, M_DFF1 3064} 3065 3066/* 3067 * DSP Filter Control 3068 */ 3069register DSPFLTRCTL { 3070 address 0x0C0 3071 access_mode RW 3072 modes M_CFG 3073 field FLTRDISABLE 0x20 3074 field EDGESENSE 0x10 3075 field DSPFCNTSEL 0x0F 3076} 3077 3078/* 3079 * DSP Data Channel Control 3080 */ 3081register DSPDATACTL { 3082 address 0x0C1 3083 access_mode RW 3084 modes M_CFG 3085 count 3 3086 field BYPASSENAB 0x80 3087 field DESQDIS 0x10 3088 field RCVROFFSTDIS 0x04 3089 field XMITOFFSTDIS 0x02 3090} 3091 3092/* 3093 * Data FIFO Read Address 3094 * Pointer to the next QWD location to be read from the data FIFO. 3095 */ 3096register DFRADDR { 3097 address 0x0C2 3098 access_mode RW 3099 size 2 3100 modes M_DFF0, M_DFF1 3101} 3102 3103/* 3104 * DSP REQ Control 3105 */ 3106register DSPREQCTL { 3107 address 0x0C2 3108 access_mode RW 3109 modes M_CFG 3110 field MANREQCTL 0xC0 3111 field MANREQDLY 0x3F 3112} 3113 3114/* 3115 * DSP ACK Control 3116 */ 3117register DSPACKCTL { 3118 address 0x0C3 3119 access_mode RW 3120 modes M_CFG 3121 field MANACKCTL 0xC0 3122 field MANACKDLY 0x3F 3123} 3124 3125/* 3126 * Data FIFO Data 3127 * Read/Write byte port into the data FIFO. The read and write 3128 * FIFO pointers increment with each read and write respectively 3129 * to this port. 3130 */ 3131register DFDAT { 3132 address 0x0C4 3133 access_mode RW 3134 modes M_DFF0, M_DFF1 3135} 3136 3137/* 3138 * DSP Channel Select 3139 */ 3140register DSPSELECT { 3141 address 0x0C4 3142 access_mode RW 3143 modes M_CFG 3144 count 1 3145 field AUTOINCEN 0x80 3146 field DSPSEL 0x1F 3147} 3148 3149const NUMDSPS 0x14 3150 3151/* 3152 * Write Bias Control 3153 */ 3154register WRTBIASCTL { 3155 address 0x0C5 3156 access_mode WO 3157 modes M_CFG 3158 count 3 3159 field AUTOXBCDIS 0x80 3160 field XMITMANVAL 0x3F 3161} 3162 3163/* 3164 * Currently the WRTBIASCTL is the same as the default. 3165 */ 3166const WRTBIASCTL_HP_DEFAULT 0x0 3167 3168/* 3169 * Receiver Bias Control 3170 */ 3171register RCVRBIOSCTL { 3172 address 0x0C6 3173 access_mode WO 3174 modes M_CFG 3175 field AUTORBCDIS 0x80 3176 field RCVRMANVAL 0x3F 3177} 3178 3179/* 3180 * Write Bias Calculator 3181 */ 3182register WRTBIASCALC { 3183 address 0x0C7 3184 access_mode RO 3185 modes M_CFG 3186} 3187 3188/* 3189 * Data FIFO Pointers 3190 * Contains the byte offset from DFWADDR and DWRADDR to the current 3191 * FIFO write/read locations. 3192 */ 3193register DFPTRS { 3194 address 0x0C8 3195 access_mode RW 3196 modes M_DFF0, M_DFF1 3197} 3198 3199/* 3200 * Receiver Bias Calculator 3201 */ 3202register RCVRBIASCALC { 3203 address 0x0C8 3204 access_mode RO 3205 modes M_CFG 3206} 3207 3208/* 3209 * Data FIFO Backup Read Pointer 3210 * Contains the data FIFO address to be restored if the last 3211 * data accessed from the data FIFO was not transferred successfully. 3212 */ 3213register DFBKPTR { 3214 address 0x0C9 3215 access_mode RW 3216 size 2 3217 modes M_DFF0, M_DFF1 3218} 3219 3220/* 3221 * Skew Calculator 3222 */ 3223register SKEWCALC { 3224 address 0x0C9 3225 access_mode RO 3226 modes M_CFG 3227} 3228 3229/* 3230 * Data FIFO Debug Control 3231 */ 3232register DFDBCTL { 3233 address 0x0CB 3234 access_mode RW 3235 modes M_DFF0, M_DFF1 3236 field DFF_CIO_WR_RDY 0x20 3237 field DFF_CIO_RD_RDY 0x10 3238 field DFF_DIR_ERR 0x08 3239 field DFF_RAMBIST_FAIL 0x04 3240 field DFF_RAMBIST_DONE 0x02 3241 field DFF_RAMBIST_EN 0x01 3242} 3243 3244/* 3245 * Data FIFO Space Count 3246 * Number of FIFO locations that are free. 3247 */ 3248register DFSCNT { 3249 address 0x0CC 3250 access_mode RO 3251 size 2 3252 modes M_DFF0, M_DFF1 3253} 3254 3255/* 3256 * Data FIFO Byte Count 3257 * Number of filled FIFO locations. 3258 */ 3259register DFBCNT { 3260 address 0x0CE 3261 access_mode RO 3262 size 2 3263 modes M_DFF0, M_DFF1 3264} 3265 3266/* 3267 * Sequencer Program Overlay Address. 3268 * Low address must be written prior to high address. 3269 */ 3270register OVLYADDR { 3271 address 0x0D4 3272 modes M_SCSI 3273 size 2 3274 access_mode RW 3275} 3276 3277/* 3278 * Sequencer Control 0 3279 * Error detection mode, speed configuration, 3280 * single step, breakpoints and program load. 3281 */ 3282register SEQCTL0 { 3283 address 0x0D6 3284 access_mode RW 3285 count 11 3286 field PERRORDIS 0x80 3287 field PAUSEDIS 0x40 3288 field FAILDIS 0x20 3289 field FASTMODE 0x10 3290 field BRKADRINTEN 0x08 3291 field STEP 0x04 3292 field SEQRESET 0x02 3293 field LOADRAM 0x01 3294} 3295 3296/* 3297 * Sequencer Control 1 3298 * Instruction RAM Diagnostics 3299 */ 3300register SEQCTL1 { 3301 address 0x0D7 3302 access_mode RW 3303 field OVRLAY_DATA_CHK 0x08 3304 field RAMBIST_DONE 0x04 3305 field RAMBIST_FAIL 0x02 3306 field RAMBIST_EN 0x01 3307} 3308 3309/* 3310 * Sequencer Flags 3311 * Zero and Carry state of the ALU. 3312 */ 3313register FLAGS { 3314 address 0x0D8 3315 access_mode RO 3316 count 23 3317 field ZERO 0x02 3318 field CARRY 0x01 3319} 3320 3321/* 3322 * Sequencer Interrupt Control 3323 */ 3324register SEQINTCTL { 3325 address 0x0D9 3326 access_mode RW 3327 field INTVEC1DSL 0x80 3328 field INT1_CONTEXT 0x20 3329 field SCS_SEQ_INT1M1 0x10 3330 field SCS_SEQ_INT1M0 0x08 3331 field INTMASK2 0x04 3332 field INTMASK1 0x02 3333 field IRET 0x01 3334} 3335 3336/* 3337 * Sequencer RAM Data Port 3338 * Single byte window into the Sequencer Instruction Ram area starting 3339 * at the address specified by OVLYADDR. To write a full instruction word, 3340 * simply write four bytes in succession. OVLYADDR will increment after the 3341 * most significant instrution byte (the byte with the parity bit) is written. 3342 */ 3343register SEQRAM { 3344 address 0x0DA 3345 access_mode RW 3346 count 2 3347} 3348 3349/* 3350 * Sequencer Program Counter 3351 * Low byte must be written prior to high byte. 3352 */ 3353register PRGMCNT { 3354 address 0x0DE 3355 access_mode RW 3356 size 2 3357 count 5 3358} 3359 3360/* 3361 * Accumulator 3362 */ 3363register ACCUM { 3364 address 0x0E0 3365 access_mode RW 3366 accumulator 3367} 3368 3369/* 3370 * Source Index Register 3371 * Incrementing index for reads of SINDIR and the destination (low byte only) 3372 * for any immediate operands passed in jmp, jc, jnc, call instructions. 3373 * Example: 3374 * mvi 0xFF call some_routine; 3375 * 3376 * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 3377 */ 3378register SINDEX { 3379 address 0x0E2 3380 access_mode RW 3381 size 2 3382 sindex 3383} 3384 3385/* 3386 * Destination Index Register 3387 * Incrementing index for writes to DINDIR. Can be used as a scratch register. 3388 */ 3389register DINDEX { 3390 address 0x0E4 3391 access_mode RW 3392 size 2 3393} 3394 3395/* 3396 * Break Address 3397 * Sequencer instruction breakpoint address address. 3398 */ 3399register BRKADDR0 { 3400 address 0x0E6 3401 access_mode RW 3402} 3403 3404register BRKADDR1 { 3405 address 0x0E6 3406 access_mode RW 3407 field BRKDIS 0x80 /* Disable Breakpoint */ 3408} 3409 3410/* 3411 * All Ones 3412 * All reads to this register return the value 0xFF. 3413 */ 3414register ALLONES { 3415 address 0x0E8 3416 access_mode RO 3417 allones 3418} 3419 3420/* 3421 * All Zeros 3422 * All reads to this register return the value 0. 3423 */ 3424register ALLZEROS { 3425 address 0x0EA 3426 access_mode RO 3427 allzeros 3428} 3429 3430/* 3431 * No Destination 3432 * Writes to this register have no effect. 3433 */ 3434register NONE { 3435 address 0x0EA 3436 access_mode WO 3437 none 3438} 3439 3440/* 3441 * Source Index Indirect 3442 * Reading this register is equivalent to reading (register_base + SINDEX) and 3443 * incrementing SINDEX by 1. 3444 */ 3445register SINDIR { 3446 address 0x0EC 3447 access_mode RO 3448} 3449 3450/* 3451 * Destination Index Indirect 3452 * Writing this register is equivalent to writing to (register_base + DINDEX) 3453 * and incrementing DINDEX by 1. 3454 */ 3455register DINDIR { 3456 address 0x0ED 3457 access_mode WO 3458} 3459 3460/* 3461 * Function One 3462 * 2's complement to bit value conversion. Write the 2's complement value 3463 * (0-7 only) to the top nibble and retrieve the bit indexed by that value 3464 * on the next read of this register. 3465 * Example: 3466 * Write 0x60 3467 * Read 0x40 3468 */ 3469register FUNCTION1 { 3470 address 0x0F0 3471 access_mode RW 3472} 3473 3474/* 3475 * Stack 3476 * Window into the stack. Each stack location is 10 bits wide reported 3477 * low byte followed by high byte. There are 8 stack locations. 3478 */ 3479register STACK { 3480 address 0x0F2 3481 access_mode RW 3482} 3483 3484/* 3485 * Interrupt Vector 1 Address 3486 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 3487 */ 3488register INTVEC1_ADDR { 3489 address 0x0F4 3490 access_mode RW 3491 size 2 3492 modes M_CFG 3493 count 1 3494} 3495 3496/* 3497 * Current Address 3498 * Address of the SEQRAM instruction currently executing instruction. 3499 */ 3500register CURADDR { 3501 address 0x0F4 3502 access_mode RW 3503 size 2 3504 modes M_SCSI 3505 count 2 3506} 3507 3508/* 3509 * Interrupt Vector 2 Address 3510 * Interrupt branch address for HST_SEQ_INT2 interrupts. 3511 */ 3512register INTVEC2_ADDR { 3513 address 0x0F6 3514 access_mode RW 3515 size 2 3516 modes M_CFG 3517 count 1 3518} 3519 3520/* 3521 * Last Address 3522 * Address of the SEQRAM instruction executed prior to the current instruction. 3523 */ 3524register LASTADDR { 3525 address 0x0F6 3526 access_mode RW 3527 size 2 3528 modes M_SCSI 3529} 3530 3531register AHD_PCI_CONFIG_BASE { 3532 address 0x100 3533 access_mode RW 3534 size 256 3535 modes M_CFG 3536} 3537 3538/* ---------------------- Scratch RAM Offsets ------------------------- */ 3539scratch_ram { 3540 /* Mode Specific */ 3541 address 0x0A0 3542 size 8 3543 modes 0, 1, 2, 3 3544 REG0 { 3545 size 2 3546 } 3547 REG1 { 3548 size 2 3549 } 3550 REG_ISR { 3551 size 2 3552 } 3553 SG_STATE { 3554 size 1 3555 field SEGS_AVAIL 0x01 3556 field LOADING_NEEDED 0x02 3557 field FETCH_INPROG 0x04 3558 } 3559 /* 3560 * Track whether the transfer byte count for 3561 * the current data phase is odd. 3562 */ 3563 DATA_COUNT_ODD { 3564 size 1 3565 } 3566} 3567 3568scratch_ram { 3569 /* Mode Specific */ 3570 address 0x0F8 3571 size 8 3572 modes 0, 1, 2, 3 3573 LONGJMP_ADDR { 3574 size 2 3575 } 3576 ACCUM_SAVE { 3577 size 1 3578 } 3579} 3580 3581 3582scratch_ram { 3583 address 0x100 3584 size 128 3585 modes 0, 1, 2, 3 3586 /* 3587 * Per "other-id" execution queues. We use an array of 3588 * tail pointers into lists of SCBs sorted by "other-id". 3589 * The execution head pointer threads the head SCBs for 3590 * each list. 3591 */ 3592 WAITING_SCB_TAILS { 3593 size 32 3594 } 3595 WAITING_TID_HEAD { 3596 size 2 3597 } 3598 WAITING_TID_TAIL { 3599 size 2 3600 } 3601 /* 3602 * SCBID of the next SCB in the new SCB queue. 3603 */ 3604 NEXT_QUEUED_SCB_ADDR { 3605 size 4 3606 } 3607 /* 3608 * head of list of SCBs that have 3609 * completed but have not been 3610 * put into the qoutfifo. 3611 */ 3612 COMPLETE_SCB_HEAD { 3613 size 2 3614 } 3615 /* 3616 * The list of completed SCBs in 3617 * the active DMA. 3618 */ 3619 COMPLETE_SCB_DMAINPROG_HEAD { 3620 size 2 3621 } 3622 /* 3623 * head of list of SCBs that have 3624 * completed but need to be uploaded 3625 * to the host prior to being completed. 3626 */ 3627 COMPLETE_DMA_SCB_HEAD { 3628 size 2 3629 } 3630 /* 3631 * tail of list of SCBs that have 3632 * completed but need to be uploaded 3633 * to the host prior to being completed. 3634 */ 3635 COMPLETE_DMA_SCB_TAIL { 3636 size 2 3637 } 3638 /* 3639 * head of list of SCBs that have 3640 * been uploaded to the host, but cannot 3641 * be completed until the QFREEZE is in 3642 * full effect (i.e. no selections pending). 3643 */ 3644 COMPLETE_ON_QFREEZE_HEAD { 3645 size 2 3646 } 3647 /* 3648 * Counting semaphore to prevent new select-outs 3649 * The queue is frozen so long as the sequencer 3650 * and kernel freeze counts differ. 3651 */ 3652 QFREEZE_COUNT { 3653 size 2 3654 } 3655 KERNEL_QFREEZE_COUNT { 3656 size 2 3657 } 3658 /* 3659 * Mode to restore on legacy idle loop exit. 3660 */ 3661 SAVED_MODE { 3662 size 1 3663 } 3664 /* 3665 * Single byte buffer used to designate the type or message 3666 * to send to a target. 3667 */ 3668 MSG_OUT { 3669 size 1 3670 } 3671 /* Parameters for DMA Logic */ 3672 DMAPARAMS { 3673 size 1 3674 count 8 3675 field PRELOADEN 0x80 3676 field WIDEODD 0x40 3677 field SCSIEN 0x20 3678 field SDMAEN 0x10 3679 field SDMAENACK 0x10 3680 field HDMAEN 0x08 3681 field HDMAENACK 0x08 3682 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3683 field FIFOFLUSH 0x02 3684 field FIFORESET 0x01 3685 } 3686 SEQ_FLAGS { 3687 size 1 3688 field NOT_IDENTIFIED 0x80 3689 field NO_CDB_SENT 0x40 3690 field TARGET_CMD_IS_TAGGED 0x40 3691 field DPHASE 0x20 3692 /* Target flags */ 3693 field TARG_CMD_PENDING 0x10 3694 field CMDPHASE_PENDING 0x08 3695 field DPHASE_PENDING 0x04 3696 field SPHASE_PENDING 0x02 3697 field NO_DISCONNECT 0x01 3698 } 3699 /* 3700 * Temporary storage for the 3701 * target/channel/lun of a 3702 * reconnecting target 3703 */ 3704 SAVED_SCSIID { 3705 size 1 3706 } 3707 SAVED_LUN { 3708 size 1 3709 } 3710 /* 3711 * The last bus phase as seen by the sequencer. 3712 */ 3713 LASTPHASE { 3714 size 1 3715 field CDI 0x80 3716 field IOI 0x40 3717 field MSGI 0x20 3718 field P_BUSFREE 0x01 3719 enum PHASE_MASK CDO|IOO|MSGO { 3720 P_DATAOUT 0x0, 3721 P_DATAIN IOO, 3722 P_DATAOUT_DT P_DATAOUT|MSGO, 3723 P_DATAIN_DT P_DATAIN|MSGO, 3724 P_COMMAND CDO, 3725 P_MESGOUT CDO|MSGO, 3726 P_STATUS CDO|IOO, 3727 P_MESGIN CDO|IOO|MSGO 3728 } 3729 } 3730 /* 3731 * Value to "or" into the SCBPTR[1] value to 3732 * indicate that an entry in the QINFIFO is valid. 3733 */ 3734 QOUTFIFO_ENTRY_VALID_TAG { 3735 size 1 3736 } 3737 /* 3738 * Kernel and sequencer offsets into the queue of 3739 * incoming target mode command descriptors. The 3740 * queue is full when the KERNEL_TQINPOS == TQINPOS. 3741 */ 3742 KERNEL_TQINPOS { 3743 size 1 3744 count 1 3745 } 3746 TQINPOS { 3747 size 1 3748 count 8 3749 } 3750 /* 3751 * Base address of our shared data with the kernel driver in host 3752 * memory. This includes the qoutfifo and target mode 3753 * incoming command queue. 3754 */ 3755 SHARED_DATA_ADDR { 3756 size 4 3757 } 3758 /* 3759 * Pointer to location in host memory for next 3760 * position in the qoutfifo. 3761 */ 3762 QOUTFIFO_NEXT_ADDR { 3763 size 4 3764 } 3765 ARG_1 { 3766 size 1 3767 mask SEND_MSG 0x80 3768 mask SEND_SENSE 0x40 3769 mask SEND_REJ 0x20 3770 mask MSGOUT_PHASEMIS 0x10 3771 mask EXIT_MSG_LOOP 0x08 3772 mask CONT_MSG_LOOP_WRITE 0x04 3773 mask CONT_MSG_LOOP_READ 0x03 3774 mask CONT_MSG_LOOP_TARG 0x02 3775 alias RETURN_1 3776 } 3777 ARG_2 { 3778 size 1 3779 count 1 3780 alias RETURN_2 3781 } 3782 3783 /* 3784 * Snapshot of MSG_OUT taken after each message is sent. 3785 */ 3786 LAST_MSG { 3787 size 1 3788 } 3789 3790 /* 3791 * Sequences the kernel driver has okayed for us. This allows 3792 * the driver to do things like prevent initiator or target 3793 * operations. 3794 */ 3795 SCSISEQ_TEMPLATE { 3796 size 1 3797 count 7 3798 field MANUALCTL 0x40 3799 field ENSELI 0x20 3800 field ENRSELI 0x10 3801 field MANUALP 0x0C 3802 field ENAUTOATNP 0x02 3803 field ALTSTIM 0x01 3804 } 3805 3806 /* 3807 * The initiator specified tag for this target mode transaction. 3808 */ 3809 INITIATOR_TAG { 3810 size 1 3811 count 1 3812 } 3813 3814 SEQ_FLAGS2 { 3815 size 1 3816 field PENDING_MK_MESSAGE 0x01 3817 field TARGET_MSG_PENDING 0x02 3818 field SELECTOUT_QFROZEN 0x04 3819 } 3820 3821 ALLOCFIFO_SCBPTR { 3822 size 2 3823 } 3824 3825 /* 3826 * The maximum amount of time to wait, when interrupt coalescing 3827 * is enabled, before issueing a CMDCMPLT interrupt for a completed 3828 * command. 3829 */ 3830 INT_COALESCING_TIMER { 3831 size 2 3832 } 3833 3834 /* 3835 * The maximum number of commands to coalesce into a single interrupt. 3836 * Actually the 2's complement of that value to simplify sequencer 3837 * code. 3838 */ 3839 INT_COALESCING_MAXCMDS { 3840 size 1 3841 } 3842 3843 /* 3844 * The minimum number of commands still outstanding required 3845 * to continue coalescing (2's complement of value). 3846 */ 3847 INT_COALESCING_MINCMDS { 3848 size 1 3849 } 3850 3851 /* 3852 * Number of commands "in-flight". 3853 */ 3854 CMDS_PENDING { 3855 size 2 3856 } 3857 3858 /* 3859 * The count of commands that have been coalesced. 3860 */ 3861 INT_COALESCING_CMDCOUNT { 3862 size 1 3863 } 3864 3865 /* 3866 * Since the HS_MAIBOX is self clearing, copy its contents to 3867 * this position in scratch ram every time it changes. 3868 */ 3869 LOCAL_HS_MAILBOX { 3870 size 1 3871 } 3872 /* 3873 * Target-mode CDB type to CDB length table used 3874 * in non-packetized operation. 3875 */ 3876 CMDSIZE_TABLE { 3877 size 8 3878 count 8 3879 } 3880 /* 3881 * When an SCB with the MK_MESSAGE flag is 3882 * queued to the controller, it cannot enter 3883 * the waiting for selection list until the 3884 * selections for any previously queued 3885 * commands to that target complete. During 3886 * the wait, the MK_MESSAGE SCB is queued 3887 * here. 3888 */ 3889 MK_MESSAGE_SCB { 3890 size 2 3891 } 3892 /* 3893 * Saved SCSIID of MK_MESSAGE_SCB to avoid 3894 * an extra SCBPTR operation when deciding 3895 * if the MK_MESSAGE_SCB can be run. 3896 */ 3897 MK_MESSAGE_SCSIID { 3898 size 1 3899 } 3900} 3901 3902/************************* Hardware SCB Definition ****************************/ 3903scb { 3904 address 0x180 3905 size 64 3906 modes 0, 1, 2, 3 3907 SCB_RESIDUAL_DATACNT { 3908 size 4 3909 alias SCB_CDB_STORE 3910 alias SCB_HOST_CDB_PTR 3911 } 3912 SCB_RESIDUAL_SGPTR { 3913 size 4 3914 field SG_ADDR_MASK 0xf8 /* In the last byte */ 3915 field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3916 field SG_LIST_NULL 0x01 /* In the first byte */ 3917 } 3918 SCB_SCSI_STATUS { 3919 size 1 3920 alias SCB_HOST_CDB_LEN 3921 } 3922 SCB_TARGET_PHASES { 3923 size 1 3924 } 3925 SCB_TARGET_DATA_DIR { 3926 size 1 3927 } 3928 SCB_TARGET_ITAG { 3929 size 1 3930 } 3931 SCB_SENSE_BUSADDR { 3932 /* 3933 * Only valid if CDB length is less than 13 bytes or 3934 * we are using a CDB pointer. Otherwise contains 3935 * the last 4 bytes of embedded cdb information. 3936 */ 3937 size 4 3938 alias SCB_NEXT_COMPLETE 3939 } 3940 SCB_TAG { 3941 alias SCB_FIFO_USE_COUNT 3942 size 2 3943 } 3944 SCB_CONTROL { 3945 size 1 3946 field TARGET_SCB 0x80 3947 field DISCENB 0x40 3948 field TAG_ENB 0x20 3949 field MK_MESSAGE 0x10 3950 field STATUS_RCVD 0x08 3951 field DISCONNECTED 0x04 3952 field SCB_TAG_TYPE 0x03 3953 } 3954 SCB_SCSIID { 3955 size 1 3956 field TID 0xF0 3957 field OID 0x0F 3958 } 3959 SCB_LUN { 3960 size 1 3961 field LID 0xff 3962 } 3963 SCB_TASK_ATTRIBUTE { 3964 size 1 3965 /* 3966 * Overloaded field for non-packetized 3967 * ignore wide residue message handling. 3968 */ 3969 field SCB_XFERLEN_ODD 0x01 3970 } 3971 SCB_CDB_LEN { 3972 size 1 3973 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 3974 } 3975 SCB_TASK_MANAGEMENT { 3976 size 1 3977 } 3978 SCB_DATAPTR { 3979 size 8 3980 } 3981 SCB_DATACNT { 3982 /* 3983 * The last byte is really the high address bits for 3984 * the data address. 3985 */ 3986 size 4 3987 field SG_LAST_SEG 0x80 /* In the fourth byte */ 3988 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3989 } 3990 SCB_SGPTR { 3991 size 4 3992 field SG_STATUS_VALID 0x04 /* In the first byte */ 3993 field SG_FULL_RESID 0x02 /* In the first byte */ 3994 field SG_LIST_NULL 0x01 /* In the first byte */ 3995 } 3996 SCB_BUSADDR { 3997 size 4 3998 } 3999 SCB_NEXT { 4000 alias SCB_NEXT_SCB_BUSADDR 4001 size 2 4002 } 4003 SCB_NEXT2 { 4004 size 2 4005 } 4006 SCB_SPARE { 4007 size 8 4008 alias SCB_PKT_LUN 4009 } 4010 SCB_DISCONNECTED_LISTS { 4011 size 8 4012 } 4013} 4014 4015/*********************************** Constants ********************************/ 4016const MK_MESSAGE_BIT_OFFSET 4 4017const TID_SHIFT 4 4018const TARGET_CMD_CMPLT 0xfe 4019const INVALID_ADDR 0x80 4020#define SCB_LIST_NULL 0xff 4021#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 4022 4023const CCSGADDR_MAX 0x80 4024const CCSCBADDR_MAX 0x80 4025const CCSGRAM_MAXSEGS 16 4026 4027/* Selection Timeout Timer Constants */ 4028const STIMESEL_SHIFT 3 4029const STIMESEL_MIN 0x18 4030const STIMESEL_BUG_ADJ 0x8 4031 4032/* WDTR Message values */ 4033const BUS_8_BIT 0x00 4034const BUS_16_BIT 0x01 4035const BUS_32_BIT 0x02 4036 4037/* Offset maximums */ 4038const MAX_OFFSET 0xfe 4039const MAX_OFFSET_PACED 0xfe 4040const MAX_OFFSET_PACED_BUG 0x7f 4041/* 4042 * Some 160 devices incorrectly accept 0xfe as a 4043 * sync offset, but will overrun this value. Limit 4044 * to 0x7f for speed lower than U320 which will 4045 * avoid the persistent sync offset overruns. 4046 */ 4047const MAX_OFFSET_NON_PACED 0x7f 4048const HOST_MSG 0xff 4049 4050/* 4051 * The size of our sense buffers. 4052 * Sense buffer mapping can be handled in either of two ways. 4053 * The first is to allocate a dmamap for each transaction. 4054 * Depending on the architecture, dmamaps can be costly. The 4055 * alternative is to statically map the buffers in much the same 4056 * way we handle our scatter gather lists. The driver implements 4057 * the later. 4058 */ 4059const AHD_SENSE_BUFSIZE 256 4060 4061/* Target mode command processing constants */ 4062const CMD_GROUP_CODE_SHIFT 0x05 4063 4064const STATUS_BUSY 0x08 4065const STATUS_QUEUE_FULL 0x28 4066const STATUS_PKT_SENSE 0xFF 4067const TARGET_DATA_IN 1 4068 4069const SCB_TRANSFER_SIZE_FULL_LUN 56 4070const SCB_TRANSFER_SIZE_1BYTE_LUN 48 4071/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 4072const PKT_OVERRUN_BUFSIZE 512 4073 4074/* 4075 * Timer parameters. 4076 */ 4077const AHD_TIMER_US_PER_TICK 25 4078const AHD_TIMER_MAX_TICKS 0xFFFF 4079const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK) 4080 4081/* 4082 * Downloaded (kernel inserted) constants 4083 */ 4084const SG_PREFETCH_CNT download 4085const SG_PREFETCH_CNT_LIMIT download 4086const SG_PREFETCH_ALIGN_MASK download 4087const SG_PREFETCH_ADDR_MASK download 4088const SG_SIZEOF download 4089const PKT_OVERRUN_BUFOFFSET download 4090const SCB_TRANSFER_SIZE download 4091const CACHELINE_MASK download 4092 4093/* 4094 * BIOS SCB offsets 4095 */ 4096const NVRAM_SCB_OFFSET 0x2C 4097