xref: /openbmc/linux/drivers/scsi/advansys.c (revision e23feb16)
1 #define DRV_NAME "advansys"
2 #define ASC_VERSION "3.4"	/* AdvanSys Driver Version */
3 
4 /*
5  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6  *
7  * Copyright (c) 1995-2000 Advanced System Products, Inc.
8  * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
9  * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
10  * All Rights Reserved.
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  */
17 
18 /*
19  * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20  * changed its name to ConnectCom Solutions, Inc.
21  * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
22  */
23 
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/ioport.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/slab.h>
32 #include <linux/mm.h>
33 #include <linux/proc_fs.h>
34 #include <linux/init.h>
35 #include <linux/blkdev.h>
36 #include <linux/isa.h>
37 #include <linux/eisa.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/firmware.h>
42 
43 #include <asm/io.h>
44 #include <asm/dma.h>
45 
46 #include <scsi/scsi_cmnd.h>
47 #include <scsi/scsi_device.h>
48 #include <scsi/scsi_tcq.h>
49 #include <scsi/scsi.h>
50 #include <scsi/scsi_host.h>
51 
52 /* FIXME:
53  *
54  *  1. Although all of the necessary command mapping places have the
55  *     appropriate dma_map.. APIs, the driver still processes its internal
56  *     queue using bus_to_virt() and virt_to_bus() which are illegal under
57  *     the API.  The entire queue processing structure will need to be
58  *     altered to fix this.
59  *  2. Need to add memory mapping workaround. Test the memory mapping.
60  *     If it doesn't work revert to I/O port access. Can a test be done
61  *     safely?
62  *  3. Handle an interrupt not working. Keep an interrupt counter in
63  *     the interrupt handler. In the timeout function if the interrupt
64  *     has not occurred then print a message and run in polled mode.
65  *  4. Need to add support for target mode commands, cf. CAM XPT.
66  *  5. check DMA mapping functions for failure
67  *  6. Use scsi_transport_spi
68  *  7. advansys_info is not safe against multiple simultaneous callers
69  *  8. Add module_param to override ISA/VLB ioport array
70  */
71 #warning this driver is still not properly converted to the DMA API
72 
73 /* Enable driver /proc statistics. */
74 #define ADVANSYS_STATS
75 
76 /* Enable driver tracing. */
77 #undef ADVANSYS_DEBUG
78 
79 /*
80  * Portable Data Types
81  *
82  * Any instance where a 32-bit long or pointer type is assumed
83  * for precision or HW defined structures, the following define
84  * types must be used. In Linux the char, short, and int types
85  * are all consistent at 8, 16, and 32 bits respectively. Pointers
86  * and long types are 64 bits on Alpha and UltraSPARC.
87  */
88 #define ASC_PADDR __u32		/* Physical/Bus address data type. */
89 #define ASC_VADDR __u32		/* Virtual address data type. */
90 #define ASC_DCNT  __u32		/* Unsigned Data count type. */
91 #define ASC_SDCNT __s32		/* Signed Data count type. */
92 
93 typedef unsigned char uchar;
94 
95 #ifndef TRUE
96 #define TRUE     (1)
97 #endif
98 #ifndef FALSE
99 #define FALSE    (0)
100 #endif
101 
102 #define ERR      (-1)
103 #define UW_ERR   (uint)(0xFFFF)
104 #define isodd_word(val)   ((((uint)val) & (uint)0x0001) != 0)
105 
106 #define PCI_VENDOR_ID_ASP		0x10cd
107 #define PCI_DEVICE_ID_ASP_1200A		0x1100
108 #define PCI_DEVICE_ID_ASP_ABP940	0x1200
109 #define PCI_DEVICE_ID_ASP_ABP940U	0x1300
110 #define PCI_DEVICE_ID_ASP_ABP940UW	0x2300
111 #define PCI_DEVICE_ID_38C0800_REV1	0x2500
112 #define PCI_DEVICE_ID_38C1600_REV1	0x2700
113 
114 /*
115  * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
116  * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
117  * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
118  * SRB structure.
119  */
120 #define CC_VERY_LONG_SG_LIST 0
121 #define ASC_SRB2SCSIQ(srb_ptr)  (srb_ptr)
122 
123 #define PortAddr                 unsigned int	/* port address size  */
124 #define inp(port)                inb(port)
125 #define outp(port, byte)         outb((byte), (port))
126 
127 #define inpw(port)               inw(port)
128 #define outpw(port, word)        outw((word), (port))
129 
130 #define ASC_MAX_SG_QUEUE    7
131 #define ASC_MAX_SG_LIST     255
132 
133 #define ASC_CS_TYPE  unsigned short
134 
135 #define ASC_IS_ISA          (0x0001)
136 #define ASC_IS_ISAPNP       (0x0081)
137 #define ASC_IS_EISA         (0x0002)
138 #define ASC_IS_PCI          (0x0004)
139 #define ASC_IS_PCI_ULTRA    (0x0104)
140 #define ASC_IS_PCMCIA       (0x0008)
141 #define ASC_IS_MCA          (0x0020)
142 #define ASC_IS_VL           (0x0040)
143 #define ASC_IS_WIDESCSI_16  (0x0100)
144 #define ASC_IS_WIDESCSI_32  (0x0200)
145 #define ASC_IS_BIG_ENDIAN   (0x8000)
146 
147 #define ASC_CHIP_MIN_VER_VL      (0x01)
148 #define ASC_CHIP_MAX_VER_VL      (0x07)
149 #define ASC_CHIP_MIN_VER_PCI     (0x09)
150 #define ASC_CHIP_MAX_VER_PCI     (0x0F)
151 #define ASC_CHIP_VER_PCI_BIT     (0x08)
152 #define ASC_CHIP_MIN_VER_ISA     (0x11)
153 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
154 #define ASC_CHIP_MAX_VER_ISA     (0x27)
155 #define ASC_CHIP_VER_ISA_BIT     (0x30)
156 #define ASC_CHIP_VER_ISAPNP_BIT  (0x20)
157 #define ASC_CHIP_VER_ASYN_BUG    (0x21)
158 #define ASC_CHIP_VER_PCI             0x08
159 #define ASC_CHIP_VER_PCI_ULTRA_3150  (ASC_CHIP_VER_PCI | 0x02)
160 #define ASC_CHIP_VER_PCI_ULTRA_3050  (ASC_CHIP_VER_PCI | 0x03)
161 #define ASC_CHIP_MIN_VER_EISA (0x41)
162 #define ASC_CHIP_MAX_VER_EISA (0x47)
163 #define ASC_CHIP_VER_EISA_BIT (0x40)
164 #define ASC_CHIP_LATEST_VER_EISA   ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
165 #define ASC_MAX_VL_DMA_COUNT    (0x07FFFFFFL)
166 #define ASC_MAX_PCI_DMA_COUNT   (0xFFFFFFFFL)
167 #define ASC_MAX_ISA_DMA_COUNT   (0x00FFFFFFL)
168 
169 #define ASC_SCSI_ID_BITS  3
170 #define ASC_SCSI_TIX_TYPE     uchar
171 #define ASC_ALL_DEVICE_BIT_SET  0xFF
172 #define ASC_SCSI_BIT_ID_TYPE  uchar
173 #define ASC_MAX_TID       7
174 #define ASC_MAX_LUN       7
175 #define ASC_SCSI_WIDTH_BIT_SET  0xFF
176 #define ASC_MAX_SENSE_LEN   32
177 #define ASC_MIN_SENSE_LEN   14
178 #define ASC_SCSI_RESET_HOLD_TIME_US  60
179 
180 /*
181  * Narrow boards only support 12-byte commands, while wide boards
182  * extend to 16-byte commands.
183  */
184 #define ASC_MAX_CDB_LEN     12
185 #define ADV_MAX_CDB_LEN     16
186 
187 #define MS_SDTR_LEN    0x03
188 #define MS_WDTR_LEN    0x02
189 
190 #define ASC_SG_LIST_PER_Q   7
191 #define QS_FREE        0x00
192 #define QS_READY       0x01
193 #define QS_DISC1       0x02
194 #define QS_DISC2       0x04
195 #define QS_BUSY        0x08
196 #define QS_ABORTED     0x40
197 #define QS_DONE        0x80
198 #define QC_NO_CALLBACK   0x01
199 #define QC_SG_SWAP_QUEUE 0x02
200 #define QC_SG_HEAD       0x04
201 #define QC_DATA_IN       0x08
202 #define QC_DATA_OUT      0x10
203 #define QC_URGENT        0x20
204 #define QC_MSG_OUT       0x40
205 #define QC_REQ_SENSE     0x80
206 #define QCSG_SG_XFER_LIST  0x02
207 #define QCSG_SG_XFER_MORE  0x04
208 #define QCSG_SG_XFER_END   0x08
209 #define QD_IN_PROGRESS       0x00
210 #define QD_NO_ERROR          0x01
211 #define QD_ABORTED_BY_HOST   0x02
212 #define QD_WITH_ERROR        0x04
213 #define QD_INVALID_REQUEST   0x80
214 #define QD_INVALID_HOST_NUM  0x81
215 #define QD_INVALID_DEVICE    0x82
216 #define QD_ERR_INTERNAL      0xFF
217 #define QHSTA_NO_ERROR               0x00
218 #define QHSTA_M_SEL_TIMEOUT          0x11
219 #define QHSTA_M_DATA_OVER_RUN        0x12
220 #define QHSTA_M_DATA_UNDER_RUN       0x12
221 #define QHSTA_M_UNEXPECTED_BUS_FREE  0x13
222 #define QHSTA_M_BAD_BUS_PHASE_SEQ    0x14
223 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
224 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
225 #define QHSTA_D_HOST_ABORT_FAILED       0x23
226 #define QHSTA_D_EXE_SCSI_Q_FAILED       0x24
227 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
228 #define QHSTA_D_ASPI_NO_BUF_POOL        0x26
229 #define QHSTA_M_WTM_TIMEOUT         0x41
230 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
231 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
232 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
233 #define QHSTA_M_TARGET_STATUS_BUSY  0x45
234 #define QHSTA_M_BAD_TAG_CODE        0x46
235 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
236 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
237 #define QHSTA_D_LRAM_CMP_ERROR        0x81
238 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
239 #define ASC_FLAG_SCSIQ_REQ        0x01
240 #define ASC_FLAG_BIOS_SCSIQ_REQ   0x02
241 #define ASC_FLAG_BIOS_ASYNC_IO    0x04
242 #define ASC_FLAG_SRB_LINEAR_ADDR  0x08
243 #define ASC_FLAG_WIN16            0x10
244 #define ASC_FLAG_WIN32            0x20
245 #define ASC_FLAG_ISA_OVER_16MB    0x40
246 #define ASC_FLAG_DOS_VM_CALLBACK  0x80
247 #define ASC_TAG_FLAG_EXTRA_BYTES               0x10
248 #define ASC_TAG_FLAG_DISABLE_DISCONNECT        0x04
249 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
250 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
251 #define ASC_SCSIQ_CPY_BEG              4
252 #define ASC_SCSIQ_SGHD_CPY_BEG         2
253 #define ASC_SCSIQ_B_FWD                0
254 #define ASC_SCSIQ_B_BWD                1
255 #define ASC_SCSIQ_B_STATUS             2
256 #define ASC_SCSIQ_B_QNO                3
257 #define ASC_SCSIQ_B_CNTL               4
258 #define ASC_SCSIQ_B_SG_QUEUE_CNT       5
259 #define ASC_SCSIQ_D_DATA_ADDR          8
260 #define ASC_SCSIQ_D_DATA_CNT          12
261 #define ASC_SCSIQ_B_SENSE_LEN         20
262 #define ASC_SCSIQ_DONE_INFO_BEG       22
263 #define ASC_SCSIQ_D_SRBPTR            22
264 #define ASC_SCSIQ_B_TARGET_IX         26
265 #define ASC_SCSIQ_B_CDB_LEN           28
266 #define ASC_SCSIQ_B_TAG_CODE          29
267 #define ASC_SCSIQ_W_VM_ID             30
268 #define ASC_SCSIQ_DONE_STATUS         32
269 #define ASC_SCSIQ_HOST_STATUS         33
270 #define ASC_SCSIQ_SCSI_STATUS         34
271 #define ASC_SCSIQ_CDB_BEG             36
272 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
273 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT  60
274 #define ASC_SCSIQ_B_FIRST_SG_WK_QP    48
275 #define ASC_SCSIQ_B_SG_WK_QP          49
276 #define ASC_SCSIQ_B_SG_WK_IX          50
277 #define ASC_SCSIQ_W_ALT_DC1           52
278 #define ASC_SCSIQ_B_LIST_CNT          6
279 #define ASC_SCSIQ_B_CUR_LIST_CNT      7
280 #define ASC_SGQ_B_SG_CNTL             4
281 #define ASC_SGQ_B_SG_HEAD_QP          5
282 #define ASC_SGQ_B_SG_LIST_CNT         6
283 #define ASC_SGQ_B_SG_CUR_LIST_CNT     7
284 #define ASC_SGQ_LIST_BEG              8
285 #define ASC_DEF_SCSI1_QNG    4
286 #define ASC_MAX_SCSI1_QNG    4
287 #define ASC_DEF_SCSI2_QNG    16
288 #define ASC_MAX_SCSI2_QNG    32
289 #define ASC_TAG_CODE_MASK    0x23
290 #define ASC_STOP_REQ_RISC_STOP      0x01
291 #define ASC_STOP_ACK_RISC_STOP      0x03
292 #define ASC_STOP_CLEAN_UP_BUSY_Q    0x10
293 #define ASC_STOP_CLEAN_UP_DISC_Q    0x20
294 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
295 #define ASC_TIDLUN_TO_IX(tid, lun)  (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
296 #define ASC_TID_TO_TARGET_ID(tid)   (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
297 #define ASC_TIX_TO_TARGET_ID(tix)   (0x01 << ((tix) & ASC_MAX_TID))
298 #define ASC_TIX_TO_TID(tix)         ((tix) & ASC_MAX_TID)
299 #define ASC_TID_TO_TIX(tid)         ((tid) & ASC_MAX_TID)
300 #define ASC_TIX_TO_LUN(tix)         (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
301 #define ASC_QNO_TO_QADDR(q_no)      ((ASC_QADR_BEG)+((int)(q_no) << 6))
302 
303 typedef struct asc_scsiq_1 {
304 	uchar status;
305 	uchar q_no;
306 	uchar cntl;
307 	uchar sg_queue_cnt;
308 	uchar target_id;
309 	uchar target_lun;
310 	ASC_PADDR data_addr;
311 	ASC_DCNT data_cnt;
312 	ASC_PADDR sense_addr;
313 	uchar sense_len;
314 	uchar extra_bytes;
315 } ASC_SCSIQ_1;
316 
317 typedef struct asc_scsiq_2 {
318 	ASC_VADDR srb_ptr;
319 	uchar target_ix;
320 	uchar flag;
321 	uchar cdb_len;
322 	uchar tag_code;
323 	ushort vm_id;
324 } ASC_SCSIQ_2;
325 
326 typedef struct asc_scsiq_3 {
327 	uchar done_stat;
328 	uchar host_stat;
329 	uchar scsi_stat;
330 	uchar scsi_msg;
331 } ASC_SCSIQ_3;
332 
333 typedef struct asc_scsiq_4 {
334 	uchar cdb[ASC_MAX_CDB_LEN];
335 	uchar y_first_sg_list_qp;
336 	uchar y_working_sg_qp;
337 	uchar y_working_sg_ix;
338 	uchar y_res;
339 	ushort x_req_count;
340 	ushort x_reconnect_rtn;
341 	ASC_PADDR x_saved_data_addr;
342 	ASC_DCNT x_saved_data_cnt;
343 } ASC_SCSIQ_4;
344 
345 typedef struct asc_q_done_info {
346 	ASC_SCSIQ_2 d2;
347 	ASC_SCSIQ_3 d3;
348 	uchar q_status;
349 	uchar q_no;
350 	uchar cntl;
351 	uchar sense_len;
352 	uchar extra_bytes;
353 	uchar res;
354 	ASC_DCNT remain_bytes;
355 } ASC_QDONE_INFO;
356 
357 typedef struct asc_sg_list {
358 	ASC_PADDR addr;
359 	ASC_DCNT bytes;
360 } ASC_SG_LIST;
361 
362 typedef struct asc_sg_head {
363 	ushort entry_cnt;
364 	ushort queue_cnt;
365 	ushort entry_to_copy;
366 	ushort res;
367 	ASC_SG_LIST sg_list[0];
368 } ASC_SG_HEAD;
369 
370 typedef struct asc_scsi_q {
371 	ASC_SCSIQ_1 q1;
372 	ASC_SCSIQ_2 q2;
373 	uchar *cdbptr;
374 	ASC_SG_HEAD *sg_head;
375 	ushort remain_sg_entry_cnt;
376 	ushort next_sg_index;
377 } ASC_SCSI_Q;
378 
379 typedef struct asc_scsi_req_q {
380 	ASC_SCSIQ_1 r1;
381 	ASC_SCSIQ_2 r2;
382 	uchar *cdbptr;
383 	ASC_SG_HEAD *sg_head;
384 	uchar *sense_ptr;
385 	ASC_SCSIQ_3 r3;
386 	uchar cdb[ASC_MAX_CDB_LEN];
387 	uchar sense[ASC_MIN_SENSE_LEN];
388 } ASC_SCSI_REQ_Q;
389 
390 typedef struct asc_scsi_bios_req_q {
391 	ASC_SCSIQ_1 r1;
392 	ASC_SCSIQ_2 r2;
393 	uchar *cdbptr;
394 	ASC_SG_HEAD *sg_head;
395 	uchar *sense_ptr;
396 	ASC_SCSIQ_3 r3;
397 	uchar cdb[ASC_MAX_CDB_LEN];
398 	uchar sense[ASC_MIN_SENSE_LEN];
399 } ASC_SCSI_BIOS_REQ_Q;
400 
401 typedef struct asc_risc_q {
402 	uchar fwd;
403 	uchar bwd;
404 	ASC_SCSIQ_1 i1;
405 	ASC_SCSIQ_2 i2;
406 	ASC_SCSIQ_3 i3;
407 	ASC_SCSIQ_4 i4;
408 } ASC_RISC_Q;
409 
410 typedef struct asc_sg_list_q {
411 	uchar seq_no;
412 	uchar q_no;
413 	uchar cntl;
414 	uchar sg_head_qp;
415 	uchar sg_list_cnt;
416 	uchar sg_cur_list_cnt;
417 } ASC_SG_LIST_Q;
418 
419 typedef struct asc_risc_sg_list_q {
420 	uchar fwd;
421 	uchar bwd;
422 	ASC_SG_LIST_Q sg;
423 	ASC_SG_LIST sg_list[7];
424 } ASC_RISC_SG_LIST_Q;
425 
426 #define ASCQ_ERR_Q_STATUS             0x0D
427 #define ASCQ_ERR_CUR_QNG              0x17
428 #define ASCQ_ERR_SG_Q_LINKS           0x18
429 #define ASCQ_ERR_ISR_RE_ENTRY         0x1A
430 #define ASCQ_ERR_CRITICAL_RE_ENTRY    0x1B
431 #define ASCQ_ERR_ISR_ON_CRITICAL      0x1C
432 
433 /*
434  * Warning code values are set in ASC_DVC_VAR  'warn_code'.
435  */
436 #define ASC_WARN_NO_ERROR             0x0000
437 #define ASC_WARN_IO_PORT_ROTATE       0x0001
438 #define ASC_WARN_EEPROM_CHKSUM        0x0002
439 #define ASC_WARN_IRQ_MODIFIED         0x0004
440 #define ASC_WARN_AUTO_CONFIG          0x0008
441 #define ASC_WARN_CMD_QNG_CONFLICT     0x0010
442 #define ASC_WARN_EEPROM_RECOVER       0x0020
443 #define ASC_WARN_CFG_MSW_RECOVER      0x0040
444 
445 /*
446  * Error code values are set in {ASC/ADV}_DVC_VAR  'err_code'.
447  */
448 #define ASC_IERR_NO_CARRIER		0x0001	/* No more carrier memory */
449 #define ASC_IERR_MCODE_CHKSUM		0x0002	/* micro code check sum error */
450 #define ASC_IERR_SET_PC_ADDR		0x0004
451 #define ASC_IERR_START_STOP_CHIP	0x0008	/* start/stop chip failed */
452 #define ASC_IERR_ILLEGAL_CONNECTION	0x0010	/* Illegal cable connection */
453 #define ASC_IERR_SINGLE_END_DEVICE	0x0020	/* SE device on DIFF bus */
454 #define ASC_IERR_REVERSED_CABLE		0x0040	/* Narrow flat cable reversed */
455 #define ASC_IERR_SET_SCSI_ID		0x0080	/* set SCSI ID failed */
456 #define ASC_IERR_HVD_DEVICE		0x0100	/* HVD device on LVD port */
457 #define ASC_IERR_BAD_SIGNATURE		0x0200	/* signature not found */
458 #define ASC_IERR_NO_BUS_TYPE		0x0400
459 #define ASC_IERR_BIST_PRE_TEST		0x0800	/* BIST pre-test error */
460 #define ASC_IERR_BIST_RAM_TEST		0x1000	/* BIST RAM test error */
461 #define ASC_IERR_BAD_CHIPTYPE		0x2000	/* Invalid chip_type setting */
462 
463 #define ASC_DEF_MAX_TOTAL_QNG   (0xF0)
464 #define ASC_MIN_TAG_Q_PER_DVC   (0x04)
465 #define ASC_MIN_FREE_Q        (0x02)
466 #define ASC_MIN_TOTAL_QNG     ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
467 #define ASC_MAX_TOTAL_QNG 240
468 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
469 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG   8
470 #define ASC_MAX_PCI_INRAM_TOTAL_QNG  20
471 #define ASC_MAX_INRAM_TAG_QNG   16
472 #define ASC_IOADR_GAP   0x10
473 #define ASC_SYN_MAX_OFFSET         0x0F
474 #define ASC_DEF_SDTR_OFFSET        0x0F
475 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX  0x02
476 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
477 
478 /* The narrow chip only supports a limited selection of transfer rates.
479  * These are encoded in the range 0..7 or 0..15 depending whether the chip
480  * is Ultra-capable or not.  These tables let us convert from one to the other.
481  */
482 static const unsigned char asc_syn_xfer_period[8] = {
483 	25, 30, 35, 40, 50, 60, 70, 85
484 };
485 
486 static const unsigned char asc_syn_ultra_xfer_period[16] = {
487 	12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
488 };
489 
490 typedef struct ext_msg {
491 	uchar msg_type;
492 	uchar msg_len;
493 	uchar msg_req;
494 	union {
495 		struct {
496 			uchar sdtr_xfer_period;
497 			uchar sdtr_req_ack_offset;
498 		} sdtr;
499 		struct {
500 			uchar wdtr_width;
501 		} wdtr;
502 		struct {
503 			uchar mdp_b3;
504 			uchar mdp_b2;
505 			uchar mdp_b1;
506 			uchar mdp_b0;
507 		} mdp;
508 	} u_ext_msg;
509 	uchar res;
510 } EXT_MSG;
511 
512 #define xfer_period     u_ext_msg.sdtr.sdtr_xfer_period
513 #define req_ack_offset  u_ext_msg.sdtr.sdtr_req_ack_offset
514 #define wdtr_width      u_ext_msg.wdtr.wdtr_width
515 #define mdp_b3          u_ext_msg.mdp_b3
516 #define mdp_b2          u_ext_msg.mdp_b2
517 #define mdp_b1          u_ext_msg.mdp_b1
518 #define mdp_b0          u_ext_msg.mdp_b0
519 
520 typedef struct asc_dvc_cfg {
521 	ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
522 	ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
523 	ASC_SCSI_BIT_ID_TYPE disc_enable;
524 	ASC_SCSI_BIT_ID_TYPE sdtr_enable;
525 	uchar chip_scsi_id;
526 	uchar isa_dma_speed;
527 	uchar isa_dma_channel;
528 	uchar chip_version;
529 	ushort mcode_date;
530 	ushort mcode_version;
531 	uchar max_tag_qng[ASC_MAX_TID + 1];
532 	uchar sdtr_period_offset[ASC_MAX_TID + 1];
533 	uchar adapter_info[6];
534 } ASC_DVC_CFG;
535 
536 #define ASC_DEF_DVC_CNTL       0xFFFF
537 #define ASC_DEF_CHIP_SCSI_ID   7
538 #define ASC_DEF_ISA_DMA_SPEED  4
539 #define ASC_INIT_STATE_BEG_GET_CFG   0x0001
540 #define ASC_INIT_STATE_END_GET_CFG   0x0002
541 #define ASC_INIT_STATE_BEG_SET_CFG   0x0004
542 #define ASC_INIT_STATE_END_SET_CFG   0x0008
543 #define ASC_INIT_STATE_BEG_LOAD_MC   0x0010
544 #define ASC_INIT_STATE_END_LOAD_MC   0x0020
545 #define ASC_INIT_STATE_BEG_INQUIRY   0x0040
546 #define ASC_INIT_STATE_END_INQUIRY   0x0080
547 #define ASC_INIT_RESET_SCSI_DONE     0x0100
548 #define ASC_INIT_STATE_WITHOUT_EEP   0x8000
549 #define ASC_BUG_FIX_IF_NOT_DWB       0x0001
550 #define ASC_BUG_FIX_ASYN_USE_SYN     0x0002
551 #define ASC_MIN_TAGGED_CMD  7
552 #define ASC_MAX_SCSI_RESET_WAIT      30
553 #define ASC_OVERRUN_BSIZE		64
554 
555 struct asc_dvc_var;		/* Forward Declaration. */
556 
557 typedef struct asc_dvc_var {
558 	PortAddr iop_base;
559 	ushort err_code;
560 	ushort dvc_cntl;
561 	ushort bug_fix_cntl;
562 	ushort bus_type;
563 	ASC_SCSI_BIT_ID_TYPE init_sdtr;
564 	ASC_SCSI_BIT_ID_TYPE sdtr_done;
565 	ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
566 	ASC_SCSI_BIT_ID_TYPE unit_not_ready;
567 	ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
568 	ASC_SCSI_BIT_ID_TYPE start_motor;
569 	uchar *overrun_buf;
570 	dma_addr_t overrun_dma;
571 	uchar scsi_reset_wait;
572 	uchar chip_no;
573 	char is_in_int;
574 	uchar max_total_qng;
575 	uchar cur_total_qng;
576 	uchar in_critical_cnt;
577 	uchar last_q_shortage;
578 	ushort init_state;
579 	uchar cur_dvc_qng[ASC_MAX_TID + 1];
580 	uchar max_dvc_qng[ASC_MAX_TID + 1];
581 	ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
582 	ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
583 	const uchar *sdtr_period_tbl;
584 	ASC_DVC_CFG *cfg;
585 	ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
586 	char redo_scam;
587 	ushort res2;
588 	uchar dos_int13_table[ASC_MAX_TID + 1];
589 	ASC_DCNT max_dma_count;
590 	ASC_SCSI_BIT_ID_TYPE no_scam;
591 	ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
592 	uchar min_sdtr_index;
593 	uchar max_sdtr_index;
594 	struct asc_board *drv_ptr;
595 	int ptr_map_count;
596 	void **ptr_map;
597 	ASC_DCNT uc_break;
598 } ASC_DVC_VAR;
599 
600 typedef struct asc_dvc_inq_info {
601 	uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
602 } ASC_DVC_INQ_INFO;
603 
604 typedef struct asc_cap_info {
605 	ASC_DCNT lba;
606 	ASC_DCNT blk_size;
607 } ASC_CAP_INFO;
608 
609 typedef struct asc_cap_info_array {
610 	ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
611 } ASC_CAP_INFO_ARRAY;
612 
613 #define ASC_MCNTL_NO_SEL_TIMEOUT  (ushort)0x0001
614 #define ASC_MCNTL_NULL_TARGET     (ushort)0x0002
615 #define ASC_CNTL_INITIATOR         (ushort)0x0001
616 #define ASC_CNTL_BIOS_GT_1GB       (ushort)0x0002
617 #define ASC_CNTL_BIOS_GT_2_DISK    (ushort)0x0004
618 #define ASC_CNTL_BIOS_REMOVABLE    (ushort)0x0008
619 #define ASC_CNTL_NO_SCAM           (ushort)0x0010
620 #define ASC_CNTL_INT_MULTI_Q       (ushort)0x0080
621 #define ASC_CNTL_NO_LUN_SUPPORT    (ushort)0x0040
622 #define ASC_CNTL_NO_VERIFY_COPY    (ushort)0x0100
623 #define ASC_CNTL_RESET_SCSI        (ushort)0x0200
624 #define ASC_CNTL_INIT_INQUIRY      (ushort)0x0400
625 #define ASC_CNTL_INIT_VERBOSE      (ushort)0x0800
626 #define ASC_CNTL_SCSI_PARITY       (ushort)0x1000
627 #define ASC_CNTL_BURST_MODE        (ushort)0x2000
628 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
629 #define ASC_EEP_DVC_CFG_BEG_VL    2
630 #define ASC_EEP_MAX_DVC_ADDR_VL   15
631 #define ASC_EEP_DVC_CFG_BEG      32
632 #define ASC_EEP_MAX_DVC_ADDR     45
633 #define ASC_EEP_MAX_RETRY        20
634 
635 /*
636  * These macros keep the chip SCSI id and ISA DMA speed
637  * bitfields in board order. C bitfields aren't portable
638  * between big and little-endian platforms so they are
639  * not used.
640  */
641 
642 #define ASC_EEP_GET_CHIP_ID(cfg)    ((cfg)->id_speed & 0x0f)
643 #define ASC_EEP_GET_DMA_SPD(cfg)    (((cfg)->id_speed & 0xf0) >> 4)
644 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
645    ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
646 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
647    ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
648 
649 typedef struct asceep_config {
650 	ushort cfg_lsw;
651 	ushort cfg_msw;
652 	uchar init_sdtr;
653 	uchar disc_enable;
654 	uchar use_cmd_qng;
655 	uchar start_motor;
656 	uchar max_total_qng;
657 	uchar max_tag_qng;
658 	uchar bios_scan;
659 	uchar power_up_wait;
660 	uchar no_scam;
661 	uchar id_speed;		/* low order 4 bits is chip scsi id */
662 	/* high order 4 bits is isa dma speed */
663 	uchar dos_int13_table[ASC_MAX_TID + 1];
664 	uchar adapter_info[6];
665 	ushort cntl;
666 	ushort chksum;
667 } ASCEEP_CONFIG;
668 
669 #define ASC_EEP_CMD_READ          0x80
670 #define ASC_EEP_CMD_WRITE         0x40
671 #define ASC_EEP_CMD_WRITE_ABLE    0x30
672 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
673 #define ASCV_MSGOUT_BEG         0x0000
674 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
675 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
676 #define ASCV_BREAK_SAVED_CODE   (ushort)0x0006
677 #define ASCV_MSGIN_BEG          (ASCV_MSGOUT_BEG+8)
678 #define ASCV_MSGIN_SDTR_PERIOD  (ASCV_MSGIN_BEG+3)
679 #define ASCV_MSGIN_SDTR_OFFSET  (ASCV_MSGIN_BEG+4)
680 #define ASCV_SDTR_DATA_BEG      (ASCV_MSGIN_BEG+8)
681 #define ASCV_SDTR_DONE_BEG      (ASCV_SDTR_DATA_BEG+8)
682 #define ASCV_MAX_DVC_QNG_BEG    (ushort)0x0020
683 #define ASCV_BREAK_ADDR           (ushort)0x0028
684 #define ASCV_BREAK_NOTIFY_COUNT   (ushort)0x002A
685 #define ASCV_BREAK_CONTROL        (ushort)0x002C
686 #define ASCV_BREAK_HIT_COUNT      (ushort)0x002E
687 
688 #define ASCV_ASCDVC_ERR_CODE_W  (ushort)0x0030
689 #define ASCV_MCODE_CHKSUM_W   (ushort)0x0032
690 #define ASCV_MCODE_SIZE_W     (ushort)0x0034
691 #define ASCV_STOP_CODE_B      (ushort)0x0036
692 #define ASCV_DVC_ERR_CODE_B   (ushort)0x0037
693 #define ASCV_OVERRUN_PADDR_D  (ushort)0x0038
694 #define ASCV_OVERRUN_BSIZE_D  (ushort)0x003C
695 #define ASCV_HALTCODE_W       (ushort)0x0040
696 #define ASCV_CHKSUM_W         (ushort)0x0042
697 #define ASCV_MC_DATE_W        (ushort)0x0044
698 #define ASCV_MC_VER_W         (ushort)0x0046
699 #define ASCV_NEXTRDY_B        (ushort)0x0048
700 #define ASCV_DONENEXT_B       (ushort)0x0049
701 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
702 #define ASCV_SCSIBUSY_B       (ushort)0x004B
703 #define ASCV_Q_DONE_IN_PROGRESS_B  (ushort)0x004C
704 #define ASCV_CURCDB_B         (ushort)0x004D
705 #define ASCV_RCLUN_B          (ushort)0x004E
706 #define ASCV_BUSY_QHEAD_B     (ushort)0x004F
707 #define ASCV_DISC1_QHEAD_B    (ushort)0x0050
708 #define ASCV_DISC_ENABLE_B    (ushort)0x0052
709 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
710 #define ASCV_HOSTSCSI_ID_B    (ushort)0x0055
711 #define ASCV_MCODE_CNTL_B     (ushort)0x0056
712 #define ASCV_NULL_TARGET_B    (ushort)0x0057
713 #define ASCV_FREE_Q_HEAD_W    (ushort)0x0058
714 #define ASCV_DONE_Q_TAIL_W    (ushort)0x005A
715 #define ASCV_FREE_Q_HEAD_B    (ushort)(ASCV_FREE_Q_HEAD_W+1)
716 #define ASCV_DONE_Q_TAIL_B    (ushort)(ASCV_DONE_Q_TAIL_W+1)
717 #define ASCV_HOST_FLAG_B      (ushort)0x005D
718 #define ASCV_TOTAL_READY_Q_B  (ushort)0x0064
719 #define ASCV_VER_SERIAL_B     (ushort)0x0065
720 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
721 #define ASCV_WTM_FLAG_B       (ushort)0x0068
722 #define ASCV_RISC_FLAG_B      (ushort)0x006A
723 #define ASCV_REQ_SG_LIST_QP   (ushort)0x006B
724 #define ASC_HOST_FLAG_IN_ISR        0x01
725 #define ASC_HOST_FLAG_ACK_INT       0x02
726 #define ASC_RISC_FLAG_GEN_INT      0x01
727 #define ASC_RISC_FLAG_REQ_SG_LIST  0x02
728 #define IOP_CTRL         (0x0F)
729 #define IOP_STATUS       (0x0E)
730 #define IOP_INT_ACK      IOP_STATUS
731 #define IOP_REG_IFC      (0x0D)
732 #define IOP_SYN_OFFSET    (0x0B)
733 #define IOP_EXTRA_CONTROL (0x0D)
734 #define IOP_REG_PC        (0x0C)
735 #define IOP_RAM_ADDR      (0x0A)
736 #define IOP_RAM_DATA      (0x08)
737 #define IOP_EEP_DATA      (0x06)
738 #define IOP_EEP_CMD       (0x07)
739 #define IOP_VERSION       (0x03)
740 #define IOP_CONFIG_HIGH   (0x04)
741 #define IOP_CONFIG_LOW    (0x02)
742 #define IOP_SIG_BYTE      (0x01)
743 #define IOP_SIG_WORD      (0x00)
744 #define IOP_REG_DC1      (0x0E)
745 #define IOP_REG_DC0      (0x0C)
746 #define IOP_REG_SB       (0x0B)
747 #define IOP_REG_DA1      (0x0A)
748 #define IOP_REG_DA0      (0x08)
749 #define IOP_REG_SC       (0x09)
750 #define IOP_DMA_SPEED    (0x07)
751 #define IOP_REG_FLAG     (0x07)
752 #define IOP_FIFO_H       (0x06)
753 #define IOP_FIFO_L       (0x04)
754 #define IOP_REG_ID       (0x05)
755 #define IOP_REG_QP       (0x03)
756 #define IOP_REG_IH       (0x02)
757 #define IOP_REG_IX       (0x01)
758 #define IOP_REG_AX       (0x00)
759 #define IFC_REG_LOCK      (0x00)
760 #define IFC_REG_UNLOCK    (0x09)
761 #define IFC_WR_EN_FILTER  (0x10)
762 #define IFC_RD_NO_EEPROM  (0x10)
763 #define IFC_SLEW_RATE     (0x20)
764 #define IFC_ACT_NEG       (0x40)
765 #define IFC_INP_FILTER    (0x80)
766 #define IFC_INIT_DEFAULT  (IFC_ACT_NEG | IFC_REG_UNLOCK)
767 #define SC_SEL   (uchar)(0x80)
768 #define SC_BSY   (uchar)(0x40)
769 #define SC_ACK   (uchar)(0x20)
770 #define SC_REQ   (uchar)(0x10)
771 #define SC_ATN   (uchar)(0x08)
772 #define SC_IO    (uchar)(0x04)
773 #define SC_CD    (uchar)(0x02)
774 #define SC_MSG   (uchar)(0x01)
775 #define SEC_SCSI_CTL         (uchar)(0x80)
776 #define SEC_ACTIVE_NEGATE    (uchar)(0x40)
777 #define SEC_SLEW_RATE        (uchar)(0x20)
778 #define SEC_ENABLE_FILTER    (uchar)(0x10)
779 #define ASC_HALT_EXTMSG_IN     (ushort)0x8000
780 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
781 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
782 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX  (ushort)0x8300
783 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX   (ushort)0x8400
784 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
785 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
786 #define ASC_MAX_QNO        0xF8
787 #define ASC_DATA_SEC_BEG   (ushort)0x0080
788 #define ASC_DATA_SEC_END   (ushort)0x0080
789 #define ASC_CODE_SEC_BEG   (ushort)0x0080
790 #define ASC_CODE_SEC_END   (ushort)0x0080
791 #define ASC_QADR_BEG       (0x4000)
792 #define ASC_QADR_USED      (ushort)(ASC_MAX_QNO * 64)
793 #define ASC_QADR_END       (ushort)0x7FFF
794 #define ASC_QLAST_ADR      (ushort)0x7FC0
795 #define ASC_QBLK_SIZE      0x40
796 #define ASC_BIOS_DATA_QBEG 0xF8
797 #define ASC_MIN_ACTIVE_QNO 0x01
798 #define ASC_QLINK_END      0xFF
799 #define ASC_EEPROM_WORDS   0x10
800 #define ASC_MAX_MGS_LEN    0x10
801 #define ASC_BIOS_ADDR_DEF  0xDC00
802 #define ASC_BIOS_SIZE      0x3800
803 #define ASC_BIOS_RAM_OFF   0x3800
804 #define ASC_BIOS_RAM_SIZE  0x800
805 #define ASC_BIOS_MIN_ADDR  0xC000
806 #define ASC_BIOS_MAX_ADDR  0xEC00
807 #define ASC_BIOS_BANK_SIZE 0x0400
808 #define ASC_MCODE_START_ADDR  0x0080
809 #define ASC_CFG0_HOST_INT_ON    0x0020
810 #define ASC_CFG0_BIOS_ON        0x0040
811 #define ASC_CFG0_VERA_BURST_ON  0x0080
812 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
813 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
814 #define ASC_CFG1_LRAM_8BITS_ON  0x0800
815 #define ASC_CFG_MSW_CLR_MASK    0x3080
816 #define CSW_TEST1             (ASC_CS_TYPE)0x8000
817 #define CSW_AUTO_CONFIG       (ASC_CS_TYPE)0x4000
818 #define CSW_RESERVED1         (ASC_CS_TYPE)0x2000
819 #define CSW_IRQ_WRITTEN       (ASC_CS_TYPE)0x1000
820 #define CSW_33MHZ_SELECTED    (ASC_CS_TYPE)0x0800
821 #define CSW_TEST2             (ASC_CS_TYPE)0x0400
822 #define CSW_TEST3             (ASC_CS_TYPE)0x0200
823 #define CSW_RESERVED2         (ASC_CS_TYPE)0x0100
824 #define CSW_DMA_DONE          (ASC_CS_TYPE)0x0080
825 #define CSW_FIFO_RDY          (ASC_CS_TYPE)0x0040
826 #define CSW_EEP_READ_DONE     (ASC_CS_TYPE)0x0020
827 #define CSW_HALTED            (ASC_CS_TYPE)0x0010
828 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
829 #define CSW_PARITY_ERR        (ASC_CS_TYPE)0x0004
830 #define CSW_SCSI_RESET_LATCH  (ASC_CS_TYPE)0x0002
831 #define CSW_INT_PENDING       (ASC_CS_TYPE)0x0001
832 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
833 #define CIW_INT_ACK      (ASC_CS_TYPE)0x0100
834 #define CIW_TEST1        (ASC_CS_TYPE)0x0200
835 #define CIW_TEST2        (ASC_CS_TYPE)0x0400
836 #define CIW_SEL_33MHZ    (ASC_CS_TYPE)0x0800
837 #define CIW_IRQ_ACT      (ASC_CS_TYPE)0x1000
838 #define CC_CHIP_RESET   (uchar)0x80
839 #define CC_SCSI_RESET   (uchar)0x40
840 #define CC_HALT         (uchar)0x20
841 #define CC_SINGLE_STEP  (uchar)0x10
842 #define CC_DMA_ABLE     (uchar)0x08
843 #define CC_TEST         (uchar)0x04
844 #define CC_BANK_ONE     (uchar)0x02
845 #define CC_DIAG         (uchar)0x01
846 #define ASC_1000_ID0W      0x04C1
847 #define ASC_1000_ID0W_FIX  0x00C1
848 #define ASC_1000_ID1B      0x25
849 #define ASC_EISA_REV_IOP_MASK  (0x0C83)
850 #define ASC_EISA_CFG_IOP_MASK  (0x0C86)
851 #define ASC_GET_EISA_SLOT(iop)  (PortAddr)((iop) & 0xF000)
852 #define INS_HALTINT        (ushort)0x6281
853 #define INS_HALT           (ushort)0x6280
854 #define INS_SINT           (ushort)0x6200
855 #define INS_RFLAG_WTM      (ushort)0x7380
856 #define ASC_MC_SAVE_CODE_WSIZE  0x500
857 #define ASC_MC_SAVE_DATA_WSIZE  0x40
858 
859 typedef struct asc_mc_saved {
860 	ushort data[ASC_MC_SAVE_DATA_WSIZE];
861 	ushort code[ASC_MC_SAVE_CODE_WSIZE];
862 } ASC_MC_SAVED;
863 
864 #define AscGetQDoneInProgress(port)         AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
865 #define AscPutQDoneInProgress(port, val)    AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
866 #define AscGetVarFreeQHead(port)            AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
867 #define AscGetVarDoneQTail(port)            AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
868 #define AscPutVarFreeQHead(port, val)       AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
869 #define AscPutVarDoneQTail(port, val)       AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
870 #define AscGetRiscVarFreeQHead(port)        AscReadLramByte((port), ASCV_NEXTRDY_B)
871 #define AscGetRiscVarDoneQTail(port)        AscReadLramByte((port), ASCV_DONENEXT_B)
872 #define AscPutRiscVarFreeQHead(port, val)   AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
873 #define AscPutRiscVarDoneQTail(port, val)   AscWriteLramByte((port), ASCV_DONENEXT_B, val)
874 #define AscPutMCodeSDTRDoneAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
875 #define AscGetMCodeSDTRDoneAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
876 #define AscPutMCodeInitSDTRAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
877 #define AscGetMCodeInitSDTRAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
878 #define AscGetChipSignatureByte(port)     (uchar)inp((port)+IOP_SIG_BYTE)
879 #define AscGetChipSignatureWord(port)     (ushort)inpw((port)+IOP_SIG_WORD)
880 #define AscGetChipVerNo(port)             (uchar)inp((port)+IOP_VERSION)
881 #define AscGetChipCfgLsw(port)            (ushort)inpw((port)+IOP_CONFIG_LOW)
882 #define AscGetChipCfgMsw(port)            (ushort)inpw((port)+IOP_CONFIG_HIGH)
883 #define AscSetChipCfgLsw(port, data)      outpw((port)+IOP_CONFIG_LOW, data)
884 #define AscSetChipCfgMsw(port, data)      outpw((port)+IOP_CONFIG_HIGH, data)
885 #define AscGetChipEEPCmd(port)            (uchar)inp((port)+IOP_EEP_CMD)
886 #define AscSetChipEEPCmd(port, data)      outp((port)+IOP_EEP_CMD, data)
887 #define AscGetChipEEPData(port)           (ushort)inpw((port)+IOP_EEP_DATA)
888 #define AscSetChipEEPData(port, data)     outpw((port)+IOP_EEP_DATA, data)
889 #define AscGetChipLramAddr(port)          (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
890 #define AscSetChipLramAddr(port, addr)    outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
891 #define AscGetChipLramData(port)          (ushort)inpw((port)+IOP_RAM_DATA)
892 #define AscSetChipLramData(port, data)    outpw((port)+IOP_RAM_DATA, data)
893 #define AscGetChipIFC(port)               (uchar)inp((port)+IOP_REG_IFC)
894 #define AscSetChipIFC(port, data)          outp((port)+IOP_REG_IFC, data)
895 #define AscGetChipStatus(port)            (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
896 #define AscSetChipStatus(port, cs_val)    outpw((port)+IOP_STATUS, cs_val)
897 #define AscGetChipControl(port)           (uchar)inp((port)+IOP_CTRL)
898 #define AscSetChipControl(port, cc_val)   outp((port)+IOP_CTRL, cc_val)
899 #define AscGetChipSyn(port)               (uchar)inp((port)+IOP_SYN_OFFSET)
900 #define AscSetChipSyn(port, data)         outp((port)+IOP_SYN_OFFSET, data)
901 #define AscSetPCAddr(port, data)          outpw((port)+IOP_REG_PC, data)
902 #define AscGetPCAddr(port)                (ushort)inpw((port)+IOP_REG_PC)
903 #define AscIsIntPending(port)             (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
904 #define AscGetChipScsiID(port)            ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
905 #define AscGetExtraControl(port)          (uchar)inp((port)+IOP_EXTRA_CONTROL)
906 #define AscSetExtraControl(port, data)    outp((port)+IOP_EXTRA_CONTROL, data)
907 #define AscReadChipAX(port)               (ushort)inpw((port)+IOP_REG_AX)
908 #define AscWriteChipAX(port, data)        outpw((port)+IOP_REG_AX, data)
909 #define AscReadChipIX(port)               (uchar)inp((port)+IOP_REG_IX)
910 #define AscWriteChipIX(port, data)        outp((port)+IOP_REG_IX, data)
911 #define AscReadChipIH(port)               (ushort)inpw((port)+IOP_REG_IH)
912 #define AscWriteChipIH(port, data)        outpw((port)+IOP_REG_IH, data)
913 #define AscReadChipQP(port)               (uchar)inp((port)+IOP_REG_QP)
914 #define AscWriteChipQP(port, data)        outp((port)+IOP_REG_QP, data)
915 #define AscReadChipFIFO_L(port)           (ushort)inpw((port)+IOP_REG_FIFO_L)
916 #define AscWriteChipFIFO_L(port, data)    outpw((port)+IOP_REG_FIFO_L, data)
917 #define AscReadChipFIFO_H(port)           (ushort)inpw((port)+IOP_REG_FIFO_H)
918 #define AscWriteChipFIFO_H(port, data)    outpw((port)+IOP_REG_FIFO_H, data)
919 #define AscReadChipDmaSpeed(port)         (uchar)inp((port)+IOP_DMA_SPEED)
920 #define AscWriteChipDmaSpeed(port, data)  outp((port)+IOP_DMA_SPEED, data)
921 #define AscReadChipDA0(port)              (ushort)inpw((port)+IOP_REG_DA0)
922 #define AscWriteChipDA0(port)             outpw((port)+IOP_REG_DA0, data)
923 #define AscReadChipDA1(port)              (ushort)inpw((port)+IOP_REG_DA1)
924 #define AscWriteChipDA1(port)             outpw((port)+IOP_REG_DA1, data)
925 #define AscReadChipDC0(port)              (ushort)inpw((port)+IOP_REG_DC0)
926 #define AscWriteChipDC0(port)             outpw((port)+IOP_REG_DC0, data)
927 #define AscReadChipDC1(port)              (ushort)inpw((port)+IOP_REG_DC1)
928 #define AscWriteChipDC1(port)             outpw((port)+IOP_REG_DC1, data)
929 #define AscReadChipDvcID(port)            (uchar)inp((port)+IOP_REG_ID)
930 #define AscWriteChipDvcID(port, data)     outp((port)+IOP_REG_ID, data)
931 
932 /*
933  * Portable Data Types
934  *
935  * Any instance where a 32-bit long or pointer type is assumed
936  * for precision or HW defined structures, the following define
937  * types must be used. In Linux the char, short, and int types
938  * are all consistent at 8, 16, and 32 bits respectively. Pointers
939  * and long types are 64 bits on Alpha and UltraSPARC.
940  */
941 #define ADV_PADDR __u32		/* Physical address data type. */
942 #define ADV_VADDR __u32		/* Virtual address data type. */
943 #define ADV_DCNT  __u32		/* Unsigned Data count type. */
944 #define ADV_SDCNT __s32		/* Signed Data count type. */
945 
946 /*
947  * These macros are used to convert a virtual address to a
948  * 32-bit value. This currently can be used on Linux Alpha
949  * which uses 64-bit virtual address but a 32-bit bus address.
950  * This is likely to break in the future, but doing this now
951  * will give us time to change the HW and FW to handle 64-bit
952  * addresses.
953  */
954 #define ADV_VADDR_TO_U32   virt_to_bus
955 #define ADV_U32_TO_VADDR   bus_to_virt
956 
957 #define AdvPortAddr  void __iomem *	/* Virtual memory address size */
958 
959 /*
960  * Define Adv Library required memory access macros.
961  */
962 #define ADV_MEM_READB(addr) readb(addr)
963 #define ADV_MEM_READW(addr) readw(addr)
964 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
965 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
966 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
967 
968 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
969 
970 /*
971  * Define total number of simultaneous maximum element scatter-gather
972  * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
973  * maximum number of outstanding commands per wide host adapter. Each
974  * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
975  * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
976  * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
977  * structures or 255 scatter-gather elements.
978  */
979 #define ADV_TOT_SG_BLOCK        ASC_DEF_MAX_HOST_QNG
980 
981 /*
982  * Define maximum number of scatter-gather elements per request.
983  */
984 #define ADV_MAX_SG_LIST         255
985 #define NO_OF_SG_PER_BLOCK              15
986 
987 #define ADV_EEP_DVC_CFG_BEGIN           (0x00)
988 #define ADV_EEP_DVC_CFG_END             (0x15)
989 #define ADV_EEP_DVC_CTL_BEGIN           (0x16)	/* location of OEM name */
990 #define ADV_EEP_MAX_WORD_ADDR           (0x1E)
991 
992 #define ADV_EEP_DELAY_MS                100
993 
994 #define ADV_EEPROM_BIG_ENDIAN          0x8000	/* EEPROM Bit 15 */
995 #define ADV_EEPROM_BIOS_ENABLE         0x4000	/* EEPROM Bit 14 */
996 /*
997  * For the ASC3550 Bit 13 is Termination Polarity control bit.
998  * For later ICs Bit 13 controls whether the CIS (Card Information
999  * Service Section) is loaded from EEPROM.
1000  */
1001 #define ADV_EEPROM_TERM_POL            0x2000	/* EEPROM Bit 13 */
1002 #define ADV_EEPROM_CIS_LD              0x2000	/* EEPROM Bit 13 */
1003 /*
1004  * ASC38C1600 Bit 11
1005  *
1006  * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1007  * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1008  * Function 0 will specify INT B.
1009  *
1010  * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1011  * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1012  * Function 1 will specify INT A.
1013  */
1014 #define ADV_EEPROM_INTAB               0x0800	/* EEPROM Bit 11 */
1015 
1016 typedef struct adveep_3550_config {
1017 	/* Word Offset, Description */
1018 
1019 	ushort cfg_lsw;		/* 00 power up initialization */
1020 	/*  bit 13 set - Term Polarity Control */
1021 	/*  bit 14 set - BIOS Enable */
1022 	/*  bit 15 set - Big Endian Mode */
1023 	ushort cfg_msw;		/* 01 unused      */
1024 	ushort disc_enable;	/* 02 disconnect enable */
1025 	ushort wdtr_able;	/* 03 Wide DTR able */
1026 	ushort sdtr_able;	/* 04 Synchronous DTR able */
1027 	ushort start_motor;	/* 05 send start up motor */
1028 	ushort tagqng_able;	/* 06 tag queuing able */
1029 	ushort bios_scan;	/* 07 BIOS device control */
1030 	ushort scam_tolerant;	/* 08 no scam */
1031 
1032 	uchar adapter_scsi_id;	/* 09 Host Adapter ID */
1033 	uchar bios_boot_delay;	/*    power up wait */
1034 
1035 	uchar scsi_reset_delay;	/* 10 reset delay */
1036 	uchar bios_id_lun;	/*    first boot device scsi id & lun */
1037 	/*    high nibble is lun */
1038 	/*    low nibble is scsi id */
1039 
1040 	uchar termination;	/* 11 0 - automatic */
1041 	/*    1 - low off / high off */
1042 	/*    2 - low off / high on */
1043 	/*    3 - low on  / high on */
1044 	/*    There is no low on  / high off */
1045 
1046 	uchar reserved1;	/*    reserved byte (not used) */
1047 
1048 	ushort bios_ctrl;	/* 12 BIOS control bits */
1049 	/*  bit 0  BIOS don't act as initiator. */
1050 	/*  bit 1  BIOS > 1 GB support */
1051 	/*  bit 2  BIOS > 2 Disk Support */
1052 	/*  bit 3  BIOS don't support removables */
1053 	/*  bit 4  BIOS support bootable CD */
1054 	/*  bit 5  BIOS scan enabled */
1055 	/*  bit 6  BIOS support multiple LUNs */
1056 	/*  bit 7  BIOS display of message */
1057 	/*  bit 8  SCAM disabled */
1058 	/*  bit 9  Reset SCSI bus during init. */
1059 	/*  bit 10 */
1060 	/*  bit 11 No verbose initialization. */
1061 	/*  bit 12 SCSI parity enabled */
1062 	/*  bit 13 */
1063 	/*  bit 14 */
1064 	/*  bit 15 */
1065 	ushort ultra_able;	/* 13 ULTRA speed able */
1066 	ushort reserved2;	/* 14 reserved */
1067 	uchar max_host_qng;	/* 15 maximum host queuing */
1068 	uchar max_dvc_qng;	/*    maximum per device queuing */
1069 	ushort dvc_cntl;	/* 16 control bit for driver */
1070 	ushort bug_fix;		/* 17 control bit for bug fix */
1071 	ushort serial_number_word1;	/* 18 Board serial number word 1 */
1072 	ushort serial_number_word2;	/* 19 Board serial number word 2 */
1073 	ushort serial_number_word3;	/* 20 Board serial number word 3 */
1074 	ushort check_sum;	/* 21 EEP check sum */
1075 	uchar oem_name[16];	/* 22 OEM name */
1076 	ushort dvc_err_code;	/* 30 last device driver error code */
1077 	ushort adv_err_code;	/* 31 last uc and Adv Lib error code */
1078 	ushort adv_err_addr;	/* 32 last uc error address */
1079 	ushort saved_dvc_err_code;	/* 33 saved last dev. driver error code   */
1080 	ushort saved_adv_err_code;	/* 34 saved last uc and Adv Lib error code */
1081 	ushort saved_adv_err_addr;	/* 35 saved last uc error address         */
1082 	ushort num_of_err;	/* 36 number of error */
1083 } ADVEEP_3550_CONFIG;
1084 
1085 typedef struct adveep_38C0800_config {
1086 	/* Word Offset, Description */
1087 
1088 	ushort cfg_lsw;		/* 00 power up initialization */
1089 	/*  bit 13 set - Load CIS */
1090 	/*  bit 14 set - BIOS Enable */
1091 	/*  bit 15 set - Big Endian Mode */
1092 	ushort cfg_msw;		/* 01 unused      */
1093 	ushort disc_enable;	/* 02 disconnect enable */
1094 	ushort wdtr_able;	/* 03 Wide DTR able */
1095 	ushort sdtr_speed1;	/* 04 SDTR Speed TID 0-3 */
1096 	ushort start_motor;	/* 05 send start up motor */
1097 	ushort tagqng_able;	/* 06 tag queuing able */
1098 	ushort bios_scan;	/* 07 BIOS device control */
1099 	ushort scam_tolerant;	/* 08 no scam */
1100 
1101 	uchar adapter_scsi_id;	/* 09 Host Adapter ID */
1102 	uchar bios_boot_delay;	/*    power up wait */
1103 
1104 	uchar scsi_reset_delay;	/* 10 reset delay */
1105 	uchar bios_id_lun;	/*    first boot device scsi id & lun */
1106 	/*    high nibble is lun */
1107 	/*    low nibble is scsi id */
1108 
1109 	uchar termination_se;	/* 11 0 - automatic */
1110 	/*    1 - low off / high off */
1111 	/*    2 - low off / high on */
1112 	/*    3 - low on  / high on */
1113 	/*    There is no low on  / high off */
1114 
1115 	uchar termination_lvd;	/* 11 0 - automatic */
1116 	/*    1 - low off / high off */
1117 	/*    2 - low off / high on */
1118 	/*    3 - low on  / high on */
1119 	/*    There is no low on  / high off */
1120 
1121 	ushort bios_ctrl;	/* 12 BIOS control bits */
1122 	/*  bit 0  BIOS don't act as initiator. */
1123 	/*  bit 1  BIOS > 1 GB support */
1124 	/*  bit 2  BIOS > 2 Disk Support */
1125 	/*  bit 3  BIOS don't support removables */
1126 	/*  bit 4  BIOS support bootable CD */
1127 	/*  bit 5  BIOS scan enabled */
1128 	/*  bit 6  BIOS support multiple LUNs */
1129 	/*  bit 7  BIOS display of message */
1130 	/*  bit 8  SCAM disabled */
1131 	/*  bit 9  Reset SCSI bus during init. */
1132 	/*  bit 10 */
1133 	/*  bit 11 No verbose initialization. */
1134 	/*  bit 12 SCSI parity enabled */
1135 	/*  bit 13 */
1136 	/*  bit 14 */
1137 	/*  bit 15 */
1138 	ushort sdtr_speed2;	/* 13 SDTR speed TID 4-7 */
1139 	ushort sdtr_speed3;	/* 14 SDTR speed TID 8-11 */
1140 	uchar max_host_qng;	/* 15 maximum host queueing */
1141 	uchar max_dvc_qng;	/*    maximum per device queuing */
1142 	ushort dvc_cntl;	/* 16 control bit for driver */
1143 	ushort sdtr_speed4;	/* 17 SDTR speed 4 TID 12-15 */
1144 	ushort serial_number_word1;	/* 18 Board serial number word 1 */
1145 	ushort serial_number_word2;	/* 19 Board serial number word 2 */
1146 	ushort serial_number_word3;	/* 20 Board serial number word 3 */
1147 	ushort check_sum;	/* 21 EEP check sum */
1148 	uchar oem_name[16];	/* 22 OEM name */
1149 	ushort dvc_err_code;	/* 30 last device driver error code */
1150 	ushort adv_err_code;	/* 31 last uc and Adv Lib error code */
1151 	ushort adv_err_addr;	/* 32 last uc error address */
1152 	ushort saved_dvc_err_code;	/* 33 saved last dev. driver error code   */
1153 	ushort saved_adv_err_code;	/* 34 saved last uc and Adv Lib error code */
1154 	ushort saved_adv_err_addr;	/* 35 saved last uc error address         */
1155 	ushort reserved36;	/* 36 reserved */
1156 	ushort reserved37;	/* 37 reserved */
1157 	ushort reserved38;	/* 38 reserved */
1158 	ushort reserved39;	/* 39 reserved */
1159 	ushort reserved40;	/* 40 reserved */
1160 	ushort reserved41;	/* 41 reserved */
1161 	ushort reserved42;	/* 42 reserved */
1162 	ushort reserved43;	/* 43 reserved */
1163 	ushort reserved44;	/* 44 reserved */
1164 	ushort reserved45;	/* 45 reserved */
1165 	ushort reserved46;	/* 46 reserved */
1166 	ushort reserved47;	/* 47 reserved */
1167 	ushort reserved48;	/* 48 reserved */
1168 	ushort reserved49;	/* 49 reserved */
1169 	ushort reserved50;	/* 50 reserved */
1170 	ushort reserved51;	/* 51 reserved */
1171 	ushort reserved52;	/* 52 reserved */
1172 	ushort reserved53;	/* 53 reserved */
1173 	ushort reserved54;	/* 54 reserved */
1174 	ushort reserved55;	/* 55 reserved */
1175 	ushort cisptr_lsw;	/* 56 CIS PTR LSW */
1176 	ushort cisprt_msw;	/* 57 CIS PTR MSW */
1177 	ushort subsysvid;	/* 58 SubSystem Vendor ID */
1178 	ushort subsysid;	/* 59 SubSystem ID */
1179 	ushort reserved60;	/* 60 reserved */
1180 	ushort reserved61;	/* 61 reserved */
1181 	ushort reserved62;	/* 62 reserved */
1182 	ushort reserved63;	/* 63 reserved */
1183 } ADVEEP_38C0800_CONFIG;
1184 
1185 typedef struct adveep_38C1600_config {
1186 	/* Word Offset, Description */
1187 
1188 	ushort cfg_lsw;		/* 00 power up initialization */
1189 	/*  bit 11 set - Func. 0 INTB, Func. 1 INTA */
1190 	/*       clear - Func. 0 INTA, Func. 1 INTB */
1191 	/*  bit 13 set - Load CIS */
1192 	/*  bit 14 set - BIOS Enable */
1193 	/*  bit 15 set - Big Endian Mode */
1194 	ushort cfg_msw;		/* 01 unused */
1195 	ushort disc_enable;	/* 02 disconnect enable */
1196 	ushort wdtr_able;	/* 03 Wide DTR able */
1197 	ushort sdtr_speed1;	/* 04 SDTR Speed TID 0-3 */
1198 	ushort start_motor;	/* 05 send start up motor */
1199 	ushort tagqng_able;	/* 06 tag queuing able */
1200 	ushort bios_scan;	/* 07 BIOS device control */
1201 	ushort scam_tolerant;	/* 08 no scam */
1202 
1203 	uchar adapter_scsi_id;	/* 09 Host Adapter ID */
1204 	uchar bios_boot_delay;	/*    power up wait */
1205 
1206 	uchar scsi_reset_delay;	/* 10 reset delay */
1207 	uchar bios_id_lun;	/*    first boot device scsi id & lun */
1208 	/*    high nibble is lun */
1209 	/*    low nibble is scsi id */
1210 
1211 	uchar termination_se;	/* 11 0 - automatic */
1212 	/*    1 - low off / high off */
1213 	/*    2 - low off / high on */
1214 	/*    3 - low on  / high on */
1215 	/*    There is no low on  / high off */
1216 
1217 	uchar termination_lvd;	/* 11 0 - automatic */
1218 	/*    1 - low off / high off */
1219 	/*    2 - low off / high on */
1220 	/*    3 - low on  / high on */
1221 	/*    There is no low on  / high off */
1222 
1223 	ushort bios_ctrl;	/* 12 BIOS control bits */
1224 	/*  bit 0  BIOS don't act as initiator. */
1225 	/*  bit 1  BIOS > 1 GB support */
1226 	/*  bit 2  BIOS > 2 Disk Support */
1227 	/*  bit 3  BIOS don't support removables */
1228 	/*  bit 4  BIOS support bootable CD */
1229 	/*  bit 5  BIOS scan enabled */
1230 	/*  bit 6  BIOS support multiple LUNs */
1231 	/*  bit 7  BIOS display of message */
1232 	/*  bit 8  SCAM disabled */
1233 	/*  bit 9  Reset SCSI bus during init. */
1234 	/*  bit 10 Basic Integrity Checking disabled */
1235 	/*  bit 11 No verbose initialization. */
1236 	/*  bit 12 SCSI parity enabled */
1237 	/*  bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1238 	/*  bit 14 */
1239 	/*  bit 15 */
1240 	ushort sdtr_speed2;	/* 13 SDTR speed TID 4-7 */
1241 	ushort sdtr_speed3;	/* 14 SDTR speed TID 8-11 */
1242 	uchar max_host_qng;	/* 15 maximum host queueing */
1243 	uchar max_dvc_qng;	/*    maximum per device queuing */
1244 	ushort dvc_cntl;	/* 16 control bit for driver */
1245 	ushort sdtr_speed4;	/* 17 SDTR speed 4 TID 12-15 */
1246 	ushort serial_number_word1;	/* 18 Board serial number word 1 */
1247 	ushort serial_number_word2;	/* 19 Board serial number word 2 */
1248 	ushort serial_number_word3;	/* 20 Board serial number word 3 */
1249 	ushort check_sum;	/* 21 EEP check sum */
1250 	uchar oem_name[16];	/* 22 OEM name */
1251 	ushort dvc_err_code;	/* 30 last device driver error code */
1252 	ushort adv_err_code;	/* 31 last uc and Adv Lib error code */
1253 	ushort adv_err_addr;	/* 32 last uc error address */
1254 	ushort saved_dvc_err_code;	/* 33 saved last dev. driver error code   */
1255 	ushort saved_adv_err_code;	/* 34 saved last uc and Adv Lib error code */
1256 	ushort saved_adv_err_addr;	/* 35 saved last uc error address         */
1257 	ushort reserved36;	/* 36 reserved */
1258 	ushort reserved37;	/* 37 reserved */
1259 	ushort reserved38;	/* 38 reserved */
1260 	ushort reserved39;	/* 39 reserved */
1261 	ushort reserved40;	/* 40 reserved */
1262 	ushort reserved41;	/* 41 reserved */
1263 	ushort reserved42;	/* 42 reserved */
1264 	ushort reserved43;	/* 43 reserved */
1265 	ushort reserved44;	/* 44 reserved */
1266 	ushort reserved45;	/* 45 reserved */
1267 	ushort reserved46;	/* 46 reserved */
1268 	ushort reserved47;	/* 47 reserved */
1269 	ushort reserved48;	/* 48 reserved */
1270 	ushort reserved49;	/* 49 reserved */
1271 	ushort reserved50;	/* 50 reserved */
1272 	ushort reserved51;	/* 51 reserved */
1273 	ushort reserved52;	/* 52 reserved */
1274 	ushort reserved53;	/* 53 reserved */
1275 	ushort reserved54;	/* 54 reserved */
1276 	ushort reserved55;	/* 55 reserved */
1277 	ushort cisptr_lsw;	/* 56 CIS PTR LSW */
1278 	ushort cisprt_msw;	/* 57 CIS PTR MSW */
1279 	ushort subsysvid;	/* 58 SubSystem Vendor ID */
1280 	ushort subsysid;	/* 59 SubSystem ID */
1281 	ushort reserved60;	/* 60 reserved */
1282 	ushort reserved61;	/* 61 reserved */
1283 	ushort reserved62;	/* 62 reserved */
1284 	ushort reserved63;	/* 63 reserved */
1285 } ADVEEP_38C1600_CONFIG;
1286 
1287 /*
1288  * EEPROM Commands
1289  */
1290 #define ASC_EEP_CMD_DONE             0x0200
1291 
1292 /* bios_ctrl */
1293 #define BIOS_CTRL_BIOS               0x0001
1294 #define BIOS_CTRL_EXTENDED_XLAT      0x0002
1295 #define BIOS_CTRL_GT_2_DISK          0x0004
1296 #define BIOS_CTRL_BIOS_REMOVABLE     0x0008
1297 #define BIOS_CTRL_BOOTABLE_CD        0x0010
1298 #define BIOS_CTRL_MULTIPLE_LUN       0x0040
1299 #define BIOS_CTRL_DISPLAY_MSG        0x0080
1300 #define BIOS_CTRL_NO_SCAM            0x0100
1301 #define BIOS_CTRL_RESET_SCSI_BUS     0x0200
1302 #define BIOS_CTRL_INIT_VERBOSE       0x0800
1303 #define BIOS_CTRL_SCSI_PARITY        0x1000
1304 #define BIOS_CTRL_AIPP_DIS           0x2000
1305 
1306 #define ADV_3550_MEMSIZE   0x2000	/* 8 KB Internal Memory */
1307 
1308 #define ADV_38C0800_MEMSIZE  0x4000	/* 16 KB Internal Memory */
1309 
1310 /*
1311  * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1312  * a special 16K Adv Library and Microcode version. After the issue is
1313  * resolved, should restore 32K support.
1314  *
1315  * #define ADV_38C1600_MEMSIZE  0x8000L   * 32 KB Internal Memory *
1316  */
1317 #define ADV_38C1600_MEMSIZE  0x4000	/* 16 KB Internal Memory */
1318 
1319 /*
1320  * Byte I/O register address from base of 'iop_base'.
1321  */
1322 #define IOPB_INTR_STATUS_REG    0x00
1323 #define IOPB_CHIP_ID_1          0x01
1324 #define IOPB_INTR_ENABLES       0x02
1325 #define IOPB_CHIP_TYPE_REV      0x03
1326 #define IOPB_RES_ADDR_4         0x04
1327 #define IOPB_RES_ADDR_5         0x05
1328 #define IOPB_RAM_DATA           0x06
1329 #define IOPB_RES_ADDR_7         0x07
1330 #define IOPB_FLAG_REG           0x08
1331 #define IOPB_RES_ADDR_9         0x09
1332 #define IOPB_RISC_CSR           0x0A
1333 #define IOPB_RES_ADDR_B         0x0B
1334 #define IOPB_RES_ADDR_C         0x0C
1335 #define IOPB_RES_ADDR_D         0x0D
1336 #define IOPB_SOFT_OVER_WR       0x0E
1337 #define IOPB_RES_ADDR_F         0x0F
1338 #define IOPB_MEM_CFG            0x10
1339 #define IOPB_RES_ADDR_11        0x11
1340 #define IOPB_GPIO_DATA          0x12
1341 #define IOPB_RES_ADDR_13        0x13
1342 #define IOPB_FLASH_PAGE         0x14
1343 #define IOPB_RES_ADDR_15        0x15
1344 #define IOPB_GPIO_CNTL          0x16
1345 #define IOPB_RES_ADDR_17        0x17
1346 #define IOPB_FLASH_DATA         0x18
1347 #define IOPB_RES_ADDR_19        0x19
1348 #define IOPB_RES_ADDR_1A        0x1A
1349 #define IOPB_RES_ADDR_1B        0x1B
1350 #define IOPB_RES_ADDR_1C        0x1C
1351 #define IOPB_RES_ADDR_1D        0x1D
1352 #define IOPB_RES_ADDR_1E        0x1E
1353 #define IOPB_RES_ADDR_1F        0x1F
1354 #define IOPB_DMA_CFG0           0x20
1355 #define IOPB_DMA_CFG1           0x21
1356 #define IOPB_TICKLE             0x22
1357 #define IOPB_DMA_REG_WR         0x23
1358 #define IOPB_SDMA_STATUS        0x24
1359 #define IOPB_SCSI_BYTE_CNT      0x25
1360 #define IOPB_HOST_BYTE_CNT      0x26
1361 #define IOPB_BYTE_LEFT_TO_XFER  0x27
1362 #define IOPB_BYTE_TO_XFER_0     0x28
1363 #define IOPB_BYTE_TO_XFER_1     0x29
1364 #define IOPB_BYTE_TO_XFER_2     0x2A
1365 #define IOPB_BYTE_TO_XFER_3     0x2B
1366 #define IOPB_ACC_GRP            0x2C
1367 #define IOPB_RES_ADDR_2D        0x2D
1368 #define IOPB_DEV_ID             0x2E
1369 #define IOPB_RES_ADDR_2F        0x2F
1370 #define IOPB_SCSI_DATA          0x30
1371 #define IOPB_RES_ADDR_31        0x31
1372 #define IOPB_RES_ADDR_32        0x32
1373 #define IOPB_SCSI_DATA_HSHK     0x33
1374 #define IOPB_SCSI_CTRL          0x34
1375 #define IOPB_RES_ADDR_35        0x35
1376 #define IOPB_RES_ADDR_36        0x36
1377 #define IOPB_RES_ADDR_37        0x37
1378 #define IOPB_RAM_BIST           0x38
1379 #define IOPB_PLL_TEST           0x39
1380 #define IOPB_PCI_INT_CFG        0x3A
1381 #define IOPB_RES_ADDR_3B        0x3B
1382 #define IOPB_RFIFO_CNT          0x3C
1383 #define IOPB_RES_ADDR_3D        0x3D
1384 #define IOPB_RES_ADDR_3E        0x3E
1385 #define IOPB_RES_ADDR_3F        0x3F
1386 
1387 /*
1388  * Word I/O register address from base of 'iop_base'.
1389  */
1390 #define IOPW_CHIP_ID_0          0x00	/* CID0  */
1391 #define IOPW_CTRL_REG           0x02	/* CC    */
1392 #define IOPW_RAM_ADDR           0x04	/* LA    */
1393 #define IOPW_RAM_DATA           0x06	/* LD    */
1394 #define IOPW_RES_ADDR_08        0x08
1395 #define IOPW_RISC_CSR           0x0A	/* CSR   */
1396 #define IOPW_SCSI_CFG0          0x0C	/* CFG0  */
1397 #define IOPW_SCSI_CFG1          0x0E	/* CFG1  */
1398 #define IOPW_RES_ADDR_10        0x10
1399 #define IOPW_SEL_MASK           0x12	/* SM    */
1400 #define IOPW_RES_ADDR_14        0x14
1401 #define IOPW_FLASH_ADDR         0x16	/* FA    */
1402 #define IOPW_RES_ADDR_18        0x18
1403 #define IOPW_EE_CMD             0x1A	/* EC    */
1404 #define IOPW_EE_DATA            0x1C	/* ED    */
1405 #define IOPW_SFIFO_CNT          0x1E	/* SFC   */
1406 #define IOPW_RES_ADDR_20        0x20
1407 #define IOPW_Q_BASE             0x22	/* QB    */
1408 #define IOPW_QP                 0x24	/* QP    */
1409 #define IOPW_IX                 0x26	/* IX    */
1410 #define IOPW_SP                 0x28	/* SP    */
1411 #define IOPW_PC                 0x2A	/* PC    */
1412 #define IOPW_RES_ADDR_2C        0x2C
1413 #define IOPW_RES_ADDR_2E        0x2E
1414 #define IOPW_SCSI_DATA          0x30	/* SD    */
1415 #define IOPW_SCSI_DATA_HSHK     0x32	/* SDH   */
1416 #define IOPW_SCSI_CTRL          0x34	/* SC    */
1417 #define IOPW_HSHK_CFG           0x36	/* HCFG  */
1418 #define IOPW_SXFR_STATUS        0x36	/* SXS   */
1419 #define IOPW_SXFR_CNTL          0x38	/* SXL   */
1420 #define IOPW_SXFR_CNTH          0x3A	/* SXH   */
1421 #define IOPW_RES_ADDR_3C        0x3C
1422 #define IOPW_RFIFO_DATA         0x3E	/* RFD   */
1423 
1424 /*
1425  * Doubleword I/O register address from base of 'iop_base'.
1426  */
1427 #define IOPDW_RES_ADDR_0         0x00
1428 #define IOPDW_RAM_DATA           0x04
1429 #define IOPDW_RES_ADDR_8         0x08
1430 #define IOPDW_RES_ADDR_C         0x0C
1431 #define IOPDW_RES_ADDR_10        0x10
1432 #define IOPDW_COMMA              0x14
1433 #define IOPDW_COMMB              0x18
1434 #define IOPDW_RES_ADDR_1C        0x1C
1435 #define IOPDW_SDMA_ADDR0         0x20
1436 #define IOPDW_SDMA_ADDR1         0x24
1437 #define IOPDW_SDMA_COUNT         0x28
1438 #define IOPDW_SDMA_ERROR         0x2C
1439 #define IOPDW_RDMA_ADDR0         0x30
1440 #define IOPDW_RDMA_ADDR1         0x34
1441 #define IOPDW_RDMA_COUNT         0x38
1442 #define IOPDW_RDMA_ERROR         0x3C
1443 
1444 #define ADV_CHIP_ID_BYTE         0x25
1445 #define ADV_CHIP_ID_WORD         0x04C1
1446 
1447 #define ADV_INTR_ENABLE_HOST_INTR                   0x01
1448 #define ADV_INTR_ENABLE_SEL_INTR                    0x02
1449 #define ADV_INTR_ENABLE_DPR_INTR                    0x04
1450 #define ADV_INTR_ENABLE_RTA_INTR                    0x08
1451 #define ADV_INTR_ENABLE_RMA_INTR                    0x10
1452 #define ADV_INTR_ENABLE_RST_INTR                    0x20
1453 #define ADV_INTR_ENABLE_DPE_INTR                    0x40
1454 #define ADV_INTR_ENABLE_GLOBAL_INTR                 0x80
1455 
1456 #define ADV_INTR_STATUS_INTRA            0x01
1457 #define ADV_INTR_STATUS_INTRB            0x02
1458 #define ADV_INTR_STATUS_INTRC            0x04
1459 
1460 #define ADV_RISC_CSR_STOP           (0x0000)
1461 #define ADV_RISC_TEST_COND          (0x2000)
1462 #define ADV_RISC_CSR_RUN            (0x4000)
1463 #define ADV_RISC_CSR_SINGLE_STEP    (0x8000)
1464 
1465 #define ADV_CTRL_REG_HOST_INTR      0x0100
1466 #define ADV_CTRL_REG_SEL_INTR       0x0200
1467 #define ADV_CTRL_REG_DPR_INTR       0x0400
1468 #define ADV_CTRL_REG_RTA_INTR       0x0800
1469 #define ADV_CTRL_REG_RMA_INTR       0x1000
1470 #define ADV_CTRL_REG_RES_BIT14      0x2000
1471 #define ADV_CTRL_REG_DPE_INTR       0x4000
1472 #define ADV_CTRL_REG_POWER_DONE     0x8000
1473 #define ADV_CTRL_REG_ANY_INTR       0xFF00
1474 
1475 #define ADV_CTRL_REG_CMD_RESET             0x00C6
1476 #define ADV_CTRL_REG_CMD_WR_IO_REG         0x00C5
1477 #define ADV_CTRL_REG_CMD_RD_IO_REG         0x00C4
1478 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE  0x00C3
1479 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE  0x00C2
1480 
1481 #define ADV_TICKLE_NOP                      0x00
1482 #define ADV_TICKLE_A                        0x01
1483 #define ADV_TICKLE_B                        0x02
1484 #define ADV_TICKLE_C                        0x03
1485 
1486 #define AdvIsIntPending(port) \
1487     (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1488 
1489 /*
1490  * SCSI_CFG0 Register bit definitions
1491  */
1492 #define TIMER_MODEAB    0xC000	/* Watchdog, Second, and Select. Timer Ctrl. */
1493 #define PARITY_EN       0x2000	/* Enable SCSI Parity Error detection */
1494 #define EVEN_PARITY     0x1000	/* Select Even Parity */
1495 #define WD_LONG         0x0800	/* Watchdog Interval, 1: 57 min, 0: 13 sec */
1496 #define QUEUE_128       0x0400	/* Queue Size, 1: 128 byte, 0: 64 byte */
1497 #define PRIM_MODE       0x0100	/* Primitive SCSI mode */
1498 #define SCAM_EN         0x0080	/* Enable SCAM selection */
1499 #define SEL_TMO_LONG    0x0040	/* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1500 #define CFRM_ID         0x0020	/* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1501 #define OUR_ID_EN       0x0010	/* Enable OUR_ID bits */
1502 #define OUR_ID          0x000F	/* SCSI ID */
1503 
1504 /*
1505  * SCSI_CFG1 Register bit definitions
1506  */
1507 #define BIG_ENDIAN      0x8000	/* Enable Big Endian Mode MIO:15, EEP:15 */
1508 #define TERM_POL        0x2000	/* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1509 #define SLEW_RATE       0x1000	/* SCSI output buffer slew rate */
1510 #define FILTER_SEL      0x0C00	/* Filter Period Selection */
1511 #define  FLTR_DISABLE    0x0000	/* Input Filtering Disabled */
1512 #define  FLTR_11_TO_20NS 0x0800	/* Input Filtering 11ns to 20ns */
1513 #define  FLTR_21_TO_39NS 0x0C00	/* Input Filtering 21ns to 39ns */
1514 #define ACTIVE_DBL      0x0200	/* Disable Active Negation */
1515 #define DIFF_MODE       0x0100	/* SCSI differential Mode (Read-Only) */
1516 #define DIFF_SENSE      0x0080	/* 1: No SE cables, 0: SE cable (Read-Only) */
1517 #define TERM_CTL_SEL    0x0040	/* Enable TERM_CTL_H and TERM_CTL_L */
1518 #define TERM_CTL        0x0030	/* External SCSI Termination Bits */
1519 #define  TERM_CTL_H      0x0020	/* Enable External SCSI Upper Termination */
1520 #define  TERM_CTL_L      0x0010	/* Enable External SCSI Lower Termination */
1521 #define CABLE_DETECT    0x000F	/* External SCSI Cable Connection Status */
1522 
1523 /*
1524  * Addendum for ASC-38C0800 Chip
1525  *
1526  * The ASC-38C1600 Chip uses the same definitions except that the
1527  * bus mode override bits [12:10] have been moved to byte register
1528  * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1529  * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1530  * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1531  * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1532  * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1533  */
1534 #define DIS_TERM_DRV    0x4000	/* 1: Read c_det[3:0], 0: cannot read */
1535 #define HVD_LVD_SE      0x1C00	/* Device Detect Bits */
1536 #define  HVD             0x1000	/* HVD Device Detect */
1537 #define  LVD             0x0800	/* LVD Device Detect */
1538 #define  SE              0x0400	/* SE Device Detect */
1539 #define TERM_LVD        0x00C0	/* LVD Termination Bits */
1540 #define  TERM_LVD_HI     0x0080	/* Enable LVD Upper Termination */
1541 #define  TERM_LVD_LO     0x0040	/* Enable LVD Lower Termination */
1542 #define TERM_SE         0x0030	/* SE Termination Bits */
1543 #define  TERM_SE_HI      0x0020	/* Enable SE Upper Termination */
1544 #define  TERM_SE_LO      0x0010	/* Enable SE Lower Termination */
1545 #define C_DET_LVD       0x000C	/* LVD Cable Detect Bits */
1546 #define  C_DET3          0x0008	/* Cable Detect for LVD External Wide */
1547 #define  C_DET2          0x0004	/* Cable Detect for LVD Internal Wide */
1548 #define C_DET_SE        0x0003	/* SE Cable Detect Bits */
1549 #define  C_DET1          0x0002	/* Cable Detect for SE Internal Wide */
1550 #define  C_DET0          0x0001	/* Cable Detect for SE Internal Narrow */
1551 
1552 #define CABLE_ILLEGAL_A 0x7
1553     /* x 0 0 0  | on  on | Illegal (all 3 connectors are used) */
1554 
1555 #define CABLE_ILLEGAL_B 0xB
1556     /* 0 x 0 0  | on  on | Illegal (all 3 connectors are used) */
1557 
1558 /*
1559  * MEM_CFG Register bit definitions
1560  */
1561 #define BIOS_EN         0x40	/* BIOS Enable MIO:14,EEP:14 */
1562 #define FAST_EE_CLK     0x20	/* Diagnostic Bit */
1563 #define RAM_SZ          0x1C	/* Specify size of RAM to RISC */
1564 #define  RAM_SZ_2KB      0x00	/* 2 KB */
1565 #define  RAM_SZ_4KB      0x04	/* 4 KB */
1566 #define  RAM_SZ_8KB      0x08	/* 8 KB */
1567 #define  RAM_SZ_16KB     0x0C	/* 16 KB */
1568 #define  RAM_SZ_32KB     0x10	/* 32 KB */
1569 #define  RAM_SZ_64KB     0x14	/* 64 KB */
1570 
1571 /*
1572  * DMA_CFG0 Register bit definitions
1573  *
1574  * This register is only accessible to the host.
1575  */
1576 #define BC_THRESH_ENB   0x80	/* PCI DMA Start Conditions */
1577 #define FIFO_THRESH     0x70	/* PCI DMA FIFO Threshold */
1578 #define  FIFO_THRESH_16B  0x00	/* 16 bytes */
1579 #define  FIFO_THRESH_32B  0x20	/* 32 bytes */
1580 #define  FIFO_THRESH_48B  0x30	/* 48 bytes */
1581 #define  FIFO_THRESH_64B  0x40	/* 64 bytes */
1582 #define  FIFO_THRESH_80B  0x50	/* 80 bytes (default) */
1583 #define  FIFO_THRESH_96B  0x60	/* 96 bytes */
1584 #define  FIFO_THRESH_112B 0x70	/* 112 bytes */
1585 #define START_CTL       0x0C	/* DMA start conditions */
1586 #define  START_CTL_TH    0x00	/* Wait threshold level (default) */
1587 #define  START_CTL_ID    0x04	/* Wait SDMA/SBUS idle */
1588 #define  START_CTL_THID  0x08	/* Wait threshold and SDMA/SBUS idle */
1589 #define  START_CTL_EMFU  0x0C	/* Wait SDMA FIFO empty/full */
1590 #define READ_CMD        0x03	/* Memory Read Method */
1591 #define  READ_CMD_MR     0x00	/* Memory Read */
1592 #define  READ_CMD_MRL    0x02	/* Memory Read Long */
1593 #define  READ_CMD_MRM    0x03	/* Memory Read Multiple (default) */
1594 
1595 /*
1596  * ASC-38C0800 RAM BIST Register bit definitions
1597  */
1598 #define RAM_TEST_MODE         0x80
1599 #define PRE_TEST_MODE         0x40
1600 #define NORMAL_MODE           0x00
1601 #define RAM_TEST_DONE         0x10
1602 #define RAM_TEST_STATUS       0x0F
1603 #define  RAM_TEST_HOST_ERROR   0x08
1604 #define  RAM_TEST_INTRAM_ERROR 0x04
1605 #define  RAM_TEST_RISC_ERROR   0x02
1606 #define  RAM_TEST_SCSI_ERROR   0x01
1607 #define  RAM_TEST_SUCCESS      0x00
1608 #define PRE_TEST_VALUE        0x05
1609 #define NORMAL_VALUE          0x00
1610 
1611 /*
1612  * ASC38C1600 Definitions
1613  *
1614  * IOPB_PCI_INT_CFG Bit Field Definitions
1615  */
1616 
1617 #define INTAB_LD        0x80	/* Value loaded from EEPROM Bit 11. */
1618 
1619 /*
1620  * Bit 1 can be set to change the interrupt for the Function to operate in
1621  * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1622  * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1623  * mode, otherwise the operating mode is undefined.
1624  */
1625 #define TOTEMPOLE       0x02
1626 
1627 /*
1628  * Bit 0 can be used to change the Int Pin for the Function. The value is
1629  * 0 by default for both Functions with Function 0 using INT A and Function
1630  * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1631  * INT A is used.
1632  *
1633  * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1634  * value specified in the PCI Configuration Space.
1635  */
1636 #define INTAB           0x01
1637 
1638 /*
1639  * Adv Library Status Definitions
1640  */
1641 #define ADV_TRUE        1
1642 #define ADV_FALSE       0
1643 #define ADV_SUCCESS     1
1644 #define ADV_BUSY        0
1645 #define ADV_ERROR       (-1)
1646 
1647 /*
1648  * ADV_DVC_VAR 'warn_code' values
1649  */
1650 #define ASC_WARN_BUSRESET_ERROR         0x0001	/* SCSI Bus Reset error */
1651 #define ASC_WARN_EEPROM_CHKSUM          0x0002	/* EEP check sum error */
1652 #define ASC_WARN_EEPROM_TERMINATION     0x0004	/* EEP termination bad field */
1653 #define ASC_WARN_ERROR                  0xFFFF	/* ADV_ERROR return */
1654 
1655 #define ADV_MAX_TID                     15	/* max. target identifier */
1656 #define ADV_MAX_LUN                     7	/* max. logical unit number */
1657 
1658 /*
1659  * Fixed locations of microcode operating variables.
1660  */
1661 #define ASC_MC_CODE_BEGIN_ADDR          0x0028	/* microcode start address */
1662 #define ASC_MC_CODE_END_ADDR            0x002A	/* microcode end address */
1663 #define ASC_MC_CODE_CHK_SUM             0x002C	/* microcode code checksum */
1664 #define ASC_MC_VERSION_DATE             0x0038	/* microcode version */
1665 #define ASC_MC_VERSION_NUM              0x003A	/* microcode number */
1666 #define ASC_MC_BIOSMEM                  0x0040	/* BIOS RISC Memory Start */
1667 #define ASC_MC_BIOSLEN                  0x0050	/* BIOS RISC Memory Length */
1668 #define ASC_MC_BIOS_SIGNATURE           0x0058	/* BIOS Signature 0x55AA */
1669 #define ASC_MC_BIOS_VERSION             0x005A	/* BIOS Version (2 bytes) */
1670 #define ASC_MC_SDTR_SPEED1              0x0090	/* SDTR Speed for TID 0-3 */
1671 #define ASC_MC_SDTR_SPEED2              0x0092	/* SDTR Speed for TID 4-7 */
1672 #define ASC_MC_SDTR_SPEED3              0x0094	/* SDTR Speed for TID 8-11 */
1673 #define ASC_MC_SDTR_SPEED4              0x0096	/* SDTR Speed for TID 12-15 */
1674 #define ASC_MC_CHIP_TYPE                0x009A
1675 #define ASC_MC_INTRB_CODE               0x009B
1676 #define ASC_MC_WDTR_ABLE                0x009C
1677 #define ASC_MC_SDTR_ABLE                0x009E
1678 #define ASC_MC_TAGQNG_ABLE              0x00A0
1679 #define ASC_MC_DISC_ENABLE              0x00A2
1680 #define ASC_MC_IDLE_CMD_STATUS          0x00A4
1681 #define ASC_MC_IDLE_CMD                 0x00A6
1682 #define ASC_MC_IDLE_CMD_PARAMETER       0x00A8
1683 #define ASC_MC_DEFAULT_SCSI_CFG0        0x00AC
1684 #define ASC_MC_DEFAULT_SCSI_CFG1        0x00AE
1685 #define ASC_MC_DEFAULT_MEM_CFG          0x00B0
1686 #define ASC_MC_DEFAULT_SEL_MASK         0x00B2
1687 #define ASC_MC_SDTR_DONE                0x00B6
1688 #define ASC_MC_NUMBER_OF_QUEUED_CMD     0x00C0
1689 #define ASC_MC_NUMBER_OF_MAX_CMD        0x00D0
1690 #define ASC_MC_DEVICE_HSHK_CFG_TABLE    0x0100
1691 #define ASC_MC_CONTROL_FLAG             0x0122	/* Microcode control flag. */
1692 #define ASC_MC_WDTR_DONE                0x0124
1693 #define ASC_MC_CAM_MODE_MASK            0x015E	/* CAM mode TID bitmask. */
1694 #define ASC_MC_ICQ                      0x0160
1695 #define ASC_MC_IRQ                      0x0164
1696 #define ASC_MC_PPR_ABLE                 0x017A
1697 
1698 /*
1699  * BIOS LRAM variable absolute offsets.
1700  */
1701 #define BIOS_CODESEG    0x54
1702 #define BIOS_CODELEN    0x56
1703 #define BIOS_SIGNATURE  0x58
1704 #define BIOS_VERSION    0x5A
1705 
1706 /*
1707  * Microcode Control Flags
1708  *
1709  * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1710  * and handled by the microcode.
1711  */
1712 #define CONTROL_FLAG_IGNORE_PERR        0x0001	/* Ignore DMA Parity Errors */
1713 #define CONTROL_FLAG_ENABLE_AIPP        0x0002	/* Enabled AIPP checking. */
1714 
1715 /*
1716  * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1717  */
1718 #define HSHK_CFG_WIDE_XFR       0x8000
1719 #define HSHK_CFG_RATE           0x0F00
1720 #define HSHK_CFG_OFFSET         0x001F
1721 
1722 #define ASC_DEF_MAX_HOST_QNG    0xFD	/* Max. number of host commands (253) */
1723 #define ASC_DEF_MIN_HOST_QNG    0x10	/* Min. number of host commands (16) */
1724 #define ASC_DEF_MAX_DVC_QNG     0x3F	/* Max. number commands per device (63) */
1725 #define ASC_DEF_MIN_DVC_QNG     0x04	/* Min. number commands per device (4) */
1726 
1727 #define ASC_QC_DATA_CHECK  0x01	/* Require ASC_QC_DATA_OUT set or clear. */
1728 #define ASC_QC_DATA_OUT    0x02	/* Data out DMA transfer. */
1729 #define ASC_QC_START_MOTOR 0x04	/* Send auto-start motor before request. */
1730 #define ASC_QC_NO_OVERRUN  0x08	/* Don't report overrun. */
1731 #define ASC_QC_FREEZE_TIDQ 0x10	/* Freeze TID queue after request. XXX TBD */
1732 
1733 #define ASC_QSC_NO_DISC     0x01	/* Don't allow disconnect for request. */
1734 #define ASC_QSC_NO_TAGMSG   0x02	/* Don't allow tag queuing for request. */
1735 #define ASC_QSC_NO_SYNC     0x04	/* Don't use Synch. transfer on request. */
1736 #define ASC_QSC_NO_WIDE     0x08	/* Don't use Wide transfer on request. */
1737 #define ASC_QSC_REDO_DTR    0x10	/* Renegotiate WDTR/SDTR before request. */
1738 /*
1739  * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1740  * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1741  */
1742 #define ASC_QSC_HEAD_TAG    0x40	/* Use Head Tag Message (0x21). */
1743 #define ASC_QSC_ORDERED_TAG 0x80	/* Use Ordered Tag Message (0x22). */
1744 
1745 /*
1746  * All fields here are accessed by the board microcode and need to be
1747  * little-endian.
1748  */
1749 typedef struct adv_carr_t {
1750 	ADV_VADDR carr_va;	/* Carrier Virtual Address */
1751 	ADV_PADDR carr_pa;	/* Carrier Physical Address */
1752 	ADV_VADDR areq_vpa;	/* ASC_SCSI_REQ_Q Virtual or Physical Address */
1753 	/*
1754 	 * next_vpa [31:4]            Carrier Virtual or Physical Next Pointer
1755 	 *
1756 	 * next_vpa [3:1]             Reserved Bits
1757 	 * next_vpa [0]               Done Flag set in Response Queue.
1758 	 */
1759 	ADV_VADDR next_vpa;
1760 } ADV_CARR_T;
1761 
1762 /*
1763  * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1764  */
1765 #define ASC_NEXT_VPA_MASK       0xFFFFFFF0
1766 
1767 #define ASC_RQ_DONE             0x00000001
1768 #define ASC_RQ_GOOD             0x00000002
1769 #define ASC_CQ_STOPPER          0x00000000
1770 
1771 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1772 
1773 #define ADV_CARRIER_NUM_PAGE_CROSSING \
1774     (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1775 
1776 #define ADV_CARRIER_BUFSIZE \
1777     ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1778 
1779 /*
1780  * ASC_SCSI_REQ_Q 'a_flag' definitions
1781  *
1782  * The Adv Library should limit use to the lower nibble (4 bits) of
1783  * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1784  */
1785 #define ADV_POLL_REQUEST                0x01	/* poll for request completion */
1786 #define ADV_SCSIQ_DONE                  0x02	/* request done */
1787 #define ADV_DONT_RETRY                  0x08	/* don't do retry */
1788 
1789 #define ADV_CHIP_ASC3550          0x01	/* Ultra-Wide IC */
1790 #define ADV_CHIP_ASC38C0800       0x02	/* Ultra2-Wide/LVD IC */
1791 #define ADV_CHIP_ASC38C1600       0x03	/* Ultra3-Wide/LVD2 IC */
1792 
1793 /*
1794  * Adapter temporary configuration structure
1795  *
1796  * This structure can be discarded after initialization. Don't add
1797  * fields here needed after initialization.
1798  *
1799  * Field naming convention:
1800  *
1801  *  *_enable indicates the field enables or disables a feature. The
1802  *  value of the field is never reset.
1803  */
1804 typedef struct adv_dvc_cfg {
1805 	ushort disc_enable;	/* enable disconnection */
1806 	uchar chip_version;	/* chip version */
1807 	uchar termination;	/* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1808 	ushort control_flag;	/* Microcode Control Flag */
1809 	ushort mcode_date;	/* Microcode date */
1810 	ushort mcode_version;	/* Microcode version */
1811 	ushort serial1;		/* EEPROM serial number word 1 */
1812 	ushort serial2;		/* EEPROM serial number word 2 */
1813 	ushort serial3;		/* EEPROM serial number word 3 */
1814 } ADV_DVC_CFG;
1815 
1816 struct adv_dvc_var;
1817 struct adv_scsi_req_q;
1818 
1819 typedef struct asc_sg_block {
1820 	uchar reserved1;
1821 	uchar reserved2;
1822 	uchar reserved3;
1823 	uchar sg_cnt;		/* Valid entries in block. */
1824 	ADV_PADDR sg_ptr;	/* Pointer to next sg block. */
1825 	struct {
1826 		ADV_PADDR sg_addr;	/* SG element address. */
1827 		ADV_DCNT sg_count;	/* SG element count. */
1828 	} sg_list[NO_OF_SG_PER_BLOCK];
1829 } ADV_SG_BLOCK;
1830 
1831 /*
1832  * ADV_SCSI_REQ_Q - microcode request structure
1833  *
1834  * All fields in this structure up to byte 60 are used by the microcode.
1835  * The microcode makes assumptions about the size and ordering of fields
1836  * in this structure. Do not change the structure definition here without
1837  * coordinating the change with the microcode.
1838  *
1839  * All fields accessed by microcode must be maintained in little_endian
1840  * order.
1841  */
1842 typedef struct adv_scsi_req_q {
1843 	uchar cntl;		/* Ucode flags and state (ASC_MC_QC_*). */
1844 	uchar target_cmd;
1845 	uchar target_id;	/* Device target identifier. */
1846 	uchar target_lun;	/* Device target logical unit number. */
1847 	ADV_PADDR data_addr;	/* Data buffer physical address. */
1848 	ADV_DCNT data_cnt;	/* Data count. Ucode sets to residual. */
1849 	ADV_PADDR sense_addr;
1850 	ADV_PADDR carr_pa;
1851 	uchar mflag;
1852 	uchar sense_len;
1853 	uchar cdb_len;		/* SCSI CDB length. Must <= 16 bytes. */
1854 	uchar scsi_cntl;
1855 	uchar done_status;	/* Completion status. */
1856 	uchar scsi_status;	/* SCSI status byte. */
1857 	uchar host_status;	/* Ucode host status. */
1858 	uchar sg_working_ix;
1859 	uchar cdb[12];		/* SCSI CDB bytes 0-11. */
1860 	ADV_PADDR sg_real_addr;	/* SG list physical address. */
1861 	ADV_PADDR scsiq_rptr;
1862 	uchar cdb16[4];		/* SCSI CDB bytes 12-15. */
1863 	ADV_VADDR scsiq_ptr;
1864 	ADV_VADDR carr_va;
1865 	/*
1866 	 * End of microcode structure - 60 bytes. The rest of the structure
1867 	 * is used by the Adv Library and ignored by the microcode.
1868 	 */
1869 	ADV_VADDR srb_ptr;
1870 	ADV_SG_BLOCK *sg_list_ptr;	/* SG list virtual address. */
1871 	char *vdata_addr;	/* Data buffer virtual address. */
1872 	uchar a_flag;
1873 	uchar pad[2];		/* Pad out to a word boundary. */
1874 } ADV_SCSI_REQ_Q;
1875 
1876 /*
1877  * The following two structures are used to process Wide Board requests.
1878  *
1879  * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1880  * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1881  * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1882  * Mid-Level SCSI request structure.
1883  *
1884  * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1885  * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1886  * up to 255 scatter-gather elements may be used per request or
1887  * ADV_SCSI_REQ_Q.
1888  *
1889  * Both structures must be 32 byte aligned.
1890  */
1891 typedef struct adv_sgblk {
1892 	ADV_SG_BLOCK sg_block;	/* Sgblock structure. */
1893 	uchar align[32];	/* Sgblock structure padding. */
1894 	struct adv_sgblk *next_sgblkp;	/* Next scatter-gather structure. */
1895 } adv_sgblk_t;
1896 
1897 typedef struct adv_req {
1898 	ADV_SCSI_REQ_Q scsi_req_q;	/* Adv Library request structure. */
1899 	uchar align[32];	/* Request structure padding. */
1900 	struct scsi_cmnd *cmndp;	/* Mid-Level SCSI command pointer. */
1901 	adv_sgblk_t *sgblkp;	/* Adv Library scatter-gather pointer. */
1902 	struct adv_req *next_reqp;	/* Next Request Structure. */
1903 } adv_req_t;
1904 
1905 /*
1906  * Adapter operation variable structure.
1907  *
1908  * One structure is required per host adapter.
1909  *
1910  * Field naming convention:
1911  *
1912  *  *_able indicates both whether a feature should be enabled or disabled
1913  *  and whether a device isi capable of the feature. At initialization
1914  *  this field may be set, but later if a device is found to be incapable
1915  *  of the feature, the field is cleared.
1916  */
1917 typedef struct adv_dvc_var {
1918 	AdvPortAddr iop_base;	/* I/O port address */
1919 	ushort err_code;	/* fatal error code */
1920 	ushort bios_ctrl;	/* BIOS control word, EEPROM word 12 */
1921 	ushort wdtr_able;	/* try WDTR for a device */
1922 	ushort sdtr_able;	/* try SDTR for a device */
1923 	ushort ultra_able;	/* try SDTR Ultra speed for a device */
1924 	ushort sdtr_speed1;	/* EEPROM SDTR Speed for TID 0-3   */
1925 	ushort sdtr_speed2;	/* EEPROM SDTR Speed for TID 4-7   */
1926 	ushort sdtr_speed3;	/* EEPROM SDTR Speed for TID 8-11  */
1927 	ushort sdtr_speed4;	/* EEPROM SDTR Speed for TID 12-15 */
1928 	ushort tagqng_able;	/* try tagged queuing with a device */
1929 	ushort ppr_able;	/* PPR message capable per TID bitmask. */
1930 	uchar max_dvc_qng;	/* maximum number of tagged commands per device */
1931 	ushort start_motor;	/* start motor command allowed */
1932 	uchar scsi_reset_wait;	/* delay in seconds after scsi bus reset */
1933 	uchar chip_no;		/* should be assigned by caller */
1934 	uchar max_host_qng;	/* maximum number of Q'ed command allowed */
1935 	ushort no_scam;		/* scam_tolerant of EEPROM */
1936 	struct asc_board *drv_ptr;	/* driver pointer to private structure */
1937 	uchar chip_scsi_id;	/* chip SCSI target ID */
1938 	uchar chip_type;
1939 	uchar bist_err_code;
1940 	ADV_CARR_T *carrier_buf;
1941 	ADV_CARR_T *carr_freelist;	/* Carrier free list. */
1942 	ADV_CARR_T *icq_sp;	/* Initiator command queue stopper pointer. */
1943 	ADV_CARR_T *irq_sp;	/* Initiator response queue stopper pointer. */
1944 	ushort carr_pending_cnt;	/* Count of pending carriers. */
1945 	struct adv_req *orig_reqp;	/* adv_req_t memory block. */
1946 	/*
1947 	 * Note: The following fields will not be used after initialization. The
1948 	 * driver may discard the buffer after initialization is done.
1949 	 */
1950 	ADV_DVC_CFG *cfg;	/* temporary configuration structure  */
1951 } ADV_DVC_VAR;
1952 
1953 /*
1954  * Microcode idle loop commands
1955  */
1956 #define IDLE_CMD_COMPLETED           0
1957 #define IDLE_CMD_STOP_CHIP           0x0001
1958 #define IDLE_CMD_STOP_CHIP_SEND_INT  0x0002
1959 #define IDLE_CMD_SEND_INT            0x0004
1960 #define IDLE_CMD_ABORT               0x0008
1961 #define IDLE_CMD_DEVICE_RESET        0x0010
1962 #define IDLE_CMD_SCSI_RESET_START    0x0020	/* Assert SCSI Bus Reset */
1963 #define IDLE_CMD_SCSI_RESET_END      0x0040	/* Deassert SCSI Bus Reset */
1964 #define IDLE_CMD_SCSIREQ             0x0080
1965 
1966 #define IDLE_CMD_STATUS_SUCCESS      0x0001
1967 #define IDLE_CMD_STATUS_FAILURE      0x0002
1968 
1969 /*
1970  * AdvSendIdleCmd() flag definitions.
1971  */
1972 #define ADV_NOWAIT     0x01
1973 
1974 /*
1975  * Wait loop time out values.
1976  */
1977 #define SCSI_WAIT_100_MSEC           100UL	/* 100 milliseconds */
1978 #define SCSI_US_PER_MSEC             1000	/* microseconds per millisecond */
1979 #define SCSI_MAX_RETRY               10	/* retry count */
1980 
1981 #define ADV_ASYNC_RDMA_FAILURE          0x01	/* Fatal RDMA failure. */
1982 #define ADV_ASYNC_SCSI_BUS_RESET_DET    0x02	/* Detected SCSI Bus Reset. */
1983 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03	/* Carrier Ready failure. */
1984 #define ADV_RDMA_IN_CARR_AND_Q_INVALID  0x04	/* RDMAed-in data invalid. */
1985 
1986 #define ADV_HOST_SCSI_BUS_RESET      0x80	/* Host Initiated SCSI Bus Reset. */
1987 
1988 /* Read byte from a register. */
1989 #define AdvReadByteRegister(iop_base, reg_off) \
1990      (ADV_MEM_READB((iop_base) + (reg_off)))
1991 
1992 /* Write byte to a register. */
1993 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1994      (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1995 
1996 /* Read word (2 bytes) from a register. */
1997 #define AdvReadWordRegister(iop_base, reg_off) \
1998      (ADV_MEM_READW((iop_base) + (reg_off)))
1999 
2000 /* Write word (2 bytes) to a register. */
2001 #define AdvWriteWordRegister(iop_base, reg_off, word) \
2002      (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2003 
2004 /* Write dword (4 bytes) to a register. */
2005 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2006      (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2007 
2008 /* Read byte from LRAM. */
2009 #define AdvReadByteLram(iop_base, addr, byte) \
2010 do { \
2011     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2012     (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2013 } while (0)
2014 
2015 /* Write byte to LRAM. */
2016 #define AdvWriteByteLram(iop_base, addr, byte) \
2017     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2018      ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2019 
2020 /* Read word (2 bytes) from LRAM. */
2021 #define AdvReadWordLram(iop_base, addr, word) \
2022 do { \
2023     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2024     (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2025 } while (0)
2026 
2027 /* Write word (2 bytes) to LRAM. */
2028 #define AdvWriteWordLram(iop_base, addr, word) \
2029     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2030      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2031 
2032 /* Write little-endian double word (4 bytes) to LRAM */
2033 /* Because of unspecified C language ordering don't use auto-increment. */
2034 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2035     ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2036       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2037                      cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2038      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2039       ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2040                      cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2041 
2042 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
2043 #define AdvReadWordAutoIncLram(iop_base) \
2044      (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2045 
2046 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
2047 #define AdvWriteWordAutoIncLram(iop_base, word) \
2048      (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2049 
2050 /*
2051  * Define macro to check for Condor signature.
2052  *
2053  * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2054  * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2055  */
2056 #define AdvFindSignature(iop_base) \
2057     (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2058     ADV_CHIP_ID_BYTE) && \
2059      (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2060     ADV_CHIP_ID_WORD)) ?  ADV_TRUE : ADV_FALSE)
2061 
2062 /*
2063  * Define macro to Return the version number of the chip at 'iop_base'.
2064  *
2065  * The second parameter 'bus_type' is currently unused.
2066  */
2067 #define AdvGetChipVersion(iop_base, bus_type) \
2068     AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2069 
2070 /*
2071  * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2072  * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2073  *
2074  * If the request has not yet been sent to the device it will simply be
2075  * aborted from RISC memory. If the request is disconnected it will be
2076  * aborted on reselection by sending an Abort Message to the target ID.
2077  *
2078  * Return value:
2079  *      ADV_TRUE(1) - Queue was successfully aborted.
2080  *      ADV_FALSE(0) - Queue was not found on the active queue list.
2081  */
2082 #define AdvAbortQueue(asc_dvc, scsiq) \
2083         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2084                        (ADV_DCNT) (scsiq))
2085 
2086 /*
2087  * Send a Bus Device Reset Message to the specified target ID.
2088  *
2089  * All outstanding commands will be purged if sending the
2090  * Bus Device Reset Message is successful.
2091  *
2092  * Return Value:
2093  *      ADV_TRUE(1) - All requests on the target are purged.
2094  *      ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2095  *                     are not purged.
2096  */
2097 #define AdvResetDevice(asc_dvc, target_id) \
2098         AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2099                     (ADV_DCNT) (target_id))
2100 
2101 /*
2102  * SCSI Wide Type definition.
2103  */
2104 #define ADV_SCSI_BIT_ID_TYPE   ushort
2105 
2106 /*
2107  * AdvInitScsiTarget() 'cntl_flag' options.
2108  */
2109 #define ADV_SCAN_LUN           0x01
2110 #define ADV_CAPINFO_NOLUN      0x02
2111 
2112 /*
2113  * Convert target id to target id bit mask.
2114  */
2115 #define ADV_TID_TO_TIDMASK(tid)   (0x01 << ((tid) & ADV_MAX_TID))
2116 
2117 /*
2118  * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2119  */
2120 
2121 #define QD_NO_STATUS         0x00	/* Request not completed yet. */
2122 #define QD_NO_ERROR          0x01
2123 #define QD_ABORTED_BY_HOST   0x02
2124 #define QD_WITH_ERROR        0x04
2125 
2126 #define QHSTA_NO_ERROR              0x00
2127 #define QHSTA_M_SEL_TIMEOUT         0x11
2128 #define QHSTA_M_DATA_OVER_RUN       0x12
2129 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2130 #define QHSTA_M_QUEUE_ABORTED       0x15
2131 #define QHSTA_M_SXFR_SDMA_ERR       0x16	/* SXFR_STATUS SCSI DMA Error */
2132 #define QHSTA_M_SXFR_SXFR_PERR      0x17	/* SXFR_STATUS SCSI Bus Parity Error */
2133 #define QHSTA_M_RDMA_PERR           0x18	/* RISC PCI DMA parity error */
2134 #define QHSTA_M_SXFR_OFF_UFLW       0x19	/* SXFR_STATUS Offset Underflow */
2135 #define QHSTA_M_SXFR_OFF_OFLW       0x20	/* SXFR_STATUS Offset Overflow */
2136 #define QHSTA_M_SXFR_WD_TMO         0x21	/* SXFR_STATUS Watchdog Timeout */
2137 #define QHSTA_M_SXFR_DESELECTED     0x22	/* SXFR_STATUS Deselected */
2138 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2139 #define QHSTA_M_SXFR_XFR_OFLW       0x12	/* SXFR_STATUS Transfer Overflow */
2140 #define QHSTA_M_SXFR_XFR_PH_ERR     0x24	/* SXFR_STATUS Transfer Phase Error */
2141 #define QHSTA_M_SXFR_UNKNOWN_ERROR  0x25	/* SXFR_STATUS Unknown Error */
2142 #define QHSTA_M_SCSI_BUS_RESET      0x30	/* Request aborted from SBR */
2143 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31	/* Request aborted from unsol. SBR */
2144 #define QHSTA_M_BUS_DEVICE_RESET    0x32	/* Request aborted from BDR */
2145 #define QHSTA_M_DIRECTION_ERR       0x35	/* Data Phase mismatch */
2146 #define QHSTA_M_DIRECTION_ERR_HUNG  0x36	/* Data Phase mismatch and bus hang */
2147 #define QHSTA_M_WTM_TIMEOUT         0x41
2148 #define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
2149 #define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
2150 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2151 #define QHSTA_M_INVALID_DEVICE      0x45	/* Bad target ID */
2152 #define QHSTA_M_FROZEN_TIDQ         0x46	/* TID Queue frozen. */
2153 #define QHSTA_M_SGBACKUP_ERROR      0x47	/* Scatter-Gather backup error */
2154 
2155 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
2156 #define ADV_8BALIGN(addr)      (((ulong) (addr) + 0x7) & ~0x7)
2157 #define ADV_16BALIGN(addr)     (((ulong) (addr) + 0xF) & ~0xF)
2158 #define ADV_32BALIGN(addr)     (((ulong) (addr) + 0x1F) & ~0x1F)
2159 
2160 /*
2161  * Total contiguous memory needed for driver SG blocks.
2162  *
2163  * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2164  * number of scatter-gather elements the driver supports in a
2165  * single request.
2166  */
2167 
2168 #define ADV_SG_LIST_MAX_BYTE_SIZE \
2169          (sizeof(ADV_SG_BLOCK) * \
2170           ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2171 
2172 /* struct asc_board flags */
2173 #define ASC_IS_WIDE_BOARD       0x04	/* AdvanSys Wide Board */
2174 
2175 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2176 
2177 #define NO_ISA_DMA              0xff	/* No ISA DMA Channel Used */
2178 
2179 #define ASC_INFO_SIZE           128	/* advansys_info() line size */
2180 
2181 /* Asc Library return codes */
2182 #define ASC_TRUE        1
2183 #define ASC_FALSE       0
2184 #define ASC_NOERROR     1
2185 #define ASC_BUSY        0
2186 #define ASC_ERROR       (-1)
2187 
2188 /* struct scsi_cmnd function return codes */
2189 #define STATUS_BYTE(byte)   (byte)
2190 #define MSG_BYTE(byte)      ((byte) << 8)
2191 #define HOST_BYTE(byte)     ((byte) << 16)
2192 #define DRIVER_BYTE(byte)   ((byte) << 24)
2193 
2194 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2195 #ifndef ADVANSYS_STATS
2196 #define ASC_STATS_ADD(shost, counter, count)
2197 #else /* ADVANSYS_STATS */
2198 #define ASC_STATS_ADD(shost, counter, count) \
2199 	(((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2200 #endif /* ADVANSYS_STATS */
2201 
2202 /* If the result wraps when calculating tenths, return 0. */
2203 #define ASC_TENTHS(num, den) \
2204     (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2205     0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2206 
2207 /*
2208  * Display a message to the console.
2209  */
2210 #define ASC_PRINT(s) \
2211     { \
2212         printk("advansys: "); \
2213         printk(s); \
2214     }
2215 
2216 #define ASC_PRINT1(s, a1) \
2217     { \
2218         printk("advansys: "); \
2219         printk((s), (a1)); \
2220     }
2221 
2222 #define ASC_PRINT2(s, a1, a2) \
2223     { \
2224         printk("advansys: "); \
2225         printk((s), (a1), (a2)); \
2226     }
2227 
2228 #define ASC_PRINT3(s, a1, a2, a3) \
2229     { \
2230         printk("advansys: "); \
2231         printk((s), (a1), (a2), (a3)); \
2232     }
2233 
2234 #define ASC_PRINT4(s, a1, a2, a3, a4) \
2235     { \
2236         printk("advansys: "); \
2237         printk((s), (a1), (a2), (a3), (a4)); \
2238     }
2239 
2240 #ifndef ADVANSYS_DEBUG
2241 
2242 #define ASC_DBG(lvl, s...)
2243 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2244 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2245 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2246 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2247 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2248 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
2249 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
2250 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
2251 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2252 
2253 #else /* ADVANSYS_DEBUG */
2254 
2255 /*
2256  * Debugging Message Levels:
2257  * 0: Errors Only
2258  * 1: High-Level Tracing
2259  * 2-N: Verbose Tracing
2260  */
2261 
2262 #define ASC_DBG(lvl, format, arg...) {					\
2263 	if (asc_dbglvl >= (lvl))					\
2264 		printk(KERN_DEBUG "%s: %s: " format, DRV_NAME,		\
2265 			__func__ , ## arg);				\
2266 }
2267 
2268 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2269     { \
2270         if (asc_dbglvl >= (lvl)) { \
2271             asc_prt_scsi_host(s); \
2272         } \
2273     }
2274 
2275 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2276     { \
2277         if (asc_dbglvl >= (lvl)) { \
2278             asc_prt_asc_scsi_q(scsiqp); \
2279         } \
2280     }
2281 
2282 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2283     { \
2284         if (asc_dbglvl >= (lvl)) { \
2285             asc_prt_asc_qdone_info(qdone); \
2286         } \
2287     }
2288 
2289 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2290     { \
2291         if (asc_dbglvl >= (lvl)) { \
2292             asc_prt_adv_scsi_req_q(scsiqp); \
2293         } \
2294     }
2295 
2296 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2297     { \
2298         if (asc_dbglvl >= (lvl)) { \
2299             asc_prt_hex((name), (start), (length)); \
2300         } \
2301     }
2302 
2303 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2304         ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2305 
2306 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2307         ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2308 
2309 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2310         ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2311 #endif /* ADVANSYS_DEBUG */
2312 
2313 #ifdef ADVANSYS_STATS
2314 
2315 /* Per board statistics structure */
2316 struct asc_stats {
2317 	/* Driver Entrypoint Statistics */
2318 	ADV_DCNT queuecommand;	/* # calls to advansys_queuecommand() */
2319 	ADV_DCNT reset;		/* # calls to advansys_eh_bus_reset() */
2320 	ADV_DCNT biosparam;	/* # calls to advansys_biosparam() */
2321 	ADV_DCNT interrupt;	/* # advansys_interrupt() calls */
2322 	ADV_DCNT callback;	/* # calls to asc/adv_isr_callback() */
2323 	ADV_DCNT done;		/* # calls to request's scsi_done function */
2324 	ADV_DCNT build_error;	/* # asc/adv_build_req() ASC_ERROR returns. */
2325 	ADV_DCNT adv_build_noreq;	/* # adv_build_req() adv_req_t alloc. fail. */
2326 	ADV_DCNT adv_build_nosg;	/* # adv_build_req() adv_sgblk_t alloc. fail. */
2327 	/* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2328 	ADV_DCNT exe_noerror;	/* # ASC_NOERROR returns. */
2329 	ADV_DCNT exe_busy;	/* # ASC_BUSY returns. */
2330 	ADV_DCNT exe_error;	/* # ASC_ERROR returns. */
2331 	ADV_DCNT exe_unknown;	/* # unknown returns. */
2332 	/* Data Transfer Statistics */
2333 	ADV_DCNT xfer_cnt;	/* # I/O requests received */
2334 	ADV_DCNT xfer_elem;	/* # scatter-gather elements */
2335 	ADV_DCNT xfer_sect;	/* # 512-byte blocks */
2336 };
2337 #endif /* ADVANSYS_STATS */
2338 
2339 /*
2340  * Structure allocated for each board.
2341  *
2342  * This structure is allocated by scsi_host_alloc() at the end
2343  * of the 'Scsi_Host' structure starting at the 'hostdata'
2344  * field. It is guaranteed to be allocated from DMA-able memory.
2345  */
2346 struct asc_board {
2347 	struct device *dev;
2348 	uint flags;		/* Board flags */
2349 	unsigned int irq;
2350 	union {
2351 		ASC_DVC_VAR asc_dvc_var;	/* Narrow board */
2352 		ADV_DVC_VAR adv_dvc_var;	/* Wide board */
2353 	} dvc_var;
2354 	union {
2355 		ASC_DVC_CFG asc_dvc_cfg;	/* Narrow board */
2356 		ADV_DVC_CFG adv_dvc_cfg;	/* Wide board */
2357 	} dvc_cfg;
2358 	ushort asc_n_io_port;	/* Number I/O ports. */
2359 	ADV_SCSI_BIT_ID_TYPE init_tidmask;	/* Target init./valid mask */
2360 	ushort reqcnt[ADV_MAX_TID + 1];	/* Starvation request count */
2361 	ADV_SCSI_BIT_ID_TYPE queue_full;	/* Queue full mask */
2362 	ushort queue_full_cnt[ADV_MAX_TID + 1];	/* Queue full count */
2363 	union {
2364 		ASCEEP_CONFIG asc_eep;	/* Narrow EEPROM config. */
2365 		ADVEEP_3550_CONFIG adv_3550_eep;	/* 3550 EEPROM config. */
2366 		ADVEEP_38C0800_CONFIG adv_38C0800_eep;	/* 38C0800 EEPROM config. */
2367 		ADVEEP_38C1600_CONFIG adv_38C1600_eep;	/* 38C1600 EEPROM config. */
2368 	} eep_config;
2369 	ulong last_reset;	/* Saved last reset time */
2370 	/* /proc/scsi/advansys/[0...] */
2371 #ifdef ADVANSYS_STATS
2372 	struct asc_stats asc_stats;	/* Board statistics */
2373 #endif				/* ADVANSYS_STATS */
2374 	/*
2375 	 * The following fields are used only for Narrow Boards.
2376 	 */
2377 	uchar sdtr_data[ASC_MAX_TID + 1];	/* SDTR information */
2378 	/*
2379 	 * The following fields are used only for Wide Boards.
2380 	 */
2381 	void __iomem *ioremap_addr;	/* I/O Memory remap address. */
2382 	ushort ioport;		/* I/O Port address. */
2383 	adv_req_t *adv_reqp;	/* Request structures. */
2384 	adv_sgblk_t *adv_sgblkp;	/* Scatter-gather structures. */
2385 	ushort bios_signature;	/* BIOS Signature. */
2386 	ushort bios_version;	/* BIOS Version. */
2387 	ushort bios_codeseg;	/* BIOS Code Segment. */
2388 	ushort bios_codelen;	/* BIOS Code Segment Length. */
2389 };
2390 
2391 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2392 							dvc_var.asc_dvc_var)
2393 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2394 							dvc_var.adv_dvc_var)
2395 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2396 
2397 #ifdef ADVANSYS_DEBUG
2398 static int asc_dbglvl = 3;
2399 
2400 /*
2401  * asc_prt_asc_dvc_var()
2402  */
2403 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2404 {
2405 	printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2406 
2407 	printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2408 	       "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2409 
2410 	printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2411 		(unsigned)h->init_sdtr);
2412 
2413 	printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2414 	       "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2415 	       (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2416 	       (unsigned)h->chip_no);
2417 
2418 	printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2419 	       "%u,\n", (unsigned)h->queue_full_or_busy,
2420 	       (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2421 
2422 	printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2423 	       "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2424 	       (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2425 	       (unsigned)h->in_critical_cnt);
2426 
2427 	printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2428 	       "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2429 	       (unsigned)h->init_state, (unsigned)h->no_scam,
2430 	       (unsigned)h->pci_fix_asyn_xfer);
2431 
2432 	printk(" cfg 0x%lx\n", (ulong)h->cfg);
2433 }
2434 
2435 /*
2436  * asc_prt_asc_dvc_cfg()
2437  */
2438 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2439 {
2440 	printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2441 
2442 	printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2443 	       h->can_tagged_qng, h->cmd_qng_enabled);
2444 	printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2445 	       h->disc_enable, h->sdtr_enable);
2446 
2447 	printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2448 		"chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2449 		h->isa_dma_channel, h->chip_version);
2450 
2451 	printk(" mcode_date 0x%x, mcode_version %d\n",
2452 		h->mcode_date, h->mcode_version);
2453 }
2454 
2455 /*
2456  * asc_prt_adv_dvc_var()
2457  *
2458  * Display an ADV_DVC_VAR structure.
2459  */
2460 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2461 {
2462 	printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2463 
2464 	printk("  iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2465 	       (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2466 
2467 	printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2468 	       (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2469 
2470 	printk("  start_motor 0x%x, scsi_reset_wait 0x%x\n",
2471 	       (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2472 
2473 	printk("  max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2474 	       (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2475 	       (ulong)h->carr_freelist);
2476 
2477 	printk("  icq_sp 0x%lx, irq_sp 0x%lx\n",
2478 	       (ulong)h->icq_sp, (ulong)h->irq_sp);
2479 
2480 	printk("  no_scam 0x%x, tagqng_able 0x%x\n",
2481 	       (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2482 
2483 	printk("  chip_scsi_id 0x%x, cfg 0x%lx\n",
2484 	       (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2485 }
2486 
2487 /*
2488  * asc_prt_adv_dvc_cfg()
2489  *
2490  * Display an ADV_DVC_CFG structure.
2491  */
2492 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2493 {
2494 	printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2495 
2496 	printk("  disc_enable 0x%x, termination 0x%x\n",
2497 	       h->disc_enable, h->termination);
2498 
2499 	printk("  chip_version 0x%x, mcode_date 0x%x\n",
2500 	       h->chip_version, h->mcode_date);
2501 
2502 	printk("  mcode_version 0x%x, control_flag 0x%x\n",
2503 	       h->mcode_version, h->control_flag);
2504 }
2505 
2506 /*
2507  * asc_prt_scsi_host()
2508  */
2509 static void asc_prt_scsi_host(struct Scsi_Host *s)
2510 {
2511 	struct asc_board *boardp = shost_priv(s);
2512 
2513 	printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2514 	printk(" host_busy %u, host_no %d, last_reset %d,\n",
2515 	       s->host_busy, s->host_no, (unsigned)s->last_reset);
2516 
2517 	printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2518 	       (ulong)s->base, (ulong)s->io_port, boardp->irq);
2519 
2520 	printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2521 	       s->dma_channel, s->this_id, s->can_queue);
2522 
2523 	printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2524 	       s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
2525 
2526 	if (ASC_NARROW_BOARD(boardp)) {
2527 		asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2528 		asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2529 	} else {
2530 		asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2531 		asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2532 	}
2533 }
2534 
2535 /*
2536  * asc_prt_hex()
2537  *
2538  * Print hexadecimal output in 4 byte groupings 32 bytes
2539  * or 8 double-words per line.
2540  */
2541 static void asc_prt_hex(char *f, uchar *s, int l)
2542 {
2543 	int i;
2544 	int j;
2545 	int k;
2546 	int m;
2547 
2548 	printk("%s: (%d bytes)\n", f, l);
2549 
2550 	for (i = 0; i < l; i += 32) {
2551 
2552 		/* Display a maximum of 8 double-words per line. */
2553 		if ((k = (l - i) / 4) >= 8) {
2554 			k = 8;
2555 			m = 0;
2556 		} else {
2557 			m = (l - i) % 4;
2558 		}
2559 
2560 		for (j = 0; j < k; j++) {
2561 			printk(" %2.2X%2.2X%2.2X%2.2X",
2562 			       (unsigned)s[i + (j * 4)],
2563 			       (unsigned)s[i + (j * 4) + 1],
2564 			       (unsigned)s[i + (j * 4) + 2],
2565 			       (unsigned)s[i + (j * 4) + 3]);
2566 		}
2567 
2568 		switch (m) {
2569 		case 0:
2570 		default:
2571 			break;
2572 		case 1:
2573 			printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2574 			break;
2575 		case 2:
2576 			printk(" %2.2X%2.2X",
2577 			       (unsigned)s[i + (j * 4)],
2578 			       (unsigned)s[i + (j * 4) + 1]);
2579 			break;
2580 		case 3:
2581 			printk(" %2.2X%2.2X%2.2X",
2582 			       (unsigned)s[i + (j * 4) + 1],
2583 			       (unsigned)s[i + (j * 4) + 2],
2584 			       (unsigned)s[i + (j * 4) + 3]);
2585 			break;
2586 		}
2587 
2588 		printk("\n");
2589 	}
2590 }
2591 
2592 /*
2593  * asc_prt_asc_scsi_q()
2594  */
2595 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2596 {
2597 	ASC_SG_HEAD *sgp;
2598 	int i;
2599 
2600 	printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2601 
2602 	printk
2603 	    (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2604 	     q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2605 	     q->q2.tag_code);
2606 
2607 	printk
2608 	    (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2609 	     (ulong)le32_to_cpu(q->q1.data_addr),
2610 	     (ulong)le32_to_cpu(q->q1.data_cnt),
2611 	     (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2612 
2613 	printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2614 	       (ulong)q->cdbptr, q->q2.cdb_len,
2615 	       (ulong)q->sg_head, q->q1.sg_queue_cnt);
2616 
2617 	if (q->sg_head) {
2618 		sgp = q->sg_head;
2619 		printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2620 		printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2621 		       sgp->queue_cnt);
2622 		for (i = 0; i < sgp->entry_cnt; i++) {
2623 			printk(" [%u]: addr 0x%lx, bytes %lu\n",
2624 			       i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2625 			       (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2626 		}
2627 
2628 	}
2629 }
2630 
2631 /*
2632  * asc_prt_asc_qdone_info()
2633  */
2634 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2635 {
2636 	printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2637 	printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2638 	       (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2639 	       q->d2.tag_code);
2640 	printk
2641 	    (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2642 	     q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2643 }
2644 
2645 /*
2646  * asc_prt_adv_sgblock()
2647  *
2648  * Display an ADV_SG_BLOCK structure.
2649  */
2650 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2651 {
2652 	int i;
2653 
2654 	printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2655 	       (ulong)b, sgblockno);
2656 	printk("  sg_cnt %u, sg_ptr 0x%lx\n",
2657 	       b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2658 	BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2659 	if (b->sg_ptr != 0)
2660 		BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2661 	for (i = 0; i < b->sg_cnt; i++) {
2662 		printk("  [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2663 		       i, (ulong)b->sg_list[i].sg_addr,
2664 		       (ulong)b->sg_list[i].sg_count);
2665 	}
2666 }
2667 
2668 /*
2669  * asc_prt_adv_scsi_req_q()
2670  *
2671  * Display an ADV_SCSI_REQ_Q structure.
2672  */
2673 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2674 {
2675 	int sg_blk_cnt;
2676 	struct asc_sg_block *sg_ptr;
2677 
2678 	printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2679 
2680 	printk("  target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2681 	       q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2682 
2683 	printk("  cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2684 	       q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2685 
2686 	printk("  data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2687 	       (ulong)le32_to_cpu(q->data_cnt),
2688 	       (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2689 
2690 	printk
2691 	    ("  cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2692 	     q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2693 
2694 	printk("  sg_working_ix 0x%x, target_cmd %u\n",
2695 	       q->sg_working_ix, q->target_cmd);
2696 
2697 	printk("  scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2698 	       (ulong)le32_to_cpu(q->scsiq_rptr),
2699 	       (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2700 
2701 	/* Display the request's ADV_SG_BLOCK structures. */
2702 	if (q->sg_list_ptr != NULL) {
2703 		sg_blk_cnt = 0;
2704 		while (1) {
2705 			/*
2706 			 * 'sg_ptr' is a physical address. Convert it to a virtual
2707 			 * address by indexing 'sg_blk_cnt' into the virtual address
2708 			 * array 'sg_list_ptr'.
2709 			 *
2710 			 * XXX - Assumes all SG physical blocks are virtually contiguous.
2711 			 */
2712 			sg_ptr =
2713 			    &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2714 			asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2715 			if (sg_ptr->sg_ptr == 0) {
2716 				break;
2717 			}
2718 			sg_blk_cnt++;
2719 		}
2720 	}
2721 }
2722 #endif /* ADVANSYS_DEBUG */
2723 
2724 /*
2725  * The advansys chip/microcode contains a 32-bit identifier for each command
2726  * known as the 'srb'.  I don't know what it stands for.  The driver used
2727  * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2728  * with bus_to_virt.  Now the driver keeps a per-host map of integers to
2729  * pointers.  It auto-expands when full, unless it can't allocate memory.
2730  * Note that an srb of 0 is treated specially by the chip/firmware, hence
2731  * the return of i+1 in this routine, and the corresponding subtraction in
2732  * the inverse routine.
2733  */
2734 #define BAD_SRB 0
2735 static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr)
2736 {
2737 	int i;
2738 	void **new_ptr;
2739 
2740 	for (i = 0; i < asc_dvc->ptr_map_count; i++) {
2741 		if (!asc_dvc->ptr_map[i])
2742 			goto out;
2743 	}
2744 
2745 	if (asc_dvc->ptr_map_count == 0)
2746 		asc_dvc->ptr_map_count = 1;
2747 	else
2748 		asc_dvc->ptr_map_count *= 2;
2749 
2750 	new_ptr = krealloc(asc_dvc->ptr_map,
2751 			asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC);
2752 	if (!new_ptr)
2753 		return BAD_SRB;
2754 	asc_dvc->ptr_map = new_ptr;
2755  out:
2756 	ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i);
2757 	asc_dvc->ptr_map[i] = ptr;
2758 	return i + 1;
2759 }
2760 
2761 static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb)
2762 {
2763 	void *ptr;
2764 
2765 	srb--;
2766 	if (srb >= asc_dvc->ptr_map_count) {
2767 		printk("advansys: bad SRB %u, max %u\n", srb,
2768 							asc_dvc->ptr_map_count);
2769 		return NULL;
2770 	}
2771 	ptr = asc_dvc->ptr_map[srb];
2772 	asc_dvc->ptr_map[srb] = NULL;
2773 	ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb);
2774 	return ptr;
2775 }
2776 
2777 /*
2778  * advansys_info()
2779  *
2780  * Return suitable for printing on the console with the argument
2781  * adapter's configuration information.
2782  *
2783  * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2784  * otherwise the static 'info' array will be overrun.
2785  */
2786 static const char *advansys_info(struct Scsi_Host *shost)
2787 {
2788 	static char info[ASC_INFO_SIZE];
2789 	struct asc_board *boardp = shost_priv(shost);
2790 	ASC_DVC_VAR *asc_dvc_varp;
2791 	ADV_DVC_VAR *adv_dvc_varp;
2792 	char *busname;
2793 	char *widename = NULL;
2794 
2795 	if (ASC_NARROW_BOARD(boardp)) {
2796 		asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2797 		ASC_DBG(1, "begin\n");
2798 		if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2799 			if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2800 			    ASC_IS_ISAPNP) {
2801 				busname = "ISA PnP";
2802 			} else {
2803 				busname = "ISA";
2804 			}
2805 			sprintf(info,
2806 				"AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2807 				ASC_VERSION, busname,
2808 				(ulong)shost->io_port,
2809 				(ulong)shost->io_port + ASC_IOADR_GAP - 1,
2810 				boardp->irq, shost->dma_channel);
2811 		} else {
2812 			if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2813 				busname = "VL";
2814 			} else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2815 				busname = "EISA";
2816 			} else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2817 				if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2818 				    == ASC_IS_PCI_ULTRA) {
2819 					busname = "PCI Ultra";
2820 				} else {
2821 					busname = "PCI";
2822 				}
2823 			} else {
2824 				busname = "?";
2825 				shost_printk(KERN_ERR, shost, "unknown bus "
2826 					"type %d\n", asc_dvc_varp->bus_type);
2827 			}
2828 			sprintf(info,
2829 				"AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2830 				ASC_VERSION, busname, (ulong)shost->io_port,
2831 				(ulong)shost->io_port + ASC_IOADR_GAP - 1,
2832 				boardp->irq);
2833 		}
2834 	} else {
2835 		/*
2836 		 * Wide Adapter Information
2837 		 *
2838 		 * Memory-mapped I/O is used instead of I/O space to access
2839 		 * the adapter, but display the I/O Port range. The Memory
2840 		 * I/O address is displayed through the driver /proc file.
2841 		 */
2842 		adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2843 		if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2844 			widename = "Ultra-Wide";
2845 		} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2846 			widename = "Ultra2-Wide";
2847 		} else {
2848 			widename = "Ultra3-Wide";
2849 		}
2850 		sprintf(info,
2851 			"AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2852 			ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2853 			(ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2854 	}
2855 	BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2856 	ASC_DBG(1, "end\n");
2857 	return info;
2858 }
2859 
2860 #ifdef CONFIG_PROC_FS
2861 
2862 /*
2863  * asc_prt_board_devices()
2864  *
2865  * Print driver information for devices attached to the board.
2866  */
2867 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2868 {
2869 	struct asc_board *boardp = shost_priv(shost);
2870 	int chip_scsi_id;
2871 	int i;
2872 
2873 	seq_printf(m,
2874 		   "\nDevice Information for AdvanSys SCSI Host %d:\n",
2875 		   shost->host_no);
2876 
2877 	if (ASC_NARROW_BOARD(boardp)) {
2878 		chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2879 	} else {
2880 		chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2881 	}
2882 
2883 	seq_printf(m, "Target IDs Detected:");
2884 	for (i = 0; i <= ADV_MAX_TID; i++) {
2885 		if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2886 			seq_printf(m, " %X,", i);
2887 	}
2888 	seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2889 }
2890 
2891 /*
2892  * Display Wide Board BIOS Information.
2893  */
2894 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2895 {
2896 	struct asc_board *boardp = shost_priv(shost);
2897 	ushort major, minor, letter;
2898 
2899 	seq_printf(m, "\nROM BIOS Version: ");
2900 
2901 	/*
2902 	 * If the BIOS saved a valid signature, then fill in
2903 	 * the BIOS code segment base address.
2904 	 */
2905 	if (boardp->bios_signature != 0x55AA) {
2906 		seq_printf(m, "Disabled or Pre-3.1\n");
2907 		seq_printf(m,
2908 			  "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2909 		seq_printf(m,
2910 			  "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2911 	} else {
2912 		major = (boardp->bios_version >> 12) & 0xF;
2913 		minor = (boardp->bios_version >> 8) & 0xF;
2914 		letter = (boardp->bios_version & 0xFF);
2915 
2916 		seq_printf(m, "%d.%d%c\n",
2917 				   major, minor,
2918 				   letter >= 26 ? '?' : letter + 'A');
2919 		/*
2920 		 * Current available ROM BIOS release is 3.1I for UW
2921 		 * and 3.2I for U2W. This code doesn't differentiate
2922 		 * UW and U2W boards.
2923 		 */
2924 		if (major < 3 || (major <= 3 && minor < 1) ||
2925 		    (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2926 			seq_printf(m,
2927 				   "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
2928 			seq_printf(m,
2929 				   "ftp://ftp.connectcom.net/pub\n");
2930 		}
2931 	}
2932 }
2933 
2934 /*
2935  * Add serial number to information bar if signature AAh
2936  * is found in at bit 15-9 (7 bits) of word 1.
2937  *
2938  * Serial Number consists fo 12 alpha-numeric digits.
2939  *
2940  *       1 - Product type (A,B,C,D..)  Word0: 15-13 (3 bits)
2941  *       2 - MFG Location (A,B,C,D..)  Word0: 12-10 (3 bits)
2942  *     3-4 - Product ID (0-99)         Word0: 9-0 (10 bits)
2943  *       5 - Product revision (A-J)    Word0:  "         "
2944  *
2945  *           Signature                 Word1: 15-9 (7 bits)
2946  *       6 - Year (0-9)                Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2947  *     7-8 - Week of the year (1-52)   Word1: 5-0 (6 bits)
2948  *
2949  *    9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2950  *
2951  * Note 1: Only production cards will have a serial number.
2952  *
2953  * Note 2: Signature is most significant 7 bits (0xFE).
2954  *
2955  * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2956  */
2957 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2958 {
2959 	ushort w, num;
2960 
2961 	if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2962 		return ASC_FALSE;
2963 	} else {
2964 		/*
2965 		 * First word - 6 digits.
2966 		 */
2967 		w = serialnum[0];
2968 
2969 		/* Product type - 1st digit. */
2970 		if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2971 			/* Product type is P=Prototype */
2972 			*cp += 0x8;
2973 		}
2974 		cp++;
2975 
2976 		/* Manufacturing location - 2nd digit. */
2977 		*cp++ = 'A' + ((w & 0x1C00) >> 10);
2978 
2979 		/* Product ID - 3rd, 4th digits. */
2980 		num = w & 0x3FF;
2981 		*cp++ = '0' + (num / 100);
2982 		num %= 100;
2983 		*cp++ = '0' + (num / 10);
2984 
2985 		/* Product revision - 5th digit. */
2986 		*cp++ = 'A' + (num % 10);
2987 
2988 		/*
2989 		 * Second word
2990 		 */
2991 		w = serialnum[1];
2992 
2993 		/*
2994 		 * Year - 6th digit.
2995 		 *
2996 		 * If bit 15 of third word is set, then the
2997 		 * last digit of the year is greater than 7.
2998 		 */
2999 		if (serialnum[2] & 0x8000) {
3000 			*cp++ = '8' + ((w & 0x1C0) >> 6);
3001 		} else {
3002 			*cp++ = '0' + ((w & 0x1C0) >> 6);
3003 		}
3004 
3005 		/* Week of year - 7th, 8th digits. */
3006 		num = w & 0x003F;
3007 		*cp++ = '0' + num / 10;
3008 		num %= 10;
3009 		*cp++ = '0' + num;
3010 
3011 		/*
3012 		 * Third word
3013 		 */
3014 		w = serialnum[2] & 0x7FFF;
3015 
3016 		/* Serial number - 9th digit. */
3017 		*cp++ = 'A' + (w / 1000);
3018 
3019 		/* 10th, 11th, 12th digits. */
3020 		num = w % 1000;
3021 		*cp++ = '0' + num / 100;
3022 		num %= 100;
3023 		*cp++ = '0' + num / 10;
3024 		num %= 10;
3025 		*cp++ = '0' + num;
3026 
3027 		*cp = '\0';	/* Null Terminate the string. */
3028 		return ASC_TRUE;
3029 	}
3030 }
3031 
3032 /*
3033  * asc_prt_asc_board_eeprom()
3034  *
3035  * Print board EEPROM configuration.
3036  */
3037 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3038 {
3039 	struct asc_board *boardp = shost_priv(shost);
3040 	ASC_DVC_VAR *asc_dvc_varp;
3041 	ASCEEP_CONFIG *ep;
3042 	int i;
3043 #ifdef CONFIG_ISA
3044 	int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3045 #endif /* CONFIG_ISA */
3046 	uchar serialstr[13];
3047 
3048 	asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3049 	ep = &boardp->eep_config.asc_eep;
3050 
3051 	seq_printf(m,
3052 		   "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3053 		   shost->host_no);
3054 
3055 	if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
3056 	    == ASC_TRUE)
3057 		seq_printf(m, " Serial Number: %s\n", serialstr);
3058 	else if (ep->adapter_info[5] == 0xBB)
3059 		seq_printf(m,
3060 			   " Default Settings Used for EEPROM-less Adapter.\n");
3061 	else
3062 		seq_printf(m,
3063 			   " Serial Number Signature Not Present.\n");
3064 
3065 	seq_printf(m,
3066 		   " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3067 		   ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3068 		   ep->max_tag_qng);
3069 
3070 	seq_printf(m,
3071 		   " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3072 
3073 	seq_printf(m, " Target ID:           ");
3074 	for (i = 0; i <= ASC_MAX_TID; i++)
3075 		seq_printf(m, " %d", i);
3076 	seq_printf(m, "\n");
3077 
3078 	seq_printf(m, " Disconnects:         ");
3079 	for (i = 0; i <= ASC_MAX_TID; i++)
3080 		seq_printf(m, " %c",
3081 			   (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3082 	seq_printf(m, "\n");
3083 
3084 	seq_printf(m, " Command Queuing:     ");
3085 	for (i = 0; i <= ASC_MAX_TID; i++)
3086 		seq_printf(m, " %c",
3087 			   (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3088 	seq_printf(m, "\n");
3089 
3090 	seq_printf(m, " Start Motor:         ");
3091 	for (i = 0; i <= ASC_MAX_TID; i++)
3092 		seq_printf(m, " %c",
3093 			   (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3094 	seq_printf(m, "\n");
3095 
3096 	seq_printf(m, " Synchronous Transfer:");
3097 	for (i = 0; i <= ASC_MAX_TID; i++)
3098 		seq_printf(m, " %c",
3099 			   (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3100 	seq_printf(m, "\n");
3101 
3102 #ifdef CONFIG_ISA
3103 	if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
3104 		seq_printf(m,
3105 			   " Host ISA DMA speed:   %d MB/S\n",
3106 			   isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
3107 	}
3108 #endif /* CONFIG_ISA */
3109 }
3110 
3111 /*
3112  * asc_prt_adv_board_eeprom()
3113  *
3114  * Print board EEPROM configuration.
3115  */
3116 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
3117 {
3118 	struct asc_board *boardp = shost_priv(shost);
3119 	ADV_DVC_VAR *adv_dvc_varp;
3120 	int i;
3121 	char *termstr;
3122 	uchar serialstr[13];
3123 	ADVEEP_3550_CONFIG *ep_3550 = NULL;
3124 	ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3125 	ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3126 	ushort word;
3127 	ushort *wordp;
3128 	ushort sdtr_speed = 0;
3129 
3130 	adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3131 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3132 		ep_3550 = &boardp->eep_config.adv_3550_eep;
3133 	} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3134 		ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
3135 	} else {
3136 		ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
3137 	}
3138 
3139 	seq_printf(m,
3140 		   "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3141 		   shost->host_no);
3142 
3143 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3144 		wordp = &ep_3550->serial_number_word1;
3145 	} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3146 		wordp = &ep_38C0800->serial_number_word1;
3147 	} else {
3148 		wordp = &ep_38C1600->serial_number_word1;
3149 	}
3150 
3151 	if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3152 		seq_printf(m, " Serial Number: %s\n", serialstr);
3153 	else
3154 		seq_printf(m, " Serial Number Signature Not Present.\n");
3155 
3156 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3157 		seq_printf(m,
3158 			   " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3159 			   ep_3550->adapter_scsi_id,
3160 			   ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3161 	else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3162 		seq_printf(m,
3163 			   " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3164 			   ep_38C0800->adapter_scsi_id,
3165 			   ep_38C0800->max_host_qng,
3166 			   ep_38C0800->max_dvc_qng);
3167 	else
3168 		seq_printf(m,
3169 			   " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3170 			   ep_38C1600->adapter_scsi_id,
3171 			   ep_38C1600->max_host_qng,
3172 			   ep_38C1600->max_dvc_qng);
3173 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3174 		word = ep_3550->termination;
3175 	} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3176 		word = ep_38C0800->termination_lvd;
3177 	} else {
3178 		word = ep_38C1600->termination_lvd;
3179 	}
3180 	switch (word) {
3181 	case 1:
3182 		termstr = "Low Off/High Off";
3183 		break;
3184 	case 2:
3185 		termstr = "Low Off/High On";
3186 		break;
3187 	case 3:
3188 		termstr = "Low On/High On";
3189 		break;
3190 	default:
3191 	case 0:
3192 		termstr = "Automatic";
3193 		break;
3194 	}
3195 
3196 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3197 		seq_printf(m,
3198 			   " termination: %u (%s), bios_ctrl: 0x%x\n",
3199 			   ep_3550->termination, termstr,
3200 			   ep_3550->bios_ctrl);
3201 	else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3202 		seq_printf(m,
3203 			   " termination: %u (%s), bios_ctrl: 0x%x\n",
3204 			   ep_38C0800->termination_lvd, termstr,
3205 			   ep_38C0800->bios_ctrl);
3206 	else
3207 		seq_printf(m,
3208 			   " termination: %u (%s), bios_ctrl: 0x%x\n",
3209 			   ep_38C1600->termination_lvd, termstr,
3210 			   ep_38C1600->bios_ctrl);
3211 
3212 	seq_printf(m, " Target ID:           ");
3213 	for (i = 0; i <= ADV_MAX_TID; i++)
3214 		seq_printf(m, " %X", i);
3215 	seq_printf(m, "\n");
3216 
3217 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3218 		word = ep_3550->disc_enable;
3219 	} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3220 		word = ep_38C0800->disc_enable;
3221 	} else {
3222 		word = ep_38C1600->disc_enable;
3223 	}
3224 	seq_printf(m, " Disconnects:         ");
3225 	for (i = 0; i <= ADV_MAX_TID; i++)
3226 		seq_printf(m, " %c",
3227 			   (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3228 	seq_printf(m, "\n");
3229 
3230 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3231 		word = ep_3550->tagqng_able;
3232 	} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3233 		word = ep_38C0800->tagqng_able;
3234 	} else {
3235 		word = ep_38C1600->tagqng_able;
3236 	}
3237 	seq_printf(m, " Command Queuing:     ");
3238 	for (i = 0; i <= ADV_MAX_TID; i++)
3239 		seq_printf(m, " %c",
3240 			   (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3241 	seq_printf(m, "\n");
3242 
3243 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3244 		word = ep_3550->start_motor;
3245 	} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3246 		word = ep_38C0800->start_motor;
3247 	} else {
3248 		word = ep_38C1600->start_motor;
3249 	}
3250 	seq_printf(m, " Start Motor:         ");
3251 	for (i = 0; i <= ADV_MAX_TID; i++)
3252 		seq_printf(m, " %c",
3253 			   (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3254 	seq_printf(m, "\n");
3255 
3256 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3257 		seq_printf(m, " Synchronous Transfer:");
3258 		for (i = 0; i <= ADV_MAX_TID; i++)
3259 			seq_printf(m, " %c",
3260 				   (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3261 				   'Y' : 'N');
3262 		seq_printf(m, "\n");
3263 	}
3264 
3265 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3266 		seq_printf(m, " Ultra Transfer:      ");
3267 		for (i = 0; i <= ADV_MAX_TID; i++)
3268 			seq_printf(m, " %c",
3269 				   (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3270 				   ? 'Y' : 'N');
3271 		seq_printf(m, "\n");
3272 	}
3273 
3274 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3275 		word = ep_3550->wdtr_able;
3276 	} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3277 		word = ep_38C0800->wdtr_able;
3278 	} else {
3279 		word = ep_38C1600->wdtr_able;
3280 	}
3281 	seq_printf(m, " Wide Transfer:       ");
3282 	for (i = 0; i <= ADV_MAX_TID; i++)
3283 		seq_printf(m, " %c",
3284 			   (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3285 	seq_printf(m, "\n");
3286 
3287 	if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3288 	    adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3289 		seq_printf(m,
3290 			   " Synchronous Transfer Speed (Mhz):\n  ");
3291 		for (i = 0; i <= ADV_MAX_TID; i++) {
3292 			char *speed_str;
3293 
3294 			if (i == 0) {
3295 				sdtr_speed = adv_dvc_varp->sdtr_speed1;
3296 			} else if (i == 4) {
3297 				sdtr_speed = adv_dvc_varp->sdtr_speed2;
3298 			} else if (i == 8) {
3299 				sdtr_speed = adv_dvc_varp->sdtr_speed3;
3300 			} else if (i == 12) {
3301 				sdtr_speed = adv_dvc_varp->sdtr_speed4;
3302 			}
3303 			switch (sdtr_speed & ADV_MAX_TID) {
3304 			case 0:
3305 				speed_str = "Off";
3306 				break;
3307 			case 1:
3308 				speed_str = "  5";
3309 				break;
3310 			case 2:
3311 				speed_str = " 10";
3312 				break;
3313 			case 3:
3314 				speed_str = " 20";
3315 				break;
3316 			case 4:
3317 				speed_str = " 40";
3318 				break;
3319 			case 5:
3320 				speed_str = " 80";
3321 				break;
3322 			default:
3323 				speed_str = "Unk";
3324 				break;
3325 			}
3326 			seq_printf(m, "%X:%s ", i, speed_str);
3327 			if (i == 7)
3328 				seq_printf(m, "\n  ");
3329 			sdtr_speed >>= 4;
3330 		}
3331 		seq_printf(m, "\n");
3332 	}
3333 }
3334 
3335 /*
3336  * asc_prt_driver_conf()
3337  */
3338 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3339 {
3340 	struct asc_board *boardp = shost_priv(shost);
3341 	int chip_scsi_id;
3342 
3343 	seq_printf(m,
3344 		"\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3345 		shost->host_no);
3346 
3347 	seq_printf(m,
3348 		   " host_busy %u, last_reset %lu, max_id %u, max_lun %u, max_channel %u\n",
3349 		   shost->host_busy, shost->last_reset, shost->max_id,
3350 		   shost->max_lun, shost->max_channel);
3351 
3352 	seq_printf(m,
3353 		   " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3354 		   shost->unique_id, shost->can_queue, shost->this_id,
3355 		   shost->sg_tablesize, shost->cmd_per_lun);
3356 
3357 	seq_printf(m,
3358 		   " unchecked_isa_dma %d, use_clustering %d\n",
3359 		   shost->unchecked_isa_dma, shost->use_clustering);
3360 
3361 	seq_printf(m,
3362 		   " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3363 		   boardp->flags, boardp->last_reset, jiffies,
3364 		   boardp->asc_n_io_port);
3365 
3366 	seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3367 
3368 	if (ASC_NARROW_BOARD(boardp)) {
3369 		chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3370 	} else {
3371 		chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
3372 	}
3373 }
3374 
3375 /*
3376  * asc_prt_asc_board_info()
3377  *
3378  * Print dynamic board configuration information.
3379  */
3380 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3381 {
3382 	struct asc_board *boardp = shost_priv(shost);
3383 	int chip_scsi_id;
3384 	ASC_DVC_VAR *v;
3385 	ASC_DVC_CFG *c;
3386 	int i;
3387 	int renegotiate = 0;
3388 
3389 	v = &boardp->dvc_var.asc_dvc_var;
3390 	c = &boardp->dvc_cfg.asc_dvc_cfg;
3391 	chip_scsi_id = c->chip_scsi_id;
3392 
3393 	seq_printf(m,
3394 		   "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3395 		   shost->host_no);
3396 
3397 	seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3398 		   "mcode_version 0x%x, err_code %u\n",
3399 		   c->chip_version, c->mcode_date, c->mcode_version,
3400 		   v->err_code);
3401 
3402 	/* Current number of commands waiting for the host. */
3403 	seq_printf(m,
3404 		   " Total Command Pending: %d\n", v->cur_total_qng);
3405 
3406 	seq_printf(m, " Command Queuing:");
3407 	for (i = 0; i <= ASC_MAX_TID; i++) {
3408 		if ((chip_scsi_id == i) ||
3409 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3410 			continue;
3411 		}
3412 		seq_printf(m, " %X:%c",
3413 			   i,
3414 			   (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3415 	}
3416 	seq_printf(m, "\n");
3417 
3418 	/* Current number of commands waiting for a device. */
3419 	seq_printf(m, " Command Queue Pending:");
3420 	for (i = 0; i <= ASC_MAX_TID; i++) {
3421 		if ((chip_scsi_id == i) ||
3422 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3423 			continue;
3424 		}
3425 		seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3426 	}
3427 	seq_printf(m, "\n");
3428 
3429 	/* Current limit on number of commands that can be sent to a device. */
3430 	seq_printf(m, " Command Queue Limit:");
3431 	for (i = 0; i <= ASC_MAX_TID; i++) {
3432 		if ((chip_scsi_id == i) ||
3433 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3434 			continue;
3435 		}
3436 		seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3437 	}
3438 	seq_printf(m, "\n");
3439 
3440 	/* Indicate whether the device has returned queue full status. */
3441 	seq_printf(m, " Command Queue Full:");
3442 	for (i = 0; i <= ASC_MAX_TID; i++) {
3443 		if ((chip_scsi_id == i) ||
3444 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3445 			continue;
3446 		}
3447 		if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3448 			seq_printf(m, " %X:Y-%d",
3449 				   i, boardp->queue_full_cnt[i]);
3450 		else
3451 			seq_printf(m, " %X:N", i);
3452 	}
3453 	seq_printf(m, "\n");
3454 
3455 	seq_printf(m, " Synchronous Transfer:");
3456 	for (i = 0; i <= ASC_MAX_TID; i++) {
3457 		if ((chip_scsi_id == i) ||
3458 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3459 			continue;
3460 		}
3461 		seq_printf(m, " %X:%c",
3462 			   i,
3463 			   (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3464 	}
3465 	seq_printf(m, "\n");
3466 
3467 	for (i = 0; i <= ASC_MAX_TID; i++) {
3468 		uchar syn_period_ix;
3469 
3470 		if ((chip_scsi_id == i) ||
3471 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3472 		    ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3473 			continue;
3474 		}
3475 
3476 		seq_printf(m, "  %X:", i);
3477 
3478 		if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3479 			seq_printf(m, " Asynchronous");
3480 		} else {
3481 			syn_period_ix =
3482 			    (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3483 							   1);
3484 
3485 			seq_printf(m,
3486 				   " Transfer Period Factor: %d (%d.%d Mhz),",
3487 				   v->sdtr_period_tbl[syn_period_ix],
3488 				   250 / v->sdtr_period_tbl[syn_period_ix],
3489 				   ASC_TENTHS(250,
3490 					      v->sdtr_period_tbl[syn_period_ix]));
3491 
3492 			seq_printf(m, " REQ/ACK Offset: %d",
3493 				   boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3494 		}
3495 
3496 		if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3497 			seq_printf(m, "*\n");
3498 			renegotiate = 1;
3499 		} else {
3500 			seq_printf(m, "\n");
3501 		}
3502 	}
3503 
3504 	if (renegotiate) {
3505 		seq_printf(m,
3506 			   " * = Re-negotiation pending before next command.\n");
3507 	}
3508 }
3509 
3510 /*
3511  * asc_prt_adv_board_info()
3512  *
3513  * Print dynamic board configuration information.
3514  */
3515 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3516 {
3517 	struct asc_board *boardp = shost_priv(shost);
3518 	int i;
3519 	ADV_DVC_VAR *v;
3520 	ADV_DVC_CFG *c;
3521 	AdvPortAddr iop_base;
3522 	ushort chip_scsi_id;
3523 	ushort lramword;
3524 	uchar lrambyte;
3525 	ushort tagqng_able;
3526 	ushort sdtr_able, wdtr_able;
3527 	ushort wdtr_done, sdtr_done;
3528 	ushort period = 0;
3529 	int renegotiate = 0;
3530 
3531 	v = &boardp->dvc_var.adv_dvc_var;
3532 	c = &boardp->dvc_cfg.adv_dvc_cfg;
3533 	iop_base = v->iop_base;
3534 	chip_scsi_id = v->chip_scsi_id;
3535 
3536 	seq_printf(m,
3537 		   "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3538 		   shost->host_no);
3539 
3540 	seq_printf(m,
3541 		   " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3542 		   (unsigned long)v->iop_base,
3543 		   AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3544 		   v->err_code);
3545 
3546 	seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3547 		   "mcode_version 0x%x\n", c->chip_version,
3548 		   c->mcode_date, c->mcode_version);
3549 
3550 	AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3551 	seq_printf(m, " Queuing Enabled:");
3552 	for (i = 0; i <= ADV_MAX_TID; i++) {
3553 		if ((chip_scsi_id == i) ||
3554 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3555 			continue;
3556 		}
3557 
3558 		seq_printf(m, " %X:%c",
3559 			   i,
3560 			   (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3561 	}
3562 	seq_printf(m, "\n");
3563 
3564 	seq_printf(m, " Queue Limit:");
3565 	for (i = 0; i <= ADV_MAX_TID; i++) {
3566 		if ((chip_scsi_id == i) ||
3567 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3568 			continue;
3569 		}
3570 
3571 		AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3572 				lrambyte);
3573 
3574 		seq_printf(m, " %X:%d", i, lrambyte);
3575 	}
3576 	seq_printf(m, "\n");
3577 
3578 	seq_printf(m, " Command Pending:");
3579 	for (i = 0; i <= ADV_MAX_TID; i++) {
3580 		if ((chip_scsi_id == i) ||
3581 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3582 			continue;
3583 		}
3584 
3585 		AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3586 				lrambyte);
3587 
3588 		seq_printf(m, " %X:%d", i, lrambyte);
3589 	}
3590 	seq_printf(m, "\n");
3591 
3592 	AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3593 	seq_printf(m, " Wide Enabled:");
3594 	for (i = 0; i <= ADV_MAX_TID; i++) {
3595 		if ((chip_scsi_id == i) ||
3596 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3597 			continue;
3598 		}
3599 
3600 		seq_printf(m, " %X:%c",
3601 			   i,
3602 			   (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3603 	}
3604 	seq_printf(m, "\n");
3605 
3606 	AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3607 	seq_printf(m, " Transfer Bit Width:");
3608 	for (i = 0; i <= ADV_MAX_TID; i++) {
3609 		if ((chip_scsi_id == i) ||
3610 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3611 			continue;
3612 		}
3613 
3614 		AdvReadWordLram(iop_base,
3615 				ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3616 				lramword);
3617 
3618 		seq_printf(m, " %X:%d",
3619 			   i, (lramword & 0x8000) ? 16 : 8);
3620 
3621 		if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3622 		    (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3623 			seq_printf(m, "*");
3624 			renegotiate = 1;
3625 		}
3626 	}
3627 	seq_printf(m, "\n");
3628 
3629 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3630 	seq_printf(m, " Synchronous Enabled:");
3631 	for (i = 0; i <= ADV_MAX_TID; i++) {
3632 		if ((chip_scsi_id == i) ||
3633 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3634 			continue;
3635 		}
3636 
3637 		seq_printf(m, " %X:%c",
3638 			   i,
3639 			   (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3640 	}
3641 	seq_printf(m, "\n");
3642 
3643 	AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3644 	for (i = 0; i <= ADV_MAX_TID; i++) {
3645 
3646 		AdvReadWordLram(iop_base,
3647 				ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3648 				lramword);
3649 		lramword &= ~0x8000;
3650 
3651 		if ((chip_scsi_id == i) ||
3652 		    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3653 		    ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3654 			continue;
3655 		}
3656 
3657 		seq_printf(m, "  %X:", i);
3658 
3659 		if ((lramword & 0x1F) == 0) {	/* Check for REQ/ACK Offset 0. */
3660 			seq_printf(m, " Asynchronous");
3661 		} else {
3662 			seq_printf(m, " Transfer Period Factor: ");
3663 
3664 			if ((lramword & 0x1F00) == 0x1100) {	/* 80 Mhz */
3665 				seq_printf(m, "9 (80.0 Mhz),");
3666 			} else if ((lramword & 0x1F00) == 0x1000) {	/* 40 Mhz */
3667 				seq_printf(m, "10 (40.0 Mhz),");
3668 			} else {	/* 20 Mhz or below. */
3669 
3670 				period = (((lramword >> 8) * 25) + 50) / 4;
3671 
3672 				if (period == 0) {	/* Should never happen. */
3673 					seq_printf(m, "%d (? Mhz), ", period);
3674 				} else {
3675 					seq_printf(m,
3676 						   "%d (%d.%d Mhz),",
3677 						   period, 250 / period,
3678 						   ASC_TENTHS(250, period));
3679 				}
3680 			}
3681 
3682 			seq_printf(m, " REQ/ACK Offset: %d",
3683 				   lramword & 0x1F);
3684 		}
3685 
3686 		if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3687 			seq_printf(m, "*\n");
3688 			renegotiate = 1;
3689 		} else {
3690 			seq_printf(m, "\n");
3691 		}
3692 	}
3693 
3694 	if (renegotiate) {
3695 		seq_printf(m,
3696 			   " * = Re-negotiation pending before next command.\n");
3697 	}
3698 }
3699 
3700 #ifdef ADVANSYS_STATS
3701 /*
3702  * asc_prt_board_stats()
3703  */
3704 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3705 {
3706 	struct asc_board *boardp = shost_priv(shost);
3707 	struct asc_stats *s = &boardp->asc_stats;
3708 
3709 	seq_printf(m,
3710 		   "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3711 		   shost->host_no);
3712 
3713 	seq_printf(m,
3714 		   " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3715 		   s->queuecommand, s->reset, s->biosparam,
3716 		   s->interrupt);
3717 
3718 	seq_printf(m,
3719 		   " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3720 		   s->callback, s->done, s->build_error,
3721 		   s->adv_build_noreq, s->adv_build_nosg);
3722 
3723 	seq_printf(m,
3724 		   " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3725 		   s->exe_noerror, s->exe_busy, s->exe_error,
3726 		   s->exe_unknown);
3727 
3728 	/*
3729 	 * Display data transfer statistics.
3730 	 */
3731 	if (s->xfer_cnt > 0) {
3732 		seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3733 			   s->xfer_cnt, s->xfer_elem);
3734 
3735 		seq_printf(m, "xfer_bytes %u.%01u kb\n",
3736 			   s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3737 
3738 		/* Scatter gather transfer statistics */
3739 		seq_printf(m, " avg_num_elem %u.%01u, ",
3740 			   s->xfer_elem / s->xfer_cnt,
3741 			   ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3742 
3743 		seq_printf(m, "avg_elem_size %u.%01u kb, ",
3744 			   (s->xfer_sect / 2) / s->xfer_elem,
3745 			   ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3746 
3747 		seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3748 			   (s->xfer_sect / 2) / s->xfer_cnt,
3749 			   ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3750 	}
3751 }
3752 #endif /* ADVANSYS_STATS */
3753 
3754 /*
3755  * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3756  *
3757  * m: seq_file to print into
3758  * shost: Scsi_Host
3759  *
3760  * Return the number of bytes read from or written to a
3761  * /proc/scsi/advansys/[0...] file.
3762  */
3763 static int
3764 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3765 {
3766 	struct asc_board *boardp = shost_priv(shost);
3767 
3768 	ASC_DBG(1, "begin\n");
3769 
3770 	/*
3771 	 * User read of /proc/scsi/advansys/[0...] file.
3772 	 */
3773 
3774 	/*
3775 	 * Get board configuration information.
3776 	 *
3777 	 * advansys_info() returns the board string from its own static buffer.
3778 	 */
3779 	/* Copy board information. */
3780 	seq_printf(m, "%s\n", (char *)advansys_info(shost));
3781 	/*
3782 	 * Display Wide Board BIOS Information.
3783 	 */
3784 	if (!ASC_NARROW_BOARD(boardp))
3785 		asc_prt_adv_bios(m, shost);
3786 
3787 	/*
3788 	 * Display driver information for each device attached to the board.
3789 	 */
3790 	asc_prt_board_devices(m, shost);
3791 
3792 	/*
3793 	 * Display EEPROM configuration for the board.
3794 	 */
3795 	if (ASC_NARROW_BOARD(boardp))
3796 		asc_prt_asc_board_eeprom(m, shost);
3797 	else
3798 		asc_prt_adv_board_eeprom(m, shost);
3799 
3800 	/*
3801 	 * Display driver configuration and information for the board.
3802 	 */
3803 	asc_prt_driver_conf(m, shost);
3804 
3805 #ifdef ADVANSYS_STATS
3806 	/*
3807 	 * Display driver statistics for the board.
3808 	 */
3809 	asc_prt_board_stats(m, shost);
3810 #endif /* ADVANSYS_STATS */
3811 
3812 	/*
3813 	 * Display Asc Library dynamic configuration information
3814 	 * for the board.
3815 	 */
3816 	if (ASC_NARROW_BOARD(boardp))
3817 		asc_prt_asc_board_info(m, shost);
3818 	else
3819 		asc_prt_adv_board_info(m, shost);
3820 	return 0;
3821 }
3822 #endif /* CONFIG_PROC_FS */
3823 
3824 static void asc_scsi_done(struct scsi_cmnd *scp)
3825 {
3826 	scsi_dma_unmap(scp);
3827 	ASC_STATS(scp->device->host, done);
3828 	scp->scsi_done(scp);
3829 }
3830 
3831 static void AscSetBank(PortAddr iop_base, uchar bank)
3832 {
3833 	uchar val;
3834 
3835 	val = AscGetChipControl(iop_base) &
3836 	    (~
3837 	     (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3838 	      CC_CHIP_RESET));
3839 	if (bank == 1) {
3840 		val |= CC_BANK_ONE;
3841 	} else if (bank == 2) {
3842 		val |= CC_DIAG | CC_BANK_ONE;
3843 	} else {
3844 		val &= ~CC_BANK_ONE;
3845 	}
3846 	AscSetChipControl(iop_base, val);
3847 }
3848 
3849 static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3850 {
3851 	AscSetBank(iop_base, 1);
3852 	AscWriteChipIH(iop_base, ins_code);
3853 	AscSetBank(iop_base, 0);
3854 }
3855 
3856 static int AscStartChip(PortAddr iop_base)
3857 {
3858 	AscSetChipControl(iop_base, 0);
3859 	if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3860 		return (0);
3861 	}
3862 	return (1);
3863 }
3864 
3865 static int AscStopChip(PortAddr iop_base)
3866 {
3867 	uchar cc_val;
3868 
3869 	cc_val =
3870 	    AscGetChipControl(iop_base) &
3871 	    (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3872 	AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3873 	AscSetChipIH(iop_base, INS_HALT);
3874 	AscSetChipIH(iop_base, INS_RFLAG_WTM);
3875 	if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3876 		return (0);
3877 	}
3878 	return (1);
3879 }
3880 
3881 static int AscIsChipHalted(PortAddr iop_base)
3882 {
3883 	if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3884 		if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3885 			return (1);
3886 		}
3887 	}
3888 	return (0);
3889 }
3890 
3891 static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3892 {
3893 	PortAddr iop_base;
3894 	int i = 10;
3895 
3896 	iop_base = asc_dvc->iop_base;
3897 	while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3898 	       && (i-- > 0)) {
3899 		mdelay(100);
3900 	}
3901 	AscStopChip(iop_base);
3902 	AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3903 	udelay(60);
3904 	AscSetChipIH(iop_base, INS_RFLAG_WTM);
3905 	AscSetChipIH(iop_base, INS_HALT);
3906 	AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3907 	AscSetChipControl(iop_base, CC_HALT);
3908 	mdelay(200);
3909 	AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3910 	AscSetChipStatus(iop_base, 0);
3911 	return (AscIsChipHalted(iop_base));
3912 }
3913 
3914 static int AscFindSignature(PortAddr iop_base)
3915 {
3916 	ushort sig_word;
3917 
3918 	ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3919 		 iop_base, AscGetChipSignatureByte(iop_base));
3920 	if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3921 		ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3922 			 iop_base, AscGetChipSignatureWord(iop_base));
3923 		sig_word = AscGetChipSignatureWord(iop_base);
3924 		if ((sig_word == (ushort)ASC_1000_ID0W) ||
3925 		    (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3926 			return (1);
3927 		}
3928 	}
3929 	return (0);
3930 }
3931 
3932 static void AscEnableInterrupt(PortAddr iop_base)
3933 {
3934 	ushort cfg;
3935 
3936 	cfg = AscGetChipCfgLsw(iop_base);
3937 	AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3938 }
3939 
3940 static void AscDisableInterrupt(PortAddr iop_base)
3941 {
3942 	ushort cfg;
3943 
3944 	cfg = AscGetChipCfgLsw(iop_base);
3945 	AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3946 }
3947 
3948 static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3949 {
3950 	unsigned char byte_data;
3951 	unsigned short word_data;
3952 
3953 	if (isodd_word(addr)) {
3954 		AscSetChipLramAddr(iop_base, addr - 1);
3955 		word_data = AscGetChipLramData(iop_base);
3956 		byte_data = (word_data >> 8) & 0xFF;
3957 	} else {
3958 		AscSetChipLramAddr(iop_base, addr);
3959 		word_data = AscGetChipLramData(iop_base);
3960 		byte_data = word_data & 0xFF;
3961 	}
3962 	return byte_data;
3963 }
3964 
3965 static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3966 {
3967 	ushort word_data;
3968 
3969 	AscSetChipLramAddr(iop_base, addr);
3970 	word_data = AscGetChipLramData(iop_base);
3971 	return (word_data);
3972 }
3973 
3974 #if CC_VERY_LONG_SG_LIST
3975 static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
3976 {
3977 	ushort val_low, val_high;
3978 	ASC_DCNT dword_data;
3979 
3980 	AscSetChipLramAddr(iop_base, addr);
3981 	val_low = AscGetChipLramData(iop_base);
3982 	val_high = AscGetChipLramData(iop_base);
3983 	dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
3984 	return (dword_data);
3985 }
3986 #endif /* CC_VERY_LONG_SG_LIST */
3987 
3988 static void
3989 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3990 {
3991 	int i;
3992 
3993 	AscSetChipLramAddr(iop_base, s_addr);
3994 	for (i = 0; i < words; i++) {
3995 		AscSetChipLramData(iop_base, set_wval);
3996 	}
3997 }
3998 
3999 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
4000 {
4001 	AscSetChipLramAddr(iop_base, addr);
4002 	AscSetChipLramData(iop_base, word_val);
4003 }
4004 
4005 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4006 {
4007 	ushort word_data;
4008 
4009 	if (isodd_word(addr)) {
4010 		addr--;
4011 		word_data = AscReadLramWord(iop_base, addr);
4012 		word_data &= 0x00FF;
4013 		word_data |= (((ushort)byte_val << 8) & 0xFF00);
4014 	} else {
4015 		word_data = AscReadLramWord(iop_base, addr);
4016 		word_data &= 0xFF00;
4017 		word_data |= ((ushort)byte_val & 0x00FF);
4018 	}
4019 	AscWriteLramWord(iop_base, addr, word_data);
4020 }
4021 
4022 /*
4023  * Copy 2 bytes to LRAM.
4024  *
4025  * The source data is assumed to be in little-endian order in memory
4026  * and is maintained in little-endian order when written to LRAM.
4027  */
4028 static void
4029 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
4030 			const uchar *s_buffer, int words)
4031 {
4032 	int i;
4033 
4034 	AscSetChipLramAddr(iop_base, s_addr);
4035 	for (i = 0; i < 2 * words; i += 2) {
4036 		/*
4037 		 * On a little-endian system the second argument below
4038 		 * produces a little-endian ushort which is written to
4039 		 * LRAM in little-endian order. On a big-endian system
4040 		 * the second argument produces a big-endian ushort which
4041 		 * is "transparently" byte-swapped by outpw() and written
4042 		 * in little-endian order to LRAM.
4043 		 */
4044 		outpw(iop_base + IOP_RAM_DATA,
4045 		      ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4046 	}
4047 }
4048 
4049 /*
4050  * Copy 4 bytes to LRAM.
4051  *
4052  * The source data is assumed to be in little-endian order in memory
4053  * and is maintained in little-endian order when written to LRAM.
4054  */
4055 static void
4056 AscMemDWordCopyPtrToLram(PortAddr iop_base,
4057 			 ushort s_addr, uchar *s_buffer, int dwords)
4058 {
4059 	int i;
4060 
4061 	AscSetChipLramAddr(iop_base, s_addr);
4062 	for (i = 0; i < 4 * dwords; i += 4) {
4063 		outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);	/* LSW */
4064 		outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]);	/* MSW */
4065 	}
4066 }
4067 
4068 /*
4069  * Copy 2 bytes from LRAM.
4070  *
4071  * The source data is assumed to be in little-endian order in LRAM
4072  * and is maintained in little-endian order when written to memory.
4073  */
4074 static void
4075 AscMemWordCopyPtrFromLram(PortAddr iop_base,
4076 			  ushort s_addr, uchar *d_buffer, int words)
4077 {
4078 	int i;
4079 	ushort word;
4080 
4081 	AscSetChipLramAddr(iop_base, s_addr);
4082 	for (i = 0; i < 2 * words; i += 2) {
4083 		word = inpw(iop_base + IOP_RAM_DATA);
4084 		d_buffer[i] = word & 0xff;
4085 		d_buffer[i + 1] = (word >> 8) & 0xff;
4086 	}
4087 }
4088 
4089 static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4090 {
4091 	ASC_DCNT sum;
4092 	int i;
4093 
4094 	sum = 0L;
4095 	for (i = 0; i < words; i++, s_addr += 2) {
4096 		sum += AscReadLramWord(iop_base, s_addr);
4097 	}
4098 	return (sum);
4099 }
4100 
4101 static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4102 {
4103 	uchar i;
4104 	ushort s_addr;
4105 	PortAddr iop_base;
4106 	ushort warn_code;
4107 
4108 	iop_base = asc_dvc->iop_base;
4109 	warn_code = 0;
4110 	AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4111 			  (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4112 				    64) >> 1));
4113 	i = ASC_MIN_ACTIVE_QNO;
4114 	s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4115 	AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4116 			 (uchar)(i + 1));
4117 	AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4118 			 (uchar)(asc_dvc->max_total_qng));
4119 	AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4120 			 (uchar)i);
4121 	i++;
4122 	s_addr += ASC_QBLK_SIZE;
4123 	for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4124 		AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4125 				 (uchar)(i + 1));
4126 		AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4127 				 (uchar)(i - 1));
4128 		AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4129 				 (uchar)i);
4130 	}
4131 	AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4132 			 (uchar)ASC_QLINK_END);
4133 	AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4134 			 (uchar)(asc_dvc->max_total_qng - 1));
4135 	AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4136 			 (uchar)asc_dvc->max_total_qng);
4137 	i++;
4138 	s_addr += ASC_QBLK_SIZE;
4139 	for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4140 	     i++, s_addr += ASC_QBLK_SIZE) {
4141 		AscWriteLramByte(iop_base,
4142 				 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4143 		AscWriteLramByte(iop_base,
4144 				 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4145 		AscWriteLramByte(iop_base,
4146 				 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
4147 	}
4148 	return warn_code;
4149 }
4150 
4151 static ASC_DCNT
4152 AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4153 		 const uchar *mcode_buf, ushort mcode_size)
4154 {
4155 	ASC_DCNT chksum;
4156 	ushort mcode_word_size;
4157 	ushort mcode_chksum;
4158 
4159 	/* Write the microcode buffer starting at LRAM address 0. */
4160 	mcode_word_size = (ushort)(mcode_size >> 1);
4161 	AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4162 	AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
4163 
4164 	chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
4165 	ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
4166 	mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4167 						 (ushort)ASC_CODE_SEC_BEG,
4168 						 (ushort)((mcode_size -
4169 							   s_addr - (ushort)
4170 							   ASC_CODE_SEC_BEG) /
4171 							  2));
4172 	ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
4173 	AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4174 	AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
4175 	return chksum;
4176 }
4177 
4178 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4179 {
4180 	PortAddr iop_base;
4181 	int i;
4182 	ushort lram_addr;
4183 
4184 	iop_base = asc_dvc->iop_base;
4185 	AscPutRiscVarFreeQHead(iop_base, 1);
4186 	AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4187 	AscPutVarFreeQHead(iop_base, 1);
4188 	AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4189 	AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4190 			 (uchar)((int)asc_dvc->max_total_qng + 1));
4191 	AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4192 			 (uchar)((int)asc_dvc->max_total_qng + 2));
4193 	AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4194 			 asc_dvc->max_total_qng);
4195 	AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4196 	AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4197 	AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4198 	AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4199 	AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4200 	AscPutQDoneInProgress(iop_base, 0);
4201 	lram_addr = ASC_QADR_BEG;
4202 	for (i = 0; i < 32; i++, lram_addr += 2) {
4203 		AscWriteLramWord(iop_base, lram_addr, 0);
4204 	}
4205 }
4206 
4207 static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4208 {
4209 	int i;
4210 	ushort warn_code;
4211 	PortAddr iop_base;
4212 	ASC_PADDR phy_addr;
4213 	ASC_DCNT phy_size;
4214 	struct asc_board *board = asc_dvc_to_board(asc_dvc);
4215 
4216 	iop_base = asc_dvc->iop_base;
4217 	warn_code = 0;
4218 	for (i = 0; i <= ASC_MAX_TID; i++) {
4219 		AscPutMCodeInitSDTRAtID(iop_base, i,
4220 					asc_dvc->cfg->sdtr_period_offset[i]);
4221 	}
4222 
4223 	AscInitQLinkVar(asc_dvc);
4224 	AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4225 			 asc_dvc->cfg->disc_enable);
4226 	AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4227 			 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4228 
4229 	/* Ensure overrun buffer is aligned on an 8 byte boundary. */
4230 	BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4231 	asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4232 					ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4233 	if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4234 		warn_code = -ENOMEM;
4235 		goto err_dma_map;
4236 	}
4237 	phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
4238 	AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4239 				 (uchar *)&phy_addr, 1);
4240 	phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
4241 	AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4242 				 (uchar *)&phy_size, 1);
4243 
4244 	asc_dvc->cfg->mcode_date =
4245 	    AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4246 	asc_dvc->cfg->mcode_version =
4247 	    AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4248 
4249 	AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4250 	if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4251 		asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4252 		warn_code = UW_ERR;
4253 		goto err_mcode_start;
4254 	}
4255 	if (AscStartChip(iop_base) != 1) {
4256 		asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4257 		warn_code = UW_ERR;
4258 		goto err_mcode_start;
4259 	}
4260 
4261 	return warn_code;
4262 
4263 err_mcode_start:
4264 	dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4265 			 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4266 err_dma_map:
4267 	asc_dvc->overrun_dma = 0;
4268 	return warn_code;
4269 }
4270 
4271 static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4272 {
4273 	const struct firmware *fw;
4274 	const char fwname[] = "advansys/mcode.bin";
4275 	int err;
4276 	unsigned long chksum;
4277 	ushort warn_code;
4278 	PortAddr iop_base;
4279 
4280 	iop_base = asc_dvc->iop_base;
4281 	warn_code = 0;
4282 	if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4283 	    !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4284 		AscResetChipAndScsiBus(asc_dvc);
4285 		mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4286 	}
4287 	asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4288 	if (asc_dvc->err_code != 0)
4289 		return UW_ERR;
4290 	if (!AscFindSignature(asc_dvc->iop_base)) {
4291 		asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4292 		return warn_code;
4293 	}
4294 	AscDisableInterrupt(iop_base);
4295 	warn_code |= AscInitLram(asc_dvc);
4296 	if (asc_dvc->err_code != 0)
4297 		return UW_ERR;
4298 
4299 	err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4300 	if (err) {
4301 		printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4302 		       fwname, err);
4303 		asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4304 		return err;
4305 	}
4306 	if (fw->size < 4) {
4307 		printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4308 		       fw->size, fwname);
4309 		release_firmware(fw);
4310 		asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4311 		return -EINVAL;
4312 	}
4313 	chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4314 		 (fw->data[1] << 8) | fw->data[0];
4315 	ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4316 	if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4317 			     fw->size - 4) != chksum) {
4318 		asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4319 		release_firmware(fw);
4320 		return warn_code;
4321 	}
4322 	release_firmware(fw);
4323 	warn_code |= AscInitMicroCodeVar(asc_dvc);
4324 	if (!asc_dvc->overrun_dma)
4325 		return warn_code;
4326 	asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4327 	AscEnableInterrupt(iop_base);
4328 	return warn_code;
4329 }
4330 
4331 /*
4332  * Load the Microcode
4333  *
4334  * Write the microcode image to RISC memory starting at address 0.
4335  *
4336  * The microcode is stored compressed in the following format:
4337  *
4338  *  254 word (508 byte) table indexed by byte code followed
4339  *  by the following byte codes:
4340  *
4341  *    1-Byte Code:
4342  *      00: Emit word 0 in table.
4343  *      01: Emit word 1 in table.
4344  *      .
4345  *      FD: Emit word 253 in table.
4346  *
4347  *    Multi-Byte Code:
4348  *      FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4349  *      FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4350  *
4351  * Returns 0 or an error if the checksum doesn't match
4352  */
4353 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4354 			    int size, int memsize, int chksum)
4355 {
4356 	int i, j, end, len = 0;
4357 	ADV_DCNT sum;
4358 
4359 	AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4360 
4361 	for (i = 253 * 2; i < size; i++) {
4362 		if (buf[i] == 0xff) {
4363 			unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4364 			for (j = 0; j < buf[i + 1]; j++) {
4365 				AdvWriteWordAutoIncLram(iop_base, word);
4366 				len += 2;
4367 			}
4368 			i += 3;
4369 		} else if (buf[i] == 0xfe) {
4370 			unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4371 			AdvWriteWordAutoIncLram(iop_base, word);
4372 			i += 2;
4373 			len += 2;
4374 		} else {
4375 			unsigned int off = buf[i] * 2;
4376 			unsigned short word = (buf[off + 1] << 8) | buf[off];
4377 			AdvWriteWordAutoIncLram(iop_base, word);
4378 			len += 2;
4379 		}
4380 	}
4381 
4382 	end = len;
4383 
4384 	while (len < memsize) {
4385 		AdvWriteWordAutoIncLram(iop_base, 0);
4386 		len += 2;
4387 	}
4388 
4389 	/* Verify the microcode checksum. */
4390 	sum = 0;
4391 	AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4392 
4393 	for (len = 0; len < end; len += 2) {
4394 		sum += AdvReadWordAutoIncLram(iop_base);
4395 	}
4396 
4397 	if (sum != chksum)
4398 		return ASC_IERR_MCODE_CHKSUM;
4399 
4400 	return 0;
4401 }
4402 
4403 static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
4404 {
4405 	ADV_CARR_T *carrp;
4406 	ADV_SDCNT buf_size;
4407 	ADV_PADDR carr_paddr;
4408 
4409 	carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
4410 	asc_dvc->carr_freelist = NULL;
4411 	if (carrp == asc_dvc->carrier_buf) {
4412 		buf_size = ADV_CARRIER_BUFSIZE;
4413 	} else {
4414 		buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
4415 	}
4416 
4417 	do {
4418 		/* Get physical address of the carrier 'carrp'. */
4419 		carr_paddr = cpu_to_le32(virt_to_bus(carrp));
4420 
4421 		buf_size -= sizeof(ADV_CARR_T);
4422 
4423 		carrp->carr_pa = carr_paddr;
4424 		carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
4425 
4426 		/*
4427 		 * Insert the carrier at the beginning of the freelist.
4428 		 */
4429 		carrp->next_vpa =
4430 			cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
4431 		asc_dvc->carr_freelist = carrp;
4432 
4433 		carrp++;
4434 	} while (buf_size > 0);
4435 }
4436 
4437 /*
4438  * Send an idle command to the chip and wait for completion.
4439  *
4440  * Command completion is polled for once per microsecond.
4441  *
4442  * The function can be called from anywhere including an interrupt handler.
4443  * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4444  * functions to prevent reentrancy.
4445  *
4446  * Return Values:
4447  *   ADV_TRUE - command completed successfully
4448  *   ADV_FALSE - command failed
4449  *   ADV_ERROR - command timed out
4450  */
4451 static int
4452 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4453 	       ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4454 {
4455 	int result;
4456 	ADV_DCNT i, j;
4457 	AdvPortAddr iop_base;
4458 
4459 	iop_base = asc_dvc->iop_base;
4460 
4461 	/*
4462 	 * Clear the idle command status which is set by the microcode
4463 	 * to a non-zero value to indicate when the command is completed.
4464 	 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4465 	 */
4466 	AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4467 
4468 	/*
4469 	 * Write the idle command value after the idle command parameter
4470 	 * has been written to avoid a race condition. If the order is not
4471 	 * followed, the microcode may process the idle command before the
4472 	 * parameters have been written to LRAM.
4473 	 */
4474 	AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4475 				cpu_to_le32(idle_cmd_parameter));
4476 	AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4477 
4478 	/*
4479 	 * Tickle the RISC to tell it to process the idle command.
4480 	 */
4481 	AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4482 	if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4483 		/*
4484 		 * Clear the tickle value. In the ASC-3550 the RISC flag
4485 		 * command 'clr_tickle_b' does not work unless the host
4486 		 * value is cleared.
4487 		 */
4488 		AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4489 	}
4490 
4491 	/* Wait for up to 100 millisecond for the idle command to timeout. */
4492 	for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4493 		/* Poll once each microsecond for command completion. */
4494 		for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4495 			AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4496 					result);
4497 			if (result != 0)
4498 				return result;
4499 			udelay(1);
4500 		}
4501 	}
4502 
4503 	BUG();		/* The idle command should never timeout. */
4504 	return ADV_ERROR;
4505 }
4506 
4507 /*
4508  * Reset SCSI Bus and purge all outstanding requests.
4509  *
4510  * Return Value:
4511  *      ADV_TRUE(1) -   All requests are purged and SCSI Bus is reset.
4512  *      ADV_FALSE(0) -  Microcode command failed.
4513  *      ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4514  *                      may be hung which requires driver recovery.
4515  */
4516 static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4517 {
4518 	int status;
4519 
4520 	/*
4521 	 * Send the SCSI Bus Reset idle start idle command which asserts
4522 	 * the SCSI Bus Reset signal.
4523 	 */
4524 	status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4525 	if (status != ADV_TRUE) {
4526 		return status;
4527 	}
4528 
4529 	/*
4530 	 * Delay for the specified SCSI Bus Reset hold time.
4531 	 *
4532 	 * The hold time delay is done on the host because the RISC has no
4533 	 * microsecond accurate timer.
4534 	 */
4535 	udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4536 
4537 	/*
4538 	 * Send the SCSI Bus Reset end idle command which de-asserts
4539 	 * the SCSI Bus Reset signal and purges any pending requests.
4540 	 */
4541 	status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4542 	if (status != ADV_TRUE) {
4543 		return status;
4544 	}
4545 
4546 	mdelay(asc_dvc->scsi_reset_wait * 1000);	/* XXX: msleep? */
4547 
4548 	return status;
4549 }
4550 
4551 /*
4552  * Initialize the ASC-3550.
4553  *
4554  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4555  *
4556  * For a non-fatal error return a warning code. If there are no warnings
4557  * then 0 is returned.
4558  *
4559  * Needed after initialization for error recovery.
4560  */
4561 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4562 {
4563 	const struct firmware *fw;
4564 	const char fwname[] = "advansys/3550.bin";
4565 	AdvPortAddr iop_base;
4566 	ushort warn_code;
4567 	int begin_addr;
4568 	int end_addr;
4569 	ushort code_sum;
4570 	int word;
4571 	int i;
4572 	int err;
4573 	unsigned long chksum;
4574 	ushort scsi_cfg1;
4575 	uchar tid;
4576 	ushort bios_mem[ASC_MC_BIOSLEN / 2];	/* BIOS RISC Memory 0x40-0x8F. */
4577 	ushort wdtr_able = 0, sdtr_able, tagqng_able;
4578 	uchar max_cmd[ADV_MAX_TID + 1];
4579 
4580 	/* If there is already an error, don't continue. */
4581 	if (asc_dvc->err_code != 0)
4582 		return ADV_ERROR;
4583 
4584 	/*
4585 	 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4586 	 */
4587 	if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4588 		asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4589 		return ADV_ERROR;
4590 	}
4591 
4592 	warn_code = 0;
4593 	iop_base = asc_dvc->iop_base;
4594 
4595 	/*
4596 	 * Save the RISC memory BIOS region before writing the microcode.
4597 	 * The BIOS may already be loaded and using its RISC LRAM region
4598 	 * so its region must be saved and restored.
4599 	 *
4600 	 * Note: This code makes the assumption, which is currently true,
4601 	 * that a chip reset does not clear RISC LRAM.
4602 	 */
4603 	for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4604 		AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4605 				bios_mem[i]);
4606 	}
4607 
4608 	/*
4609 	 * Save current per TID negotiated values.
4610 	 */
4611 	if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4612 		ushort bios_version, major, minor;
4613 
4614 		bios_version =
4615 		    bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4616 		major = (bios_version >> 12) & 0xF;
4617 		minor = (bios_version >> 8) & 0xF;
4618 		if (major < 3 || (major == 3 && minor == 1)) {
4619 			/* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4620 			AdvReadWordLram(iop_base, 0x120, wdtr_able);
4621 		} else {
4622 			AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4623 		}
4624 	}
4625 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4626 	AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4627 	for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4628 		AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4629 				max_cmd[tid]);
4630 	}
4631 
4632 	err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4633 	if (err) {
4634 		printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4635 		       fwname, err);
4636 		asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4637 		return err;
4638 	}
4639 	if (fw->size < 4) {
4640 		printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4641 		       fw->size, fwname);
4642 		release_firmware(fw);
4643 		asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
4644 		return -EINVAL;
4645 	}
4646 	chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4647 		 (fw->data[1] << 8) | fw->data[0];
4648 	asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4649 					     fw->size - 4, ADV_3550_MEMSIZE,
4650 					     chksum);
4651 	release_firmware(fw);
4652 	if (asc_dvc->err_code)
4653 		return ADV_ERROR;
4654 
4655 	/*
4656 	 * Restore the RISC memory BIOS region.
4657 	 */
4658 	for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4659 		AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4660 				 bios_mem[i]);
4661 	}
4662 
4663 	/*
4664 	 * Calculate and write the microcode code checksum to the microcode
4665 	 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4666 	 */
4667 	AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4668 	AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4669 	code_sum = 0;
4670 	AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4671 	for (word = begin_addr; word < end_addr; word += 2) {
4672 		code_sum += AdvReadWordAutoIncLram(iop_base);
4673 	}
4674 	AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4675 
4676 	/*
4677 	 * Read and save microcode version and date.
4678 	 */
4679 	AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4680 			asc_dvc->cfg->mcode_date);
4681 	AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4682 			asc_dvc->cfg->mcode_version);
4683 
4684 	/*
4685 	 * Set the chip type to indicate the ASC3550.
4686 	 */
4687 	AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4688 
4689 	/*
4690 	 * If the PCI Configuration Command Register "Parity Error Response
4691 	 * Control" Bit was clear (0), then set the microcode variable
4692 	 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4693 	 * to ignore DMA parity errors.
4694 	 */
4695 	if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4696 		AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4697 		word |= CONTROL_FLAG_IGNORE_PERR;
4698 		AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4699 	}
4700 
4701 	/*
4702 	 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4703 	 * threshold of 128 bytes. This register is only accessible to the host.
4704 	 */
4705 	AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4706 			     START_CTL_EMFU | READ_CMD_MRM);
4707 
4708 	/*
4709 	 * Microcode operating variables for WDTR, SDTR, and command tag
4710 	 * queuing will be set in slave_configure() based on what a
4711 	 * device reports it is capable of in Inquiry byte 7.
4712 	 *
4713 	 * If SCSI Bus Resets have been disabled, then directly set
4714 	 * SDTR and WDTR from the EEPROM configuration. This will allow
4715 	 * the BIOS and warm boot to work without a SCSI bus hang on
4716 	 * the Inquiry caused by host and target mismatched DTR values.
4717 	 * Without the SCSI Bus Reset, before an Inquiry a device can't
4718 	 * be assumed to be in Asynchronous, Narrow mode.
4719 	 */
4720 	if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4721 		AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4722 				 asc_dvc->wdtr_able);
4723 		AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4724 				 asc_dvc->sdtr_able);
4725 	}
4726 
4727 	/*
4728 	 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4729 	 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4730 	 * bitmask. These values determine the maximum SDTR speed negotiated
4731 	 * with a device.
4732 	 *
4733 	 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4734 	 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4735 	 * without determining here whether the device supports SDTR.
4736 	 *
4737 	 * 4-bit speed  SDTR speed name
4738 	 * ===========  ===============
4739 	 * 0000b (0x0)  SDTR disabled
4740 	 * 0001b (0x1)  5 Mhz
4741 	 * 0010b (0x2)  10 Mhz
4742 	 * 0011b (0x3)  20 Mhz (Ultra)
4743 	 * 0100b (0x4)  40 Mhz (LVD/Ultra2)
4744 	 * 0101b (0x5)  80 Mhz (LVD2/Ultra3)
4745 	 * 0110b (0x6)  Undefined
4746 	 * .
4747 	 * 1111b (0xF)  Undefined
4748 	 */
4749 	word = 0;
4750 	for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4751 		if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4752 			/* Set Ultra speed for TID 'tid'. */
4753 			word |= (0x3 << (4 * (tid % 4)));
4754 		} else {
4755 			/* Set Fast speed for TID 'tid'. */
4756 			word |= (0x2 << (4 * (tid % 4)));
4757 		}
4758 		if (tid == 3) {	/* Check if done with sdtr_speed1. */
4759 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4760 			word = 0;
4761 		} else if (tid == 7) {	/* Check if done with sdtr_speed2. */
4762 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4763 			word = 0;
4764 		} else if (tid == 11) {	/* Check if done with sdtr_speed3. */
4765 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4766 			word = 0;
4767 		} else if (tid == 15) {	/* Check if done with sdtr_speed4. */
4768 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4769 			/* End of loop. */
4770 		}
4771 	}
4772 
4773 	/*
4774 	 * Set microcode operating variable for the disconnect per TID bitmask.
4775 	 */
4776 	AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4777 			 asc_dvc->cfg->disc_enable);
4778 
4779 	/*
4780 	 * Set SCSI_CFG0 Microcode Default Value.
4781 	 *
4782 	 * The microcode will set the SCSI_CFG0 register using this value
4783 	 * after it is started below.
4784 	 */
4785 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4786 			 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4787 			 asc_dvc->chip_scsi_id);
4788 
4789 	/*
4790 	 * Determine SCSI_CFG1 Microcode Default Value.
4791 	 *
4792 	 * The microcode will set the SCSI_CFG1 register using this value
4793 	 * after it is started below.
4794 	 */
4795 
4796 	/* Read current SCSI_CFG1 Register value. */
4797 	scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4798 
4799 	/*
4800 	 * If all three connectors are in use, return an error.
4801 	 */
4802 	if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4803 	    (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4804 		asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4805 		return ADV_ERROR;
4806 	}
4807 
4808 	/*
4809 	 * If the internal narrow cable is reversed all of the SCSI_CTRL
4810 	 * register signals will be set. Check for and return an error if
4811 	 * this condition is found.
4812 	 */
4813 	if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4814 		asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4815 		return ADV_ERROR;
4816 	}
4817 
4818 	/*
4819 	 * If this is a differential board and a single-ended device
4820 	 * is attached to one of the connectors, return an error.
4821 	 */
4822 	if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4823 		asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4824 		return ADV_ERROR;
4825 	}
4826 
4827 	/*
4828 	 * If automatic termination control is enabled, then set the
4829 	 * termination value based on a table listed in a_condor.h.
4830 	 *
4831 	 * If manual termination was specified with an EEPROM setting
4832 	 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4833 	 * is ready to be 'ored' into SCSI_CFG1.
4834 	 */
4835 	if (asc_dvc->cfg->termination == 0) {
4836 		/*
4837 		 * The software always controls termination by setting TERM_CTL_SEL.
4838 		 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4839 		 */
4840 		asc_dvc->cfg->termination |= TERM_CTL_SEL;
4841 
4842 		switch (scsi_cfg1 & CABLE_DETECT) {
4843 			/* TERM_CTL_H: on, TERM_CTL_L: on */
4844 		case 0x3:
4845 		case 0x7:
4846 		case 0xB:
4847 		case 0xD:
4848 		case 0xE:
4849 		case 0xF:
4850 			asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4851 			break;
4852 
4853 			/* TERM_CTL_H: on, TERM_CTL_L: off */
4854 		case 0x1:
4855 		case 0x5:
4856 		case 0x9:
4857 		case 0xA:
4858 		case 0xC:
4859 			asc_dvc->cfg->termination |= TERM_CTL_H;
4860 			break;
4861 
4862 			/* TERM_CTL_H: off, TERM_CTL_L: off */
4863 		case 0x2:
4864 		case 0x6:
4865 			break;
4866 		}
4867 	}
4868 
4869 	/*
4870 	 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4871 	 */
4872 	scsi_cfg1 &= ~TERM_CTL;
4873 
4874 	/*
4875 	 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4876 	 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4877 	 * referenced, because the hardware internally inverts
4878 	 * the Termination High and Low bits if TERM_POL is set.
4879 	 */
4880 	scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4881 
4882 	/*
4883 	 * Set SCSI_CFG1 Microcode Default Value
4884 	 *
4885 	 * Set filter value and possibly modified termination control
4886 	 * bits in the Microcode SCSI_CFG1 Register Value.
4887 	 *
4888 	 * The microcode will set the SCSI_CFG1 register using this value
4889 	 * after it is started below.
4890 	 */
4891 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4892 			 FLTR_DISABLE | scsi_cfg1);
4893 
4894 	/*
4895 	 * Set MEM_CFG Microcode Default Value
4896 	 *
4897 	 * The microcode will set the MEM_CFG register using this value
4898 	 * after it is started below.
4899 	 *
4900 	 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4901 	 * are defined.
4902 	 *
4903 	 * ASC-3550 has 8KB internal memory.
4904 	 */
4905 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4906 			 BIOS_EN | RAM_SZ_8KB);
4907 
4908 	/*
4909 	 * Set SEL_MASK Microcode Default Value
4910 	 *
4911 	 * The microcode will set the SEL_MASK register using this value
4912 	 * after it is started below.
4913 	 */
4914 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4915 			 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4916 
4917 	AdvBuildCarrierFreelist(asc_dvc);
4918 
4919 	/*
4920 	 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4921 	 */
4922 
4923 	if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
4924 		asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4925 		return ADV_ERROR;
4926 	}
4927 	asc_dvc->carr_freelist = (ADV_CARR_T *)
4928 	    ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
4929 
4930 	/*
4931 	 * The first command issued will be placed in the stopper carrier.
4932 	 */
4933 	asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4934 
4935 	/*
4936 	 * Set RISC ICQ physical address start value.
4937 	 */
4938 	AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4939 
4940 	/*
4941 	 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4942 	 */
4943 	if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
4944 		asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4945 		return ADV_ERROR;
4946 	}
4947 	asc_dvc->carr_freelist = (ADV_CARR_T *)
4948 	    ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
4949 
4950 	/*
4951 	 * The first command completed by the RISC will be placed in
4952 	 * the stopper.
4953 	 *
4954 	 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
4955 	 * completed the RISC will set the ASC_RQ_STOPPER bit.
4956 	 */
4957 	asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4958 
4959 	/*
4960 	 * Set RISC IRQ physical address start value.
4961 	 */
4962 	AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4963 	asc_dvc->carr_pending_cnt = 0;
4964 
4965 	AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4966 			     (ADV_INTR_ENABLE_HOST_INTR |
4967 			      ADV_INTR_ENABLE_GLOBAL_INTR));
4968 
4969 	AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4970 	AdvWriteWordRegister(iop_base, IOPW_PC, word);
4971 
4972 	/* finally, finally, gentlemen, start your engine */
4973 	AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4974 
4975 	/*
4976 	 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4977 	 * Resets should be performed. The RISC has to be running
4978 	 * to issue a SCSI Bus Reset.
4979 	 */
4980 	if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4981 		/*
4982 		 * If the BIOS Signature is present in memory, restore the
4983 		 * BIOS Handshake Configuration Table and do not perform
4984 		 * a SCSI Bus Reset.
4985 		 */
4986 		if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4987 		    0x55AA) {
4988 			/*
4989 			 * Restore per TID negotiated values.
4990 			 */
4991 			AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4992 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4993 			AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4994 					 tagqng_able);
4995 			for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4996 				AdvWriteByteLram(iop_base,
4997 						 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4998 						 max_cmd[tid]);
4999 			}
5000 		} else {
5001 			if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5002 				warn_code = ASC_WARN_BUSRESET_ERROR;
5003 			}
5004 		}
5005 	}
5006 
5007 	return warn_code;
5008 }
5009 
5010 /*
5011  * Initialize the ASC-38C0800.
5012  *
5013  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
5014  *
5015  * For a non-fatal error return a warning code. If there are no warnings
5016  * then 0 is returned.
5017  *
5018  * Needed after initialization for error recovery.
5019  */
5020 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
5021 {
5022 	const struct firmware *fw;
5023 	const char fwname[] = "advansys/38C0800.bin";
5024 	AdvPortAddr iop_base;
5025 	ushort warn_code;
5026 	int begin_addr;
5027 	int end_addr;
5028 	ushort code_sum;
5029 	int word;
5030 	int i;
5031 	int err;
5032 	unsigned long chksum;
5033 	ushort scsi_cfg1;
5034 	uchar byte;
5035 	uchar tid;
5036 	ushort bios_mem[ASC_MC_BIOSLEN / 2];	/* BIOS RISC Memory 0x40-0x8F. */
5037 	ushort wdtr_able, sdtr_able, tagqng_able;
5038 	uchar max_cmd[ADV_MAX_TID + 1];
5039 
5040 	/* If there is already an error, don't continue. */
5041 	if (asc_dvc->err_code != 0)
5042 		return ADV_ERROR;
5043 
5044 	/*
5045 	 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
5046 	 */
5047 	if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
5048 		asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5049 		return ADV_ERROR;
5050 	}
5051 
5052 	warn_code = 0;
5053 	iop_base = asc_dvc->iop_base;
5054 
5055 	/*
5056 	 * Save the RISC memory BIOS region before writing the microcode.
5057 	 * The BIOS may already be loaded and using its RISC LRAM region
5058 	 * so its region must be saved and restored.
5059 	 *
5060 	 * Note: This code makes the assumption, which is currently true,
5061 	 * that a chip reset does not clear RISC LRAM.
5062 	 */
5063 	for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5064 		AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5065 				bios_mem[i]);
5066 	}
5067 
5068 	/*
5069 	 * Save current per TID negotiated values.
5070 	 */
5071 	AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5072 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5073 	AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5074 	for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5075 		AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5076 				max_cmd[tid]);
5077 	}
5078 
5079 	/*
5080 	 * RAM BIST (RAM Built-In Self Test)
5081 	 *
5082 	 * Address : I/O base + offset 0x38h register (byte).
5083 	 * Function: Bit 7-6(RW) : RAM mode
5084 	 *                          Normal Mode   : 0x00
5085 	 *                          Pre-test Mode : 0x40
5086 	 *                          RAM Test Mode : 0x80
5087 	 *           Bit 5       : unused
5088 	 *           Bit 4(RO)   : Done bit
5089 	 *           Bit 3-0(RO) : Status
5090 	 *                          Host Error    : 0x08
5091 	 *                          Int_RAM Error : 0x04
5092 	 *                          RISC Error    : 0x02
5093 	 *                          SCSI Error    : 0x01
5094 	 *                          No Error      : 0x00
5095 	 *
5096 	 * Note: RAM BIST code should be put right here, before loading the
5097 	 * microcode and after saving the RISC memory BIOS region.
5098 	 */
5099 
5100 	/*
5101 	 * LRAM Pre-test
5102 	 *
5103 	 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5104 	 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5105 	 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5106 	 * to NORMAL_MODE, return an error too.
5107 	 */
5108 	for (i = 0; i < 2; i++) {
5109 		AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5110 		mdelay(10);	/* Wait for 10ms before reading back. */
5111 		byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5112 		if ((byte & RAM_TEST_DONE) == 0
5113 		    || (byte & 0x0F) != PRE_TEST_VALUE) {
5114 			asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5115 			return ADV_ERROR;
5116 		}
5117 
5118 		AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5119 		mdelay(10);	/* Wait for 10ms before reading back. */
5120 		if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5121 		    != NORMAL_VALUE) {
5122 			asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5123 			return ADV_ERROR;
5124 		}
5125 	}
5126 
5127 	/*
5128 	 * LRAM Test - It takes about 1.5 ms to run through the test.
5129 	 *
5130 	 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5131 	 * If Done bit not set or Status not 0, save register byte, set the
5132 	 * err_code, and return an error.
5133 	 */
5134 	AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5135 	mdelay(10);	/* Wait for 10ms before checking status. */
5136 
5137 	byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5138 	if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5139 		/* Get here if Done bit not set or Status not 0. */
5140 		asc_dvc->bist_err_code = byte;	/* for BIOS display message */
5141 		asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5142 		return ADV_ERROR;
5143 	}
5144 
5145 	/* We need to reset back to normal mode after LRAM test passes. */
5146 	AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5147 
5148 	err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5149 	if (err) {
5150 		printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5151 		       fwname, err);
5152 		asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5153 		return err;
5154 	}
5155 	if (fw->size < 4) {
5156 		printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5157 		       fw->size, fwname);
5158 		release_firmware(fw);
5159 		asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5160 		return -EINVAL;
5161 	}
5162 	chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5163 		 (fw->data[1] << 8) | fw->data[0];
5164 	asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5165 					     fw->size - 4, ADV_38C0800_MEMSIZE,
5166 					     chksum);
5167 	release_firmware(fw);
5168 	if (asc_dvc->err_code)
5169 		return ADV_ERROR;
5170 
5171 	/*
5172 	 * Restore the RISC memory BIOS region.
5173 	 */
5174 	for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5175 		AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5176 				 bios_mem[i]);
5177 	}
5178 
5179 	/*
5180 	 * Calculate and write the microcode code checksum to the microcode
5181 	 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5182 	 */
5183 	AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5184 	AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5185 	code_sum = 0;
5186 	AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5187 	for (word = begin_addr; word < end_addr; word += 2) {
5188 		code_sum += AdvReadWordAutoIncLram(iop_base);
5189 	}
5190 	AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5191 
5192 	/*
5193 	 * Read microcode version and date.
5194 	 */
5195 	AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5196 			asc_dvc->cfg->mcode_date);
5197 	AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5198 			asc_dvc->cfg->mcode_version);
5199 
5200 	/*
5201 	 * Set the chip type to indicate the ASC38C0800.
5202 	 */
5203 	AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5204 
5205 	/*
5206 	 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5207 	 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5208 	 * cable detection and then we are able to read C_DET[3:0].
5209 	 *
5210 	 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5211 	 * Microcode Default Value' section below.
5212 	 */
5213 	scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5214 	AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5215 			     scsi_cfg1 | DIS_TERM_DRV);
5216 
5217 	/*
5218 	 * If the PCI Configuration Command Register "Parity Error Response
5219 	 * Control" Bit was clear (0), then set the microcode variable
5220 	 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5221 	 * to ignore DMA parity errors.
5222 	 */
5223 	if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5224 		AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5225 		word |= CONTROL_FLAG_IGNORE_PERR;
5226 		AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5227 	}
5228 
5229 	/*
5230 	 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5231 	 * bits for the default FIFO threshold.
5232 	 *
5233 	 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5234 	 *
5235 	 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5236 	 */
5237 	AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5238 			     BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5239 			     READ_CMD_MRM);
5240 
5241 	/*
5242 	 * Microcode operating variables for WDTR, SDTR, and command tag
5243 	 * queuing will be set in slave_configure() based on what a
5244 	 * device reports it is capable of in Inquiry byte 7.
5245 	 *
5246 	 * If SCSI Bus Resets have been disabled, then directly set
5247 	 * SDTR and WDTR from the EEPROM configuration. This will allow
5248 	 * the BIOS and warm boot to work without a SCSI bus hang on
5249 	 * the Inquiry caused by host and target mismatched DTR values.
5250 	 * Without the SCSI Bus Reset, before an Inquiry a device can't
5251 	 * be assumed to be in Asynchronous, Narrow mode.
5252 	 */
5253 	if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5254 		AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5255 				 asc_dvc->wdtr_able);
5256 		AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5257 				 asc_dvc->sdtr_able);
5258 	}
5259 
5260 	/*
5261 	 * Set microcode operating variables for DISC and SDTR_SPEED1,
5262 	 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5263 	 * configuration values.
5264 	 *
5265 	 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5266 	 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5267 	 * without determining here whether the device supports SDTR.
5268 	 */
5269 	AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5270 			 asc_dvc->cfg->disc_enable);
5271 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5272 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5273 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5274 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5275 
5276 	/*
5277 	 * Set SCSI_CFG0 Microcode Default Value.
5278 	 *
5279 	 * The microcode will set the SCSI_CFG0 register using this value
5280 	 * after it is started below.
5281 	 */
5282 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5283 			 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5284 			 asc_dvc->chip_scsi_id);
5285 
5286 	/*
5287 	 * Determine SCSI_CFG1 Microcode Default Value.
5288 	 *
5289 	 * The microcode will set the SCSI_CFG1 register using this value
5290 	 * after it is started below.
5291 	 */
5292 
5293 	/* Read current SCSI_CFG1 Register value. */
5294 	scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5295 
5296 	/*
5297 	 * If the internal narrow cable is reversed all of the SCSI_CTRL
5298 	 * register signals will be set. Check for and return an error if
5299 	 * this condition is found.
5300 	 */
5301 	if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5302 		asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5303 		return ADV_ERROR;
5304 	}
5305 
5306 	/*
5307 	 * All kind of combinations of devices attached to one of four
5308 	 * connectors are acceptable except HVD device attached. For example,
5309 	 * LVD device can be attached to SE connector while SE device attached
5310 	 * to LVD connector.  If LVD device attached to SE connector, it only
5311 	 * runs up to Ultra speed.
5312 	 *
5313 	 * If an HVD device is attached to one of LVD connectors, return an
5314 	 * error.  However, there is no way to detect HVD device attached to
5315 	 * SE connectors.
5316 	 */
5317 	if (scsi_cfg1 & HVD) {
5318 		asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5319 		return ADV_ERROR;
5320 	}
5321 
5322 	/*
5323 	 * If either SE or LVD automatic termination control is enabled, then
5324 	 * set the termination value based on a table listed in a_condor.h.
5325 	 *
5326 	 * If manual termination was specified with an EEPROM setting then
5327 	 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5328 	 * to be 'ored' into SCSI_CFG1.
5329 	 */
5330 	if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5331 		/* SE automatic termination control is enabled. */
5332 		switch (scsi_cfg1 & C_DET_SE) {
5333 			/* TERM_SE_HI: on, TERM_SE_LO: on */
5334 		case 0x1:
5335 		case 0x2:
5336 		case 0x3:
5337 			asc_dvc->cfg->termination |= TERM_SE;
5338 			break;
5339 
5340 			/* TERM_SE_HI: on, TERM_SE_LO: off */
5341 		case 0x0:
5342 			asc_dvc->cfg->termination |= TERM_SE_HI;
5343 			break;
5344 		}
5345 	}
5346 
5347 	if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5348 		/* LVD automatic termination control is enabled. */
5349 		switch (scsi_cfg1 & C_DET_LVD) {
5350 			/* TERM_LVD_HI: on, TERM_LVD_LO: on */
5351 		case 0x4:
5352 		case 0x8:
5353 		case 0xC:
5354 			asc_dvc->cfg->termination |= TERM_LVD;
5355 			break;
5356 
5357 			/* TERM_LVD_HI: off, TERM_LVD_LO: off */
5358 		case 0x0:
5359 			break;
5360 		}
5361 	}
5362 
5363 	/*
5364 	 * Clear any set TERM_SE and TERM_LVD bits.
5365 	 */
5366 	scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5367 
5368 	/*
5369 	 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5370 	 */
5371 	scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5372 
5373 	/*
5374 	 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5375 	 * bits and set possibly modified termination control bits in the
5376 	 * Microcode SCSI_CFG1 Register Value.
5377 	 */
5378 	scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5379 
5380 	/*
5381 	 * Set SCSI_CFG1 Microcode Default Value
5382 	 *
5383 	 * Set possibly modified termination control and reset DIS_TERM_DRV
5384 	 * bits in the Microcode SCSI_CFG1 Register Value.
5385 	 *
5386 	 * The microcode will set the SCSI_CFG1 register using this value
5387 	 * after it is started below.
5388 	 */
5389 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5390 
5391 	/*
5392 	 * Set MEM_CFG Microcode Default Value
5393 	 *
5394 	 * The microcode will set the MEM_CFG register using this value
5395 	 * after it is started below.
5396 	 *
5397 	 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5398 	 * are defined.
5399 	 *
5400 	 * ASC-38C0800 has 16KB internal memory.
5401 	 */
5402 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5403 			 BIOS_EN | RAM_SZ_16KB);
5404 
5405 	/*
5406 	 * Set SEL_MASK Microcode Default Value
5407 	 *
5408 	 * The microcode will set the SEL_MASK register using this value
5409 	 * after it is started below.
5410 	 */
5411 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5412 			 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5413 
5414 	AdvBuildCarrierFreelist(asc_dvc);
5415 
5416 	/*
5417 	 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5418 	 */
5419 
5420 	if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5421 		asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5422 		return ADV_ERROR;
5423 	}
5424 	asc_dvc->carr_freelist = (ADV_CARR_T *)
5425 	    ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5426 
5427 	/*
5428 	 * The first command issued will be placed in the stopper carrier.
5429 	 */
5430 	asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5431 
5432 	/*
5433 	 * Set RISC ICQ physical address start value.
5434 	 * carr_pa is LE, must be native before write
5435 	 */
5436 	AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5437 
5438 	/*
5439 	 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5440 	 */
5441 	if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5442 		asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5443 		return ADV_ERROR;
5444 	}
5445 	asc_dvc->carr_freelist = (ADV_CARR_T *)
5446 	    ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5447 
5448 	/*
5449 	 * The first command completed by the RISC will be placed in
5450 	 * the stopper.
5451 	 *
5452 	 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5453 	 * completed the RISC will set the ASC_RQ_STOPPER bit.
5454 	 */
5455 	asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5456 
5457 	/*
5458 	 * Set RISC IRQ physical address start value.
5459 	 *
5460 	 * carr_pa is LE, must be native before write *
5461 	 */
5462 	AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5463 	asc_dvc->carr_pending_cnt = 0;
5464 
5465 	AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5466 			     (ADV_INTR_ENABLE_HOST_INTR |
5467 			      ADV_INTR_ENABLE_GLOBAL_INTR));
5468 
5469 	AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5470 	AdvWriteWordRegister(iop_base, IOPW_PC, word);
5471 
5472 	/* finally, finally, gentlemen, start your engine */
5473 	AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5474 
5475 	/*
5476 	 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5477 	 * Resets should be performed. The RISC has to be running
5478 	 * to issue a SCSI Bus Reset.
5479 	 */
5480 	if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5481 		/*
5482 		 * If the BIOS Signature is present in memory, restore the
5483 		 * BIOS Handshake Configuration Table and do not perform
5484 		 * a SCSI Bus Reset.
5485 		 */
5486 		if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5487 		    0x55AA) {
5488 			/*
5489 			 * Restore per TID negotiated values.
5490 			 */
5491 			AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5492 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5493 			AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5494 					 tagqng_able);
5495 			for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5496 				AdvWriteByteLram(iop_base,
5497 						 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5498 						 max_cmd[tid]);
5499 			}
5500 		} else {
5501 			if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5502 				warn_code = ASC_WARN_BUSRESET_ERROR;
5503 			}
5504 		}
5505 	}
5506 
5507 	return warn_code;
5508 }
5509 
5510 /*
5511  * Initialize the ASC-38C1600.
5512  *
5513  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5514  *
5515  * For a non-fatal error return a warning code. If there are no warnings
5516  * then 0 is returned.
5517  *
5518  * Needed after initialization for error recovery.
5519  */
5520 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5521 {
5522 	const struct firmware *fw;
5523 	const char fwname[] = "advansys/38C1600.bin";
5524 	AdvPortAddr iop_base;
5525 	ushort warn_code;
5526 	int begin_addr;
5527 	int end_addr;
5528 	ushort code_sum;
5529 	long word;
5530 	int i;
5531 	int err;
5532 	unsigned long chksum;
5533 	ushort scsi_cfg1;
5534 	uchar byte;
5535 	uchar tid;
5536 	ushort bios_mem[ASC_MC_BIOSLEN / 2];	/* BIOS RISC Memory 0x40-0x8F. */
5537 	ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5538 	uchar max_cmd[ASC_MAX_TID + 1];
5539 
5540 	/* If there is already an error, don't continue. */
5541 	if (asc_dvc->err_code != 0) {
5542 		return ADV_ERROR;
5543 	}
5544 
5545 	/*
5546 	 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5547 	 */
5548 	if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5549 		asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5550 		return ADV_ERROR;
5551 	}
5552 
5553 	warn_code = 0;
5554 	iop_base = asc_dvc->iop_base;
5555 
5556 	/*
5557 	 * Save the RISC memory BIOS region before writing the microcode.
5558 	 * The BIOS may already be loaded and using its RISC LRAM region
5559 	 * so its region must be saved and restored.
5560 	 *
5561 	 * Note: This code makes the assumption, which is currently true,
5562 	 * that a chip reset does not clear RISC LRAM.
5563 	 */
5564 	for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5565 		AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5566 				bios_mem[i]);
5567 	}
5568 
5569 	/*
5570 	 * Save current per TID negotiated values.
5571 	 */
5572 	AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5573 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5574 	AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5575 	AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5576 	for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5577 		AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5578 				max_cmd[tid]);
5579 	}
5580 
5581 	/*
5582 	 * RAM BIST (Built-In Self Test)
5583 	 *
5584 	 * Address : I/O base + offset 0x38h register (byte).
5585 	 * Function: Bit 7-6(RW) : RAM mode
5586 	 *                          Normal Mode   : 0x00
5587 	 *                          Pre-test Mode : 0x40
5588 	 *                          RAM Test Mode : 0x80
5589 	 *           Bit 5       : unused
5590 	 *           Bit 4(RO)   : Done bit
5591 	 *           Bit 3-0(RO) : Status
5592 	 *                          Host Error    : 0x08
5593 	 *                          Int_RAM Error : 0x04
5594 	 *                          RISC Error    : 0x02
5595 	 *                          SCSI Error    : 0x01
5596 	 *                          No Error      : 0x00
5597 	 *
5598 	 * Note: RAM BIST code should be put right here, before loading the
5599 	 * microcode and after saving the RISC memory BIOS region.
5600 	 */
5601 
5602 	/*
5603 	 * LRAM Pre-test
5604 	 *
5605 	 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5606 	 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5607 	 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5608 	 * to NORMAL_MODE, return an error too.
5609 	 */
5610 	for (i = 0; i < 2; i++) {
5611 		AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5612 		mdelay(10);	/* Wait for 10ms before reading back. */
5613 		byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5614 		if ((byte & RAM_TEST_DONE) == 0
5615 		    || (byte & 0x0F) != PRE_TEST_VALUE) {
5616 			asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5617 			return ADV_ERROR;
5618 		}
5619 
5620 		AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5621 		mdelay(10);	/* Wait for 10ms before reading back. */
5622 		if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5623 		    != NORMAL_VALUE) {
5624 			asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5625 			return ADV_ERROR;
5626 		}
5627 	}
5628 
5629 	/*
5630 	 * LRAM Test - It takes about 1.5 ms to run through the test.
5631 	 *
5632 	 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5633 	 * If Done bit not set or Status not 0, save register byte, set the
5634 	 * err_code, and return an error.
5635 	 */
5636 	AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5637 	mdelay(10);	/* Wait for 10ms before checking status. */
5638 
5639 	byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5640 	if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5641 		/* Get here if Done bit not set or Status not 0. */
5642 		asc_dvc->bist_err_code = byte;	/* for BIOS display message */
5643 		asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5644 		return ADV_ERROR;
5645 	}
5646 
5647 	/* We need to reset back to normal mode after LRAM test passes. */
5648 	AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5649 
5650 	err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5651 	if (err) {
5652 		printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5653 		       fwname, err);
5654 		asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5655 		return err;
5656 	}
5657 	if (fw->size < 4) {
5658 		printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5659 		       fw->size, fwname);
5660 		release_firmware(fw);
5661 		asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
5662 		return -EINVAL;
5663 	}
5664 	chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5665 		 (fw->data[1] << 8) | fw->data[0];
5666 	asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5667 					     fw->size - 4, ADV_38C1600_MEMSIZE,
5668 					     chksum);
5669 	release_firmware(fw);
5670 	if (asc_dvc->err_code)
5671 		return ADV_ERROR;
5672 
5673 	/*
5674 	 * Restore the RISC memory BIOS region.
5675 	 */
5676 	for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5677 		AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5678 				 bios_mem[i]);
5679 	}
5680 
5681 	/*
5682 	 * Calculate and write the microcode code checksum to the microcode
5683 	 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5684 	 */
5685 	AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5686 	AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5687 	code_sum = 0;
5688 	AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5689 	for (word = begin_addr; word < end_addr; word += 2) {
5690 		code_sum += AdvReadWordAutoIncLram(iop_base);
5691 	}
5692 	AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5693 
5694 	/*
5695 	 * Read microcode version and date.
5696 	 */
5697 	AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5698 			asc_dvc->cfg->mcode_date);
5699 	AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5700 			asc_dvc->cfg->mcode_version);
5701 
5702 	/*
5703 	 * Set the chip type to indicate the ASC38C1600.
5704 	 */
5705 	AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5706 
5707 	/*
5708 	 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5709 	 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5710 	 * cable detection and then we are able to read C_DET[3:0].
5711 	 *
5712 	 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5713 	 * Microcode Default Value' section below.
5714 	 */
5715 	scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5716 	AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5717 			     scsi_cfg1 | DIS_TERM_DRV);
5718 
5719 	/*
5720 	 * If the PCI Configuration Command Register "Parity Error Response
5721 	 * Control" Bit was clear (0), then set the microcode variable
5722 	 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5723 	 * to ignore DMA parity errors.
5724 	 */
5725 	if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5726 		AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5727 		word |= CONTROL_FLAG_IGNORE_PERR;
5728 		AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5729 	}
5730 
5731 	/*
5732 	 * If the BIOS control flag AIPP (Asynchronous Information
5733 	 * Phase Protection) disable bit is not set, then set the firmware
5734 	 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5735 	 * AIPP checking and encoding.
5736 	 */
5737 	if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5738 		AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5739 		word |= CONTROL_FLAG_ENABLE_AIPP;
5740 		AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5741 	}
5742 
5743 	/*
5744 	 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5745 	 * and START_CTL_TH [3:2].
5746 	 */
5747 	AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5748 			     FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5749 
5750 	/*
5751 	 * Microcode operating variables for WDTR, SDTR, and command tag
5752 	 * queuing will be set in slave_configure() based on what a
5753 	 * device reports it is capable of in Inquiry byte 7.
5754 	 *
5755 	 * If SCSI Bus Resets have been disabled, then directly set
5756 	 * SDTR and WDTR from the EEPROM configuration. This will allow
5757 	 * the BIOS and warm boot to work without a SCSI bus hang on
5758 	 * the Inquiry caused by host and target mismatched DTR values.
5759 	 * Without the SCSI Bus Reset, before an Inquiry a device can't
5760 	 * be assumed to be in Asynchronous, Narrow mode.
5761 	 */
5762 	if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5763 		AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5764 				 asc_dvc->wdtr_able);
5765 		AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5766 				 asc_dvc->sdtr_able);
5767 	}
5768 
5769 	/*
5770 	 * Set microcode operating variables for DISC and SDTR_SPEED1,
5771 	 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5772 	 * configuration values.
5773 	 *
5774 	 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5775 	 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5776 	 * without determining here whether the device supports SDTR.
5777 	 */
5778 	AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5779 			 asc_dvc->cfg->disc_enable);
5780 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5781 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5782 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5783 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5784 
5785 	/*
5786 	 * Set SCSI_CFG0 Microcode Default Value.
5787 	 *
5788 	 * The microcode will set the SCSI_CFG0 register using this value
5789 	 * after it is started below.
5790 	 */
5791 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5792 			 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5793 			 asc_dvc->chip_scsi_id);
5794 
5795 	/*
5796 	 * Calculate SCSI_CFG1 Microcode Default Value.
5797 	 *
5798 	 * The microcode will set the SCSI_CFG1 register using this value
5799 	 * after it is started below.
5800 	 *
5801 	 * Each ASC-38C1600 function has only two cable detect bits.
5802 	 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5803 	 */
5804 	scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5805 
5806 	/*
5807 	 * If the cable is reversed all of the SCSI_CTRL register signals
5808 	 * will be set. Check for and return an error if this condition is
5809 	 * found.
5810 	 */
5811 	if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5812 		asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5813 		return ADV_ERROR;
5814 	}
5815 
5816 	/*
5817 	 * Each ASC-38C1600 function has two connectors. Only an HVD device
5818 	 * can not be connected to either connector. An LVD device or SE device
5819 	 * may be connected to either connecor. If an SE device is connected,
5820 	 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5821 	 *
5822 	 * If an HVD device is attached, return an error.
5823 	 */
5824 	if (scsi_cfg1 & HVD) {
5825 		asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5826 		return ADV_ERROR;
5827 	}
5828 
5829 	/*
5830 	 * Each function in the ASC-38C1600 uses only the SE cable detect and
5831 	 * termination because there are two connectors for each function. Each
5832 	 * function may use either LVD or SE mode. Corresponding the SE automatic
5833 	 * termination control EEPROM bits are used for each function. Each
5834 	 * function has its own EEPROM. If SE automatic control is enabled for
5835 	 * the function, then set the termination value based on a table listed
5836 	 * in a_condor.h.
5837 	 *
5838 	 * If manual termination is specified in the EEPROM for the function,
5839 	 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5840 	 * ready to be 'ored' into SCSI_CFG1.
5841 	 */
5842 	if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5843 		struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5844 		/* SE automatic termination control is enabled. */
5845 		switch (scsi_cfg1 & C_DET_SE) {
5846 			/* TERM_SE_HI: on, TERM_SE_LO: on */
5847 		case 0x1:
5848 		case 0x2:
5849 		case 0x3:
5850 			asc_dvc->cfg->termination |= TERM_SE;
5851 			break;
5852 
5853 		case 0x0:
5854 			if (PCI_FUNC(pdev->devfn) == 0) {
5855 				/* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5856 			} else {
5857 				/* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5858 				asc_dvc->cfg->termination |= TERM_SE_HI;
5859 			}
5860 			break;
5861 		}
5862 	}
5863 
5864 	/*
5865 	 * Clear any set TERM_SE bits.
5866 	 */
5867 	scsi_cfg1 &= ~TERM_SE;
5868 
5869 	/*
5870 	 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5871 	 */
5872 	scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5873 
5874 	/*
5875 	 * Clear Big Endian and Terminator Polarity bits and set possibly
5876 	 * modified termination control bits in the Microcode SCSI_CFG1
5877 	 * Register Value.
5878 	 *
5879 	 * Big Endian bit is not used even on big endian machines.
5880 	 */
5881 	scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5882 
5883 	/*
5884 	 * Set SCSI_CFG1 Microcode Default Value
5885 	 *
5886 	 * Set possibly modified termination control bits in the Microcode
5887 	 * SCSI_CFG1 Register Value.
5888 	 *
5889 	 * The microcode will set the SCSI_CFG1 register using this value
5890 	 * after it is started below.
5891 	 */
5892 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5893 
5894 	/*
5895 	 * Set MEM_CFG Microcode Default Value
5896 	 *
5897 	 * The microcode will set the MEM_CFG register using this value
5898 	 * after it is started below.
5899 	 *
5900 	 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5901 	 * are defined.
5902 	 *
5903 	 * ASC-38C1600 has 32KB internal memory.
5904 	 *
5905 	 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5906 	 * out a special 16K Adv Library and Microcode version. After the issue
5907 	 * resolved, we should turn back to the 32K support. Both a_condor.h and
5908 	 * mcode.sas files also need to be updated.
5909 	 *
5910 	 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5911 	 *  BIOS_EN | RAM_SZ_32KB);
5912 	 */
5913 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5914 			 BIOS_EN | RAM_SZ_16KB);
5915 
5916 	/*
5917 	 * Set SEL_MASK Microcode Default Value
5918 	 *
5919 	 * The microcode will set the SEL_MASK register using this value
5920 	 * after it is started below.
5921 	 */
5922 	AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5923 			 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5924 
5925 	AdvBuildCarrierFreelist(asc_dvc);
5926 
5927 	/*
5928 	 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5929 	 */
5930 	if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5931 		asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5932 		return ADV_ERROR;
5933 	}
5934 	asc_dvc->carr_freelist = (ADV_CARR_T *)
5935 	    ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5936 
5937 	/*
5938 	 * The first command issued will be placed in the stopper carrier.
5939 	 */
5940 	asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5941 
5942 	/*
5943 	 * Set RISC ICQ physical address start value. Initialize the
5944 	 * COMMA register to the same value otherwise the RISC will
5945 	 * prematurely detect a command is available.
5946 	 */
5947 	AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5948 	AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5949 			      le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5950 
5951 	/*
5952 	 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5953 	 */
5954 	if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5955 		asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5956 		return ADV_ERROR;
5957 	}
5958 	asc_dvc->carr_freelist = (ADV_CARR_T *)
5959 	    ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5960 
5961 	/*
5962 	 * The first command completed by the RISC will be placed in
5963 	 * the stopper.
5964 	 *
5965 	 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5966 	 * completed the RISC will set the ASC_RQ_STOPPER bit.
5967 	 */
5968 	asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5969 
5970 	/*
5971 	 * Set RISC IRQ physical address start value.
5972 	 */
5973 	AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5974 	asc_dvc->carr_pending_cnt = 0;
5975 
5976 	AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5977 			     (ADV_INTR_ENABLE_HOST_INTR |
5978 			      ADV_INTR_ENABLE_GLOBAL_INTR));
5979 	AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5980 	AdvWriteWordRegister(iop_base, IOPW_PC, word);
5981 
5982 	/* finally, finally, gentlemen, start your engine */
5983 	AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5984 
5985 	/*
5986 	 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5987 	 * Resets should be performed. The RISC has to be running
5988 	 * to issue a SCSI Bus Reset.
5989 	 */
5990 	if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5991 		/*
5992 		 * If the BIOS Signature is present in memory, restore the
5993 		 * per TID microcode operating variables.
5994 		 */
5995 		if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5996 		    0x55AA) {
5997 			/*
5998 			 * Restore per TID negotiated values.
5999 			 */
6000 			AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6001 			AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6002 			AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6003 			AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
6004 					 tagqng_able);
6005 			for (tid = 0; tid <= ASC_MAX_TID; tid++) {
6006 				AdvWriteByteLram(iop_base,
6007 						 ASC_MC_NUMBER_OF_MAX_CMD + tid,
6008 						 max_cmd[tid]);
6009 			}
6010 		} else {
6011 			if (AdvResetSB(asc_dvc) != ADV_TRUE) {
6012 				warn_code = ASC_WARN_BUSRESET_ERROR;
6013 			}
6014 		}
6015 	}
6016 
6017 	return warn_code;
6018 }
6019 
6020 /*
6021  * Reset chip and SCSI Bus.
6022  *
6023  * Return Value:
6024  *      ADV_TRUE(1) -   Chip re-initialization and SCSI Bus Reset successful.
6025  *      ADV_FALSE(0) -  Chip re-initialization and SCSI Bus Reset failure.
6026  */
6027 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
6028 {
6029 	int status;
6030 	ushort wdtr_able, sdtr_able, tagqng_able;
6031 	ushort ppr_able = 0;
6032 	uchar tid, max_cmd[ADV_MAX_TID + 1];
6033 	AdvPortAddr iop_base;
6034 	ushort bios_sig;
6035 
6036 	iop_base = asc_dvc->iop_base;
6037 
6038 	/*
6039 	 * Save current per TID negotiated values.
6040 	 */
6041 	AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6042 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6043 	if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6044 		AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6045 	}
6046 	AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6047 	for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6048 		AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6049 				max_cmd[tid]);
6050 	}
6051 
6052 	/*
6053 	 * Force the AdvInitAsc3550/38C0800Driver() function to
6054 	 * perform a SCSI Bus Reset by clearing the BIOS signature word.
6055 	 * The initialization functions assumes a SCSI Bus Reset is not
6056 	 * needed if the BIOS signature word is present.
6057 	 */
6058 	AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6059 	AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
6060 
6061 	/*
6062 	 * Stop chip and reset it.
6063 	 */
6064 	AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
6065 	AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
6066 	mdelay(100);
6067 	AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
6068 			     ADV_CTRL_REG_CMD_WR_IO_REG);
6069 
6070 	/*
6071 	 * Reset Adv Library error code, if any, and try
6072 	 * re-initializing the chip.
6073 	 */
6074 	asc_dvc->err_code = 0;
6075 	if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6076 		status = AdvInitAsc38C1600Driver(asc_dvc);
6077 	} else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6078 		status = AdvInitAsc38C0800Driver(asc_dvc);
6079 	} else {
6080 		status = AdvInitAsc3550Driver(asc_dvc);
6081 	}
6082 
6083 	/* Translate initialization return value to status value. */
6084 	if (status == 0) {
6085 		status = ADV_TRUE;
6086 	} else {
6087 		status = ADV_FALSE;
6088 	}
6089 
6090 	/*
6091 	 * Restore the BIOS signature word.
6092 	 */
6093 	AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6094 
6095 	/*
6096 	 * Restore per TID negotiated values.
6097 	 */
6098 	AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6099 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6100 	if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6101 		AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6102 	}
6103 	AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6104 	for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6105 		AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6106 				 max_cmd[tid]);
6107 	}
6108 
6109 	return status;
6110 }
6111 
6112 /*
6113  * adv_async_callback() - Adv Library asynchronous event callback function.
6114  */
6115 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
6116 {
6117 	switch (code) {
6118 	case ADV_ASYNC_SCSI_BUS_RESET_DET:
6119 		/*
6120 		 * The firmware detected a SCSI Bus reset.
6121 		 */
6122 		ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
6123 		break;
6124 
6125 	case ADV_ASYNC_RDMA_FAILURE:
6126 		/*
6127 		 * Handle RDMA failure by resetting the SCSI Bus and
6128 		 * possibly the chip if it is unresponsive. Log the error
6129 		 * with a unique code.
6130 		 */
6131 		ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
6132 		AdvResetChipAndSB(adv_dvc_varp);
6133 		break;
6134 
6135 	case ADV_HOST_SCSI_BUS_RESET:
6136 		/*
6137 		 * Host generated SCSI bus reset occurred.
6138 		 */
6139 		ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
6140 		break;
6141 
6142 	default:
6143 		ASC_DBG(0, "unknown code 0x%x\n", code);
6144 		break;
6145 	}
6146 }
6147 
6148 /*
6149  * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6150  *
6151  * Callback function for the Wide SCSI Adv Library.
6152  */
6153 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6154 {
6155 	struct asc_board *boardp;
6156 	adv_req_t *reqp;
6157 	adv_sgblk_t *sgblkp;
6158 	struct scsi_cmnd *scp;
6159 	struct Scsi_Host *shost;
6160 	ADV_DCNT resid_cnt;
6161 
6162 	ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
6163 		 (ulong)adv_dvc_varp, (ulong)scsiqp);
6164 	ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6165 
6166 	/*
6167 	 * Get the adv_req_t structure for the command that has been
6168 	 * completed. The adv_req_t structure actually contains the
6169 	 * completed ADV_SCSI_REQ_Q structure.
6170 	 */
6171 	reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
6172 	ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6173 	if (reqp == NULL) {
6174 		ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6175 		return;
6176 	}
6177 
6178 	/*
6179 	 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6180 	 * command that has been completed.
6181 	 *
6182 	 * Note: The adv_req_t request structure and adv_sgblk_t structure,
6183 	 * if any, are dropped, because a board structure pointer can not be
6184 	 * determined.
6185 	 */
6186 	scp = reqp->cmndp;
6187 	ASC_DBG(1, "scp 0x%p\n", scp);
6188 	if (scp == NULL) {
6189 		ASC_PRINT
6190 		    ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6191 		return;
6192 	}
6193 	ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6194 
6195 	shost = scp->device->host;
6196 	ASC_STATS(shost, callback);
6197 	ASC_DBG(1, "shost 0x%p\n", shost);
6198 
6199 	boardp = shost_priv(shost);
6200 	BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
6201 
6202 	/*
6203 	 * 'done_status' contains the command's ending status.
6204 	 */
6205 	switch (scsiqp->done_status) {
6206 	case QD_NO_ERROR:
6207 		ASC_DBG(2, "QD_NO_ERROR\n");
6208 		scp->result = 0;
6209 
6210 		/*
6211 		 * Check for an underrun condition.
6212 		 *
6213 		 * If there was no error and an underrun condition, then
6214 		 * then return the number of underrun bytes.
6215 		 */
6216 		resid_cnt = le32_to_cpu(scsiqp->data_cnt);
6217 		if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6218 		    resid_cnt <= scsi_bufflen(scp)) {
6219 			ASC_DBG(1, "underrun condition %lu bytes\n",
6220 				 (ulong)resid_cnt);
6221 			scsi_set_resid(scp, resid_cnt);
6222 		}
6223 		break;
6224 
6225 	case QD_WITH_ERROR:
6226 		ASC_DBG(2, "QD_WITH_ERROR\n");
6227 		switch (scsiqp->host_status) {
6228 		case QHSTA_NO_ERROR:
6229 			if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
6230 				ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
6231 				ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6232 						  SCSI_SENSE_BUFFERSIZE);
6233 				/*
6234 				 * Note: The 'status_byte()' macro used by
6235 				 * target drivers defined in scsi.h shifts the
6236 				 * status byte returned by host drivers right
6237 				 * by 1 bit.  This is why target drivers also
6238 				 * use right shifted status byte definitions.
6239 				 * For instance target drivers use
6240 				 * CHECK_CONDITION, defined to 0x1, instead of
6241 				 * the SCSI defined check condition value of
6242 				 * 0x2. Host drivers are supposed to return
6243 				 * the status byte as it is defined by SCSI.
6244 				 */
6245 				scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6246 				    STATUS_BYTE(scsiqp->scsi_status);
6247 			} else {
6248 				scp->result = STATUS_BYTE(scsiqp->scsi_status);
6249 			}
6250 			break;
6251 
6252 		default:
6253 			/* Some other QHSTA error occurred. */
6254 			ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
6255 			scp->result = HOST_BYTE(DID_BAD_TARGET);
6256 			break;
6257 		}
6258 		break;
6259 
6260 	case QD_ABORTED_BY_HOST:
6261 		ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
6262 		scp->result =
6263 		    HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6264 		break;
6265 
6266 	default:
6267 		ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
6268 		scp->result =
6269 		    HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6270 		break;
6271 	}
6272 
6273 	/*
6274 	 * If the 'init_tidmask' bit isn't already set for the target and the
6275 	 * current request finished normally, then set the bit for the target
6276 	 * to indicate that a device is present.
6277 	 */
6278 	if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6279 	    scsiqp->done_status == QD_NO_ERROR &&
6280 	    scsiqp->host_status == QHSTA_NO_ERROR) {
6281 		boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6282 	}
6283 
6284 	asc_scsi_done(scp);
6285 
6286 	/*
6287 	 * Free all 'adv_sgblk_t' structures allocated for the request.
6288 	 */
6289 	while ((sgblkp = reqp->sgblkp) != NULL) {
6290 		/* Remove 'sgblkp' from the request list. */
6291 		reqp->sgblkp = sgblkp->next_sgblkp;
6292 
6293 		/* Add 'sgblkp' to the board free list. */
6294 		sgblkp->next_sgblkp = boardp->adv_sgblkp;
6295 		boardp->adv_sgblkp = sgblkp;
6296 	}
6297 
6298 	/*
6299 	 * Free the adv_req_t structure used with the command by adding
6300 	 * it back to the board free list.
6301 	 */
6302 	reqp->next_reqp = boardp->adv_reqp;
6303 	boardp->adv_reqp = reqp;
6304 
6305 	ASC_DBG(1, "done\n");
6306 }
6307 
6308 /*
6309  * Adv Library Interrupt Service Routine
6310  *
6311  *  This function is called by a driver's interrupt service routine.
6312  *  The function disables and re-enables interrupts.
6313  *
6314  *  When a microcode idle command is completed, the ADV_DVC_VAR
6315  *  'idle_cmd_done' field is set to ADV_TRUE.
6316  *
6317  *  Note: AdvISR() can be called when interrupts are disabled or even
6318  *  when there is no hardware interrupt condition present. It will
6319  *  always check for completed idle commands and microcode requests.
6320  *  This is an important feature that shouldn't be changed because it
6321  *  allows commands to be completed from polling mode loops.
6322  *
6323  * Return:
6324  *   ADV_TRUE(1) - interrupt was pending
6325  *   ADV_FALSE(0) - no interrupt was pending
6326  */
6327 static int AdvISR(ADV_DVC_VAR *asc_dvc)
6328 {
6329 	AdvPortAddr iop_base;
6330 	uchar int_stat;
6331 	ushort target_bit;
6332 	ADV_CARR_T *free_carrp;
6333 	ADV_VADDR irq_next_vpa;
6334 	ADV_SCSI_REQ_Q *scsiq;
6335 
6336 	iop_base = asc_dvc->iop_base;
6337 
6338 	/* Reading the register clears the interrupt. */
6339 	int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6340 
6341 	if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6342 			 ADV_INTR_STATUS_INTRC)) == 0) {
6343 		return ADV_FALSE;
6344 	}
6345 
6346 	/*
6347 	 * Notify the driver of an asynchronous microcode condition by
6348 	 * calling the adv_async_callback function. The function
6349 	 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6350 	 */
6351 	if (int_stat & ADV_INTR_STATUS_INTRB) {
6352 		uchar intrb_code;
6353 
6354 		AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6355 
6356 		if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6357 		    asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6358 			if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6359 			    asc_dvc->carr_pending_cnt != 0) {
6360 				AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6361 						     ADV_TICKLE_A);
6362 				if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6363 					AdvWriteByteRegister(iop_base,
6364 							     IOPB_TICKLE,
6365 							     ADV_TICKLE_NOP);
6366 				}
6367 			}
6368 		}
6369 
6370 		adv_async_callback(asc_dvc, intrb_code);
6371 	}
6372 
6373 	/*
6374 	 * Check if the IRQ stopper carrier contains a completed request.
6375 	 */
6376 	while (((irq_next_vpa =
6377 		 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6378 		/*
6379 		 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6380 		 * The RISC will have set 'areq_vpa' to a virtual address.
6381 		 *
6382 		 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6383 		 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6384 		 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6385 		 * in AdvExeScsiQueue().
6386 		 */
6387 		scsiq = (ADV_SCSI_REQ_Q *)
6388 		    ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
6389 
6390 		/*
6391 		 * Request finished with good status and the queue was not
6392 		 * DMAed to host memory by the firmware. Set all status fields
6393 		 * to indicate good status.
6394 		 */
6395 		if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6396 			scsiq->done_status = QD_NO_ERROR;
6397 			scsiq->host_status = scsiq->scsi_status = 0;
6398 			scsiq->data_cnt = 0L;
6399 		}
6400 
6401 		/*
6402 		 * Advance the stopper pointer to the next carrier
6403 		 * ignoring the lower four bits. Free the previous
6404 		 * stopper carrier.
6405 		 */
6406 		free_carrp = asc_dvc->irq_sp;
6407 		asc_dvc->irq_sp = (ADV_CARR_T *)
6408 		    ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
6409 
6410 		free_carrp->next_vpa =
6411 		    cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6412 		asc_dvc->carr_freelist = free_carrp;
6413 		asc_dvc->carr_pending_cnt--;
6414 
6415 		target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6416 
6417 		/*
6418 		 * Clear request microcode control flag.
6419 		 */
6420 		scsiq->cntl = 0;
6421 
6422 		/*
6423 		 * Notify the driver of the completed request by passing
6424 		 * the ADV_SCSI_REQ_Q pointer to its callback function.
6425 		 */
6426 		scsiq->a_flag |= ADV_SCSIQ_DONE;
6427 		adv_isr_callback(asc_dvc, scsiq);
6428 		/*
6429 		 * Note: After the driver callback function is called, 'scsiq'
6430 		 * can no longer be referenced.
6431 		 *
6432 		 * Fall through and continue processing other completed
6433 		 * requests...
6434 		 */
6435 	}
6436 	return ADV_TRUE;
6437 }
6438 
6439 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6440 {
6441 	if (asc_dvc->err_code == 0) {
6442 		asc_dvc->err_code = err_code;
6443 		AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6444 				 err_code);
6445 	}
6446 	return err_code;
6447 }
6448 
6449 static void AscAckInterrupt(PortAddr iop_base)
6450 {
6451 	uchar host_flag;
6452 	uchar risc_flag;
6453 	ushort loop;
6454 
6455 	loop = 0;
6456 	do {
6457 		risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6458 		if (loop++ > 0x7FFF) {
6459 			break;
6460 		}
6461 	} while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6462 	host_flag =
6463 	    AscReadLramByte(iop_base,
6464 			    ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6465 	AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6466 			 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6467 	AscSetChipStatus(iop_base, CIW_INT_ACK);
6468 	loop = 0;
6469 	while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6470 		AscSetChipStatus(iop_base, CIW_INT_ACK);
6471 		if (loop++ > 3) {
6472 			break;
6473 		}
6474 	}
6475 	AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
6476 }
6477 
6478 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6479 {
6480 	const uchar *period_table;
6481 	int max_index;
6482 	int min_index;
6483 	int i;
6484 
6485 	period_table = asc_dvc->sdtr_period_tbl;
6486 	max_index = (int)asc_dvc->max_sdtr_index;
6487 	min_index = (int)asc_dvc->min_sdtr_index;
6488 	if ((syn_time <= period_table[max_index])) {
6489 		for (i = min_index; i < (max_index - 1); i++) {
6490 			if (syn_time <= period_table[i]) {
6491 				return (uchar)i;
6492 			}
6493 		}
6494 		return (uchar)max_index;
6495 	} else {
6496 		return (uchar)(max_index + 1);
6497 	}
6498 }
6499 
6500 static uchar
6501 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6502 {
6503 	EXT_MSG sdtr_buf;
6504 	uchar sdtr_period_index;
6505 	PortAddr iop_base;
6506 
6507 	iop_base = asc_dvc->iop_base;
6508 	sdtr_buf.msg_type = EXTENDED_MESSAGE;
6509 	sdtr_buf.msg_len = MS_SDTR_LEN;
6510 	sdtr_buf.msg_req = EXTENDED_SDTR;
6511 	sdtr_buf.xfer_period = sdtr_period;
6512 	sdtr_offset &= ASC_SYN_MAX_OFFSET;
6513 	sdtr_buf.req_ack_offset = sdtr_offset;
6514 	sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6515 	if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6516 		AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6517 					(uchar *)&sdtr_buf,
6518 					sizeof(EXT_MSG) >> 1);
6519 		return ((sdtr_period_index << 4) | sdtr_offset);
6520 	} else {
6521 		sdtr_buf.req_ack_offset = 0;
6522 		AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6523 					(uchar *)&sdtr_buf,
6524 					sizeof(EXT_MSG) >> 1);
6525 		return 0;
6526 	}
6527 }
6528 
6529 static uchar
6530 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6531 {
6532 	uchar byte;
6533 	uchar sdtr_period_ix;
6534 
6535 	sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6536 	if (sdtr_period_ix > asc_dvc->max_sdtr_index)
6537 		return 0xFF;
6538 	byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6539 	return byte;
6540 }
6541 
6542 static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6543 {
6544 	ASC_SCSI_BIT_ID_TYPE org_id;
6545 	int i;
6546 	int sta = TRUE;
6547 
6548 	AscSetBank(iop_base, 1);
6549 	org_id = AscReadChipDvcID(iop_base);
6550 	for (i = 0; i <= ASC_MAX_TID; i++) {
6551 		if (org_id == (0x01 << i))
6552 			break;
6553 	}
6554 	org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6555 	AscWriteChipDvcID(iop_base, id);
6556 	if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6557 		AscSetBank(iop_base, 0);
6558 		AscSetChipSyn(iop_base, sdtr_data);
6559 		if (AscGetChipSyn(iop_base) != sdtr_data) {
6560 			sta = FALSE;
6561 		}
6562 	} else {
6563 		sta = FALSE;
6564 	}
6565 	AscSetBank(iop_base, 1);
6566 	AscWriteChipDvcID(iop_base, org_id);
6567 	AscSetBank(iop_base, 0);
6568 	return (sta);
6569 }
6570 
6571 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6572 {
6573 	AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6574 	AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6575 }
6576 
6577 static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6578 {
6579 	EXT_MSG ext_msg;
6580 	EXT_MSG out_msg;
6581 	ushort halt_q_addr;
6582 	int sdtr_accept;
6583 	ushort int_halt_code;
6584 	ASC_SCSI_BIT_ID_TYPE scsi_busy;
6585 	ASC_SCSI_BIT_ID_TYPE target_id;
6586 	PortAddr iop_base;
6587 	uchar tag_code;
6588 	uchar q_status;
6589 	uchar halt_qp;
6590 	uchar sdtr_data;
6591 	uchar target_ix;
6592 	uchar q_cntl, tid_no;
6593 	uchar cur_dvc_qng;
6594 	uchar asyn_sdtr;
6595 	uchar scsi_status;
6596 	struct asc_board *boardp;
6597 
6598 	BUG_ON(!asc_dvc->drv_ptr);
6599 	boardp = asc_dvc->drv_ptr;
6600 
6601 	iop_base = asc_dvc->iop_base;
6602 	int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6603 
6604 	halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6605 	halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6606 	target_ix = AscReadLramByte(iop_base,
6607 				    (ushort)(halt_q_addr +
6608 					     (ushort)ASC_SCSIQ_B_TARGET_IX));
6609 	q_cntl = AscReadLramByte(iop_base,
6610 			    (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6611 	tid_no = ASC_TIX_TO_TID(target_ix);
6612 	target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6613 	if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6614 		asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6615 	} else {
6616 		asyn_sdtr = 0;
6617 	}
6618 	if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6619 		if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6620 			AscSetChipSDTR(iop_base, 0, tid_no);
6621 			boardp->sdtr_data[tid_no] = 0;
6622 		}
6623 		AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6624 		return (0);
6625 	} else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6626 		if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6627 			AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6628 			boardp->sdtr_data[tid_no] = asyn_sdtr;
6629 		}
6630 		AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6631 		return (0);
6632 	} else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6633 		AscMemWordCopyPtrFromLram(iop_base,
6634 					  ASCV_MSGIN_BEG,
6635 					  (uchar *)&ext_msg,
6636 					  sizeof(EXT_MSG) >> 1);
6637 
6638 		if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6639 		    ext_msg.msg_req == EXTENDED_SDTR &&
6640 		    ext_msg.msg_len == MS_SDTR_LEN) {
6641 			sdtr_accept = TRUE;
6642 			if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6643 
6644 				sdtr_accept = FALSE;
6645 				ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6646 			}
6647 			if ((ext_msg.xfer_period <
6648 			     asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
6649 			    || (ext_msg.xfer_period >
6650 				asc_dvc->sdtr_period_tbl[asc_dvc->
6651 							 max_sdtr_index])) {
6652 				sdtr_accept = FALSE;
6653 				ext_msg.xfer_period =
6654 				    asc_dvc->sdtr_period_tbl[asc_dvc->
6655 							     min_sdtr_index];
6656 			}
6657 			if (sdtr_accept) {
6658 				sdtr_data =
6659 				    AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6660 						   ext_msg.req_ack_offset);
6661 				if ((sdtr_data == 0xFF)) {
6662 
6663 					q_cntl |= QC_MSG_OUT;
6664 					asc_dvc->init_sdtr &= ~target_id;
6665 					asc_dvc->sdtr_done &= ~target_id;
6666 					AscSetChipSDTR(iop_base, asyn_sdtr,
6667 						       tid_no);
6668 					boardp->sdtr_data[tid_no] = asyn_sdtr;
6669 				}
6670 			}
6671 			if (ext_msg.req_ack_offset == 0) {
6672 
6673 				q_cntl &= ~QC_MSG_OUT;
6674 				asc_dvc->init_sdtr &= ~target_id;
6675 				asc_dvc->sdtr_done &= ~target_id;
6676 				AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6677 			} else {
6678 				if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
6679 					q_cntl &= ~QC_MSG_OUT;
6680 					asc_dvc->sdtr_done |= target_id;
6681 					asc_dvc->init_sdtr |= target_id;
6682 					asc_dvc->pci_fix_asyn_xfer &=
6683 					    ~target_id;
6684 					sdtr_data =
6685 					    AscCalSDTRData(asc_dvc,
6686 							   ext_msg.xfer_period,
6687 							   ext_msg.
6688 							   req_ack_offset);
6689 					AscSetChipSDTR(iop_base, sdtr_data,
6690 						       tid_no);
6691 					boardp->sdtr_data[tid_no] = sdtr_data;
6692 				} else {
6693 					q_cntl |= QC_MSG_OUT;
6694 					AscMsgOutSDTR(asc_dvc,
6695 						      ext_msg.xfer_period,
6696 						      ext_msg.req_ack_offset);
6697 					asc_dvc->pci_fix_asyn_xfer &=
6698 					    ~target_id;
6699 					sdtr_data =
6700 					    AscCalSDTRData(asc_dvc,
6701 							   ext_msg.xfer_period,
6702 							   ext_msg.
6703 							   req_ack_offset);
6704 					AscSetChipSDTR(iop_base, sdtr_data,
6705 						       tid_no);
6706 					boardp->sdtr_data[tid_no] = sdtr_data;
6707 					asc_dvc->sdtr_done |= target_id;
6708 					asc_dvc->init_sdtr |= target_id;
6709 				}
6710 			}
6711 
6712 			AscWriteLramByte(iop_base,
6713 					 (ushort)(halt_q_addr +
6714 						  (ushort)ASC_SCSIQ_B_CNTL),
6715 					 q_cntl);
6716 			AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6717 			return (0);
6718 		} else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6719 			   ext_msg.msg_req == EXTENDED_WDTR &&
6720 			   ext_msg.msg_len == MS_WDTR_LEN) {
6721 
6722 			ext_msg.wdtr_width = 0;
6723 			AscMemWordCopyPtrToLram(iop_base,
6724 						ASCV_MSGOUT_BEG,
6725 						(uchar *)&ext_msg,
6726 						sizeof(EXT_MSG) >> 1);
6727 			q_cntl |= QC_MSG_OUT;
6728 			AscWriteLramByte(iop_base,
6729 					 (ushort)(halt_q_addr +
6730 						  (ushort)ASC_SCSIQ_B_CNTL),
6731 					 q_cntl);
6732 			AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6733 			return (0);
6734 		} else {
6735 
6736 			ext_msg.msg_type = MESSAGE_REJECT;
6737 			AscMemWordCopyPtrToLram(iop_base,
6738 						ASCV_MSGOUT_BEG,
6739 						(uchar *)&ext_msg,
6740 						sizeof(EXT_MSG) >> 1);
6741 			q_cntl |= QC_MSG_OUT;
6742 			AscWriteLramByte(iop_base,
6743 					 (ushort)(halt_q_addr +
6744 						  (ushort)ASC_SCSIQ_B_CNTL),
6745 					 q_cntl);
6746 			AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6747 			return (0);
6748 		}
6749 	} else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6750 
6751 		q_cntl |= QC_REQ_SENSE;
6752 
6753 		if ((asc_dvc->init_sdtr & target_id) != 0) {
6754 
6755 			asc_dvc->sdtr_done &= ~target_id;
6756 
6757 			sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6758 			q_cntl |= QC_MSG_OUT;
6759 			AscMsgOutSDTR(asc_dvc,
6760 				      asc_dvc->
6761 				      sdtr_period_tbl[(sdtr_data >> 4) &
6762 						      (uchar)(asc_dvc->
6763 							      max_sdtr_index -
6764 							      1)],
6765 				      (uchar)(sdtr_data & (uchar)
6766 					      ASC_SYN_MAX_OFFSET));
6767 		}
6768 
6769 		AscWriteLramByte(iop_base,
6770 				 (ushort)(halt_q_addr +
6771 					  (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6772 
6773 		tag_code = AscReadLramByte(iop_base,
6774 					   (ushort)(halt_q_addr + (ushort)
6775 						    ASC_SCSIQ_B_TAG_CODE));
6776 		tag_code &= 0xDC;
6777 		if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6778 		    && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6779 		    ) {
6780 
6781 			tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6782 				     | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6783 
6784 		}
6785 		AscWriteLramByte(iop_base,
6786 				 (ushort)(halt_q_addr +
6787 					  (ushort)ASC_SCSIQ_B_TAG_CODE),
6788 				 tag_code);
6789 
6790 		q_status = AscReadLramByte(iop_base,
6791 					   (ushort)(halt_q_addr + (ushort)
6792 						    ASC_SCSIQ_B_STATUS));
6793 		q_status |= (QS_READY | QS_BUSY);
6794 		AscWriteLramByte(iop_base,
6795 				 (ushort)(halt_q_addr +
6796 					  (ushort)ASC_SCSIQ_B_STATUS),
6797 				 q_status);
6798 
6799 		scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6800 		scsi_busy &= ~target_id;
6801 		AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6802 
6803 		AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6804 		return (0);
6805 	} else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6806 
6807 		AscMemWordCopyPtrFromLram(iop_base,
6808 					  ASCV_MSGOUT_BEG,
6809 					  (uchar *)&out_msg,
6810 					  sizeof(EXT_MSG) >> 1);
6811 
6812 		if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6813 		    (out_msg.msg_len == MS_SDTR_LEN) &&
6814 		    (out_msg.msg_req == EXTENDED_SDTR)) {
6815 
6816 			asc_dvc->init_sdtr &= ~target_id;
6817 			asc_dvc->sdtr_done &= ~target_id;
6818 			AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6819 			boardp->sdtr_data[tid_no] = asyn_sdtr;
6820 		}
6821 		q_cntl &= ~QC_MSG_OUT;
6822 		AscWriteLramByte(iop_base,
6823 				 (ushort)(halt_q_addr +
6824 					  (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6825 		AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6826 		return (0);
6827 	} else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6828 
6829 		scsi_status = AscReadLramByte(iop_base,
6830 					      (ushort)((ushort)halt_q_addr +
6831 						       (ushort)
6832 						       ASC_SCSIQ_SCSI_STATUS));
6833 		cur_dvc_qng =
6834 		    AscReadLramByte(iop_base,
6835 				    (ushort)((ushort)ASC_QADR_BEG +
6836 					     (ushort)target_ix));
6837 		if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6838 
6839 			scsi_busy = AscReadLramByte(iop_base,
6840 						    (ushort)ASCV_SCSIBUSY_B);
6841 			scsi_busy |= target_id;
6842 			AscWriteLramByte(iop_base,
6843 					 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6844 			asc_dvc->queue_full_or_busy |= target_id;
6845 
6846 			if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6847 				if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6848 					cur_dvc_qng -= 1;
6849 					asc_dvc->max_dvc_qng[tid_no] =
6850 					    cur_dvc_qng;
6851 
6852 					AscWriteLramByte(iop_base,
6853 							 (ushort)((ushort)
6854 								  ASCV_MAX_DVC_QNG_BEG
6855 								  + (ushort)
6856 								  tid_no),
6857 							 cur_dvc_qng);
6858 
6859 					/*
6860 					 * Set the device queue depth to the
6861 					 * number of active requests when the
6862 					 * QUEUE FULL condition was encountered.
6863 					 */
6864 					boardp->queue_full |= target_id;
6865 					boardp->queue_full_cnt[tid_no] =
6866 					    cur_dvc_qng;
6867 				}
6868 			}
6869 		}
6870 		AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6871 		return (0);
6872 	}
6873 #if CC_VERY_LONG_SG_LIST
6874 	else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6875 		uchar q_no;
6876 		ushort q_addr;
6877 		uchar sg_wk_q_no;
6878 		uchar first_sg_wk_q_no;
6879 		ASC_SCSI_Q *scsiq;	/* Ptr to driver request. */
6880 		ASC_SG_HEAD *sg_head;	/* Ptr to driver SG request. */
6881 		ASC_SG_LIST_Q scsi_sg_q;	/* Structure written to queue. */
6882 		ushort sg_list_dwords;
6883 		ushort sg_entry_cnt;
6884 		uchar next_qp;
6885 		int i;
6886 
6887 		q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6888 		if (q_no == ASC_QLINK_END)
6889 			return 0;
6890 
6891 		q_addr = ASC_QNO_TO_QADDR(q_no);
6892 
6893 		/*
6894 		 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6895 		 * structure pointer using a macro provided by the driver.
6896 		 * The ASC_SCSI_REQ pointer provides a pointer to the
6897 		 * host ASC_SG_HEAD structure.
6898 		 */
6899 		/* Read request's SRB pointer. */
6900 		scsiq = (ASC_SCSI_Q *)
6901 		    ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6902 								    (ushort)
6903 								    (q_addr +
6904 								     ASC_SCSIQ_D_SRBPTR))));
6905 
6906 		/*
6907 		 * Get request's first and working SG queue.
6908 		 */
6909 		sg_wk_q_no = AscReadLramByte(iop_base,
6910 					     (ushort)(q_addr +
6911 						      ASC_SCSIQ_B_SG_WK_QP));
6912 
6913 		first_sg_wk_q_no = AscReadLramByte(iop_base,
6914 						   (ushort)(q_addr +
6915 							    ASC_SCSIQ_B_FIRST_SG_WK_QP));
6916 
6917 		/*
6918 		 * Reset request's working SG queue back to the
6919 		 * first SG queue.
6920 		 */
6921 		AscWriteLramByte(iop_base,
6922 				 (ushort)(q_addr +
6923 					  (ushort)ASC_SCSIQ_B_SG_WK_QP),
6924 				 first_sg_wk_q_no);
6925 
6926 		sg_head = scsiq->sg_head;
6927 
6928 		/*
6929 		 * Set sg_entry_cnt to the number of SG elements
6930 		 * that will be completed on this interrupt.
6931 		 *
6932 		 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6933 		 * SG elements. The data_cnt and data_addr fields which
6934 		 * add 1 to the SG element capacity are not used when
6935 		 * restarting SG handling after a halt.
6936 		 */
6937 		if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6938 			sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6939 
6940 			/*
6941 			 * Keep track of remaining number of SG elements that
6942 			 * will need to be handled on the next interrupt.
6943 			 */
6944 			scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6945 		} else {
6946 			sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6947 			scsiq->remain_sg_entry_cnt = 0;
6948 		}
6949 
6950 		/*
6951 		 * Copy SG elements into the list of allocated SG queues.
6952 		 *
6953 		 * Last index completed is saved in scsiq->next_sg_index.
6954 		 */
6955 		next_qp = first_sg_wk_q_no;
6956 		q_addr = ASC_QNO_TO_QADDR(next_qp);
6957 		scsi_sg_q.sg_head_qp = q_no;
6958 		scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6959 		for (i = 0; i < sg_head->queue_cnt; i++) {
6960 			scsi_sg_q.seq_no = i + 1;
6961 			if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6962 				sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6963 				sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6964 				/*
6965 				 * After very first SG queue RISC FW uses next
6966 				 * SG queue first element then checks sg_list_cnt
6967 				 * against zero and then decrements, so set
6968 				 * sg_list_cnt 1 less than number of SG elements
6969 				 * in each SG queue.
6970 				 */
6971 				scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6972 				scsi_sg_q.sg_cur_list_cnt =
6973 				    ASC_SG_LIST_PER_Q - 1;
6974 			} else {
6975 				/*
6976 				 * This is the last SG queue in the list of
6977 				 * allocated SG queues. If there are more
6978 				 * SG elements than will fit in the allocated
6979 				 * queues, then set the QCSG_SG_XFER_MORE flag.
6980 				 */
6981 				if (scsiq->remain_sg_entry_cnt != 0) {
6982 					scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6983 				} else {
6984 					scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6985 				}
6986 				/* equals sg_entry_cnt * 2 */
6987 				sg_list_dwords = sg_entry_cnt << 1;
6988 				scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6989 				scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6990 				sg_entry_cnt = 0;
6991 			}
6992 
6993 			scsi_sg_q.q_no = next_qp;
6994 			AscMemWordCopyPtrToLram(iop_base,
6995 						q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6996 						(uchar *)&scsi_sg_q,
6997 						sizeof(ASC_SG_LIST_Q) >> 1);
6998 
6999 			AscMemDWordCopyPtrToLram(iop_base,
7000 						 q_addr + ASC_SGQ_LIST_BEG,
7001 						 (uchar *)&sg_head->
7002 						 sg_list[scsiq->next_sg_index],
7003 						 sg_list_dwords);
7004 
7005 			scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
7006 
7007 			/*
7008 			 * If the just completed SG queue contained the
7009 			 * last SG element, then no more SG queues need
7010 			 * to be written.
7011 			 */
7012 			if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
7013 				break;
7014 			}
7015 
7016 			next_qp = AscReadLramByte(iop_base,
7017 						  (ushort)(q_addr +
7018 							   ASC_SCSIQ_B_FWD));
7019 			q_addr = ASC_QNO_TO_QADDR(next_qp);
7020 		}
7021 
7022 		/*
7023 		 * Clear the halt condition so the RISC will be restarted
7024 		 * after the return.
7025 		 */
7026 		AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7027 		return (0);
7028 	}
7029 #endif /* CC_VERY_LONG_SG_LIST */
7030 	return (0);
7031 }
7032 
7033 /*
7034  * void
7035  * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7036  *
7037  * Calling/Exit State:
7038  *    none
7039  *
7040  * Description:
7041  *     Input an ASC_QDONE_INFO structure from the chip
7042  */
7043 static void
7044 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7045 {
7046 	int i;
7047 	ushort word;
7048 
7049 	AscSetChipLramAddr(iop_base, s_addr);
7050 	for (i = 0; i < 2 * words; i += 2) {
7051 		if (i == 10) {
7052 			continue;
7053 		}
7054 		word = inpw(iop_base + IOP_RAM_DATA);
7055 		inbuf[i] = word & 0xff;
7056 		inbuf[i + 1] = (word >> 8) & 0xff;
7057 	}
7058 	ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
7059 }
7060 
7061 static uchar
7062 _AscCopyLramScsiDoneQ(PortAddr iop_base,
7063 		      ushort q_addr,
7064 		      ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
7065 {
7066 	ushort _val;
7067 	uchar sg_queue_cnt;
7068 
7069 	DvcGetQinfo(iop_base,
7070 		    q_addr + ASC_SCSIQ_DONE_INFO_BEG,
7071 		    (uchar *)scsiq,
7072 		    (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
7073 
7074 	_val = AscReadLramWord(iop_base,
7075 			       (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
7076 	scsiq->q_status = (uchar)_val;
7077 	scsiq->q_no = (uchar)(_val >> 8);
7078 	_val = AscReadLramWord(iop_base,
7079 			       (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
7080 	scsiq->cntl = (uchar)_val;
7081 	sg_queue_cnt = (uchar)(_val >> 8);
7082 	_val = AscReadLramWord(iop_base,
7083 			       (ushort)(q_addr +
7084 					(ushort)ASC_SCSIQ_B_SENSE_LEN));
7085 	scsiq->sense_len = (uchar)_val;
7086 	scsiq->extra_bytes = (uchar)(_val >> 8);
7087 
7088 	/*
7089 	 * Read high word of remain bytes from alternate location.
7090 	 */
7091 	scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
7092 							  (ushort)(q_addr +
7093 								   (ushort)
7094 								   ASC_SCSIQ_W_ALT_DC1)))
7095 			       << 16);
7096 	/*
7097 	 * Read low word of remain bytes from original location.
7098 	 */
7099 	scsiq->remain_bytes += AscReadLramWord(iop_base,
7100 					       (ushort)(q_addr + (ushort)
7101 							ASC_SCSIQ_DW_REMAIN_XFER_CNT));
7102 
7103 	scsiq->remain_bytes &= max_dma_count;
7104 	return sg_queue_cnt;
7105 }
7106 
7107 /*
7108  * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
7109  *
7110  * Interrupt callback function for the Narrow SCSI Asc Library.
7111  */
7112 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
7113 {
7114 	struct asc_board *boardp;
7115 	struct scsi_cmnd *scp;
7116 	struct Scsi_Host *shost;
7117 
7118 	ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
7119 	ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
7120 
7121 	scp = advansys_srb_to_ptr(asc_dvc_varp, qdonep->d2.srb_ptr);
7122 	if (!scp)
7123 		return;
7124 
7125 	ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7126 
7127 	shost = scp->device->host;
7128 	ASC_STATS(shost, callback);
7129 	ASC_DBG(1, "shost 0x%p\n", shost);
7130 
7131 	boardp = shost_priv(shost);
7132 	BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
7133 
7134 	dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
7135 			 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7136 	/*
7137 	 * 'qdonep' contains the command's ending status.
7138 	 */
7139 	switch (qdonep->d3.done_stat) {
7140 	case QD_NO_ERROR:
7141 		ASC_DBG(2, "QD_NO_ERROR\n");
7142 		scp->result = 0;
7143 
7144 		/*
7145 		 * Check for an underrun condition.
7146 		 *
7147 		 * If there was no error and an underrun condition, then
7148 		 * return the number of underrun bytes.
7149 		 */
7150 		if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7151 		    qdonep->remain_bytes <= scsi_bufflen(scp)) {
7152 			ASC_DBG(1, "underrun condition %u bytes\n",
7153 				 (unsigned)qdonep->remain_bytes);
7154 			scsi_set_resid(scp, qdonep->remain_bytes);
7155 		}
7156 		break;
7157 
7158 	case QD_WITH_ERROR:
7159 		ASC_DBG(2, "QD_WITH_ERROR\n");
7160 		switch (qdonep->d3.host_stat) {
7161 		case QHSTA_NO_ERROR:
7162 			if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
7163 				ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
7164 				ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7165 						  SCSI_SENSE_BUFFERSIZE);
7166 				/*
7167 				 * Note: The 'status_byte()' macro used by
7168 				 * target drivers defined in scsi.h shifts the
7169 				 * status byte returned by host drivers right
7170 				 * by 1 bit.  This is why target drivers also
7171 				 * use right shifted status byte definitions.
7172 				 * For instance target drivers use
7173 				 * CHECK_CONDITION, defined to 0x1, instead of
7174 				 * the SCSI defined check condition value of
7175 				 * 0x2. Host drivers are supposed to return
7176 				 * the status byte as it is defined by SCSI.
7177 				 */
7178 				scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7179 				    STATUS_BYTE(qdonep->d3.scsi_stat);
7180 			} else {
7181 				scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7182 			}
7183 			break;
7184 
7185 		default:
7186 			/* QHSTA error occurred */
7187 			ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
7188 			scp->result = HOST_BYTE(DID_BAD_TARGET);
7189 			break;
7190 		}
7191 		break;
7192 
7193 	case QD_ABORTED_BY_HOST:
7194 		ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
7195 		scp->result =
7196 		    HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7197 						    scsi_msg) |
7198 		    STATUS_BYTE(qdonep->d3.scsi_stat);
7199 		break;
7200 
7201 	default:
7202 		ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
7203 		scp->result =
7204 		    HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7205 						    scsi_msg) |
7206 		    STATUS_BYTE(qdonep->d3.scsi_stat);
7207 		break;
7208 	}
7209 
7210 	/*
7211 	 * If the 'init_tidmask' bit isn't already set for the target and the
7212 	 * current request finished normally, then set the bit for the target
7213 	 * to indicate that a device is present.
7214 	 */
7215 	if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7216 	    qdonep->d3.done_stat == QD_NO_ERROR &&
7217 	    qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7218 		boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7219 	}
7220 
7221 	asc_scsi_done(scp);
7222 }
7223 
7224 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7225 {
7226 	uchar next_qp;
7227 	uchar n_q_used;
7228 	uchar sg_list_qp;
7229 	uchar sg_queue_cnt;
7230 	uchar q_cnt;
7231 	uchar done_q_tail;
7232 	uchar tid_no;
7233 	ASC_SCSI_BIT_ID_TYPE scsi_busy;
7234 	ASC_SCSI_BIT_ID_TYPE target_id;
7235 	PortAddr iop_base;
7236 	ushort q_addr;
7237 	ushort sg_q_addr;
7238 	uchar cur_target_qng;
7239 	ASC_QDONE_INFO scsiq_buf;
7240 	ASC_QDONE_INFO *scsiq;
7241 	int false_overrun;
7242 
7243 	iop_base = asc_dvc->iop_base;
7244 	n_q_used = 1;
7245 	scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7246 	done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7247 	q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7248 	next_qp = AscReadLramByte(iop_base,
7249 				  (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7250 	if (next_qp != ASC_QLINK_END) {
7251 		AscPutVarDoneQTail(iop_base, next_qp);
7252 		q_addr = ASC_QNO_TO_QADDR(next_qp);
7253 		sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7254 						     asc_dvc->max_dma_count);
7255 		AscWriteLramByte(iop_base,
7256 				 (ushort)(q_addr +
7257 					  (ushort)ASC_SCSIQ_B_STATUS),
7258 				 (uchar)(scsiq->
7259 					 q_status & (uchar)~(QS_READY |
7260 							     QS_ABORTED)));
7261 		tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7262 		target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7263 		if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7264 			sg_q_addr = q_addr;
7265 			sg_list_qp = next_qp;
7266 			for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7267 				sg_list_qp = AscReadLramByte(iop_base,
7268 							     (ushort)(sg_q_addr
7269 								      + (ushort)
7270 								      ASC_SCSIQ_B_FWD));
7271 				sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7272 				if (sg_list_qp == ASC_QLINK_END) {
7273 					AscSetLibErrorCode(asc_dvc,
7274 							   ASCQ_ERR_SG_Q_LINKS);
7275 					scsiq->d3.done_stat = QD_WITH_ERROR;
7276 					scsiq->d3.host_stat =
7277 					    QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7278 					goto FATAL_ERR_QDONE;
7279 				}
7280 				AscWriteLramByte(iop_base,
7281 						 (ushort)(sg_q_addr + (ushort)
7282 							  ASC_SCSIQ_B_STATUS),
7283 						 QS_FREE);
7284 			}
7285 			n_q_used = sg_queue_cnt + 1;
7286 			AscPutVarDoneQTail(iop_base, sg_list_qp);
7287 		}
7288 		if (asc_dvc->queue_full_or_busy & target_id) {
7289 			cur_target_qng = AscReadLramByte(iop_base,
7290 							 (ushort)((ushort)
7291 								  ASC_QADR_BEG
7292 								  + (ushort)
7293 								  scsiq->d2.
7294 								  target_ix));
7295 			if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7296 				scsi_busy = AscReadLramByte(iop_base, (ushort)
7297 							    ASCV_SCSIBUSY_B);
7298 				scsi_busy &= ~target_id;
7299 				AscWriteLramByte(iop_base,
7300 						 (ushort)ASCV_SCSIBUSY_B,
7301 						 scsi_busy);
7302 				asc_dvc->queue_full_or_busy &= ~target_id;
7303 			}
7304 		}
7305 		if (asc_dvc->cur_total_qng >= n_q_used) {
7306 			asc_dvc->cur_total_qng -= n_q_used;
7307 			if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7308 				asc_dvc->cur_dvc_qng[tid_no]--;
7309 			}
7310 		} else {
7311 			AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7312 			scsiq->d3.done_stat = QD_WITH_ERROR;
7313 			goto FATAL_ERR_QDONE;
7314 		}
7315 		if ((scsiq->d2.srb_ptr == 0UL) ||
7316 		    ((scsiq->q_status & QS_ABORTED) != 0)) {
7317 			return (0x11);
7318 		} else if (scsiq->q_status == QS_DONE) {
7319 			false_overrun = FALSE;
7320 			if (scsiq->extra_bytes != 0) {
7321 				scsiq->remain_bytes +=
7322 				    (ADV_DCNT)scsiq->extra_bytes;
7323 			}
7324 			if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7325 				if (scsiq->d3.host_stat ==
7326 				    QHSTA_M_DATA_OVER_RUN) {
7327 					if ((scsiq->
7328 					     cntl & (QC_DATA_IN | QC_DATA_OUT))
7329 					    == 0) {
7330 						scsiq->d3.done_stat =
7331 						    QD_NO_ERROR;
7332 						scsiq->d3.host_stat =
7333 						    QHSTA_NO_ERROR;
7334 					} else if (false_overrun) {
7335 						scsiq->d3.done_stat =
7336 						    QD_NO_ERROR;
7337 						scsiq->d3.host_stat =
7338 						    QHSTA_NO_ERROR;
7339 					}
7340 				} else if (scsiq->d3.host_stat ==
7341 					   QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7342 					AscStopChip(iop_base);
7343 					AscSetChipControl(iop_base,
7344 							  (uchar)(CC_SCSI_RESET
7345 								  | CC_HALT));
7346 					udelay(60);
7347 					AscSetChipControl(iop_base, CC_HALT);
7348 					AscSetChipStatus(iop_base,
7349 							 CIW_CLR_SCSI_RESET_INT);
7350 					AscSetChipStatus(iop_base, 0);
7351 					AscSetChipControl(iop_base, 0);
7352 				}
7353 			}
7354 			if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7355 				asc_isr_callback(asc_dvc, scsiq);
7356 			} else {
7357 				if ((AscReadLramByte(iop_base,
7358 						     (ushort)(q_addr + (ushort)
7359 							      ASC_SCSIQ_CDB_BEG))
7360 				     == START_STOP)) {
7361 					asc_dvc->unit_not_ready &= ~target_id;
7362 					if (scsiq->d3.done_stat != QD_NO_ERROR) {
7363 						asc_dvc->start_motor &=
7364 						    ~target_id;
7365 					}
7366 				}
7367 			}
7368 			return (1);
7369 		} else {
7370 			AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7371  FATAL_ERR_QDONE:
7372 			if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7373 				asc_isr_callback(asc_dvc, scsiq);
7374 			}
7375 			return (0x80);
7376 		}
7377 	}
7378 	return (0);
7379 }
7380 
7381 static int AscISR(ASC_DVC_VAR *asc_dvc)
7382 {
7383 	ASC_CS_TYPE chipstat;
7384 	PortAddr iop_base;
7385 	ushort saved_ram_addr;
7386 	uchar ctrl_reg;
7387 	uchar saved_ctrl_reg;
7388 	int int_pending;
7389 	int status;
7390 	uchar host_flag;
7391 
7392 	iop_base = asc_dvc->iop_base;
7393 	int_pending = FALSE;
7394 
7395 	if (AscIsIntPending(iop_base) == 0)
7396 		return int_pending;
7397 
7398 	if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7399 		return ERR;
7400 	}
7401 	if (asc_dvc->in_critical_cnt != 0) {
7402 		AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7403 		return ERR;
7404 	}
7405 	if (asc_dvc->is_in_int) {
7406 		AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7407 		return ERR;
7408 	}
7409 	asc_dvc->is_in_int = TRUE;
7410 	ctrl_reg = AscGetChipControl(iop_base);
7411 	saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7412 				       CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7413 	chipstat = AscGetChipStatus(iop_base);
7414 	if (chipstat & CSW_SCSI_RESET_LATCH) {
7415 		if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7416 			int i = 10;
7417 			int_pending = TRUE;
7418 			asc_dvc->sdtr_done = 0;
7419 			saved_ctrl_reg &= (uchar)(~CC_HALT);
7420 			while ((AscGetChipStatus(iop_base) &
7421 				CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7422 				mdelay(100);
7423 			}
7424 			AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7425 			AscSetChipControl(iop_base, CC_HALT);
7426 			AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7427 			AscSetChipStatus(iop_base, 0);
7428 			chipstat = AscGetChipStatus(iop_base);
7429 		}
7430 	}
7431 	saved_ram_addr = AscGetChipLramAddr(iop_base);
7432 	host_flag = AscReadLramByte(iop_base,
7433 				    ASCV_HOST_FLAG_B) &
7434 	    (uchar)(~ASC_HOST_FLAG_IN_ISR);
7435 	AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7436 			 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7437 	if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7438 		AscAckInterrupt(iop_base);
7439 		int_pending = TRUE;
7440 		if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7441 			if (AscIsrChipHalted(asc_dvc) == ERR) {
7442 				goto ISR_REPORT_QDONE_FATAL_ERROR;
7443 			} else {
7444 				saved_ctrl_reg &= (uchar)(~CC_HALT);
7445 			}
7446 		} else {
7447  ISR_REPORT_QDONE_FATAL_ERROR:
7448 			if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7449 				while (((status =
7450 					 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7451 				}
7452 			} else {
7453 				do {
7454 					if ((status =
7455 					     AscIsrQDone(asc_dvc)) == 1) {
7456 						break;
7457 					}
7458 				} while (status == 0x11);
7459 			}
7460 			if ((status & 0x80) != 0)
7461 				int_pending = ERR;
7462 		}
7463 	}
7464 	AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7465 	AscSetChipLramAddr(iop_base, saved_ram_addr);
7466 	AscSetChipControl(iop_base, saved_ctrl_reg);
7467 	asc_dvc->is_in_int = FALSE;
7468 	return int_pending;
7469 }
7470 
7471 /*
7472  * advansys_reset()
7473  *
7474  * Reset the bus associated with the command 'scp'.
7475  *
7476  * This function runs its own thread. Interrupts must be blocked but
7477  * sleeping is allowed and no locking other than for host structures is
7478  * required. Returns SUCCESS or FAILED.
7479  */
7480 static int advansys_reset(struct scsi_cmnd *scp)
7481 {
7482 	struct Scsi_Host *shost = scp->device->host;
7483 	struct asc_board *boardp = shost_priv(shost);
7484 	unsigned long flags;
7485 	int status;
7486 	int ret = SUCCESS;
7487 
7488 	ASC_DBG(1, "0x%p\n", scp);
7489 
7490 	ASC_STATS(shost, reset);
7491 
7492 	scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
7493 
7494 	if (ASC_NARROW_BOARD(boardp)) {
7495 		ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7496 
7497 		/* Reset the chip and SCSI bus. */
7498 		ASC_DBG(1, "before AscInitAsc1000Driver()\n");
7499 		status = AscInitAsc1000Driver(asc_dvc);
7500 
7501 		/* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
7502 		if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
7503 			scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
7504 				    "0x%x, status: 0x%x\n", asc_dvc->err_code,
7505 				    status);
7506 			ret = FAILED;
7507 		} else if (status) {
7508 			scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
7509 				    "0x%x\n", status);
7510 		} else {
7511 			scmd_printk(KERN_INFO, scp, "SCSI bus reset "
7512 				    "successful\n");
7513 		}
7514 
7515 		ASC_DBG(1, "after AscInitAsc1000Driver()\n");
7516 		spin_lock_irqsave(shost->host_lock, flags);
7517 	} else {
7518 		/*
7519 		 * If the suggest reset bus flags are set, then reset the bus.
7520 		 * Otherwise only reset the device.
7521 		 */
7522 		ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
7523 
7524 		/*
7525 		 * Reset the target's SCSI bus.
7526 		 */
7527 		ASC_DBG(1, "before AdvResetChipAndSB()\n");
7528 		switch (AdvResetChipAndSB(adv_dvc)) {
7529 		case ASC_TRUE:
7530 			scmd_printk(KERN_INFO, scp, "SCSI bus reset "
7531 				    "successful\n");
7532 			break;
7533 		case ASC_FALSE:
7534 		default:
7535 			scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
7536 			ret = FAILED;
7537 			break;
7538 		}
7539 		spin_lock_irqsave(shost->host_lock, flags);
7540 		AdvISR(adv_dvc);
7541 	}
7542 
7543 	/* Save the time of the most recently completed reset. */
7544 	boardp->last_reset = jiffies;
7545 	spin_unlock_irqrestore(shost->host_lock, flags);
7546 
7547 	ASC_DBG(1, "ret %d\n", ret);
7548 
7549 	return ret;
7550 }
7551 
7552 /*
7553  * advansys_biosparam()
7554  *
7555  * Translate disk drive geometry if the "BIOS greater than 1 GB"
7556  * support is enabled for a drive.
7557  *
7558  * ip (information pointer) is an int array with the following definition:
7559  * ip[0]: heads
7560  * ip[1]: sectors
7561  * ip[2]: cylinders
7562  */
7563 static int
7564 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7565 		   sector_t capacity, int ip[])
7566 {
7567 	struct asc_board *boardp = shost_priv(sdev->host);
7568 
7569 	ASC_DBG(1, "begin\n");
7570 	ASC_STATS(sdev->host, biosparam);
7571 	if (ASC_NARROW_BOARD(boardp)) {
7572 		if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7573 		     ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7574 			ip[0] = 255;
7575 			ip[1] = 63;
7576 		} else {
7577 			ip[0] = 64;
7578 			ip[1] = 32;
7579 		}
7580 	} else {
7581 		if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7582 		     BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7583 			ip[0] = 255;
7584 			ip[1] = 63;
7585 		} else {
7586 			ip[0] = 64;
7587 			ip[1] = 32;
7588 		}
7589 	}
7590 	ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
7591 	ASC_DBG(1, "end\n");
7592 	return 0;
7593 }
7594 
7595 /*
7596  * First-level interrupt handler.
7597  *
7598  * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7599  */
7600 static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7601 {
7602 	struct Scsi_Host *shost = dev_id;
7603 	struct asc_board *boardp = shost_priv(shost);
7604 	irqreturn_t result = IRQ_NONE;
7605 
7606 	ASC_DBG(2, "boardp 0x%p\n", boardp);
7607 	spin_lock(shost->host_lock);
7608 	if (ASC_NARROW_BOARD(boardp)) {
7609 		if (AscIsIntPending(shost->io_port)) {
7610 			result = IRQ_HANDLED;
7611 			ASC_STATS(shost, interrupt);
7612 			ASC_DBG(1, "before AscISR()\n");
7613 			AscISR(&boardp->dvc_var.asc_dvc_var);
7614 		}
7615 	} else {
7616 		ASC_DBG(1, "before AdvISR()\n");
7617 		if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7618 			result = IRQ_HANDLED;
7619 			ASC_STATS(shost, interrupt);
7620 		}
7621 	}
7622 	spin_unlock(shost->host_lock);
7623 
7624 	ASC_DBG(1, "end\n");
7625 	return result;
7626 }
7627 
7628 static int AscHostReqRiscHalt(PortAddr iop_base)
7629 {
7630 	int count = 0;
7631 	int sta = 0;
7632 	uchar saved_stop_code;
7633 
7634 	if (AscIsChipHalted(iop_base))
7635 		return (1);
7636 	saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7637 	AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7638 			 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7639 	do {
7640 		if (AscIsChipHalted(iop_base)) {
7641 			sta = 1;
7642 			break;
7643 		}
7644 		mdelay(100);
7645 	} while (count++ < 20);
7646 	AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7647 	return (sta);
7648 }
7649 
7650 static int
7651 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7652 {
7653 	int sta = FALSE;
7654 
7655 	if (AscHostReqRiscHalt(iop_base)) {
7656 		sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7657 		AscStartChip(iop_base);
7658 	}
7659 	return sta;
7660 }
7661 
7662 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7663 {
7664 	char type = sdev->type;
7665 	ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
7666 
7667 	if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7668 		return;
7669 	if (asc_dvc->init_sdtr & tid_bits)
7670 		return;
7671 
7672 	if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7673 		asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
7674 
7675 	asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7676 	if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7677 	    (type == TYPE_ROM) || (type == TYPE_TAPE))
7678 		asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7679 
7680 	if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7681 		AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7682 					ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7683 }
7684 
7685 static void
7686 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7687 {
7688 	ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7689 	ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
7690 
7691 	if (sdev->lun == 0) {
7692 		ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7693 		if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7694 			asc_dvc->init_sdtr |= tid_bit;
7695 		} else {
7696 			asc_dvc->init_sdtr &= ~tid_bit;
7697 		}
7698 
7699 		if (orig_init_sdtr != asc_dvc->init_sdtr)
7700 			AscAsyncFix(asc_dvc, sdev);
7701 	}
7702 
7703 	if (sdev->tagged_supported) {
7704 		if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7705 			if (sdev->lun == 0) {
7706 				asc_dvc->cfg->can_tagged_qng |= tid_bit;
7707 				asc_dvc->use_tagged_qng |= tid_bit;
7708 			}
7709 			scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
7710 						asc_dvc->max_dvc_qng[sdev->id]);
7711 		}
7712 	} else {
7713 		if (sdev->lun == 0) {
7714 			asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7715 			asc_dvc->use_tagged_qng &= ~tid_bit;
7716 		}
7717 		scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
7718 	}
7719 
7720 	if ((sdev->lun == 0) &&
7721 	    (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7722 		AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7723 				 asc_dvc->cfg->disc_enable);
7724 		AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7725 				 asc_dvc->use_tagged_qng);
7726 		AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7727 				 asc_dvc->cfg->can_tagged_qng);
7728 
7729 		asc_dvc->max_dvc_qng[sdev->id] =
7730 					asc_dvc->cfg->max_tag_qng[sdev->id];
7731 		AscWriteLramByte(asc_dvc->iop_base,
7732 				 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7733 				 asc_dvc->max_dvc_qng[sdev->id]);
7734 	}
7735 }
7736 
7737 /*
7738  * Wide Transfers
7739  *
7740  * If the EEPROM enabled WDTR for the device and the device supports wide
7741  * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7742  * write the new value to the microcode.
7743  */
7744 static void
7745 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7746 {
7747 	unsigned short cfg_word;
7748 	AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7749 	if ((cfg_word & tidmask) != 0)
7750 		return;
7751 
7752 	cfg_word |= tidmask;
7753 	AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7754 
7755 	/*
7756 	 * Clear the microcode SDTR and WDTR negotiation done indicators for
7757 	 * the target to cause it to negotiate with the new setting set above.
7758 	 * WDTR when accepted causes the target to enter asynchronous mode, so
7759 	 * SDTR must be negotiated.
7760 	 */
7761 	AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7762 	cfg_word &= ~tidmask;
7763 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7764 	AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7765 	cfg_word &= ~tidmask;
7766 	AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7767 }
7768 
7769 /*
7770  * Synchronous Transfers
7771  *
7772  * If the EEPROM enabled SDTR for the device and the device
7773  * supports synchronous transfers, then turn on the device's
7774  * 'sdtr_able' bit. Write the new value to the microcode.
7775  */
7776 static void
7777 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7778 {
7779 	unsigned short cfg_word;
7780 	AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7781 	if ((cfg_word & tidmask) != 0)
7782 		return;
7783 
7784 	cfg_word |= tidmask;
7785 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7786 
7787 	/*
7788 	 * Clear the microcode "SDTR negotiation" done indicator for the
7789 	 * target to cause it to negotiate with the new setting set above.
7790 	 */
7791 	AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7792 	cfg_word &= ~tidmask;
7793 	AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7794 }
7795 
7796 /*
7797  * PPR (Parallel Protocol Request) Capable
7798  *
7799  * If the device supports DT mode, then it must be PPR capable.
7800  * The PPR message will be used in place of the SDTR and WDTR
7801  * messages to negotiate synchronous speed and offset, transfer
7802  * width, and protocol options.
7803  */
7804 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7805 				AdvPortAddr iop_base, unsigned short tidmask)
7806 {
7807 	AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7808 	adv_dvc->ppr_able |= tidmask;
7809 	AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7810 }
7811 
7812 static void
7813 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7814 {
7815 	AdvPortAddr iop_base = adv_dvc->iop_base;
7816 	unsigned short tidmask = 1 << sdev->id;
7817 
7818 	if (sdev->lun == 0) {
7819 		/*
7820 		 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7821 		 * is enabled in the EEPROM and the device supports the
7822 		 * feature, then enable it in the microcode.
7823 		 */
7824 
7825 		if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7826 			advansys_wide_enable_wdtr(iop_base, tidmask);
7827 		if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7828 			advansys_wide_enable_sdtr(iop_base, tidmask);
7829 		if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7830 			advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7831 
7832 		/*
7833 		 * Tag Queuing is disabled for the BIOS which runs in polled
7834 		 * mode and would see no benefit from Tag Queuing. Also by
7835 		 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7836 		 * bugs will at least work with the BIOS.
7837 		 */
7838 		if ((adv_dvc->tagqng_able & tidmask) &&
7839 		    sdev->tagged_supported) {
7840 			unsigned short cfg_word;
7841 			AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7842 			cfg_word |= tidmask;
7843 			AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7844 					 cfg_word);
7845 			AdvWriteByteLram(iop_base,
7846 					 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7847 					 adv_dvc->max_dvc_qng);
7848 		}
7849 	}
7850 
7851 	if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) {
7852 		scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG,
7853 					adv_dvc->max_dvc_qng);
7854 	} else {
7855 		scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
7856 	}
7857 }
7858 
7859 /*
7860  * Set the number of commands to queue per device for the
7861  * specified host adapter.
7862  */
7863 static int advansys_slave_configure(struct scsi_device *sdev)
7864 {
7865 	struct asc_board *boardp = shost_priv(sdev->host);
7866 
7867 	if (ASC_NARROW_BOARD(boardp))
7868 		advansys_narrow_slave_configure(sdev,
7869 						&boardp->dvc_var.asc_dvc_var);
7870 	else
7871 		advansys_wide_slave_configure(sdev,
7872 						&boardp->dvc_var.adv_dvc_var);
7873 
7874 	return 0;
7875 }
7876 
7877 static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7878 {
7879 	struct asc_board *board = shost_priv(scp->device->host);
7880 	scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
7881 					     SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7882 	dma_cache_sync(board->dev, scp->sense_buffer,
7883 		       SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
7884 	return cpu_to_le32(scp->SCp.dma_handle);
7885 }
7886 
7887 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
7888 			struct asc_scsi_q *asc_scsi_q)
7889 {
7890 	struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
7891 	int use_sg;
7892 
7893 	memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
7894 
7895 	/*
7896 	 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
7897 	 */
7898 	asc_scsi_q->q2.srb_ptr = advansys_ptr_to_srb(asc_dvc, scp);
7899 	if (asc_scsi_q->q2.srb_ptr == BAD_SRB) {
7900 		scp->result = HOST_BYTE(DID_SOFT_ERROR);
7901 		return ASC_ERROR;
7902 	}
7903 
7904 	/*
7905 	 * Build the ASC_SCSI_Q request.
7906 	 */
7907 	asc_scsi_q->cdbptr = &scp->cmnd[0];
7908 	asc_scsi_q->q2.cdb_len = scp->cmd_len;
7909 	asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7910 	asc_scsi_q->q1.target_lun = scp->device->lun;
7911 	asc_scsi_q->q2.target_ix =
7912 	    ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
7913 	asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
7914 	asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
7915 
7916 	/*
7917 	 * If there are any outstanding requests for the current target,
7918 	 * then every 255th request send an ORDERED request. This heuristic
7919 	 * tries to retain the benefit of request sorting while preventing
7920 	 * request starvation. 255 is the max number of tags or pending commands
7921 	 * a device may have outstanding.
7922 	 *
7923 	 * The request count is incremented below for every successfully
7924 	 * started request.
7925 	 *
7926 	 */
7927 	if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
7928 	    (boardp->reqcnt[scp->device->id] % 255) == 0) {
7929 		asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG;
7930 	} else {
7931 		asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG;
7932 	}
7933 
7934 	/* Build ASC_SCSI_Q */
7935 	use_sg = scsi_dma_map(scp);
7936 	if (use_sg != 0) {
7937 		int sgcnt;
7938 		struct scatterlist *slp;
7939 		struct asc_sg_head *asc_sg_head;
7940 
7941 		if (use_sg > scp->device->host->sg_tablesize) {
7942 			scmd_printk(KERN_ERR, scp, "use_sg %d > "
7943 				"sg_tablesize %d\n", use_sg,
7944 				scp->device->host->sg_tablesize);
7945 			scsi_dma_unmap(scp);
7946 			scp->result = HOST_BYTE(DID_ERROR);
7947 			return ASC_ERROR;
7948 		}
7949 
7950 		asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7951 			use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7952 		if (!asc_sg_head) {
7953 			scsi_dma_unmap(scp);
7954 			scp->result = HOST_BYTE(DID_SOFT_ERROR);
7955 			return ASC_ERROR;
7956 		}
7957 
7958 		asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7959 		asc_scsi_q->sg_head = asc_sg_head;
7960 		asc_scsi_q->q1.data_cnt = 0;
7961 		asc_scsi_q->q1.data_addr = 0;
7962 		/* This is a byte value, otherwise it would need to be swapped. */
7963 		asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
7964 		ASC_STATS_ADD(scp->device->host, xfer_elem,
7965 			      asc_sg_head->entry_cnt);
7966 
7967 		/*
7968 		 * Convert scatter-gather list into ASC_SG_HEAD list.
7969 		 */
7970 		scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
7971 			asc_sg_head->sg_list[sgcnt].addr =
7972 			    cpu_to_le32(sg_dma_address(slp));
7973 			asc_sg_head->sg_list[sgcnt].bytes =
7974 			    cpu_to_le32(sg_dma_len(slp));
7975 			ASC_STATS_ADD(scp->device->host, xfer_sect,
7976 				      DIV_ROUND_UP(sg_dma_len(slp), 512));
7977 		}
7978 	}
7979 
7980 	ASC_STATS(scp->device->host, xfer_cnt);
7981 
7982 	ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
7983 	ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7984 
7985 	return ASC_NOERROR;
7986 }
7987 
7988 /*
7989  * Build scatter-gather list for Adv Library (Wide Board).
7990  *
7991  * Additional ADV_SG_BLOCK structures will need to be allocated
7992  * if the total number of scatter-gather elements exceeds
7993  * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7994  * assumed to be physically contiguous.
7995  *
7996  * Return:
7997  *      ADV_SUCCESS(1) - SG List successfully created
7998  *      ADV_ERROR(-1) - SG List creation failed
7999  */
8000 static int
8001 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
8002 	       int use_sg)
8003 {
8004 	adv_sgblk_t *sgblkp;
8005 	ADV_SCSI_REQ_Q *scsiqp;
8006 	struct scatterlist *slp;
8007 	int sg_elem_cnt;
8008 	ADV_SG_BLOCK *sg_block, *prev_sg_block;
8009 	ADV_PADDR sg_block_paddr;
8010 	int i;
8011 
8012 	scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
8013 	slp = scsi_sglist(scp);
8014 	sg_elem_cnt = use_sg;
8015 	prev_sg_block = NULL;
8016 	reqp->sgblkp = NULL;
8017 
8018 	for (;;) {
8019 		/*
8020 		 * Allocate a 'adv_sgblk_t' structure from the board free
8021 		 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
8022 		 * (15) scatter-gather elements.
8023 		 */
8024 		if ((sgblkp = boardp->adv_sgblkp) == NULL) {
8025 			ASC_DBG(1, "no free adv_sgblk_t\n");
8026 			ASC_STATS(scp->device->host, adv_build_nosg);
8027 
8028 			/*
8029 			 * Allocation failed. Free 'adv_sgblk_t' structures
8030 			 * already allocated for the request.
8031 			 */
8032 			while ((sgblkp = reqp->sgblkp) != NULL) {
8033 				/* Remove 'sgblkp' from the request list. */
8034 				reqp->sgblkp = sgblkp->next_sgblkp;
8035 
8036 				/* Add 'sgblkp' to the board free list. */
8037 				sgblkp->next_sgblkp = boardp->adv_sgblkp;
8038 				boardp->adv_sgblkp = sgblkp;
8039 			}
8040 			return ASC_BUSY;
8041 		}
8042 
8043 		/* Complete 'adv_sgblk_t' board allocation. */
8044 		boardp->adv_sgblkp = sgblkp->next_sgblkp;
8045 		sgblkp->next_sgblkp = NULL;
8046 
8047 		/*
8048 		 * Get 8 byte aligned virtual and physical addresses
8049 		 * for the allocated ADV_SG_BLOCK structure.
8050 		 */
8051 		sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
8052 		sg_block_paddr = virt_to_bus(sg_block);
8053 
8054 		/*
8055 		 * Check if this is the first 'adv_sgblk_t' for the
8056 		 * request.
8057 		 */
8058 		if (reqp->sgblkp == NULL) {
8059 			/* Request's first scatter-gather block. */
8060 			reqp->sgblkp = sgblkp;
8061 
8062 			/*
8063 			 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
8064 			 * address pointers.
8065 			 */
8066 			scsiqp->sg_list_ptr = sg_block;
8067 			scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
8068 		} else {
8069 			/* Request's second or later scatter-gather block. */
8070 			sgblkp->next_sgblkp = reqp->sgblkp;
8071 			reqp->sgblkp = sgblkp;
8072 
8073 			/*
8074 			 * Point the previous ADV_SG_BLOCK structure to
8075 			 * the newly allocated ADV_SG_BLOCK structure.
8076 			 */
8077 			prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
8078 		}
8079 
8080 		for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
8081 			sg_block->sg_list[i].sg_addr =
8082 					cpu_to_le32(sg_dma_address(slp));
8083 			sg_block->sg_list[i].sg_count =
8084 					cpu_to_le32(sg_dma_len(slp));
8085 			ASC_STATS_ADD(scp->device->host, xfer_sect,
8086 				      DIV_ROUND_UP(sg_dma_len(slp), 512));
8087 
8088 			if (--sg_elem_cnt == 0) {	/* Last ADV_SG_BLOCK and scatter-gather entry. */
8089 				sg_block->sg_cnt = i + 1;
8090 				sg_block->sg_ptr = 0L;	/* Last ADV_SG_BLOCK in list. */
8091 				return ADV_SUCCESS;
8092 			}
8093 			slp++;
8094 		}
8095 		sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
8096 		prev_sg_block = sg_block;
8097 	}
8098 }
8099 
8100 /*
8101  * Build a request structure for the Adv Library (Wide Board).
8102  *
8103  * If an adv_req_t can not be allocated to issue the request,
8104  * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
8105  *
8106  * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
8107  * microcode for DMA addresses or math operations are byte swapped
8108  * to little-endian order.
8109  */
8110 static int
8111 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
8112 	      ADV_SCSI_REQ_Q **adv_scsiqpp)
8113 {
8114 	adv_req_t *reqp;
8115 	ADV_SCSI_REQ_Q *scsiqp;
8116 	int i;
8117 	int ret;
8118 	int use_sg;
8119 
8120 	/*
8121 	 * Allocate an adv_req_t structure from the board to execute
8122 	 * the command.
8123 	 */
8124 	if (boardp->adv_reqp == NULL) {
8125 		ASC_DBG(1, "no free adv_req_t\n");
8126 		ASC_STATS(scp->device->host, adv_build_noreq);
8127 		return ASC_BUSY;
8128 	} else {
8129 		reqp = boardp->adv_reqp;
8130 		boardp->adv_reqp = reqp->next_reqp;
8131 		reqp->next_reqp = NULL;
8132 	}
8133 
8134 	/*
8135 	 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
8136 	 */
8137 	scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
8138 
8139 	/*
8140 	 * Initialize the structure.
8141 	 */
8142 	scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
8143 
8144 	/*
8145 	 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
8146 	 */
8147 	scsiqp->srb_ptr = ADV_VADDR_TO_U32(reqp);
8148 
8149 	/*
8150 	 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
8151 	 */
8152 	reqp->cmndp = scp;
8153 
8154 	/*
8155 	 * Build the ADV_SCSI_REQ_Q request.
8156 	 */
8157 
8158 	/* Set CDB length and copy it to the request structure.  */
8159 	scsiqp->cdb_len = scp->cmd_len;
8160 	/* Copy first 12 CDB bytes to cdb[]. */
8161 	for (i = 0; i < scp->cmd_len && i < 12; i++) {
8162 		scsiqp->cdb[i] = scp->cmnd[i];
8163 	}
8164 	/* Copy last 4 CDB bytes, if present, to cdb16[]. */
8165 	for (; i < scp->cmd_len; i++) {
8166 		scsiqp->cdb16[i - 12] = scp->cmnd[i];
8167 	}
8168 
8169 	scsiqp->target_id = scp->device->id;
8170 	scsiqp->target_lun = scp->device->lun;
8171 
8172 	scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
8173 	scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE;
8174 
8175 	/* Build ADV_SCSI_REQ_Q */
8176 
8177 	use_sg = scsi_dma_map(scp);
8178 	if (use_sg == 0) {
8179 		/* Zero-length transfer */
8180 		reqp->sgblkp = NULL;
8181 		scsiqp->data_cnt = 0;
8182 		scsiqp->vdata_addr = NULL;
8183 
8184 		scsiqp->data_addr = 0;
8185 		scsiqp->sg_list_ptr = NULL;
8186 		scsiqp->sg_real_addr = 0;
8187 	} else {
8188 		if (use_sg > ADV_MAX_SG_LIST) {
8189 			scmd_printk(KERN_ERR, scp, "use_sg %d > "
8190 				   "ADV_MAX_SG_LIST %d\n", use_sg,
8191 				   scp->device->host->sg_tablesize);
8192 			scsi_dma_unmap(scp);
8193 			scp->result = HOST_BYTE(DID_ERROR);
8194 
8195 			/*
8196 			 * Free the 'adv_req_t' structure by adding it back
8197 			 * to the board free list.
8198 			 */
8199 			reqp->next_reqp = boardp->adv_reqp;
8200 			boardp->adv_reqp = reqp;
8201 
8202 			return ASC_ERROR;
8203 		}
8204 
8205 		scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8206 
8207 		ret = adv_get_sglist(boardp, reqp, scp, use_sg);
8208 		if (ret != ADV_SUCCESS) {
8209 			/*
8210 			 * Free the adv_req_t structure by adding it back to
8211 			 * the board free list.
8212 			 */
8213 			reqp->next_reqp = boardp->adv_reqp;
8214 			boardp->adv_reqp = reqp;
8215 
8216 			return ret;
8217 		}
8218 
8219 		ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
8220 	}
8221 
8222 	ASC_STATS(scp->device->host, xfer_cnt);
8223 
8224 	ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8225 	ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
8226 
8227 	*adv_scsiqpp = scsiqp;
8228 
8229 	return ASC_NOERROR;
8230 }
8231 
8232 static int AscSgListToQueue(int sg_list)
8233 {
8234 	int n_sg_list_qs;
8235 
8236 	n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8237 	if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8238 		n_sg_list_qs++;
8239 	return n_sg_list_qs + 1;
8240 }
8241 
8242 static uint
8243 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8244 {
8245 	uint cur_used_qs;
8246 	uint cur_free_qs;
8247 	ASC_SCSI_BIT_ID_TYPE target_id;
8248 	uchar tid_no;
8249 
8250 	target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8251 	tid_no = ASC_TIX_TO_TID(target_ix);
8252 	if ((asc_dvc->unit_not_ready & target_id) ||
8253 	    (asc_dvc->queue_full_or_busy & target_id)) {
8254 		return 0;
8255 	}
8256 	if (n_qs == 1) {
8257 		cur_used_qs = (uint) asc_dvc->cur_total_qng +
8258 		    (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8259 	} else {
8260 		cur_used_qs = (uint) asc_dvc->cur_total_qng +
8261 		    (uint) ASC_MIN_FREE_Q;
8262 	}
8263 	if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8264 		cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8265 		if (asc_dvc->cur_dvc_qng[tid_no] >=
8266 		    asc_dvc->max_dvc_qng[tid_no]) {
8267 			return 0;
8268 		}
8269 		return cur_free_qs;
8270 	}
8271 	if (n_qs > 1) {
8272 		if ((n_qs > asc_dvc->last_q_shortage)
8273 		    && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8274 			asc_dvc->last_q_shortage = n_qs;
8275 		}
8276 	}
8277 	return 0;
8278 }
8279 
8280 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8281 {
8282 	ushort q_addr;
8283 	uchar next_qp;
8284 	uchar q_status;
8285 
8286 	q_addr = ASC_QNO_TO_QADDR(free_q_head);
8287 	q_status = (uchar)AscReadLramByte(iop_base,
8288 					  (ushort)(q_addr +
8289 						   ASC_SCSIQ_B_STATUS));
8290 	next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8291 	if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8292 		return next_qp;
8293 	return ASC_QLINK_END;
8294 }
8295 
8296 static uchar
8297 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8298 {
8299 	uchar i;
8300 
8301 	for (i = 0; i < n_free_q; i++) {
8302 		free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8303 		if (free_q_head == ASC_QLINK_END)
8304 			break;
8305 	}
8306 	return free_q_head;
8307 }
8308 
8309 /*
8310  * void
8311  * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8312  *
8313  * Calling/Exit State:
8314  *    none
8315  *
8316  * Description:
8317  *     Output an ASC_SCSI_Q structure to the chip
8318  */
8319 static void
8320 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8321 {
8322 	int i;
8323 
8324 	ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8325 	AscSetChipLramAddr(iop_base, s_addr);
8326 	for (i = 0; i < 2 * words; i += 2) {
8327 		if (i == 4 || i == 20) {
8328 			continue;
8329 		}
8330 		outpw(iop_base + IOP_RAM_DATA,
8331 		      ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
8332 	}
8333 }
8334 
8335 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8336 {
8337 	ushort q_addr;
8338 	uchar tid_no;
8339 	uchar sdtr_data;
8340 	uchar syn_period_ix;
8341 	uchar syn_offset;
8342 	PortAddr iop_base;
8343 
8344 	iop_base = asc_dvc->iop_base;
8345 	if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8346 	    ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8347 		tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8348 		sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8349 		syn_period_ix =
8350 		    (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8351 		syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8352 		AscMsgOutSDTR(asc_dvc,
8353 			      asc_dvc->sdtr_period_tbl[syn_period_ix],
8354 			      syn_offset);
8355 		scsiq->q1.cntl |= QC_MSG_OUT;
8356 	}
8357 	q_addr = ASC_QNO_TO_QADDR(q_no);
8358 	if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
8359 		scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
8360 	}
8361 	scsiq->q1.status = QS_FREE;
8362 	AscMemWordCopyPtrToLram(iop_base,
8363 				q_addr + ASC_SCSIQ_CDB_BEG,
8364 				(uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8365 
8366 	DvcPutScsiQ(iop_base,
8367 		    q_addr + ASC_SCSIQ_CPY_BEG,
8368 		    (uchar *)&scsiq->q1.cntl,
8369 		    ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8370 	AscWriteLramWord(iop_base,
8371 			 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8372 			 (ushort)(((ushort)scsiq->q1.
8373 				   q_no << 8) | (ushort)QS_READY));
8374 	return 1;
8375 }
8376 
8377 static int
8378 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8379 {
8380 	int sta;
8381 	int i;
8382 	ASC_SG_HEAD *sg_head;
8383 	ASC_SG_LIST_Q scsi_sg_q;
8384 	ASC_DCNT saved_data_addr;
8385 	ASC_DCNT saved_data_cnt;
8386 	PortAddr iop_base;
8387 	ushort sg_list_dwords;
8388 	ushort sg_index;
8389 	ushort sg_entry_cnt;
8390 	ushort q_addr;
8391 	uchar next_qp;
8392 
8393 	iop_base = asc_dvc->iop_base;
8394 	sg_head = scsiq->sg_head;
8395 	saved_data_addr = scsiq->q1.data_addr;
8396 	saved_data_cnt = scsiq->q1.data_cnt;
8397 	scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
8398 	scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
8399 #if CC_VERY_LONG_SG_LIST
8400 	/*
8401 	 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8402 	 * then not all SG elements will fit in the allocated queues.
8403 	 * The rest of the SG elements will be copied when the RISC
8404 	 * completes the SG elements that fit and halts.
8405 	 */
8406 	if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8407 		/*
8408 		 * Set sg_entry_cnt to be the number of SG elements that
8409 		 * will fit in the allocated SG queues. It is minus 1, because
8410 		 * the first SG element is handled above. ASC_MAX_SG_LIST is
8411 		 * already inflated by 1 to account for this. For example it
8412 		 * may be 50 which is 1 + 7 queues * 7 SG elements.
8413 		 */
8414 		sg_entry_cnt = ASC_MAX_SG_LIST - 1;
8415 
8416 		/*
8417 		 * Keep track of remaining number of SG elements that will
8418 		 * need to be handled from a_isr.c.
8419 		 */
8420 		scsiq->remain_sg_entry_cnt =
8421 		    sg_head->entry_cnt - ASC_MAX_SG_LIST;
8422 	} else {
8423 #endif /* CC_VERY_LONG_SG_LIST */
8424 		/*
8425 		 * Set sg_entry_cnt to be the number of SG elements that
8426 		 * will fit in the allocated SG queues. It is minus 1, because
8427 		 * the first SG element is handled above.
8428 		 */
8429 		sg_entry_cnt = sg_head->entry_cnt - 1;
8430 #if CC_VERY_LONG_SG_LIST
8431 	}
8432 #endif /* CC_VERY_LONG_SG_LIST */
8433 	if (sg_entry_cnt != 0) {
8434 		scsiq->q1.cntl |= QC_SG_HEAD;
8435 		q_addr = ASC_QNO_TO_QADDR(q_no);
8436 		sg_index = 1;
8437 		scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8438 		scsi_sg_q.sg_head_qp = q_no;
8439 		scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8440 		for (i = 0; i < sg_head->queue_cnt; i++) {
8441 			scsi_sg_q.seq_no = i + 1;
8442 			if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8443 				sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8444 				sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8445 				if (i == 0) {
8446 					scsi_sg_q.sg_list_cnt =
8447 					    ASC_SG_LIST_PER_Q;
8448 					scsi_sg_q.sg_cur_list_cnt =
8449 					    ASC_SG_LIST_PER_Q;
8450 				} else {
8451 					scsi_sg_q.sg_list_cnt =
8452 					    ASC_SG_LIST_PER_Q - 1;
8453 					scsi_sg_q.sg_cur_list_cnt =
8454 					    ASC_SG_LIST_PER_Q - 1;
8455 				}
8456 			} else {
8457 #if CC_VERY_LONG_SG_LIST
8458 				/*
8459 				 * This is the last SG queue in the list of
8460 				 * allocated SG queues. If there are more
8461 				 * SG elements than will fit in the allocated
8462 				 * queues, then set the QCSG_SG_XFER_MORE flag.
8463 				 */
8464 				if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8465 					scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8466 				} else {
8467 #endif /* CC_VERY_LONG_SG_LIST */
8468 					scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8469 #if CC_VERY_LONG_SG_LIST
8470 				}
8471 #endif /* CC_VERY_LONG_SG_LIST */
8472 				sg_list_dwords = sg_entry_cnt << 1;
8473 				if (i == 0) {
8474 					scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8475 					scsi_sg_q.sg_cur_list_cnt =
8476 					    sg_entry_cnt;
8477 				} else {
8478 					scsi_sg_q.sg_list_cnt =
8479 					    sg_entry_cnt - 1;
8480 					scsi_sg_q.sg_cur_list_cnt =
8481 					    sg_entry_cnt - 1;
8482 				}
8483 				sg_entry_cnt = 0;
8484 			}
8485 			next_qp = AscReadLramByte(iop_base,
8486 						  (ushort)(q_addr +
8487 							   ASC_SCSIQ_B_FWD));
8488 			scsi_sg_q.q_no = next_qp;
8489 			q_addr = ASC_QNO_TO_QADDR(next_qp);
8490 			AscMemWordCopyPtrToLram(iop_base,
8491 						q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8492 						(uchar *)&scsi_sg_q,
8493 						sizeof(ASC_SG_LIST_Q) >> 1);
8494 			AscMemDWordCopyPtrToLram(iop_base,
8495 						 q_addr + ASC_SGQ_LIST_BEG,
8496 						 (uchar *)&sg_head->
8497 						 sg_list[sg_index],
8498 						 sg_list_dwords);
8499 			sg_index += ASC_SG_LIST_PER_Q;
8500 			scsiq->next_sg_index = sg_index;
8501 		}
8502 	} else {
8503 		scsiq->q1.cntl &= ~QC_SG_HEAD;
8504 	}
8505 	sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8506 	scsiq->q1.data_addr = saved_data_addr;
8507 	scsiq->q1.data_cnt = saved_data_cnt;
8508 	return (sta);
8509 }
8510 
8511 static int
8512 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8513 {
8514 	PortAddr iop_base;
8515 	uchar free_q_head;
8516 	uchar next_qp;
8517 	uchar tid_no;
8518 	uchar target_ix;
8519 	int sta;
8520 
8521 	iop_base = asc_dvc->iop_base;
8522 	target_ix = scsiq->q2.target_ix;
8523 	tid_no = ASC_TIX_TO_TID(target_ix);
8524 	sta = 0;
8525 	free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8526 	if (n_q_required > 1) {
8527 		next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8528 						    (uchar)n_q_required);
8529 		if (next_qp != ASC_QLINK_END) {
8530 			asc_dvc->last_q_shortage = 0;
8531 			scsiq->sg_head->queue_cnt = n_q_required - 1;
8532 			scsiq->q1.q_no = free_q_head;
8533 			sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8534 						     free_q_head);
8535 		}
8536 	} else if (n_q_required == 1) {
8537 		next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8538 		if (next_qp != ASC_QLINK_END) {
8539 			scsiq->q1.q_no = free_q_head;
8540 			sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
8541 		}
8542 	}
8543 	if (sta == 1) {
8544 		AscPutVarFreeQHead(iop_base, next_qp);
8545 		asc_dvc->cur_total_qng += n_q_required;
8546 		asc_dvc->cur_dvc_qng[tid_no]++;
8547 	}
8548 	return sta;
8549 }
8550 
8551 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST  16
8552 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8553 	INQUIRY,
8554 	REQUEST_SENSE,
8555 	READ_CAPACITY,
8556 	READ_TOC,
8557 	MODE_SELECT,
8558 	MODE_SENSE,
8559 	MODE_SELECT_10,
8560 	MODE_SENSE_10,
8561 	0xFF,
8562 	0xFF,
8563 	0xFF,
8564 	0xFF,
8565 	0xFF,
8566 	0xFF,
8567 	0xFF,
8568 	0xFF
8569 };
8570 
8571 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8572 {
8573 	PortAddr iop_base;
8574 	int sta;
8575 	int n_q_required;
8576 	int disable_syn_offset_one_fix;
8577 	int i;
8578 	ASC_PADDR addr;
8579 	ushort sg_entry_cnt = 0;
8580 	ushort sg_entry_cnt_minus_one = 0;
8581 	uchar target_ix;
8582 	uchar tid_no;
8583 	uchar sdtr_data;
8584 	uchar extra_bytes;
8585 	uchar scsi_cmd;
8586 	uchar disable_cmd;
8587 	ASC_SG_HEAD *sg_head;
8588 	ASC_DCNT data_cnt;
8589 
8590 	iop_base = asc_dvc->iop_base;
8591 	sg_head = scsiq->sg_head;
8592 	if (asc_dvc->err_code != 0)
8593 		return (ERR);
8594 	scsiq->q1.q_no = 0;
8595 	if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8596 		scsiq->q1.extra_bytes = 0;
8597 	}
8598 	sta = 0;
8599 	target_ix = scsiq->q2.target_ix;
8600 	tid_no = ASC_TIX_TO_TID(target_ix);
8601 	n_q_required = 1;
8602 	if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8603 		if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8604 			asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8605 			sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8606 			AscMsgOutSDTR(asc_dvc,
8607 				      asc_dvc->
8608 				      sdtr_period_tbl[(sdtr_data >> 4) &
8609 						      (uchar)(asc_dvc->
8610 							      max_sdtr_index -
8611 							      1)],
8612 				      (uchar)(sdtr_data & (uchar)
8613 					      ASC_SYN_MAX_OFFSET));
8614 			scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8615 		}
8616 	}
8617 	if (asc_dvc->in_critical_cnt != 0) {
8618 		AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8619 		return (ERR);
8620 	}
8621 	asc_dvc->in_critical_cnt++;
8622 	if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8623 		if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8624 			asc_dvc->in_critical_cnt--;
8625 			return (ERR);
8626 		}
8627 #if !CC_VERY_LONG_SG_LIST
8628 		if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8629 			asc_dvc->in_critical_cnt--;
8630 			return (ERR);
8631 		}
8632 #endif /* !CC_VERY_LONG_SG_LIST */
8633 		if (sg_entry_cnt == 1) {
8634 			scsiq->q1.data_addr =
8635 			    (ADV_PADDR)sg_head->sg_list[0].addr;
8636 			scsiq->q1.data_cnt =
8637 			    (ADV_DCNT)sg_head->sg_list[0].bytes;
8638 			scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8639 		}
8640 		sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8641 	}
8642 	scsi_cmd = scsiq->cdbptr[0];
8643 	disable_syn_offset_one_fix = FALSE;
8644 	if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8645 	    !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8646 		if (scsiq->q1.cntl & QC_SG_HEAD) {
8647 			data_cnt = 0;
8648 			for (i = 0; i < sg_entry_cnt; i++) {
8649 				data_cnt +=
8650 				    (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
8651 							  bytes);
8652 			}
8653 		} else {
8654 			data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8655 		}
8656 		if (data_cnt != 0UL) {
8657 			if (data_cnt < 512UL) {
8658 				disable_syn_offset_one_fix = TRUE;
8659 			} else {
8660 				for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8661 				     i++) {
8662 					disable_cmd =
8663 					    _syn_offset_one_disable_cmd[i];
8664 					if (disable_cmd == 0xFF) {
8665 						break;
8666 					}
8667 					if (scsi_cmd == disable_cmd) {
8668 						disable_syn_offset_one_fix =
8669 						    TRUE;
8670 						break;
8671 					}
8672 				}
8673 			}
8674 		}
8675 	}
8676 	if (disable_syn_offset_one_fix) {
8677 		scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
8678 		scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8679 				       ASC_TAG_FLAG_DISABLE_DISCONNECT);
8680 	} else {
8681 		scsiq->q2.tag_code &= 0x27;
8682 	}
8683 	if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8684 		if (asc_dvc->bug_fix_cntl) {
8685 			if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8686 				if ((scsi_cmd == READ_6) ||
8687 				    (scsi_cmd == READ_10)) {
8688 					addr =
8689 					    (ADV_PADDR)le32_to_cpu(sg_head->
8690 								   sg_list
8691 								   [sg_entry_cnt_minus_one].
8692 								   addr) +
8693 					    (ADV_DCNT)le32_to_cpu(sg_head->
8694 								  sg_list
8695 								  [sg_entry_cnt_minus_one].
8696 								  bytes);
8697 					extra_bytes =
8698 					    (uchar)((ushort)addr & 0x0003);
8699 					if ((extra_bytes != 0)
8700 					    &&
8701 					    ((scsiq->q2.
8702 					      tag_code &
8703 					      ASC_TAG_FLAG_EXTRA_BYTES)
8704 					     == 0)) {
8705 						scsiq->q2.tag_code |=
8706 						    ASC_TAG_FLAG_EXTRA_BYTES;
8707 						scsiq->q1.extra_bytes =
8708 						    extra_bytes;
8709 						data_cnt =
8710 						    le32_to_cpu(sg_head->
8711 								sg_list
8712 								[sg_entry_cnt_minus_one].
8713 								bytes);
8714 						data_cnt -=
8715 						    (ASC_DCNT) extra_bytes;
8716 						sg_head->
8717 						    sg_list
8718 						    [sg_entry_cnt_minus_one].
8719 						    bytes =
8720 						    cpu_to_le32(data_cnt);
8721 					}
8722 				}
8723 			}
8724 		}
8725 		sg_head->entry_to_copy = sg_head->entry_cnt;
8726 #if CC_VERY_LONG_SG_LIST
8727 		/*
8728 		 * Set the sg_entry_cnt to the maximum possible. The rest of
8729 		 * the SG elements will be copied when the RISC completes the
8730 		 * SG elements that fit and halts.
8731 		 */
8732 		if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8733 			sg_entry_cnt = ASC_MAX_SG_LIST;
8734 		}
8735 #endif /* CC_VERY_LONG_SG_LIST */
8736 		n_q_required = AscSgListToQueue(sg_entry_cnt);
8737 		if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8738 		     (uint) n_q_required)
8739 		    || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8740 			if ((sta =
8741 			     AscSendScsiQueue(asc_dvc, scsiq,
8742 					      n_q_required)) == 1) {
8743 				asc_dvc->in_critical_cnt--;
8744 				return (sta);
8745 			}
8746 		}
8747 	} else {
8748 		if (asc_dvc->bug_fix_cntl) {
8749 			if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8750 				if ((scsi_cmd == READ_6) ||
8751 				    (scsi_cmd == READ_10)) {
8752 					addr =
8753 					    le32_to_cpu(scsiq->q1.data_addr) +
8754 					    le32_to_cpu(scsiq->q1.data_cnt);
8755 					extra_bytes =
8756 					    (uchar)((ushort)addr & 0x0003);
8757 					if ((extra_bytes != 0)
8758 					    &&
8759 					    ((scsiq->q2.
8760 					      tag_code &
8761 					      ASC_TAG_FLAG_EXTRA_BYTES)
8762 					     == 0)) {
8763 						data_cnt =
8764 						    le32_to_cpu(scsiq->q1.
8765 								data_cnt);
8766 						if (((ushort)data_cnt & 0x01FF)
8767 						    == 0) {
8768 							scsiq->q2.tag_code |=
8769 							    ASC_TAG_FLAG_EXTRA_BYTES;
8770 							data_cnt -= (ASC_DCNT)
8771 							    extra_bytes;
8772 							scsiq->q1.data_cnt =
8773 							    cpu_to_le32
8774 							    (data_cnt);
8775 							scsiq->q1.extra_bytes =
8776 							    extra_bytes;
8777 						}
8778 					}
8779 				}
8780 			}
8781 		}
8782 		n_q_required = 1;
8783 		if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8784 		    ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8785 			if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8786 						    n_q_required)) == 1) {
8787 				asc_dvc->in_critical_cnt--;
8788 				return (sta);
8789 			}
8790 		}
8791 	}
8792 	asc_dvc->in_critical_cnt--;
8793 	return (sta);
8794 }
8795 
8796 /*
8797  * AdvExeScsiQueue() - Send a request to the RISC microcode program.
8798  *
8799  *   Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8800  *   add the carrier to the ICQ (Initiator Command Queue), and tickle the
8801  *   RISC to notify it a new command is ready to be executed.
8802  *
8803  * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8804  * set to SCSI_MAX_RETRY.
8805  *
8806  * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8807  * for DMA addresses or math operations are byte swapped to little-endian
8808  * order.
8809  *
8810  * Return:
8811  *      ADV_SUCCESS(1) - The request was successfully queued.
8812  *      ADV_BUSY(0) -    Resource unavailable; Retry again after pending
8813  *                       request completes.
8814  *      ADV_ERROR(-1) -  Invalid ADV_SCSI_REQ_Q request structure
8815  *                       host IC error.
8816  */
8817 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
8818 {
8819 	AdvPortAddr iop_base;
8820 	ADV_PADDR req_paddr;
8821 	ADV_CARR_T *new_carrp;
8822 
8823 	/*
8824 	 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
8825 	 */
8826 	if (scsiq->target_id > ADV_MAX_TID) {
8827 		scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8828 		scsiq->done_status = QD_WITH_ERROR;
8829 		return ADV_ERROR;
8830 	}
8831 
8832 	iop_base = asc_dvc->iop_base;
8833 
8834 	/*
8835 	 * Allocate a carrier ensuring at least one carrier always
8836 	 * remains on the freelist and initialize fields.
8837 	 */
8838 	if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
8839 		return ADV_BUSY;
8840 	}
8841 	asc_dvc->carr_freelist = (ADV_CARR_T *)
8842 	    ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
8843 	asc_dvc->carr_pending_cnt++;
8844 
8845 	/*
8846 	 * Set the carrier to be a stopper by setting 'next_vpa'
8847 	 * to the stopper value. The current stopper will be changed
8848 	 * below to point to the new stopper.
8849 	 */
8850 	new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
8851 
8852 	/*
8853 	 * Clear the ADV_SCSI_REQ_Q done flag.
8854 	 */
8855 	scsiq->a_flag &= ~ADV_SCSIQ_DONE;
8856 
8857 	req_paddr = virt_to_bus(scsiq);
8858 	BUG_ON(req_paddr & 31);
8859 	/* Wait for assertion before making little-endian */
8860 	req_paddr = cpu_to_le32(req_paddr);
8861 
8862 	/* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8863 	scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
8864 	scsiq->scsiq_rptr = req_paddr;
8865 
8866 	scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
8867 	/*
8868 	 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
8869 	 * order during initialization.
8870 	 */
8871 	scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
8872 
8873 	/*
8874 	 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8875 	 * the microcode. The newly allocated stopper will become the new
8876 	 * stopper.
8877 	 */
8878 	asc_dvc->icq_sp->areq_vpa = req_paddr;
8879 
8880 	/*
8881 	 * Set the 'next_vpa' pointer for the old stopper to be the
8882 	 * physical address of the new stopper. The RISC can only
8883 	 * follow physical addresses.
8884 	 */
8885 	asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
8886 
8887 	/*
8888 	 * Set the host adapter stopper pointer to point to the new carrier.
8889 	 */
8890 	asc_dvc->icq_sp = new_carrp;
8891 
8892 	if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8893 	    asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8894 		/*
8895 		 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8896 		 */
8897 		AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8898 		if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8899 			/*
8900 			 * Clear the tickle value. In the ASC-3550 the RISC flag
8901 			 * command 'clr_tickle_a' does not work unless the host
8902 			 * value is cleared.
8903 			 */
8904 			AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8905 					     ADV_TICKLE_NOP);
8906 		}
8907 	} else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8908 		/*
8909 		 * Notify the RISC a carrier is ready by writing the physical
8910 		 * address of the new carrier stopper to the COMMA register.
8911 		 */
8912 		AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8913 				      le32_to_cpu(new_carrp->carr_pa));
8914 	}
8915 
8916 	return ADV_SUCCESS;
8917 }
8918 
8919 /*
8920  * Execute a single 'Scsi_Cmnd'.
8921  */
8922 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8923 {
8924 	int ret, err_code;
8925 	struct asc_board *boardp = shost_priv(scp->device->host);
8926 
8927 	ASC_DBG(1, "scp 0x%p\n", scp);
8928 
8929 	if (ASC_NARROW_BOARD(boardp)) {
8930 		ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
8931 		struct asc_scsi_q asc_scsi_q;
8932 
8933 		/* asc_build_req() can not return ASC_BUSY. */
8934 		ret = asc_build_req(boardp, scp, &asc_scsi_q);
8935 		if (ret == ASC_ERROR) {
8936 			ASC_STATS(scp->device->host, build_error);
8937 			return ASC_ERROR;
8938 		}
8939 
8940 		ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
8941 		kfree(asc_scsi_q.sg_head);
8942 		err_code = asc_dvc->err_code;
8943 	} else {
8944 		ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8945 		ADV_SCSI_REQ_Q *adv_scsiqp;
8946 
8947 		switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
8948 		case ASC_NOERROR:
8949 			ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
8950 			break;
8951 		case ASC_BUSY:
8952 			ASC_DBG(1, "adv_build_req ASC_BUSY\n");
8953 			/*
8954 			 * The asc_stats fields 'adv_build_noreq' and
8955 			 * 'adv_build_nosg' count wide board busy conditions.
8956 			 * They are updated in adv_build_req and
8957 			 * adv_get_sglist, respectively.
8958 			 */
8959 			return ASC_BUSY;
8960 		case ASC_ERROR:
8961 		default:
8962 			ASC_DBG(1, "adv_build_req ASC_ERROR\n");
8963 			ASC_STATS(scp->device->host, build_error);
8964 			return ASC_ERROR;
8965 		}
8966 
8967 		ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
8968 		err_code = adv_dvc->err_code;
8969 	}
8970 
8971 	switch (ret) {
8972 	case ASC_NOERROR:
8973 		ASC_STATS(scp->device->host, exe_noerror);
8974 		/*
8975 		 * Increment monotonically increasing per device
8976 		 * successful request counter. Wrapping doesn't matter.
8977 		 */
8978 		boardp->reqcnt[scp->device->id]++;
8979 		ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
8980 		break;
8981 	case ASC_BUSY:
8982 		ASC_STATS(scp->device->host, exe_busy);
8983 		break;
8984 	case ASC_ERROR:
8985 		scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8986 			"err_code 0x%x\n", err_code);
8987 		ASC_STATS(scp->device->host, exe_error);
8988 		scp->result = HOST_BYTE(DID_ERROR);
8989 		break;
8990 	default:
8991 		scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8992 			"err_code 0x%x\n", err_code);
8993 		ASC_STATS(scp->device->host, exe_unknown);
8994 		scp->result = HOST_BYTE(DID_ERROR);
8995 		break;
8996 	}
8997 
8998 	ASC_DBG(1, "end\n");
8999 	return ret;
9000 }
9001 
9002 /*
9003  * advansys_queuecommand() - interrupt-driven I/O entrypoint.
9004  *
9005  * This function always returns 0. Command return status is saved
9006  * in the 'scp' result field.
9007  */
9008 static int
9009 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
9010 {
9011 	struct Scsi_Host *shost = scp->device->host;
9012 	int asc_res, result = 0;
9013 
9014 	ASC_STATS(shost, queuecommand);
9015 	scp->scsi_done = done;
9016 
9017 	asc_res = asc_execute_scsi_cmnd(scp);
9018 
9019 	switch (asc_res) {
9020 	case ASC_NOERROR:
9021 		break;
9022 	case ASC_BUSY:
9023 		result = SCSI_MLQUEUE_HOST_BUSY;
9024 		break;
9025 	case ASC_ERROR:
9026 	default:
9027 		asc_scsi_done(scp);
9028 		break;
9029 	}
9030 
9031 	return result;
9032 }
9033 
9034 static DEF_SCSI_QCMD(advansys_queuecommand)
9035 
9036 static ushort AscGetEisaChipCfg(PortAddr iop_base)
9037 {
9038 	PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9039 	    (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9040 	return inpw(eisa_cfg_iop);
9041 }
9042 
9043 /*
9044  * Return the BIOS address of the adapter at the specified
9045  * I/O port and with the specified bus type.
9046  */
9047 static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
9048 					    unsigned short bus_type)
9049 {
9050 	unsigned short cfg_lsw;
9051 	unsigned short bios_addr;
9052 
9053 	/*
9054 	 * The PCI BIOS is re-located by the motherboard BIOS. Because
9055 	 * of this the driver can not determine where a PCI BIOS is
9056 	 * loaded and executes.
9057 	 */
9058 	if (bus_type & ASC_IS_PCI)
9059 		return 0;
9060 
9061 	if ((bus_type & ASC_IS_EISA) != 0) {
9062 		cfg_lsw = AscGetEisaChipCfg(iop_base);
9063 		cfg_lsw &= 0x000F;
9064 		bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
9065 		return bios_addr;
9066 	}
9067 
9068 	cfg_lsw = AscGetChipCfgLsw(iop_base);
9069 
9070 	/*
9071 	 *  ISA PnP uses the top bit as the 32K BIOS flag
9072 	 */
9073 	if (bus_type == ASC_IS_ISAPNP)
9074 		cfg_lsw &= 0x7FFF;
9075 	bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
9076 	return bios_addr;
9077 }
9078 
9079 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
9080 {
9081 	ushort cfg_lsw;
9082 
9083 	if (AscGetChipScsiID(iop_base) == new_host_id) {
9084 		return (new_host_id);
9085 	}
9086 	cfg_lsw = AscGetChipCfgLsw(iop_base);
9087 	cfg_lsw &= 0xF8FF;
9088 	cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
9089 	AscSetChipCfgLsw(iop_base, cfg_lsw);
9090 	return (AscGetChipScsiID(iop_base));
9091 }
9092 
9093 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
9094 {
9095 	unsigned char sc;
9096 
9097 	AscSetBank(iop_base, 1);
9098 	sc = inp(iop_base + IOP_REG_SC);
9099 	AscSetBank(iop_base, 0);
9100 	return sc;
9101 }
9102 
9103 static unsigned char AscGetChipVersion(PortAddr iop_base,
9104 				       unsigned short bus_type)
9105 {
9106 	if (bus_type & ASC_IS_EISA) {
9107 		PortAddr eisa_iop;
9108 		unsigned char revision;
9109 		eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9110 		    (PortAddr) ASC_EISA_REV_IOP_MASK;
9111 		revision = inp(eisa_iop);
9112 		return ASC_CHIP_MIN_VER_EISA - 1 + revision;
9113 	}
9114 	return AscGetChipVerNo(iop_base);
9115 }
9116 
9117 #ifdef CONFIG_ISA
9118 static void AscEnableIsaDma(uchar dma_channel)
9119 {
9120 	if (dma_channel < 4) {
9121 		outp(0x000B, (ushort)(0xC0 | dma_channel));
9122 		outp(0x000A, dma_channel);
9123 	} else if (dma_channel < 8) {
9124 		outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
9125 		outp(0x00D4, (ushort)(dma_channel - 4));
9126 	}
9127 }
9128 #endif /* CONFIG_ISA */
9129 
9130 static int AscStopQueueExe(PortAddr iop_base)
9131 {
9132 	int count = 0;
9133 
9134 	if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
9135 		AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9136 				 ASC_STOP_REQ_RISC_STOP);
9137 		do {
9138 			if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
9139 			    ASC_STOP_ACK_RISC_STOP) {
9140 				return (1);
9141 			}
9142 			mdelay(100);
9143 		} while (count++ < 20);
9144 	}
9145 	return (0);
9146 }
9147 
9148 static ASC_DCNT AscGetMaxDmaCount(ushort bus_type)
9149 {
9150 	if (bus_type & ASC_IS_ISA)
9151 		return ASC_MAX_ISA_DMA_COUNT;
9152 	else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
9153 		return ASC_MAX_VL_DMA_COUNT;
9154 	return ASC_MAX_PCI_DMA_COUNT;
9155 }
9156 
9157 #ifdef CONFIG_ISA
9158 static ushort AscGetIsaDmaChannel(PortAddr iop_base)
9159 {
9160 	ushort channel;
9161 
9162 	channel = AscGetChipCfgLsw(iop_base) & 0x0003;
9163 	if (channel == 0x03)
9164 		return (0);
9165 	else if (channel == 0x00)
9166 		return (7);
9167 	return (channel + 4);
9168 }
9169 
9170 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
9171 {
9172 	ushort cfg_lsw;
9173 	uchar value;
9174 
9175 	if ((dma_channel >= 5) && (dma_channel <= 7)) {
9176 		if (dma_channel == 7)
9177 			value = 0x00;
9178 		else
9179 			value = dma_channel - 4;
9180 		cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9181 		cfg_lsw |= value;
9182 		AscSetChipCfgLsw(iop_base, cfg_lsw);
9183 		return (AscGetIsaDmaChannel(iop_base));
9184 	}
9185 	return 0;
9186 }
9187 
9188 static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
9189 {
9190 	uchar speed_value;
9191 
9192 	AscSetBank(iop_base, 1);
9193 	speed_value = AscReadChipDmaSpeed(iop_base);
9194 	speed_value &= 0x07;
9195 	AscSetBank(iop_base, 0);
9196 	return speed_value;
9197 }
9198 
9199 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
9200 {
9201 	speed_value &= 0x07;
9202 	AscSetBank(iop_base, 1);
9203 	AscWriteChipDmaSpeed(iop_base, speed_value);
9204 	AscSetBank(iop_base, 0);
9205 	return AscGetIsaDmaSpeed(iop_base);
9206 }
9207 #endif /* CONFIG_ISA */
9208 
9209 static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
9210 {
9211 	int i;
9212 	PortAddr iop_base;
9213 	ushort warn_code;
9214 	uchar chip_version;
9215 
9216 	iop_base = asc_dvc->iop_base;
9217 	warn_code = 0;
9218 	asc_dvc->err_code = 0;
9219 	if ((asc_dvc->bus_type &
9220 	     (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9221 		asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
9222 	}
9223 	AscSetChipControl(iop_base, CC_HALT);
9224 	AscSetChipStatus(iop_base, 0);
9225 	asc_dvc->bug_fix_cntl = 0;
9226 	asc_dvc->pci_fix_asyn_xfer = 0;
9227 	asc_dvc->pci_fix_asyn_xfer_always = 0;
9228 	/* asc_dvc->init_state initialized in AscInitGetConfig(). */
9229 	asc_dvc->sdtr_done = 0;
9230 	asc_dvc->cur_total_qng = 0;
9231 	asc_dvc->is_in_int = 0;
9232 	asc_dvc->in_critical_cnt = 0;
9233 	asc_dvc->last_q_shortage = 0;
9234 	asc_dvc->use_tagged_qng = 0;
9235 	asc_dvc->no_scam = 0;
9236 	asc_dvc->unit_not_ready = 0;
9237 	asc_dvc->queue_full_or_busy = 0;
9238 	asc_dvc->redo_scam = 0;
9239 	asc_dvc->res2 = 0;
9240 	asc_dvc->min_sdtr_index = 0;
9241 	asc_dvc->cfg->can_tagged_qng = 0;
9242 	asc_dvc->cfg->cmd_qng_enabled = 0;
9243 	asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9244 	asc_dvc->init_sdtr = 0;
9245 	asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9246 	asc_dvc->scsi_reset_wait = 3;
9247 	asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9248 	asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9249 	asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9250 	asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9251 	asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
9252 	chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9253 	asc_dvc->cfg->chip_version = chip_version;
9254 	asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
9255 	asc_dvc->max_sdtr_index = 7;
9256 	if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9257 	    (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9258 		asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
9259 		asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
9260 		asc_dvc->max_sdtr_index = 15;
9261 		if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9262 			AscSetExtraControl(iop_base,
9263 					   (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9264 		} else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9265 			AscSetExtraControl(iop_base,
9266 					   (SEC_ACTIVE_NEGATE |
9267 					    SEC_ENABLE_FILTER));
9268 		}
9269 	}
9270 	if (asc_dvc->bus_type == ASC_IS_PCI) {
9271 		AscSetExtraControl(iop_base,
9272 				   (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9273 	}
9274 
9275 	asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9276 #ifdef CONFIG_ISA
9277 	if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9278 		if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9279 			AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9280 			asc_dvc->bus_type = ASC_IS_ISAPNP;
9281 		}
9282 		asc_dvc->cfg->isa_dma_channel =
9283 		    (uchar)AscGetIsaDmaChannel(iop_base);
9284 	}
9285 #endif /* CONFIG_ISA */
9286 	for (i = 0; i <= ASC_MAX_TID; i++) {
9287 		asc_dvc->cur_dvc_qng[i] = 0;
9288 		asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9289 		asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9290 		asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9291 		asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
9292 	}
9293 	return warn_code;
9294 }
9295 
9296 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
9297 {
9298 	int retry;
9299 
9300 	for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9301 		unsigned char read_back;
9302 		AscSetChipEEPCmd(iop_base, cmd_reg);
9303 		mdelay(1);
9304 		read_back = AscGetChipEEPCmd(iop_base);
9305 		if (read_back == cmd_reg)
9306 			return 1;
9307 	}
9308 	return 0;
9309 }
9310 
9311 static void AscWaitEEPRead(void)
9312 {
9313 	mdelay(1);
9314 }
9315 
9316 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
9317 {
9318 	ushort read_wval;
9319 	uchar cmd_reg;
9320 
9321 	AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9322 	AscWaitEEPRead();
9323 	cmd_reg = addr | ASC_EEP_CMD_READ;
9324 	AscWriteEEPCmdReg(iop_base, cmd_reg);
9325 	AscWaitEEPRead();
9326 	read_wval = AscGetChipEEPData(iop_base);
9327 	AscWaitEEPRead();
9328 	return read_wval;
9329 }
9330 
9331 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9332 			      ushort bus_type)
9333 {
9334 	ushort wval;
9335 	ushort sum;
9336 	ushort *wbuf;
9337 	int cfg_beg;
9338 	int cfg_end;
9339 	int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9340 	int s_addr;
9341 
9342 	wbuf = (ushort *)cfg_buf;
9343 	sum = 0;
9344 	/* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9345 	for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9346 		*wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9347 		sum += *wbuf;
9348 	}
9349 	if (bus_type & ASC_IS_VL) {
9350 		cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9351 		cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9352 	} else {
9353 		cfg_beg = ASC_EEP_DVC_CFG_BEG;
9354 		cfg_end = ASC_EEP_MAX_DVC_ADDR;
9355 	}
9356 	for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9357 		wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9358 		if (s_addr <= uchar_end_in_config) {
9359 			/*
9360 			 * Swap all char fields - must unswap bytes already swapped
9361 			 * by AscReadEEPWord().
9362 			 */
9363 			*wbuf = le16_to_cpu(wval);
9364 		} else {
9365 			/* Don't swap word field at the end - cntl field. */
9366 			*wbuf = wval;
9367 		}
9368 		sum += wval;	/* Checksum treats all EEPROM data as words. */
9369 	}
9370 	/*
9371 	 * Read the checksum word which will be compared against 'sum'
9372 	 * by the caller. Word field already swapped.
9373 	 */
9374 	*wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9375 	return sum;
9376 }
9377 
9378 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
9379 {
9380 	PortAddr iop_base;
9381 	ushort q_addr;
9382 	ushort saved_word;
9383 	int sta;
9384 
9385 	iop_base = asc_dvc->iop_base;
9386 	sta = 0;
9387 	q_addr = ASC_QNO_TO_QADDR(241);
9388 	saved_word = AscReadLramWord(iop_base, q_addr);
9389 	AscSetChipLramAddr(iop_base, q_addr);
9390 	AscSetChipLramData(iop_base, 0x55AA);
9391 	mdelay(10);
9392 	AscSetChipLramAddr(iop_base, q_addr);
9393 	if (AscGetChipLramData(iop_base) == 0x55AA) {
9394 		sta = 1;
9395 		AscWriteLramWord(iop_base, q_addr, saved_word);
9396 	}
9397 	return (sta);
9398 }
9399 
9400 static void AscWaitEEPWrite(void)
9401 {
9402 	mdelay(20);
9403 }
9404 
9405 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
9406 {
9407 	ushort read_back;
9408 	int retry;
9409 
9410 	retry = 0;
9411 	while (TRUE) {
9412 		AscSetChipEEPData(iop_base, data_reg);
9413 		mdelay(1);
9414 		read_back = AscGetChipEEPData(iop_base);
9415 		if (read_back == data_reg) {
9416 			return (1);
9417 		}
9418 		if (retry++ > ASC_EEP_MAX_RETRY) {
9419 			return (0);
9420 		}
9421 	}
9422 }
9423 
9424 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
9425 {
9426 	ushort read_wval;
9427 
9428 	read_wval = AscReadEEPWord(iop_base, addr);
9429 	if (read_wval != word_val) {
9430 		AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9431 		AscWaitEEPRead();
9432 		AscWriteEEPDataReg(iop_base, word_val);
9433 		AscWaitEEPRead();
9434 		AscWriteEEPCmdReg(iop_base,
9435 				  (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9436 		AscWaitEEPWrite();
9437 		AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9438 		AscWaitEEPRead();
9439 		return (AscReadEEPWord(iop_base, addr));
9440 	}
9441 	return (read_wval);
9442 }
9443 
9444 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9445 			       ushort bus_type)
9446 {
9447 	int n_error;
9448 	ushort *wbuf;
9449 	ushort word;
9450 	ushort sum;
9451 	int s_addr;
9452 	int cfg_beg;
9453 	int cfg_end;
9454 	int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9455 
9456 	wbuf = (ushort *)cfg_buf;
9457 	n_error = 0;
9458 	sum = 0;
9459 	/* Write two config words; AscWriteEEPWord() will swap bytes. */
9460 	for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9461 		sum += *wbuf;
9462 		if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9463 			n_error++;
9464 		}
9465 	}
9466 	if (bus_type & ASC_IS_VL) {
9467 		cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9468 		cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9469 	} else {
9470 		cfg_beg = ASC_EEP_DVC_CFG_BEG;
9471 		cfg_end = ASC_EEP_MAX_DVC_ADDR;
9472 	}
9473 	for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9474 		if (s_addr <= uchar_end_in_config) {
9475 			/*
9476 			 * This is a char field. Swap char fields before they are
9477 			 * swapped again by AscWriteEEPWord().
9478 			 */
9479 			word = cpu_to_le16(*wbuf);
9480 			if (word !=
9481 			    AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9482 				n_error++;
9483 			}
9484 		} else {
9485 			/* Don't swap word field at the end - cntl field. */
9486 			if (*wbuf !=
9487 			    AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9488 				n_error++;
9489 			}
9490 		}
9491 		sum += *wbuf;	/* Checksum calculated from word values. */
9492 	}
9493 	/* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9494 	*wbuf = sum;
9495 	if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9496 		n_error++;
9497 	}
9498 
9499 	/* Read EEPROM back again. */
9500 	wbuf = (ushort *)cfg_buf;
9501 	/*
9502 	 * Read two config words; Byte-swapping done by AscReadEEPWord().
9503 	 */
9504 	for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9505 		if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9506 			n_error++;
9507 		}
9508 	}
9509 	if (bus_type & ASC_IS_VL) {
9510 		cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9511 		cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9512 	} else {
9513 		cfg_beg = ASC_EEP_DVC_CFG_BEG;
9514 		cfg_end = ASC_EEP_MAX_DVC_ADDR;
9515 	}
9516 	for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9517 		if (s_addr <= uchar_end_in_config) {
9518 			/*
9519 			 * Swap all char fields. Must unswap bytes already swapped
9520 			 * by AscReadEEPWord().
9521 			 */
9522 			word =
9523 			    le16_to_cpu(AscReadEEPWord
9524 					(iop_base, (uchar)s_addr));
9525 		} else {
9526 			/* Don't swap word field at the end - cntl field. */
9527 			word = AscReadEEPWord(iop_base, (uchar)s_addr);
9528 		}
9529 		if (*wbuf != word) {
9530 			n_error++;
9531 		}
9532 	}
9533 	/* Read checksum; Byte swapping not needed. */
9534 	if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9535 		n_error++;
9536 	}
9537 	return n_error;
9538 }
9539 
9540 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9541 			   ushort bus_type)
9542 {
9543 	int retry;
9544 	int n_error;
9545 
9546 	retry = 0;
9547 	while (TRUE) {
9548 		if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9549 						   bus_type)) == 0) {
9550 			break;
9551 		}
9552 		if (++retry > ASC_EEP_MAX_RETRY) {
9553 			break;
9554 		}
9555 	}
9556 	return n_error;
9557 }
9558 
9559 static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
9560 {
9561 	ASCEEP_CONFIG eep_config_buf;
9562 	ASCEEP_CONFIG *eep_config;
9563 	PortAddr iop_base;
9564 	ushort chksum;
9565 	ushort warn_code;
9566 	ushort cfg_msw, cfg_lsw;
9567 	int i;
9568 	int write_eep = 0;
9569 
9570 	iop_base = asc_dvc->iop_base;
9571 	warn_code = 0;
9572 	AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9573 	AscStopQueueExe(iop_base);
9574 	if ((AscStopChip(iop_base) == FALSE) ||
9575 	    (AscGetChipScsiCtrl(iop_base) != 0)) {
9576 		asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9577 		AscResetChipAndScsiBus(asc_dvc);
9578 		mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9579 	}
9580 	if (AscIsChipHalted(iop_base) == FALSE) {
9581 		asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9582 		return (warn_code);
9583 	}
9584 	AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9585 	if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9586 		asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9587 		return (warn_code);
9588 	}
9589 	eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9590 	cfg_msw = AscGetChipCfgMsw(iop_base);
9591 	cfg_lsw = AscGetChipCfgLsw(iop_base);
9592 	if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9593 		cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9594 		warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9595 		AscSetChipCfgMsw(iop_base, cfg_msw);
9596 	}
9597 	chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
9598 	ASC_DBG(1, "chksum 0x%x\n", chksum);
9599 	if (chksum == 0) {
9600 		chksum = 0xaa55;
9601 	}
9602 	if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9603 		warn_code |= ASC_WARN_AUTO_CONFIG;
9604 		if (asc_dvc->cfg->chip_version == 3) {
9605 			if (eep_config->cfg_lsw != cfg_lsw) {
9606 				warn_code |= ASC_WARN_EEPROM_RECOVER;
9607 				eep_config->cfg_lsw =
9608 				    AscGetChipCfgLsw(iop_base);
9609 			}
9610 			if (eep_config->cfg_msw != cfg_msw) {
9611 				warn_code |= ASC_WARN_EEPROM_RECOVER;
9612 				eep_config->cfg_msw =
9613 				    AscGetChipCfgMsw(iop_base);
9614 			}
9615 		}
9616 	}
9617 	eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9618 	eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
9619 	ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
9620 	if (chksum != eep_config->chksum) {
9621 		if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9622 		    ASC_CHIP_VER_PCI_ULTRA_3050) {
9623 			ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
9624 			eep_config->init_sdtr = 0xFF;
9625 			eep_config->disc_enable = 0xFF;
9626 			eep_config->start_motor = 0xFF;
9627 			eep_config->use_cmd_qng = 0;
9628 			eep_config->max_total_qng = 0xF0;
9629 			eep_config->max_tag_qng = 0x20;
9630 			eep_config->cntl = 0xBFFF;
9631 			ASC_EEP_SET_CHIP_ID(eep_config, 7);
9632 			eep_config->no_scam = 0;
9633 			eep_config->adapter_info[0] = 0;
9634 			eep_config->adapter_info[1] = 0;
9635 			eep_config->adapter_info[2] = 0;
9636 			eep_config->adapter_info[3] = 0;
9637 			eep_config->adapter_info[4] = 0;
9638 			/* Indicate EEPROM-less board. */
9639 			eep_config->adapter_info[5] = 0xBB;
9640 		} else {
9641 			ASC_PRINT
9642 			    ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9643 			write_eep = 1;
9644 			warn_code |= ASC_WARN_EEPROM_CHKSUM;
9645 		}
9646 	}
9647 	asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9648 	asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9649 	asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9650 	asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9651 	asc_dvc->start_motor = eep_config->start_motor;
9652 	asc_dvc->dvc_cntl = eep_config->cntl;
9653 	asc_dvc->no_scam = eep_config->no_scam;
9654 	asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9655 	asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9656 	asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9657 	asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9658 	asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9659 	asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9660 	if (!AscTestExternalLram(asc_dvc)) {
9661 		if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9662 		     ASC_IS_PCI_ULTRA)) {
9663 			eep_config->max_total_qng =
9664 			    ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9665 			eep_config->max_tag_qng =
9666 			    ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9667 		} else {
9668 			eep_config->cfg_msw |= 0x0800;
9669 			cfg_msw |= 0x0800;
9670 			AscSetChipCfgMsw(iop_base, cfg_msw);
9671 			eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9672 			eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
9673 		}
9674 	} else {
9675 	}
9676 	if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9677 		eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9678 	}
9679 	if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9680 		eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9681 	}
9682 	if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9683 		eep_config->max_tag_qng = eep_config->max_total_qng;
9684 	}
9685 	if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9686 		eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9687 	}
9688 	asc_dvc->max_total_qng = eep_config->max_total_qng;
9689 	if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9690 	    eep_config->use_cmd_qng) {
9691 		eep_config->disc_enable = eep_config->use_cmd_qng;
9692 		warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9693 	}
9694 	ASC_EEP_SET_CHIP_ID(eep_config,
9695 			    ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9696 	asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9697 	if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9698 	    !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
9699 		asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
9700 	}
9701 
9702 	for (i = 0; i <= ASC_MAX_TID; i++) {
9703 		asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9704 		asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9705 		asc_dvc->cfg->sdtr_period_offset[i] =
9706 		    (uchar)(ASC_DEF_SDTR_OFFSET |
9707 			    (asc_dvc->min_sdtr_index << 4));
9708 	}
9709 	eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9710 	if (write_eep) {
9711 		if ((i = AscSetEEPConfig(iop_base, eep_config,
9712 				     asc_dvc->bus_type)) != 0) {
9713 			ASC_PRINT1
9714 			    ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9715 			     i);
9716 		} else {
9717 			ASC_PRINT
9718 			    ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
9719 		}
9720 	}
9721 	return (warn_code);
9722 }
9723 
9724 static int AscInitGetConfig(struct Scsi_Host *shost)
9725 {
9726 	struct asc_board *board = shost_priv(shost);
9727 	ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9728 	unsigned short warn_code = 0;
9729 
9730 	asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9731 	if (asc_dvc->err_code != 0)
9732 		return asc_dvc->err_code;
9733 
9734 	if (AscFindSignature(asc_dvc->iop_base)) {
9735 		warn_code |= AscInitAscDvcVar(asc_dvc);
9736 		warn_code |= AscInitFromEEP(asc_dvc);
9737 		asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9738 		if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9739 			asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9740 	} else {
9741 		asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9742 	}
9743 
9744 	switch (warn_code) {
9745 	case 0:	/* No error */
9746 		break;
9747 	case ASC_WARN_IO_PORT_ROTATE:
9748 		shost_printk(KERN_WARNING, shost, "I/O port address "
9749 				"modified\n");
9750 		break;
9751 	case ASC_WARN_AUTO_CONFIG:
9752 		shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9753 				"enabled\n");
9754 		break;
9755 	case ASC_WARN_EEPROM_CHKSUM:
9756 		shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9757 		break;
9758 	case ASC_WARN_IRQ_MODIFIED:
9759 		shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9760 		break;
9761 	case ASC_WARN_CMD_QNG_CONFLICT:
9762 		shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9763 				"disconnects\n");
9764 		break;
9765 	default:
9766 		shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9767 				warn_code);
9768 		break;
9769 	}
9770 
9771 	if (asc_dvc->err_code != 0)
9772 		shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9773 			"0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9774 
9775 	return asc_dvc->err_code;
9776 }
9777 
9778 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
9779 {
9780 	struct asc_board *board = shost_priv(shost);
9781 	ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
9782 	PortAddr iop_base = asc_dvc->iop_base;
9783 	unsigned short cfg_msw;
9784 	unsigned short warn_code = 0;
9785 
9786 	asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9787 	if (asc_dvc->err_code != 0)
9788 		return asc_dvc->err_code;
9789 	if (!AscFindSignature(asc_dvc->iop_base)) {
9790 		asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9791 		return asc_dvc->err_code;
9792 	}
9793 
9794 	cfg_msw = AscGetChipCfgMsw(iop_base);
9795 	if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9796 		cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9797 		warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9798 		AscSetChipCfgMsw(iop_base, cfg_msw);
9799 	}
9800 	if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9801 	    asc_dvc->cfg->cmd_qng_enabled) {
9802 		asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9803 		warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9804 	}
9805 	if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9806 		warn_code |= ASC_WARN_AUTO_CONFIG;
9807 	}
9808 #ifdef CONFIG_PCI
9809 	if (asc_dvc->bus_type & ASC_IS_PCI) {
9810 		cfg_msw &= 0xFFC0;
9811 		AscSetChipCfgMsw(iop_base, cfg_msw);
9812 		if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
9813 		} else {
9814 			if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9815 			    (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9816 				asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9817 				asc_dvc->bug_fix_cntl |=
9818 				    ASC_BUG_FIX_ASYN_USE_SYN;
9819 			}
9820 		}
9821 	} else
9822 #endif /* CONFIG_PCI */
9823 	if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9824 		if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9825 		    == ASC_CHIP_VER_ASYN_BUG) {
9826 			asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
9827 		}
9828 	}
9829 	if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9830 	    asc_dvc->cfg->chip_scsi_id) {
9831 		asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9832 	}
9833 #ifdef CONFIG_ISA
9834 	if (asc_dvc->bus_type & ASC_IS_ISA) {
9835 		AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9836 		AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9837 	}
9838 #endif /* CONFIG_ISA */
9839 
9840 	asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9841 
9842 	switch (warn_code) {
9843 	case 0:	/* No error. */
9844 		break;
9845 	case ASC_WARN_IO_PORT_ROTATE:
9846 		shost_printk(KERN_WARNING, shost, "I/O port address "
9847 				"modified\n");
9848 		break;
9849 	case ASC_WARN_AUTO_CONFIG:
9850 		shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9851 				"enabled\n");
9852 		break;
9853 	case ASC_WARN_EEPROM_CHKSUM:
9854 		shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
9855 		break;
9856 	case ASC_WARN_IRQ_MODIFIED:
9857 		shost_printk(KERN_WARNING, shost, "IRQ modified\n");
9858 		break;
9859 	case ASC_WARN_CMD_QNG_CONFLICT:
9860 		shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9861 				"disconnects\n");
9862 		break;
9863 	default:
9864 		shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9865 				warn_code);
9866 		break;
9867 	}
9868 
9869 	if (asc_dvc->err_code != 0)
9870 		shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9871 			"0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
9872 
9873 	return asc_dvc->err_code;
9874 }
9875 
9876 /*
9877  * EEPROM Configuration.
9878  *
9879  * All drivers should use this structure to set the default EEPROM
9880  * configuration. The BIOS now uses this structure when it is built.
9881  * Additional structure information can be found in a_condor.h where
9882  * the structure is defined.
9883  *
9884  * The *_Field_IsChar structs are needed to correct for endianness.
9885  * These values are read from the board 16 bits at a time directly
9886  * into the structs. Because some fields are char, the values will be
9887  * in the wrong order. The *_Field_IsChar tells when to flip the
9888  * bytes. Data read and written to PCI memory is automatically swapped
9889  * on big-endian platforms so char fields read as words are actually being
9890  * unswapped on big-endian platforms.
9891  */
9892 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
9893 	ADV_EEPROM_BIOS_ENABLE,	/* cfg_lsw */
9894 	0x0000,			/* cfg_msw */
9895 	0xFFFF,			/* disc_enable */
9896 	0xFFFF,			/* wdtr_able */
9897 	0xFFFF,			/* sdtr_able */
9898 	0xFFFF,			/* start_motor */
9899 	0xFFFF,			/* tagqng_able */
9900 	0xFFFF,			/* bios_scan */
9901 	0,			/* scam_tolerant */
9902 	7,			/* adapter_scsi_id */
9903 	0,			/* bios_boot_delay */
9904 	3,			/* scsi_reset_delay */
9905 	0,			/* bios_id_lun */
9906 	0,			/* termination */
9907 	0,			/* reserved1 */
9908 	0xFFE7,			/* bios_ctrl */
9909 	0xFFFF,			/* ultra_able */
9910 	0,			/* reserved2 */
9911 	ASC_DEF_MAX_HOST_QNG,	/* max_host_qng */
9912 	ASC_DEF_MAX_DVC_QNG,	/* max_dvc_qng */
9913 	0,			/* dvc_cntl */
9914 	0,			/* bug_fix */
9915 	0,			/* serial_number_word1 */
9916 	0,			/* serial_number_word2 */
9917 	0,			/* serial_number_word3 */
9918 	0,			/* check_sum */
9919 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9920 	,			/* oem_name[16] */
9921 	0,			/* dvc_err_code */
9922 	0,			/* adv_err_code */
9923 	0,			/* adv_err_addr */
9924 	0,			/* saved_dvc_err_code */
9925 	0,			/* saved_adv_err_code */
9926 	0,			/* saved_adv_err_addr */
9927 	0			/* num_of_err */
9928 };
9929 
9930 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
9931 	0,			/* cfg_lsw */
9932 	0,			/* cfg_msw */
9933 	0,			/* -disc_enable */
9934 	0,			/* wdtr_able */
9935 	0,			/* sdtr_able */
9936 	0,			/* start_motor */
9937 	0,			/* tagqng_able */
9938 	0,			/* bios_scan */
9939 	0,			/* scam_tolerant */
9940 	1,			/* adapter_scsi_id */
9941 	1,			/* bios_boot_delay */
9942 	1,			/* scsi_reset_delay */
9943 	1,			/* bios_id_lun */
9944 	1,			/* termination */
9945 	1,			/* reserved1 */
9946 	0,			/* bios_ctrl */
9947 	0,			/* ultra_able */
9948 	0,			/* reserved2 */
9949 	1,			/* max_host_qng */
9950 	1,			/* max_dvc_qng */
9951 	0,			/* dvc_cntl */
9952 	0,			/* bug_fix */
9953 	0,			/* serial_number_word1 */
9954 	0,			/* serial_number_word2 */
9955 	0,			/* serial_number_word3 */
9956 	0,			/* check_sum */
9957 	{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9958 	,			/* oem_name[16] */
9959 	0,			/* dvc_err_code */
9960 	0,			/* adv_err_code */
9961 	0,			/* adv_err_addr */
9962 	0,			/* saved_dvc_err_code */
9963 	0,			/* saved_adv_err_code */
9964 	0,			/* saved_adv_err_addr */
9965 	0			/* num_of_err */
9966 };
9967 
9968 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
9969 	ADV_EEPROM_BIOS_ENABLE,	/* 00 cfg_lsw */
9970 	0x0000,			/* 01 cfg_msw */
9971 	0xFFFF,			/* 02 disc_enable */
9972 	0xFFFF,			/* 03 wdtr_able */
9973 	0x4444,			/* 04 sdtr_speed1 */
9974 	0xFFFF,			/* 05 start_motor */
9975 	0xFFFF,			/* 06 tagqng_able */
9976 	0xFFFF,			/* 07 bios_scan */
9977 	0,			/* 08 scam_tolerant */
9978 	7,			/* 09 adapter_scsi_id */
9979 	0,			/*    bios_boot_delay */
9980 	3,			/* 10 scsi_reset_delay */
9981 	0,			/*    bios_id_lun */
9982 	0,			/* 11 termination_se */
9983 	0,			/*    termination_lvd */
9984 	0xFFE7,			/* 12 bios_ctrl */
9985 	0x4444,			/* 13 sdtr_speed2 */
9986 	0x4444,			/* 14 sdtr_speed3 */
9987 	ASC_DEF_MAX_HOST_QNG,	/* 15 max_host_qng */
9988 	ASC_DEF_MAX_DVC_QNG,	/*    max_dvc_qng */
9989 	0,			/* 16 dvc_cntl */
9990 	0x4444,			/* 17 sdtr_speed4 */
9991 	0,			/* 18 serial_number_word1 */
9992 	0,			/* 19 serial_number_word2 */
9993 	0,			/* 20 serial_number_word3 */
9994 	0,			/* 21 check_sum */
9995 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9996 	,			/* 22-29 oem_name[16] */
9997 	0,			/* 30 dvc_err_code */
9998 	0,			/* 31 adv_err_code */
9999 	0,			/* 32 adv_err_addr */
10000 	0,			/* 33 saved_dvc_err_code */
10001 	0,			/* 34 saved_adv_err_code */
10002 	0,			/* 35 saved_adv_err_addr */
10003 	0,			/* 36 reserved */
10004 	0,			/* 37 reserved */
10005 	0,			/* 38 reserved */
10006 	0,			/* 39 reserved */
10007 	0,			/* 40 reserved */
10008 	0,			/* 41 reserved */
10009 	0,			/* 42 reserved */
10010 	0,			/* 43 reserved */
10011 	0,			/* 44 reserved */
10012 	0,			/* 45 reserved */
10013 	0,			/* 46 reserved */
10014 	0,			/* 47 reserved */
10015 	0,			/* 48 reserved */
10016 	0,			/* 49 reserved */
10017 	0,			/* 50 reserved */
10018 	0,			/* 51 reserved */
10019 	0,			/* 52 reserved */
10020 	0,			/* 53 reserved */
10021 	0,			/* 54 reserved */
10022 	0,			/* 55 reserved */
10023 	0,			/* 56 cisptr_lsw */
10024 	0,			/* 57 cisprt_msw */
10025 	PCI_VENDOR_ID_ASP,	/* 58 subsysvid */
10026 	PCI_DEVICE_ID_38C0800_REV1,	/* 59 subsysid */
10027 	0,			/* 60 reserved */
10028 	0,			/* 61 reserved */
10029 	0,			/* 62 reserved */
10030 	0			/* 63 reserved */
10031 };
10032 
10033 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
10034 	0,			/* 00 cfg_lsw */
10035 	0,			/* 01 cfg_msw */
10036 	0,			/* 02 disc_enable */
10037 	0,			/* 03 wdtr_able */
10038 	0,			/* 04 sdtr_speed1 */
10039 	0,			/* 05 start_motor */
10040 	0,			/* 06 tagqng_able */
10041 	0,			/* 07 bios_scan */
10042 	0,			/* 08 scam_tolerant */
10043 	1,			/* 09 adapter_scsi_id */
10044 	1,			/*    bios_boot_delay */
10045 	1,			/* 10 scsi_reset_delay */
10046 	1,			/*    bios_id_lun */
10047 	1,			/* 11 termination_se */
10048 	1,			/*    termination_lvd */
10049 	0,			/* 12 bios_ctrl */
10050 	0,			/* 13 sdtr_speed2 */
10051 	0,			/* 14 sdtr_speed3 */
10052 	1,			/* 15 max_host_qng */
10053 	1,			/*    max_dvc_qng */
10054 	0,			/* 16 dvc_cntl */
10055 	0,			/* 17 sdtr_speed4 */
10056 	0,			/* 18 serial_number_word1 */
10057 	0,			/* 19 serial_number_word2 */
10058 	0,			/* 20 serial_number_word3 */
10059 	0,			/* 21 check_sum */
10060 	{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10061 	,			/* 22-29 oem_name[16] */
10062 	0,			/* 30 dvc_err_code */
10063 	0,			/* 31 adv_err_code */
10064 	0,			/* 32 adv_err_addr */
10065 	0,			/* 33 saved_dvc_err_code */
10066 	0,			/* 34 saved_adv_err_code */
10067 	0,			/* 35 saved_adv_err_addr */
10068 	0,			/* 36 reserved */
10069 	0,			/* 37 reserved */
10070 	0,			/* 38 reserved */
10071 	0,			/* 39 reserved */
10072 	0,			/* 40 reserved */
10073 	0,			/* 41 reserved */
10074 	0,			/* 42 reserved */
10075 	0,			/* 43 reserved */
10076 	0,			/* 44 reserved */
10077 	0,			/* 45 reserved */
10078 	0,			/* 46 reserved */
10079 	0,			/* 47 reserved */
10080 	0,			/* 48 reserved */
10081 	0,			/* 49 reserved */
10082 	0,			/* 50 reserved */
10083 	0,			/* 51 reserved */
10084 	0,			/* 52 reserved */
10085 	0,			/* 53 reserved */
10086 	0,			/* 54 reserved */
10087 	0,			/* 55 reserved */
10088 	0,			/* 56 cisptr_lsw */
10089 	0,			/* 57 cisprt_msw */
10090 	0,			/* 58 subsysvid */
10091 	0,			/* 59 subsysid */
10092 	0,			/* 60 reserved */
10093 	0,			/* 61 reserved */
10094 	0,			/* 62 reserved */
10095 	0			/* 63 reserved */
10096 };
10097 
10098 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
10099 	ADV_EEPROM_BIOS_ENABLE,	/* 00 cfg_lsw */
10100 	0x0000,			/* 01 cfg_msw */
10101 	0xFFFF,			/* 02 disc_enable */
10102 	0xFFFF,			/* 03 wdtr_able */
10103 	0x5555,			/* 04 sdtr_speed1 */
10104 	0xFFFF,			/* 05 start_motor */
10105 	0xFFFF,			/* 06 tagqng_able */
10106 	0xFFFF,			/* 07 bios_scan */
10107 	0,			/* 08 scam_tolerant */
10108 	7,			/* 09 adapter_scsi_id */
10109 	0,			/*    bios_boot_delay */
10110 	3,			/* 10 scsi_reset_delay */
10111 	0,			/*    bios_id_lun */
10112 	0,			/* 11 termination_se */
10113 	0,			/*    termination_lvd */
10114 	0xFFE7,			/* 12 bios_ctrl */
10115 	0x5555,			/* 13 sdtr_speed2 */
10116 	0x5555,			/* 14 sdtr_speed3 */
10117 	ASC_DEF_MAX_HOST_QNG,	/* 15 max_host_qng */
10118 	ASC_DEF_MAX_DVC_QNG,	/*    max_dvc_qng */
10119 	0,			/* 16 dvc_cntl */
10120 	0x5555,			/* 17 sdtr_speed4 */
10121 	0,			/* 18 serial_number_word1 */
10122 	0,			/* 19 serial_number_word2 */
10123 	0,			/* 20 serial_number_word3 */
10124 	0,			/* 21 check_sum */
10125 	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10126 	,			/* 22-29 oem_name[16] */
10127 	0,			/* 30 dvc_err_code */
10128 	0,			/* 31 adv_err_code */
10129 	0,			/* 32 adv_err_addr */
10130 	0,			/* 33 saved_dvc_err_code */
10131 	0,			/* 34 saved_adv_err_code */
10132 	0,			/* 35 saved_adv_err_addr */
10133 	0,			/* 36 reserved */
10134 	0,			/* 37 reserved */
10135 	0,			/* 38 reserved */
10136 	0,			/* 39 reserved */
10137 	0,			/* 40 reserved */
10138 	0,			/* 41 reserved */
10139 	0,			/* 42 reserved */
10140 	0,			/* 43 reserved */
10141 	0,			/* 44 reserved */
10142 	0,			/* 45 reserved */
10143 	0,			/* 46 reserved */
10144 	0,			/* 47 reserved */
10145 	0,			/* 48 reserved */
10146 	0,			/* 49 reserved */
10147 	0,			/* 50 reserved */
10148 	0,			/* 51 reserved */
10149 	0,			/* 52 reserved */
10150 	0,			/* 53 reserved */
10151 	0,			/* 54 reserved */
10152 	0,			/* 55 reserved */
10153 	0,			/* 56 cisptr_lsw */
10154 	0,			/* 57 cisprt_msw */
10155 	PCI_VENDOR_ID_ASP,	/* 58 subsysvid */
10156 	PCI_DEVICE_ID_38C1600_REV1,	/* 59 subsysid */
10157 	0,			/* 60 reserved */
10158 	0,			/* 61 reserved */
10159 	0,			/* 62 reserved */
10160 	0			/* 63 reserved */
10161 };
10162 
10163 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
10164 	0,			/* 00 cfg_lsw */
10165 	0,			/* 01 cfg_msw */
10166 	0,			/* 02 disc_enable */
10167 	0,			/* 03 wdtr_able */
10168 	0,			/* 04 sdtr_speed1 */
10169 	0,			/* 05 start_motor */
10170 	0,			/* 06 tagqng_able */
10171 	0,			/* 07 bios_scan */
10172 	0,			/* 08 scam_tolerant */
10173 	1,			/* 09 adapter_scsi_id */
10174 	1,			/*    bios_boot_delay */
10175 	1,			/* 10 scsi_reset_delay */
10176 	1,			/*    bios_id_lun */
10177 	1,			/* 11 termination_se */
10178 	1,			/*    termination_lvd */
10179 	0,			/* 12 bios_ctrl */
10180 	0,			/* 13 sdtr_speed2 */
10181 	0,			/* 14 sdtr_speed3 */
10182 	1,			/* 15 max_host_qng */
10183 	1,			/*    max_dvc_qng */
10184 	0,			/* 16 dvc_cntl */
10185 	0,			/* 17 sdtr_speed4 */
10186 	0,			/* 18 serial_number_word1 */
10187 	0,			/* 19 serial_number_word2 */
10188 	0,			/* 20 serial_number_word3 */
10189 	0,			/* 21 check_sum */
10190 	{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10191 	,			/* 22-29 oem_name[16] */
10192 	0,			/* 30 dvc_err_code */
10193 	0,			/* 31 adv_err_code */
10194 	0,			/* 32 adv_err_addr */
10195 	0,			/* 33 saved_dvc_err_code */
10196 	0,			/* 34 saved_adv_err_code */
10197 	0,			/* 35 saved_adv_err_addr */
10198 	0,			/* 36 reserved */
10199 	0,			/* 37 reserved */
10200 	0,			/* 38 reserved */
10201 	0,			/* 39 reserved */
10202 	0,			/* 40 reserved */
10203 	0,			/* 41 reserved */
10204 	0,			/* 42 reserved */
10205 	0,			/* 43 reserved */
10206 	0,			/* 44 reserved */
10207 	0,			/* 45 reserved */
10208 	0,			/* 46 reserved */
10209 	0,			/* 47 reserved */
10210 	0,			/* 48 reserved */
10211 	0,			/* 49 reserved */
10212 	0,			/* 50 reserved */
10213 	0,			/* 51 reserved */
10214 	0,			/* 52 reserved */
10215 	0,			/* 53 reserved */
10216 	0,			/* 54 reserved */
10217 	0,			/* 55 reserved */
10218 	0,			/* 56 cisptr_lsw */
10219 	0,			/* 57 cisprt_msw */
10220 	0,			/* 58 subsysvid */
10221 	0,			/* 59 subsysid */
10222 	0,			/* 60 reserved */
10223 	0,			/* 61 reserved */
10224 	0,			/* 62 reserved */
10225 	0			/* 63 reserved */
10226 };
10227 
10228 #ifdef CONFIG_PCI
10229 /*
10230  * Wait for EEPROM command to complete
10231  */
10232 static void AdvWaitEEPCmd(AdvPortAddr iop_base)
10233 {
10234 	int eep_delay_ms;
10235 
10236 	for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10237 		if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10238 		    ASC_EEP_CMD_DONE) {
10239 			break;
10240 		}
10241 		mdelay(1);
10242 	}
10243 	if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10244 	    0)
10245 		BUG();
10246 }
10247 
10248 /*
10249  * Read the EEPROM from specified location
10250  */
10251 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
10252 {
10253 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10254 			     ASC_EEP_CMD_READ | eep_word_addr);
10255 	AdvWaitEEPCmd(iop_base);
10256 	return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10257 }
10258 
10259 /*
10260  * Write the EEPROM from 'cfg_buf'.
10261  */
10262 static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10263 				ADVEEP_3550_CONFIG *cfg_buf)
10264 {
10265 	ushort *wbuf;
10266 	ushort addr, chksum;
10267 	ushort *charfields;
10268 
10269 	wbuf = (ushort *)cfg_buf;
10270 	charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10271 	chksum = 0;
10272 
10273 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10274 	AdvWaitEEPCmd(iop_base);
10275 
10276 	/*
10277 	 * Write EEPROM from word 0 to word 20.
10278 	 */
10279 	for (addr = ADV_EEP_DVC_CFG_BEGIN;
10280 	     addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10281 		ushort word;
10282 
10283 		if (*charfields++) {
10284 			word = cpu_to_le16(*wbuf);
10285 		} else {
10286 			word = *wbuf;
10287 		}
10288 		chksum += *wbuf;	/* Checksum is calculated from word values. */
10289 		AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10290 		AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10291 				     ASC_EEP_CMD_WRITE | addr);
10292 		AdvWaitEEPCmd(iop_base);
10293 		mdelay(ADV_EEP_DELAY_MS);
10294 	}
10295 
10296 	/*
10297 	 * Write EEPROM checksum at word 21.
10298 	 */
10299 	AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10300 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10301 	AdvWaitEEPCmd(iop_base);
10302 	wbuf++;
10303 	charfields++;
10304 
10305 	/*
10306 	 * Write EEPROM OEM name at words 22 to 29.
10307 	 */
10308 	for (addr = ADV_EEP_DVC_CTL_BEGIN;
10309 	     addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10310 		ushort word;
10311 
10312 		if (*charfields++) {
10313 			word = cpu_to_le16(*wbuf);
10314 		} else {
10315 			word = *wbuf;
10316 		}
10317 		AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10318 		AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10319 				     ASC_EEP_CMD_WRITE | addr);
10320 		AdvWaitEEPCmd(iop_base);
10321 	}
10322 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10323 	AdvWaitEEPCmd(iop_base);
10324 }
10325 
10326 /*
10327  * Write the EEPROM from 'cfg_buf'.
10328  */
10329 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10330 				   ADVEEP_38C0800_CONFIG *cfg_buf)
10331 {
10332 	ushort *wbuf;
10333 	ushort *charfields;
10334 	ushort addr, chksum;
10335 
10336 	wbuf = (ushort *)cfg_buf;
10337 	charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10338 	chksum = 0;
10339 
10340 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10341 	AdvWaitEEPCmd(iop_base);
10342 
10343 	/*
10344 	 * Write EEPROM from word 0 to word 20.
10345 	 */
10346 	for (addr = ADV_EEP_DVC_CFG_BEGIN;
10347 	     addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10348 		ushort word;
10349 
10350 		if (*charfields++) {
10351 			word = cpu_to_le16(*wbuf);
10352 		} else {
10353 			word = *wbuf;
10354 		}
10355 		chksum += *wbuf;	/* Checksum is calculated from word values. */
10356 		AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10357 		AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10358 				     ASC_EEP_CMD_WRITE | addr);
10359 		AdvWaitEEPCmd(iop_base);
10360 		mdelay(ADV_EEP_DELAY_MS);
10361 	}
10362 
10363 	/*
10364 	 * Write EEPROM checksum at word 21.
10365 	 */
10366 	AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10367 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10368 	AdvWaitEEPCmd(iop_base);
10369 	wbuf++;
10370 	charfields++;
10371 
10372 	/*
10373 	 * Write EEPROM OEM name at words 22 to 29.
10374 	 */
10375 	for (addr = ADV_EEP_DVC_CTL_BEGIN;
10376 	     addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10377 		ushort word;
10378 
10379 		if (*charfields++) {
10380 			word = cpu_to_le16(*wbuf);
10381 		} else {
10382 			word = *wbuf;
10383 		}
10384 		AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10385 		AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10386 				     ASC_EEP_CMD_WRITE | addr);
10387 		AdvWaitEEPCmd(iop_base);
10388 	}
10389 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10390 	AdvWaitEEPCmd(iop_base);
10391 }
10392 
10393 /*
10394  * Write the EEPROM from 'cfg_buf'.
10395  */
10396 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10397 				   ADVEEP_38C1600_CONFIG *cfg_buf)
10398 {
10399 	ushort *wbuf;
10400 	ushort *charfields;
10401 	ushort addr, chksum;
10402 
10403 	wbuf = (ushort *)cfg_buf;
10404 	charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10405 	chksum = 0;
10406 
10407 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10408 	AdvWaitEEPCmd(iop_base);
10409 
10410 	/*
10411 	 * Write EEPROM from word 0 to word 20.
10412 	 */
10413 	for (addr = ADV_EEP_DVC_CFG_BEGIN;
10414 	     addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10415 		ushort word;
10416 
10417 		if (*charfields++) {
10418 			word = cpu_to_le16(*wbuf);
10419 		} else {
10420 			word = *wbuf;
10421 		}
10422 		chksum += *wbuf;	/* Checksum is calculated from word values. */
10423 		AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10424 		AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10425 				     ASC_EEP_CMD_WRITE | addr);
10426 		AdvWaitEEPCmd(iop_base);
10427 		mdelay(ADV_EEP_DELAY_MS);
10428 	}
10429 
10430 	/*
10431 	 * Write EEPROM checksum at word 21.
10432 	 */
10433 	AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10434 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10435 	AdvWaitEEPCmd(iop_base);
10436 	wbuf++;
10437 	charfields++;
10438 
10439 	/*
10440 	 * Write EEPROM OEM name at words 22 to 29.
10441 	 */
10442 	for (addr = ADV_EEP_DVC_CTL_BEGIN;
10443 	     addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10444 		ushort word;
10445 
10446 		if (*charfields++) {
10447 			word = cpu_to_le16(*wbuf);
10448 		} else {
10449 			word = *wbuf;
10450 		}
10451 		AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10452 		AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10453 				     ASC_EEP_CMD_WRITE | addr);
10454 		AdvWaitEEPCmd(iop_base);
10455 	}
10456 	AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10457 	AdvWaitEEPCmd(iop_base);
10458 }
10459 
10460 /*
10461  * Read EEPROM configuration into the specified buffer.
10462  *
10463  * Return a checksum based on the EEPROM configuration read.
10464  */
10465 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10466 				  ADVEEP_3550_CONFIG *cfg_buf)
10467 {
10468 	ushort wval, chksum;
10469 	ushort *wbuf;
10470 	int eep_addr;
10471 	ushort *charfields;
10472 
10473 	charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
10474 	wbuf = (ushort *)cfg_buf;
10475 	chksum = 0;
10476 
10477 	for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10478 	     eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10479 		wval = AdvReadEEPWord(iop_base, eep_addr);
10480 		chksum += wval;	/* Checksum is calculated from word values. */
10481 		if (*charfields++) {
10482 			*wbuf = le16_to_cpu(wval);
10483 		} else {
10484 			*wbuf = wval;
10485 		}
10486 	}
10487 	/* Read checksum word. */
10488 	*wbuf = AdvReadEEPWord(iop_base, eep_addr);
10489 	wbuf++;
10490 	charfields++;
10491 
10492 	/* Read rest of EEPROM not covered by the checksum. */
10493 	for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10494 	     eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10495 		*wbuf = AdvReadEEPWord(iop_base, eep_addr);
10496 		if (*charfields++) {
10497 			*wbuf = le16_to_cpu(*wbuf);
10498 		}
10499 	}
10500 	return chksum;
10501 }
10502 
10503 /*
10504  * Read EEPROM configuration into the specified buffer.
10505  *
10506  * Return a checksum based on the EEPROM configuration read.
10507  */
10508 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10509 				     ADVEEP_38C0800_CONFIG *cfg_buf)
10510 {
10511 	ushort wval, chksum;
10512 	ushort *wbuf;
10513 	int eep_addr;
10514 	ushort *charfields;
10515 
10516 	charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10517 	wbuf = (ushort *)cfg_buf;
10518 	chksum = 0;
10519 
10520 	for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10521 	     eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10522 		wval = AdvReadEEPWord(iop_base, eep_addr);
10523 		chksum += wval;	/* Checksum is calculated from word values. */
10524 		if (*charfields++) {
10525 			*wbuf = le16_to_cpu(wval);
10526 		} else {
10527 			*wbuf = wval;
10528 		}
10529 	}
10530 	/* Read checksum word. */
10531 	*wbuf = AdvReadEEPWord(iop_base, eep_addr);
10532 	wbuf++;
10533 	charfields++;
10534 
10535 	/* Read rest of EEPROM not covered by the checksum. */
10536 	for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10537 	     eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10538 		*wbuf = AdvReadEEPWord(iop_base, eep_addr);
10539 		if (*charfields++) {
10540 			*wbuf = le16_to_cpu(*wbuf);
10541 		}
10542 	}
10543 	return chksum;
10544 }
10545 
10546 /*
10547  * Read EEPROM configuration into the specified buffer.
10548  *
10549  * Return a checksum based on the EEPROM configuration read.
10550  */
10551 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10552 				     ADVEEP_38C1600_CONFIG *cfg_buf)
10553 {
10554 	ushort wval, chksum;
10555 	ushort *wbuf;
10556 	int eep_addr;
10557 	ushort *charfields;
10558 
10559 	charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
10560 	wbuf = (ushort *)cfg_buf;
10561 	chksum = 0;
10562 
10563 	for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10564 	     eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10565 		wval = AdvReadEEPWord(iop_base, eep_addr);
10566 		chksum += wval;	/* Checksum is calculated from word values. */
10567 		if (*charfields++) {
10568 			*wbuf = le16_to_cpu(wval);
10569 		} else {
10570 			*wbuf = wval;
10571 		}
10572 	}
10573 	/* Read checksum word. */
10574 	*wbuf = AdvReadEEPWord(iop_base, eep_addr);
10575 	wbuf++;
10576 	charfields++;
10577 
10578 	/* Read rest of EEPROM not covered by the checksum. */
10579 	for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10580 	     eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10581 		*wbuf = AdvReadEEPWord(iop_base, eep_addr);
10582 		if (*charfields++) {
10583 			*wbuf = le16_to_cpu(*wbuf);
10584 		}
10585 	}
10586 	return chksum;
10587 }
10588 
10589 /*
10590  * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10591  * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10592  * all of this is done.
10593  *
10594  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10595  *
10596  * For a non-fatal error return a warning code. If there are no warnings
10597  * then 0 is returned.
10598  *
10599  * Note: Chip is stopped on entry.
10600  */
10601 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
10602 {
10603 	AdvPortAddr iop_base;
10604 	ushort warn_code;
10605 	ADVEEP_3550_CONFIG eep_config;
10606 
10607 	iop_base = asc_dvc->iop_base;
10608 
10609 	warn_code = 0;
10610 
10611 	/*
10612 	 * Read the board's EEPROM configuration.
10613 	 *
10614 	 * Set default values if a bad checksum is found.
10615 	 */
10616 	if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10617 		warn_code |= ASC_WARN_EEPROM_CHKSUM;
10618 
10619 		/*
10620 		 * Set EEPROM default values.
10621 		 */
10622 		memcpy(&eep_config, &Default_3550_EEPROM_Config,
10623 			sizeof(ADVEEP_3550_CONFIG));
10624 
10625 		/*
10626 		 * Assume the 6 byte board serial number that was read from
10627 		 * EEPROM is correct even if the EEPROM checksum failed.
10628 		 */
10629 		eep_config.serial_number_word3 =
10630 		    AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10631 
10632 		eep_config.serial_number_word2 =
10633 		    AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10634 
10635 		eep_config.serial_number_word1 =
10636 		    AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10637 
10638 		AdvSet3550EEPConfig(iop_base, &eep_config);
10639 	}
10640 	/*
10641 	 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10642 	 * EEPROM configuration that was read.
10643 	 *
10644 	 * This is the mapping of EEPROM fields to Adv Library fields.
10645 	 */
10646 	asc_dvc->wdtr_able = eep_config.wdtr_able;
10647 	asc_dvc->sdtr_able = eep_config.sdtr_able;
10648 	asc_dvc->ultra_able = eep_config.ultra_able;
10649 	asc_dvc->tagqng_able = eep_config.tagqng_able;
10650 	asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10651 	asc_dvc->max_host_qng = eep_config.max_host_qng;
10652 	asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10653 	asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10654 	asc_dvc->start_motor = eep_config.start_motor;
10655 	asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10656 	asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10657 	asc_dvc->no_scam = eep_config.scam_tolerant;
10658 	asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10659 	asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10660 	asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10661 
10662 	/*
10663 	 * Set the host maximum queuing (max. 253, min. 16) and the per device
10664 	 * maximum queuing (max. 63, min. 4).
10665 	 */
10666 	if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10667 		eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10668 	} else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10669 		/* If the value is zero, assume it is uninitialized. */
10670 		if (eep_config.max_host_qng == 0) {
10671 			eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10672 		} else {
10673 			eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10674 		}
10675 	}
10676 
10677 	if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10678 		eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10679 	} else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10680 		/* If the value is zero, assume it is uninitialized. */
10681 		if (eep_config.max_dvc_qng == 0) {
10682 			eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10683 		} else {
10684 			eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10685 		}
10686 	}
10687 
10688 	/*
10689 	 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10690 	 * set 'max_dvc_qng' to 'max_host_qng'.
10691 	 */
10692 	if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10693 		eep_config.max_dvc_qng = eep_config.max_host_qng;
10694 	}
10695 
10696 	/*
10697 	 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10698 	 * values based on possibly adjusted EEPROM values.
10699 	 */
10700 	asc_dvc->max_host_qng = eep_config.max_host_qng;
10701 	asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10702 
10703 	/*
10704 	 * If the EEPROM 'termination' field is set to automatic (0), then set
10705 	 * the ADV_DVC_CFG 'termination' field to automatic also.
10706 	 *
10707 	 * If the termination is specified with a non-zero 'termination'
10708 	 * value check that a legal value is set and set the ADV_DVC_CFG
10709 	 * 'termination' field appropriately.
10710 	 */
10711 	if (eep_config.termination == 0) {
10712 		asc_dvc->cfg->termination = 0;	/* auto termination */
10713 	} else {
10714 		/* Enable manual control with low off / high off. */
10715 		if (eep_config.termination == 1) {
10716 			asc_dvc->cfg->termination = TERM_CTL_SEL;
10717 
10718 			/* Enable manual control with low off / high on. */
10719 		} else if (eep_config.termination == 2) {
10720 			asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10721 
10722 			/* Enable manual control with low on / high on. */
10723 		} else if (eep_config.termination == 3) {
10724 			asc_dvc->cfg->termination =
10725 			    TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10726 		} else {
10727 			/*
10728 			 * The EEPROM 'termination' field contains a bad value. Use
10729 			 * automatic termination instead.
10730 			 */
10731 			asc_dvc->cfg->termination = 0;
10732 			warn_code |= ASC_WARN_EEPROM_TERMINATION;
10733 		}
10734 	}
10735 
10736 	return warn_code;
10737 }
10738 
10739 /*
10740  * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10741  * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10742  * all of this is done.
10743  *
10744  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10745  *
10746  * For a non-fatal error return a warning code. If there are no warnings
10747  * then 0 is returned.
10748  *
10749  * Note: Chip is stopped on entry.
10750  */
10751 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
10752 {
10753 	AdvPortAddr iop_base;
10754 	ushort warn_code;
10755 	ADVEEP_38C0800_CONFIG eep_config;
10756 	uchar tid, termination;
10757 	ushort sdtr_speed = 0;
10758 
10759 	iop_base = asc_dvc->iop_base;
10760 
10761 	warn_code = 0;
10762 
10763 	/*
10764 	 * Read the board's EEPROM configuration.
10765 	 *
10766 	 * Set default values if a bad checksum is found.
10767 	 */
10768 	if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10769 	    eep_config.check_sum) {
10770 		warn_code |= ASC_WARN_EEPROM_CHKSUM;
10771 
10772 		/*
10773 		 * Set EEPROM default values.
10774 		 */
10775 		memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10776 			sizeof(ADVEEP_38C0800_CONFIG));
10777 
10778 		/*
10779 		 * Assume the 6 byte board serial number that was read from
10780 		 * EEPROM is correct even if the EEPROM checksum failed.
10781 		 */
10782 		eep_config.serial_number_word3 =
10783 		    AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10784 
10785 		eep_config.serial_number_word2 =
10786 		    AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10787 
10788 		eep_config.serial_number_word1 =
10789 		    AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10790 
10791 		AdvSet38C0800EEPConfig(iop_base, &eep_config);
10792 	}
10793 	/*
10794 	 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10795 	 * EEPROM configuration that was read.
10796 	 *
10797 	 * This is the mapping of EEPROM fields to Adv Library fields.
10798 	 */
10799 	asc_dvc->wdtr_able = eep_config.wdtr_able;
10800 	asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10801 	asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10802 	asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10803 	asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10804 	asc_dvc->tagqng_able = eep_config.tagqng_able;
10805 	asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10806 	asc_dvc->max_host_qng = eep_config.max_host_qng;
10807 	asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10808 	asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10809 	asc_dvc->start_motor = eep_config.start_motor;
10810 	asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10811 	asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10812 	asc_dvc->no_scam = eep_config.scam_tolerant;
10813 	asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10814 	asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10815 	asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
10816 
10817 	/*
10818 	 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10819 	 * are set, then set an 'sdtr_able' bit for it.
10820 	 */
10821 	asc_dvc->sdtr_able = 0;
10822 	for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10823 		if (tid == 0) {
10824 			sdtr_speed = asc_dvc->sdtr_speed1;
10825 		} else if (tid == 4) {
10826 			sdtr_speed = asc_dvc->sdtr_speed2;
10827 		} else if (tid == 8) {
10828 			sdtr_speed = asc_dvc->sdtr_speed3;
10829 		} else if (tid == 12) {
10830 			sdtr_speed = asc_dvc->sdtr_speed4;
10831 		}
10832 		if (sdtr_speed & ADV_MAX_TID) {
10833 			asc_dvc->sdtr_able |= (1 << tid);
10834 		}
10835 		sdtr_speed >>= 4;
10836 	}
10837 
10838 	/*
10839 	 * Set the host maximum queuing (max. 253, min. 16) and the per device
10840 	 * maximum queuing (max. 63, min. 4).
10841 	 */
10842 	if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10843 		eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10844 	} else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10845 		/* If the value is zero, assume it is uninitialized. */
10846 		if (eep_config.max_host_qng == 0) {
10847 			eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10848 		} else {
10849 			eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10850 		}
10851 	}
10852 
10853 	if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10854 		eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10855 	} else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10856 		/* If the value is zero, assume it is uninitialized. */
10857 		if (eep_config.max_dvc_qng == 0) {
10858 			eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10859 		} else {
10860 			eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10861 		}
10862 	}
10863 
10864 	/*
10865 	 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10866 	 * set 'max_dvc_qng' to 'max_host_qng'.
10867 	 */
10868 	if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10869 		eep_config.max_dvc_qng = eep_config.max_host_qng;
10870 	}
10871 
10872 	/*
10873 	 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10874 	 * values based on possibly adjusted EEPROM values.
10875 	 */
10876 	asc_dvc->max_host_qng = eep_config.max_host_qng;
10877 	asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10878 
10879 	/*
10880 	 * If the EEPROM 'termination' field is set to automatic (0), then set
10881 	 * the ADV_DVC_CFG 'termination' field to automatic also.
10882 	 *
10883 	 * If the termination is specified with a non-zero 'termination'
10884 	 * value check that a legal value is set and set the ADV_DVC_CFG
10885 	 * 'termination' field appropriately.
10886 	 */
10887 	if (eep_config.termination_se == 0) {
10888 		termination = 0;	/* auto termination for SE */
10889 	} else {
10890 		/* Enable manual control with low off / high off. */
10891 		if (eep_config.termination_se == 1) {
10892 			termination = 0;
10893 
10894 			/* Enable manual control with low off / high on. */
10895 		} else if (eep_config.termination_se == 2) {
10896 			termination = TERM_SE_HI;
10897 
10898 			/* Enable manual control with low on / high on. */
10899 		} else if (eep_config.termination_se == 3) {
10900 			termination = TERM_SE;
10901 		} else {
10902 			/*
10903 			 * The EEPROM 'termination_se' field contains a bad value.
10904 			 * Use automatic termination instead.
10905 			 */
10906 			termination = 0;
10907 			warn_code |= ASC_WARN_EEPROM_TERMINATION;
10908 		}
10909 	}
10910 
10911 	if (eep_config.termination_lvd == 0) {
10912 		asc_dvc->cfg->termination = termination;	/* auto termination for LVD */
10913 	} else {
10914 		/* Enable manual control with low off / high off. */
10915 		if (eep_config.termination_lvd == 1) {
10916 			asc_dvc->cfg->termination = termination;
10917 
10918 			/* Enable manual control with low off / high on. */
10919 		} else if (eep_config.termination_lvd == 2) {
10920 			asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10921 
10922 			/* Enable manual control with low on / high on. */
10923 		} else if (eep_config.termination_lvd == 3) {
10924 			asc_dvc->cfg->termination = termination | TERM_LVD;
10925 		} else {
10926 			/*
10927 			 * The EEPROM 'termination_lvd' field contains a bad value.
10928 			 * Use automatic termination instead.
10929 			 */
10930 			asc_dvc->cfg->termination = termination;
10931 			warn_code |= ASC_WARN_EEPROM_TERMINATION;
10932 		}
10933 	}
10934 
10935 	return warn_code;
10936 }
10937 
10938 /*
10939  * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10940  * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10941  * all of this is done.
10942  *
10943  * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
10944  *
10945  * For a non-fatal error return a warning code. If there are no warnings
10946  * then 0 is returned.
10947  *
10948  * Note: Chip is stopped on entry.
10949  */
10950 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
10951 {
10952 	AdvPortAddr iop_base;
10953 	ushort warn_code;
10954 	ADVEEP_38C1600_CONFIG eep_config;
10955 	uchar tid, termination;
10956 	ushort sdtr_speed = 0;
10957 
10958 	iop_base = asc_dvc->iop_base;
10959 
10960 	warn_code = 0;
10961 
10962 	/*
10963 	 * Read the board's EEPROM configuration.
10964 	 *
10965 	 * Set default values if a bad checksum is found.
10966 	 */
10967 	if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10968 	    eep_config.check_sum) {
10969 		struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10970 		warn_code |= ASC_WARN_EEPROM_CHKSUM;
10971 
10972 		/*
10973 		 * Set EEPROM default values.
10974 		 */
10975 		memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10976 			sizeof(ADVEEP_38C1600_CONFIG));
10977 
10978 		if (PCI_FUNC(pdev->devfn) != 0) {
10979 			u8 ints;
10980 			/*
10981 			 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10982 			 * and old Mac system booting problem. The Expansion
10983 			 * ROM must be disabled in Function 1 for these systems
10984 			 */
10985 			eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10986 			/*
10987 			 * Clear the INTAB (bit 11) if the GPIO 0 input
10988 			 * indicates the Function 1 interrupt line is wired
10989 			 * to INTB.
10990 			 *
10991 			 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10992 			 *   1 - Function 1 interrupt line wired to INT A.
10993 			 *   0 - Function 1 interrupt line wired to INT B.
10994 			 *
10995 			 * Note: Function 0 is always wired to INTA.
10996 			 * Put all 5 GPIO bits in input mode and then read
10997 			 * their input values.
10998 			 */
10999 			AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
11000 			ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
11001 			if ((ints & 0x01) == 0)
11002 				eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
11003 		}
11004 
11005 		/*
11006 		 * Assume the 6 byte board serial number that was read from
11007 		 * EEPROM is correct even if the EEPROM checksum failed.
11008 		 */
11009 		eep_config.serial_number_word3 =
11010 			AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
11011 		eep_config.serial_number_word2 =
11012 			AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
11013 		eep_config.serial_number_word1 =
11014 			AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
11015 
11016 		AdvSet38C1600EEPConfig(iop_base, &eep_config);
11017 	}
11018 
11019 	/*
11020 	 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
11021 	 * EEPROM configuration that was read.
11022 	 *
11023 	 * This is the mapping of EEPROM fields to Adv Library fields.
11024 	 */
11025 	asc_dvc->wdtr_able = eep_config.wdtr_able;
11026 	asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
11027 	asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
11028 	asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
11029 	asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
11030 	asc_dvc->ppr_able = 0;
11031 	asc_dvc->tagqng_able = eep_config.tagqng_able;
11032 	asc_dvc->cfg->disc_enable = eep_config.disc_enable;
11033 	asc_dvc->max_host_qng = eep_config.max_host_qng;
11034 	asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11035 	asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
11036 	asc_dvc->start_motor = eep_config.start_motor;
11037 	asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
11038 	asc_dvc->bios_ctrl = eep_config.bios_ctrl;
11039 	asc_dvc->no_scam = eep_config.scam_tolerant;
11040 
11041 	/*
11042 	 * For every Target ID if any of its 'sdtr_speed[1234]' bits
11043 	 * are set, then set an 'sdtr_able' bit for it.
11044 	 */
11045 	asc_dvc->sdtr_able = 0;
11046 	for (tid = 0; tid <= ASC_MAX_TID; tid++) {
11047 		if (tid == 0) {
11048 			sdtr_speed = asc_dvc->sdtr_speed1;
11049 		} else if (tid == 4) {
11050 			sdtr_speed = asc_dvc->sdtr_speed2;
11051 		} else if (tid == 8) {
11052 			sdtr_speed = asc_dvc->sdtr_speed3;
11053 		} else if (tid == 12) {
11054 			sdtr_speed = asc_dvc->sdtr_speed4;
11055 		}
11056 		if (sdtr_speed & ASC_MAX_TID) {
11057 			asc_dvc->sdtr_able |= (1 << tid);
11058 		}
11059 		sdtr_speed >>= 4;
11060 	}
11061 
11062 	/*
11063 	 * Set the host maximum queuing (max. 253, min. 16) and the per device
11064 	 * maximum queuing (max. 63, min. 4).
11065 	 */
11066 	if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
11067 		eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11068 	} else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
11069 		/* If the value is zero, assume it is uninitialized. */
11070 		if (eep_config.max_host_qng == 0) {
11071 			eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11072 		} else {
11073 			eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
11074 		}
11075 	}
11076 
11077 	if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
11078 		eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11079 	} else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
11080 		/* If the value is zero, assume it is uninitialized. */
11081 		if (eep_config.max_dvc_qng == 0) {
11082 			eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11083 		} else {
11084 			eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
11085 		}
11086 	}
11087 
11088 	/*
11089 	 * If 'max_dvc_qng' is greater than 'max_host_qng', then
11090 	 * set 'max_dvc_qng' to 'max_host_qng'.
11091 	 */
11092 	if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
11093 		eep_config.max_dvc_qng = eep_config.max_host_qng;
11094 	}
11095 
11096 	/*
11097 	 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
11098 	 * values based on possibly adjusted EEPROM values.
11099 	 */
11100 	asc_dvc->max_host_qng = eep_config.max_host_qng;
11101 	asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11102 
11103 	/*
11104 	 * If the EEPROM 'termination' field is set to automatic (0), then set
11105 	 * the ASC_DVC_CFG 'termination' field to automatic also.
11106 	 *
11107 	 * If the termination is specified with a non-zero 'termination'
11108 	 * value check that a legal value is set and set the ASC_DVC_CFG
11109 	 * 'termination' field appropriately.
11110 	 */
11111 	if (eep_config.termination_se == 0) {
11112 		termination = 0;	/* auto termination for SE */
11113 	} else {
11114 		/* Enable manual control with low off / high off. */
11115 		if (eep_config.termination_se == 1) {
11116 			termination = 0;
11117 
11118 			/* Enable manual control with low off / high on. */
11119 		} else if (eep_config.termination_se == 2) {
11120 			termination = TERM_SE_HI;
11121 
11122 			/* Enable manual control with low on / high on. */
11123 		} else if (eep_config.termination_se == 3) {
11124 			termination = TERM_SE;
11125 		} else {
11126 			/*
11127 			 * The EEPROM 'termination_se' field contains a bad value.
11128 			 * Use automatic termination instead.
11129 			 */
11130 			termination = 0;
11131 			warn_code |= ASC_WARN_EEPROM_TERMINATION;
11132 		}
11133 	}
11134 
11135 	if (eep_config.termination_lvd == 0) {
11136 		asc_dvc->cfg->termination = termination;	/* auto termination for LVD */
11137 	} else {
11138 		/* Enable manual control with low off / high off. */
11139 		if (eep_config.termination_lvd == 1) {
11140 			asc_dvc->cfg->termination = termination;
11141 
11142 			/* Enable manual control with low off / high on. */
11143 		} else if (eep_config.termination_lvd == 2) {
11144 			asc_dvc->cfg->termination = termination | TERM_LVD_HI;
11145 
11146 			/* Enable manual control with low on / high on. */
11147 		} else if (eep_config.termination_lvd == 3) {
11148 			asc_dvc->cfg->termination = termination | TERM_LVD;
11149 		} else {
11150 			/*
11151 			 * The EEPROM 'termination_lvd' field contains a bad value.
11152 			 * Use automatic termination instead.
11153 			 */
11154 			asc_dvc->cfg->termination = termination;
11155 			warn_code |= ASC_WARN_EEPROM_TERMINATION;
11156 		}
11157 	}
11158 
11159 	return warn_code;
11160 }
11161 
11162 /*
11163  * Initialize the ADV_DVC_VAR structure.
11164  *
11165  * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
11166  *
11167  * For a non-fatal error return a warning code. If there are no warnings
11168  * then 0 is returned.
11169  */
11170 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
11171 {
11172 	struct asc_board *board = shost_priv(shost);
11173 	ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
11174 	unsigned short warn_code = 0;
11175 	AdvPortAddr iop_base = asc_dvc->iop_base;
11176 	u16 cmd;
11177 	int status;
11178 
11179 	asc_dvc->err_code = 0;
11180 
11181 	/*
11182 	 * Save the state of the PCI Configuration Command Register
11183 	 * "Parity Error Response Control" Bit. If the bit is clear (0),
11184 	 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11185 	 * DMA parity errors.
11186 	 */
11187 	asc_dvc->cfg->control_flag = 0;
11188 	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11189 	if ((cmd & PCI_COMMAND_PARITY) == 0)
11190 		asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
11191 
11192 	asc_dvc->cfg->chip_version =
11193 	    AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11194 
11195 	ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
11196 		 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11197 		 (ushort)ADV_CHIP_ID_BYTE);
11198 
11199 	ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
11200 		 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11201 		 (ushort)ADV_CHIP_ID_WORD);
11202 
11203 	/*
11204 	 * Reset the chip to start and allow register writes.
11205 	 */
11206 	if (AdvFindSignature(iop_base) == 0) {
11207 		asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11208 		return ADV_ERROR;
11209 	} else {
11210 		/*
11211 		 * The caller must set 'chip_type' to a valid setting.
11212 		 */
11213 		if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11214 		    asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11215 		    asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11216 			asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11217 			return ADV_ERROR;
11218 		}
11219 
11220 		/*
11221 		 * Reset Chip.
11222 		 */
11223 		AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11224 				     ADV_CTRL_REG_CMD_RESET);
11225 		mdelay(100);
11226 		AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11227 				     ADV_CTRL_REG_CMD_WR_IO_REG);
11228 
11229 		if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11230 			status = AdvInitFrom38C1600EEP(asc_dvc);
11231 		} else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11232 			status = AdvInitFrom38C0800EEP(asc_dvc);
11233 		} else {
11234 			status = AdvInitFrom3550EEP(asc_dvc);
11235 		}
11236 		warn_code |= status;
11237 	}
11238 
11239 	if (warn_code != 0)
11240 		shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
11241 
11242 	if (asc_dvc->err_code)
11243 		shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11244 				asc_dvc->err_code);
11245 
11246 	return asc_dvc->err_code;
11247 }
11248 #endif
11249 
11250 static struct scsi_host_template advansys_template = {
11251 	.proc_name = DRV_NAME,
11252 #ifdef CONFIG_PROC_FS
11253 	.show_info = advansys_show_info,
11254 #endif
11255 	.name = DRV_NAME,
11256 	.info = advansys_info,
11257 	.queuecommand = advansys_queuecommand,
11258 	.eh_bus_reset_handler = advansys_reset,
11259 	.bios_param = advansys_biosparam,
11260 	.slave_configure = advansys_slave_configure,
11261 	/*
11262 	 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11263 	 * must be set. The flag will be cleared in advansys_board_found
11264 	 * for non-ISA adapters.
11265 	 */
11266 	.unchecked_isa_dma = 1,
11267 	/*
11268 	 * All adapters controlled by this driver are capable of large
11269 	 * scatter-gather lists. According to the mid-level SCSI documentation
11270 	 * this obviates any performance gain provided by setting
11271 	 * 'use_clustering'. But empirically while CPU utilization is increased
11272 	 * by enabling clustering, I/O throughput increases as well.
11273 	 */
11274 	.use_clustering = ENABLE_CLUSTERING,
11275 };
11276 
11277 static int advansys_wide_init_chip(struct Scsi_Host *shost)
11278 {
11279 	struct asc_board *board = shost_priv(shost);
11280 	struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11281 	int req_cnt = 0;
11282 	adv_req_t *reqp = NULL;
11283 	int sg_cnt = 0;
11284 	adv_sgblk_t *sgp;
11285 	int warn_code, err_code;
11286 
11287 	/*
11288 	 * Allocate buffer carrier structures. The total size
11289 	 * is about 4 KB, so allocate all at once.
11290 	 */
11291 	adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
11292 	ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf);
11293 
11294 	if (!adv_dvc->carrier_buf)
11295 		goto kmalloc_failed;
11296 
11297 	/*
11298 	 * Allocate up to 'max_host_qng' request structures for the Wide
11299 	 * board. The total size is about 16 KB, so allocate all at once.
11300 	 * If the allocation fails decrement and try again.
11301 	 */
11302 	for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
11303 		reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
11304 
11305 		ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
11306 			 (ulong)sizeof(adv_req_t) * req_cnt);
11307 
11308 		if (reqp)
11309 			break;
11310 	}
11311 
11312 	if (!reqp)
11313 		goto kmalloc_failed;
11314 
11315 	adv_dvc->orig_reqp = reqp;
11316 
11317 	/*
11318 	 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11319 	 * the Wide board. Each structure is about 136 bytes.
11320 	 */
11321 	board->adv_sgblkp = NULL;
11322 	for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
11323 		sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
11324 
11325 		if (!sgp)
11326 			break;
11327 
11328 		sgp->next_sgblkp = board->adv_sgblkp;
11329 		board->adv_sgblkp = sgp;
11330 
11331 	}
11332 
11333 	ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", sg_cnt, sizeof(adv_sgblk_t),
11334 		 sizeof(adv_sgblk_t) * sg_cnt);
11335 
11336 	if (!board->adv_sgblkp)
11337 		goto kmalloc_failed;
11338 
11339 	/*
11340 	 * Point 'adv_reqp' to the request structures and
11341 	 * link them together.
11342 	 */
11343 	req_cnt--;
11344 	reqp[req_cnt].next_reqp = NULL;
11345 	for (; req_cnt > 0; req_cnt--) {
11346 		reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
11347 	}
11348 	board->adv_reqp = &reqp[0];
11349 
11350 	if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
11351 		ASC_DBG(2, "AdvInitAsc3550Driver()\n");
11352 		warn_code = AdvInitAsc3550Driver(adv_dvc);
11353 	} else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11354 		ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
11355 		warn_code = AdvInitAsc38C0800Driver(adv_dvc);
11356 	} else {
11357 		ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
11358 		warn_code = AdvInitAsc38C1600Driver(adv_dvc);
11359 	}
11360 	err_code = adv_dvc->err_code;
11361 
11362 	if (warn_code || err_code) {
11363 		shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11364 			"0x%x\n", warn_code, err_code);
11365 	}
11366 
11367 	goto exit;
11368 
11369  kmalloc_failed:
11370 	shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
11371 	err_code = ADV_ERROR;
11372  exit:
11373 	return err_code;
11374 }
11375 
11376 static void advansys_wide_free_mem(struct asc_board *board)
11377 {
11378 	struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11379 	kfree(adv_dvc->carrier_buf);
11380 	adv_dvc->carrier_buf = NULL;
11381 	kfree(adv_dvc->orig_reqp);
11382 	adv_dvc->orig_reqp = board->adv_reqp = NULL;
11383 	while (board->adv_sgblkp) {
11384 		adv_sgblk_t *sgp = board->adv_sgblkp;
11385 		board->adv_sgblkp = sgp->next_sgblkp;
11386 		kfree(sgp);
11387 	}
11388 }
11389 
11390 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11391 				int bus_type)
11392 {
11393 	struct pci_dev *pdev;
11394 	struct asc_board *boardp = shost_priv(shost);
11395 	ASC_DVC_VAR *asc_dvc_varp = NULL;
11396 	ADV_DVC_VAR *adv_dvc_varp = NULL;
11397 	int share_irq, warn_code, ret;
11398 
11399 	pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
11400 
11401 	if (ASC_NARROW_BOARD(boardp)) {
11402 		ASC_DBG(1, "narrow board\n");
11403 		asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11404 		asc_dvc_varp->bus_type = bus_type;
11405 		asc_dvc_varp->drv_ptr = boardp;
11406 		asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
11407 		asc_dvc_varp->iop_base = iop;
11408 	} else {
11409 #ifdef CONFIG_PCI
11410 		adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11411 		adv_dvc_varp->drv_ptr = boardp;
11412 		adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
11413 		if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
11414 			ASC_DBG(1, "wide board ASC-3550\n");
11415 			adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11416 		} else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
11417 			ASC_DBG(1, "wide board ASC-38C0800\n");
11418 			adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11419 		} else {
11420 			ASC_DBG(1, "wide board ASC-38C1600\n");
11421 			adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11422 		}
11423 
11424 		boardp->asc_n_io_port = pci_resource_len(pdev, 1);
11425 		boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
11426 		if (!boardp->ioremap_addr) {
11427 			shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
11428 					"returned NULL\n",
11429 					(long)pci_resource_start(pdev, 1),
11430 					boardp->asc_n_io_port);
11431 			ret = -ENODEV;
11432 			goto err_shost;
11433 		}
11434 		adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11435 		ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
11436 
11437 		/*
11438 		 * Even though it isn't used to access wide boards, other
11439 		 * than for the debug line below, save I/O Port address so
11440 		 * that it can be reported.
11441 		 */
11442 		boardp->ioport = iop;
11443 
11444 		ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11445 				(ushort)inp(iop + 1), (ushort)inpw(iop));
11446 #endif /* CONFIG_PCI */
11447 	}
11448 
11449 	if (ASC_NARROW_BOARD(boardp)) {
11450 		/*
11451 		 * Set the board bus type and PCI IRQ before
11452 		 * calling AscInitGetConfig().
11453 		 */
11454 		switch (asc_dvc_varp->bus_type) {
11455 #ifdef CONFIG_ISA
11456 		case ASC_IS_ISA:
11457 			shost->unchecked_isa_dma = TRUE;
11458 			share_irq = 0;
11459 			break;
11460 		case ASC_IS_VL:
11461 			shost->unchecked_isa_dma = FALSE;
11462 			share_irq = 0;
11463 			break;
11464 		case ASC_IS_EISA:
11465 			shost->unchecked_isa_dma = FALSE;
11466 			share_irq = IRQF_SHARED;
11467 			break;
11468 #endif /* CONFIG_ISA */
11469 #ifdef CONFIG_PCI
11470 		case ASC_IS_PCI:
11471 			shost->unchecked_isa_dma = FALSE;
11472 			share_irq = IRQF_SHARED;
11473 			break;
11474 #endif /* CONFIG_PCI */
11475 		default:
11476 			shost_printk(KERN_ERR, shost, "unknown adapter type: "
11477 					"%d\n", asc_dvc_varp->bus_type);
11478 			shost->unchecked_isa_dma = TRUE;
11479 			share_irq = 0;
11480 			break;
11481 		}
11482 
11483 		/*
11484 		 * NOTE: AscInitGetConfig() may change the board's
11485 		 * bus_type value. The bus_type value should no
11486 		 * longer be used. If the bus_type field must be
11487 		 * referenced only use the bit-wise AND operator "&".
11488 		 */
11489 		ASC_DBG(2, "AscInitGetConfig()\n");
11490 		ret = AscInitGetConfig(shost) ? -ENODEV : 0;
11491 	} else {
11492 #ifdef CONFIG_PCI
11493 		/*
11494 		 * For Wide boards set PCI information before calling
11495 		 * AdvInitGetConfig().
11496 		 */
11497 		shost->unchecked_isa_dma = FALSE;
11498 		share_irq = IRQF_SHARED;
11499 		ASC_DBG(2, "AdvInitGetConfig()\n");
11500 
11501 		ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
11502 #endif /* CONFIG_PCI */
11503 	}
11504 
11505 	if (ret)
11506 		goto err_unmap;
11507 
11508 	/*
11509 	 * Save the EEPROM configuration so that it can be displayed
11510 	 * from /proc/scsi/advansys/[0...].
11511 	 */
11512 	if (ASC_NARROW_BOARD(boardp)) {
11513 
11514 		ASCEEP_CONFIG *ep;
11515 
11516 		/*
11517 		 * Set the adapter's target id bit in the 'init_tidmask' field.
11518 		 */
11519 		boardp->init_tidmask |=
11520 		    ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11521 
11522 		/*
11523 		 * Save EEPROM settings for the board.
11524 		 */
11525 		ep = &boardp->eep_config.asc_eep;
11526 
11527 		ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11528 		ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11529 		ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11530 		ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11531 		ep->start_motor = asc_dvc_varp->start_motor;
11532 		ep->cntl = asc_dvc_varp->dvc_cntl;
11533 		ep->no_scam = asc_dvc_varp->no_scam;
11534 		ep->max_total_qng = asc_dvc_varp->max_total_qng;
11535 		ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11536 		/* 'max_tag_qng' is set to the same value for every device. */
11537 		ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11538 		ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11539 		ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11540 		ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11541 		ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11542 		ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11543 		ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11544 
11545 		/*
11546 		 * Modify board configuration.
11547 		 */
11548 		ASC_DBG(2, "AscInitSetConfig()\n");
11549 		ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
11550 		if (ret)
11551 			goto err_unmap;
11552 	} else {
11553 		ADVEEP_3550_CONFIG *ep_3550;
11554 		ADVEEP_38C0800_CONFIG *ep_38C0800;
11555 		ADVEEP_38C1600_CONFIG *ep_38C1600;
11556 
11557 		/*
11558 		 * Save Wide EEP Configuration Information.
11559 		 */
11560 		if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11561 			ep_3550 = &boardp->eep_config.adv_3550_eep;
11562 
11563 			ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11564 			ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11565 			ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11566 			ep_3550->termination = adv_dvc_varp->cfg->termination;
11567 			ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11568 			ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11569 			ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11570 			ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11571 			ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11572 			ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11573 			ep_3550->start_motor = adv_dvc_varp->start_motor;
11574 			ep_3550->scsi_reset_delay =
11575 			    adv_dvc_varp->scsi_reset_wait;
11576 			ep_3550->serial_number_word1 =
11577 			    adv_dvc_varp->cfg->serial1;
11578 			ep_3550->serial_number_word2 =
11579 			    adv_dvc_varp->cfg->serial2;
11580 			ep_3550->serial_number_word3 =
11581 			    adv_dvc_varp->cfg->serial3;
11582 		} else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11583 			ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11584 
11585 			ep_38C0800->adapter_scsi_id =
11586 			    adv_dvc_varp->chip_scsi_id;
11587 			ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11588 			ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11589 			ep_38C0800->termination_lvd =
11590 			    adv_dvc_varp->cfg->termination;
11591 			ep_38C0800->disc_enable =
11592 			    adv_dvc_varp->cfg->disc_enable;
11593 			ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11594 			ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11595 			ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11596 			ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11597 			ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11598 			ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11599 			ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11600 			ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11601 			ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11602 			ep_38C0800->scsi_reset_delay =
11603 			    adv_dvc_varp->scsi_reset_wait;
11604 			ep_38C0800->serial_number_word1 =
11605 			    adv_dvc_varp->cfg->serial1;
11606 			ep_38C0800->serial_number_word2 =
11607 			    adv_dvc_varp->cfg->serial2;
11608 			ep_38C0800->serial_number_word3 =
11609 			    adv_dvc_varp->cfg->serial3;
11610 		} else {
11611 			ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11612 
11613 			ep_38C1600->adapter_scsi_id =
11614 			    adv_dvc_varp->chip_scsi_id;
11615 			ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11616 			ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11617 			ep_38C1600->termination_lvd =
11618 			    adv_dvc_varp->cfg->termination;
11619 			ep_38C1600->disc_enable =
11620 			    adv_dvc_varp->cfg->disc_enable;
11621 			ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11622 			ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11623 			ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11624 			ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11625 			ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11626 			ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11627 			ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11628 			ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11629 			ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11630 			ep_38C1600->scsi_reset_delay =
11631 			    adv_dvc_varp->scsi_reset_wait;
11632 			ep_38C1600->serial_number_word1 =
11633 			    adv_dvc_varp->cfg->serial1;
11634 			ep_38C1600->serial_number_word2 =
11635 			    adv_dvc_varp->cfg->serial2;
11636 			ep_38C1600->serial_number_word3 =
11637 			    adv_dvc_varp->cfg->serial3;
11638 		}
11639 
11640 		/*
11641 		 * Set the adapter's target id bit in the 'init_tidmask' field.
11642 		 */
11643 		boardp->init_tidmask |=
11644 		    ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
11645 	}
11646 
11647 	/*
11648 	 * Channels are numbered beginning with 0. For AdvanSys one host
11649 	 * structure supports one channel. Multi-channel boards have a
11650 	 * separate host structure for each channel.
11651 	 */
11652 	shost->max_channel = 0;
11653 	if (ASC_NARROW_BOARD(boardp)) {
11654 		shost->max_id = ASC_MAX_TID + 1;
11655 		shost->max_lun = ASC_MAX_LUN + 1;
11656 		shost->max_cmd_len = ASC_MAX_CDB_LEN;
11657 
11658 		shost->io_port = asc_dvc_varp->iop_base;
11659 		boardp->asc_n_io_port = ASC_IOADR_GAP;
11660 		shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11661 
11662 		/* Set maximum number of queues the adapter can handle. */
11663 		shost->can_queue = asc_dvc_varp->max_total_qng;
11664 	} else {
11665 		shost->max_id = ADV_MAX_TID + 1;
11666 		shost->max_lun = ADV_MAX_LUN + 1;
11667 		shost->max_cmd_len = ADV_MAX_CDB_LEN;
11668 
11669 		/*
11670 		 * Save the I/O Port address and length even though
11671 		 * I/O ports are not used to access Wide boards.
11672 		 * Instead the Wide boards are accessed with
11673 		 * PCI Memory Mapped I/O.
11674 		 */
11675 		shost->io_port = iop;
11676 
11677 		shost->this_id = adv_dvc_varp->chip_scsi_id;
11678 
11679 		/* Set maximum number of queues the adapter can handle. */
11680 		shost->can_queue = adv_dvc_varp->max_host_qng;
11681 	}
11682 
11683 	/*
11684 	 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11685 	 * and should be set to zero.
11686 	 *
11687 	 * But because of a bug introduced in v1.3.89 if the driver is
11688 	 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11689 	 * SCSI function 'allocate_device' will panic. To allow the driver
11690 	 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11691 	 *
11692 	 * Note: This is wrong.  cmd_per_lun should be set to the depth
11693 	 * you want on untagged devices always.
11694 	 #ifdef MODULE
11695 	 */
11696 	shost->cmd_per_lun = 1;
11697 /* #else
11698             shost->cmd_per_lun = 0;
11699 #endif */
11700 
11701 	/*
11702 	 * Set the maximum number of scatter-gather elements the
11703 	 * adapter can handle.
11704 	 */
11705 	if (ASC_NARROW_BOARD(boardp)) {
11706 		/*
11707 		 * Allow two commands with 'sg_tablesize' scatter-gather
11708 		 * elements to be executed simultaneously. This value is
11709 		 * the theoretical hardware limit. It may be decreased
11710 		 * below.
11711 		 */
11712 		shost->sg_tablesize =
11713 		    (((asc_dvc_varp->max_total_qng - 2) / 2) *
11714 		     ASC_SG_LIST_PER_Q) + 1;
11715 	} else {
11716 		shost->sg_tablesize = ADV_MAX_SG_LIST;
11717 	}
11718 
11719 	/*
11720 	 * The value of 'sg_tablesize' can not exceed the SCSI
11721 	 * mid-level driver definition of SG_ALL. SG_ALL also
11722 	 * must not be exceeded, because it is used to define the
11723 	 * size of the scatter-gather table in 'struct asc_sg_head'.
11724 	 */
11725 	if (shost->sg_tablesize > SG_ALL) {
11726 		shost->sg_tablesize = SG_ALL;
11727 	}
11728 
11729 	ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
11730 
11731 	/* BIOS start address. */
11732 	if (ASC_NARROW_BOARD(boardp)) {
11733 		shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11734 						    asc_dvc_varp->bus_type);
11735 	} else {
11736 		/*
11737 		 * Fill-in BIOS board variables. The Wide BIOS saves
11738 		 * information in LRAM that is used by the driver.
11739 		 */
11740 		AdvReadWordLram(adv_dvc_varp->iop_base,
11741 				BIOS_SIGNATURE, boardp->bios_signature);
11742 		AdvReadWordLram(adv_dvc_varp->iop_base,
11743 				BIOS_VERSION, boardp->bios_version);
11744 		AdvReadWordLram(adv_dvc_varp->iop_base,
11745 				BIOS_CODESEG, boardp->bios_codeseg);
11746 		AdvReadWordLram(adv_dvc_varp->iop_base,
11747 				BIOS_CODELEN, boardp->bios_codelen);
11748 
11749 		ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
11750 			 boardp->bios_signature, boardp->bios_version);
11751 
11752 		ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
11753 			 boardp->bios_codeseg, boardp->bios_codelen);
11754 
11755 		/*
11756 		 * If the BIOS saved a valid signature, then fill in
11757 		 * the BIOS code segment base address.
11758 		 */
11759 		if (boardp->bios_signature == 0x55AA) {
11760 			/*
11761 			 * Convert x86 realmode code segment to a linear
11762 			 * address by shifting left 4.
11763 			 */
11764 			shost->base = ((ulong)boardp->bios_codeseg << 4);
11765 		} else {
11766 			shost->base = 0;
11767 		}
11768 	}
11769 
11770 	/*
11771 	 * Register Board Resources - I/O Port, DMA, IRQ
11772 	 */
11773 
11774 	/* Register DMA Channel for Narrow boards. */
11775 	shost->dma_channel = NO_ISA_DMA;	/* Default to no ISA DMA. */
11776 #ifdef CONFIG_ISA
11777 	if (ASC_NARROW_BOARD(boardp)) {
11778 		/* Register DMA channel for ISA bus. */
11779 		if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11780 			shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
11781 			ret = request_dma(shost->dma_channel, DRV_NAME);
11782 			if (ret) {
11783 				shost_printk(KERN_ERR, shost, "request_dma() "
11784 						"%d failed %d\n",
11785 						shost->dma_channel, ret);
11786 				goto err_unmap;
11787 			}
11788 			AscEnableIsaDma(shost->dma_channel);
11789 		}
11790 	}
11791 #endif /* CONFIG_ISA */
11792 
11793 	/* Register IRQ Number. */
11794 	ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
11795 
11796 	ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
11797 			  DRV_NAME, shost);
11798 
11799 	if (ret) {
11800 		if (ret == -EBUSY) {
11801 			shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11802 					"already in use\n", boardp->irq);
11803 		} else if (ret == -EINVAL) {
11804 			shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11805 					"not valid\n", boardp->irq);
11806 		} else {
11807 			shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11808 					"failed with %d\n", boardp->irq, ret);
11809 		}
11810 		goto err_free_dma;
11811 	}
11812 
11813 	/*
11814 	 * Initialize board RISC chip and enable interrupts.
11815 	 */
11816 	if (ASC_NARROW_BOARD(boardp)) {
11817 		ASC_DBG(2, "AscInitAsc1000Driver()\n");
11818 
11819 		asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11820 		if (!asc_dvc_varp->overrun_buf) {
11821 			ret = -ENOMEM;
11822 			goto err_free_irq;
11823 		}
11824 		warn_code = AscInitAsc1000Driver(asc_dvc_varp);
11825 
11826 		if (warn_code || asc_dvc_varp->err_code) {
11827 			shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11828 					"warn 0x%x, error 0x%x\n",
11829 					asc_dvc_varp->init_state, warn_code,
11830 					asc_dvc_varp->err_code);
11831 			if (!asc_dvc_varp->overrun_dma) {
11832 				ret = -ENODEV;
11833 				goto err_free_mem;
11834 			}
11835 		}
11836 	} else {
11837 		if (advansys_wide_init_chip(shost)) {
11838 			ret = -ENODEV;
11839 			goto err_free_mem;
11840 		}
11841 	}
11842 
11843 	ASC_DBG_PRT_SCSI_HOST(2, shost);
11844 
11845 	ret = scsi_add_host(shost, boardp->dev);
11846 	if (ret)
11847 		goto err_free_mem;
11848 
11849 	scsi_scan_host(shost);
11850 	return 0;
11851 
11852  err_free_mem:
11853 	if (ASC_NARROW_BOARD(boardp)) {
11854 		if (asc_dvc_varp->overrun_dma)
11855 			dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11856 					 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11857 		kfree(asc_dvc_varp->overrun_buf);
11858 	} else
11859 		advansys_wide_free_mem(boardp);
11860  err_free_irq:
11861 	free_irq(boardp->irq, shost);
11862  err_free_dma:
11863 #ifdef CONFIG_ISA
11864 	if (shost->dma_channel != NO_ISA_DMA)
11865 		free_dma(shost->dma_channel);
11866 #endif
11867  err_unmap:
11868 	if (boardp->ioremap_addr)
11869 		iounmap(boardp->ioremap_addr);
11870  err_shost:
11871 	return ret;
11872 }
11873 
11874 /*
11875  * advansys_release()
11876  *
11877  * Release resources allocated for a single AdvanSys adapter.
11878  */
11879 static int advansys_release(struct Scsi_Host *shost)
11880 {
11881 	struct asc_board *board = shost_priv(shost);
11882 	ASC_DBG(1, "begin\n");
11883 	scsi_remove_host(shost);
11884 	free_irq(board->irq, shost);
11885 #ifdef CONFIG_ISA
11886 	if (shost->dma_channel != NO_ISA_DMA) {
11887 		ASC_DBG(1, "free_dma()\n");
11888 		free_dma(shost->dma_channel);
11889 	}
11890 #endif
11891 	if (ASC_NARROW_BOARD(board)) {
11892 		dma_unmap_single(board->dev,
11893 					board->dvc_var.asc_dvc_var.overrun_dma,
11894 					ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11895 		kfree(board->dvc_var.asc_dvc_var.overrun_buf);
11896 	} else {
11897 		iounmap(board->ioremap_addr);
11898 		advansys_wide_free_mem(board);
11899 	}
11900 	scsi_host_put(shost);
11901 	ASC_DBG(1, "end\n");
11902 	return 0;
11903 }
11904 
11905 #define ASC_IOADR_TABLE_MAX_IX  11
11906 
11907 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
11908 	0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11909 	0x0210, 0x0230, 0x0250, 0x0330
11910 };
11911 
11912 /*
11913  * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw.  It decodes as:
11914  * 00: 10
11915  * 01: 11
11916  * 10: 12
11917  * 11: 15
11918  */
11919 static unsigned int advansys_isa_irq_no(PortAddr iop_base)
11920 {
11921 	unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11922 	unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11923 	if (chip_irq == 13)
11924 		chip_irq = 15;
11925 	return chip_irq;
11926 }
11927 
11928 static int advansys_isa_probe(struct device *dev, unsigned int id)
11929 {
11930 	int err = -ENODEV;
11931 	PortAddr iop_base = _asc_def_iop_base[id];
11932 	struct Scsi_Host *shost;
11933 	struct asc_board *board;
11934 
11935 	if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
11936 		ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
11937 		return -ENODEV;
11938 	}
11939 	ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
11940 	if (!AscFindSignature(iop_base))
11941 		goto release_region;
11942 	if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
11943 		goto release_region;
11944 
11945 	err = -ENOMEM;
11946 	shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11947 	if (!shost)
11948 		goto release_region;
11949 
11950 	board = shost_priv(shost);
11951 	board->irq = advansys_isa_irq_no(iop_base);
11952 	board->dev = dev;
11953 
11954 	err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11955 	if (err)
11956 		goto free_host;
11957 
11958 	dev_set_drvdata(dev, shost);
11959 	return 0;
11960 
11961  free_host:
11962 	scsi_host_put(shost);
11963  release_region:
11964 	release_region(iop_base, ASC_IOADR_GAP);
11965 	return err;
11966 }
11967 
11968 static int advansys_isa_remove(struct device *dev, unsigned int id)
11969 {
11970 	int ioport = _asc_def_iop_base[id];
11971 	advansys_release(dev_get_drvdata(dev));
11972 	release_region(ioport, ASC_IOADR_GAP);
11973 	return 0;
11974 }
11975 
11976 static struct isa_driver advansys_isa_driver = {
11977 	.probe		= advansys_isa_probe,
11978 	.remove		= advansys_isa_remove,
11979 	.driver = {
11980 		.owner	= THIS_MODULE,
11981 		.name	= DRV_NAME,
11982 	},
11983 };
11984 
11985 /*
11986  * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw.  It decodes as:
11987  * 000: invalid
11988  * 001: 10
11989  * 010: 11
11990  * 011: 12
11991  * 100: invalid
11992  * 101: 14
11993  * 110: 15
11994  * 111: invalid
11995  */
11996 static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
11997 {
11998 	unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11999 	unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
12000 	if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
12001 		return 0;
12002 	return chip_irq;
12003 }
12004 
12005 static int advansys_vlb_probe(struct device *dev, unsigned int id)
12006 {
12007 	int err = -ENODEV;
12008 	PortAddr iop_base = _asc_def_iop_base[id];
12009 	struct Scsi_Host *shost;
12010 	struct asc_board *board;
12011 
12012 	if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
12013 		ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
12014 		return -ENODEV;
12015 	}
12016 	ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
12017 	if (!AscFindSignature(iop_base))
12018 		goto release_region;
12019 	/*
12020 	 * I don't think this condition can actually happen, but the old
12021 	 * driver did it, and the chances of finding a VLB setup in 2007
12022 	 * to do testing with is slight to none.
12023 	 */
12024 	if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
12025 		goto release_region;
12026 
12027 	err = -ENOMEM;
12028 	shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12029 	if (!shost)
12030 		goto release_region;
12031 
12032 	board = shost_priv(shost);
12033 	board->irq = advansys_vlb_irq_no(iop_base);
12034 	board->dev = dev;
12035 
12036 	err = advansys_board_found(shost, iop_base, ASC_IS_VL);
12037 	if (err)
12038 		goto free_host;
12039 
12040 	dev_set_drvdata(dev, shost);
12041 	return 0;
12042 
12043  free_host:
12044 	scsi_host_put(shost);
12045  release_region:
12046 	release_region(iop_base, ASC_IOADR_GAP);
12047 	return -ENODEV;
12048 }
12049 
12050 static struct isa_driver advansys_vlb_driver = {
12051 	.probe		= advansys_vlb_probe,
12052 	.remove		= advansys_isa_remove,
12053 	.driver = {
12054 		.owner	= THIS_MODULE,
12055 		.name	= "advansys_vlb",
12056 	},
12057 };
12058 
12059 static struct eisa_device_id advansys_eisa_table[] = {
12060 	{ "ABP7401" },
12061 	{ "ABP7501" },
12062 	{ "" }
12063 };
12064 
12065 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
12066 
12067 /*
12068  * EISA is a little more tricky than PCI; each EISA device may have two
12069  * channels, and this driver is written to make each channel its own Scsi_Host
12070  */
12071 struct eisa_scsi_data {
12072 	struct Scsi_Host *host[2];
12073 };
12074 
12075 /*
12076  * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw.  It decodes as:
12077  * 000: 10
12078  * 001: 11
12079  * 010: 12
12080  * 011: invalid
12081  * 100: 14
12082  * 101: 15
12083  * 110: invalid
12084  * 111: invalid
12085  */
12086 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
12087 {
12088 	unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
12089 	unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
12090 	if ((chip_irq == 13) || (chip_irq > 15))
12091 		return 0;
12092 	return chip_irq;
12093 }
12094 
12095 static int advansys_eisa_probe(struct device *dev)
12096 {
12097 	int i, ioport, irq = 0;
12098 	int err;
12099 	struct eisa_device *edev = to_eisa_device(dev);
12100 	struct eisa_scsi_data *data;
12101 
12102 	err = -ENOMEM;
12103 	data = kzalloc(sizeof(*data), GFP_KERNEL);
12104 	if (!data)
12105 		goto fail;
12106 	ioport = edev->base_addr + 0xc30;
12107 
12108 	err = -ENODEV;
12109 	for (i = 0; i < 2; i++, ioport += 0x20) {
12110 		struct asc_board *board;
12111 		struct Scsi_Host *shost;
12112 		if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
12113 			printk(KERN_WARNING "Region %x-%x busy\n", ioport,
12114 			       ioport + ASC_IOADR_GAP - 1);
12115 			continue;
12116 		}
12117 		if (!AscFindSignature(ioport)) {
12118 			release_region(ioport, ASC_IOADR_GAP);
12119 			continue;
12120 		}
12121 
12122 		/*
12123 		 * I don't know why we need to do this for EISA chips, but
12124 		 * not for any others.  It looks to be equivalent to
12125 		 * AscGetChipCfgMsw, but I may have overlooked something,
12126 		 * so I'm not converting it until I get an EISA board to
12127 		 * test with.
12128 		 */
12129 		inw(ioport + 4);
12130 
12131 		if (!irq)
12132 			irq = advansys_eisa_irq_no(edev);
12133 
12134 		err = -ENOMEM;
12135 		shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12136 		if (!shost)
12137 			goto release_region;
12138 
12139 		board = shost_priv(shost);
12140 		board->irq = irq;
12141 		board->dev = dev;
12142 
12143 		err = advansys_board_found(shost, ioport, ASC_IS_EISA);
12144 		if (!err) {
12145 			data->host[i] = shost;
12146 			continue;
12147 		}
12148 
12149 		scsi_host_put(shost);
12150  release_region:
12151 		release_region(ioport, ASC_IOADR_GAP);
12152 		break;
12153 	}
12154 
12155 	if (err)
12156 		goto free_data;
12157 	dev_set_drvdata(dev, data);
12158 	return 0;
12159 
12160  free_data:
12161 	kfree(data->host[0]);
12162 	kfree(data->host[1]);
12163 	kfree(data);
12164  fail:
12165 	return err;
12166 }
12167 
12168 static int advansys_eisa_remove(struct device *dev)
12169 {
12170 	int i;
12171 	struct eisa_scsi_data *data = dev_get_drvdata(dev);
12172 
12173 	for (i = 0; i < 2; i++) {
12174 		int ioport;
12175 		struct Scsi_Host *shost = data->host[i];
12176 		if (!shost)
12177 			continue;
12178 		ioport = shost->io_port;
12179 		advansys_release(shost);
12180 		release_region(ioport, ASC_IOADR_GAP);
12181 	}
12182 
12183 	kfree(data);
12184 	return 0;
12185 }
12186 
12187 static struct eisa_driver advansys_eisa_driver = {
12188 	.id_table =		advansys_eisa_table,
12189 	.driver = {
12190 		.name =		DRV_NAME,
12191 		.probe =	advansys_eisa_probe,
12192 		.remove =	advansys_eisa_remove,
12193 	}
12194 };
12195 
12196 /* PCI Devices supported by this driver */
12197 static struct pci_device_id advansys_pci_tbl[] = {
12198 	{PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12199 	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12200 	{PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12201 	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12202 	{PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12203 	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12204 	{PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12205 	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12206 	{PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12207 	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12208 	{PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12209 	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12210 	{}
12211 };
12212 
12213 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
12214 
12215 static void advansys_set_latency(struct pci_dev *pdev)
12216 {
12217 	if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12218 	    (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12219 		pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12220 	} else {
12221 		u8 latency;
12222 		pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12223 		if (latency < 0x20)
12224 			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12225 	}
12226 }
12227 
12228 static int advansys_pci_probe(struct pci_dev *pdev,
12229 			      const struct pci_device_id *ent)
12230 {
12231 	int err, ioport;
12232 	struct Scsi_Host *shost;
12233 	struct asc_board *board;
12234 
12235 	err = pci_enable_device(pdev);
12236 	if (err)
12237 		goto fail;
12238 	err = pci_request_regions(pdev, DRV_NAME);
12239 	if (err)
12240 		goto disable_device;
12241 	pci_set_master(pdev);
12242 	advansys_set_latency(pdev);
12243 
12244 	err = -ENODEV;
12245 	if (pci_resource_len(pdev, 0) == 0)
12246 		goto release_region;
12247 
12248 	ioport = pci_resource_start(pdev, 0);
12249 
12250 	err = -ENOMEM;
12251 	shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12252 	if (!shost)
12253 		goto release_region;
12254 
12255 	board = shost_priv(shost);
12256 	board->irq = pdev->irq;
12257 	board->dev = &pdev->dev;
12258 
12259 	if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12260 	    pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12261 	    pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12262 		board->flags |= ASC_IS_WIDE_BOARD;
12263 	}
12264 
12265 	err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12266 	if (err)
12267 		goto free_host;
12268 
12269 	pci_set_drvdata(pdev, shost);
12270 	return 0;
12271 
12272  free_host:
12273 	scsi_host_put(shost);
12274  release_region:
12275 	pci_release_regions(pdev);
12276  disable_device:
12277 	pci_disable_device(pdev);
12278  fail:
12279 	return err;
12280 }
12281 
12282 static void advansys_pci_remove(struct pci_dev *pdev)
12283 {
12284 	advansys_release(pci_get_drvdata(pdev));
12285 	pci_release_regions(pdev);
12286 	pci_disable_device(pdev);
12287 }
12288 
12289 static struct pci_driver advansys_pci_driver = {
12290 	.name =		DRV_NAME,
12291 	.id_table =	advansys_pci_tbl,
12292 	.probe =	advansys_pci_probe,
12293 	.remove =	advansys_pci_remove,
12294 };
12295 
12296 static int __init advansys_init(void)
12297 {
12298 	int error;
12299 
12300 	error = isa_register_driver(&advansys_isa_driver,
12301 				    ASC_IOADR_TABLE_MAX_IX);
12302 	if (error)
12303 		goto fail;
12304 
12305 	error = isa_register_driver(&advansys_vlb_driver,
12306 				    ASC_IOADR_TABLE_MAX_IX);
12307 	if (error)
12308 		goto unregister_isa;
12309 
12310 	error = eisa_driver_register(&advansys_eisa_driver);
12311 	if (error)
12312 		goto unregister_vlb;
12313 
12314 	error = pci_register_driver(&advansys_pci_driver);
12315 	if (error)
12316 		goto unregister_eisa;
12317 
12318 	return 0;
12319 
12320  unregister_eisa:
12321 	eisa_driver_unregister(&advansys_eisa_driver);
12322  unregister_vlb:
12323 	isa_unregister_driver(&advansys_vlb_driver);
12324  unregister_isa:
12325 	isa_unregister_driver(&advansys_isa_driver);
12326  fail:
12327 	return error;
12328 }
12329 
12330 static void __exit advansys_exit(void)
12331 {
12332 	pci_unregister_driver(&advansys_pci_driver);
12333 	eisa_driver_unregister(&advansys_eisa_driver);
12334 	isa_unregister_driver(&advansys_vlb_driver);
12335 	isa_unregister_driver(&advansys_isa_driver);
12336 }
12337 
12338 module_init(advansys_init);
12339 module_exit(advansys_exit);
12340 
12341 MODULE_LICENSE("GPL");
12342 MODULE_FIRMWARE("advansys/mcode.bin");
12343 MODULE_FIRMWARE("advansys/3550.bin");
12344 MODULE_FIRMWARE("advansys/38C0800.bin");
12345 MODULE_FIRMWARE("advansys/38C1600.bin");
12346