1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 4 * 5 * Copyright (c) 1995-2000 Advanced System Products, Inc. 6 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc. 7 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx> 8 * Copyright (c) 2014 Hannes Reinecke <hare@suse.de> 9 * All Rights Reserved. 10 */ 11 12 /* 13 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys) 14 * changed its name to ConnectCom Solutions, Inc. 15 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets 16 */ 17 18 #include <linux/module.h> 19 #include <linux/string.h> 20 #include <linux/kernel.h> 21 #include <linux/types.h> 22 #include <linux/ioport.h> 23 #include <linux/interrupt.h> 24 #include <linux/delay.h> 25 #include <linux/slab.h> 26 #include <linux/mm.h> 27 #include <linux/proc_fs.h> 28 #include <linux/init.h> 29 #include <linux/blkdev.h> 30 #include <linux/isa.h> 31 #include <linux/eisa.h> 32 #include <linux/pci.h> 33 #include <linux/spinlock.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/firmware.h> 36 #include <linux/dmapool.h> 37 38 #include <asm/io.h> 39 #include <asm/dma.h> 40 41 #include <scsi/scsi_cmnd.h> 42 #include <scsi/scsi_device.h> 43 #include <scsi/scsi_tcq.h> 44 #include <scsi/scsi.h> 45 #include <scsi/scsi_host.h> 46 47 #define DRV_NAME "advansys" 48 #define ASC_VERSION "3.5" /* AdvanSys Driver Version */ 49 50 /* FIXME: 51 * 52 * 1. Use scsi_transport_spi 53 * 2. advansys_info is not safe against multiple simultaneous callers 54 * 3. Add module_param to override ISA/VLB ioport array 55 */ 56 57 /* Enable driver /proc statistics. */ 58 #define ADVANSYS_STATS 59 60 /* Enable driver tracing. */ 61 #undef ADVANSYS_DEBUG 62 63 typedef unsigned char uchar; 64 65 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0) 66 67 #define PCI_VENDOR_ID_ASP 0x10cd 68 #define PCI_DEVICE_ID_ASP_1200A 0x1100 69 #define PCI_DEVICE_ID_ASP_ABP940 0x1200 70 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300 71 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 72 #define PCI_DEVICE_ID_38C0800_REV1 0x2500 73 #define PCI_DEVICE_ID_38C1600_REV1 0x2700 74 75 #define PortAddr unsigned int /* port address size */ 76 #define inp(port) inb(port) 77 #define outp(port, byte) outb((byte), (port)) 78 79 #define inpw(port) inw(port) 80 #define outpw(port, word) outw((word), (port)) 81 82 #define ASC_MAX_SG_QUEUE 7 83 #define ASC_MAX_SG_LIST 255 84 85 #define ASC_CS_TYPE unsigned short 86 87 #define ASC_IS_ISA (0x0001) 88 #define ASC_IS_ISAPNP (0x0081) 89 #define ASC_IS_EISA (0x0002) 90 #define ASC_IS_PCI (0x0004) 91 #define ASC_IS_PCI_ULTRA (0x0104) 92 #define ASC_IS_PCMCIA (0x0008) 93 #define ASC_IS_MCA (0x0020) 94 #define ASC_IS_VL (0x0040) 95 #define ASC_IS_WIDESCSI_16 (0x0100) 96 #define ASC_IS_WIDESCSI_32 (0x0200) 97 #define ASC_IS_BIG_ENDIAN (0x8000) 98 99 #define ASC_CHIP_MIN_VER_VL (0x01) 100 #define ASC_CHIP_MAX_VER_VL (0x07) 101 #define ASC_CHIP_MIN_VER_PCI (0x09) 102 #define ASC_CHIP_MAX_VER_PCI (0x0F) 103 #define ASC_CHIP_VER_PCI_BIT (0x08) 104 #define ASC_CHIP_MIN_VER_ISA (0x11) 105 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21) 106 #define ASC_CHIP_MAX_VER_ISA (0x27) 107 #define ASC_CHIP_VER_ISA_BIT (0x30) 108 #define ASC_CHIP_VER_ISAPNP_BIT (0x20) 109 #define ASC_CHIP_VER_ASYN_BUG (0x21) 110 #define ASC_CHIP_VER_PCI 0x08 111 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02) 112 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03) 113 #define ASC_CHIP_MIN_VER_EISA (0x41) 114 #define ASC_CHIP_MAX_VER_EISA (0x47) 115 #define ASC_CHIP_VER_EISA_BIT (0x40) 116 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3) 117 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL) 118 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL) 119 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL) 120 121 #define ASC_SCSI_ID_BITS 3 122 #define ASC_SCSI_TIX_TYPE uchar 123 #define ASC_ALL_DEVICE_BIT_SET 0xFF 124 #define ASC_SCSI_BIT_ID_TYPE uchar 125 #define ASC_MAX_TID 7 126 #define ASC_MAX_LUN 7 127 #define ASC_SCSI_WIDTH_BIT_SET 0xFF 128 #define ASC_MAX_SENSE_LEN 32 129 #define ASC_MIN_SENSE_LEN 14 130 #define ASC_SCSI_RESET_HOLD_TIME_US 60 131 132 /* 133 * Narrow boards only support 12-byte commands, while wide boards 134 * extend to 16-byte commands. 135 */ 136 #define ASC_MAX_CDB_LEN 12 137 #define ADV_MAX_CDB_LEN 16 138 139 #define MS_SDTR_LEN 0x03 140 #define MS_WDTR_LEN 0x02 141 142 #define ASC_SG_LIST_PER_Q 7 143 #define QS_FREE 0x00 144 #define QS_READY 0x01 145 #define QS_DISC1 0x02 146 #define QS_DISC2 0x04 147 #define QS_BUSY 0x08 148 #define QS_ABORTED 0x40 149 #define QS_DONE 0x80 150 #define QC_NO_CALLBACK 0x01 151 #define QC_SG_SWAP_QUEUE 0x02 152 #define QC_SG_HEAD 0x04 153 #define QC_DATA_IN 0x08 154 #define QC_DATA_OUT 0x10 155 #define QC_URGENT 0x20 156 #define QC_MSG_OUT 0x40 157 #define QC_REQ_SENSE 0x80 158 #define QCSG_SG_XFER_LIST 0x02 159 #define QCSG_SG_XFER_MORE 0x04 160 #define QCSG_SG_XFER_END 0x08 161 #define QD_IN_PROGRESS 0x00 162 #define QD_NO_ERROR 0x01 163 #define QD_ABORTED_BY_HOST 0x02 164 #define QD_WITH_ERROR 0x04 165 #define QD_INVALID_REQUEST 0x80 166 #define QD_INVALID_HOST_NUM 0x81 167 #define QD_INVALID_DEVICE 0x82 168 #define QD_ERR_INTERNAL 0xFF 169 #define QHSTA_NO_ERROR 0x00 170 #define QHSTA_M_SEL_TIMEOUT 0x11 171 #define QHSTA_M_DATA_OVER_RUN 0x12 172 #define QHSTA_M_DATA_UNDER_RUN 0x12 173 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 174 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 175 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 176 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 177 #define QHSTA_D_HOST_ABORT_FAILED 0x23 178 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24 179 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 180 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26 181 #define QHSTA_M_WTM_TIMEOUT 0x41 182 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 183 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 184 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 185 #define QHSTA_M_TARGET_STATUS_BUSY 0x45 186 #define QHSTA_M_BAD_TAG_CODE 0x46 187 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 188 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 189 #define QHSTA_D_LRAM_CMP_ERROR 0x81 190 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 191 #define ASC_FLAG_SCSIQ_REQ 0x01 192 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02 193 #define ASC_FLAG_BIOS_ASYNC_IO 0x04 194 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08 195 #define ASC_FLAG_WIN16 0x10 196 #define ASC_FLAG_WIN32 0x20 197 #define ASC_FLAG_ISA_OVER_16MB 0x40 198 #define ASC_FLAG_DOS_VM_CALLBACK 0x80 199 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10 200 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04 201 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 202 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 203 #define ASC_SCSIQ_CPY_BEG 4 204 #define ASC_SCSIQ_SGHD_CPY_BEG 2 205 #define ASC_SCSIQ_B_FWD 0 206 #define ASC_SCSIQ_B_BWD 1 207 #define ASC_SCSIQ_B_STATUS 2 208 #define ASC_SCSIQ_B_QNO 3 209 #define ASC_SCSIQ_B_CNTL 4 210 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5 211 #define ASC_SCSIQ_D_DATA_ADDR 8 212 #define ASC_SCSIQ_D_DATA_CNT 12 213 #define ASC_SCSIQ_B_SENSE_LEN 20 214 #define ASC_SCSIQ_DONE_INFO_BEG 22 215 #define ASC_SCSIQ_D_SRBPTR 22 216 #define ASC_SCSIQ_B_TARGET_IX 26 217 #define ASC_SCSIQ_B_CDB_LEN 28 218 #define ASC_SCSIQ_B_TAG_CODE 29 219 #define ASC_SCSIQ_W_VM_ID 30 220 #define ASC_SCSIQ_DONE_STATUS 32 221 #define ASC_SCSIQ_HOST_STATUS 33 222 #define ASC_SCSIQ_SCSI_STATUS 34 223 #define ASC_SCSIQ_CDB_BEG 36 224 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56 225 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60 226 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48 227 #define ASC_SCSIQ_B_SG_WK_QP 49 228 #define ASC_SCSIQ_B_SG_WK_IX 50 229 #define ASC_SCSIQ_W_ALT_DC1 52 230 #define ASC_SCSIQ_B_LIST_CNT 6 231 #define ASC_SCSIQ_B_CUR_LIST_CNT 7 232 #define ASC_SGQ_B_SG_CNTL 4 233 #define ASC_SGQ_B_SG_HEAD_QP 5 234 #define ASC_SGQ_B_SG_LIST_CNT 6 235 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7 236 #define ASC_SGQ_LIST_BEG 8 237 #define ASC_DEF_SCSI1_QNG 4 238 #define ASC_MAX_SCSI1_QNG 4 239 #define ASC_DEF_SCSI2_QNG 16 240 #define ASC_MAX_SCSI2_QNG 32 241 #define ASC_TAG_CODE_MASK 0x23 242 #define ASC_STOP_REQ_RISC_STOP 0x01 243 #define ASC_STOP_ACK_RISC_STOP 0x03 244 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10 245 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20 246 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40 247 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS)) 248 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid)) 249 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID)) 250 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID) 251 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID) 252 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN) 253 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6)) 254 255 typedef struct asc_scsiq_1 { 256 uchar status; 257 uchar q_no; 258 uchar cntl; 259 uchar sg_queue_cnt; 260 uchar target_id; 261 uchar target_lun; 262 __le32 data_addr; 263 __le32 data_cnt; 264 __le32 sense_addr; 265 uchar sense_len; 266 uchar extra_bytes; 267 } ASC_SCSIQ_1; 268 269 typedef struct asc_scsiq_2 { 270 u32 srb_tag; 271 uchar target_ix; 272 uchar flag; 273 uchar cdb_len; 274 uchar tag_code; 275 ushort vm_id; 276 } ASC_SCSIQ_2; 277 278 typedef struct asc_scsiq_3 { 279 uchar done_stat; 280 uchar host_stat; 281 uchar scsi_stat; 282 uchar scsi_msg; 283 } ASC_SCSIQ_3; 284 285 typedef struct asc_scsiq_4 { 286 uchar cdb[ASC_MAX_CDB_LEN]; 287 uchar y_first_sg_list_qp; 288 uchar y_working_sg_qp; 289 uchar y_working_sg_ix; 290 uchar y_res; 291 ushort x_req_count; 292 ushort x_reconnect_rtn; 293 __le32 x_saved_data_addr; 294 __le32 x_saved_data_cnt; 295 } ASC_SCSIQ_4; 296 297 typedef struct asc_q_done_info { 298 ASC_SCSIQ_2 d2; 299 ASC_SCSIQ_3 d3; 300 uchar q_status; 301 uchar q_no; 302 uchar cntl; 303 uchar sense_len; 304 uchar extra_bytes; 305 uchar res; 306 u32 remain_bytes; 307 } ASC_QDONE_INFO; 308 309 typedef struct asc_sg_list { 310 __le32 addr; 311 __le32 bytes; 312 } ASC_SG_LIST; 313 314 typedef struct asc_sg_head { 315 ushort entry_cnt; 316 ushort queue_cnt; 317 ushort entry_to_copy; 318 ushort res; 319 ASC_SG_LIST sg_list[]; 320 } ASC_SG_HEAD; 321 322 typedef struct asc_scsi_q { 323 ASC_SCSIQ_1 q1; 324 ASC_SCSIQ_2 q2; 325 uchar *cdbptr; 326 ASC_SG_HEAD *sg_head; 327 ushort remain_sg_entry_cnt; 328 ushort next_sg_index; 329 } ASC_SCSI_Q; 330 331 typedef struct asc_scsi_bios_req_q { 332 ASC_SCSIQ_1 r1; 333 ASC_SCSIQ_2 r2; 334 uchar *cdbptr; 335 ASC_SG_HEAD *sg_head; 336 uchar *sense_ptr; 337 ASC_SCSIQ_3 r3; 338 uchar cdb[ASC_MAX_CDB_LEN]; 339 uchar sense[ASC_MIN_SENSE_LEN]; 340 } ASC_SCSI_BIOS_REQ_Q; 341 342 typedef struct asc_risc_q { 343 uchar fwd; 344 uchar bwd; 345 ASC_SCSIQ_1 i1; 346 ASC_SCSIQ_2 i2; 347 ASC_SCSIQ_3 i3; 348 ASC_SCSIQ_4 i4; 349 } ASC_RISC_Q; 350 351 typedef struct asc_sg_list_q { 352 uchar seq_no; 353 uchar q_no; 354 uchar cntl; 355 uchar sg_head_qp; 356 uchar sg_list_cnt; 357 uchar sg_cur_list_cnt; 358 } ASC_SG_LIST_Q; 359 360 typedef struct asc_risc_sg_list_q { 361 uchar fwd; 362 uchar bwd; 363 ASC_SG_LIST_Q sg; 364 ASC_SG_LIST sg_list[7]; 365 } ASC_RISC_SG_LIST_Q; 366 367 #define ASCQ_ERR_Q_STATUS 0x0D 368 #define ASCQ_ERR_CUR_QNG 0x17 369 #define ASCQ_ERR_SG_Q_LINKS 0x18 370 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A 371 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B 372 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C 373 374 /* 375 * Warning code values are set in ASC_DVC_VAR 'warn_code'. 376 */ 377 #define ASC_WARN_NO_ERROR 0x0000 378 #define ASC_WARN_IO_PORT_ROTATE 0x0001 379 #define ASC_WARN_EEPROM_CHKSUM 0x0002 380 #define ASC_WARN_IRQ_MODIFIED 0x0004 381 #define ASC_WARN_AUTO_CONFIG 0x0008 382 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010 383 #define ASC_WARN_EEPROM_RECOVER 0x0020 384 #define ASC_WARN_CFG_MSW_RECOVER 0x0040 385 386 /* 387 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'. 388 */ 389 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */ 390 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 391 #define ASC_IERR_SET_PC_ADDR 0x0004 392 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 393 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */ 394 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */ 395 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */ 396 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 397 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */ 398 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 399 #define ASC_IERR_NO_BUS_TYPE 0x0400 400 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */ 401 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */ 402 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */ 403 404 #define ASC_DEF_MAX_TOTAL_QNG (0xF0) 405 #define ASC_MIN_TAG_Q_PER_DVC (0x04) 406 #define ASC_MIN_FREE_Q (0x02) 407 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q)) 408 #define ASC_MAX_TOTAL_QNG 240 409 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 410 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 411 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20 412 #define ASC_MAX_INRAM_TAG_QNG 16 413 #define ASC_IOADR_GAP 0x10 414 #define ASC_SYN_MAX_OFFSET 0x0F 415 #define ASC_DEF_SDTR_OFFSET 0x0F 416 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02 417 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41 418 419 /* The narrow chip only supports a limited selection of transfer rates. 420 * These are encoded in the range 0..7 or 0..15 depending whether the chip 421 * is Ultra-capable or not. These tables let us convert from one to the other. 422 */ 423 static const unsigned char asc_syn_xfer_period[8] = { 424 25, 30, 35, 40, 50, 60, 70, 85 425 }; 426 427 static const unsigned char asc_syn_ultra_xfer_period[16] = { 428 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107 429 }; 430 431 typedef struct ext_msg { 432 uchar msg_type; 433 uchar msg_len; 434 uchar msg_req; 435 union { 436 struct { 437 uchar sdtr_xfer_period; 438 uchar sdtr_req_ack_offset; 439 } sdtr; 440 struct { 441 uchar wdtr_width; 442 } wdtr; 443 struct { 444 uchar mdp_b3; 445 uchar mdp_b2; 446 uchar mdp_b1; 447 uchar mdp_b0; 448 } mdp; 449 } u_ext_msg; 450 uchar res; 451 } EXT_MSG; 452 453 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period 454 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset 455 #define wdtr_width u_ext_msg.wdtr.wdtr_width 456 #define mdp_b3 u_ext_msg.mdp_b3 457 #define mdp_b2 u_ext_msg.mdp_b2 458 #define mdp_b1 u_ext_msg.mdp_b1 459 #define mdp_b0 u_ext_msg.mdp_b0 460 461 typedef struct asc_dvc_cfg { 462 ASC_SCSI_BIT_ID_TYPE can_tagged_qng; 463 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled; 464 ASC_SCSI_BIT_ID_TYPE disc_enable; 465 ASC_SCSI_BIT_ID_TYPE sdtr_enable; 466 uchar chip_scsi_id; 467 uchar isa_dma_speed; 468 uchar isa_dma_channel; 469 uchar chip_version; 470 ushort mcode_date; 471 ushort mcode_version; 472 uchar max_tag_qng[ASC_MAX_TID + 1]; 473 uchar sdtr_period_offset[ASC_MAX_TID + 1]; 474 uchar adapter_info[6]; 475 } ASC_DVC_CFG; 476 477 #define ASC_DEF_DVC_CNTL 0xFFFF 478 #define ASC_DEF_CHIP_SCSI_ID 7 479 #define ASC_DEF_ISA_DMA_SPEED 4 480 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001 481 #define ASC_INIT_STATE_END_GET_CFG 0x0002 482 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004 483 #define ASC_INIT_STATE_END_SET_CFG 0x0008 484 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010 485 #define ASC_INIT_STATE_END_LOAD_MC 0x0020 486 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040 487 #define ASC_INIT_STATE_END_INQUIRY 0x0080 488 #define ASC_INIT_RESET_SCSI_DONE 0x0100 489 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000 490 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001 491 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002 492 #define ASC_MIN_TAGGED_CMD 7 493 #define ASC_MAX_SCSI_RESET_WAIT 30 494 #define ASC_OVERRUN_BSIZE 64 495 496 struct asc_dvc_var; /* Forward Declaration. */ 497 498 typedef struct asc_dvc_var { 499 PortAddr iop_base; 500 ushort err_code; 501 ushort dvc_cntl; 502 ushort bug_fix_cntl; 503 ushort bus_type; 504 ASC_SCSI_BIT_ID_TYPE init_sdtr; 505 ASC_SCSI_BIT_ID_TYPE sdtr_done; 506 ASC_SCSI_BIT_ID_TYPE use_tagged_qng; 507 ASC_SCSI_BIT_ID_TYPE unit_not_ready; 508 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy; 509 ASC_SCSI_BIT_ID_TYPE start_motor; 510 uchar *overrun_buf; 511 dma_addr_t overrun_dma; 512 uchar scsi_reset_wait; 513 uchar chip_no; 514 bool is_in_int; 515 uchar max_total_qng; 516 uchar cur_total_qng; 517 uchar in_critical_cnt; 518 uchar last_q_shortage; 519 ushort init_state; 520 uchar cur_dvc_qng[ASC_MAX_TID + 1]; 521 uchar max_dvc_qng[ASC_MAX_TID + 1]; 522 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1]; 523 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1]; 524 const uchar *sdtr_period_tbl; 525 ASC_DVC_CFG *cfg; 526 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always; 527 char redo_scam; 528 ushort res2; 529 uchar dos_int13_table[ASC_MAX_TID + 1]; 530 unsigned int max_dma_count; 531 ASC_SCSI_BIT_ID_TYPE no_scam; 532 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer; 533 uchar min_sdtr_index; 534 uchar max_sdtr_index; 535 struct asc_board *drv_ptr; 536 unsigned int uc_break; 537 } ASC_DVC_VAR; 538 539 typedef struct asc_dvc_inq_info { 540 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; 541 } ASC_DVC_INQ_INFO; 542 543 typedef struct asc_cap_info { 544 u32 lba; 545 u32 blk_size; 546 } ASC_CAP_INFO; 547 548 typedef struct asc_cap_info_array { 549 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; 550 } ASC_CAP_INFO_ARRAY; 551 552 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001 553 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002 554 #define ASC_CNTL_INITIATOR (ushort)0x0001 555 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002 556 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004 557 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008 558 #define ASC_CNTL_NO_SCAM (ushort)0x0010 559 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080 560 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040 561 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100 562 #define ASC_CNTL_RESET_SCSI (ushort)0x0200 563 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400 564 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800 565 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000 566 #define ASC_CNTL_BURST_MODE (ushort)0x2000 567 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000 568 #define ASC_EEP_DVC_CFG_BEG_VL 2 569 #define ASC_EEP_MAX_DVC_ADDR_VL 15 570 #define ASC_EEP_DVC_CFG_BEG 32 571 #define ASC_EEP_MAX_DVC_ADDR 45 572 #define ASC_EEP_MAX_RETRY 20 573 574 /* 575 * These macros keep the chip SCSI id and ISA DMA speed 576 * bitfields in board order. C bitfields aren't portable 577 * between big and little-endian platforms so they are 578 * not used. 579 */ 580 581 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f) 582 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4) 583 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \ 584 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID)) 585 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \ 586 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4) 587 588 typedef struct asceep_config { 589 ushort cfg_lsw; 590 ushort cfg_msw; 591 uchar init_sdtr; 592 uchar disc_enable; 593 uchar use_cmd_qng; 594 uchar start_motor; 595 uchar max_total_qng; 596 uchar max_tag_qng; 597 uchar bios_scan; 598 uchar power_up_wait; 599 uchar no_scam; 600 uchar id_speed; /* low order 4 bits is chip scsi id */ 601 /* high order 4 bits is isa dma speed */ 602 uchar dos_int13_table[ASC_MAX_TID + 1]; 603 uchar adapter_info[6]; 604 ushort cntl; 605 ushort chksum; 606 } ASCEEP_CONFIG; 607 608 #define ASC_EEP_CMD_READ 0x80 609 #define ASC_EEP_CMD_WRITE 0x40 610 #define ASC_EEP_CMD_WRITE_ABLE 0x30 611 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 612 #define ASCV_MSGOUT_BEG 0x0000 613 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3) 614 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4) 615 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006 616 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8) 617 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3) 618 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4) 619 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8) 620 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8) 621 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020 622 #define ASCV_BREAK_ADDR (ushort)0x0028 623 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A 624 #define ASCV_BREAK_CONTROL (ushort)0x002C 625 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E 626 627 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030 628 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032 629 #define ASCV_MCODE_SIZE_W (ushort)0x0034 630 #define ASCV_STOP_CODE_B (ushort)0x0036 631 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037 632 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038 633 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C 634 #define ASCV_HALTCODE_W (ushort)0x0040 635 #define ASCV_CHKSUM_W (ushort)0x0042 636 #define ASCV_MC_DATE_W (ushort)0x0044 637 #define ASCV_MC_VER_W (ushort)0x0046 638 #define ASCV_NEXTRDY_B (ushort)0x0048 639 #define ASCV_DONENEXT_B (ushort)0x0049 640 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A 641 #define ASCV_SCSIBUSY_B (ushort)0x004B 642 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C 643 #define ASCV_CURCDB_B (ushort)0x004D 644 #define ASCV_RCLUN_B (ushort)0x004E 645 #define ASCV_BUSY_QHEAD_B (ushort)0x004F 646 #define ASCV_DISC1_QHEAD_B (ushort)0x0050 647 #define ASCV_DISC_ENABLE_B (ushort)0x0052 648 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053 649 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055 650 #define ASCV_MCODE_CNTL_B (ushort)0x0056 651 #define ASCV_NULL_TARGET_B (ushort)0x0057 652 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058 653 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A 654 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1) 655 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1) 656 #define ASCV_HOST_FLAG_B (ushort)0x005D 657 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064 658 #define ASCV_VER_SERIAL_B (ushort)0x0065 659 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066 660 #define ASCV_WTM_FLAG_B (ushort)0x0068 661 #define ASCV_RISC_FLAG_B (ushort)0x006A 662 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B 663 #define ASC_HOST_FLAG_IN_ISR 0x01 664 #define ASC_HOST_FLAG_ACK_INT 0x02 665 #define ASC_RISC_FLAG_GEN_INT 0x01 666 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02 667 #define IOP_CTRL (0x0F) 668 #define IOP_STATUS (0x0E) 669 #define IOP_INT_ACK IOP_STATUS 670 #define IOP_REG_IFC (0x0D) 671 #define IOP_SYN_OFFSET (0x0B) 672 #define IOP_EXTRA_CONTROL (0x0D) 673 #define IOP_REG_PC (0x0C) 674 #define IOP_RAM_ADDR (0x0A) 675 #define IOP_RAM_DATA (0x08) 676 #define IOP_EEP_DATA (0x06) 677 #define IOP_EEP_CMD (0x07) 678 #define IOP_VERSION (0x03) 679 #define IOP_CONFIG_HIGH (0x04) 680 #define IOP_CONFIG_LOW (0x02) 681 #define IOP_SIG_BYTE (0x01) 682 #define IOP_SIG_WORD (0x00) 683 #define IOP_REG_DC1 (0x0E) 684 #define IOP_REG_DC0 (0x0C) 685 #define IOP_REG_SB (0x0B) 686 #define IOP_REG_DA1 (0x0A) 687 #define IOP_REG_DA0 (0x08) 688 #define IOP_REG_SC (0x09) 689 #define IOP_DMA_SPEED (0x07) 690 #define IOP_REG_FLAG (0x07) 691 #define IOP_FIFO_H (0x06) 692 #define IOP_FIFO_L (0x04) 693 #define IOP_REG_ID (0x05) 694 #define IOP_REG_QP (0x03) 695 #define IOP_REG_IH (0x02) 696 #define IOP_REG_IX (0x01) 697 #define IOP_REG_AX (0x00) 698 #define IFC_REG_LOCK (0x00) 699 #define IFC_REG_UNLOCK (0x09) 700 #define IFC_WR_EN_FILTER (0x10) 701 #define IFC_RD_NO_EEPROM (0x10) 702 #define IFC_SLEW_RATE (0x20) 703 #define IFC_ACT_NEG (0x40) 704 #define IFC_INP_FILTER (0x80) 705 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK) 706 #define SC_SEL (uchar)(0x80) 707 #define SC_BSY (uchar)(0x40) 708 #define SC_ACK (uchar)(0x20) 709 #define SC_REQ (uchar)(0x10) 710 #define SC_ATN (uchar)(0x08) 711 #define SC_IO (uchar)(0x04) 712 #define SC_CD (uchar)(0x02) 713 #define SC_MSG (uchar)(0x01) 714 #define SEC_SCSI_CTL (uchar)(0x80) 715 #define SEC_ACTIVE_NEGATE (uchar)(0x40) 716 #define SEC_SLEW_RATE (uchar)(0x20) 717 #define SEC_ENABLE_FILTER (uchar)(0x10) 718 #define ASC_HALT_EXTMSG_IN (ushort)0x8000 719 #define ASC_HALT_CHK_CONDITION (ushort)0x8100 720 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200 721 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300 722 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400 723 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000 724 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000 725 #define ASC_MAX_QNO 0xF8 726 #define ASC_DATA_SEC_BEG (ushort)0x0080 727 #define ASC_DATA_SEC_END (ushort)0x0080 728 #define ASC_CODE_SEC_BEG (ushort)0x0080 729 #define ASC_CODE_SEC_END (ushort)0x0080 730 #define ASC_QADR_BEG (0x4000) 731 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64) 732 #define ASC_QADR_END (ushort)0x7FFF 733 #define ASC_QLAST_ADR (ushort)0x7FC0 734 #define ASC_QBLK_SIZE 0x40 735 #define ASC_BIOS_DATA_QBEG 0xF8 736 #define ASC_MIN_ACTIVE_QNO 0x01 737 #define ASC_QLINK_END 0xFF 738 #define ASC_EEPROM_WORDS 0x10 739 #define ASC_MAX_MGS_LEN 0x10 740 #define ASC_BIOS_ADDR_DEF 0xDC00 741 #define ASC_BIOS_SIZE 0x3800 742 #define ASC_BIOS_RAM_OFF 0x3800 743 #define ASC_BIOS_RAM_SIZE 0x800 744 #define ASC_BIOS_MIN_ADDR 0xC000 745 #define ASC_BIOS_MAX_ADDR 0xEC00 746 #define ASC_BIOS_BANK_SIZE 0x0400 747 #define ASC_MCODE_START_ADDR 0x0080 748 #define ASC_CFG0_HOST_INT_ON 0x0020 749 #define ASC_CFG0_BIOS_ON 0x0040 750 #define ASC_CFG0_VERA_BURST_ON 0x0080 751 #define ASC_CFG0_SCSI_PARITY_ON 0x0800 752 #define ASC_CFG1_SCSI_TARGET_ON 0x0080 753 #define ASC_CFG1_LRAM_8BITS_ON 0x0800 754 #define ASC_CFG_MSW_CLR_MASK 0x3080 755 #define CSW_TEST1 (ASC_CS_TYPE)0x8000 756 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000 757 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000 758 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000 759 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800 760 #define CSW_TEST2 (ASC_CS_TYPE)0x0400 761 #define CSW_TEST3 (ASC_CS_TYPE)0x0200 762 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100 763 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080 764 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040 765 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020 766 #define CSW_HALTED (ASC_CS_TYPE)0x0010 767 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008 768 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004 769 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002 770 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001 771 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000 772 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100 773 #define CIW_TEST1 (ASC_CS_TYPE)0x0200 774 #define CIW_TEST2 (ASC_CS_TYPE)0x0400 775 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800 776 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000 777 #define CC_CHIP_RESET (uchar)0x80 778 #define CC_SCSI_RESET (uchar)0x40 779 #define CC_HALT (uchar)0x20 780 #define CC_SINGLE_STEP (uchar)0x10 781 #define CC_DMA_ABLE (uchar)0x08 782 #define CC_TEST (uchar)0x04 783 #define CC_BANK_ONE (uchar)0x02 784 #define CC_DIAG (uchar)0x01 785 #define ASC_1000_ID0W 0x04C1 786 #define ASC_1000_ID0W_FIX 0x00C1 787 #define ASC_1000_ID1B 0x25 788 #define ASC_EISA_REV_IOP_MASK (0x0C83) 789 #define ASC_EISA_CFG_IOP_MASK (0x0C86) 790 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000) 791 #define INS_HALTINT (ushort)0x6281 792 #define INS_HALT (ushort)0x6280 793 #define INS_SINT (ushort)0x6200 794 #define INS_RFLAG_WTM (ushort)0x7380 795 #define ASC_MC_SAVE_CODE_WSIZE 0x500 796 #define ASC_MC_SAVE_DATA_WSIZE 0x40 797 798 typedef struct asc_mc_saved { 799 ushort data[ASC_MC_SAVE_DATA_WSIZE]; 800 ushort code[ASC_MC_SAVE_CODE_WSIZE]; 801 } ASC_MC_SAVED; 802 803 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B) 804 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val) 805 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W) 806 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W) 807 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val) 808 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val) 809 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B) 810 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B) 811 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val) 812 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val) 813 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data)) 814 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id)) 815 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data) 816 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id)) 817 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE) 818 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD) 819 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION) 820 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW) 821 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH) 822 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data) 823 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data) 824 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD) 825 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data) 826 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA) 827 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data) 828 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR)) 829 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr) 830 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA) 831 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data) 832 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC) 833 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data) 834 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS) 835 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val) 836 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL) 837 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val) 838 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET) 839 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data) 840 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data) 841 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC) 842 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH)) 843 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID) 844 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL) 845 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data) 846 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX) 847 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data) 848 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX) 849 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data) 850 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH) 851 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data) 852 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP) 853 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data) 854 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L) 855 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data) 856 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H) 857 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data) 858 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED) 859 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data) 860 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0) 861 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data) 862 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1) 863 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data) 864 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0) 865 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data) 866 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1) 867 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data) 868 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID) 869 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data) 870 871 #define AdvPortAddr void __iomem * /* Virtual memory address size */ 872 873 /* 874 * Define Adv Library required memory access macros. 875 */ 876 #define ADV_MEM_READB(addr) readb(addr) 877 #define ADV_MEM_READW(addr) readw(addr) 878 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr) 879 #define ADV_MEM_WRITEW(addr, word) writew(word, addr) 880 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr) 881 882 /* 883 * Define total number of simultaneous maximum element scatter-gather 884 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the 885 * maximum number of outstanding commands per wide host adapter. Each 886 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather 887 * elements. Allow each command to have at least one ADV_SG_BLOCK structure. 888 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK 889 * structures or 255 scatter-gather elements. 890 */ 891 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG 892 893 /* 894 * Define maximum number of scatter-gather elements per request. 895 */ 896 #define ADV_MAX_SG_LIST 255 897 #define NO_OF_SG_PER_BLOCK 15 898 899 #define ADV_EEP_DVC_CFG_BEGIN (0x00) 900 #define ADV_EEP_DVC_CFG_END (0x15) 901 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 902 #define ADV_EEP_MAX_WORD_ADDR (0x1E) 903 904 #define ADV_EEP_DELAY_MS 100 905 906 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 907 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 908 /* 909 * For the ASC3550 Bit 13 is Termination Polarity control bit. 910 * For later ICs Bit 13 controls whether the CIS (Card Information 911 * Service Section) is loaded from EEPROM. 912 */ 913 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 914 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ 915 /* 916 * ASC38C1600 Bit 11 917 * 918 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify 919 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then 920 * Function 0 will specify INT B. 921 * 922 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify 923 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then 924 * Function 1 will specify INT A. 925 */ 926 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ 927 928 typedef struct adveep_3550_config { 929 /* Word Offset, Description */ 930 931 ushort cfg_lsw; /* 00 power up initialization */ 932 /* bit 13 set - Term Polarity Control */ 933 /* bit 14 set - BIOS Enable */ 934 /* bit 15 set - Big Endian Mode */ 935 ushort cfg_msw; /* 01 unused */ 936 ushort disc_enable; /* 02 disconnect enable */ 937 ushort wdtr_able; /* 03 Wide DTR able */ 938 ushort sdtr_able; /* 04 Synchronous DTR able */ 939 ushort start_motor; /* 05 send start up motor */ 940 ushort tagqng_able; /* 06 tag queuing able */ 941 ushort bios_scan; /* 07 BIOS device control */ 942 ushort scam_tolerant; /* 08 no scam */ 943 944 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 945 uchar bios_boot_delay; /* power up wait */ 946 947 uchar scsi_reset_delay; /* 10 reset delay */ 948 uchar bios_id_lun; /* first boot device scsi id & lun */ 949 /* high nibble is lun */ 950 /* low nibble is scsi id */ 951 952 uchar termination; /* 11 0 - automatic */ 953 /* 1 - low off / high off */ 954 /* 2 - low off / high on */ 955 /* 3 - low on / high on */ 956 /* There is no low on / high off */ 957 958 uchar reserved1; /* reserved byte (not used) */ 959 960 ushort bios_ctrl; /* 12 BIOS control bits */ 961 /* bit 0 BIOS don't act as initiator. */ 962 /* bit 1 BIOS > 1 GB support */ 963 /* bit 2 BIOS > 2 Disk Support */ 964 /* bit 3 BIOS don't support removables */ 965 /* bit 4 BIOS support bootable CD */ 966 /* bit 5 BIOS scan enabled */ 967 /* bit 6 BIOS support multiple LUNs */ 968 /* bit 7 BIOS display of message */ 969 /* bit 8 SCAM disabled */ 970 /* bit 9 Reset SCSI bus during init. */ 971 /* bit 10 */ 972 /* bit 11 No verbose initialization. */ 973 /* bit 12 SCSI parity enabled */ 974 /* bit 13 */ 975 /* bit 14 */ 976 /* bit 15 */ 977 ushort ultra_able; /* 13 ULTRA speed able */ 978 ushort reserved2; /* 14 reserved */ 979 uchar max_host_qng; /* 15 maximum host queuing */ 980 uchar max_dvc_qng; /* maximum per device queuing */ 981 ushort dvc_cntl; /* 16 control bit for driver */ 982 ushort bug_fix; /* 17 control bit for bug fix */ 983 ushort serial_number_word1; /* 18 Board serial number word 1 */ 984 ushort serial_number_word2; /* 19 Board serial number word 2 */ 985 ushort serial_number_word3; /* 20 Board serial number word 3 */ 986 ushort check_sum; /* 21 EEP check sum */ 987 uchar oem_name[16]; /* 22 OEM name */ 988 ushort dvc_err_code; /* 30 last device driver error code */ 989 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 990 ushort adv_err_addr; /* 32 last uc error address */ 991 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 992 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 993 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 994 ushort num_of_err; /* 36 number of error */ 995 } ADVEEP_3550_CONFIG; 996 997 typedef struct adveep_38C0800_config { 998 /* Word Offset, Description */ 999 1000 ushort cfg_lsw; /* 00 power up initialization */ 1001 /* bit 13 set - Load CIS */ 1002 /* bit 14 set - BIOS Enable */ 1003 /* bit 15 set - Big Endian Mode */ 1004 ushort cfg_msw; /* 01 unused */ 1005 ushort disc_enable; /* 02 disconnect enable */ 1006 ushort wdtr_able; /* 03 Wide DTR able */ 1007 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 1008 ushort start_motor; /* 05 send start up motor */ 1009 ushort tagqng_able; /* 06 tag queuing able */ 1010 ushort bios_scan; /* 07 BIOS device control */ 1011 ushort scam_tolerant; /* 08 no scam */ 1012 1013 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 1014 uchar bios_boot_delay; /* power up wait */ 1015 1016 uchar scsi_reset_delay; /* 10 reset delay */ 1017 uchar bios_id_lun; /* first boot device scsi id & lun */ 1018 /* high nibble is lun */ 1019 /* low nibble is scsi id */ 1020 1021 uchar termination_se; /* 11 0 - automatic */ 1022 /* 1 - low off / high off */ 1023 /* 2 - low off / high on */ 1024 /* 3 - low on / high on */ 1025 /* There is no low on / high off */ 1026 1027 uchar termination_lvd; /* 11 0 - automatic */ 1028 /* 1 - low off / high off */ 1029 /* 2 - low off / high on */ 1030 /* 3 - low on / high on */ 1031 /* There is no low on / high off */ 1032 1033 ushort bios_ctrl; /* 12 BIOS control bits */ 1034 /* bit 0 BIOS don't act as initiator. */ 1035 /* bit 1 BIOS > 1 GB support */ 1036 /* bit 2 BIOS > 2 Disk Support */ 1037 /* bit 3 BIOS don't support removables */ 1038 /* bit 4 BIOS support bootable CD */ 1039 /* bit 5 BIOS scan enabled */ 1040 /* bit 6 BIOS support multiple LUNs */ 1041 /* bit 7 BIOS display of message */ 1042 /* bit 8 SCAM disabled */ 1043 /* bit 9 Reset SCSI bus during init. */ 1044 /* bit 10 */ 1045 /* bit 11 No verbose initialization. */ 1046 /* bit 12 SCSI parity enabled */ 1047 /* bit 13 */ 1048 /* bit 14 */ 1049 /* bit 15 */ 1050 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 1051 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 1052 uchar max_host_qng; /* 15 maximum host queueing */ 1053 uchar max_dvc_qng; /* maximum per device queuing */ 1054 ushort dvc_cntl; /* 16 control bit for driver */ 1055 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 1056 ushort serial_number_word1; /* 18 Board serial number word 1 */ 1057 ushort serial_number_word2; /* 19 Board serial number word 2 */ 1058 ushort serial_number_word3; /* 20 Board serial number word 3 */ 1059 ushort check_sum; /* 21 EEP check sum */ 1060 uchar oem_name[16]; /* 22 OEM name */ 1061 ushort dvc_err_code; /* 30 last device driver error code */ 1062 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 1063 ushort adv_err_addr; /* 32 last uc error address */ 1064 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 1065 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 1066 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 1067 ushort reserved36; /* 36 reserved */ 1068 ushort reserved37; /* 37 reserved */ 1069 ushort reserved38; /* 38 reserved */ 1070 ushort reserved39; /* 39 reserved */ 1071 ushort reserved40; /* 40 reserved */ 1072 ushort reserved41; /* 41 reserved */ 1073 ushort reserved42; /* 42 reserved */ 1074 ushort reserved43; /* 43 reserved */ 1075 ushort reserved44; /* 44 reserved */ 1076 ushort reserved45; /* 45 reserved */ 1077 ushort reserved46; /* 46 reserved */ 1078 ushort reserved47; /* 47 reserved */ 1079 ushort reserved48; /* 48 reserved */ 1080 ushort reserved49; /* 49 reserved */ 1081 ushort reserved50; /* 50 reserved */ 1082 ushort reserved51; /* 51 reserved */ 1083 ushort reserved52; /* 52 reserved */ 1084 ushort reserved53; /* 53 reserved */ 1085 ushort reserved54; /* 54 reserved */ 1086 ushort reserved55; /* 55 reserved */ 1087 ushort cisptr_lsw; /* 56 CIS PTR LSW */ 1088 ushort cisprt_msw; /* 57 CIS PTR MSW */ 1089 ushort subsysvid; /* 58 SubSystem Vendor ID */ 1090 ushort subsysid; /* 59 SubSystem ID */ 1091 ushort reserved60; /* 60 reserved */ 1092 ushort reserved61; /* 61 reserved */ 1093 ushort reserved62; /* 62 reserved */ 1094 ushort reserved63; /* 63 reserved */ 1095 } ADVEEP_38C0800_CONFIG; 1096 1097 typedef struct adveep_38C1600_config { 1098 /* Word Offset, Description */ 1099 1100 ushort cfg_lsw; /* 00 power up initialization */ 1101 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */ 1102 /* clear - Func. 0 INTA, Func. 1 INTB */ 1103 /* bit 13 set - Load CIS */ 1104 /* bit 14 set - BIOS Enable */ 1105 /* bit 15 set - Big Endian Mode */ 1106 ushort cfg_msw; /* 01 unused */ 1107 ushort disc_enable; /* 02 disconnect enable */ 1108 ushort wdtr_able; /* 03 Wide DTR able */ 1109 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 1110 ushort start_motor; /* 05 send start up motor */ 1111 ushort tagqng_able; /* 06 tag queuing able */ 1112 ushort bios_scan; /* 07 BIOS device control */ 1113 ushort scam_tolerant; /* 08 no scam */ 1114 1115 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 1116 uchar bios_boot_delay; /* power up wait */ 1117 1118 uchar scsi_reset_delay; /* 10 reset delay */ 1119 uchar bios_id_lun; /* first boot device scsi id & lun */ 1120 /* high nibble is lun */ 1121 /* low nibble is scsi id */ 1122 1123 uchar termination_se; /* 11 0 - automatic */ 1124 /* 1 - low off / high off */ 1125 /* 2 - low off / high on */ 1126 /* 3 - low on / high on */ 1127 /* There is no low on / high off */ 1128 1129 uchar termination_lvd; /* 11 0 - automatic */ 1130 /* 1 - low off / high off */ 1131 /* 2 - low off / high on */ 1132 /* 3 - low on / high on */ 1133 /* There is no low on / high off */ 1134 1135 ushort bios_ctrl; /* 12 BIOS control bits */ 1136 /* bit 0 BIOS don't act as initiator. */ 1137 /* bit 1 BIOS > 1 GB support */ 1138 /* bit 2 BIOS > 2 Disk Support */ 1139 /* bit 3 BIOS don't support removables */ 1140 /* bit 4 BIOS support bootable CD */ 1141 /* bit 5 BIOS scan enabled */ 1142 /* bit 6 BIOS support multiple LUNs */ 1143 /* bit 7 BIOS display of message */ 1144 /* bit 8 SCAM disabled */ 1145 /* bit 9 Reset SCSI bus during init. */ 1146 /* bit 10 Basic Integrity Checking disabled */ 1147 /* bit 11 No verbose initialization. */ 1148 /* bit 12 SCSI parity enabled */ 1149 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */ 1150 /* bit 14 */ 1151 /* bit 15 */ 1152 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 1153 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 1154 uchar max_host_qng; /* 15 maximum host queueing */ 1155 uchar max_dvc_qng; /* maximum per device queuing */ 1156 ushort dvc_cntl; /* 16 control bit for driver */ 1157 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 1158 ushort serial_number_word1; /* 18 Board serial number word 1 */ 1159 ushort serial_number_word2; /* 19 Board serial number word 2 */ 1160 ushort serial_number_word3; /* 20 Board serial number word 3 */ 1161 ushort check_sum; /* 21 EEP check sum */ 1162 uchar oem_name[16]; /* 22 OEM name */ 1163 ushort dvc_err_code; /* 30 last device driver error code */ 1164 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 1165 ushort adv_err_addr; /* 32 last uc error address */ 1166 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 1167 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 1168 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 1169 ushort reserved36; /* 36 reserved */ 1170 ushort reserved37; /* 37 reserved */ 1171 ushort reserved38; /* 38 reserved */ 1172 ushort reserved39; /* 39 reserved */ 1173 ushort reserved40; /* 40 reserved */ 1174 ushort reserved41; /* 41 reserved */ 1175 ushort reserved42; /* 42 reserved */ 1176 ushort reserved43; /* 43 reserved */ 1177 ushort reserved44; /* 44 reserved */ 1178 ushort reserved45; /* 45 reserved */ 1179 ushort reserved46; /* 46 reserved */ 1180 ushort reserved47; /* 47 reserved */ 1181 ushort reserved48; /* 48 reserved */ 1182 ushort reserved49; /* 49 reserved */ 1183 ushort reserved50; /* 50 reserved */ 1184 ushort reserved51; /* 51 reserved */ 1185 ushort reserved52; /* 52 reserved */ 1186 ushort reserved53; /* 53 reserved */ 1187 ushort reserved54; /* 54 reserved */ 1188 ushort reserved55; /* 55 reserved */ 1189 ushort cisptr_lsw; /* 56 CIS PTR LSW */ 1190 ushort cisprt_msw; /* 57 CIS PTR MSW */ 1191 ushort subsysvid; /* 58 SubSystem Vendor ID */ 1192 ushort subsysid; /* 59 SubSystem ID */ 1193 ushort reserved60; /* 60 reserved */ 1194 ushort reserved61; /* 61 reserved */ 1195 ushort reserved62; /* 62 reserved */ 1196 ushort reserved63; /* 63 reserved */ 1197 } ADVEEP_38C1600_CONFIG; 1198 1199 /* 1200 * EEPROM Commands 1201 */ 1202 #define ASC_EEP_CMD_DONE 0x0200 1203 1204 /* bios_ctrl */ 1205 #define BIOS_CTRL_BIOS 0x0001 1206 #define BIOS_CTRL_EXTENDED_XLAT 0x0002 1207 #define BIOS_CTRL_GT_2_DISK 0x0004 1208 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008 1209 #define BIOS_CTRL_BOOTABLE_CD 0x0010 1210 #define BIOS_CTRL_MULTIPLE_LUN 0x0040 1211 #define BIOS_CTRL_DISPLAY_MSG 0x0080 1212 #define BIOS_CTRL_NO_SCAM 0x0100 1213 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 1214 #define BIOS_CTRL_INIT_VERBOSE 0x0800 1215 #define BIOS_CTRL_SCSI_PARITY 0x1000 1216 #define BIOS_CTRL_AIPP_DIS 0x2000 1217 1218 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 1219 1220 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 1221 1222 /* 1223 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is 1224 * a special 16K Adv Library and Microcode version. After the issue is 1225 * resolved, should restore 32K support. 1226 * 1227 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory * 1228 */ 1229 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 1230 1231 /* 1232 * Byte I/O register address from base of 'iop_base'. 1233 */ 1234 #define IOPB_INTR_STATUS_REG 0x00 1235 #define IOPB_CHIP_ID_1 0x01 1236 #define IOPB_INTR_ENABLES 0x02 1237 #define IOPB_CHIP_TYPE_REV 0x03 1238 #define IOPB_RES_ADDR_4 0x04 1239 #define IOPB_RES_ADDR_5 0x05 1240 #define IOPB_RAM_DATA 0x06 1241 #define IOPB_RES_ADDR_7 0x07 1242 #define IOPB_FLAG_REG 0x08 1243 #define IOPB_RES_ADDR_9 0x09 1244 #define IOPB_RISC_CSR 0x0A 1245 #define IOPB_RES_ADDR_B 0x0B 1246 #define IOPB_RES_ADDR_C 0x0C 1247 #define IOPB_RES_ADDR_D 0x0D 1248 #define IOPB_SOFT_OVER_WR 0x0E 1249 #define IOPB_RES_ADDR_F 0x0F 1250 #define IOPB_MEM_CFG 0x10 1251 #define IOPB_RES_ADDR_11 0x11 1252 #define IOPB_GPIO_DATA 0x12 1253 #define IOPB_RES_ADDR_13 0x13 1254 #define IOPB_FLASH_PAGE 0x14 1255 #define IOPB_RES_ADDR_15 0x15 1256 #define IOPB_GPIO_CNTL 0x16 1257 #define IOPB_RES_ADDR_17 0x17 1258 #define IOPB_FLASH_DATA 0x18 1259 #define IOPB_RES_ADDR_19 0x19 1260 #define IOPB_RES_ADDR_1A 0x1A 1261 #define IOPB_RES_ADDR_1B 0x1B 1262 #define IOPB_RES_ADDR_1C 0x1C 1263 #define IOPB_RES_ADDR_1D 0x1D 1264 #define IOPB_RES_ADDR_1E 0x1E 1265 #define IOPB_RES_ADDR_1F 0x1F 1266 #define IOPB_DMA_CFG0 0x20 1267 #define IOPB_DMA_CFG1 0x21 1268 #define IOPB_TICKLE 0x22 1269 #define IOPB_DMA_REG_WR 0x23 1270 #define IOPB_SDMA_STATUS 0x24 1271 #define IOPB_SCSI_BYTE_CNT 0x25 1272 #define IOPB_HOST_BYTE_CNT 0x26 1273 #define IOPB_BYTE_LEFT_TO_XFER 0x27 1274 #define IOPB_BYTE_TO_XFER_0 0x28 1275 #define IOPB_BYTE_TO_XFER_1 0x29 1276 #define IOPB_BYTE_TO_XFER_2 0x2A 1277 #define IOPB_BYTE_TO_XFER_3 0x2B 1278 #define IOPB_ACC_GRP 0x2C 1279 #define IOPB_RES_ADDR_2D 0x2D 1280 #define IOPB_DEV_ID 0x2E 1281 #define IOPB_RES_ADDR_2F 0x2F 1282 #define IOPB_SCSI_DATA 0x30 1283 #define IOPB_RES_ADDR_31 0x31 1284 #define IOPB_RES_ADDR_32 0x32 1285 #define IOPB_SCSI_DATA_HSHK 0x33 1286 #define IOPB_SCSI_CTRL 0x34 1287 #define IOPB_RES_ADDR_35 0x35 1288 #define IOPB_RES_ADDR_36 0x36 1289 #define IOPB_RES_ADDR_37 0x37 1290 #define IOPB_RAM_BIST 0x38 1291 #define IOPB_PLL_TEST 0x39 1292 #define IOPB_PCI_INT_CFG 0x3A 1293 #define IOPB_RES_ADDR_3B 0x3B 1294 #define IOPB_RFIFO_CNT 0x3C 1295 #define IOPB_RES_ADDR_3D 0x3D 1296 #define IOPB_RES_ADDR_3E 0x3E 1297 #define IOPB_RES_ADDR_3F 0x3F 1298 1299 /* 1300 * Word I/O register address from base of 'iop_base'. 1301 */ 1302 #define IOPW_CHIP_ID_0 0x00 /* CID0 */ 1303 #define IOPW_CTRL_REG 0x02 /* CC */ 1304 #define IOPW_RAM_ADDR 0x04 /* LA */ 1305 #define IOPW_RAM_DATA 0x06 /* LD */ 1306 #define IOPW_RES_ADDR_08 0x08 1307 #define IOPW_RISC_CSR 0x0A /* CSR */ 1308 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 1309 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 1310 #define IOPW_RES_ADDR_10 0x10 1311 #define IOPW_SEL_MASK 0x12 /* SM */ 1312 #define IOPW_RES_ADDR_14 0x14 1313 #define IOPW_FLASH_ADDR 0x16 /* FA */ 1314 #define IOPW_RES_ADDR_18 0x18 1315 #define IOPW_EE_CMD 0x1A /* EC */ 1316 #define IOPW_EE_DATA 0x1C /* ED */ 1317 #define IOPW_SFIFO_CNT 0x1E /* SFC */ 1318 #define IOPW_RES_ADDR_20 0x20 1319 #define IOPW_Q_BASE 0x22 /* QB */ 1320 #define IOPW_QP 0x24 /* QP */ 1321 #define IOPW_IX 0x26 /* IX */ 1322 #define IOPW_SP 0x28 /* SP */ 1323 #define IOPW_PC 0x2A /* PC */ 1324 #define IOPW_RES_ADDR_2C 0x2C 1325 #define IOPW_RES_ADDR_2E 0x2E 1326 #define IOPW_SCSI_DATA 0x30 /* SD */ 1327 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 1328 #define IOPW_SCSI_CTRL 0x34 /* SC */ 1329 #define IOPW_HSHK_CFG 0x36 /* HCFG */ 1330 #define IOPW_SXFR_STATUS 0x36 /* SXS */ 1331 #define IOPW_SXFR_CNTL 0x38 /* SXL */ 1332 #define IOPW_SXFR_CNTH 0x3A /* SXH */ 1333 #define IOPW_RES_ADDR_3C 0x3C 1334 #define IOPW_RFIFO_DATA 0x3E /* RFD */ 1335 1336 /* 1337 * Doubleword I/O register address from base of 'iop_base'. 1338 */ 1339 #define IOPDW_RES_ADDR_0 0x00 1340 #define IOPDW_RAM_DATA 0x04 1341 #define IOPDW_RES_ADDR_8 0x08 1342 #define IOPDW_RES_ADDR_C 0x0C 1343 #define IOPDW_RES_ADDR_10 0x10 1344 #define IOPDW_COMMA 0x14 1345 #define IOPDW_COMMB 0x18 1346 #define IOPDW_RES_ADDR_1C 0x1C 1347 #define IOPDW_SDMA_ADDR0 0x20 1348 #define IOPDW_SDMA_ADDR1 0x24 1349 #define IOPDW_SDMA_COUNT 0x28 1350 #define IOPDW_SDMA_ERROR 0x2C 1351 #define IOPDW_RDMA_ADDR0 0x30 1352 #define IOPDW_RDMA_ADDR1 0x34 1353 #define IOPDW_RDMA_COUNT 0x38 1354 #define IOPDW_RDMA_ERROR 0x3C 1355 1356 #define ADV_CHIP_ID_BYTE 0x25 1357 #define ADV_CHIP_ID_WORD 0x04C1 1358 1359 #define ADV_INTR_ENABLE_HOST_INTR 0x01 1360 #define ADV_INTR_ENABLE_SEL_INTR 0x02 1361 #define ADV_INTR_ENABLE_DPR_INTR 0x04 1362 #define ADV_INTR_ENABLE_RTA_INTR 0x08 1363 #define ADV_INTR_ENABLE_RMA_INTR 0x10 1364 #define ADV_INTR_ENABLE_RST_INTR 0x20 1365 #define ADV_INTR_ENABLE_DPE_INTR 0x40 1366 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80 1367 1368 #define ADV_INTR_STATUS_INTRA 0x01 1369 #define ADV_INTR_STATUS_INTRB 0x02 1370 #define ADV_INTR_STATUS_INTRC 0x04 1371 1372 #define ADV_RISC_CSR_STOP (0x0000) 1373 #define ADV_RISC_TEST_COND (0x2000) 1374 #define ADV_RISC_CSR_RUN (0x4000) 1375 #define ADV_RISC_CSR_SINGLE_STEP (0x8000) 1376 1377 #define ADV_CTRL_REG_HOST_INTR 0x0100 1378 #define ADV_CTRL_REG_SEL_INTR 0x0200 1379 #define ADV_CTRL_REG_DPR_INTR 0x0400 1380 #define ADV_CTRL_REG_RTA_INTR 0x0800 1381 #define ADV_CTRL_REG_RMA_INTR 0x1000 1382 #define ADV_CTRL_REG_RES_BIT14 0x2000 1383 #define ADV_CTRL_REG_DPE_INTR 0x4000 1384 #define ADV_CTRL_REG_POWER_DONE 0x8000 1385 #define ADV_CTRL_REG_ANY_INTR 0xFF00 1386 1387 #define ADV_CTRL_REG_CMD_RESET 0x00C6 1388 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5 1389 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4 1390 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 1391 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 1392 1393 #define ADV_TICKLE_NOP 0x00 1394 #define ADV_TICKLE_A 0x01 1395 #define ADV_TICKLE_B 0x02 1396 #define ADV_TICKLE_C 0x03 1397 1398 #define AdvIsIntPending(port) \ 1399 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR) 1400 1401 /* 1402 * SCSI_CFG0 Register bit definitions 1403 */ 1404 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 1405 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 1406 #define EVEN_PARITY 0x1000 /* Select Even Parity */ 1407 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 1408 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 1409 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */ 1410 #define SCAM_EN 0x0080 /* Enable SCAM selection */ 1411 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 1412 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 1413 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 1414 #define OUR_ID 0x000F /* SCSI ID */ 1415 1416 /* 1417 * SCSI_CFG1 Register bit definitions 1418 */ 1419 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 1420 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 1421 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 1422 #define FILTER_SEL 0x0C00 /* Filter Period Selection */ 1423 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 1424 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 1425 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 1426 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */ 1427 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 1428 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 1429 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 1430 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */ 1431 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 1432 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 1433 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 1434 1435 /* 1436 * Addendum for ASC-38C0800 Chip 1437 * 1438 * The ASC-38C1600 Chip uses the same definitions except that the 1439 * bus mode override bits [12:10] have been moved to byte register 1440 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in 1441 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) 1442 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. 1443 * Also each ASC-38C1600 function or channel uses only cable bits [5:4] 1444 * and [1:0]. Bits [14], [7:6], [3:2] are unused. 1445 */ 1446 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ 1447 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */ 1448 #define HVD 0x1000 /* HVD Device Detect */ 1449 #define LVD 0x0800 /* LVD Device Detect */ 1450 #define SE 0x0400 /* SE Device Detect */ 1451 #define TERM_LVD 0x00C0 /* LVD Termination Bits */ 1452 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ 1453 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ 1454 #define TERM_SE 0x0030 /* SE Termination Bits */ 1455 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ 1456 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ 1457 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */ 1458 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */ 1459 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ 1460 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */ 1461 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ 1462 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ 1463 1464 #define CABLE_ILLEGAL_A 0x7 1465 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 1466 1467 #define CABLE_ILLEGAL_B 0xB 1468 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 1469 1470 /* 1471 * MEM_CFG Register bit definitions 1472 */ 1473 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 1474 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */ 1475 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */ 1476 #define RAM_SZ_2KB 0x00 /* 2 KB */ 1477 #define RAM_SZ_4KB 0x04 /* 4 KB */ 1478 #define RAM_SZ_8KB 0x08 /* 8 KB */ 1479 #define RAM_SZ_16KB 0x0C /* 16 KB */ 1480 #define RAM_SZ_32KB 0x10 /* 32 KB */ 1481 #define RAM_SZ_64KB 0x14 /* 64 KB */ 1482 1483 /* 1484 * DMA_CFG0 Register bit definitions 1485 * 1486 * This register is only accessible to the host. 1487 */ 1488 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 1489 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 1490 #define FIFO_THRESH_16B 0x00 /* 16 bytes */ 1491 #define FIFO_THRESH_32B 0x20 /* 32 bytes */ 1492 #define FIFO_THRESH_48B 0x30 /* 48 bytes */ 1493 #define FIFO_THRESH_64B 0x40 /* 64 bytes */ 1494 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 1495 #define FIFO_THRESH_96B 0x60 /* 96 bytes */ 1496 #define FIFO_THRESH_112B 0x70 /* 112 bytes */ 1497 #define START_CTL 0x0C /* DMA start conditions */ 1498 #define START_CTL_TH 0x00 /* Wait threshold level (default) */ 1499 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 1500 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 1501 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 1502 #define READ_CMD 0x03 /* Memory Read Method */ 1503 #define READ_CMD_MR 0x00 /* Memory Read */ 1504 #define READ_CMD_MRL 0x02 /* Memory Read Long */ 1505 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 1506 1507 /* 1508 * ASC-38C0800 RAM BIST Register bit definitions 1509 */ 1510 #define RAM_TEST_MODE 0x80 1511 #define PRE_TEST_MODE 0x40 1512 #define NORMAL_MODE 0x00 1513 #define RAM_TEST_DONE 0x10 1514 #define RAM_TEST_STATUS 0x0F 1515 #define RAM_TEST_HOST_ERROR 0x08 1516 #define RAM_TEST_INTRAM_ERROR 0x04 1517 #define RAM_TEST_RISC_ERROR 0x02 1518 #define RAM_TEST_SCSI_ERROR 0x01 1519 #define RAM_TEST_SUCCESS 0x00 1520 #define PRE_TEST_VALUE 0x05 1521 #define NORMAL_VALUE 0x00 1522 1523 /* 1524 * ASC38C1600 Definitions 1525 * 1526 * IOPB_PCI_INT_CFG Bit Field Definitions 1527 */ 1528 1529 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ 1530 1531 /* 1532 * Bit 1 can be set to change the interrupt for the Function to operate in 1533 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in 1534 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same 1535 * mode, otherwise the operating mode is undefined. 1536 */ 1537 #define TOTEMPOLE 0x02 1538 1539 /* 1540 * Bit 0 can be used to change the Int Pin for the Function. The value is 1541 * 0 by default for both Functions with Function 0 using INT A and Function 1542 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, 1543 * INT A is used. 1544 * 1545 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin 1546 * value specified in the PCI Configuration Space. 1547 */ 1548 #define INTAB 0x01 1549 1550 /* 1551 * Adv Library Status Definitions 1552 */ 1553 #define ADV_TRUE 1 1554 #define ADV_FALSE 0 1555 #define ADV_SUCCESS 1 1556 #define ADV_BUSY 0 1557 #define ADV_ERROR (-1) 1558 1559 /* 1560 * ADV_DVC_VAR 'warn_code' values 1561 */ 1562 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ 1563 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 1564 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 1565 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */ 1566 1567 #define ADV_MAX_TID 15 /* max. target identifier */ 1568 #define ADV_MAX_LUN 7 /* max. logical unit number */ 1569 1570 /* 1571 * Fixed locations of microcode operating variables. 1572 */ 1573 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 1574 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ 1575 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 1576 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ 1577 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */ 1578 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 1579 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 1580 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 1581 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ 1582 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 1583 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 1584 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 1585 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 1586 #define ASC_MC_CHIP_TYPE 0x009A 1587 #define ASC_MC_INTRB_CODE 0x009B 1588 #define ASC_MC_WDTR_ABLE 0x009C 1589 #define ASC_MC_SDTR_ABLE 0x009E 1590 #define ASC_MC_TAGQNG_ABLE 0x00A0 1591 #define ASC_MC_DISC_ENABLE 0x00A2 1592 #define ASC_MC_IDLE_CMD_STATUS 0x00A4 1593 #define ASC_MC_IDLE_CMD 0x00A6 1594 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8 1595 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC 1596 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE 1597 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0 1598 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2 1599 #define ASC_MC_SDTR_DONE 0x00B6 1600 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 1601 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 1602 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 1603 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 1604 #define ASC_MC_WDTR_DONE 0x0124 1605 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 1606 #define ASC_MC_ICQ 0x0160 1607 #define ASC_MC_IRQ 0x0164 1608 #define ASC_MC_PPR_ABLE 0x017A 1609 1610 /* 1611 * BIOS LRAM variable absolute offsets. 1612 */ 1613 #define BIOS_CODESEG 0x54 1614 #define BIOS_CODELEN 0x56 1615 #define BIOS_SIGNATURE 0x58 1616 #define BIOS_VERSION 0x5A 1617 1618 /* 1619 * Microcode Control Flags 1620 * 1621 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) 1622 * and handled by the microcode. 1623 */ 1624 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ 1625 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */ 1626 1627 /* 1628 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format 1629 */ 1630 #define HSHK_CFG_WIDE_XFR 0x8000 1631 #define HSHK_CFG_RATE 0x0F00 1632 #define HSHK_CFG_OFFSET 0x001F 1633 1634 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ 1635 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ 1636 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ 1637 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ 1638 1639 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */ 1640 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 1641 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 1642 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 1643 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */ 1644 1645 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 1646 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 1647 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ 1648 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 1649 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ 1650 /* 1651 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or 1652 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 1653 */ 1654 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 1655 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 1656 1657 /* 1658 * All fields here are accessed by the board microcode and need to be 1659 * little-endian. 1660 */ 1661 typedef struct adv_carr_t { 1662 __le32 carr_va; /* Carrier Virtual Address */ 1663 __le32 carr_pa; /* Carrier Physical Address */ 1664 __le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */ 1665 /* 1666 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer 1667 * 1668 * next_vpa [3:1] Reserved Bits 1669 * next_vpa [0] Done Flag set in Response Queue. 1670 */ 1671 __le32 next_vpa; 1672 } ADV_CARR_T; 1673 1674 /* 1675 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field. 1676 */ 1677 #define ADV_NEXT_VPA_MASK 0xFFFFFFF0 1678 1679 #define ADV_RQ_DONE 0x00000001 1680 #define ADV_RQ_GOOD 0x00000002 1681 #define ADV_CQ_STOPPER 0x00000000 1682 1683 #define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK) 1684 1685 /* 1686 * Each carrier is 64 bytes, and we need three additional 1687 * carrier for icq, irq, and the termination carrier. 1688 */ 1689 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3) 1690 1691 #define ADV_CARRIER_BUFSIZE \ 1692 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) 1693 1694 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ 1695 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ 1696 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ 1697 1698 /* 1699 * Adapter temporary configuration structure 1700 * 1701 * This structure can be discarded after initialization. Don't add 1702 * fields here needed after initialization. 1703 * 1704 * Field naming convention: 1705 * 1706 * *_enable indicates the field enables or disables a feature. The 1707 * value of the field is never reset. 1708 */ 1709 typedef struct adv_dvc_cfg { 1710 ushort disc_enable; /* enable disconnection */ 1711 uchar chip_version; /* chip version */ 1712 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ 1713 ushort control_flag; /* Microcode Control Flag */ 1714 ushort mcode_date; /* Microcode date */ 1715 ushort mcode_version; /* Microcode version */ 1716 ushort serial1; /* EEPROM serial number word 1 */ 1717 ushort serial2; /* EEPROM serial number word 2 */ 1718 ushort serial3; /* EEPROM serial number word 3 */ 1719 } ADV_DVC_CFG; 1720 1721 struct adv_dvc_var; 1722 struct adv_scsi_req_q; 1723 1724 typedef struct adv_sg_block { 1725 uchar reserved1; 1726 uchar reserved2; 1727 uchar reserved3; 1728 uchar sg_cnt; /* Valid entries in block. */ 1729 __le32 sg_ptr; /* Pointer to next sg block. */ 1730 struct { 1731 __le32 sg_addr; /* SG element address. */ 1732 __le32 sg_count; /* SG element count. */ 1733 } sg_list[NO_OF_SG_PER_BLOCK]; 1734 } ADV_SG_BLOCK; 1735 1736 /* 1737 * ADV_SCSI_REQ_Q - microcode request structure 1738 * 1739 * All fields in this structure up to byte 60 are used by the microcode. 1740 * The microcode makes assumptions about the size and ordering of fields 1741 * in this structure. Do not change the structure definition here without 1742 * coordinating the change with the microcode. 1743 * 1744 * All fields accessed by microcode must be maintained in little_endian 1745 * order. 1746 */ 1747 typedef struct adv_scsi_req_q { 1748 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */ 1749 uchar target_cmd; 1750 uchar target_id; /* Device target identifier. */ 1751 uchar target_lun; /* Device target logical unit number. */ 1752 __le32 data_addr; /* Data buffer physical address. */ 1753 __le32 data_cnt; /* Data count. Ucode sets to residual. */ 1754 __le32 sense_addr; 1755 __le32 carr_pa; 1756 uchar mflag; 1757 uchar sense_len; 1758 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ 1759 uchar scsi_cntl; 1760 uchar done_status; /* Completion status. */ 1761 uchar scsi_status; /* SCSI status byte. */ 1762 uchar host_status; /* Ucode host status. */ 1763 uchar sg_working_ix; 1764 uchar cdb[12]; /* SCSI CDB bytes 0-11. */ 1765 __le32 sg_real_addr; /* SG list physical address. */ 1766 __le32 scsiq_rptr; 1767 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */ 1768 __le32 scsiq_ptr; 1769 __le32 carr_va; 1770 /* 1771 * End of microcode structure - 60 bytes. The rest of the structure 1772 * is used by the Adv Library and ignored by the microcode. 1773 */ 1774 u32 srb_tag; 1775 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */ 1776 } ADV_SCSI_REQ_Q; 1777 1778 /* 1779 * The following two structures are used to process Wide Board requests. 1780 * 1781 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library 1782 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the 1783 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points 1784 * to the Mid-Level SCSI request structure. 1785 * 1786 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each 1787 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux 1788 * up to 255 scatter-gather elements may be used per request or 1789 * ADV_SCSI_REQ_Q. 1790 * 1791 * Both structures must be 32 byte aligned. 1792 */ 1793 typedef struct adv_sgblk { 1794 ADV_SG_BLOCK sg_block; /* Sgblock structure. */ 1795 dma_addr_t sg_addr; /* Physical address */ 1796 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */ 1797 } adv_sgblk_t; 1798 1799 typedef struct adv_req { 1800 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */ 1801 uchar align[24]; /* Request structure padding. */ 1802 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */ 1803 dma_addr_t req_addr; 1804 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */ 1805 } adv_req_t __aligned(32); 1806 1807 /* 1808 * Adapter operation variable structure. 1809 * 1810 * One structure is required per host adapter. 1811 * 1812 * Field naming convention: 1813 * 1814 * *_able indicates both whether a feature should be enabled or disabled 1815 * and whether a device isi capable of the feature. At initialization 1816 * this field may be set, but later if a device is found to be incapable 1817 * of the feature, the field is cleared. 1818 */ 1819 typedef struct adv_dvc_var { 1820 AdvPortAddr iop_base; /* I/O port address */ 1821 ushort err_code; /* fatal error code */ 1822 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */ 1823 ushort wdtr_able; /* try WDTR for a device */ 1824 ushort sdtr_able; /* try SDTR for a device */ 1825 ushort ultra_able; /* try SDTR Ultra speed for a device */ 1826 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ 1827 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ 1828 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ 1829 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ 1830 ushort tagqng_able; /* try tagged queuing with a device */ 1831 ushort ppr_able; /* PPR message capable per TID bitmask. */ 1832 uchar max_dvc_qng; /* maximum number of tagged commands per device */ 1833 ushort start_motor; /* start motor command allowed */ 1834 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */ 1835 uchar chip_no; /* should be assigned by caller */ 1836 uchar max_host_qng; /* maximum number of Q'ed command allowed */ 1837 ushort no_scam; /* scam_tolerant of EEPROM */ 1838 struct asc_board *drv_ptr; /* driver pointer to private structure */ 1839 uchar chip_scsi_id; /* chip SCSI target ID */ 1840 uchar chip_type; 1841 uchar bist_err_code; 1842 ADV_CARR_T *carrier; 1843 ADV_CARR_T *carr_freelist; /* Carrier free list. */ 1844 dma_addr_t carrier_addr; 1845 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */ 1846 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */ 1847 ushort carr_pending_cnt; /* Count of pending carriers. */ 1848 /* 1849 * Note: The following fields will not be used after initialization. The 1850 * driver may discard the buffer after initialization is done. 1851 */ 1852 ADV_DVC_CFG *cfg; /* temporary configuration structure */ 1853 } ADV_DVC_VAR; 1854 1855 /* 1856 * Microcode idle loop commands 1857 */ 1858 #define IDLE_CMD_COMPLETED 0 1859 #define IDLE_CMD_STOP_CHIP 0x0001 1860 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 1861 #define IDLE_CMD_SEND_INT 0x0004 1862 #define IDLE_CMD_ABORT 0x0008 1863 #define IDLE_CMD_DEVICE_RESET 0x0010 1864 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ 1865 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ 1866 #define IDLE_CMD_SCSIREQ 0x0080 1867 1868 #define IDLE_CMD_STATUS_SUCCESS 0x0001 1869 #define IDLE_CMD_STATUS_FAILURE 0x0002 1870 1871 /* 1872 * AdvSendIdleCmd() flag definitions. 1873 */ 1874 #define ADV_NOWAIT 0x01 1875 1876 /* 1877 * Wait loop time out values. 1878 */ 1879 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ 1880 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ 1881 #define SCSI_MAX_RETRY 10 /* retry count */ 1882 1883 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 1884 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ 1885 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ 1886 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */ 1887 1888 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ 1889 1890 /* Read byte from a register. */ 1891 #define AdvReadByteRegister(iop_base, reg_off) \ 1892 (ADV_MEM_READB((iop_base) + (reg_off))) 1893 1894 /* Write byte to a register. */ 1895 #define AdvWriteByteRegister(iop_base, reg_off, byte) \ 1896 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte))) 1897 1898 /* Read word (2 bytes) from a register. */ 1899 #define AdvReadWordRegister(iop_base, reg_off) \ 1900 (ADV_MEM_READW((iop_base) + (reg_off))) 1901 1902 /* Write word (2 bytes) to a register. */ 1903 #define AdvWriteWordRegister(iop_base, reg_off, word) \ 1904 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word))) 1905 1906 /* Write dword (4 bytes) to a register. */ 1907 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \ 1908 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword))) 1909 1910 /* Read byte from LRAM. */ 1911 #define AdvReadByteLram(iop_base, addr, byte) \ 1912 do { \ 1913 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ 1914 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \ 1915 } while (0) 1916 1917 /* Write byte to LRAM. */ 1918 #define AdvWriteByteLram(iop_base, addr, byte) \ 1919 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1920 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte))) 1921 1922 /* Read word (2 bytes) from LRAM. */ 1923 #define AdvReadWordLram(iop_base, addr, word) \ 1924 do { \ 1925 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ 1926 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \ 1927 } while (0) 1928 1929 /* Write word (2 bytes) to LRAM. */ 1930 #define AdvWriteWordLram(iop_base, addr, word) \ 1931 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1932 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) 1933 1934 /* Write little-endian double word (4 bytes) to LRAM */ 1935 /* Because of unspecified C language ordering don't use auto-increment. */ 1936 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \ 1937 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1938 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ 1939 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \ 1940 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \ 1941 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ 1942 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF))))) 1943 1944 /* Read word (2 bytes) from LRAM assuming that the address is already set. */ 1945 #define AdvReadWordAutoIncLram(iop_base) \ 1946 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)) 1947 1948 /* Write word (2 bytes) to LRAM assuming that the address is already set. */ 1949 #define AdvWriteWordAutoIncLram(iop_base, word) \ 1950 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) 1951 1952 /* 1953 * Define macro to check for Condor signature. 1954 * 1955 * Evaluate to ADV_TRUE if a Condor chip is found the specified port 1956 * address 'iop_base'. Otherwise evalue to ADV_FALSE. 1957 */ 1958 #define AdvFindSignature(iop_base) \ 1959 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \ 1960 ADV_CHIP_ID_BYTE) && \ 1961 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \ 1962 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE) 1963 1964 /* 1965 * Define macro to Return the version number of the chip at 'iop_base'. 1966 * 1967 * The second parameter 'bus_type' is currently unused. 1968 */ 1969 #define AdvGetChipVersion(iop_base, bus_type) \ 1970 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV) 1971 1972 /* 1973 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must 1974 * match the ADV_SCSI_REQ_Q 'srb_tag' field. 1975 * 1976 * If the request has not yet been sent to the device it will simply be 1977 * aborted from RISC memory. If the request is disconnected it will be 1978 * aborted on reselection by sending an Abort Message to the target ID. 1979 * 1980 * Return value: 1981 * ADV_TRUE(1) - Queue was successfully aborted. 1982 * ADV_FALSE(0) - Queue was not found on the active queue list. 1983 */ 1984 #define AdvAbortQueue(asc_dvc, srb_tag) \ 1985 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \ 1986 (ADV_DCNT) (srb_tag)) 1987 1988 /* 1989 * Send a Bus Device Reset Message to the specified target ID. 1990 * 1991 * All outstanding commands will be purged if sending the 1992 * Bus Device Reset Message is successful. 1993 * 1994 * Return Value: 1995 * ADV_TRUE(1) - All requests on the target are purged. 1996 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 1997 * are not purged. 1998 */ 1999 #define AdvResetDevice(asc_dvc, target_id) \ 2000 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \ 2001 (ADV_DCNT) (target_id)) 2002 2003 /* 2004 * SCSI Wide Type definition. 2005 */ 2006 #define ADV_SCSI_BIT_ID_TYPE ushort 2007 2008 /* 2009 * AdvInitScsiTarget() 'cntl_flag' options. 2010 */ 2011 #define ADV_SCAN_LUN 0x01 2012 #define ADV_CAPINFO_NOLUN 0x02 2013 2014 /* 2015 * Convert target id to target id bit mask. 2016 */ 2017 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID)) 2018 2019 /* 2020 * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values. 2021 */ 2022 2023 #define QD_NO_STATUS 0x00 /* Request not completed yet. */ 2024 #define QD_NO_ERROR 0x01 2025 #define QD_ABORTED_BY_HOST 0x02 2026 #define QD_WITH_ERROR 0x04 2027 2028 #define QHSTA_NO_ERROR 0x00 2029 #define QHSTA_M_SEL_TIMEOUT 0x11 2030 #define QHSTA_M_DATA_OVER_RUN 0x12 2031 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 2032 #define QHSTA_M_QUEUE_ABORTED 0x15 2033 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 2034 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 2035 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 2036 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 2037 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 2038 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 2039 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 2040 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 2041 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 2042 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 2043 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 2044 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ 2045 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ 2046 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ 2047 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ 2048 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ 2049 #define QHSTA_M_WTM_TIMEOUT 0x41 2050 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 2051 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 2052 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 2053 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 2054 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ 2055 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ 2056 2057 /* Return the address that is aligned at the next doubleword >= to 'addr'. */ 2058 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F) 2059 2060 /* 2061 * Total contiguous memory needed for driver SG blocks. 2062 * 2063 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum 2064 * number of scatter-gather elements the driver supports in a 2065 * single request. 2066 */ 2067 2068 #define ADV_SG_LIST_MAX_BYTE_SIZE \ 2069 (sizeof(ADV_SG_BLOCK) * \ 2070 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)) 2071 2072 /* struct asc_board flags */ 2073 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */ 2074 2075 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0) 2076 2077 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */ 2078 2079 #define ASC_INFO_SIZE 128 /* advansys_info() line size */ 2080 2081 /* Asc Library return codes */ 2082 #define ASC_TRUE 1 2083 #define ASC_FALSE 0 2084 #define ASC_NOERROR 1 2085 #define ASC_BUSY 0 2086 #define ASC_ERROR (-1) 2087 2088 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1) 2089 #ifndef ADVANSYS_STATS 2090 #define ASC_STATS_ADD(shost, counter, count) 2091 #else /* ADVANSYS_STATS */ 2092 #define ASC_STATS_ADD(shost, counter, count) \ 2093 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count)) 2094 #endif /* ADVANSYS_STATS */ 2095 2096 /* If the result wraps when calculating tenths, return 0. */ 2097 #define ASC_TENTHS(num, den) \ 2098 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \ 2099 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den))))) 2100 2101 /* 2102 * Display a message to the console. 2103 */ 2104 #define ASC_PRINT(s) \ 2105 { \ 2106 printk("advansys: "); \ 2107 printk(s); \ 2108 } 2109 2110 #define ASC_PRINT1(s, a1) \ 2111 { \ 2112 printk("advansys: "); \ 2113 printk((s), (a1)); \ 2114 } 2115 2116 #define ASC_PRINT2(s, a1, a2) \ 2117 { \ 2118 printk("advansys: "); \ 2119 printk((s), (a1), (a2)); \ 2120 } 2121 2122 #define ASC_PRINT3(s, a1, a2, a3) \ 2123 { \ 2124 printk("advansys: "); \ 2125 printk((s), (a1), (a2), (a3)); \ 2126 } 2127 2128 #define ASC_PRINT4(s, a1, a2, a3, a4) \ 2129 { \ 2130 printk("advansys: "); \ 2131 printk((s), (a1), (a2), (a3), (a4)); \ 2132 } 2133 2134 #ifndef ADVANSYS_DEBUG 2135 2136 #define ASC_DBG(lvl, s...) 2137 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) 2138 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) 2139 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) 2140 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) 2141 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) 2142 #define ASC_DBG_PRT_HEX(lvl, name, start, length) 2143 #define ASC_DBG_PRT_CDB(lvl, cdb, len) 2144 #define ASC_DBG_PRT_SENSE(lvl, sense, len) 2145 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) 2146 2147 #else /* ADVANSYS_DEBUG */ 2148 2149 /* 2150 * Debugging Message Levels: 2151 * 0: Errors Only 2152 * 1: High-Level Tracing 2153 * 2-N: Verbose Tracing 2154 */ 2155 2156 #define ASC_DBG(lvl, format, arg...) { \ 2157 if (asc_dbglvl >= (lvl)) \ 2158 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \ 2159 __func__ , ## arg); \ 2160 } 2161 2162 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \ 2163 { \ 2164 if (asc_dbglvl >= (lvl)) { \ 2165 asc_prt_scsi_host(s); \ 2166 } \ 2167 } 2168 2169 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \ 2170 { \ 2171 if (asc_dbglvl >= (lvl)) { \ 2172 asc_prt_asc_scsi_q(scsiqp); \ 2173 } \ 2174 } 2175 2176 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \ 2177 { \ 2178 if (asc_dbglvl >= (lvl)) { \ 2179 asc_prt_asc_qdone_info(qdone); \ 2180 } \ 2181 } 2182 2183 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \ 2184 { \ 2185 if (asc_dbglvl >= (lvl)) { \ 2186 asc_prt_adv_scsi_req_q(scsiqp); \ 2187 } \ 2188 } 2189 2190 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \ 2191 { \ 2192 if (asc_dbglvl >= (lvl)) { \ 2193 asc_prt_hex((name), (start), (length)); \ 2194 } \ 2195 } 2196 2197 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \ 2198 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len)); 2199 2200 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \ 2201 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len)); 2202 2203 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \ 2204 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len)); 2205 #endif /* ADVANSYS_DEBUG */ 2206 2207 #ifdef ADVANSYS_STATS 2208 2209 /* Per board statistics structure */ 2210 struct asc_stats { 2211 /* Driver Entrypoint Statistics */ 2212 unsigned int queuecommand; /* # calls to advansys_queuecommand() */ 2213 unsigned int reset; /* # calls to advansys_eh_bus_reset() */ 2214 unsigned int biosparam; /* # calls to advansys_biosparam() */ 2215 unsigned int interrupt; /* # advansys_interrupt() calls */ 2216 unsigned int callback; /* # calls to asc/adv_isr_callback() */ 2217 unsigned int done; /* # calls to request's scsi_done function */ 2218 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */ 2219 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */ 2220 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */ 2221 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */ 2222 unsigned int exe_noerror; /* # ASC_NOERROR returns. */ 2223 unsigned int exe_busy; /* # ASC_BUSY returns. */ 2224 unsigned int exe_error; /* # ASC_ERROR returns. */ 2225 unsigned int exe_unknown; /* # unknown returns. */ 2226 /* Data Transfer Statistics */ 2227 unsigned int xfer_cnt; /* # I/O requests received */ 2228 unsigned int xfer_elem; /* # scatter-gather elements */ 2229 unsigned int xfer_sect; /* # 512-byte blocks */ 2230 }; 2231 #endif /* ADVANSYS_STATS */ 2232 2233 /* 2234 * Structure allocated for each board. 2235 * 2236 * This structure is allocated by scsi_host_alloc() at the end 2237 * of the 'Scsi_Host' structure starting at the 'hostdata' 2238 * field. It is guaranteed to be allocated from DMA-able memory. 2239 */ 2240 struct asc_board { 2241 struct device *dev; 2242 struct Scsi_Host *shost; 2243 uint flags; /* Board flags */ 2244 unsigned int irq; 2245 union { 2246 ASC_DVC_VAR asc_dvc_var; /* Narrow board */ 2247 ADV_DVC_VAR adv_dvc_var; /* Wide board */ 2248 } dvc_var; 2249 union { 2250 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */ 2251 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */ 2252 } dvc_cfg; 2253 ushort asc_n_io_port; /* Number I/O ports. */ 2254 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */ 2255 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */ 2256 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */ 2257 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */ 2258 union { 2259 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */ 2260 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */ 2261 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */ 2262 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */ 2263 } eep_config; 2264 /* /proc/scsi/advansys/[0...] */ 2265 #ifdef ADVANSYS_STATS 2266 struct asc_stats asc_stats; /* Board statistics */ 2267 #endif /* ADVANSYS_STATS */ 2268 /* 2269 * The following fields are used only for Narrow Boards. 2270 */ 2271 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */ 2272 /* 2273 * The following fields are used only for Wide Boards. 2274 */ 2275 void __iomem *ioremap_addr; /* I/O Memory remap address. */ 2276 ushort ioport; /* I/O Port address. */ 2277 adv_req_t *adv_reqp; /* Request structures. */ 2278 dma_addr_t adv_reqp_addr; 2279 size_t adv_reqp_size; 2280 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */ 2281 ushort bios_signature; /* BIOS Signature. */ 2282 ushort bios_version; /* BIOS Version. */ 2283 ushort bios_codeseg; /* BIOS Code Segment. */ 2284 ushort bios_codelen; /* BIOS Code Segment Length. */ 2285 }; 2286 2287 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \ 2288 dvc_var.asc_dvc_var) 2289 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \ 2290 dvc_var.adv_dvc_var) 2291 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev) 2292 2293 #ifdef ADVANSYS_DEBUG 2294 static int asc_dbglvl = 3; 2295 2296 /* 2297 * asc_prt_asc_dvc_var() 2298 */ 2299 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h) 2300 { 2301 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h); 2302 2303 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl " 2304 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl); 2305 2306 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type, 2307 (unsigned)h->init_sdtr); 2308 2309 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, " 2310 "chip_no 0x%x,\n", (unsigned)h->sdtr_done, 2311 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready, 2312 (unsigned)h->chip_no); 2313 2314 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait " 2315 "%u,\n", (unsigned)h->queue_full_or_busy, 2316 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); 2317 2318 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, " 2319 "in_critical_cnt %u,\n", (unsigned)h->is_in_int, 2320 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng, 2321 (unsigned)h->in_critical_cnt); 2322 2323 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, " 2324 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage, 2325 (unsigned)h->init_state, (unsigned)h->no_scam, 2326 (unsigned)h->pci_fix_asyn_xfer); 2327 2328 printk(" cfg 0x%lx\n", (ulong)h->cfg); 2329 } 2330 2331 /* 2332 * asc_prt_asc_dvc_cfg() 2333 */ 2334 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h) 2335 { 2336 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h); 2337 2338 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n", 2339 h->can_tagged_qng, h->cmd_qng_enabled); 2340 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n", 2341 h->disc_enable, h->sdtr_enable); 2342 2343 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, " 2344 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed, 2345 h->isa_dma_channel, h->chip_version); 2346 2347 printk(" mcode_date 0x%x, mcode_version %d\n", 2348 h->mcode_date, h->mcode_version); 2349 } 2350 2351 /* 2352 * asc_prt_adv_dvc_var() 2353 * 2354 * Display an ADV_DVC_VAR structure. 2355 */ 2356 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h) 2357 { 2358 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h); 2359 2360 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n", 2361 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able); 2362 2363 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n", 2364 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able); 2365 2366 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n", 2367 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); 2368 2369 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n", 2370 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng, 2371 h->carr_freelist); 2372 2373 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp); 2374 2375 printk(" no_scam 0x%x, tagqng_able 0x%x\n", 2376 (unsigned)h->no_scam, (unsigned)h->tagqng_able); 2377 2378 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n", 2379 (unsigned)h->chip_scsi_id, (ulong)h->cfg); 2380 } 2381 2382 /* 2383 * asc_prt_adv_dvc_cfg() 2384 * 2385 * Display an ADV_DVC_CFG structure. 2386 */ 2387 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h) 2388 { 2389 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h); 2390 2391 printk(" disc_enable 0x%x, termination 0x%x\n", 2392 h->disc_enable, h->termination); 2393 2394 printk(" chip_version 0x%x, mcode_date 0x%x\n", 2395 h->chip_version, h->mcode_date); 2396 2397 printk(" mcode_version 0x%x, control_flag 0x%x\n", 2398 h->mcode_version, h->control_flag); 2399 } 2400 2401 /* 2402 * asc_prt_scsi_host() 2403 */ 2404 static void asc_prt_scsi_host(struct Scsi_Host *s) 2405 { 2406 struct asc_board *boardp = shost_priv(s); 2407 2408 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev)); 2409 printk(" host_busy %d, host_no %d,\n", 2410 scsi_host_busy(s), s->host_no); 2411 2412 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n", 2413 (ulong)s->base, (ulong)s->io_port, boardp->irq); 2414 2415 printk(" dma_channel %d, this_id %d, can_queue %d,\n", 2416 s->dma_channel, s->this_id, s->can_queue); 2417 2418 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n", 2419 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma); 2420 2421 if (ASC_NARROW_BOARD(boardp)) { 2422 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var); 2423 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg); 2424 } else { 2425 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var); 2426 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg); 2427 } 2428 } 2429 2430 /* 2431 * asc_prt_hex() 2432 * 2433 * Print hexadecimal output in 4 byte groupings 32 bytes 2434 * or 8 double-words per line. 2435 */ 2436 static void asc_prt_hex(char *f, uchar *s, int l) 2437 { 2438 int i; 2439 int j; 2440 int k; 2441 int m; 2442 2443 printk("%s: (%d bytes)\n", f, l); 2444 2445 for (i = 0; i < l; i += 32) { 2446 2447 /* Display a maximum of 8 double-words per line. */ 2448 if ((k = (l - i) / 4) >= 8) { 2449 k = 8; 2450 m = 0; 2451 } else { 2452 m = (l - i) % 4; 2453 } 2454 2455 for (j = 0; j < k; j++) { 2456 printk(" %2.2X%2.2X%2.2X%2.2X", 2457 (unsigned)s[i + (j * 4)], 2458 (unsigned)s[i + (j * 4) + 1], 2459 (unsigned)s[i + (j * 4) + 2], 2460 (unsigned)s[i + (j * 4) + 3]); 2461 } 2462 2463 switch (m) { 2464 case 0: 2465 default: 2466 break; 2467 case 1: 2468 printk(" %2.2X", (unsigned)s[i + (j * 4)]); 2469 break; 2470 case 2: 2471 printk(" %2.2X%2.2X", 2472 (unsigned)s[i + (j * 4)], 2473 (unsigned)s[i + (j * 4) + 1]); 2474 break; 2475 case 3: 2476 printk(" %2.2X%2.2X%2.2X", 2477 (unsigned)s[i + (j * 4) + 1], 2478 (unsigned)s[i + (j * 4) + 2], 2479 (unsigned)s[i + (j * 4) + 3]); 2480 break; 2481 } 2482 2483 printk("\n"); 2484 } 2485 } 2486 2487 /* 2488 * asc_prt_asc_scsi_q() 2489 */ 2490 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q) 2491 { 2492 ASC_SG_HEAD *sgp; 2493 int i; 2494 2495 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q); 2496 2497 printk 2498 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n", 2499 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag, 2500 q->q2.tag_code); 2501 2502 printk 2503 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", 2504 (ulong)le32_to_cpu(q->q1.data_addr), 2505 (ulong)le32_to_cpu(q->q1.data_cnt), 2506 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len); 2507 2508 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n", 2509 (ulong)q->cdbptr, q->q2.cdb_len, 2510 (ulong)q->sg_head, q->q1.sg_queue_cnt); 2511 2512 if (q->sg_head) { 2513 sgp = q->sg_head; 2514 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp); 2515 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, 2516 sgp->queue_cnt); 2517 for (i = 0; i < sgp->entry_cnt; i++) { 2518 printk(" [%u]: addr 0x%lx, bytes %lu\n", 2519 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr), 2520 (ulong)le32_to_cpu(sgp->sg_list[i].bytes)); 2521 } 2522 2523 } 2524 } 2525 2526 /* 2527 * asc_prt_asc_qdone_info() 2528 */ 2529 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q) 2530 { 2531 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q); 2532 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n", 2533 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len, 2534 q->d2.tag_code); 2535 printk 2536 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n", 2537 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg); 2538 } 2539 2540 /* 2541 * asc_prt_adv_sgblock() 2542 * 2543 * Display an ADV_SG_BLOCK structure. 2544 */ 2545 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b) 2546 { 2547 int i; 2548 2549 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n", 2550 (ulong)b, sgblockno); 2551 printk(" sg_cnt %u, sg_ptr 0x%x\n", 2552 b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr)); 2553 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK); 2554 if (b->sg_ptr != 0) 2555 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK); 2556 for (i = 0; i < b->sg_cnt; i++) { 2557 printk(" [%u]: sg_addr 0x%x, sg_count 0x%x\n", 2558 i, (u32)le32_to_cpu(b->sg_list[i].sg_addr), 2559 (u32)le32_to_cpu(b->sg_list[i].sg_count)); 2560 } 2561 } 2562 2563 /* 2564 * asc_prt_adv_scsi_req_q() 2565 * 2566 * Display an ADV_SCSI_REQ_Q structure. 2567 */ 2568 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q) 2569 { 2570 int sg_blk_cnt; 2571 struct adv_sg_block *sg_ptr; 2572 adv_sgblk_t *sgblkp; 2573 2574 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q); 2575 2576 printk(" target_id %u, target_lun %u, srb_tag 0x%x\n", 2577 q->target_id, q->target_lun, q->srb_tag); 2578 2579 printk(" cntl 0x%x, data_addr 0x%lx\n", 2580 q->cntl, (ulong)le32_to_cpu(q->data_addr)); 2581 2582 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", 2583 (ulong)le32_to_cpu(q->data_cnt), 2584 (ulong)le32_to_cpu(q->sense_addr), q->sense_len); 2585 2586 printk 2587 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n", 2588 q->cdb_len, q->done_status, q->host_status, q->scsi_status); 2589 2590 printk(" sg_working_ix 0x%x, target_cmd %u\n", 2591 q->sg_working_ix, q->target_cmd); 2592 2593 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n", 2594 (ulong)le32_to_cpu(q->scsiq_rptr), 2595 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr); 2596 2597 /* Display the request's ADV_SG_BLOCK structures. */ 2598 if (q->sg_list_ptr != NULL) { 2599 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block); 2600 sg_blk_cnt = 0; 2601 while (sgblkp) { 2602 sg_ptr = &sgblkp->sg_block; 2603 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr); 2604 if (sg_ptr->sg_ptr == 0) { 2605 break; 2606 } 2607 sgblkp = sgblkp->next_sgblkp; 2608 sg_blk_cnt++; 2609 } 2610 } 2611 } 2612 #endif /* ADVANSYS_DEBUG */ 2613 2614 /* 2615 * advansys_info() 2616 * 2617 * Return suitable for printing on the console with the argument 2618 * adapter's configuration information. 2619 * 2620 * Note: The information line should not exceed ASC_INFO_SIZE bytes, 2621 * otherwise the static 'info' array will be overrun. 2622 */ 2623 static const char *advansys_info(struct Scsi_Host *shost) 2624 { 2625 static char info[ASC_INFO_SIZE]; 2626 struct asc_board *boardp = shost_priv(shost); 2627 ASC_DVC_VAR *asc_dvc_varp; 2628 ADV_DVC_VAR *adv_dvc_varp; 2629 char *busname; 2630 char *widename = NULL; 2631 2632 if (ASC_NARROW_BOARD(boardp)) { 2633 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 2634 ASC_DBG(1, "begin\n"); 2635 if (asc_dvc_varp->bus_type & ASC_IS_ISA) { 2636 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) == 2637 ASC_IS_ISAPNP) { 2638 busname = "ISA PnP"; 2639 } else { 2640 busname = "ISA"; 2641 } 2642 sprintf(info, 2643 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X", 2644 ASC_VERSION, busname, 2645 (ulong)shost->io_port, 2646 (ulong)shost->io_port + ASC_IOADR_GAP - 1, 2647 boardp->irq, shost->dma_channel); 2648 } else { 2649 if (asc_dvc_varp->bus_type & ASC_IS_VL) { 2650 busname = "VL"; 2651 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) { 2652 busname = "EISA"; 2653 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) { 2654 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA) 2655 == ASC_IS_PCI_ULTRA) { 2656 busname = "PCI Ultra"; 2657 } else { 2658 busname = "PCI"; 2659 } 2660 } else { 2661 busname = "?"; 2662 shost_printk(KERN_ERR, shost, "unknown bus " 2663 "type %d\n", asc_dvc_varp->bus_type); 2664 } 2665 sprintf(info, 2666 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X", 2667 ASC_VERSION, busname, (ulong)shost->io_port, 2668 (ulong)shost->io_port + ASC_IOADR_GAP - 1, 2669 boardp->irq); 2670 } 2671 } else { 2672 /* 2673 * Wide Adapter Information 2674 * 2675 * Memory-mapped I/O is used instead of I/O space to access 2676 * the adapter, but display the I/O Port range. The Memory 2677 * I/O address is displayed through the driver /proc file. 2678 */ 2679 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 2680 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2681 widename = "Ultra-Wide"; 2682 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2683 widename = "Ultra2-Wide"; 2684 } else { 2685 widename = "Ultra3-Wide"; 2686 } 2687 sprintf(info, 2688 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X", 2689 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base, 2690 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq); 2691 } 2692 BUG_ON(strlen(info) >= ASC_INFO_SIZE); 2693 ASC_DBG(1, "end\n"); 2694 return info; 2695 } 2696 2697 #ifdef CONFIG_PROC_FS 2698 2699 /* 2700 * asc_prt_board_devices() 2701 * 2702 * Print driver information for devices attached to the board. 2703 */ 2704 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost) 2705 { 2706 struct asc_board *boardp = shost_priv(shost); 2707 int chip_scsi_id; 2708 int i; 2709 2710 seq_printf(m, 2711 "\nDevice Information for AdvanSys SCSI Host %d:\n", 2712 shost->host_no); 2713 2714 if (ASC_NARROW_BOARD(boardp)) { 2715 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id; 2716 } else { 2717 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id; 2718 } 2719 2720 seq_puts(m, "Target IDs Detected:"); 2721 for (i = 0; i <= ADV_MAX_TID; i++) { 2722 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) 2723 seq_printf(m, " %X,", i); 2724 } 2725 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id); 2726 } 2727 2728 /* 2729 * Display Wide Board BIOS Information. 2730 */ 2731 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost) 2732 { 2733 struct asc_board *boardp = shost_priv(shost); 2734 ushort major, minor, letter; 2735 2736 seq_puts(m, "\nROM BIOS Version: "); 2737 2738 /* 2739 * If the BIOS saved a valid signature, then fill in 2740 * the BIOS code segment base address. 2741 */ 2742 if (boardp->bios_signature != 0x55AA) { 2743 seq_puts(m, "Disabled or Pre-3.1\n" 2744 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n" 2745 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n"); 2746 } else { 2747 major = (boardp->bios_version >> 12) & 0xF; 2748 minor = (boardp->bios_version >> 8) & 0xF; 2749 letter = (boardp->bios_version & 0xFF); 2750 2751 seq_printf(m, "%d.%d%c\n", 2752 major, minor, 2753 letter >= 26 ? '?' : letter + 'A'); 2754 /* 2755 * Current available ROM BIOS release is 3.1I for UW 2756 * and 3.2I for U2W. This code doesn't differentiate 2757 * UW and U2W boards. 2758 */ 2759 if (major < 3 || (major <= 3 && minor < 1) || 2760 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) { 2761 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n" 2762 "ftp://ftp.connectcom.net/pub\n"); 2763 } 2764 } 2765 } 2766 2767 /* 2768 * Add serial number to information bar if signature AAh 2769 * is found in at bit 15-9 (7 bits) of word 1. 2770 * 2771 * Serial Number consists fo 12 alpha-numeric digits. 2772 * 2773 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits) 2774 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits) 2775 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits) 2776 * 5 - Product revision (A-J) Word0: " " 2777 * 2778 * Signature Word1: 15-9 (7 bits) 2779 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit) 2780 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits) 2781 * 2782 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits) 2783 * 2784 * Note 1: Only production cards will have a serial number. 2785 * 2786 * Note 2: Signature is most significant 7 bits (0xFE). 2787 * 2788 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE. 2789 */ 2790 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp) 2791 { 2792 ushort w, num; 2793 2794 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) { 2795 return ASC_FALSE; 2796 } else { 2797 /* 2798 * First word - 6 digits. 2799 */ 2800 w = serialnum[0]; 2801 2802 /* Product type - 1st digit. */ 2803 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') { 2804 /* Product type is P=Prototype */ 2805 *cp += 0x8; 2806 } 2807 cp++; 2808 2809 /* Manufacturing location - 2nd digit. */ 2810 *cp++ = 'A' + ((w & 0x1C00) >> 10); 2811 2812 /* Product ID - 3rd, 4th digits. */ 2813 num = w & 0x3FF; 2814 *cp++ = '0' + (num / 100); 2815 num %= 100; 2816 *cp++ = '0' + (num / 10); 2817 2818 /* Product revision - 5th digit. */ 2819 *cp++ = 'A' + (num % 10); 2820 2821 /* 2822 * Second word 2823 */ 2824 w = serialnum[1]; 2825 2826 /* 2827 * Year - 6th digit. 2828 * 2829 * If bit 15 of third word is set, then the 2830 * last digit of the year is greater than 7. 2831 */ 2832 if (serialnum[2] & 0x8000) { 2833 *cp++ = '8' + ((w & 0x1C0) >> 6); 2834 } else { 2835 *cp++ = '0' + ((w & 0x1C0) >> 6); 2836 } 2837 2838 /* Week of year - 7th, 8th digits. */ 2839 num = w & 0x003F; 2840 *cp++ = '0' + num / 10; 2841 num %= 10; 2842 *cp++ = '0' + num; 2843 2844 /* 2845 * Third word 2846 */ 2847 w = serialnum[2] & 0x7FFF; 2848 2849 /* Serial number - 9th digit. */ 2850 *cp++ = 'A' + (w / 1000); 2851 2852 /* 10th, 11th, 12th digits. */ 2853 num = w % 1000; 2854 *cp++ = '0' + num / 100; 2855 num %= 100; 2856 *cp++ = '0' + num / 10; 2857 num %= 10; 2858 *cp++ = '0' + num; 2859 2860 *cp = '\0'; /* Null Terminate the string. */ 2861 return ASC_TRUE; 2862 } 2863 } 2864 2865 /* 2866 * asc_prt_asc_board_eeprom() 2867 * 2868 * Print board EEPROM configuration. 2869 */ 2870 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost) 2871 { 2872 struct asc_board *boardp = shost_priv(shost); 2873 ASCEEP_CONFIG *ep; 2874 int i; 2875 uchar serialstr[13]; 2876 #ifdef CONFIG_ISA 2877 ASC_DVC_VAR *asc_dvc_varp; 2878 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 }; 2879 2880 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 2881 #endif /* CONFIG_ISA */ 2882 ep = &boardp->eep_config.asc_eep; 2883 2884 seq_printf(m, 2885 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", 2886 shost->host_no); 2887 2888 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr) 2889 == ASC_TRUE) 2890 seq_printf(m, " Serial Number: %s\n", serialstr); 2891 else if (ep->adapter_info[5] == 0xBB) 2892 seq_puts(m, 2893 " Default Settings Used for EEPROM-less Adapter.\n"); 2894 else 2895 seq_puts(m, " Serial Number Signature Not Present.\n"); 2896 2897 seq_printf(m, 2898 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2899 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, 2900 ep->max_tag_qng); 2901 2902 seq_printf(m, 2903 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam); 2904 2905 seq_puts(m, " Target ID: "); 2906 for (i = 0; i <= ASC_MAX_TID; i++) 2907 seq_printf(m, " %d", i); 2908 2909 seq_puts(m, "\n Disconnects: "); 2910 for (i = 0; i <= ASC_MAX_TID; i++) 2911 seq_printf(m, " %c", 2912 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2913 2914 seq_puts(m, "\n Command Queuing: "); 2915 for (i = 0; i <= ASC_MAX_TID; i++) 2916 seq_printf(m, " %c", 2917 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2918 2919 seq_puts(m, "\n Start Motor: "); 2920 for (i = 0; i <= ASC_MAX_TID; i++) 2921 seq_printf(m, " %c", 2922 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2923 2924 seq_puts(m, "\n Synchronous Transfer:"); 2925 for (i = 0; i <= ASC_MAX_TID; i++) 2926 seq_printf(m, " %c", 2927 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2928 seq_putc(m, '\n'); 2929 2930 #ifdef CONFIG_ISA 2931 if (asc_dvc_varp->bus_type & ASC_IS_ISA) { 2932 seq_printf(m, 2933 " Host ISA DMA speed: %d MB/S\n", 2934 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]); 2935 } 2936 #endif /* CONFIG_ISA */ 2937 } 2938 2939 /* 2940 * asc_prt_adv_board_eeprom() 2941 * 2942 * Print board EEPROM configuration. 2943 */ 2944 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost) 2945 { 2946 struct asc_board *boardp = shost_priv(shost); 2947 ADV_DVC_VAR *adv_dvc_varp; 2948 int i; 2949 char *termstr; 2950 uchar serialstr[13]; 2951 ADVEEP_3550_CONFIG *ep_3550 = NULL; 2952 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL; 2953 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL; 2954 ushort word; 2955 ushort *wordp; 2956 ushort sdtr_speed = 0; 2957 2958 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 2959 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2960 ep_3550 = &boardp->eep_config.adv_3550_eep; 2961 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2962 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; 2963 } else { 2964 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; 2965 } 2966 2967 seq_printf(m, 2968 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", 2969 shost->host_no); 2970 2971 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2972 wordp = &ep_3550->serial_number_word1; 2973 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2974 wordp = &ep_38C0800->serial_number_word1; 2975 } else { 2976 wordp = &ep_38C1600->serial_number_word1; 2977 } 2978 2979 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) 2980 seq_printf(m, " Serial Number: %s\n", serialstr); 2981 else 2982 seq_puts(m, " Serial Number Signature Not Present.\n"); 2983 2984 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) 2985 seq_printf(m, 2986 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2987 ep_3550->adapter_scsi_id, 2988 ep_3550->max_host_qng, ep_3550->max_dvc_qng); 2989 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) 2990 seq_printf(m, 2991 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2992 ep_38C0800->adapter_scsi_id, 2993 ep_38C0800->max_host_qng, 2994 ep_38C0800->max_dvc_qng); 2995 else 2996 seq_printf(m, 2997 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2998 ep_38C1600->adapter_scsi_id, 2999 ep_38C1600->max_host_qng, 3000 ep_38C1600->max_dvc_qng); 3001 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3002 word = ep_3550->termination; 3003 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3004 word = ep_38C0800->termination_lvd; 3005 } else { 3006 word = ep_38C1600->termination_lvd; 3007 } 3008 switch (word) { 3009 case 1: 3010 termstr = "Low Off/High Off"; 3011 break; 3012 case 2: 3013 termstr = "Low Off/High On"; 3014 break; 3015 case 3: 3016 termstr = "Low On/High On"; 3017 break; 3018 default: 3019 case 0: 3020 termstr = "Automatic"; 3021 break; 3022 } 3023 3024 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) 3025 seq_printf(m, 3026 " termination: %u (%s), bios_ctrl: 0x%x\n", 3027 ep_3550->termination, termstr, 3028 ep_3550->bios_ctrl); 3029 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) 3030 seq_printf(m, 3031 " termination: %u (%s), bios_ctrl: 0x%x\n", 3032 ep_38C0800->termination_lvd, termstr, 3033 ep_38C0800->bios_ctrl); 3034 else 3035 seq_printf(m, 3036 " termination: %u (%s), bios_ctrl: 0x%x\n", 3037 ep_38C1600->termination_lvd, termstr, 3038 ep_38C1600->bios_ctrl); 3039 3040 seq_puts(m, " Target ID: "); 3041 for (i = 0; i <= ADV_MAX_TID; i++) 3042 seq_printf(m, " %X", i); 3043 seq_putc(m, '\n'); 3044 3045 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3046 word = ep_3550->disc_enable; 3047 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3048 word = ep_38C0800->disc_enable; 3049 } else { 3050 word = ep_38C1600->disc_enable; 3051 } 3052 seq_puts(m, " Disconnects: "); 3053 for (i = 0; i <= ADV_MAX_TID; i++) 3054 seq_printf(m, " %c", 3055 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3056 seq_putc(m, '\n'); 3057 3058 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3059 word = ep_3550->tagqng_able; 3060 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3061 word = ep_38C0800->tagqng_able; 3062 } else { 3063 word = ep_38C1600->tagqng_able; 3064 } 3065 seq_puts(m, " Command Queuing: "); 3066 for (i = 0; i <= ADV_MAX_TID; i++) 3067 seq_printf(m, " %c", 3068 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3069 seq_putc(m, '\n'); 3070 3071 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3072 word = ep_3550->start_motor; 3073 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3074 word = ep_38C0800->start_motor; 3075 } else { 3076 word = ep_38C1600->start_motor; 3077 } 3078 seq_puts(m, " Start Motor: "); 3079 for (i = 0; i <= ADV_MAX_TID; i++) 3080 seq_printf(m, " %c", 3081 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3082 seq_putc(m, '\n'); 3083 3084 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3085 seq_puts(m, " Synchronous Transfer:"); 3086 for (i = 0; i <= ADV_MAX_TID; i++) 3087 seq_printf(m, " %c", 3088 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 3089 'Y' : 'N'); 3090 seq_putc(m, '\n'); 3091 } 3092 3093 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3094 seq_puts(m, " Ultra Transfer: "); 3095 for (i = 0; i <= ADV_MAX_TID; i++) 3096 seq_printf(m, " %c", 3097 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i)) 3098 ? 'Y' : 'N'); 3099 seq_putc(m, '\n'); 3100 } 3101 3102 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3103 word = ep_3550->wdtr_able; 3104 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3105 word = ep_38C0800->wdtr_able; 3106 } else { 3107 word = ep_38C1600->wdtr_able; 3108 } 3109 seq_puts(m, " Wide Transfer: "); 3110 for (i = 0; i <= ADV_MAX_TID; i++) 3111 seq_printf(m, " %c", 3112 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3113 seq_putc(m, '\n'); 3114 3115 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 || 3116 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) { 3117 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n "); 3118 for (i = 0; i <= ADV_MAX_TID; i++) { 3119 char *speed_str; 3120 3121 if (i == 0) { 3122 sdtr_speed = adv_dvc_varp->sdtr_speed1; 3123 } else if (i == 4) { 3124 sdtr_speed = adv_dvc_varp->sdtr_speed2; 3125 } else if (i == 8) { 3126 sdtr_speed = adv_dvc_varp->sdtr_speed3; 3127 } else if (i == 12) { 3128 sdtr_speed = adv_dvc_varp->sdtr_speed4; 3129 } 3130 switch (sdtr_speed & ADV_MAX_TID) { 3131 case 0: 3132 speed_str = "Off"; 3133 break; 3134 case 1: 3135 speed_str = " 5"; 3136 break; 3137 case 2: 3138 speed_str = " 10"; 3139 break; 3140 case 3: 3141 speed_str = " 20"; 3142 break; 3143 case 4: 3144 speed_str = " 40"; 3145 break; 3146 case 5: 3147 speed_str = " 80"; 3148 break; 3149 default: 3150 speed_str = "Unk"; 3151 break; 3152 } 3153 seq_printf(m, "%X:%s ", i, speed_str); 3154 if (i == 7) 3155 seq_puts(m, "\n "); 3156 sdtr_speed >>= 4; 3157 } 3158 seq_putc(m, '\n'); 3159 } 3160 } 3161 3162 /* 3163 * asc_prt_driver_conf() 3164 */ 3165 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost) 3166 { 3167 struct asc_board *boardp = shost_priv(shost); 3168 3169 seq_printf(m, 3170 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n", 3171 shost->host_no); 3172 3173 seq_printf(m, 3174 " host_busy %d, max_id %u, max_lun %llu, max_channel %u\n", 3175 scsi_host_busy(shost), shost->max_id, 3176 shost->max_lun, shost->max_channel); 3177 3178 seq_printf(m, 3179 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n", 3180 shost->unique_id, shost->can_queue, shost->this_id, 3181 shost->sg_tablesize, shost->cmd_per_lun); 3182 3183 seq_printf(m, 3184 " unchecked_isa_dma %d\n", 3185 shost->unchecked_isa_dma); 3186 3187 seq_printf(m, 3188 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n", 3189 boardp->flags, shost->last_reset, jiffies, 3190 boardp->asc_n_io_port); 3191 3192 seq_printf(m, " io_port 0x%lx\n", shost->io_port); 3193 } 3194 3195 /* 3196 * asc_prt_asc_board_info() 3197 * 3198 * Print dynamic board configuration information. 3199 */ 3200 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost) 3201 { 3202 struct asc_board *boardp = shost_priv(shost); 3203 int chip_scsi_id; 3204 ASC_DVC_VAR *v; 3205 ASC_DVC_CFG *c; 3206 int i; 3207 int renegotiate = 0; 3208 3209 v = &boardp->dvc_var.asc_dvc_var; 3210 c = &boardp->dvc_cfg.asc_dvc_cfg; 3211 chip_scsi_id = c->chip_scsi_id; 3212 3213 seq_printf(m, 3214 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", 3215 shost->host_no); 3216 3217 seq_printf(m, " chip_version %u, mcode_date 0x%x, " 3218 "mcode_version 0x%x, err_code %u\n", 3219 c->chip_version, c->mcode_date, c->mcode_version, 3220 v->err_code); 3221 3222 /* Current number of commands waiting for the host. */ 3223 seq_printf(m, 3224 " Total Command Pending: %d\n", v->cur_total_qng); 3225 3226 seq_puts(m, " Command Queuing:"); 3227 for (i = 0; i <= ASC_MAX_TID; i++) { 3228 if ((chip_scsi_id == i) || 3229 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3230 continue; 3231 } 3232 seq_printf(m, " %X:%c", 3233 i, 3234 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3235 } 3236 3237 /* Current number of commands waiting for a device. */ 3238 seq_puts(m, "\n Command Queue Pending:"); 3239 for (i = 0; i <= ASC_MAX_TID; i++) { 3240 if ((chip_scsi_id == i) || 3241 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3242 continue; 3243 } 3244 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]); 3245 } 3246 3247 /* Current limit on number of commands that can be sent to a device. */ 3248 seq_puts(m, "\n Command Queue Limit:"); 3249 for (i = 0; i <= ASC_MAX_TID; i++) { 3250 if ((chip_scsi_id == i) || 3251 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3252 continue; 3253 } 3254 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]); 3255 } 3256 3257 /* Indicate whether the device has returned queue full status. */ 3258 seq_puts(m, "\n Command Queue Full:"); 3259 for (i = 0; i <= ASC_MAX_TID; i++) { 3260 if ((chip_scsi_id == i) || 3261 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3262 continue; 3263 } 3264 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) 3265 seq_printf(m, " %X:Y-%d", 3266 i, boardp->queue_full_cnt[i]); 3267 else 3268 seq_printf(m, " %X:N", i); 3269 } 3270 3271 seq_puts(m, "\n Synchronous Transfer:"); 3272 for (i = 0; i <= ASC_MAX_TID; i++) { 3273 if ((chip_scsi_id == i) || 3274 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3275 continue; 3276 } 3277 seq_printf(m, " %X:%c", 3278 i, 3279 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3280 } 3281 seq_putc(m, '\n'); 3282 3283 for (i = 0; i <= ASC_MAX_TID; i++) { 3284 uchar syn_period_ix; 3285 3286 if ((chip_scsi_id == i) || 3287 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || 3288 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) { 3289 continue; 3290 } 3291 3292 seq_printf(m, " %X:", i); 3293 3294 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) { 3295 seq_puts(m, " Asynchronous"); 3296 } else { 3297 syn_period_ix = 3298 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - 3299 1); 3300 3301 seq_printf(m, 3302 " Transfer Period Factor: %d (%d.%d Mhz),", 3303 v->sdtr_period_tbl[syn_period_ix], 3304 250 / v->sdtr_period_tbl[syn_period_ix], 3305 ASC_TENTHS(250, 3306 v->sdtr_period_tbl[syn_period_ix])); 3307 3308 seq_printf(m, " REQ/ACK Offset: %d", 3309 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET); 3310 } 3311 3312 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3313 seq_puts(m, "*\n"); 3314 renegotiate = 1; 3315 } else { 3316 seq_putc(m, '\n'); 3317 } 3318 } 3319 3320 if (renegotiate) { 3321 seq_puts(m, " * = Re-negotiation pending before next command.\n"); 3322 } 3323 } 3324 3325 /* 3326 * asc_prt_adv_board_info() 3327 * 3328 * Print dynamic board configuration information. 3329 */ 3330 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost) 3331 { 3332 struct asc_board *boardp = shost_priv(shost); 3333 int i; 3334 ADV_DVC_VAR *v; 3335 ADV_DVC_CFG *c; 3336 AdvPortAddr iop_base; 3337 ushort chip_scsi_id; 3338 ushort lramword; 3339 uchar lrambyte; 3340 ushort tagqng_able; 3341 ushort sdtr_able, wdtr_able; 3342 ushort wdtr_done, sdtr_done; 3343 ushort period = 0; 3344 int renegotiate = 0; 3345 3346 v = &boardp->dvc_var.adv_dvc_var; 3347 c = &boardp->dvc_cfg.adv_dvc_cfg; 3348 iop_base = v->iop_base; 3349 chip_scsi_id = v->chip_scsi_id; 3350 3351 seq_printf(m, 3352 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", 3353 shost->host_no); 3354 3355 seq_printf(m, 3356 " iop_base 0x%lx, cable_detect: %X, err_code %u\n", 3357 (unsigned long)v->iop_base, 3358 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT, 3359 v->err_code); 3360 3361 seq_printf(m, " chip_version %u, mcode_date 0x%x, " 3362 "mcode_version 0x%x\n", c->chip_version, 3363 c->mcode_date, c->mcode_version); 3364 3365 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 3366 seq_puts(m, " Queuing Enabled:"); 3367 for (i = 0; i <= ADV_MAX_TID; i++) { 3368 if ((chip_scsi_id == i) || 3369 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3370 continue; 3371 } 3372 3373 seq_printf(m, " %X:%c", 3374 i, 3375 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3376 } 3377 3378 seq_puts(m, "\n Queue Limit:"); 3379 for (i = 0; i <= ADV_MAX_TID; i++) { 3380 if ((chip_scsi_id == i) || 3381 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3382 continue; 3383 } 3384 3385 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, 3386 lrambyte); 3387 3388 seq_printf(m, " %X:%d", i, lrambyte); 3389 } 3390 3391 seq_puts(m, "\n Command Pending:"); 3392 for (i = 0; i <= ADV_MAX_TID; i++) { 3393 if ((chip_scsi_id == i) || 3394 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3395 continue; 3396 } 3397 3398 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, 3399 lrambyte); 3400 3401 seq_printf(m, " %X:%d", i, lrambyte); 3402 } 3403 seq_putc(m, '\n'); 3404 3405 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 3406 seq_puts(m, " Wide Enabled:"); 3407 for (i = 0; i <= ADV_MAX_TID; i++) { 3408 if ((chip_scsi_id == i) || 3409 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3410 continue; 3411 } 3412 3413 seq_printf(m, " %X:%c", 3414 i, 3415 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3416 } 3417 seq_putc(m, '\n'); 3418 3419 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done); 3420 seq_puts(m, " Transfer Bit Width:"); 3421 for (i = 0; i <= ADV_MAX_TID; i++) { 3422 if ((chip_scsi_id == i) || 3423 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3424 continue; 3425 } 3426 3427 AdvReadWordLram(iop_base, 3428 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), 3429 lramword); 3430 3431 seq_printf(m, " %X:%d", 3432 i, (lramword & 0x8000) ? 16 : 8); 3433 3434 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) && 3435 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3436 seq_putc(m, '*'); 3437 renegotiate = 1; 3438 } 3439 } 3440 seq_putc(m, '\n'); 3441 3442 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 3443 seq_puts(m, " Synchronous Enabled:"); 3444 for (i = 0; i <= ADV_MAX_TID; i++) { 3445 if ((chip_scsi_id == i) || 3446 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3447 continue; 3448 } 3449 3450 seq_printf(m, " %X:%c", 3451 i, 3452 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3453 } 3454 seq_putc(m, '\n'); 3455 3456 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done); 3457 for (i = 0; i <= ADV_MAX_TID; i++) { 3458 3459 AdvReadWordLram(iop_base, 3460 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), 3461 lramword); 3462 lramword &= ~0x8000; 3463 3464 if ((chip_scsi_id == i) || 3465 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || 3466 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) { 3467 continue; 3468 } 3469 3470 seq_printf(m, " %X:", i); 3471 3472 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */ 3473 seq_puts(m, " Asynchronous"); 3474 } else { 3475 seq_puts(m, " Transfer Period Factor: "); 3476 3477 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */ 3478 seq_puts(m, "9 (80.0 Mhz),"); 3479 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */ 3480 seq_puts(m, "10 (40.0 Mhz),"); 3481 } else { /* 20 Mhz or below. */ 3482 3483 period = (((lramword >> 8) * 25) + 50) / 4; 3484 3485 if (period == 0) { /* Should never happen. */ 3486 seq_printf(m, "%d (? Mhz), ", period); 3487 } else { 3488 seq_printf(m, 3489 "%d (%d.%d Mhz),", 3490 period, 250 / period, 3491 ASC_TENTHS(250, period)); 3492 } 3493 } 3494 3495 seq_printf(m, " REQ/ACK Offset: %d", 3496 lramword & 0x1F); 3497 } 3498 3499 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3500 seq_puts(m, "*\n"); 3501 renegotiate = 1; 3502 } else { 3503 seq_putc(m, '\n'); 3504 } 3505 } 3506 3507 if (renegotiate) { 3508 seq_puts(m, " * = Re-negotiation pending before next command.\n"); 3509 } 3510 } 3511 3512 #ifdef ADVANSYS_STATS 3513 /* 3514 * asc_prt_board_stats() 3515 */ 3516 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost) 3517 { 3518 struct asc_board *boardp = shost_priv(shost); 3519 struct asc_stats *s = &boardp->asc_stats; 3520 3521 seq_printf(m, 3522 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", 3523 shost->host_no); 3524 3525 seq_printf(m, 3526 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n", 3527 s->queuecommand, s->reset, s->biosparam, 3528 s->interrupt); 3529 3530 seq_printf(m, 3531 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n", 3532 s->callback, s->done, s->build_error, 3533 s->adv_build_noreq, s->adv_build_nosg); 3534 3535 seq_printf(m, 3536 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n", 3537 s->exe_noerror, s->exe_busy, s->exe_error, 3538 s->exe_unknown); 3539 3540 /* 3541 * Display data transfer statistics. 3542 */ 3543 if (s->xfer_cnt > 0) { 3544 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ", 3545 s->xfer_cnt, s->xfer_elem); 3546 3547 seq_printf(m, "xfer_bytes %u.%01u kb\n", 3548 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2)); 3549 3550 /* Scatter gather transfer statistics */ 3551 seq_printf(m, " avg_num_elem %u.%01u, ", 3552 s->xfer_elem / s->xfer_cnt, 3553 ASC_TENTHS(s->xfer_elem, s->xfer_cnt)); 3554 3555 seq_printf(m, "avg_elem_size %u.%01u kb, ", 3556 (s->xfer_sect / 2) / s->xfer_elem, 3557 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem)); 3558 3559 seq_printf(m, "avg_xfer_size %u.%01u kb\n", 3560 (s->xfer_sect / 2) / s->xfer_cnt, 3561 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt)); 3562 } 3563 } 3564 #endif /* ADVANSYS_STATS */ 3565 3566 /* 3567 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...} 3568 * 3569 * m: seq_file to print into 3570 * shost: Scsi_Host 3571 * 3572 * Return the number of bytes read from or written to a 3573 * /proc/scsi/advansys/[0...] file. 3574 */ 3575 static int 3576 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost) 3577 { 3578 struct asc_board *boardp = shost_priv(shost); 3579 3580 ASC_DBG(1, "begin\n"); 3581 3582 /* 3583 * User read of /proc/scsi/advansys/[0...] file. 3584 */ 3585 3586 /* 3587 * Get board configuration information. 3588 * 3589 * advansys_info() returns the board string from its own static buffer. 3590 */ 3591 /* Copy board information. */ 3592 seq_printf(m, "%s\n", (char *)advansys_info(shost)); 3593 /* 3594 * Display Wide Board BIOS Information. 3595 */ 3596 if (!ASC_NARROW_BOARD(boardp)) 3597 asc_prt_adv_bios(m, shost); 3598 3599 /* 3600 * Display driver information for each device attached to the board. 3601 */ 3602 asc_prt_board_devices(m, shost); 3603 3604 /* 3605 * Display EEPROM configuration for the board. 3606 */ 3607 if (ASC_NARROW_BOARD(boardp)) 3608 asc_prt_asc_board_eeprom(m, shost); 3609 else 3610 asc_prt_adv_board_eeprom(m, shost); 3611 3612 /* 3613 * Display driver configuration and information for the board. 3614 */ 3615 asc_prt_driver_conf(m, shost); 3616 3617 #ifdef ADVANSYS_STATS 3618 /* 3619 * Display driver statistics for the board. 3620 */ 3621 asc_prt_board_stats(m, shost); 3622 #endif /* ADVANSYS_STATS */ 3623 3624 /* 3625 * Display Asc Library dynamic configuration information 3626 * for the board. 3627 */ 3628 if (ASC_NARROW_BOARD(boardp)) 3629 asc_prt_asc_board_info(m, shost); 3630 else 3631 asc_prt_adv_board_info(m, shost); 3632 return 0; 3633 } 3634 #endif /* CONFIG_PROC_FS */ 3635 3636 static void asc_scsi_done(struct scsi_cmnd *scp) 3637 { 3638 scsi_dma_unmap(scp); 3639 ASC_STATS(scp->device->host, done); 3640 scp->scsi_done(scp); 3641 } 3642 3643 static void AscSetBank(PortAddr iop_base, uchar bank) 3644 { 3645 uchar val; 3646 3647 val = AscGetChipControl(iop_base) & 3648 (~ 3649 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | 3650 CC_CHIP_RESET)); 3651 if (bank == 1) { 3652 val |= CC_BANK_ONE; 3653 } else if (bank == 2) { 3654 val |= CC_DIAG | CC_BANK_ONE; 3655 } else { 3656 val &= ~CC_BANK_ONE; 3657 } 3658 AscSetChipControl(iop_base, val); 3659 } 3660 3661 static void AscSetChipIH(PortAddr iop_base, ushort ins_code) 3662 { 3663 AscSetBank(iop_base, 1); 3664 AscWriteChipIH(iop_base, ins_code); 3665 AscSetBank(iop_base, 0); 3666 } 3667 3668 static int AscStartChip(PortAddr iop_base) 3669 { 3670 AscSetChipControl(iop_base, 0); 3671 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { 3672 return (0); 3673 } 3674 return (1); 3675 } 3676 3677 static bool AscStopChip(PortAddr iop_base) 3678 { 3679 uchar cc_val; 3680 3681 cc_val = 3682 AscGetChipControl(iop_base) & 3683 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG)); 3684 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT)); 3685 AscSetChipIH(iop_base, INS_HALT); 3686 AscSetChipIH(iop_base, INS_RFLAG_WTM); 3687 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) { 3688 return false; 3689 } 3690 return true; 3691 } 3692 3693 static bool AscIsChipHalted(PortAddr iop_base) 3694 { 3695 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { 3696 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) { 3697 return true; 3698 } 3699 } 3700 return false; 3701 } 3702 3703 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc) 3704 { 3705 PortAddr iop_base; 3706 int i = 10; 3707 3708 iop_base = asc_dvc->iop_base; 3709 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) 3710 && (i-- > 0)) { 3711 mdelay(100); 3712 } 3713 AscStopChip(iop_base); 3714 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT); 3715 udelay(60); 3716 AscSetChipIH(iop_base, INS_RFLAG_WTM); 3717 AscSetChipIH(iop_base, INS_HALT); 3718 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT); 3719 AscSetChipControl(iop_base, CC_HALT); 3720 mdelay(200); 3721 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); 3722 AscSetChipStatus(iop_base, 0); 3723 return (AscIsChipHalted(iop_base)); 3724 } 3725 3726 static int AscFindSignature(PortAddr iop_base) 3727 { 3728 ushort sig_word; 3729 3730 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n", 3731 iop_base, AscGetChipSignatureByte(iop_base)); 3732 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) { 3733 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n", 3734 iop_base, AscGetChipSignatureWord(iop_base)); 3735 sig_word = AscGetChipSignatureWord(iop_base); 3736 if ((sig_word == (ushort)ASC_1000_ID0W) || 3737 (sig_word == (ushort)ASC_1000_ID0W_FIX)) { 3738 return (1); 3739 } 3740 } 3741 return (0); 3742 } 3743 3744 static void AscEnableInterrupt(PortAddr iop_base) 3745 { 3746 ushort cfg; 3747 3748 cfg = AscGetChipCfgLsw(iop_base); 3749 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON); 3750 } 3751 3752 static void AscDisableInterrupt(PortAddr iop_base) 3753 { 3754 ushort cfg; 3755 3756 cfg = AscGetChipCfgLsw(iop_base); 3757 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON)); 3758 } 3759 3760 static uchar AscReadLramByte(PortAddr iop_base, ushort addr) 3761 { 3762 unsigned char byte_data; 3763 unsigned short word_data; 3764 3765 if (isodd_word(addr)) { 3766 AscSetChipLramAddr(iop_base, addr - 1); 3767 word_data = AscGetChipLramData(iop_base); 3768 byte_data = (word_data >> 8) & 0xFF; 3769 } else { 3770 AscSetChipLramAddr(iop_base, addr); 3771 word_data = AscGetChipLramData(iop_base); 3772 byte_data = word_data & 0xFF; 3773 } 3774 return byte_data; 3775 } 3776 3777 static ushort AscReadLramWord(PortAddr iop_base, ushort addr) 3778 { 3779 ushort word_data; 3780 3781 AscSetChipLramAddr(iop_base, addr); 3782 word_data = AscGetChipLramData(iop_base); 3783 return (word_data); 3784 } 3785 3786 static void 3787 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words) 3788 { 3789 int i; 3790 3791 AscSetChipLramAddr(iop_base, s_addr); 3792 for (i = 0; i < words; i++) { 3793 AscSetChipLramData(iop_base, set_wval); 3794 } 3795 } 3796 3797 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val) 3798 { 3799 AscSetChipLramAddr(iop_base, addr); 3800 AscSetChipLramData(iop_base, word_val); 3801 } 3802 3803 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val) 3804 { 3805 ushort word_data; 3806 3807 if (isodd_word(addr)) { 3808 addr--; 3809 word_data = AscReadLramWord(iop_base, addr); 3810 word_data &= 0x00FF; 3811 word_data |= (((ushort)byte_val << 8) & 0xFF00); 3812 } else { 3813 word_data = AscReadLramWord(iop_base, addr); 3814 word_data &= 0xFF00; 3815 word_data |= ((ushort)byte_val & 0x00FF); 3816 } 3817 AscWriteLramWord(iop_base, addr, word_data); 3818 } 3819 3820 /* 3821 * Copy 2 bytes to LRAM. 3822 * 3823 * The source data is assumed to be in little-endian order in memory 3824 * and is maintained in little-endian order when written to LRAM. 3825 */ 3826 static void 3827 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr, 3828 const uchar *s_buffer, int words) 3829 { 3830 int i; 3831 3832 AscSetChipLramAddr(iop_base, s_addr); 3833 for (i = 0; i < 2 * words; i += 2) { 3834 /* 3835 * On a little-endian system the second argument below 3836 * produces a little-endian ushort which is written to 3837 * LRAM in little-endian order. On a big-endian system 3838 * the second argument produces a big-endian ushort which 3839 * is "transparently" byte-swapped by outpw() and written 3840 * in little-endian order to LRAM. 3841 */ 3842 outpw(iop_base + IOP_RAM_DATA, 3843 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); 3844 } 3845 } 3846 3847 /* 3848 * Copy 4 bytes to LRAM. 3849 * 3850 * The source data is assumed to be in little-endian order in memory 3851 * and is maintained in little-endian order when written to LRAM. 3852 */ 3853 static void 3854 AscMemDWordCopyPtrToLram(PortAddr iop_base, 3855 ushort s_addr, uchar *s_buffer, int dwords) 3856 { 3857 int i; 3858 3859 AscSetChipLramAddr(iop_base, s_addr); 3860 for (i = 0; i < 4 * dwords; i += 4) { 3861 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */ 3862 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */ 3863 } 3864 } 3865 3866 /* 3867 * Copy 2 bytes from LRAM. 3868 * 3869 * The source data is assumed to be in little-endian order in LRAM 3870 * and is maintained in little-endian order when written to memory. 3871 */ 3872 static void 3873 AscMemWordCopyPtrFromLram(PortAddr iop_base, 3874 ushort s_addr, uchar *d_buffer, int words) 3875 { 3876 int i; 3877 ushort word; 3878 3879 AscSetChipLramAddr(iop_base, s_addr); 3880 for (i = 0; i < 2 * words; i += 2) { 3881 word = inpw(iop_base + IOP_RAM_DATA); 3882 d_buffer[i] = word & 0xff; 3883 d_buffer[i + 1] = (word >> 8) & 0xff; 3884 } 3885 } 3886 3887 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words) 3888 { 3889 u32 sum = 0; 3890 int i; 3891 3892 for (i = 0; i < words; i++, s_addr += 2) { 3893 sum += AscReadLramWord(iop_base, s_addr); 3894 } 3895 return (sum); 3896 } 3897 3898 static void AscInitLram(ASC_DVC_VAR *asc_dvc) 3899 { 3900 uchar i; 3901 ushort s_addr; 3902 PortAddr iop_base; 3903 3904 iop_base = asc_dvc->iop_base; 3905 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0, 3906 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) * 3907 64) >> 1)); 3908 i = ASC_MIN_ACTIVE_QNO; 3909 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 3910 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 3911 (uchar)(i + 1)); 3912 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 3913 (uchar)(asc_dvc->max_total_qng)); 3914 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 3915 (uchar)i); 3916 i++; 3917 s_addr += ASC_QBLK_SIZE; 3918 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 3919 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 3920 (uchar)(i + 1)); 3921 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 3922 (uchar)(i - 1)); 3923 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 3924 (uchar)i); 3925 } 3926 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 3927 (uchar)ASC_QLINK_END); 3928 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 3929 (uchar)(asc_dvc->max_total_qng - 1)); 3930 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 3931 (uchar)asc_dvc->max_total_qng); 3932 i++; 3933 s_addr += ASC_QBLK_SIZE; 3934 for (; i <= (uchar)(asc_dvc->max_total_qng + 3); 3935 i++, s_addr += ASC_QBLK_SIZE) { 3936 AscWriteLramByte(iop_base, 3937 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i); 3938 AscWriteLramByte(iop_base, 3939 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i); 3940 AscWriteLramByte(iop_base, 3941 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i); 3942 } 3943 } 3944 3945 static u32 3946 AscLoadMicroCode(PortAddr iop_base, ushort s_addr, 3947 const uchar *mcode_buf, ushort mcode_size) 3948 { 3949 u32 chksum; 3950 ushort mcode_word_size; 3951 ushort mcode_chksum; 3952 3953 /* Write the microcode buffer starting at LRAM address 0. */ 3954 mcode_word_size = (ushort)(mcode_size >> 1); 3955 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size); 3956 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size); 3957 3958 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size); 3959 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum); 3960 mcode_chksum = (ushort)AscMemSumLramWord(iop_base, 3961 (ushort)ASC_CODE_SEC_BEG, 3962 (ushort)((mcode_size - 3963 s_addr - (ushort) 3964 ASC_CODE_SEC_BEG) / 3965 2)); 3966 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum); 3967 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum); 3968 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size); 3969 return chksum; 3970 } 3971 3972 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc) 3973 { 3974 PortAddr iop_base; 3975 int i; 3976 ushort lram_addr; 3977 3978 iop_base = asc_dvc->iop_base; 3979 AscPutRiscVarFreeQHead(iop_base, 1); 3980 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng); 3981 AscPutVarFreeQHead(iop_base, 1); 3982 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng); 3983 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B, 3984 (uchar)((int)asc_dvc->max_total_qng + 1)); 3985 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B, 3986 (uchar)((int)asc_dvc->max_total_qng + 2)); 3987 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B, 3988 asc_dvc->max_total_qng); 3989 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0); 3990 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 3991 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0); 3992 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0); 3993 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0); 3994 AscPutQDoneInProgress(iop_base, 0); 3995 lram_addr = ASC_QADR_BEG; 3996 for (i = 0; i < 32; i++, lram_addr += 2) { 3997 AscWriteLramWord(iop_base, lram_addr, 0); 3998 } 3999 } 4000 4001 static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc) 4002 { 4003 int i; 4004 int warn_code; 4005 PortAddr iop_base; 4006 __le32 phy_addr; 4007 __le32 phy_size; 4008 struct asc_board *board = asc_dvc_to_board(asc_dvc); 4009 4010 iop_base = asc_dvc->iop_base; 4011 warn_code = 0; 4012 for (i = 0; i <= ASC_MAX_TID; i++) { 4013 AscPutMCodeInitSDTRAtID(iop_base, i, 4014 asc_dvc->cfg->sdtr_period_offset[i]); 4015 } 4016 4017 AscInitQLinkVar(asc_dvc); 4018 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B, 4019 asc_dvc->cfg->disc_enable); 4020 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B, 4021 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id)); 4022 4023 /* Ensure overrun buffer is aligned on an 8 byte boundary. */ 4024 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7); 4025 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf, 4026 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 4027 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) { 4028 warn_code = -ENOMEM; 4029 goto err_dma_map; 4030 } 4031 phy_addr = cpu_to_le32(asc_dvc->overrun_dma); 4032 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D, 4033 (uchar *)&phy_addr, 1); 4034 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE); 4035 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D, 4036 (uchar *)&phy_size, 1); 4037 4038 asc_dvc->cfg->mcode_date = 4039 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W); 4040 asc_dvc->cfg->mcode_version = 4041 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W); 4042 4043 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); 4044 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { 4045 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; 4046 warn_code = -EINVAL; 4047 goto err_mcode_start; 4048 } 4049 if (AscStartChip(iop_base) != 1) { 4050 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; 4051 warn_code = -EIO; 4052 goto err_mcode_start; 4053 } 4054 4055 return warn_code; 4056 4057 err_mcode_start: 4058 dma_unmap_single(board->dev, asc_dvc->overrun_dma, 4059 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 4060 err_dma_map: 4061 asc_dvc->overrun_dma = 0; 4062 return warn_code; 4063 } 4064 4065 static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc) 4066 { 4067 const struct firmware *fw; 4068 const char fwname[] = "advansys/mcode.bin"; 4069 int err; 4070 unsigned long chksum; 4071 int warn_code; 4072 PortAddr iop_base; 4073 4074 iop_base = asc_dvc->iop_base; 4075 warn_code = 0; 4076 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) && 4077 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) { 4078 AscResetChipAndScsiBus(asc_dvc); 4079 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ 4080 } 4081 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC; 4082 if (asc_dvc->err_code != 0) 4083 return ASC_ERROR; 4084 if (!AscFindSignature(asc_dvc->iop_base)) { 4085 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 4086 return warn_code; 4087 } 4088 AscDisableInterrupt(iop_base); 4089 AscInitLram(asc_dvc); 4090 4091 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4092 if (err) { 4093 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4094 fwname, err); 4095 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4096 return err; 4097 } 4098 if (fw->size < 4) { 4099 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4100 fw->size, fwname); 4101 release_firmware(fw); 4102 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4103 return -EINVAL; 4104 } 4105 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4106 (fw->data[1] << 8) | fw->data[0]; 4107 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum); 4108 if (AscLoadMicroCode(iop_base, 0, &fw->data[4], 4109 fw->size - 4) != chksum) { 4110 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4111 release_firmware(fw); 4112 return warn_code; 4113 } 4114 release_firmware(fw); 4115 warn_code |= AscInitMicroCodeVar(asc_dvc); 4116 if (!asc_dvc->overrun_dma) 4117 return warn_code; 4118 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC; 4119 AscEnableInterrupt(iop_base); 4120 return warn_code; 4121 } 4122 4123 /* 4124 * Load the Microcode 4125 * 4126 * Write the microcode image to RISC memory starting at address 0. 4127 * 4128 * The microcode is stored compressed in the following format: 4129 * 4130 * 254 word (508 byte) table indexed by byte code followed 4131 * by the following byte codes: 4132 * 4133 * 1-Byte Code: 4134 * 00: Emit word 0 in table. 4135 * 01: Emit word 1 in table. 4136 * . 4137 * FD: Emit word 253 in table. 4138 * 4139 * Multi-Byte Code: 4140 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 4141 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 4142 * 4143 * Returns 0 or an error if the checksum doesn't match 4144 */ 4145 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf, 4146 int size, int memsize, int chksum) 4147 { 4148 int i, j, end, len = 0; 4149 u32 sum; 4150 4151 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); 4152 4153 for (i = 253 * 2; i < size; i++) { 4154 if (buf[i] == 0xff) { 4155 unsigned short word = (buf[i + 3] << 8) | buf[i + 2]; 4156 for (j = 0; j < buf[i + 1]; j++) { 4157 AdvWriteWordAutoIncLram(iop_base, word); 4158 len += 2; 4159 } 4160 i += 3; 4161 } else if (buf[i] == 0xfe) { 4162 unsigned short word = (buf[i + 2] << 8) | buf[i + 1]; 4163 AdvWriteWordAutoIncLram(iop_base, word); 4164 i += 2; 4165 len += 2; 4166 } else { 4167 unsigned int off = buf[i] * 2; 4168 unsigned short word = (buf[off + 1] << 8) | buf[off]; 4169 AdvWriteWordAutoIncLram(iop_base, word); 4170 len += 2; 4171 } 4172 } 4173 4174 end = len; 4175 4176 while (len < memsize) { 4177 AdvWriteWordAutoIncLram(iop_base, 0); 4178 len += 2; 4179 } 4180 4181 /* Verify the microcode checksum. */ 4182 sum = 0; 4183 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); 4184 4185 for (len = 0; len < end; len += 2) { 4186 sum += AdvReadWordAutoIncLram(iop_base); 4187 } 4188 4189 if (sum != chksum) 4190 return ASC_IERR_MCODE_CHKSUM; 4191 4192 return 0; 4193 } 4194 4195 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc) 4196 { 4197 off_t carr_offset = 0, next_offset; 4198 dma_addr_t carr_paddr; 4199 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i; 4200 4201 for (i = 0; i < carr_num; i++) { 4202 carr_offset = i * sizeof(ADV_CARR_T); 4203 /* Get physical address of the carrier 'carrp'. */ 4204 carr_paddr = adv_dvc->carrier_addr + carr_offset; 4205 4206 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr); 4207 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset); 4208 adv_dvc->carrier[i].areq_vpa = 0; 4209 next_offset = carr_offset + sizeof(ADV_CARR_T); 4210 if (i == carr_num) 4211 next_offset = ~0; 4212 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset); 4213 } 4214 /* 4215 * We cannot have a carrier with 'carr_va' of '0', as 4216 * a reference to this carrier would be interpreted as 4217 * list termination. 4218 * So start at carrier 1 with the freelist. 4219 */ 4220 adv_dvc->carr_freelist = &adv_dvc->carrier[1]; 4221 } 4222 4223 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset) 4224 { 4225 int index; 4226 4227 BUG_ON(offset > ADV_CARRIER_BUFSIZE); 4228 4229 index = offset / sizeof(ADV_CARR_T); 4230 return &adv_dvc->carrier[index]; 4231 } 4232 4233 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc) 4234 { 4235 ADV_CARR_T *carrp = adv_dvc->carr_freelist; 4236 u32 next_vpa = le32_to_cpu(carrp->next_vpa); 4237 4238 if (next_vpa == 0 || next_vpa == ~0) { 4239 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa); 4240 return NULL; 4241 } 4242 4243 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa); 4244 /* 4245 * insert stopper carrier to terminate list 4246 */ 4247 carrp->next_vpa = cpu_to_le32(ADV_CQ_STOPPER); 4248 4249 return carrp; 4250 } 4251 4252 /* 4253 * 'offset' is the index in the request pointer array 4254 */ 4255 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset) 4256 { 4257 struct asc_board *boardp = adv_dvc->drv_ptr; 4258 4259 BUG_ON(offset > adv_dvc->max_host_qng); 4260 return &boardp->adv_reqp[offset]; 4261 } 4262 4263 /* 4264 * Send an idle command to the chip and wait for completion. 4265 * 4266 * Command completion is polled for once per microsecond. 4267 * 4268 * The function can be called from anywhere including an interrupt handler. 4269 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical() 4270 * functions to prevent reentrancy. 4271 * 4272 * Return Values: 4273 * ADV_TRUE - command completed successfully 4274 * ADV_FALSE - command failed 4275 * ADV_ERROR - command timed out 4276 */ 4277 static int 4278 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc, 4279 ushort idle_cmd, u32 idle_cmd_parameter) 4280 { 4281 int result, i, j; 4282 AdvPortAddr iop_base; 4283 4284 iop_base = asc_dvc->iop_base; 4285 4286 /* 4287 * Clear the idle command status which is set by the microcode 4288 * to a non-zero value to indicate when the command is completed. 4289 * The non-zero result is one of the IDLE_CMD_STATUS_* values 4290 */ 4291 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0); 4292 4293 /* 4294 * Write the idle command value after the idle command parameter 4295 * has been written to avoid a race condition. If the order is not 4296 * followed, the microcode may process the idle command before the 4297 * parameters have been written to LRAM. 4298 */ 4299 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER, 4300 cpu_to_le32(idle_cmd_parameter)); 4301 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd); 4302 4303 /* 4304 * Tickle the RISC to tell it to process the idle command. 4305 */ 4306 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B); 4307 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 4308 /* 4309 * Clear the tickle value. In the ASC-3550 the RISC flag 4310 * command 'clr_tickle_b' does not work unless the host 4311 * value is cleared. 4312 */ 4313 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP); 4314 } 4315 4316 /* Wait for up to 100 millisecond for the idle command to timeout. */ 4317 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 4318 /* Poll once each microsecond for command completion. */ 4319 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 4320 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, 4321 result); 4322 if (result != 0) 4323 return result; 4324 udelay(1); 4325 } 4326 } 4327 4328 BUG(); /* The idle command should never timeout. */ 4329 return ADV_ERROR; 4330 } 4331 4332 /* 4333 * Reset SCSI Bus and purge all outstanding requests. 4334 * 4335 * Return Value: 4336 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset. 4337 * ADV_FALSE(0) - Microcode command failed. 4338 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC 4339 * may be hung which requires driver recovery. 4340 */ 4341 static int AdvResetSB(ADV_DVC_VAR *asc_dvc) 4342 { 4343 int status; 4344 4345 /* 4346 * Send the SCSI Bus Reset idle start idle command which asserts 4347 * the SCSI Bus Reset signal. 4348 */ 4349 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L); 4350 if (status != ADV_TRUE) { 4351 return status; 4352 } 4353 4354 /* 4355 * Delay for the specified SCSI Bus Reset hold time. 4356 * 4357 * The hold time delay is done on the host because the RISC has no 4358 * microsecond accurate timer. 4359 */ 4360 udelay(ASC_SCSI_RESET_HOLD_TIME_US); 4361 4362 /* 4363 * Send the SCSI Bus Reset end idle command which de-asserts 4364 * the SCSI Bus Reset signal and purges any pending requests. 4365 */ 4366 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L); 4367 if (status != ADV_TRUE) { 4368 return status; 4369 } 4370 4371 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ 4372 4373 return status; 4374 } 4375 4376 /* 4377 * Initialize the ASC-3550. 4378 * 4379 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 4380 * 4381 * For a non-fatal error return a warning code. If there are no warnings 4382 * then 0 is returned. 4383 * 4384 * Needed after initialization for error recovery. 4385 */ 4386 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc) 4387 { 4388 const struct firmware *fw; 4389 const char fwname[] = "advansys/3550.bin"; 4390 AdvPortAddr iop_base; 4391 ushort warn_code; 4392 int begin_addr; 4393 int end_addr; 4394 ushort code_sum; 4395 int word; 4396 int i; 4397 int err; 4398 unsigned long chksum; 4399 ushort scsi_cfg1; 4400 uchar tid; 4401 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 4402 ushort wdtr_able = 0, sdtr_able, tagqng_able; 4403 uchar max_cmd[ADV_MAX_TID + 1]; 4404 4405 /* If there is already an error, don't continue. */ 4406 if (asc_dvc->err_code != 0) 4407 return ADV_ERROR; 4408 4409 /* 4410 * The caller must set 'chip_type' to ADV_CHIP_ASC3550. 4411 */ 4412 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) { 4413 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 4414 return ADV_ERROR; 4415 } 4416 4417 warn_code = 0; 4418 iop_base = asc_dvc->iop_base; 4419 4420 /* 4421 * Save the RISC memory BIOS region before writing the microcode. 4422 * The BIOS may already be loaded and using its RISC LRAM region 4423 * so its region must be saved and restored. 4424 * 4425 * Note: This code makes the assumption, which is currently true, 4426 * that a chip reset does not clear RISC LRAM. 4427 */ 4428 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4429 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4430 bios_mem[i]); 4431 } 4432 4433 /* 4434 * Save current per TID negotiated values. 4435 */ 4436 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) { 4437 ushort bios_version, major, minor; 4438 4439 bios_version = 4440 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2]; 4441 major = (bios_version >> 12) & 0xF; 4442 minor = (bios_version >> 8) & 0xF; 4443 if (major < 3 || (major == 3 && minor == 1)) { 4444 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ 4445 AdvReadWordLram(iop_base, 0x120, wdtr_able); 4446 } else { 4447 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 4448 } 4449 } 4450 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 4451 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 4452 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4453 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 4454 max_cmd[tid]); 4455 } 4456 4457 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4458 if (err) { 4459 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4460 fwname, err); 4461 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4462 return err; 4463 } 4464 if (fw->size < 4) { 4465 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4466 fw->size, fwname); 4467 release_firmware(fw); 4468 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4469 return -EINVAL; 4470 } 4471 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4472 (fw->data[1] << 8) | fw->data[0]; 4473 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 4474 fw->size - 4, ADV_3550_MEMSIZE, 4475 chksum); 4476 release_firmware(fw); 4477 if (asc_dvc->err_code) 4478 return ADV_ERROR; 4479 4480 /* 4481 * Restore the RISC memory BIOS region. 4482 */ 4483 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4484 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4485 bios_mem[i]); 4486 } 4487 4488 /* 4489 * Calculate and write the microcode code checksum to the microcode 4490 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 4491 */ 4492 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 4493 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 4494 code_sum = 0; 4495 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 4496 for (word = begin_addr; word < end_addr; word += 2) { 4497 code_sum += AdvReadWordAutoIncLram(iop_base); 4498 } 4499 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 4500 4501 /* 4502 * Read and save microcode version and date. 4503 */ 4504 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 4505 asc_dvc->cfg->mcode_date); 4506 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 4507 asc_dvc->cfg->mcode_version); 4508 4509 /* 4510 * Set the chip type to indicate the ASC3550. 4511 */ 4512 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550); 4513 4514 /* 4515 * If the PCI Configuration Command Register "Parity Error Response 4516 * Control" Bit was clear (0), then set the microcode variable 4517 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 4518 * to ignore DMA parity errors. 4519 */ 4520 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 4521 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4522 word |= CONTROL_FLAG_IGNORE_PERR; 4523 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4524 } 4525 4526 /* 4527 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO 4528 * threshold of 128 bytes. This register is only accessible to the host. 4529 */ 4530 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 4531 START_CTL_EMFU | READ_CMD_MRM); 4532 4533 /* 4534 * Microcode operating variables for WDTR, SDTR, and command tag 4535 * queuing will be set in slave_configure() based on what a 4536 * device reports it is capable of in Inquiry byte 7. 4537 * 4538 * If SCSI Bus Resets have been disabled, then directly set 4539 * SDTR and WDTR from the EEPROM configuration. This will allow 4540 * the BIOS and warm boot to work without a SCSI bus hang on 4541 * the Inquiry caused by host and target mismatched DTR values. 4542 * Without the SCSI Bus Reset, before an Inquiry a device can't 4543 * be assumed to be in Asynchronous, Narrow mode. 4544 */ 4545 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 4546 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 4547 asc_dvc->wdtr_able); 4548 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 4549 asc_dvc->sdtr_able); 4550 } 4551 4552 /* 4553 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 4554 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 4555 * bitmask. These values determine the maximum SDTR speed negotiated 4556 * with a device. 4557 * 4558 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 4559 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 4560 * without determining here whether the device supports SDTR. 4561 * 4562 * 4-bit speed SDTR speed name 4563 * =========== =============== 4564 * 0000b (0x0) SDTR disabled 4565 * 0001b (0x1) 5 Mhz 4566 * 0010b (0x2) 10 Mhz 4567 * 0011b (0x3) 20 Mhz (Ultra) 4568 * 0100b (0x4) 40 Mhz (LVD/Ultra2) 4569 * 0101b (0x5) 80 Mhz (LVD2/Ultra3) 4570 * 0110b (0x6) Undefined 4571 * . 4572 * 1111b (0xF) Undefined 4573 */ 4574 word = 0; 4575 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4576 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) { 4577 /* Set Ultra speed for TID 'tid'. */ 4578 word |= (0x3 << (4 * (tid % 4))); 4579 } else { 4580 /* Set Fast speed for TID 'tid'. */ 4581 word |= (0x2 << (4 * (tid % 4))); 4582 } 4583 if (tid == 3) { /* Check if done with sdtr_speed1. */ 4584 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word); 4585 word = 0; 4586 } else if (tid == 7) { /* Check if done with sdtr_speed2. */ 4587 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word); 4588 word = 0; 4589 } else if (tid == 11) { /* Check if done with sdtr_speed3. */ 4590 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word); 4591 word = 0; 4592 } else if (tid == 15) { /* Check if done with sdtr_speed4. */ 4593 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word); 4594 /* End of loop. */ 4595 } 4596 } 4597 4598 /* 4599 * Set microcode operating variable for the disconnect per TID bitmask. 4600 */ 4601 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 4602 asc_dvc->cfg->disc_enable); 4603 4604 /* 4605 * Set SCSI_CFG0 Microcode Default Value. 4606 * 4607 * The microcode will set the SCSI_CFG0 register using this value 4608 * after it is started below. 4609 */ 4610 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 4611 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 4612 asc_dvc->chip_scsi_id); 4613 4614 /* 4615 * Determine SCSI_CFG1 Microcode Default Value. 4616 * 4617 * The microcode will set the SCSI_CFG1 register using this value 4618 * after it is started below. 4619 */ 4620 4621 /* Read current SCSI_CFG1 Register value. */ 4622 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 4623 4624 /* 4625 * If all three connectors are in use, return an error. 4626 */ 4627 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 4628 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 4629 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION; 4630 return ADV_ERROR; 4631 } 4632 4633 /* 4634 * If the internal narrow cable is reversed all of the SCSI_CTRL 4635 * register signals will be set. Check for and return an error if 4636 * this condition is found. 4637 */ 4638 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 4639 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 4640 return ADV_ERROR; 4641 } 4642 4643 /* 4644 * If this is a differential board and a single-ended device 4645 * is attached to one of the connectors, return an error. 4646 */ 4647 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) { 4648 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE; 4649 return ADV_ERROR; 4650 } 4651 4652 /* 4653 * If automatic termination control is enabled, then set the 4654 * termination value based on a table listed in a_condor.h. 4655 * 4656 * If manual termination was specified with an EEPROM setting 4657 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and 4658 * is ready to be 'ored' into SCSI_CFG1. 4659 */ 4660 if (asc_dvc->cfg->termination == 0) { 4661 /* 4662 * The software always controls termination by setting TERM_CTL_SEL. 4663 * If TERM_CTL_SEL were set to 0, the hardware would set termination. 4664 */ 4665 asc_dvc->cfg->termination |= TERM_CTL_SEL; 4666 4667 switch (scsi_cfg1 & CABLE_DETECT) { 4668 /* TERM_CTL_H: on, TERM_CTL_L: on */ 4669 case 0x3: 4670 case 0x7: 4671 case 0xB: 4672 case 0xD: 4673 case 0xE: 4674 case 0xF: 4675 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L); 4676 break; 4677 4678 /* TERM_CTL_H: on, TERM_CTL_L: off */ 4679 case 0x1: 4680 case 0x5: 4681 case 0x9: 4682 case 0xA: 4683 case 0xC: 4684 asc_dvc->cfg->termination |= TERM_CTL_H; 4685 break; 4686 4687 /* TERM_CTL_H: off, TERM_CTL_L: off */ 4688 case 0x2: 4689 case 0x6: 4690 break; 4691 } 4692 } 4693 4694 /* 4695 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 4696 */ 4697 scsi_cfg1 &= ~TERM_CTL; 4698 4699 /* 4700 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 4701 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 4702 * referenced, because the hardware internally inverts 4703 * the Termination High and Low bits if TERM_POL is set. 4704 */ 4705 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL)); 4706 4707 /* 4708 * Set SCSI_CFG1 Microcode Default Value 4709 * 4710 * Set filter value and possibly modified termination control 4711 * bits in the Microcode SCSI_CFG1 Register Value. 4712 * 4713 * The microcode will set the SCSI_CFG1 register using this value 4714 * after it is started below. 4715 */ 4716 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, 4717 FLTR_DISABLE | scsi_cfg1); 4718 4719 /* 4720 * Set MEM_CFG Microcode Default Value 4721 * 4722 * The microcode will set the MEM_CFG register using this value 4723 * after it is started below. 4724 * 4725 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 4726 * are defined. 4727 * 4728 * ASC-3550 has 8KB internal memory. 4729 */ 4730 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 4731 BIOS_EN | RAM_SZ_8KB); 4732 4733 /* 4734 * Set SEL_MASK Microcode Default Value 4735 * 4736 * The microcode will set the SEL_MASK register using this value 4737 * after it is started below. 4738 */ 4739 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 4740 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 4741 4742 AdvBuildCarrierFreelist(asc_dvc); 4743 4744 /* 4745 * Set-up the Host->RISC Initiator Command Queue (ICQ). 4746 */ 4747 4748 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc); 4749 if (!asc_dvc->icq_sp) { 4750 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 4751 return ADV_ERROR; 4752 } 4753 4754 /* 4755 * Set RISC ICQ physical address start value. 4756 */ 4757 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 4758 4759 /* 4760 * Set-up the RISC->Host Initiator Response Queue (IRQ). 4761 */ 4762 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc); 4763 if (!asc_dvc->irq_sp) { 4764 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 4765 return ADV_ERROR; 4766 } 4767 4768 /* 4769 * Set RISC IRQ physical address start value. 4770 */ 4771 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 4772 asc_dvc->carr_pending_cnt = 0; 4773 4774 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 4775 (ADV_INTR_ENABLE_HOST_INTR | 4776 ADV_INTR_ENABLE_GLOBAL_INTR)); 4777 4778 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 4779 AdvWriteWordRegister(iop_base, IOPW_PC, word); 4780 4781 /* finally, finally, gentlemen, start your engine */ 4782 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 4783 4784 /* 4785 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 4786 * Resets should be performed. The RISC has to be running 4787 * to issue a SCSI Bus Reset. 4788 */ 4789 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 4790 /* 4791 * If the BIOS Signature is present in memory, restore the 4792 * BIOS Handshake Configuration Table and do not perform 4793 * a SCSI Bus Reset. 4794 */ 4795 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 4796 0x55AA) { 4797 /* 4798 * Restore per TID negotiated values. 4799 */ 4800 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 4801 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 4802 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 4803 tagqng_able); 4804 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4805 AdvWriteByteLram(iop_base, 4806 ASC_MC_NUMBER_OF_MAX_CMD + tid, 4807 max_cmd[tid]); 4808 } 4809 } else { 4810 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 4811 warn_code = ASC_WARN_BUSRESET_ERROR; 4812 } 4813 } 4814 } 4815 4816 return warn_code; 4817 } 4818 4819 /* 4820 * Initialize the ASC-38C0800. 4821 * 4822 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 4823 * 4824 * For a non-fatal error return a warning code. If there are no warnings 4825 * then 0 is returned. 4826 * 4827 * Needed after initialization for error recovery. 4828 */ 4829 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc) 4830 { 4831 const struct firmware *fw; 4832 const char fwname[] = "advansys/38C0800.bin"; 4833 AdvPortAddr iop_base; 4834 ushort warn_code; 4835 int begin_addr; 4836 int end_addr; 4837 ushort code_sum; 4838 int word; 4839 int i; 4840 int err; 4841 unsigned long chksum; 4842 ushort scsi_cfg1; 4843 uchar byte; 4844 uchar tid; 4845 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 4846 ushort wdtr_able, sdtr_able, tagqng_able; 4847 uchar max_cmd[ADV_MAX_TID + 1]; 4848 4849 /* If there is already an error, don't continue. */ 4850 if (asc_dvc->err_code != 0) 4851 return ADV_ERROR; 4852 4853 /* 4854 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800. 4855 */ 4856 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) { 4857 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 4858 return ADV_ERROR; 4859 } 4860 4861 warn_code = 0; 4862 iop_base = asc_dvc->iop_base; 4863 4864 /* 4865 * Save the RISC memory BIOS region before writing the microcode. 4866 * The BIOS may already be loaded and using its RISC LRAM region 4867 * so its region must be saved and restored. 4868 * 4869 * Note: This code makes the assumption, which is currently true, 4870 * that a chip reset does not clear RISC LRAM. 4871 */ 4872 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4873 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4874 bios_mem[i]); 4875 } 4876 4877 /* 4878 * Save current per TID negotiated values. 4879 */ 4880 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 4881 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 4882 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 4883 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4884 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 4885 max_cmd[tid]); 4886 } 4887 4888 /* 4889 * RAM BIST (RAM Built-In Self Test) 4890 * 4891 * Address : I/O base + offset 0x38h register (byte). 4892 * Function: Bit 7-6(RW) : RAM mode 4893 * Normal Mode : 0x00 4894 * Pre-test Mode : 0x40 4895 * RAM Test Mode : 0x80 4896 * Bit 5 : unused 4897 * Bit 4(RO) : Done bit 4898 * Bit 3-0(RO) : Status 4899 * Host Error : 0x08 4900 * Int_RAM Error : 0x04 4901 * RISC Error : 0x02 4902 * SCSI Error : 0x01 4903 * No Error : 0x00 4904 * 4905 * Note: RAM BIST code should be put right here, before loading the 4906 * microcode and after saving the RISC memory BIOS region. 4907 */ 4908 4909 /* 4910 * LRAM Pre-test 4911 * 4912 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 4913 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 4914 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 4915 * to NORMAL_MODE, return an error too. 4916 */ 4917 for (i = 0; i < 2; i++) { 4918 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); 4919 mdelay(10); /* Wait for 10ms before reading back. */ 4920 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 4921 if ((byte & RAM_TEST_DONE) == 0 4922 || (byte & 0x0F) != PRE_TEST_VALUE) { 4923 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 4924 return ADV_ERROR; 4925 } 4926 4927 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 4928 mdelay(10); /* Wait for 10ms before reading back. */ 4929 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) 4930 != NORMAL_VALUE) { 4931 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 4932 return ADV_ERROR; 4933 } 4934 } 4935 4936 /* 4937 * LRAM Test - It takes about 1.5 ms to run through the test. 4938 * 4939 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 4940 * If Done bit not set or Status not 0, save register byte, set the 4941 * err_code, and return an error. 4942 */ 4943 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); 4944 mdelay(10); /* Wait for 10ms before checking status. */ 4945 4946 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 4947 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 4948 /* Get here if Done bit not set or Status not 0. */ 4949 asc_dvc->bist_err_code = byte; /* for BIOS display message */ 4950 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; 4951 return ADV_ERROR; 4952 } 4953 4954 /* We need to reset back to normal mode after LRAM test passes. */ 4955 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 4956 4957 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4958 if (err) { 4959 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4960 fwname, err); 4961 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4962 return err; 4963 } 4964 if (fw->size < 4) { 4965 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4966 fw->size, fwname); 4967 release_firmware(fw); 4968 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4969 return -EINVAL; 4970 } 4971 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4972 (fw->data[1] << 8) | fw->data[0]; 4973 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 4974 fw->size - 4, ADV_38C0800_MEMSIZE, 4975 chksum); 4976 release_firmware(fw); 4977 if (asc_dvc->err_code) 4978 return ADV_ERROR; 4979 4980 /* 4981 * Restore the RISC memory BIOS region. 4982 */ 4983 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4984 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4985 bios_mem[i]); 4986 } 4987 4988 /* 4989 * Calculate and write the microcode code checksum to the microcode 4990 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 4991 */ 4992 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 4993 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 4994 code_sum = 0; 4995 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 4996 for (word = begin_addr; word < end_addr; word += 2) { 4997 code_sum += AdvReadWordAutoIncLram(iop_base); 4998 } 4999 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 5000 5001 /* 5002 * Read microcode version and date. 5003 */ 5004 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 5005 asc_dvc->cfg->mcode_date); 5006 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 5007 asc_dvc->cfg->mcode_version); 5008 5009 /* 5010 * Set the chip type to indicate the ASC38C0800. 5011 */ 5012 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800); 5013 5014 /* 5015 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 5016 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 5017 * cable detection and then we are able to read C_DET[3:0]. 5018 * 5019 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 5020 * Microcode Default Value' section below. 5021 */ 5022 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5023 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, 5024 scsi_cfg1 | DIS_TERM_DRV); 5025 5026 /* 5027 * If the PCI Configuration Command Register "Parity Error Response 5028 * Control" Bit was clear (0), then set the microcode variable 5029 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 5030 * to ignore DMA parity errors. 5031 */ 5032 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 5033 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5034 word |= CONTROL_FLAG_IGNORE_PERR; 5035 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5036 } 5037 5038 /* 5039 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2] 5040 * bits for the default FIFO threshold. 5041 * 5042 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 5043 * 5044 * For DMA Errata #4 set the BC_THRESH_ENB bit. 5045 */ 5046 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 5047 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | 5048 READ_CMD_MRM); 5049 5050 /* 5051 * Microcode operating variables for WDTR, SDTR, and command tag 5052 * queuing will be set in slave_configure() based on what a 5053 * device reports it is capable of in Inquiry byte 7. 5054 * 5055 * If SCSI Bus Resets have been disabled, then directly set 5056 * SDTR and WDTR from the EEPROM configuration. This will allow 5057 * the BIOS and warm boot to work without a SCSI bus hang on 5058 * the Inquiry caused by host and target mismatched DTR values. 5059 * Without the SCSI Bus Reset, before an Inquiry a device can't 5060 * be assumed to be in Asynchronous, Narrow mode. 5061 */ 5062 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 5063 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 5064 asc_dvc->wdtr_able); 5065 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 5066 asc_dvc->sdtr_able); 5067 } 5068 5069 /* 5070 * Set microcode operating variables for DISC and SDTR_SPEED1, 5071 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 5072 * configuration values. 5073 * 5074 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 5075 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 5076 * without determining here whether the device supports SDTR. 5077 */ 5078 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 5079 asc_dvc->cfg->disc_enable); 5080 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); 5081 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); 5082 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); 5083 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); 5084 5085 /* 5086 * Set SCSI_CFG0 Microcode Default Value. 5087 * 5088 * The microcode will set the SCSI_CFG0 register using this value 5089 * after it is started below. 5090 */ 5091 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 5092 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 5093 asc_dvc->chip_scsi_id); 5094 5095 /* 5096 * Determine SCSI_CFG1 Microcode Default Value. 5097 * 5098 * The microcode will set the SCSI_CFG1 register using this value 5099 * after it is started below. 5100 */ 5101 5102 /* Read current SCSI_CFG1 Register value. */ 5103 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5104 5105 /* 5106 * If the internal narrow cable is reversed all of the SCSI_CTRL 5107 * register signals will be set. Check for and return an error if 5108 * this condition is found. 5109 */ 5110 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 5111 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 5112 return ADV_ERROR; 5113 } 5114 5115 /* 5116 * All kind of combinations of devices attached to one of four 5117 * connectors are acceptable except HVD device attached. For example, 5118 * LVD device can be attached to SE connector while SE device attached 5119 * to LVD connector. If LVD device attached to SE connector, it only 5120 * runs up to Ultra speed. 5121 * 5122 * If an HVD device is attached to one of LVD connectors, return an 5123 * error. However, there is no way to detect HVD device attached to 5124 * SE connectors. 5125 */ 5126 if (scsi_cfg1 & HVD) { 5127 asc_dvc->err_code = ASC_IERR_HVD_DEVICE; 5128 return ADV_ERROR; 5129 } 5130 5131 /* 5132 * If either SE or LVD automatic termination control is enabled, then 5133 * set the termination value based on a table listed in a_condor.h. 5134 * 5135 * If manual termination was specified with an EEPROM setting then 5136 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready 5137 * to be 'ored' into SCSI_CFG1. 5138 */ 5139 if ((asc_dvc->cfg->termination & TERM_SE) == 0) { 5140 /* SE automatic termination control is enabled. */ 5141 switch (scsi_cfg1 & C_DET_SE) { 5142 /* TERM_SE_HI: on, TERM_SE_LO: on */ 5143 case 0x1: 5144 case 0x2: 5145 case 0x3: 5146 asc_dvc->cfg->termination |= TERM_SE; 5147 break; 5148 5149 /* TERM_SE_HI: on, TERM_SE_LO: off */ 5150 case 0x0: 5151 asc_dvc->cfg->termination |= TERM_SE_HI; 5152 break; 5153 } 5154 } 5155 5156 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) { 5157 /* LVD automatic termination control is enabled. */ 5158 switch (scsi_cfg1 & C_DET_LVD) { 5159 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 5160 case 0x4: 5161 case 0x8: 5162 case 0xC: 5163 asc_dvc->cfg->termination |= TERM_LVD; 5164 break; 5165 5166 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 5167 case 0x0: 5168 break; 5169 } 5170 } 5171 5172 /* 5173 * Clear any set TERM_SE and TERM_LVD bits. 5174 */ 5175 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD); 5176 5177 /* 5178 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 5179 */ 5180 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0); 5181 5182 /* 5183 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE 5184 * bits and set possibly modified termination control bits in the 5185 * Microcode SCSI_CFG1 Register Value. 5186 */ 5187 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE); 5188 5189 /* 5190 * Set SCSI_CFG1 Microcode Default Value 5191 * 5192 * Set possibly modified termination control and reset DIS_TERM_DRV 5193 * bits in the Microcode SCSI_CFG1 Register Value. 5194 * 5195 * The microcode will set the SCSI_CFG1 register using this value 5196 * after it is started below. 5197 */ 5198 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 5199 5200 /* 5201 * Set MEM_CFG Microcode Default Value 5202 * 5203 * The microcode will set the MEM_CFG register using this value 5204 * after it is started below. 5205 * 5206 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 5207 * are defined. 5208 * 5209 * ASC-38C0800 has 16KB internal memory. 5210 */ 5211 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5212 BIOS_EN | RAM_SZ_16KB); 5213 5214 /* 5215 * Set SEL_MASK Microcode Default Value 5216 * 5217 * The microcode will set the SEL_MASK register using this value 5218 * after it is started below. 5219 */ 5220 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 5221 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 5222 5223 AdvBuildCarrierFreelist(asc_dvc); 5224 5225 /* 5226 * Set-up the Host->RISC Initiator Command Queue (ICQ). 5227 */ 5228 5229 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc); 5230 if (!asc_dvc->icq_sp) { 5231 ASC_DBG(0, "Failed to get ICQ carrier\n"); 5232 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5233 return ADV_ERROR; 5234 } 5235 5236 /* 5237 * Set RISC ICQ physical address start value. 5238 * carr_pa is LE, must be native before write 5239 */ 5240 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 5241 5242 /* 5243 * Set-up the RISC->Host Initiator Response Queue (IRQ). 5244 */ 5245 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc); 5246 if (!asc_dvc->irq_sp) { 5247 ASC_DBG(0, "Failed to get IRQ carrier\n"); 5248 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5249 return ADV_ERROR; 5250 } 5251 5252 /* 5253 * Set RISC IRQ physical address start value. 5254 * 5255 * carr_pa is LE, must be native before write * 5256 */ 5257 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 5258 asc_dvc->carr_pending_cnt = 0; 5259 5260 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 5261 (ADV_INTR_ENABLE_HOST_INTR | 5262 ADV_INTR_ENABLE_GLOBAL_INTR)); 5263 5264 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 5265 AdvWriteWordRegister(iop_base, IOPW_PC, word); 5266 5267 /* finally, finally, gentlemen, start your engine */ 5268 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 5269 5270 /* 5271 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 5272 * Resets should be performed. The RISC has to be running 5273 * to issue a SCSI Bus Reset. 5274 */ 5275 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 5276 /* 5277 * If the BIOS Signature is present in memory, restore the 5278 * BIOS Handshake Configuration Table and do not perform 5279 * a SCSI Bus Reset. 5280 */ 5281 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 5282 0x55AA) { 5283 /* 5284 * Restore per TID negotiated values. 5285 */ 5286 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5287 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5288 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 5289 tagqng_able); 5290 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5291 AdvWriteByteLram(iop_base, 5292 ASC_MC_NUMBER_OF_MAX_CMD + tid, 5293 max_cmd[tid]); 5294 } 5295 } else { 5296 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 5297 warn_code = ASC_WARN_BUSRESET_ERROR; 5298 } 5299 } 5300 } 5301 5302 return warn_code; 5303 } 5304 5305 /* 5306 * Initialize the ASC-38C1600. 5307 * 5308 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 5309 * 5310 * For a non-fatal error return a warning code. If there are no warnings 5311 * then 0 is returned. 5312 * 5313 * Needed after initialization for error recovery. 5314 */ 5315 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc) 5316 { 5317 const struct firmware *fw; 5318 const char fwname[] = "advansys/38C1600.bin"; 5319 AdvPortAddr iop_base; 5320 ushort warn_code; 5321 int begin_addr; 5322 int end_addr; 5323 ushort code_sum; 5324 long word; 5325 int i; 5326 int err; 5327 unsigned long chksum; 5328 ushort scsi_cfg1; 5329 uchar byte; 5330 uchar tid; 5331 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 5332 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able; 5333 uchar max_cmd[ASC_MAX_TID + 1]; 5334 5335 /* If there is already an error, don't continue. */ 5336 if (asc_dvc->err_code != 0) { 5337 return ADV_ERROR; 5338 } 5339 5340 /* 5341 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600. 5342 */ 5343 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { 5344 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 5345 return ADV_ERROR; 5346 } 5347 5348 warn_code = 0; 5349 iop_base = asc_dvc->iop_base; 5350 5351 /* 5352 * Save the RISC memory BIOS region before writing the microcode. 5353 * The BIOS may already be loaded and using its RISC LRAM region 5354 * so its region must be saved and restored. 5355 * 5356 * Note: This code makes the assumption, which is currently true, 5357 * that a chip reset does not clear RISC LRAM. 5358 */ 5359 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5360 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5361 bios_mem[i]); 5362 } 5363 5364 /* 5365 * Save current per TID negotiated values. 5366 */ 5367 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5368 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5369 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5370 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5371 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 5372 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5373 max_cmd[tid]); 5374 } 5375 5376 /* 5377 * RAM BIST (Built-In Self Test) 5378 * 5379 * Address : I/O base + offset 0x38h register (byte). 5380 * Function: Bit 7-6(RW) : RAM mode 5381 * Normal Mode : 0x00 5382 * Pre-test Mode : 0x40 5383 * RAM Test Mode : 0x80 5384 * Bit 5 : unused 5385 * Bit 4(RO) : Done bit 5386 * Bit 3-0(RO) : Status 5387 * Host Error : 0x08 5388 * Int_RAM Error : 0x04 5389 * RISC Error : 0x02 5390 * SCSI Error : 0x01 5391 * No Error : 0x00 5392 * 5393 * Note: RAM BIST code should be put right here, before loading the 5394 * microcode and after saving the RISC memory BIOS region. 5395 */ 5396 5397 /* 5398 * LRAM Pre-test 5399 * 5400 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 5401 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 5402 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 5403 * to NORMAL_MODE, return an error too. 5404 */ 5405 for (i = 0; i < 2; i++) { 5406 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); 5407 mdelay(10); /* Wait for 10ms before reading back. */ 5408 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 5409 if ((byte & RAM_TEST_DONE) == 0 5410 || (byte & 0x0F) != PRE_TEST_VALUE) { 5411 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 5412 return ADV_ERROR; 5413 } 5414 5415 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 5416 mdelay(10); /* Wait for 10ms before reading back. */ 5417 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) 5418 != NORMAL_VALUE) { 5419 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 5420 return ADV_ERROR; 5421 } 5422 } 5423 5424 /* 5425 * LRAM Test - It takes about 1.5 ms to run through the test. 5426 * 5427 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 5428 * If Done bit not set or Status not 0, save register byte, set the 5429 * err_code, and return an error. 5430 */ 5431 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); 5432 mdelay(10); /* Wait for 10ms before checking status. */ 5433 5434 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 5435 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 5436 /* Get here if Done bit not set or Status not 0. */ 5437 asc_dvc->bist_err_code = byte; /* for BIOS display message */ 5438 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; 5439 return ADV_ERROR; 5440 } 5441 5442 /* We need to reset back to normal mode after LRAM test passes. */ 5443 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 5444 5445 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 5446 if (err) { 5447 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 5448 fwname, err); 5449 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5450 return err; 5451 } 5452 if (fw->size < 4) { 5453 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 5454 fw->size, fwname); 5455 release_firmware(fw); 5456 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5457 return -EINVAL; 5458 } 5459 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 5460 (fw->data[1] << 8) | fw->data[0]; 5461 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 5462 fw->size - 4, ADV_38C1600_MEMSIZE, 5463 chksum); 5464 release_firmware(fw); 5465 if (asc_dvc->err_code) 5466 return ADV_ERROR; 5467 5468 /* 5469 * Restore the RISC memory BIOS region. 5470 */ 5471 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5472 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5473 bios_mem[i]); 5474 } 5475 5476 /* 5477 * Calculate and write the microcode code checksum to the microcode 5478 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 5479 */ 5480 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 5481 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 5482 code_sum = 0; 5483 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 5484 for (word = begin_addr; word < end_addr; word += 2) { 5485 code_sum += AdvReadWordAutoIncLram(iop_base); 5486 } 5487 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 5488 5489 /* 5490 * Read microcode version and date. 5491 */ 5492 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 5493 asc_dvc->cfg->mcode_date); 5494 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 5495 asc_dvc->cfg->mcode_version); 5496 5497 /* 5498 * Set the chip type to indicate the ASC38C1600. 5499 */ 5500 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600); 5501 5502 /* 5503 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 5504 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 5505 * cable detection and then we are able to read C_DET[3:0]. 5506 * 5507 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 5508 * Microcode Default Value' section below. 5509 */ 5510 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5511 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, 5512 scsi_cfg1 | DIS_TERM_DRV); 5513 5514 /* 5515 * If the PCI Configuration Command Register "Parity Error Response 5516 * Control" Bit was clear (0), then set the microcode variable 5517 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 5518 * to ignore DMA parity errors. 5519 */ 5520 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 5521 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5522 word |= CONTROL_FLAG_IGNORE_PERR; 5523 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5524 } 5525 5526 /* 5527 * If the BIOS control flag AIPP (Asynchronous Information 5528 * Phase Protection) disable bit is not set, then set the firmware 5529 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable 5530 * AIPP checking and encoding. 5531 */ 5532 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 5533 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5534 word |= CONTROL_FLAG_ENABLE_AIPP; 5535 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5536 } 5537 5538 /* 5539 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4], 5540 * and START_CTL_TH [3:2]. 5541 */ 5542 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 5543 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 5544 5545 /* 5546 * Microcode operating variables for WDTR, SDTR, and command tag 5547 * queuing will be set in slave_configure() based on what a 5548 * device reports it is capable of in Inquiry byte 7. 5549 * 5550 * If SCSI Bus Resets have been disabled, then directly set 5551 * SDTR and WDTR from the EEPROM configuration. This will allow 5552 * the BIOS and warm boot to work without a SCSI bus hang on 5553 * the Inquiry caused by host and target mismatched DTR values. 5554 * Without the SCSI Bus Reset, before an Inquiry a device can't 5555 * be assumed to be in Asynchronous, Narrow mode. 5556 */ 5557 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 5558 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 5559 asc_dvc->wdtr_able); 5560 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 5561 asc_dvc->sdtr_able); 5562 } 5563 5564 /* 5565 * Set microcode operating variables for DISC and SDTR_SPEED1, 5566 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 5567 * configuration values. 5568 * 5569 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 5570 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 5571 * without determining here whether the device supports SDTR. 5572 */ 5573 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 5574 asc_dvc->cfg->disc_enable); 5575 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); 5576 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); 5577 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); 5578 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); 5579 5580 /* 5581 * Set SCSI_CFG0 Microcode Default Value. 5582 * 5583 * The microcode will set the SCSI_CFG0 register using this value 5584 * after it is started below. 5585 */ 5586 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 5587 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 5588 asc_dvc->chip_scsi_id); 5589 5590 /* 5591 * Calculate SCSI_CFG1 Microcode Default Value. 5592 * 5593 * The microcode will set the SCSI_CFG1 register using this value 5594 * after it is started below. 5595 * 5596 * Each ASC-38C1600 function has only two cable detect bits. 5597 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 5598 */ 5599 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5600 5601 /* 5602 * If the cable is reversed all of the SCSI_CTRL register signals 5603 * will be set. Check for and return an error if this condition is 5604 * found. 5605 */ 5606 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 5607 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 5608 return ADV_ERROR; 5609 } 5610 5611 /* 5612 * Each ASC-38C1600 function has two connectors. Only an HVD device 5613 * can not be connected to either connector. An LVD device or SE device 5614 * may be connected to either connecor. If an SE device is connected, 5615 * then at most Ultra speed (20 Mhz) can be used on both connectors. 5616 * 5617 * If an HVD device is attached, return an error. 5618 */ 5619 if (scsi_cfg1 & HVD) { 5620 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE; 5621 return ADV_ERROR; 5622 } 5623 5624 /* 5625 * Each function in the ASC-38C1600 uses only the SE cable detect and 5626 * termination because there are two connectors for each function. Each 5627 * function may use either LVD or SE mode. Corresponding the SE automatic 5628 * termination control EEPROM bits are used for each function. Each 5629 * function has its own EEPROM. If SE automatic control is enabled for 5630 * the function, then set the termination value based on a table listed 5631 * in a_condor.h. 5632 * 5633 * If manual termination is specified in the EEPROM for the function, 5634 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is 5635 * ready to be 'ored' into SCSI_CFG1. 5636 */ 5637 if ((asc_dvc->cfg->termination & TERM_SE) == 0) { 5638 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); 5639 /* SE automatic termination control is enabled. */ 5640 switch (scsi_cfg1 & C_DET_SE) { 5641 /* TERM_SE_HI: on, TERM_SE_LO: on */ 5642 case 0x1: 5643 case 0x2: 5644 case 0x3: 5645 asc_dvc->cfg->termination |= TERM_SE; 5646 break; 5647 5648 case 0x0: 5649 if (PCI_FUNC(pdev->devfn) == 0) { 5650 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 5651 } else { 5652 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 5653 asc_dvc->cfg->termination |= TERM_SE_HI; 5654 } 5655 break; 5656 } 5657 } 5658 5659 /* 5660 * Clear any set TERM_SE bits. 5661 */ 5662 scsi_cfg1 &= ~TERM_SE; 5663 5664 /* 5665 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 5666 */ 5667 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE); 5668 5669 /* 5670 * Clear Big Endian and Terminator Polarity bits and set possibly 5671 * modified termination control bits in the Microcode SCSI_CFG1 5672 * Register Value. 5673 * 5674 * Big Endian bit is not used even on big endian machines. 5675 */ 5676 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL); 5677 5678 /* 5679 * Set SCSI_CFG1 Microcode Default Value 5680 * 5681 * Set possibly modified termination control bits in the Microcode 5682 * SCSI_CFG1 Register Value. 5683 * 5684 * The microcode will set the SCSI_CFG1 register using this value 5685 * after it is started below. 5686 */ 5687 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 5688 5689 /* 5690 * Set MEM_CFG Microcode Default Value 5691 * 5692 * The microcode will set the MEM_CFG register using this value 5693 * after it is started below. 5694 * 5695 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 5696 * are defined. 5697 * 5698 * ASC-38C1600 has 32KB internal memory. 5699 * 5700 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come 5701 * out a special 16K Adv Library and Microcode version. After the issue 5702 * resolved, we should turn back to the 32K support. Both a_condor.h and 5703 * mcode.sas files also need to be updated. 5704 * 5705 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5706 * BIOS_EN | RAM_SZ_32KB); 5707 */ 5708 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5709 BIOS_EN | RAM_SZ_16KB); 5710 5711 /* 5712 * Set SEL_MASK Microcode Default Value 5713 * 5714 * The microcode will set the SEL_MASK register using this value 5715 * after it is started below. 5716 */ 5717 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 5718 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 5719 5720 AdvBuildCarrierFreelist(asc_dvc); 5721 5722 /* 5723 * Set-up the Host->RISC Initiator Command Queue (ICQ). 5724 */ 5725 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc); 5726 if (!asc_dvc->icq_sp) { 5727 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5728 return ADV_ERROR; 5729 } 5730 5731 /* 5732 * Set RISC ICQ physical address start value. Initialize the 5733 * COMMA register to the same value otherwise the RISC will 5734 * prematurely detect a command is available. 5735 */ 5736 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 5737 AdvWriteDWordRegister(iop_base, IOPDW_COMMA, 5738 le32_to_cpu(asc_dvc->icq_sp->carr_pa)); 5739 5740 /* 5741 * Set-up the RISC->Host Initiator Response Queue (IRQ). 5742 */ 5743 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc); 5744 if (!asc_dvc->irq_sp) { 5745 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5746 return ADV_ERROR; 5747 } 5748 5749 /* 5750 * Set RISC IRQ physical address start value. 5751 */ 5752 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 5753 asc_dvc->carr_pending_cnt = 0; 5754 5755 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 5756 (ADV_INTR_ENABLE_HOST_INTR | 5757 ADV_INTR_ENABLE_GLOBAL_INTR)); 5758 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 5759 AdvWriteWordRegister(iop_base, IOPW_PC, word); 5760 5761 /* finally, finally, gentlemen, start your engine */ 5762 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 5763 5764 /* 5765 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 5766 * Resets should be performed. The RISC has to be running 5767 * to issue a SCSI Bus Reset. 5768 */ 5769 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 5770 /* 5771 * If the BIOS Signature is present in memory, restore the 5772 * per TID microcode operating variables. 5773 */ 5774 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 5775 0x55AA) { 5776 /* 5777 * Restore per TID negotiated values. 5778 */ 5779 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5780 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5781 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5782 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 5783 tagqng_able); 5784 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 5785 AdvWriteByteLram(iop_base, 5786 ASC_MC_NUMBER_OF_MAX_CMD + tid, 5787 max_cmd[tid]); 5788 } 5789 } else { 5790 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 5791 warn_code = ASC_WARN_BUSRESET_ERROR; 5792 } 5793 } 5794 } 5795 5796 return warn_code; 5797 } 5798 5799 /* 5800 * Reset chip and SCSI Bus. 5801 * 5802 * Return Value: 5803 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 5804 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 5805 */ 5806 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc) 5807 { 5808 int status; 5809 ushort wdtr_able, sdtr_able, tagqng_able; 5810 ushort ppr_able = 0; 5811 uchar tid, max_cmd[ADV_MAX_TID + 1]; 5812 AdvPortAddr iop_base; 5813 ushort bios_sig; 5814 5815 iop_base = asc_dvc->iop_base; 5816 5817 /* 5818 * Save current per TID negotiated values. 5819 */ 5820 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5821 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5822 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 5823 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5824 } 5825 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5826 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5827 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5828 max_cmd[tid]); 5829 } 5830 5831 /* 5832 * Force the AdvInitAsc3550/38C0800Driver() function to 5833 * perform a SCSI Bus Reset by clearing the BIOS signature word. 5834 * The initialization functions assumes a SCSI Bus Reset is not 5835 * needed if the BIOS signature word is present. 5836 */ 5837 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); 5838 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0); 5839 5840 /* 5841 * Stop chip and reset it. 5842 */ 5843 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP); 5844 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET); 5845 mdelay(100); 5846 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 5847 ADV_CTRL_REG_CMD_WR_IO_REG); 5848 5849 /* 5850 * Reset Adv Library error code, if any, and try 5851 * re-initializing the chip. 5852 */ 5853 asc_dvc->err_code = 0; 5854 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 5855 status = AdvInitAsc38C1600Driver(asc_dvc); 5856 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 5857 status = AdvInitAsc38C0800Driver(asc_dvc); 5858 } else { 5859 status = AdvInitAsc3550Driver(asc_dvc); 5860 } 5861 5862 /* Translate initialization return value to status value. */ 5863 if (status == 0) { 5864 status = ADV_TRUE; 5865 } else { 5866 status = ADV_FALSE; 5867 } 5868 5869 /* 5870 * Restore the BIOS signature word. 5871 */ 5872 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); 5873 5874 /* 5875 * Restore per TID negotiated values. 5876 */ 5877 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5878 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5879 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 5880 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5881 } 5882 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5883 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5884 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5885 max_cmd[tid]); 5886 } 5887 5888 return status; 5889 } 5890 5891 /* 5892 * adv_async_callback() - Adv Library asynchronous event callback function. 5893 */ 5894 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code) 5895 { 5896 switch (code) { 5897 case ADV_ASYNC_SCSI_BUS_RESET_DET: 5898 /* 5899 * The firmware detected a SCSI Bus reset. 5900 */ 5901 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n"); 5902 break; 5903 5904 case ADV_ASYNC_RDMA_FAILURE: 5905 /* 5906 * Handle RDMA failure by resetting the SCSI Bus and 5907 * possibly the chip if it is unresponsive. Log the error 5908 * with a unique code. 5909 */ 5910 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n"); 5911 AdvResetChipAndSB(adv_dvc_varp); 5912 break; 5913 5914 case ADV_HOST_SCSI_BUS_RESET: 5915 /* 5916 * Host generated SCSI bus reset occurred. 5917 */ 5918 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n"); 5919 break; 5920 5921 default: 5922 ASC_DBG(0, "unknown code 0x%x\n", code); 5923 break; 5924 } 5925 } 5926 5927 /* 5928 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR(). 5929 * 5930 * Callback function for the Wide SCSI Adv Library. 5931 */ 5932 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp) 5933 { 5934 struct asc_board *boardp = adv_dvc_varp->drv_ptr; 5935 adv_req_t *reqp; 5936 adv_sgblk_t *sgblkp; 5937 struct scsi_cmnd *scp; 5938 u32 resid_cnt; 5939 dma_addr_t sense_addr; 5940 5941 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n", 5942 adv_dvc_varp, scsiqp); 5943 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); 5944 5945 /* 5946 * Get the adv_req_t structure for the command that has been 5947 * completed. The adv_req_t structure actually contains the 5948 * completed ADV_SCSI_REQ_Q structure. 5949 */ 5950 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag); 5951 5952 ASC_DBG(1, "scp 0x%p\n", scp); 5953 if (scp == NULL) { 5954 ASC_PRINT 5955 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n"); 5956 return; 5957 } 5958 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); 5959 5960 reqp = (adv_req_t *)scp->host_scribble; 5961 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp); 5962 if (reqp == NULL) { 5963 ASC_PRINT("adv_isr_callback: reqp is NULL\n"); 5964 return; 5965 } 5966 /* 5967 * Remove backreferences to avoid duplicate 5968 * command completions. 5969 */ 5970 scp->host_scribble = NULL; 5971 reqp->cmndp = NULL; 5972 5973 ASC_STATS(boardp->shost, callback); 5974 ASC_DBG(1, "shost 0x%p\n", boardp->shost); 5975 5976 sense_addr = le32_to_cpu(scsiqp->sense_addr); 5977 dma_unmap_single(boardp->dev, sense_addr, 5978 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 5979 5980 /* 5981 * 'done_status' contains the command's ending status. 5982 */ 5983 scp->result = 0; 5984 switch (scsiqp->done_status) { 5985 case QD_NO_ERROR: 5986 ASC_DBG(2, "QD_NO_ERROR\n"); 5987 5988 /* 5989 * Check for an underrun condition. 5990 * 5991 * If there was no error and an underrun condition, then 5992 * then return the number of underrun bytes. 5993 */ 5994 resid_cnt = le32_to_cpu(scsiqp->data_cnt); 5995 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 && 5996 resid_cnt <= scsi_bufflen(scp)) { 5997 ASC_DBG(1, "underrun condition %lu bytes\n", 5998 (ulong)resid_cnt); 5999 scsi_set_resid(scp, resid_cnt); 6000 } 6001 break; 6002 6003 case QD_WITH_ERROR: 6004 ASC_DBG(2, "QD_WITH_ERROR\n"); 6005 switch (scsiqp->host_status) { 6006 case QHSTA_NO_ERROR: 6007 set_status_byte(scp, scsiqp->scsi_status); 6008 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) { 6009 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n"); 6010 ASC_DBG_PRT_SENSE(2, scp->sense_buffer, 6011 SCSI_SENSE_BUFFERSIZE); 6012 set_driver_byte(scp, DRIVER_SENSE); 6013 } 6014 break; 6015 6016 default: 6017 /* Some other QHSTA error occurred. */ 6018 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status); 6019 set_host_byte(scp, DID_BAD_TARGET); 6020 break; 6021 } 6022 break; 6023 6024 case QD_ABORTED_BY_HOST: 6025 ASC_DBG(1, "QD_ABORTED_BY_HOST\n"); 6026 set_status_byte(scp, scsiqp->scsi_status); 6027 set_host_byte(scp, DID_ABORT); 6028 break; 6029 6030 default: 6031 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status); 6032 set_status_byte(scp, scsiqp->scsi_status); 6033 set_host_byte(scp, DID_ERROR); 6034 break; 6035 } 6036 6037 /* 6038 * If the 'init_tidmask' bit isn't already set for the target and the 6039 * current request finished normally, then set the bit for the target 6040 * to indicate that a device is present. 6041 */ 6042 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && 6043 scsiqp->done_status == QD_NO_ERROR && 6044 scsiqp->host_status == QHSTA_NO_ERROR) { 6045 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); 6046 } 6047 6048 asc_scsi_done(scp); 6049 6050 /* 6051 * Free all 'adv_sgblk_t' structures allocated for the request. 6052 */ 6053 while ((sgblkp = reqp->sgblkp) != NULL) { 6054 /* Remove 'sgblkp' from the request list. */ 6055 reqp->sgblkp = sgblkp->next_sgblkp; 6056 6057 dma_pool_free(boardp->adv_sgblk_pool, sgblkp, 6058 sgblkp->sg_addr); 6059 } 6060 6061 ASC_DBG(1, "done\n"); 6062 } 6063 6064 /* 6065 * Adv Library Interrupt Service Routine 6066 * 6067 * This function is called by a driver's interrupt service routine. 6068 * The function disables and re-enables interrupts. 6069 * 6070 * When a microcode idle command is completed, the ADV_DVC_VAR 6071 * 'idle_cmd_done' field is set to ADV_TRUE. 6072 * 6073 * Note: AdvISR() can be called when interrupts are disabled or even 6074 * when there is no hardware interrupt condition present. It will 6075 * always check for completed idle commands and microcode requests. 6076 * This is an important feature that shouldn't be changed because it 6077 * allows commands to be completed from polling mode loops. 6078 * 6079 * Return: 6080 * ADV_TRUE(1) - interrupt was pending 6081 * ADV_FALSE(0) - no interrupt was pending 6082 */ 6083 static int AdvISR(ADV_DVC_VAR *asc_dvc) 6084 { 6085 AdvPortAddr iop_base; 6086 uchar int_stat; 6087 ADV_CARR_T *free_carrp; 6088 __le32 irq_next_vpa; 6089 ADV_SCSI_REQ_Q *scsiq; 6090 adv_req_t *reqp; 6091 6092 iop_base = asc_dvc->iop_base; 6093 6094 /* Reading the register clears the interrupt. */ 6095 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG); 6096 6097 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB | 6098 ADV_INTR_STATUS_INTRC)) == 0) { 6099 return ADV_FALSE; 6100 } 6101 6102 /* 6103 * Notify the driver of an asynchronous microcode condition by 6104 * calling the adv_async_callback function. The function 6105 * is passed the microcode ASC_MC_INTRB_CODE byte value. 6106 */ 6107 if (int_stat & ADV_INTR_STATUS_INTRB) { 6108 uchar intrb_code; 6109 6110 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code); 6111 6112 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || 6113 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 6114 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 6115 asc_dvc->carr_pending_cnt != 0) { 6116 AdvWriteByteRegister(iop_base, IOPB_TICKLE, 6117 ADV_TICKLE_A); 6118 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 6119 AdvWriteByteRegister(iop_base, 6120 IOPB_TICKLE, 6121 ADV_TICKLE_NOP); 6122 } 6123 } 6124 } 6125 6126 adv_async_callback(asc_dvc, intrb_code); 6127 } 6128 6129 /* 6130 * Check if the IRQ stopper carrier contains a completed request. 6131 */ 6132 while (((irq_next_vpa = 6133 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ADV_RQ_DONE) != 0) { 6134 /* 6135 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure. 6136 * The RISC will have set 'areq_vpa' to a virtual address. 6137 * 6138 * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr 6139 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion 6140 * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr' 6141 * in AdvExeScsiQueue(). 6142 */ 6143 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa); 6144 ASC_DBG(1, "irq_sp %p areq_vpa %u\n", 6145 asc_dvc->irq_sp, pa_offset); 6146 reqp = adv_get_reqp(asc_dvc, pa_offset); 6147 scsiq = &reqp->scsi_req_q; 6148 6149 /* 6150 * Request finished with good status and the queue was not 6151 * DMAed to host memory by the firmware. Set all status fields 6152 * to indicate good status. 6153 */ 6154 if ((irq_next_vpa & ADV_RQ_GOOD) != 0) { 6155 scsiq->done_status = QD_NO_ERROR; 6156 scsiq->host_status = scsiq->scsi_status = 0; 6157 scsiq->data_cnt = 0L; 6158 } 6159 6160 /* 6161 * Advance the stopper pointer to the next carrier 6162 * ignoring the lower four bits. Free the previous 6163 * stopper carrier. 6164 */ 6165 free_carrp = asc_dvc->irq_sp; 6166 asc_dvc->irq_sp = adv_get_carrier(asc_dvc, 6167 ADV_GET_CARRP(irq_next_vpa)); 6168 6169 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va; 6170 asc_dvc->carr_freelist = free_carrp; 6171 asc_dvc->carr_pending_cnt--; 6172 6173 /* 6174 * Clear request microcode control flag. 6175 */ 6176 scsiq->cntl = 0; 6177 6178 /* 6179 * Notify the driver of the completed request by passing 6180 * the ADV_SCSI_REQ_Q pointer to its callback function. 6181 */ 6182 adv_isr_callback(asc_dvc, scsiq); 6183 /* 6184 * Note: After the driver callback function is called, 'scsiq' 6185 * can no longer be referenced. 6186 * 6187 * Fall through and continue processing other completed 6188 * requests... 6189 */ 6190 } 6191 return ADV_TRUE; 6192 } 6193 6194 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code) 6195 { 6196 if (asc_dvc->err_code == 0) { 6197 asc_dvc->err_code = err_code; 6198 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W, 6199 err_code); 6200 } 6201 return err_code; 6202 } 6203 6204 static void AscAckInterrupt(PortAddr iop_base) 6205 { 6206 uchar host_flag; 6207 uchar risc_flag; 6208 ushort loop; 6209 6210 loop = 0; 6211 do { 6212 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B); 6213 if (loop++ > 0x7FFF) { 6214 break; 6215 } 6216 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 6217 host_flag = 6218 AscReadLramByte(iop_base, 6219 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT); 6220 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, 6221 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT)); 6222 AscSetChipStatus(iop_base, CIW_INT_ACK); 6223 loop = 0; 6224 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) { 6225 AscSetChipStatus(iop_base, CIW_INT_ACK); 6226 if (loop++ > 3) { 6227 break; 6228 } 6229 } 6230 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); 6231 } 6232 6233 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time) 6234 { 6235 const uchar *period_table; 6236 int max_index; 6237 int min_index; 6238 int i; 6239 6240 period_table = asc_dvc->sdtr_period_tbl; 6241 max_index = (int)asc_dvc->max_sdtr_index; 6242 min_index = (int)asc_dvc->min_sdtr_index; 6243 if ((syn_time <= period_table[max_index])) { 6244 for (i = min_index; i < (max_index - 1); i++) { 6245 if (syn_time <= period_table[i]) { 6246 return (uchar)i; 6247 } 6248 } 6249 return (uchar)max_index; 6250 } else { 6251 return (uchar)(max_index + 1); 6252 } 6253 } 6254 6255 static uchar 6256 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset) 6257 { 6258 PortAddr iop_base = asc_dvc->iop_base; 6259 uchar sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period); 6260 EXT_MSG sdtr_buf = { 6261 .msg_type = EXTENDED_MESSAGE, 6262 .msg_len = MS_SDTR_LEN, 6263 .msg_req = EXTENDED_SDTR, 6264 .xfer_period = sdtr_period, 6265 .req_ack_offset = sdtr_offset, 6266 }; 6267 sdtr_offset &= ASC_SYN_MAX_OFFSET; 6268 6269 if (sdtr_period_index <= asc_dvc->max_sdtr_index) { 6270 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, 6271 (uchar *)&sdtr_buf, 6272 sizeof(EXT_MSG) >> 1); 6273 return ((sdtr_period_index << 4) | sdtr_offset); 6274 } else { 6275 sdtr_buf.req_ack_offset = 0; 6276 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, 6277 (uchar *)&sdtr_buf, 6278 sizeof(EXT_MSG) >> 1); 6279 return 0; 6280 } 6281 } 6282 6283 static uchar 6284 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset) 6285 { 6286 uchar byte; 6287 uchar sdtr_period_ix; 6288 6289 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period); 6290 if (sdtr_period_ix > asc_dvc->max_sdtr_index) 6291 return 0xFF; 6292 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 6293 return byte; 6294 } 6295 6296 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data) 6297 { 6298 ASC_SCSI_BIT_ID_TYPE org_id; 6299 int i; 6300 bool sta = true; 6301 6302 AscSetBank(iop_base, 1); 6303 org_id = AscReadChipDvcID(iop_base); 6304 for (i = 0; i <= ASC_MAX_TID; i++) { 6305 if (org_id == (0x01 << i)) 6306 break; 6307 } 6308 org_id = (ASC_SCSI_BIT_ID_TYPE) i; 6309 AscWriteChipDvcID(iop_base, id); 6310 if (AscReadChipDvcID(iop_base) == (0x01 << id)) { 6311 AscSetBank(iop_base, 0); 6312 AscSetChipSyn(iop_base, sdtr_data); 6313 if (AscGetChipSyn(iop_base) != sdtr_data) { 6314 sta = false; 6315 } 6316 } else { 6317 sta = false; 6318 } 6319 AscSetBank(iop_base, 1); 6320 AscWriteChipDvcID(iop_base, org_id); 6321 AscSetBank(iop_base, 0); 6322 return (sta); 6323 } 6324 6325 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no) 6326 { 6327 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); 6328 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data); 6329 } 6330 6331 static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) 6332 { 6333 EXT_MSG ext_msg; 6334 EXT_MSG out_msg; 6335 ushort halt_q_addr; 6336 bool sdtr_accept; 6337 ushort int_halt_code; 6338 ASC_SCSI_BIT_ID_TYPE scsi_busy; 6339 ASC_SCSI_BIT_ID_TYPE target_id; 6340 PortAddr iop_base; 6341 uchar tag_code; 6342 uchar q_status; 6343 uchar halt_qp; 6344 uchar sdtr_data; 6345 uchar target_ix; 6346 uchar q_cntl, tid_no; 6347 uchar cur_dvc_qng; 6348 uchar asyn_sdtr; 6349 uchar scsi_status; 6350 struct asc_board *boardp; 6351 6352 BUG_ON(!asc_dvc->drv_ptr); 6353 boardp = asc_dvc->drv_ptr; 6354 6355 iop_base = asc_dvc->iop_base; 6356 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W); 6357 6358 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B); 6359 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 6360 target_ix = AscReadLramByte(iop_base, 6361 (ushort)(halt_q_addr + 6362 (ushort)ASC_SCSIQ_B_TARGET_IX)); 6363 q_cntl = AscReadLramByte(iop_base, 6364 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL)); 6365 tid_no = ASC_TIX_TO_TID(target_ix); 6366 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no); 6367 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 6368 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 6369 } else { 6370 asyn_sdtr = 0; 6371 } 6372 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 6373 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 6374 AscSetChipSDTR(iop_base, 0, tid_no); 6375 boardp->sdtr_data[tid_no] = 0; 6376 } 6377 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6378 return; 6379 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 6380 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 6381 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 6382 boardp->sdtr_data[tid_no] = asyn_sdtr; 6383 } 6384 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6385 return; 6386 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 6387 AscMemWordCopyPtrFromLram(iop_base, 6388 ASCV_MSGIN_BEG, 6389 (uchar *)&ext_msg, 6390 sizeof(EXT_MSG) >> 1); 6391 6392 if (ext_msg.msg_type == EXTENDED_MESSAGE && 6393 ext_msg.msg_req == EXTENDED_SDTR && 6394 ext_msg.msg_len == MS_SDTR_LEN) { 6395 sdtr_accept = true; 6396 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) { 6397 6398 sdtr_accept = false; 6399 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 6400 } 6401 if ((ext_msg.xfer_period < 6402 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index]) 6403 || (ext_msg.xfer_period > 6404 asc_dvc->sdtr_period_tbl[asc_dvc-> 6405 max_sdtr_index])) { 6406 sdtr_accept = false; 6407 ext_msg.xfer_period = 6408 asc_dvc->sdtr_period_tbl[asc_dvc-> 6409 min_sdtr_index]; 6410 } 6411 if (sdtr_accept) { 6412 sdtr_data = 6413 AscCalSDTRData(asc_dvc, ext_msg.xfer_period, 6414 ext_msg.req_ack_offset); 6415 if (sdtr_data == 0xFF) { 6416 6417 q_cntl |= QC_MSG_OUT; 6418 asc_dvc->init_sdtr &= ~target_id; 6419 asc_dvc->sdtr_done &= ~target_id; 6420 AscSetChipSDTR(iop_base, asyn_sdtr, 6421 tid_no); 6422 boardp->sdtr_data[tid_no] = asyn_sdtr; 6423 } 6424 } 6425 if (ext_msg.req_ack_offset == 0) { 6426 6427 q_cntl &= ~QC_MSG_OUT; 6428 asc_dvc->init_sdtr &= ~target_id; 6429 asc_dvc->sdtr_done &= ~target_id; 6430 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 6431 } else { 6432 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) { 6433 q_cntl &= ~QC_MSG_OUT; 6434 asc_dvc->sdtr_done |= target_id; 6435 asc_dvc->init_sdtr |= target_id; 6436 asc_dvc->pci_fix_asyn_xfer &= 6437 ~target_id; 6438 sdtr_data = 6439 AscCalSDTRData(asc_dvc, 6440 ext_msg.xfer_period, 6441 ext_msg. 6442 req_ack_offset); 6443 AscSetChipSDTR(iop_base, sdtr_data, 6444 tid_no); 6445 boardp->sdtr_data[tid_no] = sdtr_data; 6446 } else { 6447 q_cntl |= QC_MSG_OUT; 6448 AscMsgOutSDTR(asc_dvc, 6449 ext_msg.xfer_period, 6450 ext_msg.req_ack_offset); 6451 asc_dvc->pci_fix_asyn_xfer &= 6452 ~target_id; 6453 sdtr_data = 6454 AscCalSDTRData(asc_dvc, 6455 ext_msg.xfer_period, 6456 ext_msg. 6457 req_ack_offset); 6458 AscSetChipSDTR(iop_base, sdtr_data, 6459 tid_no); 6460 boardp->sdtr_data[tid_no] = sdtr_data; 6461 asc_dvc->sdtr_done |= target_id; 6462 asc_dvc->init_sdtr |= target_id; 6463 } 6464 } 6465 6466 AscWriteLramByte(iop_base, 6467 (ushort)(halt_q_addr + 6468 (ushort)ASC_SCSIQ_B_CNTL), 6469 q_cntl); 6470 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6471 return; 6472 } else if (ext_msg.msg_type == EXTENDED_MESSAGE && 6473 ext_msg.msg_req == EXTENDED_WDTR && 6474 ext_msg.msg_len == MS_WDTR_LEN) { 6475 6476 ext_msg.wdtr_width = 0; 6477 AscMemWordCopyPtrToLram(iop_base, 6478 ASCV_MSGOUT_BEG, 6479 (uchar *)&ext_msg, 6480 sizeof(EXT_MSG) >> 1); 6481 q_cntl |= QC_MSG_OUT; 6482 AscWriteLramByte(iop_base, 6483 (ushort)(halt_q_addr + 6484 (ushort)ASC_SCSIQ_B_CNTL), 6485 q_cntl); 6486 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6487 return; 6488 } else { 6489 6490 ext_msg.msg_type = MESSAGE_REJECT; 6491 AscMemWordCopyPtrToLram(iop_base, 6492 ASCV_MSGOUT_BEG, 6493 (uchar *)&ext_msg, 6494 sizeof(EXT_MSG) >> 1); 6495 q_cntl |= QC_MSG_OUT; 6496 AscWriteLramByte(iop_base, 6497 (ushort)(halt_q_addr + 6498 (ushort)ASC_SCSIQ_B_CNTL), 6499 q_cntl); 6500 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6501 return; 6502 } 6503 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 6504 6505 q_cntl |= QC_REQ_SENSE; 6506 6507 if ((asc_dvc->init_sdtr & target_id) != 0) { 6508 6509 asc_dvc->sdtr_done &= ~target_id; 6510 6511 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 6512 q_cntl |= QC_MSG_OUT; 6513 AscMsgOutSDTR(asc_dvc, 6514 asc_dvc-> 6515 sdtr_period_tbl[(sdtr_data >> 4) & 6516 (uchar)(asc_dvc-> 6517 max_sdtr_index - 6518 1)], 6519 (uchar)(sdtr_data & (uchar) 6520 ASC_SYN_MAX_OFFSET)); 6521 } 6522 6523 AscWriteLramByte(iop_base, 6524 (ushort)(halt_q_addr + 6525 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); 6526 6527 tag_code = AscReadLramByte(iop_base, 6528 (ushort)(halt_q_addr + (ushort) 6529 ASC_SCSIQ_B_TAG_CODE)); 6530 tag_code &= 0xDC; 6531 if ((asc_dvc->pci_fix_asyn_xfer & target_id) 6532 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id) 6533 ) { 6534 6535 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT 6536 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 6537 6538 } 6539 AscWriteLramByte(iop_base, 6540 (ushort)(halt_q_addr + 6541 (ushort)ASC_SCSIQ_B_TAG_CODE), 6542 tag_code); 6543 6544 q_status = AscReadLramByte(iop_base, 6545 (ushort)(halt_q_addr + (ushort) 6546 ASC_SCSIQ_B_STATUS)); 6547 q_status |= (QS_READY | QS_BUSY); 6548 AscWriteLramByte(iop_base, 6549 (ushort)(halt_q_addr + 6550 (ushort)ASC_SCSIQ_B_STATUS), 6551 q_status); 6552 6553 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B); 6554 scsi_busy &= ~target_id; 6555 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy); 6556 6557 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6558 return; 6559 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 6560 6561 AscMemWordCopyPtrFromLram(iop_base, 6562 ASCV_MSGOUT_BEG, 6563 (uchar *)&out_msg, 6564 sizeof(EXT_MSG) >> 1); 6565 6566 if ((out_msg.msg_type == EXTENDED_MESSAGE) && 6567 (out_msg.msg_len == MS_SDTR_LEN) && 6568 (out_msg.msg_req == EXTENDED_SDTR)) { 6569 6570 asc_dvc->init_sdtr &= ~target_id; 6571 asc_dvc->sdtr_done &= ~target_id; 6572 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 6573 boardp->sdtr_data[tid_no] = asyn_sdtr; 6574 } 6575 q_cntl &= ~QC_MSG_OUT; 6576 AscWriteLramByte(iop_base, 6577 (ushort)(halt_q_addr + 6578 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); 6579 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6580 return; 6581 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 6582 6583 scsi_status = AscReadLramByte(iop_base, 6584 (ushort)((ushort)halt_q_addr + 6585 (ushort) 6586 ASC_SCSIQ_SCSI_STATUS)); 6587 cur_dvc_qng = 6588 AscReadLramByte(iop_base, 6589 (ushort)((ushort)ASC_QADR_BEG + 6590 (ushort)target_ix)); 6591 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) { 6592 6593 scsi_busy = AscReadLramByte(iop_base, 6594 (ushort)ASCV_SCSIBUSY_B); 6595 scsi_busy |= target_id; 6596 AscWriteLramByte(iop_base, 6597 (ushort)ASCV_SCSIBUSY_B, scsi_busy); 6598 asc_dvc->queue_full_or_busy |= target_id; 6599 6600 if (scsi_status == SAM_STAT_TASK_SET_FULL) { 6601 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 6602 cur_dvc_qng -= 1; 6603 asc_dvc->max_dvc_qng[tid_no] = 6604 cur_dvc_qng; 6605 6606 AscWriteLramByte(iop_base, 6607 (ushort)((ushort) 6608 ASCV_MAX_DVC_QNG_BEG 6609 + (ushort) 6610 tid_no), 6611 cur_dvc_qng); 6612 6613 /* 6614 * Set the device queue depth to the 6615 * number of active requests when the 6616 * QUEUE FULL condition was encountered. 6617 */ 6618 boardp->queue_full |= target_id; 6619 boardp->queue_full_cnt[tid_no] = 6620 cur_dvc_qng; 6621 } 6622 } 6623 } 6624 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6625 return; 6626 } 6627 return; 6628 } 6629 6630 /* 6631 * void 6632 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) 6633 * 6634 * Calling/Exit State: 6635 * none 6636 * 6637 * Description: 6638 * Input an ASC_QDONE_INFO structure from the chip 6639 */ 6640 static void 6641 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) 6642 { 6643 int i; 6644 ushort word; 6645 6646 AscSetChipLramAddr(iop_base, s_addr); 6647 for (i = 0; i < 2 * words; i += 2) { 6648 if (i == 10) { 6649 continue; 6650 } 6651 word = inpw(iop_base + IOP_RAM_DATA); 6652 inbuf[i] = word & 0xff; 6653 inbuf[i + 1] = (word >> 8) & 0xff; 6654 } 6655 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words); 6656 } 6657 6658 static uchar 6659 _AscCopyLramScsiDoneQ(PortAddr iop_base, 6660 ushort q_addr, 6661 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count) 6662 { 6663 ushort _val; 6664 uchar sg_queue_cnt; 6665 6666 DvcGetQinfo(iop_base, 6667 q_addr + ASC_SCSIQ_DONE_INFO_BEG, 6668 (uchar *)scsiq, 6669 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2); 6670 6671 _val = AscReadLramWord(iop_base, 6672 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS)); 6673 scsiq->q_status = (uchar)_val; 6674 scsiq->q_no = (uchar)(_val >> 8); 6675 _val = AscReadLramWord(iop_base, 6676 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL)); 6677 scsiq->cntl = (uchar)_val; 6678 sg_queue_cnt = (uchar)(_val >> 8); 6679 _val = AscReadLramWord(iop_base, 6680 (ushort)(q_addr + 6681 (ushort)ASC_SCSIQ_B_SENSE_LEN)); 6682 scsiq->sense_len = (uchar)_val; 6683 scsiq->extra_bytes = (uchar)(_val >> 8); 6684 6685 /* 6686 * Read high word of remain bytes from alternate location. 6687 */ 6688 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base, 6689 (ushort)(q_addr + 6690 (ushort) 6691 ASC_SCSIQ_W_ALT_DC1))) 6692 << 16); 6693 /* 6694 * Read low word of remain bytes from original location. 6695 */ 6696 scsiq->remain_bytes += AscReadLramWord(iop_base, 6697 (ushort)(q_addr + (ushort) 6698 ASC_SCSIQ_DW_REMAIN_XFER_CNT)); 6699 6700 scsiq->remain_bytes &= max_dma_count; 6701 return sg_queue_cnt; 6702 } 6703 6704 /* 6705 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR(). 6706 * 6707 * Interrupt callback function for the Narrow SCSI Asc Library. 6708 */ 6709 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep) 6710 { 6711 struct asc_board *boardp = asc_dvc_varp->drv_ptr; 6712 u32 srb_tag; 6713 struct scsi_cmnd *scp; 6714 6715 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep); 6716 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep); 6717 6718 /* 6719 * Decrease the srb_tag by 1 to find the SCSI command 6720 */ 6721 srb_tag = qdonep->d2.srb_tag - 1; 6722 scp = scsi_host_find_tag(boardp->shost, srb_tag); 6723 if (!scp) 6724 return; 6725 6726 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); 6727 6728 ASC_STATS(boardp->shost, callback); 6729 6730 dma_unmap_single(boardp->dev, scp->SCp.dma_handle, 6731 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 6732 /* 6733 * 'qdonep' contains the command's ending status. 6734 */ 6735 scp->result = 0; 6736 switch (qdonep->d3.done_stat) { 6737 case QD_NO_ERROR: 6738 ASC_DBG(2, "QD_NO_ERROR\n"); 6739 6740 /* 6741 * Check for an underrun condition. 6742 * 6743 * If there was no error and an underrun condition, then 6744 * return the number of underrun bytes. 6745 */ 6746 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 && 6747 qdonep->remain_bytes <= scsi_bufflen(scp)) { 6748 ASC_DBG(1, "underrun condition %u bytes\n", 6749 (unsigned)qdonep->remain_bytes); 6750 scsi_set_resid(scp, qdonep->remain_bytes); 6751 } 6752 break; 6753 6754 case QD_WITH_ERROR: 6755 ASC_DBG(2, "QD_WITH_ERROR\n"); 6756 switch (qdonep->d3.host_stat) { 6757 case QHSTA_NO_ERROR: 6758 set_status_byte(scp, qdonep->d3.scsi_stat); 6759 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) { 6760 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n"); 6761 ASC_DBG_PRT_SENSE(2, scp->sense_buffer, 6762 SCSI_SENSE_BUFFERSIZE); 6763 set_driver_byte(scp, DRIVER_SENSE); 6764 } 6765 break; 6766 6767 default: 6768 /* QHSTA error occurred */ 6769 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat); 6770 set_host_byte(scp, DID_BAD_TARGET); 6771 break; 6772 } 6773 break; 6774 6775 case QD_ABORTED_BY_HOST: 6776 ASC_DBG(1, "QD_ABORTED_BY_HOST\n"); 6777 set_status_byte(scp, qdonep->d3.scsi_stat); 6778 set_msg_byte(scp, qdonep->d3.scsi_msg); 6779 set_host_byte(scp, DID_ABORT); 6780 break; 6781 6782 default: 6783 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat); 6784 set_status_byte(scp, qdonep->d3.scsi_stat); 6785 set_msg_byte(scp, qdonep->d3.scsi_msg); 6786 set_host_byte(scp, DID_ERROR); 6787 break; 6788 } 6789 6790 /* 6791 * If the 'init_tidmask' bit isn't already set for the target and the 6792 * current request finished normally, then set the bit for the target 6793 * to indicate that a device is present. 6794 */ 6795 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && 6796 qdonep->d3.done_stat == QD_NO_ERROR && 6797 qdonep->d3.host_stat == QHSTA_NO_ERROR) { 6798 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); 6799 } 6800 6801 asc_scsi_done(scp); 6802 } 6803 6804 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc) 6805 { 6806 uchar next_qp; 6807 uchar n_q_used; 6808 uchar sg_list_qp; 6809 uchar sg_queue_cnt; 6810 uchar q_cnt; 6811 uchar done_q_tail; 6812 uchar tid_no; 6813 ASC_SCSI_BIT_ID_TYPE scsi_busy; 6814 ASC_SCSI_BIT_ID_TYPE target_id; 6815 PortAddr iop_base; 6816 ushort q_addr; 6817 ushort sg_q_addr; 6818 uchar cur_target_qng; 6819 ASC_QDONE_INFO scsiq_buf; 6820 ASC_QDONE_INFO *scsiq; 6821 bool false_overrun; 6822 6823 iop_base = asc_dvc->iop_base; 6824 n_q_used = 1; 6825 scsiq = (ASC_QDONE_INFO *)&scsiq_buf; 6826 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base); 6827 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 6828 next_qp = AscReadLramByte(iop_base, 6829 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD)); 6830 if (next_qp != ASC_QLINK_END) { 6831 AscPutVarDoneQTail(iop_base, next_qp); 6832 q_addr = ASC_QNO_TO_QADDR(next_qp); 6833 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq, 6834 asc_dvc->max_dma_count); 6835 AscWriteLramByte(iop_base, 6836 (ushort)(q_addr + 6837 (ushort)ASC_SCSIQ_B_STATUS), 6838 (uchar)(scsiq-> 6839 q_status & (uchar)~(QS_READY | 6840 QS_ABORTED))); 6841 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 6842 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 6843 if ((scsiq->cntl & QC_SG_HEAD) != 0) { 6844 sg_q_addr = q_addr; 6845 sg_list_qp = next_qp; 6846 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 6847 sg_list_qp = AscReadLramByte(iop_base, 6848 (ushort)(sg_q_addr 6849 + (ushort) 6850 ASC_SCSIQ_B_FWD)); 6851 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 6852 if (sg_list_qp == ASC_QLINK_END) { 6853 AscSetLibErrorCode(asc_dvc, 6854 ASCQ_ERR_SG_Q_LINKS); 6855 scsiq->d3.done_stat = QD_WITH_ERROR; 6856 scsiq->d3.host_stat = 6857 QHSTA_D_QDONE_SG_LIST_CORRUPTED; 6858 goto FATAL_ERR_QDONE; 6859 } 6860 AscWriteLramByte(iop_base, 6861 (ushort)(sg_q_addr + (ushort) 6862 ASC_SCSIQ_B_STATUS), 6863 QS_FREE); 6864 } 6865 n_q_used = sg_queue_cnt + 1; 6866 AscPutVarDoneQTail(iop_base, sg_list_qp); 6867 } 6868 if (asc_dvc->queue_full_or_busy & target_id) { 6869 cur_target_qng = AscReadLramByte(iop_base, 6870 (ushort)((ushort) 6871 ASC_QADR_BEG 6872 + (ushort) 6873 scsiq->d2. 6874 target_ix)); 6875 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) { 6876 scsi_busy = AscReadLramByte(iop_base, (ushort) 6877 ASCV_SCSIBUSY_B); 6878 scsi_busy &= ~target_id; 6879 AscWriteLramByte(iop_base, 6880 (ushort)ASCV_SCSIBUSY_B, 6881 scsi_busy); 6882 asc_dvc->queue_full_or_busy &= ~target_id; 6883 } 6884 } 6885 if (asc_dvc->cur_total_qng >= n_q_used) { 6886 asc_dvc->cur_total_qng -= n_q_used; 6887 if (asc_dvc->cur_dvc_qng[tid_no] != 0) { 6888 asc_dvc->cur_dvc_qng[tid_no]--; 6889 } 6890 } else { 6891 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG); 6892 scsiq->d3.done_stat = QD_WITH_ERROR; 6893 goto FATAL_ERR_QDONE; 6894 } 6895 if ((scsiq->d2.srb_tag == 0UL) || 6896 ((scsiq->q_status & QS_ABORTED) != 0)) { 6897 return (0x11); 6898 } else if (scsiq->q_status == QS_DONE) { 6899 /* 6900 * This is also curious. 6901 * false_overrun will _always_ be set to 'false' 6902 */ 6903 false_overrun = false; 6904 if (scsiq->extra_bytes != 0) { 6905 scsiq->remain_bytes += scsiq->extra_bytes; 6906 } 6907 if (scsiq->d3.done_stat == QD_WITH_ERROR) { 6908 if (scsiq->d3.host_stat == 6909 QHSTA_M_DATA_OVER_RUN) { 6910 if ((scsiq-> 6911 cntl & (QC_DATA_IN | QC_DATA_OUT)) 6912 == 0) { 6913 scsiq->d3.done_stat = 6914 QD_NO_ERROR; 6915 scsiq->d3.host_stat = 6916 QHSTA_NO_ERROR; 6917 } else if (false_overrun) { 6918 scsiq->d3.done_stat = 6919 QD_NO_ERROR; 6920 scsiq->d3.host_stat = 6921 QHSTA_NO_ERROR; 6922 } 6923 } else if (scsiq->d3.host_stat == 6924 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 6925 AscStopChip(iop_base); 6926 AscSetChipControl(iop_base, 6927 (uchar)(CC_SCSI_RESET 6928 | CC_HALT)); 6929 udelay(60); 6930 AscSetChipControl(iop_base, CC_HALT); 6931 AscSetChipStatus(iop_base, 6932 CIW_CLR_SCSI_RESET_INT); 6933 AscSetChipStatus(iop_base, 0); 6934 AscSetChipControl(iop_base, 0); 6935 } 6936 } 6937 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { 6938 asc_isr_callback(asc_dvc, scsiq); 6939 } else { 6940 if ((AscReadLramByte(iop_base, 6941 (ushort)(q_addr + (ushort) 6942 ASC_SCSIQ_CDB_BEG)) 6943 == START_STOP)) { 6944 asc_dvc->unit_not_ready &= ~target_id; 6945 if (scsiq->d3.done_stat != QD_NO_ERROR) { 6946 asc_dvc->start_motor &= 6947 ~target_id; 6948 } 6949 } 6950 } 6951 return (1); 6952 } else { 6953 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS); 6954 FATAL_ERR_QDONE: 6955 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { 6956 asc_isr_callback(asc_dvc, scsiq); 6957 } 6958 return (0x80); 6959 } 6960 } 6961 return (0); 6962 } 6963 6964 static int AscISR(ASC_DVC_VAR *asc_dvc) 6965 { 6966 ASC_CS_TYPE chipstat; 6967 PortAddr iop_base; 6968 ushort saved_ram_addr; 6969 uchar ctrl_reg; 6970 uchar saved_ctrl_reg; 6971 int int_pending; 6972 int status; 6973 uchar host_flag; 6974 6975 iop_base = asc_dvc->iop_base; 6976 int_pending = ASC_FALSE; 6977 6978 if (AscIsIntPending(iop_base) == 0) 6979 return int_pending; 6980 6981 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) { 6982 return ASC_ERROR; 6983 } 6984 if (asc_dvc->in_critical_cnt != 0) { 6985 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL); 6986 return ASC_ERROR; 6987 } 6988 if (asc_dvc->is_in_int) { 6989 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY); 6990 return ASC_ERROR; 6991 } 6992 asc_dvc->is_in_int = true; 6993 ctrl_reg = AscGetChipControl(iop_base); 6994 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET | 6995 CC_SINGLE_STEP | CC_DIAG | CC_TEST)); 6996 chipstat = AscGetChipStatus(iop_base); 6997 if (chipstat & CSW_SCSI_RESET_LATCH) { 6998 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 6999 int i = 10; 7000 int_pending = ASC_TRUE; 7001 asc_dvc->sdtr_done = 0; 7002 saved_ctrl_reg &= (uchar)(~CC_HALT); 7003 while ((AscGetChipStatus(iop_base) & 7004 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) { 7005 mdelay(100); 7006 } 7007 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT)); 7008 AscSetChipControl(iop_base, CC_HALT); 7009 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); 7010 AscSetChipStatus(iop_base, 0); 7011 chipstat = AscGetChipStatus(iop_base); 7012 } 7013 } 7014 saved_ram_addr = AscGetChipLramAddr(iop_base); 7015 host_flag = AscReadLramByte(iop_base, 7016 ASCV_HOST_FLAG_B) & 7017 (uchar)(~ASC_HOST_FLAG_IN_ISR); 7018 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, 7019 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR)); 7020 if ((chipstat & CSW_INT_PENDING) || (int_pending)) { 7021 AscAckInterrupt(iop_base); 7022 int_pending = ASC_TRUE; 7023 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) { 7024 AscIsrChipHalted(asc_dvc); 7025 saved_ctrl_reg &= (uchar)(~CC_HALT); 7026 } else { 7027 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) { 7028 while (((status = 7029 AscIsrQDone(asc_dvc)) & 0x01) != 0) { 7030 } 7031 } else { 7032 do { 7033 if ((status = 7034 AscIsrQDone(asc_dvc)) == 1) { 7035 break; 7036 } 7037 } while (status == 0x11); 7038 } 7039 if ((status & 0x80) != 0) 7040 int_pending = ASC_ERROR; 7041 } 7042 } 7043 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); 7044 AscSetChipLramAddr(iop_base, saved_ram_addr); 7045 AscSetChipControl(iop_base, saved_ctrl_reg); 7046 asc_dvc->is_in_int = false; 7047 return int_pending; 7048 } 7049 7050 /* 7051 * advansys_reset() 7052 * 7053 * Reset the host associated with the command 'scp'. 7054 * 7055 * This function runs its own thread. Interrupts must be blocked but 7056 * sleeping is allowed and no locking other than for host structures is 7057 * required. Returns SUCCESS or FAILED. 7058 */ 7059 static int advansys_reset(struct scsi_cmnd *scp) 7060 { 7061 struct Scsi_Host *shost = scp->device->host; 7062 struct asc_board *boardp = shost_priv(shost); 7063 unsigned long flags; 7064 int status; 7065 int ret = SUCCESS; 7066 7067 ASC_DBG(1, "0x%p\n", scp); 7068 7069 ASC_STATS(shost, reset); 7070 7071 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n"); 7072 7073 if (ASC_NARROW_BOARD(boardp)) { 7074 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; 7075 7076 /* Reset the chip and SCSI bus. */ 7077 ASC_DBG(1, "before AscInitAsc1000Driver()\n"); 7078 status = AscInitAsc1000Driver(asc_dvc); 7079 7080 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */ 7081 if (asc_dvc->err_code || !asc_dvc->overrun_dma) { 7082 scmd_printk(KERN_INFO, scp, "SCSI host reset error: " 7083 "0x%x, status: 0x%x\n", asc_dvc->err_code, 7084 status); 7085 ret = FAILED; 7086 } else if (status) { 7087 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: " 7088 "0x%x\n", status); 7089 } else { 7090 scmd_printk(KERN_INFO, scp, "SCSI host reset " 7091 "successful\n"); 7092 } 7093 7094 ASC_DBG(1, "after AscInitAsc1000Driver()\n"); 7095 } else { 7096 /* 7097 * If the suggest reset bus flags are set, then reset the bus. 7098 * Otherwise only reset the device. 7099 */ 7100 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var; 7101 7102 /* 7103 * Reset the chip and SCSI bus. 7104 */ 7105 ASC_DBG(1, "before AdvResetChipAndSB()\n"); 7106 switch (AdvResetChipAndSB(adv_dvc)) { 7107 case ASC_TRUE: 7108 scmd_printk(KERN_INFO, scp, "SCSI host reset " 7109 "successful\n"); 7110 break; 7111 case ASC_FALSE: 7112 default: 7113 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n"); 7114 ret = FAILED; 7115 break; 7116 } 7117 spin_lock_irqsave(shost->host_lock, flags); 7118 AdvISR(adv_dvc); 7119 spin_unlock_irqrestore(shost->host_lock, flags); 7120 } 7121 7122 ASC_DBG(1, "ret %d\n", ret); 7123 7124 return ret; 7125 } 7126 7127 /* 7128 * advansys_biosparam() 7129 * 7130 * Translate disk drive geometry if the "BIOS greater than 1 GB" 7131 * support is enabled for a drive. 7132 * 7133 * ip (information pointer) is an int array with the following definition: 7134 * ip[0]: heads 7135 * ip[1]: sectors 7136 * ip[2]: cylinders 7137 */ 7138 static int 7139 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev, 7140 sector_t capacity, int ip[]) 7141 { 7142 struct asc_board *boardp = shost_priv(sdev->host); 7143 7144 ASC_DBG(1, "begin\n"); 7145 ASC_STATS(sdev->host, biosparam); 7146 if (ASC_NARROW_BOARD(boardp)) { 7147 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl & 7148 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) { 7149 ip[0] = 255; 7150 ip[1] = 63; 7151 } else { 7152 ip[0] = 64; 7153 ip[1] = 32; 7154 } 7155 } else { 7156 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl & 7157 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) { 7158 ip[0] = 255; 7159 ip[1] = 63; 7160 } else { 7161 ip[0] = 64; 7162 ip[1] = 32; 7163 } 7164 } 7165 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]); 7166 ASC_DBG(1, "end\n"); 7167 return 0; 7168 } 7169 7170 /* 7171 * First-level interrupt handler. 7172 * 7173 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host. 7174 */ 7175 static irqreturn_t advansys_interrupt(int irq, void *dev_id) 7176 { 7177 struct Scsi_Host *shost = dev_id; 7178 struct asc_board *boardp = shost_priv(shost); 7179 irqreturn_t result = IRQ_NONE; 7180 unsigned long flags; 7181 7182 ASC_DBG(2, "boardp 0x%p\n", boardp); 7183 spin_lock_irqsave(shost->host_lock, flags); 7184 if (ASC_NARROW_BOARD(boardp)) { 7185 if (AscIsIntPending(shost->io_port)) { 7186 result = IRQ_HANDLED; 7187 ASC_STATS(shost, interrupt); 7188 ASC_DBG(1, "before AscISR()\n"); 7189 AscISR(&boardp->dvc_var.asc_dvc_var); 7190 } 7191 } else { 7192 ASC_DBG(1, "before AdvISR()\n"); 7193 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) { 7194 result = IRQ_HANDLED; 7195 ASC_STATS(shost, interrupt); 7196 } 7197 } 7198 spin_unlock_irqrestore(shost->host_lock, flags); 7199 7200 ASC_DBG(1, "end\n"); 7201 return result; 7202 } 7203 7204 static bool AscHostReqRiscHalt(PortAddr iop_base) 7205 { 7206 int count = 0; 7207 bool sta = false; 7208 uchar saved_stop_code; 7209 7210 if (AscIsChipHalted(iop_base)) 7211 return true; 7212 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B); 7213 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 7214 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 7215 do { 7216 if (AscIsChipHalted(iop_base)) { 7217 sta = true; 7218 break; 7219 } 7220 mdelay(100); 7221 } while (count++ < 20); 7222 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code); 7223 return sta; 7224 } 7225 7226 static bool 7227 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data) 7228 { 7229 bool sta = false; 7230 7231 if (AscHostReqRiscHalt(iop_base)) { 7232 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); 7233 AscStartChip(iop_base); 7234 } 7235 return sta; 7236 } 7237 7238 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev) 7239 { 7240 char type = sdev->type; 7241 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id; 7242 7243 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)) 7244 return; 7245 if (asc_dvc->init_sdtr & tid_bits) 7246 return; 7247 7248 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0)) 7249 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits; 7250 7251 asc_dvc->pci_fix_asyn_xfer |= tid_bits; 7252 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) || 7253 (type == TYPE_ROM) || (type == TYPE_TAPE)) 7254 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits; 7255 7256 if (asc_dvc->pci_fix_asyn_xfer & tid_bits) 7257 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id, 7258 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 7259 } 7260 7261 static void 7262 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc) 7263 { 7264 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id; 7265 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng; 7266 7267 if (sdev->lun == 0) { 7268 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr; 7269 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) { 7270 asc_dvc->init_sdtr |= tid_bit; 7271 } else { 7272 asc_dvc->init_sdtr &= ~tid_bit; 7273 } 7274 7275 if (orig_init_sdtr != asc_dvc->init_sdtr) 7276 AscAsyncFix(asc_dvc, sdev); 7277 } 7278 7279 if (sdev->tagged_supported) { 7280 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) { 7281 if (sdev->lun == 0) { 7282 asc_dvc->cfg->can_tagged_qng |= tid_bit; 7283 asc_dvc->use_tagged_qng |= tid_bit; 7284 } 7285 scsi_change_queue_depth(sdev, 7286 asc_dvc->max_dvc_qng[sdev->id]); 7287 } 7288 } else { 7289 if (sdev->lun == 0) { 7290 asc_dvc->cfg->can_tagged_qng &= ~tid_bit; 7291 asc_dvc->use_tagged_qng &= ~tid_bit; 7292 } 7293 } 7294 7295 if ((sdev->lun == 0) && 7296 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) { 7297 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B, 7298 asc_dvc->cfg->disc_enable); 7299 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B, 7300 asc_dvc->use_tagged_qng); 7301 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B, 7302 asc_dvc->cfg->can_tagged_qng); 7303 7304 asc_dvc->max_dvc_qng[sdev->id] = 7305 asc_dvc->cfg->max_tag_qng[sdev->id]; 7306 AscWriteLramByte(asc_dvc->iop_base, 7307 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id), 7308 asc_dvc->max_dvc_qng[sdev->id]); 7309 } 7310 } 7311 7312 /* 7313 * Wide Transfers 7314 * 7315 * If the EEPROM enabled WDTR for the device and the device supports wide 7316 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and 7317 * write the new value to the microcode. 7318 */ 7319 static void 7320 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask) 7321 { 7322 unsigned short cfg_word; 7323 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); 7324 if ((cfg_word & tidmask) != 0) 7325 return; 7326 7327 cfg_word |= tidmask; 7328 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); 7329 7330 /* 7331 * Clear the microcode SDTR and WDTR negotiation done indicators for 7332 * the target to cause it to negotiate with the new setting set above. 7333 * WDTR when accepted causes the target to enter asynchronous mode, so 7334 * SDTR must be negotiated. 7335 */ 7336 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7337 cfg_word &= ~tidmask; 7338 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7339 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); 7340 cfg_word &= ~tidmask; 7341 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); 7342 } 7343 7344 /* 7345 * Synchronous Transfers 7346 * 7347 * If the EEPROM enabled SDTR for the device and the device 7348 * supports synchronous transfers, then turn on the device's 7349 * 'sdtr_able' bit. Write the new value to the microcode. 7350 */ 7351 static void 7352 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask) 7353 { 7354 unsigned short cfg_word; 7355 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); 7356 if ((cfg_word & tidmask) != 0) 7357 return; 7358 7359 cfg_word |= tidmask; 7360 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); 7361 7362 /* 7363 * Clear the microcode "SDTR negotiation" done indicator for the 7364 * target to cause it to negotiate with the new setting set above. 7365 */ 7366 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7367 cfg_word &= ~tidmask; 7368 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7369 } 7370 7371 /* 7372 * PPR (Parallel Protocol Request) Capable 7373 * 7374 * If the device supports DT mode, then it must be PPR capable. 7375 * The PPR message will be used in place of the SDTR and WDTR 7376 * messages to negotiate synchronous speed and offset, transfer 7377 * width, and protocol options. 7378 */ 7379 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc, 7380 AdvPortAddr iop_base, unsigned short tidmask) 7381 { 7382 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); 7383 adv_dvc->ppr_able |= tidmask; 7384 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); 7385 } 7386 7387 static void 7388 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc) 7389 { 7390 AdvPortAddr iop_base = adv_dvc->iop_base; 7391 unsigned short tidmask = 1 << sdev->id; 7392 7393 if (sdev->lun == 0) { 7394 /* 7395 * Handle WDTR, SDTR, and Tag Queuing. If the feature 7396 * is enabled in the EEPROM and the device supports the 7397 * feature, then enable it in the microcode. 7398 */ 7399 7400 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr) 7401 advansys_wide_enable_wdtr(iop_base, tidmask); 7402 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr) 7403 advansys_wide_enable_sdtr(iop_base, tidmask); 7404 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr) 7405 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask); 7406 7407 /* 7408 * Tag Queuing is disabled for the BIOS which runs in polled 7409 * mode and would see no benefit from Tag Queuing. Also by 7410 * disabling Tag Queuing in the BIOS devices with Tag Queuing 7411 * bugs will at least work with the BIOS. 7412 */ 7413 if ((adv_dvc->tagqng_able & tidmask) && 7414 sdev->tagged_supported) { 7415 unsigned short cfg_word; 7416 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word); 7417 cfg_word |= tidmask; 7418 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 7419 cfg_word); 7420 AdvWriteByteLram(iop_base, 7421 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id, 7422 adv_dvc->max_dvc_qng); 7423 } 7424 } 7425 7426 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) 7427 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng); 7428 } 7429 7430 /* 7431 * Set the number of commands to queue per device for the 7432 * specified host adapter. 7433 */ 7434 static int advansys_slave_configure(struct scsi_device *sdev) 7435 { 7436 struct asc_board *boardp = shost_priv(sdev->host); 7437 7438 if (ASC_NARROW_BOARD(boardp)) 7439 advansys_narrow_slave_configure(sdev, 7440 &boardp->dvc_var.asc_dvc_var); 7441 else 7442 advansys_wide_slave_configure(sdev, 7443 &boardp->dvc_var.adv_dvc_var); 7444 7445 return 0; 7446 } 7447 7448 static __le32 asc_get_sense_buffer_dma(struct scsi_cmnd *scp) 7449 { 7450 struct asc_board *board = shost_priv(scp->device->host); 7451 7452 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer, 7453 SCSI_SENSE_BUFFERSIZE, 7454 DMA_FROM_DEVICE); 7455 if (dma_mapping_error(board->dev, scp->SCp.dma_handle)) { 7456 ASC_DBG(1, "failed to map sense buffer\n"); 7457 return 0; 7458 } 7459 return cpu_to_le32(scp->SCp.dma_handle); 7460 } 7461 7462 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, 7463 struct asc_scsi_q *asc_scsi_q) 7464 { 7465 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var; 7466 int use_sg; 7467 u32 srb_tag; 7468 7469 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q)); 7470 7471 /* 7472 * Set the srb_tag to the command tag + 1, as 7473 * srb_tag '0' is used internally by the chip. 7474 */ 7475 srb_tag = scp->request->tag + 1; 7476 asc_scsi_q->q2.srb_tag = srb_tag; 7477 7478 /* 7479 * Build the ASC_SCSI_Q request. 7480 */ 7481 asc_scsi_q->cdbptr = &scp->cmnd[0]; 7482 asc_scsi_q->q2.cdb_len = scp->cmd_len; 7483 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id); 7484 asc_scsi_q->q1.target_lun = scp->device->lun; 7485 asc_scsi_q->q2.target_ix = 7486 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun); 7487 asc_scsi_q->q1.sense_addr = asc_get_sense_buffer_dma(scp); 7488 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE; 7489 if (!asc_scsi_q->q1.sense_addr) 7490 return ASC_BUSY; 7491 7492 /* 7493 * If there are any outstanding requests for the current target, 7494 * then every 255th request send an ORDERED request. This heuristic 7495 * tries to retain the benefit of request sorting while preventing 7496 * request starvation. 255 is the max number of tags or pending commands 7497 * a device may have outstanding. 7498 * 7499 * The request count is incremented below for every successfully 7500 * started request. 7501 * 7502 */ 7503 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) && 7504 (boardp->reqcnt[scp->device->id] % 255) == 0) { 7505 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG; 7506 } else { 7507 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG; 7508 } 7509 7510 /* Build ASC_SCSI_Q */ 7511 use_sg = scsi_dma_map(scp); 7512 if (use_sg < 0) { 7513 ASC_DBG(1, "failed to map sglist\n"); 7514 return ASC_BUSY; 7515 } else if (use_sg > 0) { 7516 int sgcnt; 7517 struct scatterlist *slp; 7518 struct asc_sg_head *asc_sg_head; 7519 7520 if (use_sg > scp->device->host->sg_tablesize) { 7521 scmd_printk(KERN_ERR, scp, "use_sg %d > " 7522 "sg_tablesize %d\n", use_sg, 7523 scp->device->host->sg_tablesize); 7524 scsi_dma_unmap(scp); 7525 set_host_byte(scp, DID_ERROR); 7526 return ASC_ERROR; 7527 } 7528 7529 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) + 7530 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC); 7531 if (!asc_sg_head) { 7532 scsi_dma_unmap(scp); 7533 set_host_byte(scp, DID_SOFT_ERROR); 7534 return ASC_ERROR; 7535 } 7536 7537 asc_scsi_q->q1.cntl |= QC_SG_HEAD; 7538 asc_scsi_q->sg_head = asc_sg_head; 7539 asc_scsi_q->q1.data_cnt = 0; 7540 asc_scsi_q->q1.data_addr = 0; 7541 /* This is a byte value, otherwise it would need to be swapped. */ 7542 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg; 7543 ASC_STATS_ADD(scp->device->host, xfer_elem, 7544 asc_sg_head->entry_cnt); 7545 7546 /* 7547 * Convert scatter-gather list into ASC_SG_HEAD list. 7548 */ 7549 scsi_for_each_sg(scp, slp, use_sg, sgcnt) { 7550 asc_sg_head->sg_list[sgcnt].addr = 7551 cpu_to_le32(sg_dma_address(slp)); 7552 asc_sg_head->sg_list[sgcnt].bytes = 7553 cpu_to_le32(sg_dma_len(slp)); 7554 ASC_STATS_ADD(scp->device->host, xfer_sect, 7555 DIV_ROUND_UP(sg_dma_len(slp), 512)); 7556 } 7557 } 7558 7559 ASC_STATS(scp->device->host, xfer_cnt); 7560 7561 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q); 7562 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); 7563 7564 return ASC_NOERROR; 7565 } 7566 7567 /* 7568 * Build scatter-gather list for Adv Library (Wide Board). 7569 * 7570 * Additional ADV_SG_BLOCK structures will need to be allocated 7571 * if the total number of scatter-gather elements exceeds 7572 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are 7573 * assumed to be physically contiguous. 7574 * 7575 * Return: 7576 * ADV_SUCCESS(1) - SG List successfully created 7577 * ADV_ERROR(-1) - SG List creation failed 7578 */ 7579 static int 7580 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, 7581 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg) 7582 { 7583 adv_sgblk_t *sgblkp, *prev_sgblkp; 7584 struct scatterlist *slp; 7585 int sg_elem_cnt; 7586 ADV_SG_BLOCK *sg_block, *prev_sg_block; 7587 dma_addr_t sgblk_paddr; 7588 int i; 7589 7590 slp = scsi_sglist(scp); 7591 sg_elem_cnt = use_sg; 7592 prev_sgblkp = NULL; 7593 prev_sg_block = NULL; 7594 reqp->sgblkp = NULL; 7595 7596 for (;;) { 7597 /* 7598 * Allocate a 'adv_sgblk_t' structure from the board free 7599 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK 7600 * (15) scatter-gather elements. 7601 */ 7602 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC, 7603 &sgblk_paddr); 7604 if (!sgblkp) { 7605 ASC_DBG(1, "no free adv_sgblk_t\n"); 7606 ASC_STATS(scp->device->host, adv_build_nosg); 7607 7608 /* 7609 * Allocation failed. Free 'adv_sgblk_t' structures 7610 * already allocated for the request. 7611 */ 7612 while ((sgblkp = reqp->sgblkp) != NULL) { 7613 /* Remove 'sgblkp' from the request list. */ 7614 reqp->sgblkp = sgblkp->next_sgblkp; 7615 sgblkp->next_sgblkp = NULL; 7616 dma_pool_free(boardp->adv_sgblk_pool, sgblkp, 7617 sgblkp->sg_addr); 7618 } 7619 return ASC_BUSY; 7620 } 7621 /* Complete 'adv_sgblk_t' board allocation. */ 7622 sgblkp->sg_addr = sgblk_paddr; 7623 sgblkp->next_sgblkp = NULL; 7624 sg_block = &sgblkp->sg_block; 7625 7626 /* 7627 * Check if this is the first 'adv_sgblk_t' for the 7628 * request. 7629 */ 7630 if (reqp->sgblkp == NULL) { 7631 /* Request's first scatter-gather block. */ 7632 reqp->sgblkp = sgblkp; 7633 7634 /* 7635 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical 7636 * address pointers. 7637 */ 7638 scsiqp->sg_list_ptr = sg_block; 7639 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr); 7640 } else { 7641 /* Request's second or later scatter-gather block. */ 7642 prev_sgblkp->next_sgblkp = sgblkp; 7643 7644 /* 7645 * Point the previous ADV_SG_BLOCK structure to 7646 * the newly allocated ADV_SG_BLOCK structure. 7647 */ 7648 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr); 7649 } 7650 7651 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 7652 sg_block->sg_list[i].sg_addr = 7653 cpu_to_le32(sg_dma_address(slp)); 7654 sg_block->sg_list[i].sg_count = 7655 cpu_to_le32(sg_dma_len(slp)); 7656 ASC_STATS_ADD(scp->device->host, xfer_sect, 7657 DIV_ROUND_UP(sg_dma_len(slp), 512)); 7658 7659 if (--sg_elem_cnt == 0) { 7660 /* 7661 * Last ADV_SG_BLOCK and scatter-gather entry. 7662 */ 7663 sg_block->sg_cnt = i + 1; 7664 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */ 7665 return ADV_SUCCESS; 7666 } 7667 slp = sg_next(slp); 7668 } 7669 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 7670 prev_sg_block = sg_block; 7671 prev_sgblkp = sgblkp; 7672 } 7673 } 7674 7675 /* 7676 * Build a request structure for the Adv Library (Wide Board). 7677 * 7678 * If an adv_req_t can not be allocated to issue the request, 7679 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR. 7680 * 7681 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the 7682 * microcode for DMA addresses or math operations are byte swapped 7683 * to little-endian order. 7684 */ 7685 static int 7686 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, 7687 adv_req_t **adv_reqpp) 7688 { 7689 u32 srb_tag = scp->request->tag; 7690 adv_req_t *reqp; 7691 ADV_SCSI_REQ_Q *scsiqp; 7692 int ret; 7693 int use_sg; 7694 dma_addr_t sense_addr; 7695 7696 /* 7697 * Allocate an adv_req_t structure from the board to execute 7698 * the command. 7699 */ 7700 reqp = &boardp->adv_reqp[srb_tag]; 7701 if (reqp->cmndp && reqp->cmndp != scp ) { 7702 ASC_DBG(1, "no free adv_req_t\n"); 7703 ASC_STATS(scp->device->host, adv_build_noreq); 7704 return ASC_BUSY; 7705 } 7706 7707 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t)); 7708 7709 scsiqp = &reqp->scsi_req_q; 7710 7711 /* 7712 * Initialize the structure. 7713 */ 7714 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0; 7715 7716 /* 7717 * Set the srb_tag to the command tag. 7718 */ 7719 scsiqp->srb_tag = srb_tag; 7720 7721 /* 7722 * Set 'host_scribble' to point to the adv_req_t structure. 7723 */ 7724 reqp->cmndp = scp; 7725 scp->host_scribble = (void *)reqp; 7726 7727 /* 7728 * Build the ADV_SCSI_REQ_Q request. 7729 */ 7730 7731 /* Set CDB length and copy it to the request structure. */ 7732 scsiqp->cdb_len = scp->cmd_len; 7733 /* Copy first 12 CDB bytes to cdb[]. */ 7734 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12); 7735 /* Copy last 4 CDB bytes, if present, to cdb16[]. */ 7736 if (scp->cmd_len > 12) { 7737 int cdb16_len = scp->cmd_len - 12; 7738 7739 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len); 7740 } 7741 7742 scsiqp->target_id = scp->device->id; 7743 scsiqp->target_lun = scp->device->lun; 7744 7745 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer, 7746 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 7747 if (dma_mapping_error(boardp->dev, sense_addr)) { 7748 ASC_DBG(1, "failed to map sense buffer\n"); 7749 ASC_STATS(scp->device->host, adv_build_noreq); 7750 return ASC_BUSY; 7751 } 7752 scsiqp->sense_addr = cpu_to_le32(sense_addr); 7753 scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE; 7754 7755 /* Build ADV_SCSI_REQ_Q */ 7756 7757 use_sg = scsi_dma_map(scp); 7758 if (use_sg < 0) { 7759 ASC_DBG(1, "failed to map SG list\n"); 7760 ASC_STATS(scp->device->host, adv_build_noreq); 7761 return ASC_BUSY; 7762 } else if (use_sg == 0) { 7763 /* Zero-length transfer */ 7764 reqp->sgblkp = NULL; 7765 scsiqp->data_cnt = 0; 7766 7767 scsiqp->data_addr = 0; 7768 scsiqp->sg_list_ptr = NULL; 7769 scsiqp->sg_real_addr = 0; 7770 } else { 7771 if (use_sg > ADV_MAX_SG_LIST) { 7772 scmd_printk(KERN_ERR, scp, "use_sg %d > " 7773 "ADV_MAX_SG_LIST %d\n", use_sg, 7774 scp->device->host->sg_tablesize); 7775 scsi_dma_unmap(scp); 7776 set_host_byte(scp, DID_ERROR); 7777 reqp->cmndp = NULL; 7778 scp->host_scribble = NULL; 7779 7780 return ASC_ERROR; 7781 } 7782 7783 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp)); 7784 7785 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg); 7786 if (ret != ADV_SUCCESS) { 7787 scsi_dma_unmap(scp); 7788 set_host_byte(scp, DID_ERROR); 7789 reqp->cmndp = NULL; 7790 scp->host_scribble = NULL; 7791 7792 return ret; 7793 } 7794 7795 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg); 7796 } 7797 7798 ASC_STATS(scp->device->host, xfer_cnt); 7799 7800 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); 7801 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); 7802 7803 *adv_reqpp = reqp; 7804 7805 return ASC_NOERROR; 7806 } 7807 7808 static int AscSgListToQueue(int sg_list) 7809 { 7810 int n_sg_list_qs; 7811 7812 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 7813 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 7814 n_sg_list_qs++; 7815 return n_sg_list_qs + 1; 7816 } 7817 7818 static uint 7819 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs) 7820 { 7821 uint cur_used_qs; 7822 uint cur_free_qs; 7823 ASC_SCSI_BIT_ID_TYPE target_id; 7824 uchar tid_no; 7825 7826 target_id = ASC_TIX_TO_TARGET_ID(target_ix); 7827 tid_no = ASC_TIX_TO_TID(target_ix); 7828 if ((asc_dvc->unit_not_ready & target_id) || 7829 (asc_dvc->queue_full_or_busy & target_id)) { 7830 return 0; 7831 } 7832 if (n_qs == 1) { 7833 cur_used_qs = (uint) asc_dvc->cur_total_qng + 7834 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q; 7835 } else { 7836 cur_used_qs = (uint) asc_dvc->cur_total_qng + 7837 (uint) ASC_MIN_FREE_Q; 7838 } 7839 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) { 7840 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs; 7841 if (asc_dvc->cur_dvc_qng[tid_no] >= 7842 asc_dvc->max_dvc_qng[tid_no]) { 7843 return 0; 7844 } 7845 return cur_free_qs; 7846 } 7847 if (n_qs > 1) { 7848 if ((n_qs > asc_dvc->last_q_shortage) 7849 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) { 7850 asc_dvc->last_q_shortage = n_qs; 7851 } 7852 } 7853 return 0; 7854 } 7855 7856 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head) 7857 { 7858 ushort q_addr; 7859 uchar next_qp; 7860 uchar q_status; 7861 7862 q_addr = ASC_QNO_TO_QADDR(free_q_head); 7863 q_status = (uchar)AscReadLramByte(iop_base, 7864 (ushort)(q_addr + 7865 ASC_SCSIQ_B_STATUS)); 7866 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD)); 7867 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 7868 return next_qp; 7869 return ASC_QLINK_END; 7870 } 7871 7872 static uchar 7873 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q) 7874 { 7875 uchar i; 7876 7877 for (i = 0; i < n_free_q; i++) { 7878 free_q_head = AscAllocFreeQueue(iop_base, free_q_head); 7879 if (free_q_head == ASC_QLINK_END) 7880 break; 7881 } 7882 return free_q_head; 7883 } 7884 7885 /* 7886 * void 7887 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) 7888 * 7889 * Calling/Exit State: 7890 * none 7891 * 7892 * Description: 7893 * Output an ASC_SCSI_Q structure to the chip 7894 */ 7895 static void 7896 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) 7897 { 7898 int i; 7899 7900 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words); 7901 AscSetChipLramAddr(iop_base, s_addr); 7902 for (i = 0; i < 2 * words; i += 2) { 7903 if (i == 4 || i == 20) { 7904 continue; 7905 } 7906 outpw(iop_base + IOP_RAM_DATA, 7907 ((ushort)outbuf[i + 1] << 8) | outbuf[i]); 7908 } 7909 } 7910 7911 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) 7912 { 7913 ushort q_addr; 7914 uchar tid_no; 7915 uchar sdtr_data; 7916 uchar syn_period_ix; 7917 uchar syn_offset; 7918 PortAddr iop_base; 7919 7920 iop_base = asc_dvc->iop_base; 7921 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) && 7922 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) { 7923 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 7924 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 7925 syn_period_ix = 7926 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1); 7927 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 7928 AscMsgOutSDTR(asc_dvc, 7929 asc_dvc->sdtr_period_tbl[syn_period_ix], 7930 syn_offset); 7931 scsiq->q1.cntl |= QC_MSG_OUT; 7932 } 7933 q_addr = ASC_QNO_TO_QADDR(q_no); 7934 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) { 7935 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG; 7936 } 7937 scsiq->q1.status = QS_FREE; 7938 AscMemWordCopyPtrToLram(iop_base, 7939 q_addr + ASC_SCSIQ_CDB_BEG, 7940 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 7941 7942 DvcPutScsiQ(iop_base, 7943 q_addr + ASC_SCSIQ_CPY_BEG, 7944 (uchar *)&scsiq->q1.cntl, 7945 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1); 7946 AscWriteLramWord(iop_base, 7947 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS), 7948 (ushort)(((ushort)scsiq->q1. 7949 q_no << 8) | (ushort)QS_READY)); 7950 return 1; 7951 } 7952 7953 static int 7954 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) 7955 { 7956 int sta; 7957 int i; 7958 ASC_SG_HEAD *sg_head; 7959 ASC_SG_LIST_Q scsi_sg_q; 7960 __le32 saved_data_addr; 7961 __le32 saved_data_cnt; 7962 PortAddr iop_base; 7963 ushort sg_list_dwords; 7964 ushort sg_index; 7965 ushort sg_entry_cnt; 7966 ushort q_addr; 7967 uchar next_qp; 7968 7969 iop_base = asc_dvc->iop_base; 7970 sg_head = scsiq->sg_head; 7971 saved_data_addr = scsiq->q1.data_addr; 7972 saved_data_cnt = scsiq->q1.data_cnt; 7973 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr); 7974 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes); 7975 /* 7976 * Set sg_entry_cnt to be the number of SG elements that 7977 * will fit in the allocated SG queues. It is minus 1, because 7978 * the first SG element is handled above. 7979 */ 7980 sg_entry_cnt = sg_head->entry_cnt - 1; 7981 7982 if (sg_entry_cnt != 0) { 7983 scsiq->q1.cntl |= QC_SG_HEAD; 7984 q_addr = ASC_QNO_TO_QADDR(q_no); 7985 sg_index = 1; 7986 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 7987 scsi_sg_q.sg_head_qp = q_no; 7988 scsi_sg_q.cntl = QCSG_SG_XFER_LIST; 7989 for (i = 0; i < sg_head->queue_cnt; i++) { 7990 scsi_sg_q.seq_no = i + 1; 7991 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 7992 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2); 7993 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 7994 if (i == 0) { 7995 scsi_sg_q.sg_list_cnt = 7996 ASC_SG_LIST_PER_Q; 7997 scsi_sg_q.sg_cur_list_cnt = 7998 ASC_SG_LIST_PER_Q; 7999 } else { 8000 scsi_sg_q.sg_list_cnt = 8001 ASC_SG_LIST_PER_Q - 1; 8002 scsi_sg_q.sg_cur_list_cnt = 8003 ASC_SG_LIST_PER_Q - 1; 8004 } 8005 } else { 8006 scsi_sg_q.cntl |= QCSG_SG_XFER_END; 8007 sg_list_dwords = sg_entry_cnt << 1; 8008 if (i == 0) { 8009 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 8010 scsi_sg_q.sg_cur_list_cnt = 8011 sg_entry_cnt; 8012 } else { 8013 scsi_sg_q.sg_list_cnt = 8014 sg_entry_cnt - 1; 8015 scsi_sg_q.sg_cur_list_cnt = 8016 sg_entry_cnt - 1; 8017 } 8018 sg_entry_cnt = 0; 8019 } 8020 next_qp = AscReadLramByte(iop_base, 8021 (ushort)(q_addr + 8022 ASC_SCSIQ_B_FWD)); 8023 scsi_sg_q.q_no = next_qp; 8024 q_addr = ASC_QNO_TO_QADDR(next_qp); 8025 AscMemWordCopyPtrToLram(iop_base, 8026 q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 8027 (uchar *)&scsi_sg_q, 8028 sizeof(ASC_SG_LIST_Q) >> 1); 8029 AscMemDWordCopyPtrToLram(iop_base, 8030 q_addr + ASC_SGQ_LIST_BEG, 8031 (uchar *)&sg_head-> 8032 sg_list[sg_index], 8033 sg_list_dwords); 8034 sg_index += ASC_SG_LIST_PER_Q; 8035 scsiq->next_sg_index = sg_index; 8036 } 8037 } else { 8038 scsiq->q1.cntl &= ~QC_SG_HEAD; 8039 } 8040 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no); 8041 scsiq->q1.data_addr = saved_data_addr; 8042 scsiq->q1.data_cnt = saved_data_cnt; 8043 return (sta); 8044 } 8045 8046 static int 8047 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required) 8048 { 8049 PortAddr iop_base; 8050 uchar free_q_head; 8051 uchar next_qp; 8052 uchar tid_no; 8053 uchar target_ix; 8054 int sta; 8055 8056 iop_base = asc_dvc->iop_base; 8057 target_ix = scsiq->q2.target_ix; 8058 tid_no = ASC_TIX_TO_TID(target_ix); 8059 sta = 0; 8060 free_q_head = (uchar)AscGetVarFreeQHead(iop_base); 8061 if (n_q_required > 1) { 8062 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head, 8063 (uchar)n_q_required); 8064 if (next_qp != ASC_QLINK_END) { 8065 asc_dvc->last_q_shortage = 0; 8066 scsiq->sg_head->queue_cnt = n_q_required - 1; 8067 scsiq->q1.q_no = free_q_head; 8068 sta = AscPutReadySgListQueue(asc_dvc, scsiq, 8069 free_q_head); 8070 } 8071 } else if (n_q_required == 1) { 8072 next_qp = AscAllocFreeQueue(iop_base, free_q_head); 8073 if (next_qp != ASC_QLINK_END) { 8074 scsiq->q1.q_no = free_q_head; 8075 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head); 8076 } 8077 } 8078 if (sta == 1) { 8079 AscPutVarFreeQHead(iop_base, next_qp); 8080 asc_dvc->cur_total_qng += n_q_required; 8081 asc_dvc->cur_dvc_qng[tid_no]++; 8082 } 8083 return sta; 8084 } 8085 8086 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16 8087 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = { 8088 INQUIRY, 8089 REQUEST_SENSE, 8090 READ_CAPACITY, 8091 READ_TOC, 8092 MODE_SELECT, 8093 MODE_SENSE, 8094 MODE_SELECT_10, 8095 MODE_SENSE_10, 8096 0xFF, 8097 0xFF, 8098 0xFF, 8099 0xFF, 8100 0xFF, 8101 0xFF, 8102 0xFF, 8103 0xFF 8104 }; 8105 8106 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) 8107 { 8108 PortAddr iop_base; 8109 int sta; 8110 int n_q_required; 8111 bool disable_syn_offset_one_fix; 8112 int i; 8113 u32 addr; 8114 ushort sg_entry_cnt = 0; 8115 ushort sg_entry_cnt_minus_one = 0; 8116 uchar target_ix; 8117 uchar tid_no; 8118 uchar sdtr_data; 8119 uchar extra_bytes; 8120 uchar scsi_cmd; 8121 uchar disable_cmd; 8122 ASC_SG_HEAD *sg_head; 8123 unsigned long data_cnt; 8124 8125 iop_base = asc_dvc->iop_base; 8126 sg_head = scsiq->sg_head; 8127 if (asc_dvc->err_code != 0) 8128 return ASC_ERROR; 8129 scsiq->q1.q_no = 0; 8130 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) { 8131 scsiq->q1.extra_bytes = 0; 8132 } 8133 sta = 0; 8134 target_ix = scsiq->q2.target_ix; 8135 tid_no = ASC_TIX_TO_TID(target_ix); 8136 n_q_required = 1; 8137 if (scsiq->cdbptr[0] == REQUEST_SENSE) { 8138 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) { 8139 asc_dvc->sdtr_done &= ~scsiq->q1.target_id; 8140 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 8141 AscMsgOutSDTR(asc_dvc, 8142 asc_dvc-> 8143 sdtr_period_tbl[(sdtr_data >> 4) & 8144 (uchar)(asc_dvc-> 8145 max_sdtr_index - 8146 1)], 8147 (uchar)(sdtr_data & (uchar) 8148 ASC_SYN_MAX_OFFSET)); 8149 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT); 8150 } 8151 } 8152 if (asc_dvc->in_critical_cnt != 0) { 8153 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY); 8154 return ASC_ERROR; 8155 } 8156 asc_dvc->in_critical_cnt++; 8157 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { 8158 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) { 8159 asc_dvc->in_critical_cnt--; 8160 return ASC_ERROR; 8161 } 8162 if (sg_entry_cnt > ASC_MAX_SG_LIST) { 8163 asc_dvc->in_critical_cnt--; 8164 return ASC_ERROR; 8165 } 8166 if (sg_entry_cnt == 1) { 8167 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr); 8168 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes); 8169 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE); 8170 } 8171 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 8172 } 8173 scsi_cmd = scsiq->cdbptr[0]; 8174 disable_syn_offset_one_fix = false; 8175 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 8176 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 8177 if (scsiq->q1.cntl & QC_SG_HEAD) { 8178 data_cnt = 0; 8179 for (i = 0; i < sg_entry_cnt; i++) { 8180 data_cnt += le32_to_cpu(sg_head->sg_list[i]. 8181 bytes); 8182 } 8183 } else { 8184 data_cnt = le32_to_cpu(scsiq->q1.data_cnt); 8185 } 8186 if (data_cnt != 0UL) { 8187 if (data_cnt < 512UL) { 8188 disable_syn_offset_one_fix = true; 8189 } else { 8190 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; 8191 i++) { 8192 disable_cmd = 8193 _syn_offset_one_disable_cmd[i]; 8194 if (disable_cmd == 0xFF) { 8195 break; 8196 } 8197 if (scsi_cmd == disable_cmd) { 8198 disable_syn_offset_one_fix = 8199 true; 8200 break; 8201 } 8202 } 8203 } 8204 } 8205 } 8206 if (disable_syn_offset_one_fix) { 8207 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG; 8208 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 8209 ASC_TAG_FLAG_DISABLE_DISCONNECT); 8210 } else { 8211 scsiq->q2.tag_code &= 0x27; 8212 } 8213 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { 8214 if (asc_dvc->bug_fix_cntl) { 8215 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 8216 if ((scsi_cmd == READ_6) || 8217 (scsi_cmd == READ_10)) { 8218 addr = le32_to_cpu(sg_head-> 8219 sg_list 8220 [sg_entry_cnt_minus_one]. 8221 addr) + 8222 le32_to_cpu(sg_head-> 8223 sg_list 8224 [sg_entry_cnt_minus_one]. 8225 bytes); 8226 extra_bytes = 8227 (uchar)((ushort)addr & 0x0003); 8228 if ((extra_bytes != 0) 8229 && 8230 ((scsiq->q2. 8231 tag_code & 8232 ASC_TAG_FLAG_EXTRA_BYTES) 8233 == 0)) { 8234 scsiq->q2.tag_code |= 8235 ASC_TAG_FLAG_EXTRA_BYTES; 8236 scsiq->q1.extra_bytes = 8237 extra_bytes; 8238 data_cnt = 8239 le32_to_cpu(sg_head-> 8240 sg_list 8241 [sg_entry_cnt_minus_one]. 8242 bytes); 8243 data_cnt -= extra_bytes; 8244 sg_head-> 8245 sg_list 8246 [sg_entry_cnt_minus_one]. 8247 bytes = 8248 cpu_to_le32(data_cnt); 8249 } 8250 } 8251 } 8252 } 8253 sg_head->entry_to_copy = sg_head->entry_cnt; 8254 n_q_required = AscSgListToQueue(sg_entry_cnt); 8255 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >= 8256 (uint) n_q_required) 8257 || ((scsiq->q1.cntl & QC_URGENT) != 0)) { 8258 if ((sta = 8259 AscSendScsiQueue(asc_dvc, scsiq, 8260 n_q_required)) == 1) { 8261 asc_dvc->in_critical_cnt--; 8262 return (sta); 8263 } 8264 } 8265 } else { 8266 if (asc_dvc->bug_fix_cntl) { 8267 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 8268 if ((scsi_cmd == READ_6) || 8269 (scsi_cmd == READ_10)) { 8270 addr = 8271 le32_to_cpu(scsiq->q1.data_addr) + 8272 le32_to_cpu(scsiq->q1.data_cnt); 8273 extra_bytes = 8274 (uchar)((ushort)addr & 0x0003); 8275 if ((extra_bytes != 0) 8276 && 8277 ((scsiq->q2. 8278 tag_code & 8279 ASC_TAG_FLAG_EXTRA_BYTES) 8280 == 0)) { 8281 data_cnt = 8282 le32_to_cpu(scsiq->q1. 8283 data_cnt); 8284 if (((ushort)data_cnt & 0x01FF) 8285 == 0) { 8286 scsiq->q2.tag_code |= 8287 ASC_TAG_FLAG_EXTRA_BYTES; 8288 data_cnt -= extra_bytes; 8289 scsiq->q1.data_cnt = 8290 cpu_to_le32 8291 (data_cnt); 8292 scsiq->q1.extra_bytes = 8293 extra_bytes; 8294 } 8295 } 8296 } 8297 } 8298 } 8299 n_q_required = 1; 8300 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) || 8301 ((scsiq->q1.cntl & QC_URGENT) != 0)) { 8302 if ((sta = AscSendScsiQueue(asc_dvc, scsiq, 8303 n_q_required)) == 1) { 8304 asc_dvc->in_critical_cnt--; 8305 return (sta); 8306 } 8307 } 8308 } 8309 asc_dvc->in_critical_cnt--; 8310 return (sta); 8311 } 8312 8313 /* 8314 * AdvExeScsiQueue() - Send a request to the RISC microcode program. 8315 * 8316 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q, 8317 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 8318 * RISC to notify it a new command is ready to be executed. 8319 * 8320 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 8321 * set to SCSI_MAX_RETRY. 8322 * 8323 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode 8324 * for DMA addresses or math operations are byte swapped to little-endian 8325 * order. 8326 * 8327 * Return: 8328 * ADV_SUCCESS(1) - The request was successfully queued. 8329 * ADV_BUSY(0) - Resource unavailable; Retry again after pending 8330 * request completes. 8331 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure 8332 * host IC error. 8333 */ 8334 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp) 8335 { 8336 AdvPortAddr iop_base; 8337 ADV_CARR_T *new_carrp; 8338 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q; 8339 8340 /* 8341 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID. 8342 */ 8343 if (scsiq->target_id > ADV_MAX_TID) { 8344 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 8345 scsiq->done_status = QD_WITH_ERROR; 8346 return ADV_ERROR; 8347 } 8348 8349 iop_base = asc_dvc->iop_base; 8350 8351 /* 8352 * Allocate a carrier ensuring at least one carrier always 8353 * remains on the freelist and initialize fields. 8354 */ 8355 new_carrp = adv_get_next_carrier(asc_dvc); 8356 if (!new_carrp) { 8357 ASC_DBG(1, "No free carriers\n"); 8358 return ADV_BUSY; 8359 } 8360 8361 asc_dvc->carr_pending_cnt++; 8362 8363 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */ 8364 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag); 8365 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr); 8366 8367 scsiq->carr_va = asc_dvc->icq_sp->carr_va; 8368 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa; 8369 8370 /* 8371 * Use the current stopper to send the ADV_SCSI_REQ_Q command to 8372 * the microcode. The newly allocated stopper will become the new 8373 * stopper. 8374 */ 8375 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr; 8376 8377 /* 8378 * Set the 'next_vpa' pointer for the old stopper to be the 8379 * physical address of the new stopper. The RISC can only 8380 * follow physical addresses. 8381 */ 8382 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa; 8383 8384 /* 8385 * Set the host adapter stopper pointer to point to the new carrier. 8386 */ 8387 asc_dvc->icq_sp = new_carrp; 8388 8389 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || 8390 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 8391 /* 8392 * Tickle the RISC to tell it to read its Command Queue Head pointer. 8393 */ 8394 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A); 8395 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 8396 /* 8397 * Clear the tickle value. In the ASC-3550 the RISC flag 8398 * command 'clr_tickle_a' does not work unless the host 8399 * value is cleared. 8400 */ 8401 AdvWriteByteRegister(iop_base, IOPB_TICKLE, 8402 ADV_TICKLE_NOP); 8403 } 8404 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 8405 /* 8406 * Notify the RISC a carrier is ready by writing the physical 8407 * address of the new carrier stopper to the COMMA register. 8408 */ 8409 AdvWriteDWordRegister(iop_base, IOPDW_COMMA, 8410 le32_to_cpu(new_carrp->carr_pa)); 8411 } 8412 8413 return ADV_SUCCESS; 8414 } 8415 8416 /* 8417 * Execute a single 'struct scsi_cmnd'. 8418 */ 8419 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp) 8420 { 8421 int ret, err_code; 8422 struct asc_board *boardp = shost_priv(scp->device->host); 8423 8424 ASC_DBG(1, "scp 0x%p\n", scp); 8425 8426 if (ASC_NARROW_BOARD(boardp)) { 8427 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; 8428 struct asc_scsi_q asc_scsi_q; 8429 8430 ret = asc_build_req(boardp, scp, &asc_scsi_q); 8431 if (ret != ASC_NOERROR) { 8432 ASC_STATS(scp->device->host, build_error); 8433 return ret; 8434 } 8435 8436 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q); 8437 kfree(asc_scsi_q.sg_head); 8438 err_code = asc_dvc->err_code; 8439 } else { 8440 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var; 8441 adv_req_t *adv_reqp; 8442 8443 switch (adv_build_req(boardp, scp, &adv_reqp)) { 8444 case ASC_NOERROR: 8445 ASC_DBG(3, "adv_build_req ASC_NOERROR\n"); 8446 break; 8447 case ASC_BUSY: 8448 ASC_DBG(1, "adv_build_req ASC_BUSY\n"); 8449 /* 8450 * The asc_stats fields 'adv_build_noreq' and 8451 * 'adv_build_nosg' count wide board busy conditions. 8452 * They are updated in adv_build_req and 8453 * adv_get_sglist, respectively. 8454 */ 8455 return ASC_BUSY; 8456 case ASC_ERROR: 8457 default: 8458 ASC_DBG(1, "adv_build_req ASC_ERROR\n"); 8459 ASC_STATS(scp->device->host, build_error); 8460 return ASC_ERROR; 8461 } 8462 8463 ret = AdvExeScsiQueue(adv_dvc, adv_reqp); 8464 err_code = adv_dvc->err_code; 8465 } 8466 8467 switch (ret) { 8468 case ASC_NOERROR: 8469 ASC_STATS(scp->device->host, exe_noerror); 8470 /* 8471 * Increment monotonically increasing per device 8472 * successful request counter. Wrapping doesn't matter. 8473 */ 8474 boardp->reqcnt[scp->device->id]++; 8475 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n"); 8476 break; 8477 case ASC_BUSY: 8478 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n"); 8479 ASC_STATS(scp->device->host, exe_busy); 8480 break; 8481 case ASC_ERROR: 8482 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, " 8483 "err_code 0x%x\n", err_code); 8484 ASC_STATS(scp->device->host, exe_error); 8485 set_host_byte(scp, DID_ERROR); 8486 break; 8487 default: 8488 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, " 8489 "err_code 0x%x\n", err_code); 8490 ASC_STATS(scp->device->host, exe_unknown); 8491 set_host_byte(scp, DID_ERROR); 8492 break; 8493 } 8494 8495 ASC_DBG(1, "end\n"); 8496 return ret; 8497 } 8498 8499 /* 8500 * advansys_queuecommand() - interrupt-driven I/O entrypoint. 8501 * 8502 * This function always returns 0. Command return status is saved 8503 * in the 'scp' result field. 8504 */ 8505 static int 8506 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *)) 8507 { 8508 struct Scsi_Host *shost = scp->device->host; 8509 int asc_res, result = 0; 8510 8511 ASC_STATS(shost, queuecommand); 8512 scp->scsi_done = done; 8513 8514 asc_res = asc_execute_scsi_cmnd(scp); 8515 8516 switch (asc_res) { 8517 case ASC_NOERROR: 8518 break; 8519 case ASC_BUSY: 8520 result = SCSI_MLQUEUE_HOST_BUSY; 8521 break; 8522 case ASC_ERROR: 8523 default: 8524 asc_scsi_done(scp); 8525 break; 8526 } 8527 8528 return result; 8529 } 8530 8531 static DEF_SCSI_QCMD(advansys_queuecommand) 8532 8533 static ushort AscGetEisaChipCfg(PortAddr iop_base) 8534 { 8535 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | 8536 (PortAddr) (ASC_EISA_CFG_IOP_MASK); 8537 return inpw(eisa_cfg_iop); 8538 } 8539 8540 /* 8541 * Return the BIOS address of the adapter at the specified 8542 * I/O port and with the specified bus type. 8543 */ 8544 static unsigned short AscGetChipBiosAddress(PortAddr iop_base, 8545 unsigned short bus_type) 8546 { 8547 unsigned short cfg_lsw; 8548 unsigned short bios_addr; 8549 8550 /* 8551 * The PCI BIOS is re-located by the motherboard BIOS. Because 8552 * of this the driver can not determine where a PCI BIOS is 8553 * loaded and executes. 8554 */ 8555 if (bus_type & ASC_IS_PCI) 8556 return 0; 8557 8558 if ((bus_type & ASC_IS_EISA) != 0) { 8559 cfg_lsw = AscGetEisaChipCfg(iop_base); 8560 cfg_lsw &= 0x000F; 8561 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE; 8562 return bios_addr; 8563 } 8564 8565 cfg_lsw = AscGetChipCfgLsw(iop_base); 8566 8567 /* 8568 * ISA PnP uses the top bit as the 32K BIOS flag 8569 */ 8570 if (bus_type == ASC_IS_ISAPNP) 8571 cfg_lsw &= 0x7FFF; 8572 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE; 8573 return bios_addr; 8574 } 8575 8576 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id) 8577 { 8578 ushort cfg_lsw; 8579 8580 if (AscGetChipScsiID(iop_base) == new_host_id) { 8581 return (new_host_id); 8582 } 8583 cfg_lsw = AscGetChipCfgLsw(iop_base); 8584 cfg_lsw &= 0xF8FF; 8585 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8); 8586 AscSetChipCfgLsw(iop_base, cfg_lsw); 8587 return (AscGetChipScsiID(iop_base)); 8588 } 8589 8590 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base) 8591 { 8592 unsigned char sc; 8593 8594 AscSetBank(iop_base, 1); 8595 sc = inp(iop_base + IOP_REG_SC); 8596 AscSetBank(iop_base, 0); 8597 return sc; 8598 } 8599 8600 static unsigned char AscGetChipVersion(PortAddr iop_base, 8601 unsigned short bus_type) 8602 { 8603 if (bus_type & ASC_IS_EISA) { 8604 PortAddr eisa_iop; 8605 unsigned char revision; 8606 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | 8607 (PortAddr) ASC_EISA_REV_IOP_MASK; 8608 revision = inp(eisa_iop); 8609 return ASC_CHIP_MIN_VER_EISA - 1 + revision; 8610 } 8611 return AscGetChipVerNo(iop_base); 8612 } 8613 8614 #ifdef CONFIG_ISA 8615 static void AscEnableIsaDma(uchar dma_channel) 8616 { 8617 if (dma_channel < 4) { 8618 outp(0x000B, (ushort)(0xC0 | dma_channel)); 8619 outp(0x000A, dma_channel); 8620 } else if (dma_channel < 8) { 8621 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4))); 8622 outp(0x00D4, (ushort)(dma_channel - 4)); 8623 } 8624 } 8625 #endif /* CONFIG_ISA */ 8626 8627 static int AscStopQueueExe(PortAddr iop_base) 8628 { 8629 int count = 0; 8630 8631 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) { 8632 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 8633 ASC_STOP_REQ_RISC_STOP); 8634 do { 8635 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) & 8636 ASC_STOP_ACK_RISC_STOP) { 8637 return (1); 8638 } 8639 mdelay(100); 8640 } while (count++ < 20); 8641 } 8642 return (0); 8643 } 8644 8645 static unsigned int AscGetMaxDmaCount(ushort bus_type) 8646 { 8647 if (bus_type & ASC_IS_ISA) 8648 return ASC_MAX_ISA_DMA_COUNT; 8649 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 8650 return ASC_MAX_VL_DMA_COUNT; 8651 return ASC_MAX_PCI_DMA_COUNT; 8652 } 8653 8654 #ifdef CONFIG_ISA 8655 static ushort AscGetIsaDmaChannel(PortAddr iop_base) 8656 { 8657 ushort channel; 8658 8659 channel = AscGetChipCfgLsw(iop_base) & 0x0003; 8660 if (channel == 0x03) 8661 return (0); 8662 else if (channel == 0x00) 8663 return (7); 8664 return (channel + 4); 8665 } 8666 8667 static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel) 8668 { 8669 ushort cfg_lsw; 8670 uchar value; 8671 8672 if ((dma_channel >= 5) && (dma_channel <= 7)) { 8673 if (dma_channel == 7) 8674 value = 0x00; 8675 else 8676 value = dma_channel - 4; 8677 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC; 8678 cfg_lsw |= value; 8679 AscSetChipCfgLsw(iop_base, cfg_lsw); 8680 return (AscGetIsaDmaChannel(iop_base)); 8681 } 8682 return 0; 8683 } 8684 8685 static uchar AscGetIsaDmaSpeed(PortAddr iop_base) 8686 { 8687 uchar speed_value; 8688 8689 AscSetBank(iop_base, 1); 8690 speed_value = AscReadChipDmaSpeed(iop_base); 8691 speed_value &= 0x07; 8692 AscSetBank(iop_base, 0); 8693 return speed_value; 8694 } 8695 8696 static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value) 8697 { 8698 speed_value &= 0x07; 8699 AscSetBank(iop_base, 1); 8700 AscWriteChipDmaSpeed(iop_base, speed_value); 8701 AscSetBank(iop_base, 0); 8702 return AscGetIsaDmaSpeed(iop_base); 8703 } 8704 #endif /* CONFIG_ISA */ 8705 8706 static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc) 8707 { 8708 int i; 8709 PortAddr iop_base; 8710 uchar chip_version; 8711 8712 iop_base = asc_dvc->iop_base; 8713 asc_dvc->err_code = 0; 8714 if ((asc_dvc->bus_type & 8715 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) { 8716 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE; 8717 } 8718 AscSetChipControl(iop_base, CC_HALT); 8719 AscSetChipStatus(iop_base, 0); 8720 asc_dvc->bug_fix_cntl = 0; 8721 asc_dvc->pci_fix_asyn_xfer = 0; 8722 asc_dvc->pci_fix_asyn_xfer_always = 0; 8723 /* asc_dvc->init_state initialized in AscInitGetConfig(). */ 8724 asc_dvc->sdtr_done = 0; 8725 asc_dvc->cur_total_qng = 0; 8726 asc_dvc->is_in_int = false; 8727 asc_dvc->in_critical_cnt = 0; 8728 asc_dvc->last_q_shortage = 0; 8729 asc_dvc->use_tagged_qng = 0; 8730 asc_dvc->no_scam = 0; 8731 asc_dvc->unit_not_ready = 0; 8732 asc_dvc->queue_full_or_busy = 0; 8733 asc_dvc->redo_scam = 0; 8734 asc_dvc->res2 = 0; 8735 asc_dvc->min_sdtr_index = 0; 8736 asc_dvc->cfg->can_tagged_qng = 0; 8737 asc_dvc->cfg->cmd_qng_enabled = 0; 8738 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL; 8739 asc_dvc->init_sdtr = 0; 8740 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 8741 asc_dvc->scsi_reset_wait = 3; 8742 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 8743 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type); 8744 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 8745 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 8746 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 8747 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type); 8748 asc_dvc->cfg->chip_version = chip_version; 8749 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period; 8750 asc_dvc->max_sdtr_index = 7; 8751 if ((asc_dvc->bus_type & ASC_IS_PCI) && 8752 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 8753 asc_dvc->bus_type = ASC_IS_PCI_ULTRA; 8754 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period; 8755 asc_dvc->max_sdtr_index = 15; 8756 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) { 8757 AscSetExtraControl(iop_base, 8758 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 8759 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) { 8760 AscSetExtraControl(iop_base, 8761 (SEC_ACTIVE_NEGATE | 8762 SEC_ENABLE_FILTER)); 8763 } 8764 } 8765 if (asc_dvc->bus_type == ASC_IS_PCI) { 8766 AscSetExtraControl(iop_base, 8767 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 8768 } 8769 8770 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 8771 #ifdef CONFIG_ISA 8772 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) { 8773 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) { 8774 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT); 8775 asc_dvc->bus_type = ASC_IS_ISAPNP; 8776 } 8777 asc_dvc->cfg->isa_dma_channel = 8778 (uchar)AscGetIsaDmaChannel(iop_base); 8779 } 8780 #endif /* CONFIG_ISA */ 8781 for (i = 0; i <= ASC_MAX_TID; i++) { 8782 asc_dvc->cur_dvc_qng[i] = 0; 8783 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 8784 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L; 8785 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L; 8786 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 8787 } 8788 } 8789 8790 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg) 8791 { 8792 int retry; 8793 8794 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) { 8795 unsigned char read_back; 8796 AscSetChipEEPCmd(iop_base, cmd_reg); 8797 mdelay(1); 8798 read_back = AscGetChipEEPCmd(iop_base); 8799 if (read_back == cmd_reg) 8800 return 1; 8801 } 8802 return 0; 8803 } 8804 8805 static void AscWaitEEPRead(void) 8806 { 8807 mdelay(1); 8808 } 8809 8810 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr) 8811 { 8812 ushort read_wval; 8813 uchar cmd_reg; 8814 8815 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); 8816 AscWaitEEPRead(); 8817 cmd_reg = addr | ASC_EEP_CMD_READ; 8818 AscWriteEEPCmdReg(iop_base, cmd_reg); 8819 AscWaitEEPRead(); 8820 read_wval = AscGetChipEEPData(iop_base); 8821 AscWaitEEPRead(); 8822 return read_wval; 8823 } 8824 8825 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, 8826 ushort bus_type) 8827 { 8828 ushort wval; 8829 ushort sum; 8830 ushort *wbuf; 8831 int cfg_beg; 8832 int cfg_end; 8833 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; 8834 int s_addr; 8835 8836 wbuf = (ushort *)cfg_buf; 8837 sum = 0; 8838 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */ 8839 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 8840 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); 8841 sum += *wbuf; 8842 } 8843 if (bus_type & ASC_IS_VL) { 8844 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 8845 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 8846 } else { 8847 cfg_beg = ASC_EEP_DVC_CFG_BEG; 8848 cfg_end = ASC_EEP_MAX_DVC_ADDR; 8849 } 8850 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 8851 wval = AscReadEEPWord(iop_base, (uchar)s_addr); 8852 if (s_addr <= uchar_end_in_config) { 8853 /* 8854 * Swap all char fields - must unswap bytes already swapped 8855 * by AscReadEEPWord(). 8856 */ 8857 *wbuf = le16_to_cpu(wval); 8858 } else { 8859 /* Don't swap word field at the end - cntl field. */ 8860 *wbuf = wval; 8861 } 8862 sum += wval; /* Checksum treats all EEPROM data as words. */ 8863 } 8864 /* 8865 * Read the checksum word which will be compared against 'sum' 8866 * by the caller. Word field already swapped. 8867 */ 8868 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); 8869 return sum; 8870 } 8871 8872 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc) 8873 { 8874 PortAddr iop_base; 8875 ushort q_addr; 8876 ushort saved_word; 8877 int sta; 8878 8879 iop_base = asc_dvc->iop_base; 8880 sta = 0; 8881 q_addr = ASC_QNO_TO_QADDR(241); 8882 saved_word = AscReadLramWord(iop_base, q_addr); 8883 AscSetChipLramAddr(iop_base, q_addr); 8884 AscSetChipLramData(iop_base, 0x55AA); 8885 mdelay(10); 8886 AscSetChipLramAddr(iop_base, q_addr); 8887 if (AscGetChipLramData(iop_base) == 0x55AA) { 8888 sta = 1; 8889 AscWriteLramWord(iop_base, q_addr, saved_word); 8890 } 8891 return (sta); 8892 } 8893 8894 static void AscWaitEEPWrite(void) 8895 { 8896 mdelay(20); 8897 } 8898 8899 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) 8900 { 8901 ushort read_back; 8902 int retry; 8903 8904 retry = 0; 8905 while (true) { 8906 AscSetChipEEPData(iop_base, data_reg); 8907 mdelay(1); 8908 read_back = AscGetChipEEPData(iop_base); 8909 if (read_back == data_reg) { 8910 return (1); 8911 } 8912 if (retry++ > ASC_EEP_MAX_RETRY) { 8913 return (0); 8914 } 8915 } 8916 } 8917 8918 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val) 8919 { 8920 ushort read_wval; 8921 8922 read_wval = AscReadEEPWord(iop_base, addr); 8923 if (read_wval != word_val) { 8924 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE); 8925 AscWaitEEPRead(); 8926 AscWriteEEPDataReg(iop_base, word_val); 8927 AscWaitEEPRead(); 8928 AscWriteEEPCmdReg(iop_base, 8929 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr)); 8930 AscWaitEEPWrite(); 8931 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); 8932 AscWaitEEPRead(); 8933 return (AscReadEEPWord(iop_base, addr)); 8934 } 8935 return (read_wval); 8936 } 8937 8938 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, 8939 ushort bus_type) 8940 { 8941 int n_error; 8942 ushort *wbuf; 8943 ushort word; 8944 ushort sum; 8945 int s_addr; 8946 int cfg_beg; 8947 int cfg_end; 8948 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; 8949 8950 wbuf = (ushort *)cfg_buf; 8951 n_error = 0; 8952 sum = 0; 8953 /* Write two config words; AscWriteEEPWord() will swap bytes. */ 8954 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 8955 sum += *wbuf; 8956 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { 8957 n_error++; 8958 } 8959 } 8960 if (bus_type & ASC_IS_VL) { 8961 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 8962 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 8963 } else { 8964 cfg_beg = ASC_EEP_DVC_CFG_BEG; 8965 cfg_end = ASC_EEP_MAX_DVC_ADDR; 8966 } 8967 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 8968 if (s_addr <= uchar_end_in_config) { 8969 /* 8970 * This is a char field. Swap char fields before they are 8971 * swapped again by AscWriteEEPWord(). 8972 */ 8973 word = cpu_to_le16(*wbuf); 8974 if (word != 8975 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) { 8976 n_error++; 8977 } 8978 } else { 8979 /* Don't swap word field at the end - cntl field. */ 8980 if (*wbuf != 8981 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { 8982 n_error++; 8983 } 8984 } 8985 sum += *wbuf; /* Checksum calculated from word values. */ 8986 } 8987 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */ 8988 *wbuf = sum; 8989 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) { 8990 n_error++; 8991 } 8992 8993 /* Read EEPROM back again. */ 8994 wbuf = (ushort *)cfg_buf; 8995 /* 8996 * Read two config words; Byte-swapping done by AscReadEEPWord(). 8997 */ 8998 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 8999 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) { 9000 n_error++; 9001 } 9002 } 9003 if (bus_type & ASC_IS_VL) { 9004 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 9005 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 9006 } else { 9007 cfg_beg = ASC_EEP_DVC_CFG_BEG; 9008 cfg_end = ASC_EEP_MAX_DVC_ADDR; 9009 } 9010 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 9011 if (s_addr <= uchar_end_in_config) { 9012 /* 9013 * Swap all char fields. Must unswap bytes already swapped 9014 * by AscReadEEPWord(). 9015 */ 9016 word = 9017 le16_to_cpu(AscReadEEPWord 9018 (iop_base, (uchar)s_addr)); 9019 } else { 9020 /* Don't swap word field at the end - cntl field. */ 9021 word = AscReadEEPWord(iop_base, (uchar)s_addr); 9022 } 9023 if (*wbuf != word) { 9024 n_error++; 9025 } 9026 } 9027 /* Read checksum; Byte swapping not needed. */ 9028 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) { 9029 n_error++; 9030 } 9031 return n_error; 9032 } 9033 9034 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, 9035 ushort bus_type) 9036 { 9037 int retry; 9038 int n_error; 9039 9040 retry = 0; 9041 while (true) { 9042 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf, 9043 bus_type)) == 0) { 9044 break; 9045 } 9046 if (++retry > ASC_EEP_MAX_RETRY) { 9047 break; 9048 } 9049 } 9050 return n_error; 9051 } 9052 9053 static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc) 9054 { 9055 ASCEEP_CONFIG eep_config_buf; 9056 ASCEEP_CONFIG *eep_config; 9057 PortAddr iop_base; 9058 ushort chksum; 9059 ushort warn_code; 9060 ushort cfg_msw, cfg_lsw; 9061 int i; 9062 int write_eep = 0; 9063 9064 iop_base = asc_dvc->iop_base; 9065 warn_code = 0; 9066 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE); 9067 AscStopQueueExe(iop_base); 9068 if ((AscStopChip(iop_base)) || 9069 (AscGetChipScsiCtrl(iop_base) != 0)) { 9070 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE; 9071 AscResetChipAndScsiBus(asc_dvc); 9072 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ 9073 } 9074 if (!AscIsChipHalted(iop_base)) { 9075 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; 9076 return (warn_code); 9077 } 9078 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); 9079 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { 9080 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; 9081 return (warn_code); 9082 } 9083 eep_config = (ASCEEP_CONFIG *)&eep_config_buf; 9084 cfg_msw = AscGetChipCfgMsw(iop_base); 9085 cfg_lsw = AscGetChipCfgLsw(iop_base); 9086 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 9087 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 9088 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 9089 AscSetChipCfgMsw(iop_base, cfg_msw); 9090 } 9091 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type); 9092 ASC_DBG(1, "chksum 0x%x\n", chksum); 9093 if (chksum == 0) { 9094 chksum = 0xaa55; 9095 } 9096 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { 9097 warn_code |= ASC_WARN_AUTO_CONFIG; 9098 if (asc_dvc->cfg->chip_version == 3) { 9099 if (eep_config->cfg_lsw != cfg_lsw) { 9100 warn_code |= ASC_WARN_EEPROM_RECOVER; 9101 eep_config->cfg_lsw = 9102 AscGetChipCfgLsw(iop_base); 9103 } 9104 if (eep_config->cfg_msw != cfg_msw) { 9105 warn_code |= ASC_WARN_EEPROM_RECOVER; 9106 eep_config->cfg_msw = 9107 AscGetChipCfgMsw(iop_base); 9108 } 9109 } 9110 } 9111 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 9112 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 9113 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum); 9114 if (chksum != eep_config->chksum) { 9115 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) == 9116 ASC_CHIP_VER_PCI_ULTRA_3050) { 9117 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n"); 9118 eep_config->init_sdtr = 0xFF; 9119 eep_config->disc_enable = 0xFF; 9120 eep_config->start_motor = 0xFF; 9121 eep_config->use_cmd_qng = 0; 9122 eep_config->max_total_qng = 0xF0; 9123 eep_config->max_tag_qng = 0x20; 9124 eep_config->cntl = 0xBFFF; 9125 ASC_EEP_SET_CHIP_ID(eep_config, 7); 9126 eep_config->no_scam = 0; 9127 eep_config->adapter_info[0] = 0; 9128 eep_config->adapter_info[1] = 0; 9129 eep_config->adapter_info[2] = 0; 9130 eep_config->adapter_info[3] = 0; 9131 eep_config->adapter_info[4] = 0; 9132 /* Indicate EEPROM-less board. */ 9133 eep_config->adapter_info[5] = 0xBB; 9134 } else { 9135 ASC_PRINT 9136 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n"); 9137 write_eep = 1; 9138 warn_code |= ASC_WARN_EEPROM_CHKSUM; 9139 } 9140 } 9141 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr; 9142 asc_dvc->cfg->disc_enable = eep_config->disc_enable; 9143 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng; 9144 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config); 9145 asc_dvc->start_motor = eep_config->start_motor; 9146 asc_dvc->dvc_cntl = eep_config->cntl; 9147 asc_dvc->no_scam = eep_config->no_scam; 9148 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0]; 9149 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1]; 9150 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2]; 9151 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3]; 9152 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4]; 9153 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5]; 9154 if (!AscTestExternalLram(asc_dvc)) { 9155 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == 9156 ASC_IS_PCI_ULTRA)) { 9157 eep_config->max_total_qng = 9158 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 9159 eep_config->max_tag_qng = 9160 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 9161 } else { 9162 eep_config->cfg_msw |= 0x0800; 9163 cfg_msw |= 0x0800; 9164 AscSetChipCfgMsw(iop_base, cfg_msw); 9165 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 9166 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 9167 } 9168 } else { 9169 } 9170 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) { 9171 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 9172 } 9173 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) { 9174 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 9175 } 9176 if (eep_config->max_tag_qng > eep_config->max_total_qng) { 9177 eep_config->max_tag_qng = eep_config->max_total_qng; 9178 } 9179 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) { 9180 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 9181 } 9182 asc_dvc->max_total_qng = eep_config->max_total_qng; 9183 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 9184 eep_config->use_cmd_qng) { 9185 eep_config->disc_enable = eep_config->use_cmd_qng; 9186 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 9187 } 9188 ASC_EEP_SET_CHIP_ID(eep_config, 9189 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID); 9190 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config); 9191 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 9192 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 9193 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 9194 } 9195 9196 for (i = 0; i <= ASC_MAX_TID; i++) { 9197 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i]; 9198 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng; 9199 asc_dvc->cfg->sdtr_period_offset[i] = 9200 (uchar)(ASC_DEF_SDTR_OFFSET | 9201 (asc_dvc->min_sdtr_index << 4)); 9202 } 9203 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base); 9204 if (write_eep) { 9205 if ((i = AscSetEEPConfig(iop_base, eep_config, 9206 asc_dvc->bus_type)) != 0) { 9207 ASC_PRINT1 9208 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", 9209 i); 9210 } else { 9211 ASC_PRINT 9212 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n"); 9213 } 9214 } 9215 return (warn_code); 9216 } 9217 9218 static int AscInitGetConfig(struct Scsi_Host *shost) 9219 { 9220 struct asc_board *board = shost_priv(shost); 9221 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var; 9222 unsigned short warn_code = 0; 9223 9224 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG; 9225 if (asc_dvc->err_code != 0) 9226 return asc_dvc->err_code; 9227 9228 if (AscFindSignature(asc_dvc->iop_base)) { 9229 AscInitAscDvcVar(asc_dvc); 9230 warn_code = AscInitFromEEP(asc_dvc); 9231 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG; 9232 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) 9233 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT; 9234 } else { 9235 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 9236 } 9237 9238 switch (warn_code) { 9239 case 0: /* No error */ 9240 break; 9241 case ASC_WARN_IO_PORT_ROTATE: 9242 shost_printk(KERN_WARNING, shost, "I/O port address " 9243 "modified\n"); 9244 break; 9245 case ASC_WARN_AUTO_CONFIG: 9246 shost_printk(KERN_WARNING, shost, "I/O port increment switch " 9247 "enabled\n"); 9248 break; 9249 case ASC_WARN_EEPROM_CHKSUM: 9250 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n"); 9251 break; 9252 case ASC_WARN_IRQ_MODIFIED: 9253 shost_printk(KERN_WARNING, shost, "IRQ modified\n"); 9254 break; 9255 case ASC_WARN_CMD_QNG_CONFLICT: 9256 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o " 9257 "disconnects\n"); 9258 break; 9259 default: 9260 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n", 9261 warn_code); 9262 break; 9263 } 9264 9265 if (asc_dvc->err_code != 0) 9266 shost_printk(KERN_ERR, shost, "error 0x%x at init_state " 9267 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state); 9268 9269 return asc_dvc->err_code; 9270 } 9271 9272 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) 9273 { 9274 struct asc_board *board = shost_priv(shost); 9275 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var; 9276 PortAddr iop_base = asc_dvc->iop_base; 9277 unsigned short cfg_msw; 9278 unsigned short warn_code = 0; 9279 9280 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG; 9281 if (asc_dvc->err_code != 0) 9282 return asc_dvc->err_code; 9283 if (!AscFindSignature(asc_dvc->iop_base)) { 9284 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 9285 return asc_dvc->err_code; 9286 } 9287 9288 cfg_msw = AscGetChipCfgMsw(iop_base); 9289 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 9290 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 9291 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 9292 AscSetChipCfgMsw(iop_base, cfg_msw); 9293 } 9294 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) != 9295 asc_dvc->cfg->cmd_qng_enabled) { 9296 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled; 9297 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 9298 } 9299 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { 9300 warn_code |= ASC_WARN_AUTO_CONFIG; 9301 } 9302 #ifdef CONFIG_PCI 9303 if (asc_dvc->bus_type & ASC_IS_PCI) { 9304 cfg_msw &= 0xFFC0; 9305 AscSetChipCfgMsw(iop_base, cfg_msw); 9306 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) { 9307 } else { 9308 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || 9309 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { 9310 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 9311 asc_dvc->bug_fix_cntl |= 9312 ASC_BUG_FIX_ASYN_USE_SYN; 9313 } 9314 } 9315 } else 9316 #endif /* CONFIG_PCI */ 9317 if (asc_dvc->bus_type == ASC_IS_ISAPNP) { 9318 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) 9319 == ASC_CHIP_VER_ASYN_BUG) { 9320 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 9321 } 9322 } 9323 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) != 9324 asc_dvc->cfg->chip_scsi_id) { 9325 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID; 9326 } 9327 #ifdef CONFIG_ISA 9328 if (asc_dvc->bus_type & ASC_IS_ISA) { 9329 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel); 9330 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed); 9331 } 9332 #endif /* CONFIG_ISA */ 9333 9334 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG; 9335 9336 switch (warn_code) { 9337 case 0: /* No error. */ 9338 break; 9339 case ASC_WARN_IO_PORT_ROTATE: 9340 shost_printk(KERN_WARNING, shost, "I/O port address " 9341 "modified\n"); 9342 break; 9343 case ASC_WARN_AUTO_CONFIG: 9344 shost_printk(KERN_WARNING, shost, "I/O port increment switch " 9345 "enabled\n"); 9346 break; 9347 case ASC_WARN_EEPROM_CHKSUM: 9348 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n"); 9349 break; 9350 case ASC_WARN_IRQ_MODIFIED: 9351 shost_printk(KERN_WARNING, shost, "IRQ modified\n"); 9352 break; 9353 case ASC_WARN_CMD_QNG_CONFLICT: 9354 shost_printk(KERN_WARNING, shost, "tag queuing w/o " 9355 "disconnects\n"); 9356 break; 9357 default: 9358 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n", 9359 warn_code); 9360 break; 9361 } 9362 9363 if (asc_dvc->err_code != 0) 9364 shost_printk(KERN_ERR, shost, "error 0x%x at init_state " 9365 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state); 9366 9367 return asc_dvc->err_code; 9368 } 9369 9370 /* 9371 * EEPROM Configuration. 9372 * 9373 * All drivers should use this structure to set the default EEPROM 9374 * configuration. The BIOS now uses this structure when it is built. 9375 * Additional structure information can be found in a_condor.h where 9376 * the structure is defined. 9377 * 9378 * The *_Field_IsChar structs are needed to correct for endianness. 9379 * These values are read from the board 16 bits at a time directly 9380 * into the structs. Because some fields are char, the values will be 9381 * in the wrong order. The *_Field_IsChar tells when to flip the 9382 * bytes. Data read and written to PCI memory is automatically swapped 9383 * on big-endian platforms so char fields read as words are actually being 9384 * unswapped on big-endian platforms. 9385 */ 9386 #ifdef CONFIG_PCI 9387 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = { 9388 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 9389 0x0000, /* cfg_msw */ 9390 0xFFFF, /* disc_enable */ 9391 0xFFFF, /* wdtr_able */ 9392 0xFFFF, /* sdtr_able */ 9393 0xFFFF, /* start_motor */ 9394 0xFFFF, /* tagqng_able */ 9395 0xFFFF, /* bios_scan */ 9396 0, /* scam_tolerant */ 9397 7, /* adapter_scsi_id */ 9398 0, /* bios_boot_delay */ 9399 3, /* scsi_reset_delay */ 9400 0, /* bios_id_lun */ 9401 0, /* termination */ 9402 0, /* reserved1 */ 9403 0xFFE7, /* bios_ctrl */ 9404 0xFFFF, /* ultra_able */ 9405 0, /* reserved2 */ 9406 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ 9407 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 9408 0, /* dvc_cntl */ 9409 0, /* bug_fix */ 9410 0, /* serial_number_word1 */ 9411 0, /* serial_number_word2 */ 9412 0, /* serial_number_word3 */ 9413 0, /* check_sum */ 9414 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 9415 , /* oem_name[16] */ 9416 0, /* dvc_err_code */ 9417 0, /* adv_err_code */ 9418 0, /* adv_err_addr */ 9419 0, /* saved_dvc_err_code */ 9420 0, /* saved_adv_err_code */ 9421 0, /* saved_adv_err_addr */ 9422 0 /* num_of_err */ 9423 }; 9424 9425 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = { 9426 0, /* cfg_lsw */ 9427 0, /* cfg_msw */ 9428 0, /* -disc_enable */ 9429 0, /* wdtr_able */ 9430 0, /* sdtr_able */ 9431 0, /* start_motor */ 9432 0, /* tagqng_able */ 9433 0, /* bios_scan */ 9434 0, /* scam_tolerant */ 9435 1, /* adapter_scsi_id */ 9436 1, /* bios_boot_delay */ 9437 1, /* scsi_reset_delay */ 9438 1, /* bios_id_lun */ 9439 1, /* termination */ 9440 1, /* reserved1 */ 9441 0, /* bios_ctrl */ 9442 0, /* ultra_able */ 9443 0, /* reserved2 */ 9444 1, /* max_host_qng */ 9445 1, /* max_dvc_qng */ 9446 0, /* dvc_cntl */ 9447 0, /* bug_fix */ 9448 0, /* serial_number_word1 */ 9449 0, /* serial_number_word2 */ 9450 0, /* serial_number_word3 */ 9451 0, /* check_sum */ 9452 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 9453 , /* oem_name[16] */ 9454 0, /* dvc_err_code */ 9455 0, /* adv_err_code */ 9456 0, /* adv_err_addr */ 9457 0, /* saved_dvc_err_code */ 9458 0, /* saved_adv_err_code */ 9459 0, /* saved_adv_err_addr */ 9460 0 /* num_of_err */ 9461 }; 9462 9463 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = { 9464 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 9465 0x0000, /* 01 cfg_msw */ 9466 0xFFFF, /* 02 disc_enable */ 9467 0xFFFF, /* 03 wdtr_able */ 9468 0x4444, /* 04 sdtr_speed1 */ 9469 0xFFFF, /* 05 start_motor */ 9470 0xFFFF, /* 06 tagqng_able */ 9471 0xFFFF, /* 07 bios_scan */ 9472 0, /* 08 scam_tolerant */ 9473 7, /* 09 adapter_scsi_id */ 9474 0, /* bios_boot_delay */ 9475 3, /* 10 scsi_reset_delay */ 9476 0, /* bios_id_lun */ 9477 0, /* 11 termination_se */ 9478 0, /* termination_lvd */ 9479 0xFFE7, /* 12 bios_ctrl */ 9480 0x4444, /* 13 sdtr_speed2 */ 9481 0x4444, /* 14 sdtr_speed3 */ 9482 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 9483 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 9484 0, /* 16 dvc_cntl */ 9485 0x4444, /* 17 sdtr_speed4 */ 9486 0, /* 18 serial_number_word1 */ 9487 0, /* 19 serial_number_word2 */ 9488 0, /* 20 serial_number_word3 */ 9489 0, /* 21 check_sum */ 9490 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 9491 , /* 22-29 oem_name[16] */ 9492 0, /* 30 dvc_err_code */ 9493 0, /* 31 adv_err_code */ 9494 0, /* 32 adv_err_addr */ 9495 0, /* 33 saved_dvc_err_code */ 9496 0, /* 34 saved_adv_err_code */ 9497 0, /* 35 saved_adv_err_addr */ 9498 0, /* 36 reserved */ 9499 0, /* 37 reserved */ 9500 0, /* 38 reserved */ 9501 0, /* 39 reserved */ 9502 0, /* 40 reserved */ 9503 0, /* 41 reserved */ 9504 0, /* 42 reserved */ 9505 0, /* 43 reserved */ 9506 0, /* 44 reserved */ 9507 0, /* 45 reserved */ 9508 0, /* 46 reserved */ 9509 0, /* 47 reserved */ 9510 0, /* 48 reserved */ 9511 0, /* 49 reserved */ 9512 0, /* 50 reserved */ 9513 0, /* 51 reserved */ 9514 0, /* 52 reserved */ 9515 0, /* 53 reserved */ 9516 0, /* 54 reserved */ 9517 0, /* 55 reserved */ 9518 0, /* 56 cisptr_lsw */ 9519 0, /* 57 cisprt_msw */ 9520 PCI_VENDOR_ID_ASP, /* 58 subsysvid */ 9521 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */ 9522 0, /* 60 reserved */ 9523 0, /* 61 reserved */ 9524 0, /* 62 reserved */ 9525 0 /* 63 reserved */ 9526 }; 9527 9528 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = { 9529 0, /* 00 cfg_lsw */ 9530 0, /* 01 cfg_msw */ 9531 0, /* 02 disc_enable */ 9532 0, /* 03 wdtr_able */ 9533 0, /* 04 sdtr_speed1 */ 9534 0, /* 05 start_motor */ 9535 0, /* 06 tagqng_able */ 9536 0, /* 07 bios_scan */ 9537 0, /* 08 scam_tolerant */ 9538 1, /* 09 adapter_scsi_id */ 9539 1, /* bios_boot_delay */ 9540 1, /* 10 scsi_reset_delay */ 9541 1, /* bios_id_lun */ 9542 1, /* 11 termination_se */ 9543 1, /* termination_lvd */ 9544 0, /* 12 bios_ctrl */ 9545 0, /* 13 sdtr_speed2 */ 9546 0, /* 14 sdtr_speed3 */ 9547 1, /* 15 max_host_qng */ 9548 1, /* max_dvc_qng */ 9549 0, /* 16 dvc_cntl */ 9550 0, /* 17 sdtr_speed4 */ 9551 0, /* 18 serial_number_word1 */ 9552 0, /* 19 serial_number_word2 */ 9553 0, /* 20 serial_number_word3 */ 9554 0, /* 21 check_sum */ 9555 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 9556 , /* 22-29 oem_name[16] */ 9557 0, /* 30 dvc_err_code */ 9558 0, /* 31 adv_err_code */ 9559 0, /* 32 adv_err_addr */ 9560 0, /* 33 saved_dvc_err_code */ 9561 0, /* 34 saved_adv_err_code */ 9562 0, /* 35 saved_adv_err_addr */ 9563 0, /* 36 reserved */ 9564 0, /* 37 reserved */ 9565 0, /* 38 reserved */ 9566 0, /* 39 reserved */ 9567 0, /* 40 reserved */ 9568 0, /* 41 reserved */ 9569 0, /* 42 reserved */ 9570 0, /* 43 reserved */ 9571 0, /* 44 reserved */ 9572 0, /* 45 reserved */ 9573 0, /* 46 reserved */ 9574 0, /* 47 reserved */ 9575 0, /* 48 reserved */ 9576 0, /* 49 reserved */ 9577 0, /* 50 reserved */ 9578 0, /* 51 reserved */ 9579 0, /* 52 reserved */ 9580 0, /* 53 reserved */ 9581 0, /* 54 reserved */ 9582 0, /* 55 reserved */ 9583 0, /* 56 cisptr_lsw */ 9584 0, /* 57 cisprt_msw */ 9585 0, /* 58 subsysvid */ 9586 0, /* 59 subsysid */ 9587 0, /* 60 reserved */ 9588 0, /* 61 reserved */ 9589 0, /* 62 reserved */ 9590 0 /* 63 reserved */ 9591 }; 9592 9593 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = { 9594 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 9595 0x0000, /* 01 cfg_msw */ 9596 0xFFFF, /* 02 disc_enable */ 9597 0xFFFF, /* 03 wdtr_able */ 9598 0x5555, /* 04 sdtr_speed1 */ 9599 0xFFFF, /* 05 start_motor */ 9600 0xFFFF, /* 06 tagqng_able */ 9601 0xFFFF, /* 07 bios_scan */ 9602 0, /* 08 scam_tolerant */ 9603 7, /* 09 adapter_scsi_id */ 9604 0, /* bios_boot_delay */ 9605 3, /* 10 scsi_reset_delay */ 9606 0, /* bios_id_lun */ 9607 0, /* 11 termination_se */ 9608 0, /* termination_lvd */ 9609 0xFFE7, /* 12 bios_ctrl */ 9610 0x5555, /* 13 sdtr_speed2 */ 9611 0x5555, /* 14 sdtr_speed3 */ 9612 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 9613 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 9614 0, /* 16 dvc_cntl */ 9615 0x5555, /* 17 sdtr_speed4 */ 9616 0, /* 18 serial_number_word1 */ 9617 0, /* 19 serial_number_word2 */ 9618 0, /* 20 serial_number_word3 */ 9619 0, /* 21 check_sum */ 9620 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 9621 , /* 22-29 oem_name[16] */ 9622 0, /* 30 dvc_err_code */ 9623 0, /* 31 adv_err_code */ 9624 0, /* 32 adv_err_addr */ 9625 0, /* 33 saved_dvc_err_code */ 9626 0, /* 34 saved_adv_err_code */ 9627 0, /* 35 saved_adv_err_addr */ 9628 0, /* 36 reserved */ 9629 0, /* 37 reserved */ 9630 0, /* 38 reserved */ 9631 0, /* 39 reserved */ 9632 0, /* 40 reserved */ 9633 0, /* 41 reserved */ 9634 0, /* 42 reserved */ 9635 0, /* 43 reserved */ 9636 0, /* 44 reserved */ 9637 0, /* 45 reserved */ 9638 0, /* 46 reserved */ 9639 0, /* 47 reserved */ 9640 0, /* 48 reserved */ 9641 0, /* 49 reserved */ 9642 0, /* 50 reserved */ 9643 0, /* 51 reserved */ 9644 0, /* 52 reserved */ 9645 0, /* 53 reserved */ 9646 0, /* 54 reserved */ 9647 0, /* 55 reserved */ 9648 0, /* 56 cisptr_lsw */ 9649 0, /* 57 cisprt_msw */ 9650 PCI_VENDOR_ID_ASP, /* 58 subsysvid */ 9651 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */ 9652 0, /* 60 reserved */ 9653 0, /* 61 reserved */ 9654 0, /* 62 reserved */ 9655 0 /* 63 reserved */ 9656 }; 9657 9658 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = { 9659 0, /* 00 cfg_lsw */ 9660 0, /* 01 cfg_msw */ 9661 0, /* 02 disc_enable */ 9662 0, /* 03 wdtr_able */ 9663 0, /* 04 sdtr_speed1 */ 9664 0, /* 05 start_motor */ 9665 0, /* 06 tagqng_able */ 9666 0, /* 07 bios_scan */ 9667 0, /* 08 scam_tolerant */ 9668 1, /* 09 adapter_scsi_id */ 9669 1, /* bios_boot_delay */ 9670 1, /* 10 scsi_reset_delay */ 9671 1, /* bios_id_lun */ 9672 1, /* 11 termination_se */ 9673 1, /* termination_lvd */ 9674 0, /* 12 bios_ctrl */ 9675 0, /* 13 sdtr_speed2 */ 9676 0, /* 14 sdtr_speed3 */ 9677 1, /* 15 max_host_qng */ 9678 1, /* max_dvc_qng */ 9679 0, /* 16 dvc_cntl */ 9680 0, /* 17 sdtr_speed4 */ 9681 0, /* 18 serial_number_word1 */ 9682 0, /* 19 serial_number_word2 */ 9683 0, /* 20 serial_number_word3 */ 9684 0, /* 21 check_sum */ 9685 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 9686 , /* 22-29 oem_name[16] */ 9687 0, /* 30 dvc_err_code */ 9688 0, /* 31 adv_err_code */ 9689 0, /* 32 adv_err_addr */ 9690 0, /* 33 saved_dvc_err_code */ 9691 0, /* 34 saved_adv_err_code */ 9692 0, /* 35 saved_adv_err_addr */ 9693 0, /* 36 reserved */ 9694 0, /* 37 reserved */ 9695 0, /* 38 reserved */ 9696 0, /* 39 reserved */ 9697 0, /* 40 reserved */ 9698 0, /* 41 reserved */ 9699 0, /* 42 reserved */ 9700 0, /* 43 reserved */ 9701 0, /* 44 reserved */ 9702 0, /* 45 reserved */ 9703 0, /* 46 reserved */ 9704 0, /* 47 reserved */ 9705 0, /* 48 reserved */ 9706 0, /* 49 reserved */ 9707 0, /* 50 reserved */ 9708 0, /* 51 reserved */ 9709 0, /* 52 reserved */ 9710 0, /* 53 reserved */ 9711 0, /* 54 reserved */ 9712 0, /* 55 reserved */ 9713 0, /* 56 cisptr_lsw */ 9714 0, /* 57 cisprt_msw */ 9715 0, /* 58 subsysvid */ 9716 0, /* 59 subsysid */ 9717 0, /* 60 reserved */ 9718 0, /* 61 reserved */ 9719 0, /* 62 reserved */ 9720 0 /* 63 reserved */ 9721 }; 9722 9723 /* 9724 * Wait for EEPROM command to complete 9725 */ 9726 static void AdvWaitEEPCmd(AdvPortAddr iop_base) 9727 { 9728 int eep_delay_ms; 9729 9730 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) { 9731 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & 9732 ASC_EEP_CMD_DONE) { 9733 break; 9734 } 9735 mdelay(1); 9736 } 9737 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 9738 0) 9739 BUG(); 9740 } 9741 9742 /* 9743 * Read the EEPROM from specified location 9744 */ 9745 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr) 9746 { 9747 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9748 ASC_EEP_CMD_READ | eep_word_addr); 9749 AdvWaitEEPCmd(iop_base); 9750 return AdvReadWordRegister(iop_base, IOPW_EE_DATA); 9751 } 9752 9753 /* 9754 * Write the EEPROM from 'cfg_buf'. 9755 */ 9756 static void AdvSet3550EEPConfig(AdvPortAddr iop_base, 9757 ADVEEP_3550_CONFIG *cfg_buf) 9758 { 9759 ushort *wbuf; 9760 ushort addr, chksum; 9761 ushort *charfields; 9762 9763 wbuf = (ushort *)cfg_buf; 9764 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; 9765 chksum = 0; 9766 9767 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 9768 AdvWaitEEPCmd(iop_base); 9769 9770 /* 9771 * Write EEPROM from word 0 to word 20. 9772 */ 9773 for (addr = ADV_EEP_DVC_CFG_BEGIN; 9774 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 9775 ushort word; 9776 9777 if (*charfields++) { 9778 word = cpu_to_le16(*wbuf); 9779 } else { 9780 word = *wbuf; 9781 } 9782 chksum += *wbuf; /* Checksum is calculated from word values. */ 9783 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9784 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9785 ASC_EEP_CMD_WRITE | addr); 9786 AdvWaitEEPCmd(iop_base); 9787 mdelay(ADV_EEP_DELAY_MS); 9788 } 9789 9790 /* 9791 * Write EEPROM checksum at word 21. 9792 */ 9793 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 9794 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 9795 AdvWaitEEPCmd(iop_base); 9796 wbuf++; 9797 charfields++; 9798 9799 /* 9800 * Write EEPROM OEM name at words 22 to 29. 9801 */ 9802 for (addr = ADV_EEP_DVC_CTL_BEGIN; 9803 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 9804 ushort word; 9805 9806 if (*charfields++) { 9807 word = cpu_to_le16(*wbuf); 9808 } else { 9809 word = *wbuf; 9810 } 9811 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9812 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9813 ASC_EEP_CMD_WRITE | addr); 9814 AdvWaitEEPCmd(iop_base); 9815 } 9816 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 9817 AdvWaitEEPCmd(iop_base); 9818 } 9819 9820 /* 9821 * Write the EEPROM from 'cfg_buf'. 9822 */ 9823 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base, 9824 ADVEEP_38C0800_CONFIG *cfg_buf) 9825 { 9826 ushort *wbuf; 9827 ushort *charfields; 9828 ushort addr, chksum; 9829 9830 wbuf = (ushort *)cfg_buf; 9831 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; 9832 chksum = 0; 9833 9834 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 9835 AdvWaitEEPCmd(iop_base); 9836 9837 /* 9838 * Write EEPROM from word 0 to word 20. 9839 */ 9840 for (addr = ADV_EEP_DVC_CFG_BEGIN; 9841 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 9842 ushort word; 9843 9844 if (*charfields++) { 9845 word = cpu_to_le16(*wbuf); 9846 } else { 9847 word = *wbuf; 9848 } 9849 chksum += *wbuf; /* Checksum is calculated from word values. */ 9850 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9851 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9852 ASC_EEP_CMD_WRITE | addr); 9853 AdvWaitEEPCmd(iop_base); 9854 mdelay(ADV_EEP_DELAY_MS); 9855 } 9856 9857 /* 9858 * Write EEPROM checksum at word 21. 9859 */ 9860 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 9861 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 9862 AdvWaitEEPCmd(iop_base); 9863 wbuf++; 9864 charfields++; 9865 9866 /* 9867 * Write EEPROM OEM name at words 22 to 29. 9868 */ 9869 for (addr = ADV_EEP_DVC_CTL_BEGIN; 9870 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 9871 ushort word; 9872 9873 if (*charfields++) { 9874 word = cpu_to_le16(*wbuf); 9875 } else { 9876 word = *wbuf; 9877 } 9878 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9879 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9880 ASC_EEP_CMD_WRITE | addr); 9881 AdvWaitEEPCmd(iop_base); 9882 } 9883 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 9884 AdvWaitEEPCmd(iop_base); 9885 } 9886 9887 /* 9888 * Write the EEPROM from 'cfg_buf'. 9889 */ 9890 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base, 9891 ADVEEP_38C1600_CONFIG *cfg_buf) 9892 { 9893 ushort *wbuf; 9894 ushort *charfields; 9895 ushort addr, chksum; 9896 9897 wbuf = (ushort *)cfg_buf; 9898 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; 9899 chksum = 0; 9900 9901 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 9902 AdvWaitEEPCmd(iop_base); 9903 9904 /* 9905 * Write EEPROM from word 0 to word 20. 9906 */ 9907 for (addr = ADV_EEP_DVC_CFG_BEGIN; 9908 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 9909 ushort word; 9910 9911 if (*charfields++) { 9912 word = cpu_to_le16(*wbuf); 9913 } else { 9914 word = *wbuf; 9915 } 9916 chksum += *wbuf; /* Checksum is calculated from word values. */ 9917 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9918 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9919 ASC_EEP_CMD_WRITE | addr); 9920 AdvWaitEEPCmd(iop_base); 9921 mdelay(ADV_EEP_DELAY_MS); 9922 } 9923 9924 /* 9925 * Write EEPROM checksum at word 21. 9926 */ 9927 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 9928 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 9929 AdvWaitEEPCmd(iop_base); 9930 wbuf++; 9931 charfields++; 9932 9933 /* 9934 * Write EEPROM OEM name at words 22 to 29. 9935 */ 9936 for (addr = ADV_EEP_DVC_CTL_BEGIN; 9937 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 9938 ushort word; 9939 9940 if (*charfields++) { 9941 word = cpu_to_le16(*wbuf); 9942 } else { 9943 word = *wbuf; 9944 } 9945 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9946 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9947 ASC_EEP_CMD_WRITE | addr); 9948 AdvWaitEEPCmd(iop_base); 9949 } 9950 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 9951 AdvWaitEEPCmd(iop_base); 9952 } 9953 9954 /* 9955 * Read EEPROM configuration into the specified buffer. 9956 * 9957 * Return a checksum based on the EEPROM configuration read. 9958 */ 9959 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base, 9960 ADVEEP_3550_CONFIG *cfg_buf) 9961 { 9962 ushort wval, chksum; 9963 ushort *wbuf; 9964 int eep_addr; 9965 ushort *charfields; 9966 9967 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; 9968 wbuf = (ushort *)cfg_buf; 9969 chksum = 0; 9970 9971 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 9972 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 9973 wval = AdvReadEEPWord(iop_base, eep_addr); 9974 chksum += wval; /* Checksum is calculated from word values. */ 9975 if (*charfields++) { 9976 *wbuf = le16_to_cpu(wval); 9977 } else { 9978 *wbuf = wval; 9979 } 9980 } 9981 /* Read checksum word. */ 9982 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9983 wbuf++; 9984 charfields++; 9985 9986 /* Read rest of EEPROM not covered by the checksum. */ 9987 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 9988 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 9989 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9990 if (*charfields++) { 9991 *wbuf = le16_to_cpu(*wbuf); 9992 } 9993 } 9994 return chksum; 9995 } 9996 9997 /* 9998 * Read EEPROM configuration into the specified buffer. 9999 * 10000 * Return a checksum based on the EEPROM configuration read. 10001 */ 10002 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base, 10003 ADVEEP_38C0800_CONFIG *cfg_buf) 10004 { 10005 ushort wval, chksum; 10006 ushort *wbuf; 10007 int eep_addr; 10008 ushort *charfields; 10009 10010 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; 10011 wbuf = (ushort *)cfg_buf; 10012 chksum = 0; 10013 10014 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 10015 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 10016 wval = AdvReadEEPWord(iop_base, eep_addr); 10017 chksum += wval; /* Checksum is calculated from word values. */ 10018 if (*charfields++) { 10019 *wbuf = le16_to_cpu(wval); 10020 } else { 10021 *wbuf = wval; 10022 } 10023 } 10024 /* Read checksum word. */ 10025 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 10026 wbuf++; 10027 charfields++; 10028 10029 /* Read rest of EEPROM not covered by the checksum. */ 10030 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 10031 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 10032 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 10033 if (*charfields++) { 10034 *wbuf = le16_to_cpu(*wbuf); 10035 } 10036 } 10037 return chksum; 10038 } 10039 10040 /* 10041 * Read EEPROM configuration into the specified buffer. 10042 * 10043 * Return a checksum based on the EEPROM configuration read. 10044 */ 10045 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base, 10046 ADVEEP_38C1600_CONFIG *cfg_buf) 10047 { 10048 ushort wval, chksum; 10049 ushort *wbuf; 10050 int eep_addr; 10051 ushort *charfields; 10052 10053 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; 10054 wbuf = (ushort *)cfg_buf; 10055 chksum = 0; 10056 10057 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 10058 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 10059 wval = AdvReadEEPWord(iop_base, eep_addr); 10060 chksum += wval; /* Checksum is calculated from word values. */ 10061 if (*charfields++) { 10062 *wbuf = le16_to_cpu(wval); 10063 } else { 10064 *wbuf = wval; 10065 } 10066 } 10067 /* Read checksum word. */ 10068 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 10069 wbuf++; 10070 charfields++; 10071 10072 /* Read rest of EEPROM not covered by the checksum. */ 10073 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 10074 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 10075 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 10076 if (*charfields++) { 10077 *wbuf = le16_to_cpu(*wbuf); 10078 } 10079 } 10080 return chksum; 10081 } 10082 10083 /* 10084 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 10085 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 10086 * all of this is done. 10087 * 10088 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 10089 * 10090 * For a non-fatal error return a warning code. If there are no warnings 10091 * then 0 is returned. 10092 * 10093 * Note: Chip is stopped on entry. 10094 */ 10095 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc) 10096 { 10097 AdvPortAddr iop_base; 10098 ushort warn_code; 10099 ADVEEP_3550_CONFIG eep_config; 10100 10101 iop_base = asc_dvc->iop_base; 10102 10103 warn_code = 0; 10104 10105 /* 10106 * Read the board's EEPROM configuration. 10107 * 10108 * Set default values if a bad checksum is found. 10109 */ 10110 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) { 10111 warn_code |= ASC_WARN_EEPROM_CHKSUM; 10112 10113 /* 10114 * Set EEPROM default values. 10115 */ 10116 memcpy(&eep_config, &Default_3550_EEPROM_Config, 10117 sizeof(ADVEEP_3550_CONFIG)); 10118 10119 /* 10120 * Assume the 6 byte board serial number that was read from 10121 * EEPROM is correct even if the EEPROM checksum failed. 10122 */ 10123 eep_config.serial_number_word3 = 10124 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 10125 10126 eep_config.serial_number_word2 = 10127 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 10128 10129 eep_config.serial_number_word1 = 10130 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 10131 10132 AdvSet3550EEPConfig(iop_base, &eep_config); 10133 } 10134 /* 10135 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 10136 * EEPROM configuration that was read. 10137 * 10138 * This is the mapping of EEPROM fields to Adv Library fields. 10139 */ 10140 asc_dvc->wdtr_able = eep_config.wdtr_able; 10141 asc_dvc->sdtr_able = eep_config.sdtr_able; 10142 asc_dvc->ultra_able = eep_config.ultra_able; 10143 asc_dvc->tagqng_able = eep_config.tagqng_able; 10144 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 10145 asc_dvc->max_host_qng = eep_config.max_host_qng; 10146 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10147 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); 10148 asc_dvc->start_motor = eep_config.start_motor; 10149 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 10150 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 10151 asc_dvc->no_scam = eep_config.scam_tolerant; 10152 asc_dvc->cfg->serial1 = eep_config.serial_number_word1; 10153 asc_dvc->cfg->serial2 = eep_config.serial_number_word2; 10154 asc_dvc->cfg->serial3 = eep_config.serial_number_word3; 10155 10156 /* 10157 * Set the host maximum queuing (max. 253, min. 16) and the per device 10158 * maximum queuing (max. 63, min. 4). 10159 */ 10160 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 10161 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10162 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 10163 /* If the value is zero, assume it is uninitialized. */ 10164 if (eep_config.max_host_qng == 0) { 10165 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10166 } else { 10167 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 10168 } 10169 } 10170 10171 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 10172 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10173 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 10174 /* If the value is zero, assume it is uninitialized. */ 10175 if (eep_config.max_dvc_qng == 0) { 10176 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10177 } else { 10178 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 10179 } 10180 } 10181 10182 /* 10183 * If 'max_dvc_qng' is greater than 'max_host_qng', then 10184 * set 'max_dvc_qng' to 'max_host_qng'. 10185 */ 10186 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 10187 eep_config.max_dvc_qng = eep_config.max_host_qng; 10188 } 10189 10190 /* 10191 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 10192 * values based on possibly adjusted EEPROM values. 10193 */ 10194 asc_dvc->max_host_qng = eep_config.max_host_qng; 10195 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10196 10197 /* 10198 * If the EEPROM 'termination' field is set to automatic (0), then set 10199 * the ADV_DVC_CFG 'termination' field to automatic also. 10200 * 10201 * If the termination is specified with a non-zero 'termination' 10202 * value check that a legal value is set and set the ADV_DVC_CFG 10203 * 'termination' field appropriately. 10204 */ 10205 if (eep_config.termination == 0) { 10206 asc_dvc->cfg->termination = 0; /* auto termination */ 10207 } else { 10208 /* Enable manual control with low off / high off. */ 10209 if (eep_config.termination == 1) { 10210 asc_dvc->cfg->termination = TERM_CTL_SEL; 10211 10212 /* Enable manual control with low off / high on. */ 10213 } else if (eep_config.termination == 2) { 10214 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H; 10215 10216 /* Enable manual control with low on / high on. */ 10217 } else if (eep_config.termination == 3) { 10218 asc_dvc->cfg->termination = 10219 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L; 10220 } else { 10221 /* 10222 * The EEPROM 'termination' field contains a bad value. Use 10223 * automatic termination instead. 10224 */ 10225 asc_dvc->cfg->termination = 0; 10226 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10227 } 10228 } 10229 10230 return warn_code; 10231 } 10232 10233 /* 10234 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 10235 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 10236 * all of this is done. 10237 * 10238 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 10239 * 10240 * For a non-fatal error return a warning code. If there are no warnings 10241 * then 0 is returned. 10242 * 10243 * Note: Chip is stopped on entry. 10244 */ 10245 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc) 10246 { 10247 AdvPortAddr iop_base; 10248 ushort warn_code; 10249 ADVEEP_38C0800_CONFIG eep_config; 10250 uchar tid, termination; 10251 ushort sdtr_speed = 0; 10252 10253 iop_base = asc_dvc->iop_base; 10254 10255 warn_code = 0; 10256 10257 /* 10258 * Read the board's EEPROM configuration. 10259 * 10260 * Set default values if a bad checksum is found. 10261 */ 10262 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != 10263 eep_config.check_sum) { 10264 warn_code |= ASC_WARN_EEPROM_CHKSUM; 10265 10266 /* 10267 * Set EEPROM default values. 10268 */ 10269 memcpy(&eep_config, &Default_38C0800_EEPROM_Config, 10270 sizeof(ADVEEP_38C0800_CONFIG)); 10271 10272 /* 10273 * Assume the 6 byte board serial number that was read from 10274 * EEPROM is correct even if the EEPROM checksum failed. 10275 */ 10276 eep_config.serial_number_word3 = 10277 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 10278 10279 eep_config.serial_number_word2 = 10280 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 10281 10282 eep_config.serial_number_word1 = 10283 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 10284 10285 AdvSet38C0800EEPConfig(iop_base, &eep_config); 10286 } 10287 /* 10288 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the 10289 * EEPROM configuration that was read. 10290 * 10291 * This is the mapping of EEPROM fields to Adv Library fields. 10292 */ 10293 asc_dvc->wdtr_able = eep_config.wdtr_able; 10294 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; 10295 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; 10296 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; 10297 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; 10298 asc_dvc->tagqng_able = eep_config.tagqng_able; 10299 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 10300 asc_dvc->max_host_qng = eep_config.max_host_qng; 10301 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10302 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); 10303 asc_dvc->start_motor = eep_config.start_motor; 10304 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 10305 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 10306 asc_dvc->no_scam = eep_config.scam_tolerant; 10307 asc_dvc->cfg->serial1 = eep_config.serial_number_word1; 10308 asc_dvc->cfg->serial2 = eep_config.serial_number_word2; 10309 asc_dvc->cfg->serial3 = eep_config.serial_number_word3; 10310 10311 /* 10312 * For every Target ID if any of its 'sdtr_speed[1234]' bits 10313 * are set, then set an 'sdtr_able' bit for it. 10314 */ 10315 asc_dvc->sdtr_able = 0; 10316 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 10317 if (tid == 0) { 10318 sdtr_speed = asc_dvc->sdtr_speed1; 10319 } else if (tid == 4) { 10320 sdtr_speed = asc_dvc->sdtr_speed2; 10321 } else if (tid == 8) { 10322 sdtr_speed = asc_dvc->sdtr_speed3; 10323 } else if (tid == 12) { 10324 sdtr_speed = asc_dvc->sdtr_speed4; 10325 } 10326 if (sdtr_speed & ADV_MAX_TID) { 10327 asc_dvc->sdtr_able |= (1 << tid); 10328 } 10329 sdtr_speed >>= 4; 10330 } 10331 10332 /* 10333 * Set the host maximum queuing (max. 253, min. 16) and the per device 10334 * maximum queuing (max. 63, min. 4). 10335 */ 10336 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 10337 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10338 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 10339 /* If the value is zero, assume it is uninitialized. */ 10340 if (eep_config.max_host_qng == 0) { 10341 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10342 } else { 10343 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 10344 } 10345 } 10346 10347 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 10348 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10349 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 10350 /* If the value is zero, assume it is uninitialized. */ 10351 if (eep_config.max_dvc_qng == 0) { 10352 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10353 } else { 10354 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 10355 } 10356 } 10357 10358 /* 10359 * If 'max_dvc_qng' is greater than 'max_host_qng', then 10360 * set 'max_dvc_qng' to 'max_host_qng'. 10361 */ 10362 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 10363 eep_config.max_dvc_qng = eep_config.max_host_qng; 10364 } 10365 10366 /* 10367 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 10368 * values based on possibly adjusted EEPROM values. 10369 */ 10370 asc_dvc->max_host_qng = eep_config.max_host_qng; 10371 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10372 10373 /* 10374 * If the EEPROM 'termination' field is set to automatic (0), then set 10375 * the ADV_DVC_CFG 'termination' field to automatic also. 10376 * 10377 * If the termination is specified with a non-zero 'termination' 10378 * value check that a legal value is set and set the ADV_DVC_CFG 10379 * 'termination' field appropriately. 10380 */ 10381 if (eep_config.termination_se == 0) { 10382 termination = 0; /* auto termination for SE */ 10383 } else { 10384 /* Enable manual control with low off / high off. */ 10385 if (eep_config.termination_se == 1) { 10386 termination = 0; 10387 10388 /* Enable manual control with low off / high on. */ 10389 } else if (eep_config.termination_se == 2) { 10390 termination = TERM_SE_HI; 10391 10392 /* Enable manual control with low on / high on. */ 10393 } else if (eep_config.termination_se == 3) { 10394 termination = TERM_SE; 10395 } else { 10396 /* 10397 * The EEPROM 'termination_se' field contains a bad value. 10398 * Use automatic termination instead. 10399 */ 10400 termination = 0; 10401 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10402 } 10403 } 10404 10405 if (eep_config.termination_lvd == 0) { 10406 asc_dvc->cfg->termination = termination; /* auto termination for LVD */ 10407 } else { 10408 /* Enable manual control with low off / high off. */ 10409 if (eep_config.termination_lvd == 1) { 10410 asc_dvc->cfg->termination = termination; 10411 10412 /* Enable manual control with low off / high on. */ 10413 } else if (eep_config.termination_lvd == 2) { 10414 asc_dvc->cfg->termination = termination | TERM_LVD_HI; 10415 10416 /* Enable manual control with low on / high on. */ 10417 } else if (eep_config.termination_lvd == 3) { 10418 asc_dvc->cfg->termination = termination | TERM_LVD; 10419 } else { 10420 /* 10421 * The EEPROM 'termination_lvd' field contains a bad value. 10422 * Use automatic termination instead. 10423 */ 10424 asc_dvc->cfg->termination = termination; 10425 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10426 } 10427 } 10428 10429 return warn_code; 10430 } 10431 10432 /* 10433 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and 10434 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while 10435 * all of this is done. 10436 * 10437 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 10438 * 10439 * For a non-fatal error return a warning code. If there are no warnings 10440 * then 0 is returned. 10441 * 10442 * Note: Chip is stopped on entry. 10443 */ 10444 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc) 10445 { 10446 AdvPortAddr iop_base; 10447 ushort warn_code; 10448 ADVEEP_38C1600_CONFIG eep_config; 10449 uchar tid, termination; 10450 ushort sdtr_speed = 0; 10451 10452 iop_base = asc_dvc->iop_base; 10453 10454 warn_code = 0; 10455 10456 /* 10457 * Read the board's EEPROM configuration. 10458 * 10459 * Set default values if a bad checksum is found. 10460 */ 10461 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != 10462 eep_config.check_sum) { 10463 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); 10464 warn_code |= ASC_WARN_EEPROM_CHKSUM; 10465 10466 /* 10467 * Set EEPROM default values. 10468 */ 10469 memcpy(&eep_config, &Default_38C1600_EEPROM_Config, 10470 sizeof(ADVEEP_38C1600_CONFIG)); 10471 10472 if (PCI_FUNC(pdev->devfn) != 0) { 10473 u8 ints; 10474 /* 10475 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 10476 * and old Mac system booting problem. The Expansion 10477 * ROM must be disabled in Function 1 for these systems 10478 */ 10479 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE; 10480 /* 10481 * Clear the INTAB (bit 11) if the GPIO 0 input 10482 * indicates the Function 1 interrupt line is wired 10483 * to INTB. 10484 * 10485 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input: 10486 * 1 - Function 1 interrupt line wired to INT A. 10487 * 0 - Function 1 interrupt line wired to INT B. 10488 * 10489 * Note: Function 0 is always wired to INTA. 10490 * Put all 5 GPIO bits in input mode and then read 10491 * their input values. 10492 */ 10493 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0); 10494 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA); 10495 if ((ints & 0x01) == 0) 10496 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB; 10497 } 10498 10499 /* 10500 * Assume the 6 byte board serial number that was read from 10501 * EEPROM is correct even if the EEPROM checksum failed. 10502 */ 10503 eep_config.serial_number_word3 = 10504 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 10505 eep_config.serial_number_word2 = 10506 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 10507 eep_config.serial_number_word1 = 10508 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 10509 10510 AdvSet38C1600EEPConfig(iop_base, &eep_config); 10511 } 10512 10513 /* 10514 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 10515 * EEPROM configuration that was read. 10516 * 10517 * This is the mapping of EEPROM fields to Adv Library fields. 10518 */ 10519 asc_dvc->wdtr_able = eep_config.wdtr_able; 10520 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; 10521 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; 10522 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; 10523 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; 10524 asc_dvc->ppr_able = 0; 10525 asc_dvc->tagqng_able = eep_config.tagqng_able; 10526 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 10527 asc_dvc->max_host_qng = eep_config.max_host_qng; 10528 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10529 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID); 10530 asc_dvc->start_motor = eep_config.start_motor; 10531 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 10532 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 10533 asc_dvc->no_scam = eep_config.scam_tolerant; 10534 10535 /* 10536 * For every Target ID if any of its 'sdtr_speed[1234]' bits 10537 * are set, then set an 'sdtr_able' bit for it. 10538 */ 10539 asc_dvc->sdtr_able = 0; 10540 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 10541 if (tid == 0) { 10542 sdtr_speed = asc_dvc->sdtr_speed1; 10543 } else if (tid == 4) { 10544 sdtr_speed = asc_dvc->sdtr_speed2; 10545 } else if (tid == 8) { 10546 sdtr_speed = asc_dvc->sdtr_speed3; 10547 } else if (tid == 12) { 10548 sdtr_speed = asc_dvc->sdtr_speed4; 10549 } 10550 if (sdtr_speed & ASC_MAX_TID) { 10551 asc_dvc->sdtr_able |= (1 << tid); 10552 } 10553 sdtr_speed >>= 4; 10554 } 10555 10556 /* 10557 * Set the host maximum queuing (max. 253, min. 16) and the per device 10558 * maximum queuing (max. 63, min. 4). 10559 */ 10560 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 10561 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10562 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 10563 /* If the value is zero, assume it is uninitialized. */ 10564 if (eep_config.max_host_qng == 0) { 10565 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10566 } else { 10567 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 10568 } 10569 } 10570 10571 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 10572 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10573 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 10574 /* If the value is zero, assume it is uninitialized. */ 10575 if (eep_config.max_dvc_qng == 0) { 10576 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10577 } else { 10578 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 10579 } 10580 } 10581 10582 /* 10583 * If 'max_dvc_qng' is greater than 'max_host_qng', then 10584 * set 'max_dvc_qng' to 'max_host_qng'. 10585 */ 10586 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 10587 eep_config.max_dvc_qng = eep_config.max_host_qng; 10588 } 10589 10590 /* 10591 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng' 10592 * values based on possibly adjusted EEPROM values. 10593 */ 10594 asc_dvc->max_host_qng = eep_config.max_host_qng; 10595 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10596 10597 /* 10598 * If the EEPROM 'termination' field is set to automatic (0), then set 10599 * the ASC_DVC_CFG 'termination' field to automatic also. 10600 * 10601 * If the termination is specified with a non-zero 'termination' 10602 * value check that a legal value is set and set the ASC_DVC_CFG 10603 * 'termination' field appropriately. 10604 */ 10605 if (eep_config.termination_se == 0) { 10606 termination = 0; /* auto termination for SE */ 10607 } else { 10608 /* Enable manual control with low off / high off. */ 10609 if (eep_config.termination_se == 1) { 10610 termination = 0; 10611 10612 /* Enable manual control with low off / high on. */ 10613 } else if (eep_config.termination_se == 2) { 10614 termination = TERM_SE_HI; 10615 10616 /* Enable manual control with low on / high on. */ 10617 } else if (eep_config.termination_se == 3) { 10618 termination = TERM_SE; 10619 } else { 10620 /* 10621 * The EEPROM 'termination_se' field contains a bad value. 10622 * Use automatic termination instead. 10623 */ 10624 termination = 0; 10625 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10626 } 10627 } 10628 10629 if (eep_config.termination_lvd == 0) { 10630 asc_dvc->cfg->termination = termination; /* auto termination for LVD */ 10631 } else { 10632 /* Enable manual control with low off / high off. */ 10633 if (eep_config.termination_lvd == 1) { 10634 asc_dvc->cfg->termination = termination; 10635 10636 /* Enable manual control with low off / high on. */ 10637 } else if (eep_config.termination_lvd == 2) { 10638 asc_dvc->cfg->termination = termination | TERM_LVD_HI; 10639 10640 /* Enable manual control with low on / high on. */ 10641 } else if (eep_config.termination_lvd == 3) { 10642 asc_dvc->cfg->termination = termination | TERM_LVD; 10643 } else { 10644 /* 10645 * The EEPROM 'termination_lvd' field contains a bad value. 10646 * Use automatic termination instead. 10647 */ 10648 asc_dvc->cfg->termination = termination; 10649 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10650 } 10651 } 10652 10653 return warn_code; 10654 } 10655 10656 /* 10657 * Initialize the ADV_DVC_VAR structure. 10658 * 10659 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 10660 * 10661 * For a non-fatal error return a warning code. If there are no warnings 10662 * then 0 is returned. 10663 */ 10664 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) 10665 { 10666 struct asc_board *board = shost_priv(shost); 10667 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var; 10668 unsigned short warn_code = 0; 10669 AdvPortAddr iop_base = asc_dvc->iop_base; 10670 u16 cmd; 10671 int status; 10672 10673 asc_dvc->err_code = 0; 10674 10675 /* 10676 * Save the state of the PCI Configuration Command Register 10677 * "Parity Error Response Control" Bit. If the bit is clear (0), 10678 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore 10679 * DMA parity errors. 10680 */ 10681 asc_dvc->cfg->control_flag = 0; 10682 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 10683 if ((cmd & PCI_COMMAND_PARITY) == 0) 10684 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR; 10685 10686 asc_dvc->cfg->chip_version = 10687 AdvGetChipVersion(iop_base, asc_dvc->bus_type); 10688 10689 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n", 10690 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1), 10691 (ushort)ADV_CHIP_ID_BYTE); 10692 10693 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n", 10694 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0), 10695 (ushort)ADV_CHIP_ID_WORD); 10696 10697 /* 10698 * Reset the chip to start and allow register writes. 10699 */ 10700 if (AdvFindSignature(iop_base) == 0) { 10701 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 10702 return ADV_ERROR; 10703 } else { 10704 /* 10705 * The caller must set 'chip_type' to a valid setting. 10706 */ 10707 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 && 10708 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 && 10709 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { 10710 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE; 10711 return ADV_ERROR; 10712 } 10713 10714 /* 10715 * Reset Chip. 10716 */ 10717 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 10718 ADV_CTRL_REG_CMD_RESET); 10719 mdelay(100); 10720 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 10721 ADV_CTRL_REG_CMD_WR_IO_REG); 10722 10723 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 10724 status = AdvInitFrom38C1600EEP(asc_dvc); 10725 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 10726 status = AdvInitFrom38C0800EEP(asc_dvc); 10727 } else { 10728 status = AdvInitFrom3550EEP(asc_dvc); 10729 } 10730 warn_code |= status; 10731 } 10732 10733 if (warn_code != 0) 10734 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code); 10735 10736 if (asc_dvc->err_code) 10737 shost_printk(KERN_ERR, shost, "error code 0x%x\n", 10738 asc_dvc->err_code); 10739 10740 return asc_dvc->err_code; 10741 } 10742 #endif 10743 10744 static struct scsi_host_template advansys_template = { 10745 .proc_name = DRV_NAME, 10746 #ifdef CONFIG_PROC_FS 10747 .show_info = advansys_show_info, 10748 #endif 10749 .name = DRV_NAME, 10750 .info = advansys_info, 10751 .queuecommand = advansys_queuecommand, 10752 .eh_host_reset_handler = advansys_reset, 10753 .bios_param = advansys_biosparam, 10754 .slave_configure = advansys_slave_configure, 10755 /* 10756 * Because the driver may control an ISA adapter 'unchecked_isa_dma' 10757 * must be set. The flag will be cleared in advansys_board_found 10758 * for non-ISA adapters. 10759 */ 10760 .unchecked_isa_dma = true, 10761 }; 10762 10763 static int advansys_wide_init_chip(struct Scsi_Host *shost) 10764 { 10765 struct asc_board *board = shost_priv(shost); 10766 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var; 10767 size_t sgblk_pool_size; 10768 int warn_code, err_code; 10769 10770 /* 10771 * Allocate buffer carrier structures. The total size 10772 * is about 8 KB, so allocate all at once. 10773 */ 10774 adv_dvc->carrier = dma_alloc_coherent(board->dev, 10775 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL); 10776 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier); 10777 10778 if (!adv_dvc->carrier) 10779 goto kmalloc_failed; 10780 10781 /* 10782 * Allocate up to 'max_host_qng' request structures for the Wide 10783 * board. The total size is about 16 KB, so allocate all at once. 10784 * If the allocation fails decrement and try again. 10785 */ 10786 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t); 10787 if (board->adv_reqp_size & 0x1f) { 10788 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t)); 10789 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size); 10790 } 10791 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size, 10792 &board->adv_reqp_addr, GFP_KERNEL); 10793 10794 if (!board->adv_reqp) 10795 goto kmalloc_failed; 10796 10797 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp, 10798 adv_dvc->max_host_qng, board->adv_reqp_size); 10799 10800 /* 10801 * Allocate up to ADV_TOT_SG_BLOCK request structures for 10802 * the Wide board. Each structure is about 136 bytes. 10803 */ 10804 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK; 10805 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev, 10806 sgblk_pool_size, 32, 0); 10807 10808 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK, 10809 sizeof(adv_sgblk_t), sgblk_pool_size); 10810 10811 if (!board->adv_sgblk_pool) 10812 goto kmalloc_failed; 10813 10814 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) { 10815 ASC_DBG(2, "AdvInitAsc3550Driver()\n"); 10816 warn_code = AdvInitAsc3550Driver(adv_dvc); 10817 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) { 10818 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n"); 10819 warn_code = AdvInitAsc38C0800Driver(adv_dvc); 10820 } else { 10821 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n"); 10822 warn_code = AdvInitAsc38C1600Driver(adv_dvc); 10823 } 10824 err_code = adv_dvc->err_code; 10825 10826 if (warn_code || err_code) { 10827 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error " 10828 "0x%x\n", warn_code, err_code); 10829 } 10830 10831 goto exit; 10832 10833 kmalloc_failed: 10834 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n"); 10835 err_code = ADV_ERROR; 10836 exit: 10837 return err_code; 10838 } 10839 10840 static void advansys_wide_free_mem(struct asc_board *board) 10841 { 10842 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var; 10843 10844 if (adv_dvc->carrier) { 10845 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE, 10846 adv_dvc->carrier, adv_dvc->carrier_addr); 10847 adv_dvc->carrier = NULL; 10848 } 10849 if (board->adv_reqp) { 10850 dma_free_coherent(board->dev, board->adv_reqp_size, 10851 board->adv_reqp, board->adv_reqp_addr); 10852 board->adv_reqp = NULL; 10853 } 10854 if (board->adv_sgblk_pool) { 10855 dma_pool_destroy(board->adv_sgblk_pool); 10856 board->adv_sgblk_pool = NULL; 10857 } 10858 } 10859 10860 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop, 10861 int bus_type) 10862 { 10863 struct pci_dev *pdev; 10864 struct asc_board *boardp = shost_priv(shost); 10865 ASC_DVC_VAR *asc_dvc_varp = NULL; 10866 ADV_DVC_VAR *adv_dvc_varp = NULL; 10867 int share_irq, warn_code, ret; 10868 10869 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL; 10870 10871 if (ASC_NARROW_BOARD(boardp)) { 10872 ASC_DBG(1, "narrow board\n"); 10873 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 10874 asc_dvc_varp->bus_type = bus_type; 10875 asc_dvc_varp->drv_ptr = boardp; 10876 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg; 10877 asc_dvc_varp->iop_base = iop; 10878 } else { 10879 #ifdef CONFIG_PCI 10880 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 10881 adv_dvc_varp->drv_ptr = boardp; 10882 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg; 10883 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) { 10884 ASC_DBG(1, "wide board ASC-3550\n"); 10885 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550; 10886 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) { 10887 ASC_DBG(1, "wide board ASC-38C0800\n"); 10888 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800; 10889 } else { 10890 ASC_DBG(1, "wide board ASC-38C1600\n"); 10891 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600; 10892 } 10893 10894 boardp->asc_n_io_port = pci_resource_len(pdev, 1); 10895 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1); 10896 if (!boardp->ioremap_addr) { 10897 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) " 10898 "returned NULL\n", 10899 (long)pci_resource_start(pdev, 1), 10900 boardp->asc_n_io_port); 10901 ret = -ENODEV; 10902 goto err_shost; 10903 } 10904 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr; 10905 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base); 10906 10907 /* 10908 * Even though it isn't used to access wide boards, other 10909 * than for the debug line below, save I/O Port address so 10910 * that it can be reported. 10911 */ 10912 boardp->ioport = iop; 10913 10914 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n", 10915 (ushort)inp(iop + 1), (ushort)inpw(iop)); 10916 #endif /* CONFIG_PCI */ 10917 } 10918 10919 if (ASC_NARROW_BOARD(boardp)) { 10920 /* 10921 * Set the board bus type and PCI IRQ before 10922 * calling AscInitGetConfig(). 10923 */ 10924 switch (asc_dvc_varp->bus_type) { 10925 #ifdef CONFIG_ISA 10926 case ASC_IS_ISA: 10927 shost->unchecked_isa_dma = true; 10928 share_irq = 0; 10929 break; 10930 case ASC_IS_VL: 10931 shost->unchecked_isa_dma = false; 10932 share_irq = 0; 10933 break; 10934 case ASC_IS_EISA: 10935 shost->unchecked_isa_dma = false; 10936 share_irq = IRQF_SHARED; 10937 break; 10938 #endif /* CONFIG_ISA */ 10939 #ifdef CONFIG_PCI 10940 case ASC_IS_PCI: 10941 shost->unchecked_isa_dma = false; 10942 share_irq = IRQF_SHARED; 10943 break; 10944 #endif /* CONFIG_PCI */ 10945 default: 10946 shost_printk(KERN_ERR, shost, "unknown adapter type: " 10947 "%d\n", asc_dvc_varp->bus_type); 10948 shost->unchecked_isa_dma = false; 10949 share_irq = 0; 10950 break; 10951 } 10952 10953 /* 10954 * NOTE: AscInitGetConfig() may change the board's 10955 * bus_type value. The bus_type value should no 10956 * longer be used. If the bus_type field must be 10957 * referenced only use the bit-wise AND operator "&". 10958 */ 10959 ASC_DBG(2, "AscInitGetConfig()\n"); 10960 ret = AscInitGetConfig(shost) ? -ENODEV : 0; 10961 } else { 10962 #ifdef CONFIG_PCI 10963 /* 10964 * For Wide boards set PCI information before calling 10965 * AdvInitGetConfig(). 10966 */ 10967 shost->unchecked_isa_dma = false; 10968 share_irq = IRQF_SHARED; 10969 ASC_DBG(2, "AdvInitGetConfig()\n"); 10970 10971 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0; 10972 #else 10973 share_irq = 0; 10974 ret = -ENODEV; 10975 #endif /* CONFIG_PCI */ 10976 } 10977 10978 if (ret) 10979 goto err_unmap; 10980 10981 /* 10982 * Save the EEPROM configuration so that it can be displayed 10983 * from /proc/scsi/advansys/[0...]. 10984 */ 10985 if (ASC_NARROW_BOARD(boardp)) { 10986 10987 ASCEEP_CONFIG *ep; 10988 10989 /* 10990 * Set the adapter's target id bit in the 'init_tidmask' field. 10991 */ 10992 boardp->init_tidmask |= 10993 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id); 10994 10995 /* 10996 * Save EEPROM settings for the board. 10997 */ 10998 ep = &boardp->eep_config.asc_eep; 10999 11000 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable; 11001 ep->disc_enable = asc_dvc_varp->cfg->disc_enable; 11002 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled; 11003 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed); 11004 ep->start_motor = asc_dvc_varp->start_motor; 11005 ep->cntl = asc_dvc_varp->dvc_cntl; 11006 ep->no_scam = asc_dvc_varp->no_scam; 11007 ep->max_total_qng = asc_dvc_varp->max_total_qng; 11008 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id); 11009 /* 'max_tag_qng' is set to the same value for every device. */ 11010 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0]; 11011 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0]; 11012 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1]; 11013 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2]; 11014 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3]; 11015 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4]; 11016 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5]; 11017 11018 /* 11019 * Modify board configuration. 11020 */ 11021 ASC_DBG(2, "AscInitSetConfig()\n"); 11022 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0; 11023 if (ret) 11024 goto err_unmap; 11025 } else { 11026 ADVEEP_3550_CONFIG *ep_3550; 11027 ADVEEP_38C0800_CONFIG *ep_38C0800; 11028 ADVEEP_38C1600_CONFIG *ep_38C1600; 11029 11030 /* 11031 * Save Wide EEP Configuration Information. 11032 */ 11033 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 11034 ep_3550 = &boardp->eep_config.adv_3550_eep; 11035 11036 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id; 11037 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng; 11038 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 11039 ep_3550->termination = adv_dvc_varp->cfg->termination; 11040 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable; 11041 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl; 11042 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able; 11043 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able; 11044 ep_3550->ultra_able = adv_dvc_varp->ultra_able; 11045 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able; 11046 ep_3550->start_motor = adv_dvc_varp->start_motor; 11047 ep_3550->scsi_reset_delay = 11048 adv_dvc_varp->scsi_reset_wait; 11049 ep_3550->serial_number_word1 = 11050 adv_dvc_varp->cfg->serial1; 11051 ep_3550->serial_number_word2 = 11052 adv_dvc_varp->cfg->serial2; 11053 ep_3550->serial_number_word3 = 11054 adv_dvc_varp->cfg->serial3; 11055 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 11056 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; 11057 11058 ep_38C0800->adapter_scsi_id = 11059 adv_dvc_varp->chip_scsi_id; 11060 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng; 11061 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 11062 ep_38C0800->termination_lvd = 11063 adv_dvc_varp->cfg->termination; 11064 ep_38C0800->disc_enable = 11065 adv_dvc_varp->cfg->disc_enable; 11066 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl; 11067 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able; 11068 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; 11069 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; 11070 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; 11071 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; 11072 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; 11073 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; 11074 ep_38C0800->start_motor = adv_dvc_varp->start_motor; 11075 ep_38C0800->scsi_reset_delay = 11076 adv_dvc_varp->scsi_reset_wait; 11077 ep_38C0800->serial_number_word1 = 11078 adv_dvc_varp->cfg->serial1; 11079 ep_38C0800->serial_number_word2 = 11080 adv_dvc_varp->cfg->serial2; 11081 ep_38C0800->serial_number_word3 = 11082 adv_dvc_varp->cfg->serial3; 11083 } else { 11084 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; 11085 11086 ep_38C1600->adapter_scsi_id = 11087 adv_dvc_varp->chip_scsi_id; 11088 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng; 11089 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 11090 ep_38C1600->termination_lvd = 11091 adv_dvc_varp->cfg->termination; 11092 ep_38C1600->disc_enable = 11093 adv_dvc_varp->cfg->disc_enable; 11094 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl; 11095 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able; 11096 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; 11097 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; 11098 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; 11099 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; 11100 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; 11101 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; 11102 ep_38C1600->start_motor = adv_dvc_varp->start_motor; 11103 ep_38C1600->scsi_reset_delay = 11104 adv_dvc_varp->scsi_reset_wait; 11105 ep_38C1600->serial_number_word1 = 11106 adv_dvc_varp->cfg->serial1; 11107 ep_38C1600->serial_number_word2 = 11108 adv_dvc_varp->cfg->serial2; 11109 ep_38C1600->serial_number_word3 = 11110 adv_dvc_varp->cfg->serial3; 11111 } 11112 11113 /* 11114 * Set the adapter's target id bit in the 'init_tidmask' field. 11115 */ 11116 boardp->init_tidmask |= 11117 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id); 11118 } 11119 11120 /* 11121 * Channels are numbered beginning with 0. For AdvanSys one host 11122 * structure supports one channel. Multi-channel boards have a 11123 * separate host structure for each channel. 11124 */ 11125 shost->max_channel = 0; 11126 if (ASC_NARROW_BOARD(boardp)) { 11127 shost->max_id = ASC_MAX_TID + 1; 11128 shost->max_lun = ASC_MAX_LUN + 1; 11129 shost->max_cmd_len = ASC_MAX_CDB_LEN; 11130 11131 shost->io_port = asc_dvc_varp->iop_base; 11132 boardp->asc_n_io_port = ASC_IOADR_GAP; 11133 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id; 11134 11135 /* Set maximum number of queues the adapter can handle. */ 11136 shost->can_queue = asc_dvc_varp->max_total_qng; 11137 } else { 11138 shost->max_id = ADV_MAX_TID + 1; 11139 shost->max_lun = ADV_MAX_LUN + 1; 11140 shost->max_cmd_len = ADV_MAX_CDB_LEN; 11141 11142 /* 11143 * Save the I/O Port address and length even though 11144 * I/O ports are not used to access Wide boards. 11145 * Instead the Wide boards are accessed with 11146 * PCI Memory Mapped I/O. 11147 */ 11148 shost->io_port = iop; 11149 11150 shost->this_id = adv_dvc_varp->chip_scsi_id; 11151 11152 /* Set maximum number of queues the adapter can handle. */ 11153 shost->can_queue = adv_dvc_varp->max_host_qng; 11154 } 11155 11156 /* 11157 * Set the maximum number of scatter-gather elements the 11158 * adapter can handle. 11159 */ 11160 if (ASC_NARROW_BOARD(boardp)) { 11161 /* 11162 * Allow two commands with 'sg_tablesize' scatter-gather 11163 * elements to be executed simultaneously. This value is 11164 * the theoretical hardware limit. It may be decreased 11165 * below. 11166 */ 11167 shost->sg_tablesize = 11168 (((asc_dvc_varp->max_total_qng - 2) / 2) * 11169 ASC_SG_LIST_PER_Q) + 1; 11170 } else { 11171 shost->sg_tablesize = ADV_MAX_SG_LIST; 11172 } 11173 11174 /* 11175 * The value of 'sg_tablesize' can not exceed the SCSI 11176 * mid-level driver definition of SG_ALL. SG_ALL also 11177 * must not be exceeded, because it is used to define the 11178 * size of the scatter-gather table in 'struct asc_sg_head'. 11179 */ 11180 if (shost->sg_tablesize > SG_ALL) { 11181 shost->sg_tablesize = SG_ALL; 11182 } 11183 11184 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize); 11185 11186 /* BIOS start address. */ 11187 if (ASC_NARROW_BOARD(boardp)) { 11188 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base, 11189 asc_dvc_varp->bus_type); 11190 } else { 11191 /* 11192 * Fill-in BIOS board variables. The Wide BIOS saves 11193 * information in LRAM that is used by the driver. 11194 */ 11195 AdvReadWordLram(adv_dvc_varp->iop_base, 11196 BIOS_SIGNATURE, boardp->bios_signature); 11197 AdvReadWordLram(adv_dvc_varp->iop_base, 11198 BIOS_VERSION, boardp->bios_version); 11199 AdvReadWordLram(adv_dvc_varp->iop_base, 11200 BIOS_CODESEG, boardp->bios_codeseg); 11201 AdvReadWordLram(adv_dvc_varp->iop_base, 11202 BIOS_CODELEN, boardp->bios_codelen); 11203 11204 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n", 11205 boardp->bios_signature, boardp->bios_version); 11206 11207 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n", 11208 boardp->bios_codeseg, boardp->bios_codelen); 11209 11210 /* 11211 * If the BIOS saved a valid signature, then fill in 11212 * the BIOS code segment base address. 11213 */ 11214 if (boardp->bios_signature == 0x55AA) { 11215 /* 11216 * Convert x86 realmode code segment to a linear 11217 * address by shifting left 4. 11218 */ 11219 shost->base = ((ulong)boardp->bios_codeseg << 4); 11220 } else { 11221 shost->base = 0; 11222 } 11223 } 11224 11225 /* 11226 * Register Board Resources - I/O Port, DMA, IRQ 11227 */ 11228 11229 /* Register DMA Channel for Narrow boards. */ 11230 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */ 11231 #ifdef CONFIG_ISA 11232 if (ASC_NARROW_BOARD(boardp)) { 11233 /* Register DMA channel for ISA bus. */ 11234 if (asc_dvc_varp->bus_type & ASC_IS_ISA) { 11235 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel; 11236 ret = request_dma(shost->dma_channel, DRV_NAME); 11237 if (ret) { 11238 shost_printk(KERN_ERR, shost, "request_dma() " 11239 "%d failed %d\n", 11240 shost->dma_channel, ret); 11241 goto err_unmap; 11242 } 11243 AscEnableIsaDma(shost->dma_channel); 11244 } 11245 } 11246 #endif /* CONFIG_ISA */ 11247 11248 /* Register IRQ Number. */ 11249 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost); 11250 11251 ret = request_irq(boardp->irq, advansys_interrupt, share_irq, 11252 DRV_NAME, shost); 11253 11254 if (ret) { 11255 if (ret == -EBUSY) { 11256 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 11257 "already in use\n", boardp->irq); 11258 } else if (ret == -EINVAL) { 11259 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 11260 "not valid\n", boardp->irq); 11261 } else { 11262 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 11263 "failed with %d\n", boardp->irq, ret); 11264 } 11265 goto err_free_dma; 11266 } 11267 11268 /* 11269 * Initialize board RISC chip and enable interrupts. 11270 */ 11271 if (ASC_NARROW_BOARD(boardp)) { 11272 ASC_DBG(2, "AscInitAsc1000Driver()\n"); 11273 11274 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL); 11275 if (!asc_dvc_varp->overrun_buf) { 11276 ret = -ENOMEM; 11277 goto err_free_irq; 11278 } 11279 warn_code = AscInitAsc1000Driver(asc_dvc_varp); 11280 11281 if (warn_code || asc_dvc_varp->err_code) { 11282 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, " 11283 "warn 0x%x, error 0x%x\n", 11284 asc_dvc_varp->init_state, warn_code, 11285 asc_dvc_varp->err_code); 11286 if (!asc_dvc_varp->overrun_dma) { 11287 ret = -ENODEV; 11288 goto err_free_mem; 11289 } 11290 } 11291 } else { 11292 if (advansys_wide_init_chip(shost)) { 11293 ret = -ENODEV; 11294 goto err_free_mem; 11295 } 11296 } 11297 11298 ASC_DBG_PRT_SCSI_HOST(2, shost); 11299 11300 ret = scsi_add_host(shost, boardp->dev); 11301 if (ret) 11302 goto err_free_mem; 11303 11304 scsi_scan_host(shost); 11305 return 0; 11306 11307 err_free_mem: 11308 if (ASC_NARROW_BOARD(boardp)) { 11309 if (asc_dvc_varp->overrun_dma) 11310 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma, 11311 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 11312 kfree(asc_dvc_varp->overrun_buf); 11313 } else 11314 advansys_wide_free_mem(boardp); 11315 err_free_irq: 11316 free_irq(boardp->irq, shost); 11317 err_free_dma: 11318 #ifdef CONFIG_ISA 11319 if (shost->dma_channel != NO_ISA_DMA) 11320 free_dma(shost->dma_channel); 11321 #endif 11322 err_unmap: 11323 if (boardp->ioremap_addr) 11324 iounmap(boardp->ioremap_addr); 11325 #ifdef CONFIG_PCI 11326 err_shost: 11327 #endif 11328 return ret; 11329 } 11330 11331 /* 11332 * advansys_release() 11333 * 11334 * Release resources allocated for a single AdvanSys adapter. 11335 */ 11336 static int advansys_release(struct Scsi_Host *shost) 11337 { 11338 struct asc_board *board = shost_priv(shost); 11339 ASC_DBG(1, "begin\n"); 11340 scsi_remove_host(shost); 11341 free_irq(board->irq, shost); 11342 #ifdef CONFIG_ISA 11343 if (shost->dma_channel != NO_ISA_DMA) { 11344 ASC_DBG(1, "free_dma()\n"); 11345 free_dma(shost->dma_channel); 11346 } 11347 #endif 11348 if (ASC_NARROW_BOARD(board)) { 11349 dma_unmap_single(board->dev, 11350 board->dvc_var.asc_dvc_var.overrun_dma, 11351 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 11352 kfree(board->dvc_var.asc_dvc_var.overrun_buf); 11353 } else { 11354 iounmap(board->ioremap_addr); 11355 advansys_wide_free_mem(board); 11356 } 11357 scsi_host_put(shost); 11358 ASC_DBG(1, "end\n"); 11359 return 0; 11360 } 11361 11362 #define ASC_IOADR_TABLE_MAX_IX 11 11363 11364 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = { 11365 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190, 11366 0x0210, 0x0230, 0x0250, 0x0330 11367 }; 11368 11369 /* 11370 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as: 11371 * 00: 10 11372 * 01: 11 11373 * 10: 12 11374 * 11: 15 11375 */ 11376 static unsigned int advansys_isa_irq_no(PortAddr iop_base) 11377 { 11378 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base); 11379 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10; 11380 if (chip_irq == 13) 11381 chip_irq = 15; 11382 return chip_irq; 11383 } 11384 11385 static int advansys_isa_probe(struct device *dev, unsigned int id) 11386 { 11387 int err = -ENODEV; 11388 PortAddr iop_base = _asc_def_iop_base[id]; 11389 struct Scsi_Host *shost; 11390 struct asc_board *board; 11391 11392 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) { 11393 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base); 11394 return -ENODEV; 11395 } 11396 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base); 11397 if (!AscFindSignature(iop_base)) 11398 goto release_region; 11399 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT)) 11400 goto release_region; 11401 11402 err = -ENOMEM; 11403 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11404 if (!shost) 11405 goto release_region; 11406 11407 board = shost_priv(shost); 11408 board->irq = advansys_isa_irq_no(iop_base); 11409 board->dev = dev; 11410 board->shost = shost; 11411 11412 err = advansys_board_found(shost, iop_base, ASC_IS_ISA); 11413 if (err) 11414 goto free_host; 11415 11416 dev_set_drvdata(dev, shost); 11417 return 0; 11418 11419 free_host: 11420 scsi_host_put(shost); 11421 release_region: 11422 release_region(iop_base, ASC_IOADR_GAP); 11423 return err; 11424 } 11425 11426 static void advansys_isa_remove(struct device *dev, unsigned int id) 11427 { 11428 int ioport = _asc_def_iop_base[id]; 11429 advansys_release(dev_get_drvdata(dev)); 11430 release_region(ioport, ASC_IOADR_GAP); 11431 } 11432 11433 static struct isa_driver advansys_isa_driver = { 11434 .probe = advansys_isa_probe, 11435 .remove = advansys_isa_remove, 11436 .driver = { 11437 .owner = THIS_MODULE, 11438 .name = DRV_NAME, 11439 }, 11440 }; 11441 11442 /* 11443 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as: 11444 * 000: invalid 11445 * 001: 10 11446 * 010: 11 11447 * 011: 12 11448 * 100: invalid 11449 * 101: 14 11450 * 110: 15 11451 * 111: invalid 11452 */ 11453 static unsigned int advansys_vlb_irq_no(PortAddr iop_base) 11454 { 11455 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base); 11456 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9; 11457 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15)) 11458 return 0; 11459 return chip_irq; 11460 } 11461 11462 static int advansys_vlb_probe(struct device *dev, unsigned int id) 11463 { 11464 int err = -ENODEV; 11465 PortAddr iop_base = _asc_def_iop_base[id]; 11466 struct Scsi_Host *shost; 11467 struct asc_board *board; 11468 11469 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) { 11470 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base); 11471 return -ENODEV; 11472 } 11473 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base); 11474 if (!AscFindSignature(iop_base)) 11475 goto release_region; 11476 /* 11477 * I don't think this condition can actually happen, but the old 11478 * driver did it, and the chances of finding a VLB setup in 2007 11479 * to do testing with is slight to none. 11480 */ 11481 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL) 11482 goto release_region; 11483 11484 err = -ENOMEM; 11485 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11486 if (!shost) 11487 goto release_region; 11488 11489 board = shost_priv(shost); 11490 board->irq = advansys_vlb_irq_no(iop_base); 11491 board->dev = dev; 11492 board->shost = shost; 11493 11494 err = advansys_board_found(shost, iop_base, ASC_IS_VL); 11495 if (err) 11496 goto free_host; 11497 11498 dev_set_drvdata(dev, shost); 11499 return 0; 11500 11501 free_host: 11502 scsi_host_put(shost); 11503 release_region: 11504 release_region(iop_base, ASC_IOADR_GAP); 11505 return -ENODEV; 11506 } 11507 11508 static struct isa_driver advansys_vlb_driver = { 11509 .probe = advansys_vlb_probe, 11510 .remove = advansys_isa_remove, 11511 .driver = { 11512 .owner = THIS_MODULE, 11513 .name = "advansys_vlb", 11514 }, 11515 }; 11516 11517 static struct eisa_device_id advansys_eisa_table[] = { 11518 { "ABP7401" }, 11519 { "ABP7501" }, 11520 { "" } 11521 }; 11522 11523 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table); 11524 11525 /* 11526 * EISA is a little more tricky than PCI; each EISA device may have two 11527 * channels, and this driver is written to make each channel its own Scsi_Host 11528 */ 11529 struct eisa_scsi_data { 11530 struct Scsi_Host *host[2]; 11531 }; 11532 11533 /* 11534 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as: 11535 * 000: 10 11536 * 001: 11 11537 * 010: 12 11538 * 011: invalid 11539 * 100: 14 11540 * 101: 15 11541 * 110: invalid 11542 * 111: invalid 11543 */ 11544 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev) 11545 { 11546 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86); 11547 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10; 11548 if ((chip_irq == 13) || (chip_irq > 15)) 11549 return 0; 11550 return chip_irq; 11551 } 11552 11553 static int advansys_eisa_probe(struct device *dev) 11554 { 11555 int i, ioport, irq = 0; 11556 int err; 11557 struct eisa_device *edev = to_eisa_device(dev); 11558 struct eisa_scsi_data *data; 11559 11560 err = -ENOMEM; 11561 data = kzalloc(sizeof(*data), GFP_KERNEL); 11562 if (!data) 11563 goto fail; 11564 ioport = edev->base_addr + 0xc30; 11565 11566 err = -ENODEV; 11567 for (i = 0; i < 2; i++, ioport += 0x20) { 11568 struct asc_board *board; 11569 struct Scsi_Host *shost; 11570 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) { 11571 printk(KERN_WARNING "Region %x-%x busy\n", ioport, 11572 ioport + ASC_IOADR_GAP - 1); 11573 continue; 11574 } 11575 if (!AscFindSignature(ioport)) { 11576 release_region(ioport, ASC_IOADR_GAP); 11577 continue; 11578 } 11579 11580 /* 11581 * I don't know why we need to do this for EISA chips, but 11582 * not for any others. It looks to be equivalent to 11583 * AscGetChipCfgMsw, but I may have overlooked something, 11584 * so I'm not converting it until I get an EISA board to 11585 * test with. 11586 */ 11587 inw(ioport + 4); 11588 11589 if (!irq) 11590 irq = advansys_eisa_irq_no(edev); 11591 11592 err = -ENOMEM; 11593 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11594 if (!shost) 11595 goto release_region; 11596 11597 board = shost_priv(shost); 11598 board->irq = irq; 11599 board->dev = dev; 11600 board->shost = shost; 11601 11602 err = advansys_board_found(shost, ioport, ASC_IS_EISA); 11603 if (!err) { 11604 data->host[i] = shost; 11605 continue; 11606 } 11607 11608 scsi_host_put(shost); 11609 release_region: 11610 release_region(ioport, ASC_IOADR_GAP); 11611 break; 11612 } 11613 11614 if (err) 11615 goto free_data; 11616 dev_set_drvdata(dev, data); 11617 return 0; 11618 11619 free_data: 11620 kfree(data->host[0]); 11621 kfree(data->host[1]); 11622 kfree(data); 11623 fail: 11624 return err; 11625 } 11626 11627 static int advansys_eisa_remove(struct device *dev) 11628 { 11629 int i; 11630 struct eisa_scsi_data *data = dev_get_drvdata(dev); 11631 11632 for (i = 0; i < 2; i++) { 11633 int ioport; 11634 struct Scsi_Host *shost = data->host[i]; 11635 if (!shost) 11636 continue; 11637 ioport = shost->io_port; 11638 advansys_release(shost); 11639 release_region(ioport, ASC_IOADR_GAP); 11640 } 11641 11642 kfree(data); 11643 return 0; 11644 } 11645 11646 static struct eisa_driver advansys_eisa_driver = { 11647 .id_table = advansys_eisa_table, 11648 .driver = { 11649 .name = DRV_NAME, 11650 .probe = advansys_eisa_probe, 11651 .remove = advansys_eisa_remove, 11652 } 11653 }; 11654 11655 /* PCI Devices supported by this driver */ 11656 static struct pci_device_id advansys_pci_tbl[] = { 11657 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A, 11658 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11659 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940, 11660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11661 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U, 11662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11663 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW, 11664 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11665 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1, 11666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11667 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1, 11668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11669 {} 11670 }; 11671 11672 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl); 11673 11674 static void advansys_set_latency(struct pci_dev *pdev) 11675 { 11676 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || 11677 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { 11678 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0); 11679 } else { 11680 u8 latency; 11681 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency); 11682 if (latency < 0x20) 11683 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20); 11684 } 11685 } 11686 11687 static int advansys_pci_probe(struct pci_dev *pdev, 11688 const struct pci_device_id *ent) 11689 { 11690 int err, ioport; 11691 struct Scsi_Host *shost; 11692 struct asc_board *board; 11693 11694 err = pci_enable_device(pdev); 11695 if (err) 11696 goto fail; 11697 err = pci_request_regions(pdev, DRV_NAME); 11698 if (err) 11699 goto disable_device; 11700 pci_set_master(pdev); 11701 advansys_set_latency(pdev); 11702 11703 err = -ENODEV; 11704 if (pci_resource_len(pdev, 0) == 0) 11705 goto release_region; 11706 11707 ioport = pci_resource_start(pdev, 0); 11708 11709 err = -ENOMEM; 11710 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11711 if (!shost) 11712 goto release_region; 11713 11714 board = shost_priv(shost); 11715 board->irq = pdev->irq; 11716 board->dev = &pdev->dev; 11717 board->shost = shost; 11718 11719 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW || 11720 pdev->device == PCI_DEVICE_ID_38C0800_REV1 || 11721 pdev->device == PCI_DEVICE_ID_38C1600_REV1) { 11722 board->flags |= ASC_IS_WIDE_BOARD; 11723 } 11724 11725 err = advansys_board_found(shost, ioport, ASC_IS_PCI); 11726 if (err) 11727 goto free_host; 11728 11729 pci_set_drvdata(pdev, shost); 11730 return 0; 11731 11732 free_host: 11733 scsi_host_put(shost); 11734 release_region: 11735 pci_release_regions(pdev); 11736 disable_device: 11737 pci_disable_device(pdev); 11738 fail: 11739 return err; 11740 } 11741 11742 static void advansys_pci_remove(struct pci_dev *pdev) 11743 { 11744 advansys_release(pci_get_drvdata(pdev)); 11745 pci_release_regions(pdev); 11746 pci_disable_device(pdev); 11747 } 11748 11749 static struct pci_driver advansys_pci_driver = { 11750 .name = DRV_NAME, 11751 .id_table = advansys_pci_tbl, 11752 .probe = advansys_pci_probe, 11753 .remove = advansys_pci_remove, 11754 }; 11755 11756 static int __init advansys_init(void) 11757 { 11758 int error; 11759 11760 error = isa_register_driver(&advansys_isa_driver, 11761 ASC_IOADR_TABLE_MAX_IX); 11762 if (error) 11763 goto fail; 11764 11765 error = isa_register_driver(&advansys_vlb_driver, 11766 ASC_IOADR_TABLE_MAX_IX); 11767 if (error) 11768 goto unregister_isa; 11769 11770 error = eisa_driver_register(&advansys_eisa_driver); 11771 if (error) 11772 goto unregister_vlb; 11773 11774 error = pci_register_driver(&advansys_pci_driver); 11775 if (error) 11776 goto unregister_eisa; 11777 11778 return 0; 11779 11780 unregister_eisa: 11781 eisa_driver_unregister(&advansys_eisa_driver); 11782 unregister_vlb: 11783 isa_unregister_driver(&advansys_vlb_driver); 11784 unregister_isa: 11785 isa_unregister_driver(&advansys_isa_driver); 11786 fail: 11787 return error; 11788 } 11789 11790 static void __exit advansys_exit(void) 11791 { 11792 pci_unregister_driver(&advansys_pci_driver); 11793 eisa_driver_unregister(&advansys_eisa_driver); 11794 isa_unregister_driver(&advansys_vlb_driver); 11795 isa_unregister_driver(&advansys_isa_driver); 11796 } 11797 11798 module_init(advansys_init); 11799 module_exit(advansys_exit); 11800 11801 MODULE_LICENSE("GPL"); 11802 MODULE_FIRMWARE("advansys/mcode.bin"); 11803 MODULE_FIRMWARE("advansys/3550.bin"); 11804 MODULE_FIRMWARE("advansys/38C0800.bin"); 11805 MODULE_FIRMWARE("advansys/38C1600.bin"); 11806