1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 4 * 5 * Copyright (c) 1995-2000 Advanced System Products, Inc. 6 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc. 7 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx> 8 * Copyright (c) 2014 Hannes Reinecke <hare@suse.de> 9 * All Rights Reserved. 10 */ 11 12 /* 13 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys) 14 * changed its name to ConnectCom Solutions, Inc. 15 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets 16 */ 17 18 #include <linux/module.h> 19 #include <linux/string.h> 20 #include <linux/kernel.h> 21 #include <linux/types.h> 22 #include <linux/ioport.h> 23 #include <linux/interrupt.h> 24 #include <linux/delay.h> 25 #include <linux/slab.h> 26 #include <linux/mm.h> 27 #include <linux/proc_fs.h> 28 #include <linux/init.h> 29 #include <linux/blkdev.h> 30 #include <linux/isa.h> 31 #include <linux/eisa.h> 32 #include <linux/pci.h> 33 #include <linux/spinlock.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/firmware.h> 36 #include <linux/dmapool.h> 37 38 #include <asm/io.h> 39 #include <asm/dma.h> 40 41 #include <scsi/scsi_cmnd.h> 42 #include <scsi/scsi_device.h> 43 #include <scsi/scsi_tcq.h> 44 #include <scsi/scsi.h> 45 #include <scsi/scsi_host.h> 46 47 #define DRV_NAME "advansys" 48 #define ASC_VERSION "3.5" /* AdvanSys Driver Version */ 49 50 /* FIXME: 51 * 52 * 1. Use scsi_transport_spi 53 * 2. advansys_info is not safe against multiple simultaneous callers 54 * 3. Add module_param to override ISA/VLB ioport array 55 */ 56 57 /* Enable driver /proc statistics. */ 58 #define ADVANSYS_STATS 59 60 /* Enable driver tracing. */ 61 #undef ADVANSYS_DEBUG 62 63 typedef unsigned char uchar; 64 65 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0) 66 67 #define PCI_VENDOR_ID_ASP 0x10cd 68 #define PCI_DEVICE_ID_ASP_1200A 0x1100 69 #define PCI_DEVICE_ID_ASP_ABP940 0x1200 70 #define PCI_DEVICE_ID_ASP_ABP940U 0x1300 71 #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 72 #define PCI_DEVICE_ID_38C0800_REV1 0x2500 73 #define PCI_DEVICE_ID_38C1600_REV1 0x2700 74 75 #define PortAddr unsigned int /* port address size */ 76 #define inp(port) inb(port) 77 #define outp(port, byte) outb((byte), (port)) 78 79 #define inpw(port) inw(port) 80 #define outpw(port, word) outw((word), (port)) 81 82 #define ASC_MAX_SG_QUEUE 7 83 #define ASC_MAX_SG_LIST 255 84 85 #define ASC_CS_TYPE unsigned short 86 87 #define ASC_IS_EISA (0x0002) 88 #define ASC_IS_PCI (0x0004) 89 #define ASC_IS_PCI_ULTRA (0x0104) 90 #define ASC_IS_PCMCIA (0x0008) 91 #define ASC_IS_MCA (0x0020) 92 #define ASC_IS_VL (0x0040) 93 #define ASC_IS_WIDESCSI_16 (0x0100) 94 #define ASC_IS_WIDESCSI_32 (0x0200) 95 #define ASC_IS_BIG_ENDIAN (0x8000) 96 97 #define ASC_CHIP_MIN_VER_VL (0x01) 98 #define ASC_CHIP_MAX_VER_VL (0x07) 99 #define ASC_CHIP_MIN_VER_PCI (0x09) 100 #define ASC_CHIP_MAX_VER_PCI (0x0F) 101 #define ASC_CHIP_VER_PCI_BIT (0x08) 102 #define ASC_CHIP_VER_ASYN_BUG (0x21) 103 #define ASC_CHIP_VER_PCI 0x08 104 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02) 105 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03) 106 #define ASC_CHIP_MIN_VER_EISA (0x41) 107 #define ASC_CHIP_MAX_VER_EISA (0x47) 108 #define ASC_CHIP_VER_EISA_BIT (0x40) 109 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3) 110 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL) 111 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL) 112 113 #define ASC_SCSI_ID_BITS 3 114 #define ASC_SCSI_TIX_TYPE uchar 115 #define ASC_ALL_DEVICE_BIT_SET 0xFF 116 #define ASC_SCSI_BIT_ID_TYPE uchar 117 #define ASC_MAX_TID 7 118 #define ASC_MAX_LUN 7 119 #define ASC_SCSI_WIDTH_BIT_SET 0xFF 120 #define ASC_MAX_SENSE_LEN 32 121 #define ASC_MIN_SENSE_LEN 14 122 #define ASC_SCSI_RESET_HOLD_TIME_US 60 123 124 /* 125 * Narrow boards only support 12-byte commands, while wide boards 126 * extend to 16-byte commands. 127 */ 128 #define ASC_MAX_CDB_LEN 12 129 #define ADV_MAX_CDB_LEN 16 130 131 #define MS_SDTR_LEN 0x03 132 #define MS_WDTR_LEN 0x02 133 134 #define ASC_SG_LIST_PER_Q 7 135 #define QS_FREE 0x00 136 #define QS_READY 0x01 137 #define QS_DISC1 0x02 138 #define QS_DISC2 0x04 139 #define QS_BUSY 0x08 140 #define QS_ABORTED 0x40 141 #define QS_DONE 0x80 142 #define QC_NO_CALLBACK 0x01 143 #define QC_SG_SWAP_QUEUE 0x02 144 #define QC_SG_HEAD 0x04 145 #define QC_DATA_IN 0x08 146 #define QC_DATA_OUT 0x10 147 #define QC_URGENT 0x20 148 #define QC_MSG_OUT 0x40 149 #define QC_REQ_SENSE 0x80 150 #define QCSG_SG_XFER_LIST 0x02 151 #define QCSG_SG_XFER_MORE 0x04 152 #define QCSG_SG_XFER_END 0x08 153 #define QD_IN_PROGRESS 0x00 154 #define QD_NO_ERROR 0x01 155 #define QD_ABORTED_BY_HOST 0x02 156 #define QD_WITH_ERROR 0x04 157 #define QD_INVALID_REQUEST 0x80 158 #define QD_INVALID_HOST_NUM 0x81 159 #define QD_INVALID_DEVICE 0x82 160 #define QD_ERR_INTERNAL 0xFF 161 #define QHSTA_NO_ERROR 0x00 162 #define QHSTA_M_SEL_TIMEOUT 0x11 163 #define QHSTA_M_DATA_OVER_RUN 0x12 164 #define QHSTA_M_DATA_UNDER_RUN 0x12 165 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 166 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 167 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 168 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 169 #define QHSTA_D_HOST_ABORT_FAILED 0x23 170 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24 171 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 172 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26 173 #define QHSTA_M_WTM_TIMEOUT 0x41 174 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 175 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 176 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 177 #define QHSTA_M_TARGET_STATUS_BUSY 0x45 178 #define QHSTA_M_BAD_TAG_CODE 0x46 179 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 180 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 181 #define QHSTA_D_LRAM_CMP_ERROR 0x81 182 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 183 #define ASC_FLAG_SCSIQ_REQ 0x01 184 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02 185 #define ASC_FLAG_BIOS_ASYNC_IO 0x04 186 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08 187 #define ASC_FLAG_WIN16 0x10 188 #define ASC_FLAG_WIN32 0x20 189 #define ASC_FLAG_DOS_VM_CALLBACK 0x80 190 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10 191 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04 192 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 193 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 194 #define ASC_SCSIQ_CPY_BEG 4 195 #define ASC_SCSIQ_SGHD_CPY_BEG 2 196 #define ASC_SCSIQ_B_FWD 0 197 #define ASC_SCSIQ_B_BWD 1 198 #define ASC_SCSIQ_B_STATUS 2 199 #define ASC_SCSIQ_B_QNO 3 200 #define ASC_SCSIQ_B_CNTL 4 201 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5 202 #define ASC_SCSIQ_D_DATA_ADDR 8 203 #define ASC_SCSIQ_D_DATA_CNT 12 204 #define ASC_SCSIQ_B_SENSE_LEN 20 205 #define ASC_SCSIQ_DONE_INFO_BEG 22 206 #define ASC_SCSIQ_D_SRBPTR 22 207 #define ASC_SCSIQ_B_TARGET_IX 26 208 #define ASC_SCSIQ_B_CDB_LEN 28 209 #define ASC_SCSIQ_B_TAG_CODE 29 210 #define ASC_SCSIQ_W_VM_ID 30 211 #define ASC_SCSIQ_DONE_STATUS 32 212 #define ASC_SCSIQ_HOST_STATUS 33 213 #define ASC_SCSIQ_SCSI_STATUS 34 214 #define ASC_SCSIQ_CDB_BEG 36 215 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56 216 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60 217 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48 218 #define ASC_SCSIQ_B_SG_WK_QP 49 219 #define ASC_SCSIQ_B_SG_WK_IX 50 220 #define ASC_SCSIQ_W_ALT_DC1 52 221 #define ASC_SCSIQ_B_LIST_CNT 6 222 #define ASC_SCSIQ_B_CUR_LIST_CNT 7 223 #define ASC_SGQ_B_SG_CNTL 4 224 #define ASC_SGQ_B_SG_HEAD_QP 5 225 #define ASC_SGQ_B_SG_LIST_CNT 6 226 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7 227 #define ASC_SGQ_LIST_BEG 8 228 #define ASC_DEF_SCSI1_QNG 4 229 #define ASC_MAX_SCSI1_QNG 4 230 #define ASC_DEF_SCSI2_QNG 16 231 #define ASC_MAX_SCSI2_QNG 32 232 #define ASC_TAG_CODE_MASK 0x23 233 #define ASC_STOP_REQ_RISC_STOP 0x01 234 #define ASC_STOP_ACK_RISC_STOP 0x03 235 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10 236 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20 237 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40 238 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS)) 239 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid)) 240 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID)) 241 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID) 242 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID) 243 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN) 244 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6)) 245 246 typedef struct asc_scsiq_1 { 247 uchar status; 248 uchar q_no; 249 uchar cntl; 250 uchar sg_queue_cnt; 251 uchar target_id; 252 uchar target_lun; 253 __le32 data_addr; 254 __le32 data_cnt; 255 __le32 sense_addr; 256 uchar sense_len; 257 uchar extra_bytes; 258 } ASC_SCSIQ_1; 259 260 typedef struct asc_scsiq_2 { 261 u32 srb_tag; 262 uchar target_ix; 263 uchar flag; 264 uchar cdb_len; 265 uchar tag_code; 266 ushort vm_id; 267 } ASC_SCSIQ_2; 268 269 typedef struct asc_scsiq_3 { 270 uchar done_stat; 271 uchar host_stat; 272 uchar scsi_stat; 273 uchar scsi_msg; 274 } ASC_SCSIQ_3; 275 276 typedef struct asc_scsiq_4 { 277 uchar cdb[ASC_MAX_CDB_LEN]; 278 uchar y_first_sg_list_qp; 279 uchar y_working_sg_qp; 280 uchar y_working_sg_ix; 281 uchar y_res; 282 ushort x_req_count; 283 ushort x_reconnect_rtn; 284 __le32 x_saved_data_addr; 285 __le32 x_saved_data_cnt; 286 } ASC_SCSIQ_4; 287 288 typedef struct asc_q_done_info { 289 ASC_SCSIQ_2 d2; 290 ASC_SCSIQ_3 d3; 291 uchar q_status; 292 uchar q_no; 293 uchar cntl; 294 uchar sense_len; 295 uchar extra_bytes; 296 uchar res; 297 u32 remain_bytes; 298 } ASC_QDONE_INFO; 299 300 typedef struct asc_sg_list { 301 __le32 addr; 302 __le32 bytes; 303 } ASC_SG_LIST; 304 305 typedef struct asc_sg_head { 306 ushort entry_cnt; 307 ushort queue_cnt; 308 ushort entry_to_copy; 309 ushort res; 310 ASC_SG_LIST sg_list[]; 311 } ASC_SG_HEAD; 312 313 typedef struct asc_scsi_q { 314 ASC_SCSIQ_1 q1; 315 ASC_SCSIQ_2 q2; 316 uchar *cdbptr; 317 ASC_SG_HEAD *sg_head; 318 ushort remain_sg_entry_cnt; 319 ushort next_sg_index; 320 } ASC_SCSI_Q; 321 322 typedef struct asc_scsi_bios_req_q { 323 ASC_SCSIQ_1 r1; 324 ASC_SCSIQ_2 r2; 325 uchar *cdbptr; 326 ASC_SG_HEAD *sg_head; 327 uchar *sense_ptr; 328 ASC_SCSIQ_3 r3; 329 uchar cdb[ASC_MAX_CDB_LEN]; 330 uchar sense[ASC_MIN_SENSE_LEN]; 331 } ASC_SCSI_BIOS_REQ_Q; 332 333 typedef struct asc_risc_q { 334 uchar fwd; 335 uchar bwd; 336 ASC_SCSIQ_1 i1; 337 ASC_SCSIQ_2 i2; 338 ASC_SCSIQ_3 i3; 339 ASC_SCSIQ_4 i4; 340 } ASC_RISC_Q; 341 342 typedef struct asc_sg_list_q { 343 uchar seq_no; 344 uchar q_no; 345 uchar cntl; 346 uchar sg_head_qp; 347 uchar sg_list_cnt; 348 uchar sg_cur_list_cnt; 349 } ASC_SG_LIST_Q; 350 351 typedef struct asc_risc_sg_list_q { 352 uchar fwd; 353 uchar bwd; 354 ASC_SG_LIST_Q sg; 355 ASC_SG_LIST sg_list[7]; 356 } ASC_RISC_SG_LIST_Q; 357 358 #define ASCQ_ERR_Q_STATUS 0x0D 359 #define ASCQ_ERR_CUR_QNG 0x17 360 #define ASCQ_ERR_SG_Q_LINKS 0x18 361 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A 362 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B 363 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C 364 365 /* 366 * Warning code values are set in ASC_DVC_VAR 'warn_code'. 367 */ 368 #define ASC_WARN_NO_ERROR 0x0000 369 #define ASC_WARN_IO_PORT_ROTATE 0x0001 370 #define ASC_WARN_EEPROM_CHKSUM 0x0002 371 #define ASC_WARN_IRQ_MODIFIED 0x0004 372 #define ASC_WARN_AUTO_CONFIG 0x0008 373 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010 374 #define ASC_WARN_EEPROM_RECOVER 0x0020 375 #define ASC_WARN_CFG_MSW_RECOVER 0x0040 376 377 /* 378 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'. 379 */ 380 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */ 381 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 382 #define ASC_IERR_SET_PC_ADDR 0x0004 383 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 384 #define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */ 385 #define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */ 386 #define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */ 387 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 388 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */ 389 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 390 #define ASC_IERR_NO_BUS_TYPE 0x0400 391 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */ 392 #define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */ 393 #define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */ 394 395 #define ASC_DEF_MAX_TOTAL_QNG (0xF0) 396 #define ASC_MIN_TAG_Q_PER_DVC (0x04) 397 #define ASC_MIN_FREE_Q (0x02) 398 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q)) 399 #define ASC_MAX_TOTAL_QNG 240 400 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 401 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 402 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20 403 #define ASC_MAX_INRAM_TAG_QNG 16 404 #define ASC_IOADR_GAP 0x10 405 #define ASC_SYN_MAX_OFFSET 0x0F 406 #define ASC_DEF_SDTR_OFFSET 0x0F 407 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02 408 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41 409 410 /* The narrow chip only supports a limited selection of transfer rates. 411 * These are encoded in the range 0..7 or 0..15 depending whether the chip 412 * is Ultra-capable or not. These tables let us convert from one to the other. 413 */ 414 static const unsigned char asc_syn_xfer_period[8] = { 415 25, 30, 35, 40, 50, 60, 70, 85 416 }; 417 418 static const unsigned char asc_syn_ultra_xfer_period[16] = { 419 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107 420 }; 421 422 typedef struct ext_msg { 423 uchar msg_type; 424 uchar msg_len; 425 uchar msg_req; 426 union { 427 struct { 428 uchar sdtr_xfer_period; 429 uchar sdtr_req_ack_offset; 430 } sdtr; 431 struct { 432 uchar wdtr_width; 433 } wdtr; 434 struct { 435 uchar mdp_b3; 436 uchar mdp_b2; 437 uchar mdp_b1; 438 uchar mdp_b0; 439 } mdp; 440 } u_ext_msg; 441 uchar res; 442 } EXT_MSG; 443 444 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period 445 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset 446 #define wdtr_width u_ext_msg.wdtr.wdtr_width 447 #define mdp_b3 u_ext_msg.mdp_b3 448 #define mdp_b2 u_ext_msg.mdp_b2 449 #define mdp_b1 u_ext_msg.mdp_b1 450 #define mdp_b0 u_ext_msg.mdp_b0 451 452 typedef struct asc_dvc_cfg { 453 ASC_SCSI_BIT_ID_TYPE can_tagged_qng; 454 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled; 455 ASC_SCSI_BIT_ID_TYPE disc_enable; 456 ASC_SCSI_BIT_ID_TYPE sdtr_enable; 457 uchar chip_scsi_id; 458 uchar chip_version; 459 ushort mcode_date; 460 ushort mcode_version; 461 uchar max_tag_qng[ASC_MAX_TID + 1]; 462 uchar sdtr_period_offset[ASC_MAX_TID + 1]; 463 uchar adapter_info[6]; 464 } ASC_DVC_CFG; 465 466 #define ASC_DEF_DVC_CNTL 0xFFFF 467 #define ASC_DEF_CHIP_SCSI_ID 7 468 #define ASC_DEF_ISA_DMA_SPEED 4 469 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001 470 #define ASC_INIT_STATE_END_GET_CFG 0x0002 471 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004 472 #define ASC_INIT_STATE_END_SET_CFG 0x0008 473 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010 474 #define ASC_INIT_STATE_END_LOAD_MC 0x0020 475 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040 476 #define ASC_INIT_STATE_END_INQUIRY 0x0080 477 #define ASC_INIT_RESET_SCSI_DONE 0x0100 478 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000 479 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001 480 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002 481 #define ASC_MIN_TAGGED_CMD 7 482 #define ASC_MAX_SCSI_RESET_WAIT 30 483 #define ASC_OVERRUN_BSIZE 64 484 485 struct asc_dvc_var; /* Forward Declaration. */ 486 487 typedef struct asc_dvc_var { 488 PortAddr iop_base; 489 ushort err_code; 490 ushort dvc_cntl; 491 ushort bug_fix_cntl; 492 ushort bus_type; 493 ASC_SCSI_BIT_ID_TYPE init_sdtr; 494 ASC_SCSI_BIT_ID_TYPE sdtr_done; 495 ASC_SCSI_BIT_ID_TYPE use_tagged_qng; 496 ASC_SCSI_BIT_ID_TYPE unit_not_ready; 497 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy; 498 ASC_SCSI_BIT_ID_TYPE start_motor; 499 uchar *overrun_buf; 500 dma_addr_t overrun_dma; 501 uchar scsi_reset_wait; 502 uchar chip_no; 503 bool is_in_int; 504 uchar max_total_qng; 505 uchar cur_total_qng; 506 uchar in_critical_cnt; 507 uchar last_q_shortage; 508 ushort init_state; 509 uchar cur_dvc_qng[ASC_MAX_TID + 1]; 510 uchar max_dvc_qng[ASC_MAX_TID + 1]; 511 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1]; 512 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1]; 513 const uchar *sdtr_period_tbl; 514 ASC_DVC_CFG *cfg; 515 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always; 516 char redo_scam; 517 ushort res2; 518 uchar dos_int13_table[ASC_MAX_TID + 1]; 519 unsigned int max_dma_count; 520 ASC_SCSI_BIT_ID_TYPE no_scam; 521 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer; 522 uchar min_sdtr_index; 523 uchar max_sdtr_index; 524 struct asc_board *drv_ptr; 525 unsigned int uc_break; 526 } ASC_DVC_VAR; 527 528 typedef struct asc_dvc_inq_info { 529 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; 530 } ASC_DVC_INQ_INFO; 531 532 typedef struct asc_cap_info { 533 u32 lba; 534 u32 blk_size; 535 } ASC_CAP_INFO; 536 537 typedef struct asc_cap_info_array { 538 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; 539 } ASC_CAP_INFO_ARRAY; 540 541 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001 542 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002 543 #define ASC_CNTL_INITIATOR (ushort)0x0001 544 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002 545 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004 546 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008 547 #define ASC_CNTL_NO_SCAM (ushort)0x0010 548 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080 549 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040 550 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100 551 #define ASC_CNTL_RESET_SCSI (ushort)0x0200 552 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400 553 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800 554 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000 555 #define ASC_CNTL_BURST_MODE (ushort)0x2000 556 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000 557 #define ASC_EEP_DVC_CFG_BEG_VL 2 558 #define ASC_EEP_MAX_DVC_ADDR_VL 15 559 #define ASC_EEP_DVC_CFG_BEG 32 560 #define ASC_EEP_MAX_DVC_ADDR 45 561 #define ASC_EEP_MAX_RETRY 20 562 563 /* 564 * These macros keep the chip SCSI id bitfields in board order. C bitfields 565 * aren't portable between big and little-endian platforms so they are not used. 566 */ 567 568 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f) 569 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4) 570 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \ 571 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID)) 572 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \ 573 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4) 574 575 typedef struct asceep_config { 576 ushort cfg_lsw; 577 ushort cfg_msw; 578 uchar init_sdtr; 579 uchar disc_enable; 580 uchar use_cmd_qng; 581 uchar start_motor; 582 uchar max_total_qng; 583 uchar max_tag_qng; 584 uchar bios_scan; 585 uchar power_up_wait; 586 uchar no_scam; 587 uchar id_speed; /* low order 4 bits is chip scsi id */ 588 /* high order 4 bits is isa dma speed */ 589 uchar dos_int13_table[ASC_MAX_TID + 1]; 590 uchar adapter_info[6]; 591 ushort cntl; 592 ushort chksum; 593 } ASCEEP_CONFIG; 594 595 #define ASC_EEP_CMD_READ 0x80 596 #define ASC_EEP_CMD_WRITE 0x40 597 #define ASC_EEP_CMD_WRITE_ABLE 0x30 598 #define ASC_EEP_CMD_WRITE_DISABLE 0x00 599 #define ASCV_MSGOUT_BEG 0x0000 600 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3) 601 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4) 602 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006 603 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8) 604 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3) 605 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4) 606 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8) 607 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8) 608 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020 609 #define ASCV_BREAK_ADDR (ushort)0x0028 610 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A 611 #define ASCV_BREAK_CONTROL (ushort)0x002C 612 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E 613 614 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030 615 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032 616 #define ASCV_MCODE_SIZE_W (ushort)0x0034 617 #define ASCV_STOP_CODE_B (ushort)0x0036 618 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037 619 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038 620 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C 621 #define ASCV_HALTCODE_W (ushort)0x0040 622 #define ASCV_CHKSUM_W (ushort)0x0042 623 #define ASCV_MC_DATE_W (ushort)0x0044 624 #define ASCV_MC_VER_W (ushort)0x0046 625 #define ASCV_NEXTRDY_B (ushort)0x0048 626 #define ASCV_DONENEXT_B (ushort)0x0049 627 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A 628 #define ASCV_SCSIBUSY_B (ushort)0x004B 629 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C 630 #define ASCV_CURCDB_B (ushort)0x004D 631 #define ASCV_RCLUN_B (ushort)0x004E 632 #define ASCV_BUSY_QHEAD_B (ushort)0x004F 633 #define ASCV_DISC1_QHEAD_B (ushort)0x0050 634 #define ASCV_DISC_ENABLE_B (ushort)0x0052 635 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053 636 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055 637 #define ASCV_MCODE_CNTL_B (ushort)0x0056 638 #define ASCV_NULL_TARGET_B (ushort)0x0057 639 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058 640 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A 641 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1) 642 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1) 643 #define ASCV_HOST_FLAG_B (ushort)0x005D 644 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064 645 #define ASCV_VER_SERIAL_B (ushort)0x0065 646 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066 647 #define ASCV_WTM_FLAG_B (ushort)0x0068 648 #define ASCV_RISC_FLAG_B (ushort)0x006A 649 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B 650 #define ASC_HOST_FLAG_IN_ISR 0x01 651 #define ASC_HOST_FLAG_ACK_INT 0x02 652 #define ASC_RISC_FLAG_GEN_INT 0x01 653 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02 654 #define IOP_CTRL (0x0F) 655 #define IOP_STATUS (0x0E) 656 #define IOP_INT_ACK IOP_STATUS 657 #define IOP_REG_IFC (0x0D) 658 #define IOP_SYN_OFFSET (0x0B) 659 #define IOP_EXTRA_CONTROL (0x0D) 660 #define IOP_REG_PC (0x0C) 661 #define IOP_RAM_ADDR (0x0A) 662 #define IOP_RAM_DATA (0x08) 663 #define IOP_EEP_DATA (0x06) 664 #define IOP_EEP_CMD (0x07) 665 #define IOP_VERSION (0x03) 666 #define IOP_CONFIG_HIGH (0x04) 667 #define IOP_CONFIG_LOW (0x02) 668 #define IOP_SIG_BYTE (0x01) 669 #define IOP_SIG_WORD (0x00) 670 #define IOP_REG_DC1 (0x0E) 671 #define IOP_REG_DC0 (0x0C) 672 #define IOP_REG_SB (0x0B) 673 #define IOP_REG_DA1 (0x0A) 674 #define IOP_REG_DA0 (0x08) 675 #define IOP_REG_SC (0x09) 676 #define IOP_DMA_SPEED (0x07) 677 #define IOP_REG_FLAG (0x07) 678 #define IOP_FIFO_H (0x06) 679 #define IOP_FIFO_L (0x04) 680 #define IOP_REG_ID (0x05) 681 #define IOP_REG_QP (0x03) 682 #define IOP_REG_IH (0x02) 683 #define IOP_REG_IX (0x01) 684 #define IOP_REG_AX (0x00) 685 #define IFC_REG_LOCK (0x00) 686 #define IFC_REG_UNLOCK (0x09) 687 #define IFC_WR_EN_FILTER (0x10) 688 #define IFC_RD_NO_EEPROM (0x10) 689 #define IFC_SLEW_RATE (0x20) 690 #define IFC_ACT_NEG (0x40) 691 #define IFC_INP_FILTER (0x80) 692 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK) 693 #define SC_SEL (uchar)(0x80) 694 #define SC_BSY (uchar)(0x40) 695 #define SC_ACK (uchar)(0x20) 696 #define SC_REQ (uchar)(0x10) 697 #define SC_ATN (uchar)(0x08) 698 #define SC_IO (uchar)(0x04) 699 #define SC_CD (uchar)(0x02) 700 #define SC_MSG (uchar)(0x01) 701 #define SEC_SCSI_CTL (uchar)(0x80) 702 #define SEC_ACTIVE_NEGATE (uchar)(0x40) 703 #define SEC_SLEW_RATE (uchar)(0x20) 704 #define SEC_ENABLE_FILTER (uchar)(0x10) 705 #define ASC_HALT_EXTMSG_IN (ushort)0x8000 706 #define ASC_HALT_CHK_CONDITION (ushort)0x8100 707 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200 708 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300 709 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400 710 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000 711 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000 712 #define ASC_MAX_QNO 0xF8 713 #define ASC_DATA_SEC_BEG (ushort)0x0080 714 #define ASC_DATA_SEC_END (ushort)0x0080 715 #define ASC_CODE_SEC_BEG (ushort)0x0080 716 #define ASC_CODE_SEC_END (ushort)0x0080 717 #define ASC_QADR_BEG (0x4000) 718 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64) 719 #define ASC_QADR_END (ushort)0x7FFF 720 #define ASC_QLAST_ADR (ushort)0x7FC0 721 #define ASC_QBLK_SIZE 0x40 722 #define ASC_BIOS_DATA_QBEG 0xF8 723 #define ASC_MIN_ACTIVE_QNO 0x01 724 #define ASC_QLINK_END 0xFF 725 #define ASC_EEPROM_WORDS 0x10 726 #define ASC_MAX_MGS_LEN 0x10 727 #define ASC_BIOS_ADDR_DEF 0xDC00 728 #define ASC_BIOS_SIZE 0x3800 729 #define ASC_BIOS_RAM_OFF 0x3800 730 #define ASC_BIOS_RAM_SIZE 0x800 731 #define ASC_BIOS_MIN_ADDR 0xC000 732 #define ASC_BIOS_MAX_ADDR 0xEC00 733 #define ASC_BIOS_BANK_SIZE 0x0400 734 #define ASC_MCODE_START_ADDR 0x0080 735 #define ASC_CFG0_HOST_INT_ON 0x0020 736 #define ASC_CFG0_BIOS_ON 0x0040 737 #define ASC_CFG0_VERA_BURST_ON 0x0080 738 #define ASC_CFG0_SCSI_PARITY_ON 0x0800 739 #define ASC_CFG1_SCSI_TARGET_ON 0x0080 740 #define ASC_CFG1_LRAM_8BITS_ON 0x0800 741 #define ASC_CFG_MSW_CLR_MASK 0x3080 742 #define CSW_TEST1 (ASC_CS_TYPE)0x8000 743 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000 744 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000 745 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000 746 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800 747 #define CSW_TEST2 (ASC_CS_TYPE)0x0400 748 #define CSW_TEST3 (ASC_CS_TYPE)0x0200 749 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100 750 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080 751 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040 752 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020 753 #define CSW_HALTED (ASC_CS_TYPE)0x0010 754 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008 755 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004 756 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002 757 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001 758 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000 759 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100 760 #define CIW_TEST1 (ASC_CS_TYPE)0x0200 761 #define CIW_TEST2 (ASC_CS_TYPE)0x0400 762 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800 763 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000 764 #define CC_CHIP_RESET (uchar)0x80 765 #define CC_SCSI_RESET (uchar)0x40 766 #define CC_HALT (uchar)0x20 767 #define CC_SINGLE_STEP (uchar)0x10 768 #define CC_DMA_ABLE (uchar)0x08 769 #define CC_TEST (uchar)0x04 770 #define CC_BANK_ONE (uchar)0x02 771 #define CC_DIAG (uchar)0x01 772 #define ASC_1000_ID0W 0x04C1 773 #define ASC_1000_ID0W_FIX 0x00C1 774 #define ASC_1000_ID1B 0x25 775 #define ASC_EISA_REV_IOP_MASK (0x0C83) 776 #define ASC_EISA_CFG_IOP_MASK (0x0C86) 777 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000) 778 #define INS_HALTINT (ushort)0x6281 779 #define INS_HALT (ushort)0x6280 780 #define INS_SINT (ushort)0x6200 781 #define INS_RFLAG_WTM (ushort)0x7380 782 #define ASC_MC_SAVE_CODE_WSIZE 0x500 783 #define ASC_MC_SAVE_DATA_WSIZE 0x40 784 785 typedef struct asc_mc_saved { 786 ushort data[ASC_MC_SAVE_DATA_WSIZE]; 787 ushort code[ASC_MC_SAVE_CODE_WSIZE]; 788 } ASC_MC_SAVED; 789 790 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B) 791 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val) 792 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W) 793 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W) 794 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val) 795 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val) 796 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B) 797 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B) 798 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val) 799 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val) 800 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data)) 801 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id)) 802 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data) 803 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id)) 804 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE) 805 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD) 806 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION) 807 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW) 808 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH) 809 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data) 810 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data) 811 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD) 812 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data) 813 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA) 814 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data) 815 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR)) 816 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr) 817 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA) 818 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data) 819 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC) 820 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data) 821 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS) 822 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val) 823 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL) 824 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val) 825 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET) 826 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data) 827 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data) 828 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC) 829 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH)) 830 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID) 831 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL) 832 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data) 833 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX) 834 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data) 835 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX) 836 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data) 837 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH) 838 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data) 839 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP) 840 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data) 841 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L) 842 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data) 843 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H) 844 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data) 845 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED) 846 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data) 847 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0) 848 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data) 849 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1) 850 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data) 851 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0) 852 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data) 853 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1) 854 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data) 855 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID) 856 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data) 857 858 #define AdvPortAddr void __iomem * /* Virtual memory address size */ 859 860 /* 861 * Define Adv Library required memory access macros. 862 */ 863 #define ADV_MEM_READB(addr) readb(addr) 864 #define ADV_MEM_READW(addr) readw(addr) 865 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr) 866 #define ADV_MEM_WRITEW(addr, word) writew(word, addr) 867 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr) 868 869 /* 870 * Define total number of simultaneous maximum element scatter-gather 871 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the 872 * maximum number of outstanding commands per wide host adapter. Each 873 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather 874 * elements. Allow each command to have at least one ADV_SG_BLOCK structure. 875 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK 876 * structures or 255 scatter-gather elements. 877 */ 878 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG 879 880 /* 881 * Define maximum number of scatter-gather elements per request. 882 */ 883 #define ADV_MAX_SG_LIST 255 884 #define NO_OF_SG_PER_BLOCK 15 885 886 #define ADV_EEP_DVC_CFG_BEGIN (0x00) 887 #define ADV_EEP_DVC_CFG_END (0x15) 888 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 889 #define ADV_EEP_MAX_WORD_ADDR (0x1E) 890 891 #define ADV_EEP_DELAY_MS 100 892 893 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 894 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 895 /* 896 * For the ASC3550 Bit 13 is Termination Polarity control bit. 897 * For later ICs Bit 13 controls whether the CIS (Card Information 898 * Service Section) is loaded from EEPROM. 899 */ 900 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 901 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ 902 /* 903 * ASC38C1600 Bit 11 904 * 905 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify 906 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then 907 * Function 0 will specify INT B. 908 * 909 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify 910 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then 911 * Function 1 will specify INT A. 912 */ 913 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ 914 915 typedef struct adveep_3550_config { 916 /* Word Offset, Description */ 917 918 ushort cfg_lsw; /* 00 power up initialization */ 919 /* bit 13 set - Term Polarity Control */ 920 /* bit 14 set - BIOS Enable */ 921 /* bit 15 set - Big Endian Mode */ 922 ushort cfg_msw; /* 01 unused */ 923 ushort disc_enable; /* 02 disconnect enable */ 924 ushort wdtr_able; /* 03 Wide DTR able */ 925 ushort sdtr_able; /* 04 Synchronous DTR able */ 926 ushort start_motor; /* 05 send start up motor */ 927 ushort tagqng_able; /* 06 tag queuing able */ 928 ushort bios_scan; /* 07 BIOS device control */ 929 ushort scam_tolerant; /* 08 no scam */ 930 931 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 932 uchar bios_boot_delay; /* power up wait */ 933 934 uchar scsi_reset_delay; /* 10 reset delay */ 935 uchar bios_id_lun; /* first boot device scsi id & lun */ 936 /* high nibble is lun */ 937 /* low nibble is scsi id */ 938 939 uchar termination; /* 11 0 - automatic */ 940 /* 1 - low off / high off */ 941 /* 2 - low off / high on */ 942 /* 3 - low on / high on */ 943 /* There is no low on / high off */ 944 945 uchar reserved1; /* reserved byte (not used) */ 946 947 ushort bios_ctrl; /* 12 BIOS control bits */ 948 /* bit 0 BIOS don't act as initiator. */ 949 /* bit 1 BIOS > 1 GB support */ 950 /* bit 2 BIOS > 2 Disk Support */ 951 /* bit 3 BIOS don't support removables */ 952 /* bit 4 BIOS support bootable CD */ 953 /* bit 5 BIOS scan enabled */ 954 /* bit 6 BIOS support multiple LUNs */ 955 /* bit 7 BIOS display of message */ 956 /* bit 8 SCAM disabled */ 957 /* bit 9 Reset SCSI bus during init. */ 958 /* bit 10 */ 959 /* bit 11 No verbose initialization. */ 960 /* bit 12 SCSI parity enabled */ 961 /* bit 13 */ 962 /* bit 14 */ 963 /* bit 15 */ 964 ushort ultra_able; /* 13 ULTRA speed able */ 965 ushort reserved2; /* 14 reserved */ 966 uchar max_host_qng; /* 15 maximum host queuing */ 967 uchar max_dvc_qng; /* maximum per device queuing */ 968 ushort dvc_cntl; /* 16 control bit for driver */ 969 ushort bug_fix; /* 17 control bit for bug fix */ 970 ushort serial_number_word1; /* 18 Board serial number word 1 */ 971 ushort serial_number_word2; /* 19 Board serial number word 2 */ 972 ushort serial_number_word3; /* 20 Board serial number word 3 */ 973 ushort check_sum; /* 21 EEP check sum */ 974 uchar oem_name[16]; /* 22 OEM name */ 975 ushort dvc_err_code; /* 30 last device driver error code */ 976 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 977 ushort adv_err_addr; /* 32 last uc error address */ 978 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 979 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 980 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 981 ushort num_of_err; /* 36 number of error */ 982 } ADVEEP_3550_CONFIG; 983 984 typedef struct adveep_38C0800_config { 985 /* Word Offset, Description */ 986 987 ushort cfg_lsw; /* 00 power up initialization */ 988 /* bit 13 set - Load CIS */ 989 /* bit 14 set - BIOS Enable */ 990 /* bit 15 set - Big Endian Mode */ 991 ushort cfg_msw; /* 01 unused */ 992 ushort disc_enable; /* 02 disconnect enable */ 993 ushort wdtr_able; /* 03 Wide DTR able */ 994 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 995 ushort start_motor; /* 05 send start up motor */ 996 ushort tagqng_able; /* 06 tag queuing able */ 997 ushort bios_scan; /* 07 BIOS device control */ 998 ushort scam_tolerant; /* 08 no scam */ 999 1000 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 1001 uchar bios_boot_delay; /* power up wait */ 1002 1003 uchar scsi_reset_delay; /* 10 reset delay */ 1004 uchar bios_id_lun; /* first boot device scsi id & lun */ 1005 /* high nibble is lun */ 1006 /* low nibble is scsi id */ 1007 1008 uchar termination_se; /* 11 0 - automatic */ 1009 /* 1 - low off / high off */ 1010 /* 2 - low off / high on */ 1011 /* 3 - low on / high on */ 1012 /* There is no low on / high off */ 1013 1014 uchar termination_lvd; /* 11 0 - automatic */ 1015 /* 1 - low off / high off */ 1016 /* 2 - low off / high on */ 1017 /* 3 - low on / high on */ 1018 /* There is no low on / high off */ 1019 1020 ushort bios_ctrl; /* 12 BIOS control bits */ 1021 /* bit 0 BIOS don't act as initiator. */ 1022 /* bit 1 BIOS > 1 GB support */ 1023 /* bit 2 BIOS > 2 Disk Support */ 1024 /* bit 3 BIOS don't support removables */ 1025 /* bit 4 BIOS support bootable CD */ 1026 /* bit 5 BIOS scan enabled */ 1027 /* bit 6 BIOS support multiple LUNs */ 1028 /* bit 7 BIOS display of message */ 1029 /* bit 8 SCAM disabled */ 1030 /* bit 9 Reset SCSI bus during init. */ 1031 /* bit 10 */ 1032 /* bit 11 No verbose initialization. */ 1033 /* bit 12 SCSI parity enabled */ 1034 /* bit 13 */ 1035 /* bit 14 */ 1036 /* bit 15 */ 1037 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 1038 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 1039 uchar max_host_qng; /* 15 maximum host queueing */ 1040 uchar max_dvc_qng; /* maximum per device queuing */ 1041 ushort dvc_cntl; /* 16 control bit for driver */ 1042 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 1043 ushort serial_number_word1; /* 18 Board serial number word 1 */ 1044 ushort serial_number_word2; /* 19 Board serial number word 2 */ 1045 ushort serial_number_word3; /* 20 Board serial number word 3 */ 1046 ushort check_sum; /* 21 EEP check sum */ 1047 uchar oem_name[16]; /* 22 OEM name */ 1048 ushort dvc_err_code; /* 30 last device driver error code */ 1049 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 1050 ushort adv_err_addr; /* 32 last uc error address */ 1051 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 1052 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 1053 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 1054 ushort reserved36; /* 36 reserved */ 1055 ushort reserved37; /* 37 reserved */ 1056 ushort reserved38; /* 38 reserved */ 1057 ushort reserved39; /* 39 reserved */ 1058 ushort reserved40; /* 40 reserved */ 1059 ushort reserved41; /* 41 reserved */ 1060 ushort reserved42; /* 42 reserved */ 1061 ushort reserved43; /* 43 reserved */ 1062 ushort reserved44; /* 44 reserved */ 1063 ushort reserved45; /* 45 reserved */ 1064 ushort reserved46; /* 46 reserved */ 1065 ushort reserved47; /* 47 reserved */ 1066 ushort reserved48; /* 48 reserved */ 1067 ushort reserved49; /* 49 reserved */ 1068 ushort reserved50; /* 50 reserved */ 1069 ushort reserved51; /* 51 reserved */ 1070 ushort reserved52; /* 52 reserved */ 1071 ushort reserved53; /* 53 reserved */ 1072 ushort reserved54; /* 54 reserved */ 1073 ushort reserved55; /* 55 reserved */ 1074 ushort cisptr_lsw; /* 56 CIS PTR LSW */ 1075 ushort cisprt_msw; /* 57 CIS PTR MSW */ 1076 ushort subsysvid; /* 58 SubSystem Vendor ID */ 1077 ushort subsysid; /* 59 SubSystem ID */ 1078 ushort reserved60; /* 60 reserved */ 1079 ushort reserved61; /* 61 reserved */ 1080 ushort reserved62; /* 62 reserved */ 1081 ushort reserved63; /* 63 reserved */ 1082 } ADVEEP_38C0800_CONFIG; 1083 1084 typedef struct adveep_38C1600_config { 1085 /* Word Offset, Description */ 1086 1087 ushort cfg_lsw; /* 00 power up initialization */ 1088 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */ 1089 /* clear - Func. 0 INTA, Func. 1 INTB */ 1090 /* bit 13 set - Load CIS */ 1091 /* bit 14 set - BIOS Enable */ 1092 /* bit 15 set - Big Endian Mode */ 1093 ushort cfg_msw; /* 01 unused */ 1094 ushort disc_enable; /* 02 disconnect enable */ 1095 ushort wdtr_able; /* 03 Wide DTR able */ 1096 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 1097 ushort start_motor; /* 05 send start up motor */ 1098 ushort tagqng_able; /* 06 tag queuing able */ 1099 ushort bios_scan; /* 07 BIOS device control */ 1100 ushort scam_tolerant; /* 08 no scam */ 1101 1102 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 1103 uchar bios_boot_delay; /* power up wait */ 1104 1105 uchar scsi_reset_delay; /* 10 reset delay */ 1106 uchar bios_id_lun; /* first boot device scsi id & lun */ 1107 /* high nibble is lun */ 1108 /* low nibble is scsi id */ 1109 1110 uchar termination_se; /* 11 0 - automatic */ 1111 /* 1 - low off / high off */ 1112 /* 2 - low off / high on */ 1113 /* 3 - low on / high on */ 1114 /* There is no low on / high off */ 1115 1116 uchar termination_lvd; /* 11 0 - automatic */ 1117 /* 1 - low off / high off */ 1118 /* 2 - low off / high on */ 1119 /* 3 - low on / high on */ 1120 /* There is no low on / high off */ 1121 1122 ushort bios_ctrl; /* 12 BIOS control bits */ 1123 /* bit 0 BIOS don't act as initiator. */ 1124 /* bit 1 BIOS > 1 GB support */ 1125 /* bit 2 BIOS > 2 Disk Support */ 1126 /* bit 3 BIOS don't support removables */ 1127 /* bit 4 BIOS support bootable CD */ 1128 /* bit 5 BIOS scan enabled */ 1129 /* bit 6 BIOS support multiple LUNs */ 1130 /* bit 7 BIOS display of message */ 1131 /* bit 8 SCAM disabled */ 1132 /* bit 9 Reset SCSI bus during init. */ 1133 /* bit 10 Basic Integrity Checking disabled */ 1134 /* bit 11 No verbose initialization. */ 1135 /* bit 12 SCSI parity enabled */ 1136 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */ 1137 /* bit 14 */ 1138 /* bit 15 */ 1139 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 1140 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 1141 uchar max_host_qng; /* 15 maximum host queueing */ 1142 uchar max_dvc_qng; /* maximum per device queuing */ 1143 ushort dvc_cntl; /* 16 control bit for driver */ 1144 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 1145 ushort serial_number_word1; /* 18 Board serial number word 1 */ 1146 ushort serial_number_word2; /* 19 Board serial number word 2 */ 1147 ushort serial_number_word3; /* 20 Board serial number word 3 */ 1148 ushort check_sum; /* 21 EEP check sum */ 1149 uchar oem_name[16]; /* 22 OEM name */ 1150 ushort dvc_err_code; /* 30 last device driver error code */ 1151 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 1152 ushort adv_err_addr; /* 32 last uc error address */ 1153 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 1154 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 1155 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 1156 ushort reserved36; /* 36 reserved */ 1157 ushort reserved37; /* 37 reserved */ 1158 ushort reserved38; /* 38 reserved */ 1159 ushort reserved39; /* 39 reserved */ 1160 ushort reserved40; /* 40 reserved */ 1161 ushort reserved41; /* 41 reserved */ 1162 ushort reserved42; /* 42 reserved */ 1163 ushort reserved43; /* 43 reserved */ 1164 ushort reserved44; /* 44 reserved */ 1165 ushort reserved45; /* 45 reserved */ 1166 ushort reserved46; /* 46 reserved */ 1167 ushort reserved47; /* 47 reserved */ 1168 ushort reserved48; /* 48 reserved */ 1169 ushort reserved49; /* 49 reserved */ 1170 ushort reserved50; /* 50 reserved */ 1171 ushort reserved51; /* 51 reserved */ 1172 ushort reserved52; /* 52 reserved */ 1173 ushort reserved53; /* 53 reserved */ 1174 ushort reserved54; /* 54 reserved */ 1175 ushort reserved55; /* 55 reserved */ 1176 ushort cisptr_lsw; /* 56 CIS PTR LSW */ 1177 ushort cisprt_msw; /* 57 CIS PTR MSW */ 1178 ushort subsysvid; /* 58 SubSystem Vendor ID */ 1179 ushort subsysid; /* 59 SubSystem ID */ 1180 ushort reserved60; /* 60 reserved */ 1181 ushort reserved61; /* 61 reserved */ 1182 ushort reserved62; /* 62 reserved */ 1183 ushort reserved63; /* 63 reserved */ 1184 } ADVEEP_38C1600_CONFIG; 1185 1186 /* 1187 * EEPROM Commands 1188 */ 1189 #define ASC_EEP_CMD_DONE 0x0200 1190 1191 /* bios_ctrl */ 1192 #define BIOS_CTRL_BIOS 0x0001 1193 #define BIOS_CTRL_EXTENDED_XLAT 0x0002 1194 #define BIOS_CTRL_GT_2_DISK 0x0004 1195 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008 1196 #define BIOS_CTRL_BOOTABLE_CD 0x0010 1197 #define BIOS_CTRL_MULTIPLE_LUN 0x0040 1198 #define BIOS_CTRL_DISPLAY_MSG 0x0080 1199 #define BIOS_CTRL_NO_SCAM 0x0100 1200 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 1201 #define BIOS_CTRL_INIT_VERBOSE 0x0800 1202 #define BIOS_CTRL_SCSI_PARITY 0x1000 1203 #define BIOS_CTRL_AIPP_DIS 0x2000 1204 1205 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 1206 1207 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 1208 1209 /* 1210 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is 1211 * a special 16K Adv Library and Microcode version. After the issue is 1212 * resolved, should restore 32K support. 1213 * 1214 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory * 1215 */ 1216 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 1217 1218 /* 1219 * Byte I/O register address from base of 'iop_base'. 1220 */ 1221 #define IOPB_INTR_STATUS_REG 0x00 1222 #define IOPB_CHIP_ID_1 0x01 1223 #define IOPB_INTR_ENABLES 0x02 1224 #define IOPB_CHIP_TYPE_REV 0x03 1225 #define IOPB_RES_ADDR_4 0x04 1226 #define IOPB_RES_ADDR_5 0x05 1227 #define IOPB_RAM_DATA 0x06 1228 #define IOPB_RES_ADDR_7 0x07 1229 #define IOPB_FLAG_REG 0x08 1230 #define IOPB_RES_ADDR_9 0x09 1231 #define IOPB_RISC_CSR 0x0A 1232 #define IOPB_RES_ADDR_B 0x0B 1233 #define IOPB_RES_ADDR_C 0x0C 1234 #define IOPB_RES_ADDR_D 0x0D 1235 #define IOPB_SOFT_OVER_WR 0x0E 1236 #define IOPB_RES_ADDR_F 0x0F 1237 #define IOPB_MEM_CFG 0x10 1238 #define IOPB_RES_ADDR_11 0x11 1239 #define IOPB_GPIO_DATA 0x12 1240 #define IOPB_RES_ADDR_13 0x13 1241 #define IOPB_FLASH_PAGE 0x14 1242 #define IOPB_RES_ADDR_15 0x15 1243 #define IOPB_GPIO_CNTL 0x16 1244 #define IOPB_RES_ADDR_17 0x17 1245 #define IOPB_FLASH_DATA 0x18 1246 #define IOPB_RES_ADDR_19 0x19 1247 #define IOPB_RES_ADDR_1A 0x1A 1248 #define IOPB_RES_ADDR_1B 0x1B 1249 #define IOPB_RES_ADDR_1C 0x1C 1250 #define IOPB_RES_ADDR_1D 0x1D 1251 #define IOPB_RES_ADDR_1E 0x1E 1252 #define IOPB_RES_ADDR_1F 0x1F 1253 #define IOPB_DMA_CFG0 0x20 1254 #define IOPB_DMA_CFG1 0x21 1255 #define IOPB_TICKLE 0x22 1256 #define IOPB_DMA_REG_WR 0x23 1257 #define IOPB_SDMA_STATUS 0x24 1258 #define IOPB_SCSI_BYTE_CNT 0x25 1259 #define IOPB_HOST_BYTE_CNT 0x26 1260 #define IOPB_BYTE_LEFT_TO_XFER 0x27 1261 #define IOPB_BYTE_TO_XFER_0 0x28 1262 #define IOPB_BYTE_TO_XFER_1 0x29 1263 #define IOPB_BYTE_TO_XFER_2 0x2A 1264 #define IOPB_BYTE_TO_XFER_3 0x2B 1265 #define IOPB_ACC_GRP 0x2C 1266 #define IOPB_RES_ADDR_2D 0x2D 1267 #define IOPB_DEV_ID 0x2E 1268 #define IOPB_RES_ADDR_2F 0x2F 1269 #define IOPB_SCSI_DATA 0x30 1270 #define IOPB_RES_ADDR_31 0x31 1271 #define IOPB_RES_ADDR_32 0x32 1272 #define IOPB_SCSI_DATA_HSHK 0x33 1273 #define IOPB_SCSI_CTRL 0x34 1274 #define IOPB_RES_ADDR_35 0x35 1275 #define IOPB_RES_ADDR_36 0x36 1276 #define IOPB_RES_ADDR_37 0x37 1277 #define IOPB_RAM_BIST 0x38 1278 #define IOPB_PLL_TEST 0x39 1279 #define IOPB_PCI_INT_CFG 0x3A 1280 #define IOPB_RES_ADDR_3B 0x3B 1281 #define IOPB_RFIFO_CNT 0x3C 1282 #define IOPB_RES_ADDR_3D 0x3D 1283 #define IOPB_RES_ADDR_3E 0x3E 1284 #define IOPB_RES_ADDR_3F 0x3F 1285 1286 /* 1287 * Word I/O register address from base of 'iop_base'. 1288 */ 1289 #define IOPW_CHIP_ID_0 0x00 /* CID0 */ 1290 #define IOPW_CTRL_REG 0x02 /* CC */ 1291 #define IOPW_RAM_ADDR 0x04 /* LA */ 1292 #define IOPW_RAM_DATA 0x06 /* LD */ 1293 #define IOPW_RES_ADDR_08 0x08 1294 #define IOPW_RISC_CSR 0x0A /* CSR */ 1295 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 1296 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 1297 #define IOPW_RES_ADDR_10 0x10 1298 #define IOPW_SEL_MASK 0x12 /* SM */ 1299 #define IOPW_RES_ADDR_14 0x14 1300 #define IOPW_FLASH_ADDR 0x16 /* FA */ 1301 #define IOPW_RES_ADDR_18 0x18 1302 #define IOPW_EE_CMD 0x1A /* EC */ 1303 #define IOPW_EE_DATA 0x1C /* ED */ 1304 #define IOPW_SFIFO_CNT 0x1E /* SFC */ 1305 #define IOPW_RES_ADDR_20 0x20 1306 #define IOPW_Q_BASE 0x22 /* QB */ 1307 #define IOPW_QP 0x24 /* QP */ 1308 #define IOPW_IX 0x26 /* IX */ 1309 #define IOPW_SP 0x28 /* SP */ 1310 #define IOPW_PC 0x2A /* PC */ 1311 #define IOPW_RES_ADDR_2C 0x2C 1312 #define IOPW_RES_ADDR_2E 0x2E 1313 #define IOPW_SCSI_DATA 0x30 /* SD */ 1314 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 1315 #define IOPW_SCSI_CTRL 0x34 /* SC */ 1316 #define IOPW_HSHK_CFG 0x36 /* HCFG */ 1317 #define IOPW_SXFR_STATUS 0x36 /* SXS */ 1318 #define IOPW_SXFR_CNTL 0x38 /* SXL */ 1319 #define IOPW_SXFR_CNTH 0x3A /* SXH */ 1320 #define IOPW_RES_ADDR_3C 0x3C 1321 #define IOPW_RFIFO_DATA 0x3E /* RFD */ 1322 1323 /* 1324 * Doubleword I/O register address from base of 'iop_base'. 1325 */ 1326 #define IOPDW_RES_ADDR_0 0x00 1327 #define IOPDW_RAM_DATA 0x04 1328 #define IOPDW_RES_ADDR_8 0x08 1329 #define IOPDW_RES_ADDR_C 0x0C 1330 #define IOPDW_RES_ADDR_10 0x10 1331 #define IOPDW_COMMA 0x14 1332 #define IOPDW_COMMB 0x18 1333 #define IOPDW_RES_ADDR_1C 0x1C 1334 #define IOPDW_SDMA_ADDR0 0x20 1335 #define IOPDW_SDMA_ADDR1 0x24 1336 #define IOPDW_SDMA_COUNT 0x28 1337 #define IOPDW_SDMA_ERROR 0x2C 1338 #define IOPDW_RDMA_ADDR0 0x30 1339 #define IOPDW_RDMA_ADDR1 0x34 1340 #define IOPDW_RDMA_COUNT 0x38 1341 #define IOPDW_RDMA_ERROR 0x3C 1342 1343 #define ADV_CHIP_ID_BYTE 0x25 1344 #define ADV_CHIP_ID_WORD 0x04C1 1345 1346 #define ADV_INTR_ENABLE_HOST_INTR 0x01 1347 #define ADV_INTR_ENABLE_SEL_INTR 0x02 1348 #define ADV_INTR_ENABLE_DPR_INTR 0x04 1349 #define ADV_INTR_ENABLE_RTA_INTR 0x08 1350 #define ADV_INTR_ENABLE_RMA_INTR 0x10 1351 #define ADV_INTR_ENABLE_RST_INTR 0x20 1352 #define ADV_INTR_ENABLE_DPE_INTR 0x40 1353 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80 1354 1355 #define ADV_INTR_STATUS_INTRA 0x01 1356 #define ADV_INTR_STATUS_INTRB 0x02 1357 #define ADV_INTR_STATUS_INTRC 0x04 1358 1359 #define ADV_RISC_CSR_STOP (0x0000) 1360 #define ADV_RISC_TEST_COND (0x2000) 1361 #define ADV_RISC_CSR_RUN (0x4000) 1362 #define ADV_RISC_CSR_SINGLE_STEP (0x8000) 1363 1364 #define ADV_CTRL_REG_HOST_INTR 0x0100 1365 #define ADV_CTRL_REG_SEL_INTR 0x0200 1366 #define ADV_CTRL_REG_DPR_INTR 0x0400 1367 #define ADV_CTRL_REG_RTA_INTR 0x0800 1368 #define ADV_CTRL_REG_RMA_INTR 0x1000 1369 #define ADV_CTRL_REG_RES_BIT14 0x2000 1370 #define ADV_CTRL_REG_DPE_INTR 0x4000 1371 #define ADV_CTRL_REG_POWER_DONE 0x8000 1372 #define ADV_CTRL_REG_ANY_INTR 0xFF00 1373 1374 #define ADV_CTRL_REG_CMD_RESET 0x00C6 1375 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5 1376 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4 1377 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 1378 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 1379 1380 #define ADV_TICKLE_NOP 0x00 1381 #define ADV_TICKLE_A 0x01 1382 #define ADV_TICKLE_B 0x02 1383 #define ADV_TICKLE_C 0x03 1384 1385 #define AdvIsIntPending(port) \ 1386 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR) 1387 1388 /* 1389 * SCSI_CFG0 Register bit definitions 1390 */ 1391 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 1392 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 1393 #define EVEN_PARITY 0x1000 /* Select Even Parity */ 1394 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 1395 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 1396 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */ 1397 #define SCAM_EN 0x0080 /* Enable SCAM selection */ 1398 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 1399 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 1400 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 1401 #define OUR_ID 0x000F /* SCSI ID */ 1402 1403 /* 1404 * SCSI_CFG1 Register bit definitions 1405 */ 1406 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 1407 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 1408 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 1409 #define FILTER_SEL 0x0C00 /* Filter Period Selection */ 1410 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 1411 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 1412 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 1413 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */ 1414 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 1415 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 1416 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 1417 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */ 1418 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 1419 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 1420 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 1421 1422 /* 1423 * Addendum for ASC-38C0800 Chip 1424 * 1425 * The ASC-38C1600 Chip uses the same definitions except that the 1426 * bus mode override bits [12:10] have been moved to byte register 1427 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in 1428 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) 1429 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. 1430 * Also each ASC-38C1600 function or channel uses only cable bits [5:4] 1431 * and [1:0]. Bits [14], [7:6], [3:2] are unused. 1432 */ 1433 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ 1434 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */ 1435 #define HVD 0x1000 /* HVD Device Detect */ 1436 #define LVD 0x0800 /* LVD Device Detect */ 1437 #define SE 0x0400 /* SE Device Detect */ 1438 #define TERM_LVD 0x00C0 /* LVD Termination Bits */ 1439 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ 1440 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ 1441 #define TERM_SE 0x0030 /* SE Termination Bits */ 1442 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ 1443 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ 1444 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */ 1445 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */ 1446 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ 1447 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */ 1448 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ 1449 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ 1450 1451 #define CABLE_ILLEGAL_A 0x7 1452 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 1453 1454 #define CABLE_ILLEGAL_B 0xB 1455 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 1456 1457 /* 1458 * MEM_CFG Register bit definitions 1459 */ 1460 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 1461 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */ 1462 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */ 1463 #define RAM_SZ_2KB 0x00 /* 2 KB */ 1464 #define RAM_SZ_4KB 0x04 /* 4 KB */ 1465 #define RAM_SZ_8KB 0x08 /* 8 KB */ 1466 #define RAM_SZ_16KB 0x0C /* 16 KB */ 1467 #define RAM_SZ_32KB 0x10 /* 32 KB */ 1468 #define RAM_SZ_64KB 0x14 /* 64 KB */ 1469 1470 /* 1471 * DMA_CFG0 Register bit definitions 1472 * 1473 * This register is only accessible to the host. 1474 */ 1475 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 1476 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 1477 #define FIFO_THRESH_16B 0x00 /* 16 bytes */ 1478 #define FIFO_THRESH_32B 0x20 /* 32 bytes */ 1479 #define FIFO_THRESH_48B 0x30 /* 48 bytes */ 1480 #define FIFO_THRESH_64B 0x40 /* 64 bytes */ 1481 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 1482 #define FIFO_THRESH_96B 0x60 /* 96 bytes */ 1483 #define FIFO_THRESH_112B 0x70 /* 112 bytes */ 1484 #define START_CTL 0x0C /* DMA start conditions */ 1485 #define START_CTL_TH 0x00 /* Wait threshold level (default) */ 1486 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 1487 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 1488 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 1489 #define READ_CMD 0x03 /* Memory Read Method */ 1490 #define READ_CMD_MR 0x00 /* Memory Read */ 1491 #define READ_CMD_MRL 0x02 /* Memory Read Long */ 1492 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 1493 1494 /* 1495 * ASC-38C0800 RAM BIST Register bit definitions 1496 */ 1497 #define RAM_TEST_MODE 0x80 1498 #define PRE_TEST_MODE 0x40 1499 #define NORMAL_MODE 0x00 1500 #define RAM_TEST_DONE 0x10 1501 #define RAM_TEST_STATUS 0x0F 1502 #define RAM_TEST_HOST_ERROR 0x08 1503 #define RAM_TEST_INTRAM_ERROR 0x04 1504 #define RAM_TEST_RISC_ERROR 0x02 1505 #define RAM_TEST_SCSI_ERROR 0x01 1506 #define RAM_TEST_SUCCESS 0x00 1507 #define PRE_TEST_VALUE 0x05 1508 #define NORMAL_VALUE 0x00 1509 1510 /* 1511 * ASC38C1600 Definitions 1512 * 1513 * IOPB_PCI_INT_CFG Bit Field Definitions 1514 */ 1515 1516 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ 1517 1518 /* 1519 * Bit 1 can be set to change the interrupt for the Function to operate in 1520 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in 1521 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same 1522 * mode, otherwise the operating mode is undefined. 1523 */ 1524 #define TOTEMPOLE 0x02 1525 1526 /* 1527 * Bit 0 can be used to change the Int Pin for the Function. The value is 1528 * 0 by default for both Functions with Function 0 using INT A and Function 1529 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, 1530 * INT A is used. 1531 * 1532 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin 1533 * value specified in the PCI Configuration Space. 1534 */ 1535 #define INTAB 0x01 1536 1537 /* 1538 * Adv Library Status Definitions 1539 */ 1540 #define ADV_TRUE 1 1541 #define ADV_FALSE 0 1542 #define ADV_SUCCESS 1 1543 #define ADV_BUSY 0 1544 #define ADV_ERROR (-1) 1545 1546 /* 1547 * ADV_DVC_VAR 'warn_code' values 1548 */ 1549 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ 1550 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 1551 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 1552 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */ 1553 1554 #define ADV_MAX_TID 15 /* max. target identifier */ 1555 #define ADV_MAX_LUN 7 /* max. logical unit number */ 1556 1557 /* 1558 * Fixed locations of microcode operating variables. 1559 */ 1560 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 1561 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ 1562 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 1563 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ 1564 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */ 1565 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 1566 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 1567 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 1568 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ 1569 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 1570 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 1571 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 1572 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 1573 #define ASC_MC_CHIP_TYPE 0x009A 1574 #define ASC_MC_INTRB_CODE 0x009B 1575 #define ASC_MC_WDTR_ABLE 0x009C 1576 #define ASC_MC_SDTR_ABLE 0x009E 1577 #define ASC_MC_TAGQNG_ABLE 0x00A0 1578 #define ASC_MC_DISC_ENABLE 0x00A2 1579 #define ASC_MC_IDLE_CMD_STATUS 0x00A4 1580 #define ASC_MC_IDLE_CMD 0x00A6 1581 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8 1582 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC 1583 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE 1584 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0 1585 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2 1586 #define ASC_MC_SDTR_DONE 0x00B6 1587 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 1588 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 1589 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 1590 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 1591 #define ASC_MC_WDTR_DONE 0x0124 1592 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 1593 #define ASC_MC_ICQ 0x0160 1594 #define ASC_MC_IRQ 0x0164 1595 #define ASC_MC_PPR_ABLE 0x017A 1596 1597 /* 1598 * BIOS LRAM variable absolute offsets. 1599 */ 1600 #define BIOS_CODESEG 0x54 1601 #define BIOS_CODELEN 0x56 1602 #define BIOS_SIGNATURE 0x58 1603 #define BIOS_VERSION 0x5A 1604 1605 /* 1606 * Microcode Control Flags 1607 * 1608 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) 1609 * and handled by the microcode. 1610 */ 1611 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ 1612 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */ 1613 1614 /* 1615 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format 1616 */ 1617 #define HSHK_CFG_WIDE_XFR 0x8000 1618 #define HSHK_CFG_RATE 0x0F00 1619 #define HSHK_CFG_OFFSET 0x001F 1620 1621 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ 1622 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ 1623 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ 1624 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ 1625 1626 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */ 1627 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 1628 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 1629 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 1630 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */ 1631 1632 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 1633 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 1634 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ 1635 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 1636 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ 1637 /* 1638 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or 1639 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 1640 */ 1641 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 1642 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 1643 1644 /* 1645 * All fields here are accessed by the board microcode and need to be 1646 * little-endian. 1647 */ 1648 typedef struct adv_carr_t { 1649 __le32 carr_va; /* Carrier Virtual Address */ 1650 __le32 carr_pa; /* Carrier Physical Address */ 1651 __le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */ 1652 /* 1653 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer 1654 * 1655 * next_vpa [3:1] Reserved Bits 1656 * next_vpa [0] Done Flag set in Response Queue. 1657 */ 1658 __le32 next_vpa; 1659 } ADV_CARR_T; 1660 1661 /* 1662 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field. 1663 */ 1664 #define ADV_NEXT_VPA_MASK 0xFFFFFFF0 1665 1666 #define ADV_RQ_DONE 0x00000001 1667 #define ADV_RQ_GOOD 0x00000002 1668 #define ADV_CQ_STOPPER 0x00000000 1669 1670 #define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK) 1671 1672 /* 1673 * Each carrier is 64 bytes, and we need three additional 1674 * carrier for icq, irq, and the termination carrier. 1675 */ 1676 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3) 1677 1678 #define ADV_CARRIER_BUFSIZE \ 1679 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) 1680 1681 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ 1682 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ 1683 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ 1684 1685 /* 1686 * Adapter temporary configuration structure 1687 * 1688 * This structure can be discarded after initialization. Don't add 1689 * fields here needed after initialization. 1690 * 1691 * Field naming convention: 1692 * 1693 * *_enable indicates the field enables or disables a feature. The 1694 * value of the field is never reset. 1695 */ 1696 typedef struct adv_dvc_cfg { 1697 ushort disc_enable; /* enable disconnection */ 1698 uchar chip_version; /* chip version */ 1699 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ 1700 ushort control_flag; /* Microcode Control Flag */ 1701 ushort mcode_date; /* Microcode date */ 1702 ushort mcode_version; /* Microcode version */ 1703 ushort serial1; /* EEPROM serial number word 1 */ 1704 ushort serial2; /* EEPROM serial number word 2 */ 1705 ushort serial3; /* EEPROM serial number word 3 */ 1706 } ADV_DVC_CFG; 1707 1708 struct adv_dvc_var; 1709 struct adv_scsi_req_q; 1710 1711 typedef struct adv_sg_block { 1712 uchar reserved1; 1713 uchar reserved2; 1714 uchar reserved3; 1715 uchar sg_cnt; /* Valid entries in block. */ 1716 __le32 sg_ptr; /* Pointer to next sg block. */ 1717 struct { 1718 __le32 sg_addr; /* SG element address. */ 1719 __le32 sg_count; /* SG element count. */ 1720 } sg_list[NO_OF_SG_PER_BLOCK]; 1721 } ADV_SG_BLOCK; 1722 1723 /* 1724 * ADV_SCSI_REQ_Q - microcode request structure 1725 * 1726 * All fields in this structure up to byte 60 are used by the microcode. 1727 * The microcode makes assumptions about the size and ordering of fields 1728 * in this structure. Do not change the structure definition here without 1729 * coordinating the change with the microcode. 1730 * 1731 * All fields accessed by microcode must be maintained in little_endian 1732 * order. 1733 */ 1734 typedef struct adv_scsi_req_q { 1735 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */ 1736 uchar target_cmd; 1737 uchar target_id; /* Device target identifier. */ 1738 uchar target_lun; /* Device target logical unit number. */ 1739 __le32 data_addr; /* Data buffer physical address. */ 1740 __le32 data_cnt; /* Data count. Ucode sets to residual. */ 1741 __le32 sense_addr; 1742 __le32 carr_pa; 1743 uchar mflag; 1744 uchar sense_len; 1745 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ 1746 uchar scsi_cntl; 1747 uchar done_status; /* Completion status. */ 1748 uchar scsi_status; /* SCSI status byte. */ 1749 uchar host_status; /* Ucode host status. */ 1750 uchar sg_working_ix; 1751 uchar cdb[12]; /* SCSI CDB bytes 0-11. */ 1752 __le32 sg_real_addr; /* SG list physical address. */ 1753 __le32 scsiq_rptr; 1754 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */ 1755 __le32 scsiq_ptr; 1756 __le32 carr_va; 1757 /* 1758 * End of microcode structure - 60 bytes. The rest of the structure 1759 * is used by the Adv Library and ignored by the microcode. 1760 */ 1761 u32 srb_tag; 1762 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */ 1763 } ADV_SCSI_REQ_Q; 1764 1765 /* 1766 * The following two structures are used to process Wide Board requests. 1767 * 1768 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library 1769 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the 1770 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points 1771 * to the Mid-Level SCSI request structure. 1772 * 1773 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each 1774 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux 1775 * up to 255 scatter-gather elements may be used per request or 1776 * ADV_SCSI_REQ_Q. 1777 * 1778 * Both structures must be 32 byte aligned. 1779 */ 1780 typedef struct adv_sgblk { 1781 ADV_SG_BLOCK sg_block; /* Sgblock structure. */ 1782 dma_addr_t sg_addr; /* Physical address */ 1783 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */ 1784 } adv_sgblk_t; 1785 1786 typedef struct adv_req { 1787 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */ 1788 uchar align[24]; /* Request structure padding. */ 1789 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */ 1790 dma_addr_t req_addr; 1791 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */ 1792 } adv_req_t __aligned(32); 1793 1794 /* 1795 * Adapter operation variable structure. 1796 * 1797 * One structure is required per host adapter. 1798 * 1799 * Field naming convention: 1800 * 1801 * *_able indicates both whether a feature should be enabled or disabled 1802 * and whether a device is capable of the feature. At initialization 1803 * this field may be set, but later if a device is found to be incapable 1804 * of the feature, the field is cleared. 1805 */ 1806 typedef struct adv_dvc_var { 1807 AdvPortAddr iop_base; /* I/O port address */ 1808 ushort err_code; /* fatal error code */ 1809 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */ 1810 ushort wdtr_able; /* try WDTR for a device */ 1811 ushort sdtr_able; /* try SDTR for a device */ 1812 ushort ultra_able; /* try SDTR Ultra speed for a device */ 1813 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ 1814 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ 1815 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ 1816 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ 1817 ushort tagqng_able; /* try tagged queuing with a device */ 1818 ushort ppr_able; /* PPR message capable per TID bitmask. */ 1819 uchar max_dvc_qng; /* maximum number of tagged commands per device */ 1820 ushort start_motor; /* start motor command allowed */ 1821 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */ 1822 uchar chip_no; /* should be assigned by caller */ 1823 uchar max_host_qng; /* maximum number of Q'ed command allowed */ 1824 ushort no_scam; /* scam_tolerant of EEPROM */ 1825 struct asc_board *drv_ptr; /* driver pointer to private structure */ 1826 uchar chip_scsi_id; /* chip SCSI target ID */ 1827 uchar chip_type; 1828 uchar bist_err_code; 1829 ADV_CARR_T *carrier; 1830 ADV_CARR_T *carr_freelist; /* Carrier free list. */ 1831 dma_addr_t carrier_addr; 1832 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */ 1833 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */ 1834 ushort carr_pending_cnt; /* Count of pending carriers. */ 1835 /* 1836 * Note: The following fields will not be used after initialization. The 1837 * driver may discard the buffer after initialization is done. 1838 */ 1839 ADV_DVC_CFG *cfg; /* temporary configuration structure */ 1840 } ADV_DVC_VAR; 1841 1842 /* 1843 * Microcode idle loop commands 1844 */ 1845 #define IDLE_CMD_COMPLETED 0 1846 #define IDLE_CMD_STOP_CHIP 0x0001 1847 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 1848 #define IDLE_CMD_SEND_INT 0x0004 1849 #define IDLE_CMD_ABORT 0x0008 1850 #define IDLE_CMD_DEVICE_RESET 0x0010 1851 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ 1852 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ 1853 #define IDLE_CMD_SCSIREQ 0x0080 1854 1855 #define IDLE_CMD_STATUS_SUCCESS 0x0001 1856 #define IDLE_CMD_STATUS_FAILURE 0x0002 1857 1858 /* 1859 * AdvSendIdleCmd() flag definitions. 1860 */ 1861 #define ADV_NOWAIT 0x01 1862 1863 /* 1864 * Wait loop time out values. 1865 */ 1866 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ 1867 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ 1868 #define SCSI_MAX_RETRY 10 /* retry count */ 1869 1870 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 1871 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ 1872 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ 1873 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */ 1874 1875 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ 1876 1877 /* Read byte from a register. */ 1878 #define AdvReadByteRegister(iop_base, reg_off) \ 1879 (ADV_MEM_READB((iop_base) + (reg_off))) 1880 1881 /* Write byte to a register. */ 1882 #define AdvWriteByteRegister(iop_base, reg_off, byte) \ 1883 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte))) 1884 1885 /* Read word (2 bytes) from a register. */ 1886 #define AdvReadWordRegister(iop_base, reg_off) \ 1887 (ADV_MEM_READW((iop_base) + (reg_off))) 1888 1889 /* Write word (2 bytes) to a register. */ 1890 #define AdvWriteWordRegister(iop_base, reg_off, word) \ 1891 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word))) 1892 1893 /* Write dword (4 bytes) to a register. */ 1894 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \ 1895 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword))) 1896 1897 /* Read byte from LRAM. */ 1898 #define AdvReadByteLram(iop_base, addr, byte) \ 1899 do { \ 1900 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ 1901 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \ 1902 } while (0) 1903 1904 /* Write byte to LRAM. */ 1905 #define AdvWriteByteLram(iop_base, addr, byte) \ 1906 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1907 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte))) 1908 1909 /* Read word (2 bytes) from LRAM. */ 1910 #define AdvReadWordLram(iop_base, addr, word) \ 1911 do { \ 1912 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ 1913 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \ 1914 } while (0) 1915 1916 /* Write word (2 bytes) to LRAM. */ 1917 #define AdvWriteWordLram(iop_base, addr, word) \ 1918 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1919 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) 1920 1921 /* Write little-endian double word (4 bytes) to LRAM */ 1922 /* Because of unspecified C language ordering don't use auto-increment. */ 1923 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \ 1924 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1925 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ 1926 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \ 1927 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \ 1928 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ 1929 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF))))) 1930 1931 /* Read word (2 bytes) from LRAM assuming that the address is already set. */ 1932 #define AdvReadWordAutoIncLram(iop_base) \ 1933 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)) 1934 1935 /* Write word (2 bytes) to LRAM assuming that the address is already set. */ 1936 #define AdvWriteWordAutoIncLram(iop_base, word) \ 1937 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) 1938 1939 /* 1940 * Define macro to check for Condor signature. 1941 * 1942 * Evaluate to ADV_TRUE if a Condor chip is found the specified port 1943 * address 'iop_base'. Otherwise evalue to ADV_FALSE. 1944 */ 1945 #define AdvFindSignature(iop_base) \ 1946 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \ 1947 ADV_CHIP_ID_BYTE) && \ 1948 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \ 1949 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE) 1950 1951 /* 1952 * Define macro to Return the version number of the chip at 'iop_base'. 1953 * 1954 * The second parameter 'bus_type' is currently unused. 1955 */ 1956 #define AdvGetChipVersion(iop_base, bus_type) \ 1957 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV) 1958 1959 /* 1960 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must 1961 * match the ADV_SCSI_REQ_Q 'srb_tag' field. 1962 * 1963 * If the request has not yet been sent to the device it will simply be 1964 * aborted from RISC memory. If the request is disconnected it will be 1965 * aborted on reselection by sending an Abort Message to the target ID. 1966 * 1967 * Return value: 1968 * ADV_TRUE(1) - Queue was successfully aborted. 1969 * ADV_FALSE(0) - Queue was not found on the active queue list. 1970 */ 1971 #define AdvAbortQueue(asc_dvc, srb_tag) \ 1972 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \ 1973 (ADV_DCNT) (srb_tag)) 1974 1975 /* 1976 * Send a Bus Device Reset Message to the specified target ID. 1977 * 1978 * All outstanding commands will be purged if sending the 1979 * Bus Device Reset Message is successful. 1980 * 1981 * Return Value: 1982 * ADV_TRUE(1) - All requests on the target are purged. 1983 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 1984 * are not purged. 1985 */ 1986 #define AdvResetDevice(asc_dvc, target_id) \ 1987 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \ 1988 (ADV_DCNT) (target_id)) 1989 1990 /* 1991 * SCSI Wide Type definition. 1992 */ 1993 #define ADV_SCSI_BIT_ID_TYPE ushort 1994 1995 /* 1996 * AdvInitScsiTarget() 'cntl_flag' options. 1997 */ 1998 #define ADV_SCAN_LUN 0x01 1999 #define ADV_CAPINFO_NOLUN 0x02 2000 2001 /* 2002 * Convert target id to target id bit mask. 2003 */ 2004 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID)) 2005 2006 /* 2007 * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values. 2008 */ 2009 2010 #define QD_NO_STATUS 0x00 /* Request not completed yet. */ 2011 #define QD_NO_ERROR 0x01 2012 #define QD_ABORTED_BY_HOST 0x02 2013 #define QD_WITH_ERROR 0x04 2014 2015 #define QHSTA_NO_ERROR 0x00 2016 #define QHSTA_M_SEL_TIMEOUT 0x11 2017 #define QHSTA_M_DATA_OVER_RUN 0x12 2018 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 2019 #define QHSTA_M_QUEUE_ABORTED 0x15 2020 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 2021 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 2022 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 2023 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 2024 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 2025 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 2026 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 2027 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 2028 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 2029 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 2030 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 2031 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ 2032 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ 2033 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ 2034 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ 2035 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ 2036 #define QHSTA_M_WTM_TIMEOUT 0x41 2037 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 2038 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 2039 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 2040 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 2041 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ 2042 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ 2043 2044 /* Return the address that is aligned at the next doubleword >= to 'addr'. */ 2045 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F) 2046 2047 /* 2048 * Total contiguous memory needed for driver SG blocks. 2049 * 2050 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum 2051 * number of scatter-gather elements the driver supports in a 2052 * single request. 2053 */ 2054 2055 #define ADV_SG_LIST_MAX_BYTE_SIZE \ 2056 (sizeof(ADV_SG_BLOCK) * \ 2057 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)) 2058 2059 /* struct asc_board flags */ 2060 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */ 2061 2062 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0) 2063 2064 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */ 2065 2066 #define ASC_INFO_SIZE 128 /* advansys_info() line size */ 2067 2068 /* Asc Library return codes */ 2069 #define ASC_TRUE 1 2070 #define ASC_FALSE 0 2071 #define ASC_NOERROR 1 2072 #define ASC_BUSY 0 2073 #define ASC_ERROR (-1) 2074 2075 #define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1) 2076 #ifndef ADVANSYS_STATS 2077 #define ASC_STATS_ADD(shost, counter, count) 2078 #else /* ADVANSYS_STATS */ 2079 #define ASC_STATS_ADD(shost, counter, count) \ 2080 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count)) 2081 #endif /* ADVANSYS_STATS */ 2082 2083 /* If the result wraps when calculating tenths, return 0. */ 2084 #define ASC_TENTHS(num, den) \ 2085 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \ 2086 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den))))) 2087 2088 /* 2089 * Display a message to the console. 2090 */ 2091 #define ASC_PRINT(s) \ 2092 { \ 2093 printk("advansys: "); \ 2094 printk(s); \ 2095 } 2096 2097 #define ASC_PRINT1(s, a1) \ 2098 { \ 2099 printk("advansys: "); \ 2100 printk((s), (a1)); \ 2101 } 2102 2103 #define ASC_PRINT2(s, a1, a2) \ 2104 { \ 2105 printk("advansys: "); \ 2106 printk((s), (a1), (a2)); \ 2107 } 2108 2109 #define ASC_PRINT3(s, a1, a2, a3) \ 2110 { \ 2111 printk("advansys: "); \ 2112 printk((s), (a1), (a2), (a3)); \ 2113 } 2114 2115 #define ASC_PRINT4(s, a1, a2, a3, a4) \ 2116 { \ 2117 printk("advansys: "); \ 2118 printk((s), (a1), (a2), (a3), (a4)); \ 2119 } 2120 2121 #ifndef ADVANSYS_DEBUG 2122 2123 #define ASC_DBG(lvl, s...) 2124 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) 2125 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) 2126 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) 2127 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) 2128 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) 2129 #define ASC_DBG_PRT_HEX(lvl, name, start, length) 2130 #define ASC_DBG_PRT_CDB(lvl, cdb, len) 2131 #define ASC_DBG_PRT_SENSE(lvl, sense, len) 2132 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) 2133 2134 #else /* ADVANSYS_DEBUG */ 2135 2136 /* 2137 * Debugging Message Levels: 2138 * 0: Errors Only 2139 * 1: High-Level Tracing 2140 * 2-N: Verbose Tracing 2141 */ 2142 2143 #define ASC_DBG(lvl, format, arg...) { \ 2144 if (asc_dbglvl >= (lvl)) \ 2145 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \ 2146 __func__ , ## arg); \ 2147 } 2148 2149 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \ 2150 { \ 2151 if (asc_dbglvl >= (lvl)) { \ 2152 asc_prt_scsi_host(s); \ 2153 } \ 2154 } 2155 2156 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \ 2157 { \ 2158 if (asc_dbglvl >= (lvl)) { \ 2159 asc_prt_asc_scsi_q(scsiqp); \ 2160 } \ 2161 } 2162 2163 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \ 2164 { \ 2165 if (asc_dbglvl >= (lvl)) { \ 2166 asc_prt_asc_qdone_info(qdone); \ 2167 } \ 2168 } 2169 2170 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \ 2171 { \ 2172 if (asc_dbglvl >= (lvl)) { \ 2173 asc_prt_adv_scsi_req_q(scsiqp); \ 2174 } \ 2175 } 2176 2177 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \ 2178 { \ 2179 if (asc_dbglvl >= (lvl)) { \ 2180 asc_prt_hex((name), (start), (length)); \ 2181 } \ 2182 } 2183 2184 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \ 2185 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len)); 2186 2187 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \ 2188 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len)); 2189 2190 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \ 2191 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len)); 2192 #endif /* ADVANSYS_DEBUG */ 2193 2194 #ifdef ADVANSYS_STATS 2195 2196 /* Per board statistics structure */ 2197 struct asc_stats { 2198 /* Driver Entrypoint Statistics */ 2199 unsigned int queuecommand; /* # calls to advansys_queuecommand() */ 2200 unsigned int reset; /* # calls to advansys_eh_bus_reset() */ 2201 unsigned int biosparam; /* # calls to advansys_biosparam() */ 2202 unsigned int interrupt; /* # advansys_interrupt() calls */ 2203 unsigned int callback; /* # calls to asc/adv_isr_callback() */ 2204 unsigned int done; /* # calls to request's scsi_done function */ 2205 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */ 2206 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */ 2207 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */ 2208 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */ 2209 unsigned int exe_noerror; /* # ASC_NOERROR returns. */ 2210 unsigned int exe_busy; /* # ASC_BUSY returns. */ 2211 unsigned int exe_error; /* # ASC_ERROR returns. */ 2212 unsigned int exe_unknown; /* # unknown returns. */ 2213 /* Data Transfer Statistics */ 2214 unsigned int xfer_cnt; /* # I/O requests received */ 2215 unsigned int xfer_elem; /* # scatter-gather elements */ 2216 unsigned int xfer_sect; /* # 512-byte blocks */ 2217 }; 2218 #endif /* ADVANSYS_STATS */ 2219 2220 /* 2221 * Structure allocated for each board. 2222 * 2223 * This structure is allocated by scsi_host_alloc() at the end 2224 * of the 'Scsi_Host' structure starting at the 'hostdata' 2225 * field. It is guaranteed to be allocated from DMA-able memory. 2226 */ 2227 struct asc_board { 2228 struct device *dev; 2229 struct Scsi_Host *shost; 2230 uint flags; /* Board flags */ 2231 unsigned int irq; 2232 union { 2233 ASC_DVC_VAR asc_dvc_var; /* Narrow board */ 2234 ADV_DVC_VAR adv_dvc_var; /* Wide board */ 2235 } dvc_var; 2236 union { 2237 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */ 2238 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */ 2239 } dvc_cfg; 2240 ushort asc_n_io_port; /* Number I/O ports. */ 2241 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */ 2242 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */ 2243 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */ 2244 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */ 2245 union { 2246 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */ 2247 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */ 2248 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */ 2249 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */ 2250 } eep_config; 2251 /* /proc/scsi/advansys/[0...] */ 2252 #ifdef ADVANSYS_STATS 2253 struct asc_stats asc_stats; /* Board statistics */ 2254 #endif /* ADVANSYS_STATS */ 2255 /* 2256 * The following fields are used only for Narrow Boards. 2257 */ 2258 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */ 2259 /* 2260 * The following fields are used only for Wide Boards. 2261 */ 2262 void __iomem *ioremap_addr; /* I/O Memory remap address. */ 2263 ushort ioport; /* I/O Port address. */ 2264 adv_req_t *adv_reqp; /* Request structures. */ 2265 dma_addr_t adv_reqp_addr; 2266 size_t adv_reqp_size; 2267 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */ 2268 ushort bios_signature; /* BIOS Signature. */ 2269 ushort bios_version; /* BIOS Version. */ 2270 ushort bios_codeseg; /* BIOS Code Segment. */ 2271 ushort bios_codelen; /* BIOS Code Segment Length. */ 2272 }; 2273 2274 #define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \ 2275 dvc_var.asc_dvc_var) 2276 #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \ 2277 dvc_var.adv_dvc_var) 2278 #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev) 2279 2280 #ifdef ADVANSYS_DEBUG 2281 static int asc_dbglvl = 3; 2282 2283 /* 2284 * asc_prt_asc_dvc_var() 2285 */ 2286 static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h) 2287 { 2288 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h); 2289 2290 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl " 2291 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl); 2292 2293 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type, 2294 (unsigned)h->init_sdtr); 2295 2296 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, " 2297 "chip_no 0x%x,\n", (unsigned)h->sdtr_done, 2298 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready, 2299 (unsigned)h->chip_no); 2300 2301 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait " 2302 "%u,\n", (unsigned)h->queue_full_or_busy, 2303 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); 2304 2305 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, " 2306 "in_critical_cnt %u,\n", (unsigned)h->is_in_int, 2307 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng, 2308 (unsigned)h->in_critical_cnt); 2309 2310 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, " 2311 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage, 2312 (unsigned)h->init_state, (unsigned)h->no_scam, 2313 (unsigned)h->pci_fix_asyn_xfer); 2314 2315 printk(" cfg 0x%lx\n", (ulong)h->cfg); 2316 } 2317 2318 /* 2319 * asc_prt_asc_dvc_cfg() 2320 */ 2321 static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h) 2322 { 2323 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h); 2324 2325 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n", 2326 h->can_tagged_qng, h->cmd_qng_enabled); 2327 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n", 2328 h->disc_enable, h->sdtr_enable); 2329 2330 printk(" chip_scsi_id %d, chip_version %d,\n", 2331 h->chip_scsi_id, h->chip_version); 2332 2333 printk(" mcode_date 0x%x, mcode_version %d\n", 2334 h->mcode_date, h->mcode_version); 2335 } 2336 2337 /* 2338 * asc_prt_adv_dvc_var() 2339 * 2340 * Display an ADV_DVC_VAR structure. 2341 */ 2342 static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h) 2343 { 2344 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h); 2345 2346 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n", 2347 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able); 2348 2349 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n", 2350 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able); 2351 2352 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n", 2353 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); 2354 2355 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n", 2356 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng, 2357 h->carr_freelist); 2358 2359 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp); 2360 2361 printk(" no_scam 0x%x, tagqng_able 0x%x\n", 2362 (unsigned)h->no_scam, (unsigned)h->tagqng_able); 2363 2364 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n", 2365 (unsigned)h->chip_scsi_id, (ulong)h->cfg); 2366 } 2367 2368 /* 2369 * asc_prt_adv_dvc_cfg() 2370 * 2371 * Display an ADV_DVC_CFG structure. 2372 */ 2373 static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h) 2374 { 2375 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h); 2376 2377 printk(" disc_enable 0x%x, termination 0x%x\n", 2378 h->disc_enable, h->termination); 2379 2380 printk(" chip_version 0x%x, mcode_date 0x%x\n", 2381 h->chip_version, h->mcode_date); 2382 2383 printk(" mcode_version 0x%x, control_flag 0x%x\n", 2384 h->mcode_version, h->control_flag); 2385 } 2386 2387 /* 2388 * asc_prt_scsi_host() 2389 */ 2390 static void asc_prt_scsi_host(struct Scsi_Host *s) 2391 { 2392 struct asc_board *boardp = shost_priv(s); 2393 2394 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev)); 2395 printk(" host_busy %d, host_no %d,\n", 2396 scsi_host_busy(s), s->host_no); 2397 2398 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n", 2399 (ulong)s->base, (ulong)s->io_port, boardp->irq); 2400 2401 printk(" dma_channel %d, this_id %d, can_queue %d,\n", 2402 s->dma_channel, s->this_id, s->can_queue); 2403 2404 printk(" cmd_per_lun %d, sg_tablesize %d\n", 2405 s->cmd_per_lun, s->sg_tablesize); 2406 2407 if (ASC_NARROW_BOARD(boardp)) { 2408 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var); 2409 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg); 2410 } else { 2411 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var); 2412 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg); 2413 } 2414 } 2415 2416 /* 2417 * asc_prt_hex() 2418 * 2419 * Print hexadecimal output in 4 byte groupings 32 bytes 2420 * or 8 double-words per line. 2421 */ 2422 static void asc_prt_hex(char *f, uchar *s, int l) 2423 { 2424 int i; 2425 int j; 2426 int k; 2427 int m; 2428 2429 printk("%s: (%d bytes)\n", f, l); 2430 2431 for (i = 0; i < l; i += 32) { 2432 2433 /* Display a maximum of 8 double-words per line. */ 2434 if ((k = (l - i) / 4) >= 8) { 2435 k = 8; 2436 m = 0; 2437 } else { 2438 m = (l - i) % 4; 2439 } 2440 2441 for (j = 0; j < k; j++) { 2442 printk(" %2.2X%2.2X%2.2X%2.2X", 2443 (unsigned)s[i + (j * 4)], 2444 (unsigned)s[i + (j * 4) + 1], 2445 (unsigned)s[i + (j * 4) + 2], 2446 (unsigned)s[i + (j * 4) + 3]); 2447 } 2448 2449 switch (m) { 2450 case 0: 2451 default: 2452 break; 2453 case 1: 2454 printk(" %2.2X", (unsigned)s[i + (j * 4)]); 2455 break; 2456 case 2: 2457 printk(" %2.2X%2.2X", 2458 (unsigned)s[i + (j * 4)], 2459 (unsigned)s[i + (j * 4) + 1]); 2460 break; 2461 case 3: 2462 printk(" %2.2X%2.2X%2.2X", 2463 (unsigned)s[i + (j * 4) + 1], 2464 (unsigned)s[i + (j * 4) + 2], 2465 (unsigned)s[i + (j * 4) + 3]); 2466 break; 2467 } 2468 2469 printk("\n"); 2470 } 2471 } 2472 2473 /* 2474 * asc_prt_asc_scsi_q() 2475 */ 2476 static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q) 2477 { 2478 ASC_SG_HEAD *sgp; 2479 int i; 2480 2481 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q); 2482 2483 printk 2484 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n", 2485 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag, 2486 q->q2.tag_code); 2487 2488 printk 2489 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", 2490 (ulong)le32_to_cpu(q->q1.data_addr), 2491 (ulong)le32_to_cpu(q->q1.data_cnt), 2492 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len); 2493 2494 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n", 2495 (ulong)q->cdbptr, q->q2.cdb_len, 2496 (ulong)q->sg_head, q->q1.sg_queue_cnt); 2497 2498 if (q->sg_head) { 2499 sgp = q->sg_head; 2500 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp); 2501 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, 2502 sgp->queue_cnt); 2503 for (i = 0; i < sgp->entry_cnt; i++) { 2504 printk(" [%u]: addr 0x%lx, bytes %lu\n", 2505 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr), 2506 (ulong)le32_to_cpu(sgp->sg_list[i].bytes)); 2507 } 2508 2509 } 2510 } 2511 2512 /* 2513 * asc_prt_asc_qdone_info() 2514 */ 2515 static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q) 2516 { 2517 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q); 2518 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n", 2519 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len, 2520 q->d2.tag_code); 2521 printk 2522 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n", 2523 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg); 2524 } 2525 2526 /* 2527 * asc_prt_adv_sgblock() 2528 * 2529 * Display an ADV_SG_BLOCK structure. 2530 */ 2531 static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b) 2532 { 2533 int i; 2534 2535 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n", 2536 (ulong)b, sgblockno); 2537 printk(" sg_cnt %u, sg_ptr 0x%x\n", 2538 b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr)); 2539 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK); 2540 if (b->sg_ptr != 0) 2541 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK); 2542 for (i = 0; i < b->sg_cnt; i++) { 2543 printk(" [%u]: sg_addr 0x%x, sg_count 0x%x\n", 2544 i, (u32)le32_to_cpu(b->sg_list[i].sg_addr), 2545 (u32)le32_to_cpu(b->sg_list[i].sg_count)); 2546 } 2547 } 2548 2549 /* 2550 * asc_prt_adv_scsi_req_q() 2551 * 2552 * Display an ADV_SCSI_REQ_Q structure. 2553 */ 2554 static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q) 2555 { 2556 int sg_blk_cnt; 2557 struct adv_sg_block *sg_ptr; 2558 adv_sgblk_t *sgblkp; 2559 2560 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q); 2561 2562 printk(" target_id %u, target_lun %u, srb_tag 0x%x\n", 2563 q->target_id, q->target_lun, q->srb_tag); 2564 2565 printk(" cntl 0x%x, data_addr 0x%lx\n", 2566 q->cntl, (ulong)le32_to_cpu(q->data_addr)); 2567 2568 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", 2569 (ulong)le32_to_cpu(q->data_cnt), 2570 (ulong)le32_to_cpu(q->sense_addr), q->sense_len); 2571 2572 printk 2573 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n", 2574 q->cdb_len, q->done_status, q->host_status, q->scsi_status); 2575 2576 printk(" sg_working_ix 0x%x, target_cmd %u\n", 2577 q->sg_working_ix, q->target_cmd); 2578 2579 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n", 2580 (ulong)le32_to_cpu(q->scsiq_rptr), 2581 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr); 2582 2583 /* Display the request's ADV_SG_BLOCK structures. */ 2584 if (q->sg_list_ptr != NULL) { 2585 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block); 2586 sg_blk_cnt = 0; 2587 while (sgblkp) { 2588 sg_ptr = &sgblkp->sg_block; 2589 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr); 2590 if (sg_ptr->sg_ptr == 0) { 2591 break; 2592 } 2593 sgblkp = sgblkp->next_sgblkp; 2594 sg_blk_cnt++; 2595 } 2596 } 2597 } 2598 #endif /* ADVANSYS_DEBUG */ 2599 2600 /* 2601 * advansys_info() 2602 * 2603 * Return suitable for printing on the console with the argument 2604 * adapter's configuration information. 2605 * 2606 * Note: The information line should not exceed ASC_INFO_SIZE bytes, 2607 * otherwise the static 'info' array will be overrun. 2608 */ 2609 static const char *advansys_info(struct Scsi_Host *shost) 2610 { 2611 static char info[ASC_INFO_SIZE]; 2612 struct asc_board *boardp = shost_priv(shost); 2613 ASC_DVC_VAR *asc_dvc_varp; 2614 ADV_DVC_VAR *adv_dvc_varp; 2615 char *busname; 2616 char *widename = NULL; 2617 2618 if (ASC_NARROW_BOARD(boardp)) { 2619 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 2620 ASC_DBG(1, "begin\n"); 2621 2622 if (asc_dvc_varp->bus_type & ASC_IS_VL) { 2623 busname = "VL"; 2624 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) { 2625 busname = "EISA"; 2626 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) { 2627 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA) 2628 == ASC_IS_PCI_ULTRA) { 2629 busname = "PCI Ultra"; 2630 } else { 2631 busname = "PCI"; 2632 } 2633 } else { 2634 busname = "?"; 2635 shost_printk(KERN_ERR, shost, "unknown bus " 2636 "type %d\n", asc_dvc_varp->bus_type); 2637 } 2638 sprintf(info, 2639 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X", 2640 ASC_VERSION, busname, (ulong)shost->io_port, 2641 (ulong)shost->io_port + ASC_IOADR_GAP - 1, 2642 boardp->irq); 2643 } else { 2644 /* 2645 * Wide Adapter Information 2646 * 2647 * Memory-mapped I/O is used instead of I/O space to access 2648 * the adapter, but display the I/O Port range. The Memory 2649 * I/O address is displayed through the driver /proc file. 2650 */ 2651 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 2652 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2653 widename = "Ultra-Wide"; 2654 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2655 widename = "Ultra2-Wide"; 2656 } else { 2657 widename = "Ultra3-Wide"; 2658 } 2659 sprintf(info, 2660 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X", 2661 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base, 2662 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq); 2663 } 2664 BUG_ON(strlen(info) >= ASC_INFO_SIZE); 2665 ASC_DBG(1, "end\n"); 2666 return info; 2667 } 2668 2669 #ifdef CONFIG_PROC_FS 2670 2671 /* 2672 * asc_prt_board_devices() 2673 * 2674 * Print driver information for devices attached to the board. 2675 */ 2676 static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost) 2677 { 2678 struct asc_board *boardp = shost_priv(shost); 2679 int chip_scsi_id; 2680 int i; 2681 2682 seq_printf(m, 2683 "\nDevice Information for AdvanSys SCSI Host %d:\n", 2684 shost->host_no); 2685 2686 if (ASC_NARROW_BOARD(boardp)) { 2687 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id; 2688 } else { 2689 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id; 2690 } 2691 2692 seq_puts(m, "Target IDs Detected:"); 2693 for (i = 0; i <= ADV_MAX_TID; i++) { 2694 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) 2695 seq_printf(m, " %X,", i); 2696 } 2697 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id); 2698 } 2699 2700 /* 2701 * Display Wide Board BIOS Information. 2702 */ 2703 static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost) 2704 { 2705 struct asc_board *boardp = shost_priv(shost); 2706 ushort major, minor, letter; 2707 2708 seq_puts(m, "\nROM BIOS Version: "); 2709 2710 /* 2711 * If the BIOS saved a valid signature, then fill in 2712 * the BIOS code segment base address. 2713 */ 2714 if (boardp->bios_signature != 0x55AA) { 2715 seq_puts(m, "Disabled or Pre-3.1\n" 2716 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n" 2717 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n"); 2718 } else { 2719 major = (boardp->bios_version >> 12) & 0xF; 2720 minor = (boardp->bios_version >> 8) & 0xF; 2721 letter = (boardp->bios_version & 0xFF); 2722 2723 seq_printf(m, "%d.%d%c\n", 2724 major, minor, 2725 letter >= 26 ? '?' : letter + 'A'); 2726 /* 2727 * Current available ROM BIOS release is 3.1I for UW 2728 * and 3.2I for U2W. This code doesn't differentiate 2729 * UW and U2W boards. 2730 */ 2731 if (major < 3 || (major <= 3 && minor < 1) || 2732 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) { 2733 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n" 2734 "ftp://ftp.connectcom.net/pub\n"); 2735 } 2736 } 2737 } 2738 2739 /* 2740 * Add serial number to information bar if signature AAh 2741 * is found in at bit 15-9 (7 bits) of word 1. 2742 * 2743 * Serial Number consists fo 12 alpha-numeric digits. 2744 * 2745 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits) 2746 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits) 2747 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits) 2748 * 5 - Product revision (A-J) Word0: " " 2749 * 2750 * Signature Word1: 15-9 (7 bits) 2751 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit) 2752 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits) 2753 * 2754 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits) 2755 * 2756 * Note 1: Only production cards will have a serial number. 2757 * 2758 * Note 2: Signature is most significant 7 bits (0xFE). 2759 * 2760 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE. 2761 */ 2762 static int asc_get_eeprom_string(ushort *serialnum, uchar *cp) 2763 { 2764 ushort w, num; 2765 2766 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) { 2767 return ASC_FALSE; 2768 } else { 2769 /* 2770 * First word - 6 digits. 2771 */ 2772 w = serialnum[0]; 2773 2774 /* Product type - 1st digit. */ 2775 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') { 2776 /* Product type is P=Prototype */ 2777 *cp += 0x8; 2778 } 2779 cp++; 2780 2781 /* Manufacturing location - 2nd digit. */ 2782 *cp++ = 'A' + ((w & 0x1C00) >> 10); 2783 2784 /* Product ID - 3rd, 4th digits. */ 2785 num = w & 0x3FF; 2786 *cp++ = '0' + (num / 100); 2787 num %= 100; 2788 *cp++ = '0' + (num / 10); 2789 2790 /* Product revision - 5th digit. */ 2791 *cp++ = 'A' + (num % 10); 2792 2793 /* 2794 * Second word 2795 */ 2796 w = serialnum[1]; 2797 2798 /* 2799 * Year - 6th digit. 2800 * 2801 * If bit 15 of third word is set, then the 2802 * last digit of the year is greater than 7. 2803 */ 2804 if (serialnum[2] & 0x8000) { 2805 *cp++ = '8' + ((w & 0x1C0) >> 6); 2806 } else { 2807 *cp++ = '0' + ((w & 0x1C0) >> 6); 2808 } 2809 2810 /* Week of year - 7th, 8th digits. */ 2811 num = w & 0x003F; 2812 *cp++ = '0' + num / 10; 2813 num %= 10; 2814 *cp++ = '0' + num; 2815 2816 /* 2817 * Third word 2818 */ 2819 w = serialnum[2] & 0x7FFF; 2820 2821 /* Serial number - 9th digit. */ 2822 *cp++ = 'A' + (w / 1000); 2823 2824 /* 10th, 11th, 12th digits. */ 2825 num = w % 1000; 2826 *cp++ = '0' + num / 100; 2827 num %= 100; 2828 *cp++ = '0' + num / 10; 2829 num %= 10; 2830 *cp++ = '0' + num; 2831 2832 *cp = '\0'; /* Null Terminate the string. */ 2833 return ASC_TRUE; 2834 } 2835 } 2836 2837 /* 2838 * asc_prt_asc_board_eeprom() 2839 * 2840 * Print board EEPROM configuration. 2841 */ 2842 static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost) 2843 { 2844 struct asc_board *boardp = shost_priv(shost); 2845 ASCEEP_CONFIG *ep; 2846 int i; 2847 uchar serialstr[13]; 2848 2849 ep = &boardp->eep_config.asc_eep; 2850 2851 seq_printf(m, 2852 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", 2853 shost->host_no); 2854 2855 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr) 2856 == ASC_TRUE) 2857 seq_printf(m, " Serial Number: %s\n", serialstr); 2858 else if (ep->adapter_info[5] == 0xBB) 2859 seq_puts(m, 2860 " Default Settings Used for EEPROM-less Adapter.\n"); 2861 else 2862 seq_puts(m, " Serial Number Signature Not Present.\n"); 2863 2864 seq_printf(m, 2865 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2866 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, 2867 ep->max_tag_qng); 2868 2869 seq_printf(m, 2870 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam); 2871 2872 seq_puts(m, " Target ID: "); 2873 for (i = 0; i <= ASC_MAX_TID; i++) 2874 seq_printf(m, " %d", i); 2875 2876 seq_puts(m, "\n Disconnects: "); 2877 for (i = 0; i <= ASC_MAX_TID; i++) 2878 seq_printf(m, " %c", 2879 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2880 2881 seq_puts(m, "\n Command Queuing: "); 2882 for (i = 0; i <= ASC_MAX_TID; i++) 2883 seq_printf(m, " %c", 2884 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2885 2886 seq_puts(m, "\n Start Motor: "); 2887 for (i = 0; i <= ASC_MAX_TID; i++) 2888 seq_printf(m, " %c", 2889 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2890 2891 seq_puts(m, "\n Synchronous Transfer:"); 2892 for (i = 0; i <= ASC_MAX_TID; i++) 2893 seq_printf(m, " %c", 2894 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 2895 seq_putc(m, '\n'); 2896 } 2897 2898 /* 2899 * asc_prt_adv_board_eeprom() 2900 * 2901 * Print board EEPROM configuration. 2902 */ 2903 static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost) 2904 { 2905 struct asc_board *boardp = shost_priv(shost); 2906 ADV_DVC_VAR *adv_dvc_varp; 2907 int i; 2908 char *termstr; 2909 uchar serialstr[13]; 2910 ADVEEP_3550_CONFIG *ep_3550 = NULL; 2911 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL; 2912 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL; 2913 ushort word; 2914 ushort *wordp; 2915 ushort sdtr_speed = 0; 2916 2917 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 2918 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2919 ep_3550 = &boardp->eep_config.adv_3550_eep; 2920 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2921 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; 2922 } else { 2923 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; 2924 } 2925 2926 seq_printf(m, 2927 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", 2928 shost->host_no); 2929 2930 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2931 wordp = &ep_3550->serial_number_word1; 2932 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2933 wordp = &ep_38C0800->serial_number_word1; 2934 } else { 2935 wordp = &ep_38C1600->serial_number_word1; 2936 } 2937 2938 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) 2939 seq_printf(m, " Serial Number: %s\n", serialstr); 2940 else 2941 seq_puts(m, " Serial Number Signature Not Present.\n"); 2942 2943 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) 2944 seq_printf(m, 2945 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2946 ep_3550->adapter_scsi_id, 2947 ep_3550->max_host_qng, ep_3550->max_dvc_qng); 2948 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) 2949 seq_printf(m, 2950 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2951 ep_38C0800->adapter_scsi_id, 2952 ep_38C0800->max_host_qng, 2953 ep_38C0800->max_dvc_qng); 2954 else 2955 seq_printf(m, 2956 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 2957 ep_38C1600->adapter_scsi_id, 2958 ep_38C1600->max_host_qng, 2959 ep_38C1600->max_dvc_qng); 2960 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2961 word = ep_3550->termination; 2962 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2963 word = ep_38C0800->termination_lvd; 2964 } else { 2965 word = ep_38C1600->termination_lvd; 2966 } 2967 switch (word) { 2968 case 1: 2969 termstr = "Low Off/High Off"; 2970 break; 2971 case 2: 2972 termstr = "Low Off/High On"; 2973 break; 2974 case 3: 2975 termstr = "Low On/High On"; 2976 break; 2977 default: 2978 case 0: 2979 termstr = "Automatic"; 2980 break; 2981 } 2982 2983 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) 2984 seq_printf(m, 2985 " termination: %u (%s), bios_ctrl: 0x%x\n", 2986 ep_3550->termination, termstr, 2987 ep_3550->bios_ctrl); 2988 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) 2989 seq_printf(m, 2990 " termination: %u (%s), bios_ctrl: 0x%x\n", 2991 ep_38C0800->termination_lvd, termstr, 2992 ep_38C0800->bios_ctrl); 2993 else 2994 seq_printf(m, 2995 " termination: %u (%s), bios_ctrl: 0x%x\n", 2996 ep_38C1600->termination_lvd, termstr, 2997 ep_38C1600->bios_ctrl); 2998 2999 seq_puts(m, " Target ID: "); 3000 for (i = 0; i <= ADV_MAX_TID; i++) 3001 seq_printf(m, " %X", i); 3002 seq_putc(m, '\n'); 3003 3004 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3005 word = ep_3550->disc_enable; 3006 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3007 word = ep_38C0800->disc_enable; 3008 } else { 3009 word = ep_38C1600->disc_enable; 3010 } 3011 seq_puts(m, " Disconnects: "); 3012 for (i = 0; i <= ADV_MAX_TID; i++) 3013 seq_printf(m, " %c", 3014 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3015 seq_putc(m, '\n'); 3016 3017 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3018 word = ep_3550->tagqng_able; 3019 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3020 word = ep_38C0800->tagqng_able; 3021 } else { 3022 word = ep_38C1600->tagqng_able; 3023 } 3024 seq_puts(m, " Command Queuing: "); 3025 for (i = 0; i <= ADV_MAX_TID; i++) 3026 seq_printf(m, " %c", 3027 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3028 seq_putc(m, '\n'); 3029 3030 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3031 word = ep_3550->start_motor; 3032 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3033 word = ep_38C0800->start_motor; 3034 } else { 3035 word = ep_38C1600->start_motor; 3036 } 3037 seq_puts(m, " Start Motor: "); 3038 for (i = 0; i <= ADV_MAX_TID; i++) 3039 seq_printf(m, " %c", 3040 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3041 seq_putc(m, '\n'); 3042 3043 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3044 seq_puts(m, " Synchronous Transfer:"); 3045 for (i = 0; i <= ADV_MAX_TID; i++) 3046 seq_printf(m, " %c", 3047 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 3048 'Y' : 'N'); 3049 seq_putc(m, '\n'); 3050 } 3051 3052 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3053 seq_puts(m, " Ultra Transfer: "); 3054 for (i = 0; i <= ADV_MAX_TID; i++) 3055 seq_printf(m, " %c", 3056 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i)) 3057 ? 'Y' : 'N'); 3058 seq_putc(m, '\n'); 3059 } 3060 3061 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3062 word = ep_3550->wdtr_able; 3063 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3064 word = ep_38C0800->wdtr_able; 3065 } else { 3066 word = ep_38C1600->wdtr_able; 3067 } 3068 seq_puts(m, " Wide Transfer: "); 3069 for (i = 0; i <= ADV_MAX_TID; i++) 3070 seq_printf(m, " %c", 3071 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3072 seq_putc(m, '\n'); 3073 3074 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 || 3075 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) { 3076 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n "); 3077 for (i = 0; i <= ADV_MAX_TID; i++) { 3078 char *speed_str; 3079 3080 if (i == 0) { 3081 sdtr_speed = adv_dvc_varp->sdtr_speed1; 3082 } else if (i == 4) { 3083 sdtr_speed = adv_dvc_varp->sdtr_speed2; 3084 } else if (i == 8) { 3085 sdtr_speed = adv_dvc_varp->sdtr_speed3; 3086 } else if (i == 12) { 3087 sdtr_speed = adv_dvc_varp->sdtr_speed4; 3088 } 3089 switch (sdtr_speed & ADV_MAX_TID) { 3090 case 0: 3091 speed_str = "Off"; 3092 break; 3093 case 1: 3094 speed_str = " 5"; 3095 break; 3096 case 2: 3097 speed_str = " 10"; 3098 break; 3099 case 3: 3100 speed_str = " 20"; 3101 break; 3102 case 4: 3103 speed_str = " 40"; 3104 break; 3105 case 5: 3106 speed_str = " 80"; 3107 break; 3108 default: 3109 speed_str = "Unk"; 3110 break; 3111 } 3112 seq_printf(m, "%X:%s ", i, speed_str); 3113 if (i == 7) 3114 seq_puts(m, "\n "); 3115 sdtr_speed >>= 4; 3116 } 3117 seq_putc(m, '\n'); 3118 } 3119 } 3120 3121 /* 3122 * asc_prt_driver_conf() 3123 */ 3124 static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost) 3125 { 3126 struct asc_board *boardp = shost_priv(shost); 3127 3128 seq_printf(m, 3129 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n", 3130 shost->host_no); 3131 3132 seq_printf(m, 3133 " host_busy %d, max_id %u, max_lun %llu, max_channel %u\n", 3134 scsi_host_busy(shost), shost->max_id, 3135 shost->max_lun, shost->max_channel); 3136 3137 seq_printf(m, 3138 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n", 3139 shost->unique_id, shost->can_queue, shost->this_id, 3140 shost->sg_tablesize, shost->cmd_per_lun); 3141 3142 seq_printf(m, 3143 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n", 3144 boardp->flags, shost->last_reset, jiffies, 3145 boardp->asc_n_io_port); 3146 3147 seq_printf(m, " io_port 0x%lx\n", shost->io_port); 3148 } 3149 3150 /* 3151 * asc_prt_asc_board_info() 3152 * 3153 * Print dynamic board configuration information. 3154 */ 3155 static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost) 3156 { 3157 struct asc_board *boardp = shost_priv(shost); 3158 int chip_scsi_id; 3159 ASC_DVC_VAR *v; 3160 ASC_DVC_CFG *c; 3161 int i; 3162 int renegotiate = 0; 3163 3164 v = &boardp->dvc_var.asc_dvc_var; 3165 c = &boardp->dvc_cfg.asc_dvc_cfg; 3166 chip_scsi_id = c->chip_scsi_id; 3167 3168 seq_printf(m, 3169 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", 3170 shost->host_no); 3171 3172 seq_printf(m, " chip_version %u, mcode_date 0x%x, " 3173 "mcode_version 0x%x, err_code %u\n", 3174 c->chip_version, c->mcode_date, c->mcode_version, 3175 v->err_code); 3176 3177 /* Current number of commands waiting for the host. */ 3178 seq_printf(m, 3179 " Total Command Pending: %d\n", v->cur_total_qng); 3180 3181 seq_puts(m, " Command Queuing:"); 3182 for (i = 0; i <= ASC_MAX_TID; i++) { 3183 if ((chip_scsi_id == i) || 3184 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3185 continue; 3186 } 3187 seq_printf(m, " %X:%c", 3188 i, 3189 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3190 } 3191 3192 /* Current number of commands waiting for a device. */ 3193 seq_puts(m, "\n Command Queue Pending:"); 3194 for (i = 0; i <= ASC_MAX_TID; i++) { 3195 if ((chip_scsi_id == i) || 3196 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3197 continue; 3198 } 3199 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]); 3200 } 3201 3202 /* Current limit on number of commands that can be sent to a device. */ 3203 seq_puts(m, "\n Command Queue Limit:"); 3204 for (i = 0; i <= ASC_MAX_TID; i++) { 3205 if ((chip_scsi_id == i) || 3206 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3207 continue; 3208 } 3209 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]); 3210 } 3211 3212 /* Indicate whether the device has returned queue full status. */ 3213 seq_puts(m, "\n Command Queue Full:"); 3214 for (i = 0; i <= ASC_MAX_TID; i++) { 3215 if ((chip_scsi_id == i) || 3216 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3217 continue; 3218 } 3219 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) 3220 seq_printf(m, " %X:Y-%d", 3221 i, boardp->queue_full_cnt[i]); 3222 else 3223 seq_printf(m, " %X:N", i); 3224 } 3225 3226 seq_puts(m, "\n Synchronous Transfer:"); 3227 for (i = 0; i <= ASC_MAX_TID; i++) { 3228 if ((chip_scsi_id == i) || 3229 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3230 continue; 3231 } 3232 seq_printf(m, " %X:%c", 3233 i, 3234 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3235 } 3236 seq_putc(m, '\n'); 3237 3238 for (i = 0; i <= ASC_MAX_TID; i++) { 3239 uchar syn_period_ix; 3240 3241 if ((chip_scsi_id == i) || 3242 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || 3243 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) { 3244 continue; 3245 } 3246 3247 seq_printf(m, " %X:", i); 3248 3249 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) { 3250 seq_puts(m, " Asynchronous"); 3251 } else { 3252 syn_period_ix = 3253 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - 3254 1); 3255 3256 seq_printf(m, 3257 " Transfer Period Factor: %d (%d.%d Mhz),", 3258 v->sdtr_period_tbl[syn_period_ix], 3259 250 / v->sdtr_period_tbl[syn_period_ix], 3260 ASC_TENTHS(250, 3261 v->sdtr_period_tbl[syn_period_ix])); 3262 3263 seq_printf(m, " REQ/ACK Offset: %d", 3264 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET); 3265 } 3266 3267 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3268 seq_puts(m, "*\n"); 3269 renegotiate = 1; 3270 } else { 3271 seq_putc(m, '\n'); 3272 } 3273 } 3274 3275 if (renegotiate) { 3276 seq_puts(m, " * = Re-negotiation pending before next command.\n"); 3277 } 3278 } 3279 3280 /* 3281 * asc_prt_adv_board_info() 3282 * 3283 * Print dynamic board configuration information. 3284 */ 3285 static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost) 3286 { 3287 struct asc_board *boardp = shost_priv(shost); 3288 int i; 3289 ADV_DVC_VAR *v; 3290 ADV_DVC_CFG *c; 3291 AdvPortAddr iop_base; 3292 ushort chip_scsi_id; 3293 ushort lramword; 3294 uchar lrambyte; 3295 ushort tagqng_able; 3296 ushort sdtr_able, wdtr_able; 3297 ushort wdtr_done, sdtr_done; 3298 ushort period = 0; 3299 int renegotiate = 0; 3300 3301 v = &boardp->dvc_var.adv_dvc_var; 3302 c = &boardp->dvc_cfg.adv_dvc_cfg; 3303 iop_base = v->iop_base; 3304 chip_scsi_id = v->chip_scsi_id; 3305 3306 seq_printf(m, 3307 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", 3308 shost->host_no); 3309 3310 seq_printf(m, 3311 " iop_base 0x%lx, cable_detect: %X, err_code %u\n", 3312 (unsigned long)v->iop_base, 3313 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT, 3314 v->err_code); 3315 3316 seq_printf(m, " chip_version %u, mcode_date 0x%x, " 3317 "mcode_version 0x%x\n", c->chip_version, 3318 c->mcode_date, c->mcode_version); 3319 3320 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 3321 seq_puts(m, " Queuing Enabled:"); 3322 for (i = 0; i <= ADV_MAX_TID; i++) { 3323 if ((chip_scsi_id == i) || 3324 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3325 continue; 3326 } 3327 3328 seq_printf(m, " %X:%c", 3329 i, 3330 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3331 } 3332 3333 seq_puts(m, "\n Queue Limit:"); 3334 for (i = 0; i <= ADV_MAX_TID; i++) { 3335 if ((chip_scsi_id == i) || 3336 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3337 continue; 3338 } 3339 3340 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, 3341 lrambyte); 3342 3343 seq_printf(m, " %X:%d", i, lrambyte); 3344 } 3345 3346 seq_puts(m, "\n Command Pending:"); 3347 for (i = 0; i <= ADV_MAX_TID; i++) { 3348 if ((chip_scsi_id == i) || 3349 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3350 continue; 3351 } 3352 3353 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, 3354 lrambyte); 3355 3356 seq_printf(m, " %X:%d", i, lrambyte); 3357 } 3358 seq_putc(m, '\n'); 3359 3360 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 3361 seq_puts(m, " Wide Enabled:"); 3362 for (i = 0; i <= ADV_MAX_TID; i++) { 3363 if ((chip_scsi_id == i) || 3364 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3365 continue; 3366 } 3367 3368 seq_printf(m, " %X:%c", 3369 i, 3370 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3371 } 3372 seq_putc(m, '\n'); 3373 3374 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done); 3375 seq_puts(m, " Transfer Bit Width:"); 3376 for (i = 0; i <= ADV_MAX_TID; i++) { 3377 if ((chip_scsi_id == i) || 3378 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3379 continue; 3380 } 3381 3382 AdvReadWordLram(iop_base, 3383 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), 3384 lramword); 3385 3386 seq_printf(m, " %X:%d", 3387 i, (lramword & 0x8000) ? 16 : 8); 3388 3389 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) && 3390 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3391 seq_putc(m, '*'); 3392 renegotiate = 1; 3393 } 3394 } 3395 seq_putc(m, '\n'); 3396 3397 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 3398 seq_puts(m, " Synchronous Enabled:"); 3399 for (i = 0; i <= ADV_MAX_TID; i++) { 3400 if ((chip_scsi_id == i) || 3401 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3402 continue; 3403 } 3404 3405 seq_printf(m, " %X:%c", 3406 i, 3407 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3408 } 3409 seq_putc(m, '\n'); 3410 3411 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done); 3412 for (i = 0; i <= ADV_MAX_TID; i++) { 3413 3414 AdvReadWordLram(iop_base, 3415 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), 3416 lramword); 3417 lramword &= ~0x8000; 3418 3419 if ((chip_scsi_id == i) || 3420 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || 3421 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) { 3422 continue; 3423 } 3424 3425 seq_printf(m, " %X:", i); 3426 3427 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */ 3428 seq_puts(m, " Asynchronous"); 3429 } else { 3430 seq_puts(m, " Transfer Period Factor: "); 3431 3432 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */ 3433 seq_puts(m, "9 (80.0 Mhz),"); 3434 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */ 3435 seq_puts(m, "10 (40.0 Mhz),"); 3436 } else { /* 20 Mhz or below. */ 3437 3438 period = (((lramword >> 8) * 25) + 50) / 4; 3439 3440 if (period == 0) { /* Should never happen. */ 3441 seq_printf(m, "%d (? Mhz), ", period); 3442 } else { 3443 seq_printf(m, 3444 "%d (%d.%d Mhz),", 3445 period, 250 / period, 3446 ASC_TENTHS(250, period)); 3447 } 3448 } 3449 3450 seq_printf(m, " REQ/ACK Offset: %d", 3451 lramword & 0x1F); 3452 } 3453 3454 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3455 seq_puts(m, "*\n"); 3456 renegotiate = 1; 3457 } else { 3458 seq_putc(m, '\n'); 3459 } 3460 } 3461 3462 if (renegotiate) { 3463 seq_puts(m, " * = Re-negotiation pending before next command.\n"); 3464 } 3465 } 3466 3467 #ifdef ADVANSYS_STATS 3468 /* 3469 * asc_prt_board_stats() 3470 */ 3471 static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost) 3472 { 3473 struct asc_board *boardp = shost_priv(shost); 3474 struct asc_stats *s = &boardp->asc_stats; 3475 3476 seq_printf(m, 3477 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", 3478 shost->host_no); 3479 3480 seq_printf(m, 3481 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n", 3482 s->queuecommand, s->reset, s->biosparam, 3483 s->interrupt); 3484 3485 seq_printf(m, 3486 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n", 3487 s->callback, s->done, s->build_error, 3488 s->adv_build_noreq, s->adv_build_nosg); 3489 3490 seq_printf(m, 3491 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n", 3492 s->exe_noerror, s->exe_busy, s->exe_error, 3493 s->exe_unknown); 3494 3495 /* 3496 * Display data transfer statistics. 3497 */ 3498 if (s->xfer_cnt > 0) { 3499 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ", 3500 s->xfer_cnt, s->xfer_elem); 3501 3502 seq_printf(m, "xfer_bytes %u.%01u kb\n", 3503 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2)); 3504 3505 /* Scatter gather transfer statistics */ 3506 seq_printf(m, " avg_num_elem %u.%01u, ", 3507 s->xfer_elem / s->xfer_cnt, 3508 ASC_TENTHS(s->xfer_elem, s->xfer_cnt)); 3509 3510 seq_printf(m, "avg_elem_size %u.%01u kb, ", 3511 (s->xfer_sect / 2) / s->xfer_elem, 3512 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem)); 3513 3514 seq_printf(m, "avg_xfer_size %u.%01u kb\n", 3515 (s->xfer_sect / 2) / s->xfer_cnt, 3516 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt)); 3517 } 3518 } 3519 #endif /* ADVANSYS_STATS */ 3520 3521 /* 3522 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...} 3523 * 3524 * m: seq_file to print into 3525 * shost: Scsi_Host 3526 * 3527 * Return the number of bytes read from or written to a 3528 * /proc/scsi/advansys/[0...] file. 3529 */ 3530 static int 3531 advansys_show_info(struct seq_file *m, struct Scsi_Host *shost) 3532 { 3533 struct asc_board *boardp = shost_priv(shost); 3534 3535 ASC_DBG(1, "begin\n"); 3536 3537 /* 3538 * User read of /proc/scsi/advansys/[0...] file. 3539 */ 3540 3541 /* 3542 * Get board configuration information. 3543 * 3544 * advansys_info() returns the board string from its own static buffer. 3545 */ 3546 /* Copy board information. */ 3547 seq_printf(m, "%s\n", (char *)advansys_info(shost)); 3548 /* 3549 * Display Wide Board BIOS Information. 3550 */ 3551 if (!ASC_NARROW_BOARD(boardp)) 3552 asc_prt_adv_bios(m, shost); 3553 3554 /* 3555 * Display driver information for each device attached to the board. 3556 */ 3557 asc_prt_board_devices(m, shost); 3558 3559 /* 3560 * Display EEPROM configuration for the board. 3561 */ 3562 if (ASC_NARROW_BOARD(boardp)) 3563 asc_prt_asc_board_eeprom(m, shost); 3564 else 3565 asc_prt_adv_board_eeprom(m, shost); 3566 3567 /* 3568 * Display driver configuration and information for the board. 3569 */ 3570 asc_prt_driver_conf(m, shost); 3571 3572 #ifdef ADVANSYS_STATS 3573 /* 3574 * Display driver statistics for the board. 3575 */ 3576 asc_prt_board_stats(m, shost); 3577 #endif /* ADVANSYS_STATS */ 3578 3579 /* 3580 * Display Asc Library dynamic configuration information 3581 * for the board. 3582 */ 3583 if (ASC_NARROW_BOARD(boardp)) 3584 asc_prt_asc_board_info(m, shost); 3585 else 3586 asc_prt_adv_board_info(m, shost); 3587 return 0; 3588 } 3589 #endif /* CONFIG_PROC_FS */ 3590 3591 static void asc_scsi_done(struct scsi_cmnd *scp) 3592 { 3593 scsi_dma_unmap(scp); 3594 ASC_STATS(scp->device->host, done); 3595 scp->scsi_done(scp); 3596 } 3597 3598 static void AscSetBank(PortAddr iop_base, uchar bank) 3599 { 3600 uchar val; 3601 3602 val = AscGetChipControl(iop_base) & 3603 (~ 3604 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | 3605 CC_CHIP_RESET)); 3606 if (bank == 1) { 3607 val |= CC_BANK_ONE; 3608 } else if (bank == 2) { 3609 val |= CC_DIAG | CC_BANK_ONE; 3610 } else { 3611 val &= ~CC_BANK_ONE; 3612 } 3613 AscSetChipControl(iop_base, val); 3614 } 3615 3616 static void AscSetChipIH(PortAddr iop_base, ushort ins_code) 3617 { 3618 AscSetBank(iop_base, 1); 3619 AscWriteChipIH(iop_base, ins_code); 3620 AscSetBank(iop_base, 0); 3621 } 3622 3623 static int AscStartChip(PortAddr iop_base) 3624 { 3625 AscSetChipControl(iop_base, 0); 3626 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { 3627 return (0); 3628 } 3629 return (1); 3630 } 3631 3632 static bool AscStopChip(PortAddr iop_base) 3633 { 3634 uchar cc_val; 3635 3636 cc_val = 3637 AscGetChipControl(iop_base) & 3638 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG)); 3639 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT)); 3640 AscSetChipIH(iop_base, INS_HALT); 3641 AscSetChipIH(iop_base, INS_RFLAG_WTM); 3642 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) { 3643 return false; 3644 } 3645 return true; 3646 } 3647 3648 static bool AscIsChipHalted(PortAddr iop_base) 3649 { 3650 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { 3651 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) { 3652 return true; 3653 } 3654 } 3655 return false; 3656 } 3657 3658 static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc) 3659 { 3660 PortAddr iop_base; 3661 int i = 10; 3662 3663 iop_base = asc_dvc->iop_base; 3664 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) 3665 && (i-- > 0)) { 3666 mdelay(100); 3667 } 3668 AscStopChip(iop_base); 3669 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT); 3670 udelay(60); 3671 AscSetChipIH(iop_base, INS_RFLAG_WTM); 3672 AscSetChipIH(iop_base, INS_HALT); 3673 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT); 3674 AscSetChipControl(iop_base, CC_HALT); 3675 mdelay(200); 3676 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); 3677 AscSetChipStatus(iop_base, 0); 3678 return (AscIsChipHalted(iop_base)); 3679 } 3680 3681 static int AscFindSignature(PortAddr iop_base) 3682 { 3683 ushort sig_word; 3684 3685 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n", 3686 iop_base, AscGetChipSignatureByte(iop_base)); 3687 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) { 3688 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n", 3689 iop_base, AscGetChipSignatureWord(iop_base)); 3690 sig_word = AscGetChipSignatureWord(iop_base); 3691 if ((sig_word == (ushort)ASC_1000_ID0W) || 3692 (sig_word == (ushort)ASC_1000_ID0W_FIX)) { 3693 return (1); 3694 } 3695 } 3696 return (0); 3697 } 3698 3699 static void AscEnableInterrupt(PortAddr iop_base) 3700 { 3701 ushort cfg; 3702 3703 cfg = AscGetChipCfgLsw(iop_base); 3704 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON); 3705 } 3706 3707 static void AscDisableInterrupt(PortAddr iop_base) 3708 { 3709 ushort cfg; 3710 3711 cfg = AscGetChipCfgLsw(iop_base); 3712 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON)); 3713 } 3714 3715 static uchar AscReadLramByte(PortAddr iop_base, ushort addr) 3716 { 3717 unsigned char byte_data; 3718 unsigned short word_data; 3719 3720 if (isodd_word(addr)) { 3721 AscSetChipLramAddr(iop_base, addr - 1); 3722 word_data = AscGetChipLramData(iop_base); 3723 byte_data = (word_data >> 8) & 0xFF; 3724 } else { 3725 AscSetChipLramAddr(iop_base, addr); 3726 word_data = AscGetChipLramData(iop_base); 3727 byte_data = word_data & 0xFF; 3728 } 3729 return byte_data; 3730 } 3731 3732 static ushort AscReadLramWord(PortAddr iop_base, ushort addr) 3733 { 3734 ushort word_data; 3735 3736 AscSetChipLramAddr(iop_base, addr); 3737 word_data = AscGetChipLramData(iop_base); 3738 return (word_data); 3739 } 3740 3741 static void 3742 AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words) 3743 { 3744 int i; 3745 3746 AscSetChipLramAddr(iop_base, s_addr); 3747 for (i = 0; i < words; i++) { 3748 AscSetChipLramData(iop_base, set_wval); 3749 } 3750 } 3751 3752 static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val) 3753 { 3754 AscSetChipLramAddr(iop_base, addr); 3755 AscSetChipLramData(iop_base, word_val); 3756 } 3757 3758 static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val) 3759 { 3760 ushort word_data; 3761 3762 if (isodd_word(addr)) { 3763 addr--; 3764 word_data = AscReadLramWord(iop_base, addr); 3765 word_data &= 0x00FF; 3766 word_data |= (((ushort)byte_val << 8) & 0xFF00); 3767 } else { 3768 word_data = AscReadLramWord(iop_base, addr); 3769 word_data &= 0xFF00; 3770 word_data |= ((ushort)byte_val & 0x00FF); 3771 } 3772 AscWriteLramWord(iop_base, addr, word_data); 3773 } 3774 3775 /* 3776 * Copy 2 bytes to LRAM. 3777 * 3778 * The source data is assumed to be in little-endian order in memory 3779 * and is maintained in little-endian order when written to LRAM. 3780 */ 3781 static void 3782 AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr, 3783 const uchar *s_buffer, int words) 3784 { 3785 int i; 3786 3787 AscSetChipLramAddr(iop_base, s_addr); 3788 for (i = 0; i < 2 * words; i += 2) { 3789 /* 3790 * On a little-endian system the second argument below 3791 * produces a little-endian ushort which is written to 3792 * LRAM in little-endian order. On a big-endian system 3793 * the second argument produces a big-endian ushort which 3794 * is "transparently" byte-swapped by outpw() and written 3795 * in little-endian order to LRAM. 3796 */ 3797 outpw(iop_base + IOP_RAM_DATA, 3798 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); 3799 } 3800 } 3801 3802 /* 3803 * Copy 4 bytes to LRAM. 3804 * 3805 * The source data is assumed to be in little-endian order in memory 3806 * and is maintained in little-endian order when written to LRAM. 3807 */ 3808 static void 3809 AscMemDWordCopyPtrToLram(PortAddr iop_base, 3810 ushort s_addr, uchar *s_buffer, int dwords) 3811 { 3812 int i; 3813 3814 AscSetChipLramAddr(iop_base, s_addr); 3815 for (i = 0; i < 4 * dwords; i += 4) { 3816 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */ 3817 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */ 3818 } 3819 } 3820 3821 /* 3822 * Copy 2 bytes from LRAM. 3823 * 3824 * The source data is assumed to be in little-endian order in LRAM 3825 * and is maintained in little-endian order when written to memory. 3826 */ 3827 static void 3828 AscMemWordCopyPtrFromLram(PortAddr iop_base, 3829 ushort s_addr, uchar *d_buffer, int words) 3830 { 3831 int i; 3832 ushort word; 3833 3834 AscSetChipLramAddr(iop_base, s_addr); 3835 for (i = 0; i < 2 * words; i += 2) { 3836 word = inpw(iop_base + IOP_RAM_DATA); 3837 d_buffer[i] = word & 0xff; 3838 d_buffer[i + 1] = (word >> 8) & 0xff; 3839 } 3840 } 3841 3842 static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words) 3843 { 3844 u32 sum = 0; 3845 int i; 3846 3847 for (i = 0; i < words; i++, s_addr += 2) { 3848 sum += AscReadLramWord(iop_base, s_addr); 3849 } 3850 return (sum); 3851 } 3852 3853 static void AscInitLram(ASC_DVC_VAR *asc_dvc) 3854 { 3855 uchar i; 3856 ushort s_addr; 3857 PortAddr iop_base; 3858 3859 iop_base = asc_dvc->iop_base; 3860 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0, 3861 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) * 3862 64) >> 1)); 3863 i = ASC_MIN_ACTIVE_QNO; 3864 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 3865 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 3866 (uchar)(i + 1)); 3867 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 3868 (uchar)(asc_dvc->max_total_qng)); 3869 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 3870 (uchar)i); 3871 i++; 3872 s_addr += ASC_QBLK_SIZE; 3873 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 3874 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 3875 (uchar)(i + 1)); 3876 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 3877 (uchar)(i - 1)); 3878 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 3879 (uchar)i); 3880 } 3881 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 3882 (uchar)ASC_QLINK_END); 3883 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 3884 (uchar)(asc_dvc->max_total_qng - 1)); 3885 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 3886 (uchar)asc_dvc->max_total_qng); 3887 i++; 3888 s_addr += ASC_QBLK_SIZE; 3889 for (; i <= (uchar)(asc_dvc->max_total_qng + 3); 3890 i++, s_addr += ASC_QBLK_SIZE) { 3891 AscWriteLramByte(iop_base, 3892 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i); 3893 AscWriteLramByte(iop_base, 3894 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i); 3895 AscWriteLramByte(iop_base, 3896 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i); 3897 } 3898 } 3899 3900 static u32 3901 AscLoadMicroCode(PortAddr iop_base, ushort s_addr, 3902 const uchar *mcode_buf, ushort mcode_size) 3903 { 3904 u32 chksum; 3905 ushort mcode_word_size; 3906 ushort mcode_chksum; 3907 3908 /* Write the microcode buffer starting at LRAM address 0. */ 3909 mcode_word_size = (ushort)(mcode_size >> 1); 3910 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size); 3911 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size); 3912 3913 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size); 3914 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum); 3915 mcode_chksum = (ushort)AscMemSumLramWord(iop_base, 3916 (ushort)ASC_CODE_SEC_BEG, 3917 (ushort)((mcode_size - 3918 s_addr - (ushort) 3919 ASC_CODE_SEC_BEG) / 3920 2)); 3921 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum); 3922 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum); 3923 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size); 3924 return chksum; 3925 } 3926 3927 static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc) 3928 { 3929 PortAddr iop_base; 3930 int i; 3931 ushort lram_addr; 3932 3933 iop_base = asc_dvc->iop_base; 3934 AscPutRiscVarFreeQHead(iop_base, 1); 3935 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng); 3936 AscPutVarFreeQHead(iop_base, 1); 3937 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng); 3938 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B, 3939 (uchar)((int)asc_dvc->max_total_qng + 1)); 3940 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B, 3941 (uchar)((int)asc_dvc->max_total_qng + 2)); 3942 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B, 3943 asc_dvc->max_total_qng); 3944 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0); 3945 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 3946 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0); 3947 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0); 3948 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0); 3949 AscPutQDoneInProgress(iop_base, 0); 3950 lram_addr = ASC_QADR_BEG; 3951 for (i = 0; i < 32; i++, lram_addr += 2) { 3952 AscWriteLramWord(iop_base, lram_addr, 0); 3953 } 3954 } 3955 3956 static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc) 3957 { 3958 int i; 3959 int warn_code; 3960 PortAddr iop_base; 3961 __le32 phy_addr; 3962 __le32 phy_size; 3963 struct asc_board *board = asc_dvc_to_board(asc_dvc); 3964 3965 iop_base = asc_dvc->iop_base; 3966 warn_code = 0; 3967 for (i = 0; i <= ASC_MAX_TID; i++) { 3968 AscPutMCodeInitSDTRAtID(iop_base, i, 3969 asc_dvc->cfg->sdtr_period_offset[i]); 3970 } 3971 3972 AscInitQLinkVar(asc_dvc); 3973 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B, 3974 asc_dvc->cfg->disc_enable); 3975 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B, 3976 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id)); 3977 3978 /* Ensure overrun buffer is aligned on an 8 byte boundary. */ 3979 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7); 3980 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf, 3981 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 3982 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) { 3983 warn_code = -ENOMEM; 3984 goto err_dma_map; 3985 } 3986 phy_addr = cpu_to_le32(asc_dvc->overrun_dma); 3987 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D, 3988 (uchar *)&phy_addr, 1); 3989 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE); 3990 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D, 3991 (uchar *)&phy_size, 1); 3992 3993 asc_dvc->cfg->mcode_date = 3994 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W); 3995 asc_dvc->cfg->mcode_version = 3996 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W); 3997 3998 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); 3999 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { 4000 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; 4001 warn_code = -EINVAL; 4002 goto err_mcode_start; 4003 } 4004 if (AscStartChip(iop_base) != 1) { 4005 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; 4006 warn_code = -EIO; 4007 goto err_mcode_start; 4008 } 4009 4010 return warn_code; 4011 4012 err_mcode_start: 4013 dma_unmap_single(board->dev, asc_dvc->overrun_dma, 4014 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 4015 err_dma_map: 4016 asc_dvc->overrun_dma = 0; 4017 return warn_code; 4018 } 4019 4020 static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc) 4021 { 4022 const struct firmware *fw; 4023 const char fwname[] = "advansys/mcode.bin"; 4024 int err; 4025 unsigned long chksum; 4026 int warn_code; 4027 PortAddr iop_base; 4028 4029 iop_base = asc_dvc->iop_base; 4030 warn_code = 0; 4031 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) && 4032 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) { 4033 AscResetChipAndScsiBus(asc_dvc); 4034 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ 4035 } 4036 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC; 4037 if (asc_dvc->err_code != 0) 4038 return ASC_ERROR; 4039 if (!AscFindSignature(asc_dvc->iop_base)) { 4040 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 4041 return warn_code; 4042 } 4043 AscDisableInterrupt(iop_base); 4044 AscInitLram(asc_dvc); 4045 4046 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4047 if (err) { 4048 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4049 fwname, err); 4050 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4051 return err; 4052 } 4053 if (fw->size < 4) { 4054 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4055 fw->size, fwname); 4056 release_firmware(fw); 4057 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4058 return -EINVAL; 4059 } 4060 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4061 (fw->data[1] << 8) | fw->data[0]; 4062 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum); 4063 if (AscLoadMicroCode(iop_base, 0, &fw->data[4], 4064 fw->size - 4) != chksum) { 4065 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4066 release_firmware(fw); 4067 return warn_code; 4068 } 4069 release_firmware(fw); 4070 warn_code |= AscInitMicroCodeVar(asc_dvc); 4071 if (!asc_dvc->overrun_dma) 4072 return warn_code; 4073 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC; 4074 AscEnableInterrupt(iop_base); 4075 return warn_code; 4076 } 4077 4078 /* 4079 * Load the Microcode 4080 * 4081 * Write the microcode image to RISC memory starting at address 0. 4082 * 4083 * The microcode is stored compressed in the following format: 4084 * 4085 * 254 word (508 byte) table indexed by byte code followed 4086 * by the following byte codes: 4087 * 4088 * 1-Byte Code: 4089 * 00: Emit word 0 in table. 4090 * 01: Emit word 1 in table. 4091 * . 4092 * FD: Emit word 253 in table. 4093 * 4094 * Multi-Byte Code: 4095 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 4096 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 4097 * 4098 * Returns 0 or an error if the checksum doesn't match 4099 */ 4100 static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf, 4101 int size, int memsize, int chksum) 4102 { 4103 int i, j, end, len = 0; 4104 u32 sum; 4105 4106 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); 4107 4108 for (i = 253 * 2; i < size; i++) { 4109 if (buf[i] == 0xff) { 4110 unsigned short word = (buf[i + 3] << 8) | buf[i + 2]; 4111 for (j = 0; j < buf[i + 1]; j++) { 4112 AdvWriteWordAutoIncLram(iop_base, word); 4113 len += 2; 4114 } 4115 i += 3; 4116 } else if (buf[i] == 0xfe) { 4117 unsigned short word = (buf[i + 2] << 8) | buf[i + 1]; 4118 AdvWriteWordAutoIncLram(iop_base, word); 4119 i += 2; 4120 len += 2; 4121 } else { 4122 unsigned int off = buf[i] * 2; 4123 unsigned short word = (buf[off + 1] << 8) | buf[off]; 4124 AdvWriteWordAutoIncLram(iop_base, word); 4125 len += 2; 4126 } 4127 } 4128 4129 end = len; 4130 4131 while (len < memsize) { 4132 AdvWriteWordAutoIncLram(iop_base, 0); 4133 len += 2; 4134 } 4135 4136 /* Verify the microcode checksum. */ 4137 sum = 0; 4138 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); 4139 4140 for (len = 0; len < end; len += 2) { 4141 sum += AdvReadWordAutoIncLram(iop_base); 4142 } 4143 4144 if (sum != chksum) 4145 return ASC_IERR_MCODE_CHKSUM; 4146 4147 return 0; 4148 } 4149 4150 static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc) 4151 { 4152 off_t carr_offset = 0, next_offset; 4153 dma_addr_t carr_paddr; 4154 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i; 4155 4156 for (i = 0; i < carr_num; i++) { 4157 carr_offset = i * sizeof(ADV_CARR_T); 4158 /* Get physical address of the carrier 'carrp'. */ 4159 carr_paddr = adv_dvc->carrier_addr + carr_offset; 4160 4161 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr); 4162 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset); 4163 adv_dvc->carrier[i].areq_vpa = 0; 4164 next_offset = carr_offset + sizeof(ADV_CARR_T); 4165 if (i == carr_num) 4166 next_offset = ~0; 4167 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset); 4168 } 4169 /* 4170 * We cannot have a carrier with 'carr_va' of '0', as 4171 * a reference to this carrier would be interpreted as 4172 * list termination. 4173 * So start at carrier 1 with the freelist. 4174 */ 4175 adv_dvc->carr_freelist = &adv_dvc->carrier[1]; 4176 } 4177 4178 static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset) 4179 { 4180 int index; 4181 4182 BUG_ON(offset > ADV_CARRIER_BUFSIZE); 4183 4184 index = offset / sizeof(ADV_CARR_T); 4185 return &adv_dvc->carrier[index]; 4186 } 4187 4188 static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc) 4189 { 4190 ADV_CARR_T *carrp = adv_dvc->carr_freelist; 4191 u32 next_vpa = le32_to_cpu(carrp->next_vpa); 4192 4193 if (next_vpa == 0 || next_vpa == ~0) { 4194 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa); 4195 return NULL; 4196 } 4197 4198 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa); 4199 /* 4200 * insert stopper carrier to terminate list 4201 */ 4202 carrp->next_vpa = cpu_to_le32(ADV_CQ_STOPPER); 4203 4204 return carrp; 4205 } 4206 4207 /* 4208 * 'offset' is the index in the request pointer array 4209 */ 4210 static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset) 4211 { 4212 struct asc_board *boardp = adv_dvc->drv_ptr; 4213 4214 BUG_ON(offset > adv_dvc->max_host_qng); 4215 return &boardp->adv_reqp[offset]; 4216 } 4217 4218 /* 4219 * Send an idle command to the chip and wait for completion. 4220 * 4221 * Command completion is polled for once per microsecond. 4222 * 4223 * The function can be called from anywhere including an interrupt handler. 4224 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical() 4225 * functions to prevent reentrancy. 4226 * 4227 * Return Values: 4228 * ADV_TRUE - command completed successfully 4229 * ADV_FALSE - command failed 4230 * ADV_ERROR - command timed out 4231 */ 4232 static int 4233 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc, 4234 ushort idle_cmd, u32 idle_cmd_parameter) 4235 { 4236 int result, i, j; 4237 AdvPortAddr iop_base; 4238 4239 iop_base = asc_dvc->iop_base; 4240 4241 /* 4242 * Clear the idle command status which is set by the microcode 4243 * to a non-zero value to indicate when the command is completed. 4244 * The non-zero result is one of the IDLE_CMD_STATUS_* values 4245 */ 4246 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0); 4247 4248 /* 4249 * Write the idle command value after the idle command parameter 4250 * has been written to avoid a race condition. If the order is not 4251 * followed, the microcode may process the idle command before the 4252 * parameters have been written to LRAM. 4253 */ 4254 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER, 4255 cpu_to_le32(idle_cmd_parameter)); 4256 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd); 4257 4258 /* 4259 * Tickle the RISC to tell it to process the idle command. 4260 */ 4261 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B); 4262 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 4263 /* 4264 * Clear the tickle value. In the ASC-3550 the RISC flag 4265 * command 'clr_tickle_b' does not work unless the host 4266 * value is cleared. 4267 */ 4268 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP); 4269 } 4270 4271 /* Wait for up to 100 millisecond for the idle command to timeout. */ 4272 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 4273 /* Poll once each microsecond for command completion. */ 4274 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 4275 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, 4276 result); 4277 if (result != 0) 4278 return result; 4279 udelay(1); 4280 } 4281 } 4282 4283 BUG(); /* The idle command should never timeout. */ 4284 return ADV_ERROR; 4285 } 4286 4287 /* 4288 * Reset SCSI Bus and purge all outstanding requests. 4289 * 4290 * Return Value: 4291 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset. 4292 * ADV_FALSE(0) - Microcode command failed. 4293 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC 4294 * may be hung which requires driver recovery. 4295 */ 4296 static int AdvResetSB(ADV_DVC_VAR *asc_dvc) 4297 { 4298 int status; 4299 4300 /* 4301 * Send the SCSI Bus Reset idle start idle command which asserts 4302 * the SCSI Bus Reset signal. 4303 */ 4304 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L); 4305 if (status != ADV_TRUE) { 4306 return status; 4307 } 4308 4309 /* 4310 * Delay for the specified SCSI Bus Reset hold time. 4311 * 4312 * The hold time delay is done on the host because the RISC has no 4313 * microsecond accurate timer. 4314 */ 4315 udelay(ASC_SCSI_RESET_HOLD_TIME_US); 4316 4317 /* 4318 * Send the SCSI Bus Reset end idle command which de-asserts 4319 * the SCSI Bus Reset signal and purges any pending requests. 4320 */ 4321 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L); 4322 if (status != ADV_TRUE) { 4323 return status; 4324 } 4325 4326 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ 4327 4328 return status; 4329 } 4330 4331 /* 4332 * Initialize the ASC-3550. 4333 * 4334 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 4335 * 4336 * For a non-fatal error return a warning code. If there are no warnings 4337 * then 0 is returned. 4338 * 4339 * Needed after initialization for error recovery. 4340 */ 4341 static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc) 4342 { 4343 const struct firmware *fw; 4344 const char fwname[] = "advansys/3550.bin"; 4345 AdvPortAddr iop_base; 4346 ushort warn_code; 4347 int begin_addr; 4348 int end_addr; 4349 ushort code_sum; 4350 int word; 4351 int i; 4352 int err; 4353 unsigned long chksum; 4354 ushort scsi_cfg1; 4355 uchar tid; 4356 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 4357 ushort wdtr_able = 0, sdtr_able, tagqng_able; 4358 uchar max_cmd[ADV_MAX_TID + 1]; 4359 4360 /* If there is already an error, don't continue. */ 4361 if (asc_dvc->err_code != 0) 4362 return ADV_ERROR; 4363 4364 /* 4365 * The caller must set 'chip_type' to ADV_CHIP_ASC3550. 4366 */ 4367 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) { 4368 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 4369 return ADV_ERROR; 4370 } 4371 4372 warn_code = 0; 4373 iop_base = asc_dvc->iop_base; 4374 4375 /* 4376 * Save the RISC memory BIOS region before writing the microcode. 4377 * The BIOS may already be loaded and using its RISC LRAM region 4378 * so its region must be saved and restored. 4379 * 4380 * Note: This code makes the assumption, which is currently true, 4381 * that a chip reset does not clear RISC LRAM. 4382 */ 4383 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4384 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4385 bios_mem[i]); 4386 } 4387 4388 /* 4389 * Save current per TID negotiated values. 4390 */ 4391 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) { 4392 ushort bios_version, major, minor; 4393 4394 bios_version = 4395 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2]; 4396 major = (bios_version >> 12) & 0xF; 4397 minor = (bios_version >> 8) & 0xF; 4398 if (major < 3 || (major == 3 && minor == 1)) { 4399 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ 4400 AdvReadWordLram(iop_base, 0x120, wdtr_able); 4401 } else { 4402 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 4403 } 4404 } 4405 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 4406 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 4407 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4408 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 4409 max_cmd[tid]); 4410 } 4411 4412 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4413 if (err) { 4414 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4415 fwname, err); 4416 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4417 return err; 4418 } 4419 if (fw->size < 4) { 4420 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4421 fw->size, fwname); 4422 release_firmware(fw); 4423 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4424 return -EINVAL; 4425 } 4426 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4427 (fw->data[1] << 8) | fw->data[0]; 4428 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 4429 fw->size - 4, ADV_3550_MEMSIZE, 4430 chksum); 4431 release_firmware(fw); 4432 if (asc_dvc->err_code) 4433 return ADV_ERROR; 4434 4435 /* 4436 * Restore the RISC memory BIOS region. 4437 */ 4438 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4439 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4440 bios_mem[i]); 4441 } 4442 4443 /* 4444 * Calculate and write the microcode code checksum to the microcode 4445 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 4446 */ 4447 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 4448 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 4449 code_sum = 0; 4450 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 4451 for (word = begin_addr; word < end_addr; word += 2) { 4452 code_sum += AdvReadWordAutoIncLram(iop_base); 4453 } 4454 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 4455 4456 /* 4457 * Read and save microcode version and date. 4458 */ 4459 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 4460 asc_dvc->cfg->mcode_date); 4461 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 4462 asc_dvc->cfg->mcode_version); 4463 4464 /* 4465 * Set the chip type to indicate the ASC3550. 4466 */ 4467 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550); 4468 4469 /* 4470 * If the PCI Configuration Command Register "Parity Error Response 4471 * Control" Bit was clear (0), then set the microcode variable 4472 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 4473 * to ignore DMA parity errors. 4474 */ 4475 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 4476 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4477 word |= CONTROL_FLAG_IGNORE_PERR; 4478 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4479 } 4480 4481 /* 4482 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO 4483 * threshold of 128 bytes. This register is only accessible to the host. 4484 */ 4485 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 4486 START_CTL_EMFU | READ_CMD_MRM); 4487 4488 /* 4489 * Microcode operating variables for WDTR, SDTR, and command tag 4490 * queuing will be set in slave_configure() based on what a 4491 * device reports it is capable of in Inquiry byte 7. 4492 * 4493 * If SCSI Bus Resets have been disabled, then directly set 4494 * SDTR and WDTR from the EEPROM configuration. This will allow 4495 * the BIOS and warm boot to work without a SCSI bus hang on 4496 * the Inquiry caused by host and target mismatched DTR values. 4497 * Without the SCSI Bus Reset, before an Inquiry a device can't 4498 * be assumed to be in Asynchronous, Narrow mode. 4499 */ 4500 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 4501 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 4502 asc_dvc->wdtr_able); 4503 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 4504 asc_dvc->sdtr_able); 4505 } 4506 4507 /* 4508 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 4509 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 4510 * bitmask. These values determine the maximum SDTR speed negotiated 4511 * with a device. 4512 * 4513 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 4514 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 4515 * without determining here whether the device supports SDTR. 4516 * 4517 * 4-bit speed SDTR speed name 4518 * =========== =============== 4519 * 0000b (0x0) SDTR disabled 4520 * 0001b (0x1) 5 Mhz 4521 * 0010b (0x2) 10 Mhz 4522 * 0011b (0x3) 20 Mhz (Ultra) 4523 * 0100b (0x4) 40 Mhz (LVD/Ultra2) 4524 * 0101b (0x5) 80 Mhz (LVD2/Ultra3) 4525 * 0110b (0x6) Undefined 4526 * . 4527 * 1111b (0xF) Undefined 4528 */ 4529 word = 0; 4530 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4531 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) { 4532 /* Set Ultra speed for TID 'tid'. */ 4533 word |= (0x3 << (4 * (tid % 4))); 4534 } else { 4535 /* Set Fast speed for TID 'tid'. */ 4536 word |= (0x2 << (4 * (tid % 4))); 4537 } 4538 if (tid == 3) { /* Check if done with sdtr_speed1. */ 4539 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word); 4540 word = 0; 4541 } else if (tid == 7) { /* Check if done with sdtr_speed2. */ 4542 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word); 4543 word = 0; 4544 } else if (tid == 11) { /* Check if done with sdtr_speed3. */ 4545 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word); 4546 word = 0; 4547 } else if (tid == 15) { /* Check if done with sdtr_speed4. */ 4548 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word); 4549 /* End of loop. */ 4550 } 4551 } 4552 4553 /* 4554 * Set microcode operating variable for the disconnect per TID bitmask. 4555 */ 4556 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 4557 asc_dvc->cfg->disc_enable); 4558 4559 /* 4560 * Set SCSI_CFG0 Microcode Default Value. 4561 * 4562 * The microcode will set the SCSI_CFG0 register using this value 4563 * after it is started below. 4564 */ 4565 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 4566 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 4567 asc_dvc->chip_scsi_id); 4568 4569 /* 4570 * Determine SCSI_CFG1 Microcode Default Value. 4571 * 4572 * The microcode will set the SCSI_CFG1 register using this value 4573 * after it is started below. 4574 */ 4575 4576 /* Read current SCSI_CFG1 Register value. */ 4577 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 4578 4579 /* 4580 * If all three connectors are in use, return an error. 4581 */ 4582 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 4583 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 4584 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION; 4585 return ADV_ERROR; 4586 } 4587 4588 /* 4589 * If the internal narrow cable is reversed all of the SCSI_CTRL 4590 * register signals will be set. Check for and return an error if 4591 * this condition is found. 4592 */ 4593 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 4594 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 4595 return ADV_ERROR; 4596 } 4597 4598 /* 4599 * If this is a differential board and a single-ended device 4600 * is attached to one of the connectors, return an error. 4601 */ 4602 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) { 4603 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE; 4604 return ADV_ERROR; 4605 } 4606 4607 /* 4608 * If automatic termination control is enabled, then set the 4609 * termination value based on a table listed in a_condor.h. 4610 * 4611 * If manual termination was specified with an EEPROM setting 4612 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and 4613 * is ready to be 'ored' into SCSI_CFG1. 4614 */ 4615 if (asc_dvc->cfg->termination == 0) { 4616 /* 4617 * The software always controls termination by setting TERM_CTL_SEL. 4618 * If TERM_CTL_SEL were set to 0, the hardware would set termination. 4619 */ 4620 asc_dvc->cfg->termination |= TERM_CTL_SEL; 4621 4622 switch (scsi_cfg1 & CABLE_DETECT) { 4623 /* TERM_CTL_H: on, TERM_CTL_L: on */ 4624 case 0x3: 4625 case 0x7: 4626 case 0xB: 4627 case 0xD: 4628 case 0xE: 4629 case 0xF: 4630 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L); 4631 break; 4632 4633 /* TERM_CTL_H: on, TERM_CTL_L: off */ 4634 case 0x1: 4635 case 0x5: 4636 case 0x9: 4637 case 0xA: 4638 case 0xC: 4639 asc_dvc->cfg->termination |= TERM_CTL_H; 4640 break; 4641 4642 /* TERM_CTL_H: off, TERM_CTL_L: off */ 4643 case 0x2: 4644 case 0x6: 4645 break; 4646 } 4647 } 4648 4649 /* 4650 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 4651 */ 4652 scsi_cfg1 &= ~TERM_CTL; 4653 4654 /* 4655 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 4656 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 4657 * referenced, because the hardware internally inverts 4658 * the Termination High and Low bits if TERM_POL is set. 4659 */ 4660 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL)); 4661 4662 /* 4663 * Set SCSI_CFG1 Microcode Default Value 4664 * 4665 * Set filter value and possibly modified termination control 4666 * bits in the Microcode SCSI_CFG1 Register Value. 4667 * 4668 * The microcode will set the SCSI_CFG1 register using this value 4669 * after it is started below. 4670 */ 4671 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, 4672 FLTR_DISABLE | scsi_cfg1); 4673 4674 /* 4675 * Set MEM_CFG Microcode Default Value 4676 * 4677 * The microcode will set the MEM_CFG register using this value 4678 * after it is started below. 4679 * 4680 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 4681 * are defined. 4682 * 4683 * ASC-3550 has 8KB internal memory. 4684 */ 4685 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 4686 BIOS_EN | RAM_SZ_8KB); 4687 4688 /* 4689 * Set SEL_MASK Microcode Default Value 4690 * 4691 * The microcode will set the SEL_MASK register using this value 4692 * after it is started below. 4693 */ 4694 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 4695 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 4696 4697 AdvBuildCarrierFreelist(asc_dvc); 4698 4699 /* 4700 * Set-up the Host->RISC Initiator Command Queue (ICQ). 4701 */ 4702 4703 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc); 4704 if (!asc_dvc->icq_sp) { 4705 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 4706 return ADV_ERROR; 4707 } 4708 4709 /* 4710 * Set RISC ICQ physical address start value. 4711 */ 4712 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 4713 4714 /* 4715 * Set-up the RISC->Host Initiator Response Queue (IRQ). 4716 */ 4717 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc); 4718 if (!asc_dvc->irq_sp) { 4719 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 4720 return ADV_ERROR; 4721 } 4722 4723 /* 4724 * Set RISC IRQ physical address start value. 4725 */ 4726 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 4727 asc_dvc->carr_pending_cnt = 0; 4728 4729 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 4730 (ADV_INTR_ENABLE_HOST_INTR | 4731 ADV_INTR_ENABLE_GLOBAL_INTR)); 4732 4733 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 4734 AdvWriteWordRegister(iop_base, IOPW_PC, word); 4735 4736 /* finally, finally, gentlemen, start your engine */ 4737 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 4738 4739 /* 4740 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 4741 * Resets should be performed. The RISC has to be running 4742 * to issue a SCSI Bus Reset. 4743 */ 4744 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 4745 /* 4746 * If the BIOS Signature is present in memory, restore the 4747 * BIOS Handshake Configuration Table and do not perform 4748 * a SCSI Bus Reset. 4749 */ 4750 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 4751 0x55AA) { 4752 /* 4753 * Restore per TID negotiated values. 4754 */ 4755 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 4756 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 4757 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 4758 tagqng_able); 4759 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4760 AdvWriteByteLram(iop_base, 4761 ASC_MC_NUMBER_OF_MAX_CMD + tid, 4762 max_cmd[tid]); 4763 } 4764 } else { 4765 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 4766 warn_code = ASC_WARN_BUSRESET_ERROR; 4767 } 4768 } 4769 } 4770 4771 return warn_code; 4772 } 4773 4774 /* 4775 * Initialize the ASC-38C0800. 4776 * 4777 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 4778 * 4779 * For a non-fatal error return a warning code. If there are no warnings 4780 * then 0 is returned. 4781 * 4782 * Needed after initialization for error recovery. 4783 */ 4784 static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc) 4785 { 4786 const struct firmware *fw; 4787 const char fwname[] = "advansys/38C0800.bin"; 4788 AdvPortAddr iop_base; 4789 ushort warn_code; 4790 int begin_addr; 4791 int end_addr; 4792 ushort code_sum; 4793 int word; 4794 int i; 4795 int err; 4796 unsigned long chksum; 4797 ushort scsi_cfg1; 4798 uchar byte; 4799 uchar tid; 4800 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 4801 ushort wdtr_able, sdtr_able, tagqng_able; 4802 uchar max_cmd[ADV_MAX_TID + 1]; 4803 4804 /* If there is already an error, don't continue. */ 4805 if (asc_dvc->err_code != 0) 4806 return ADV_ERROR; 4807 4808 /* 4809 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800. 4810 */ 4811 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) { 4812 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 4813 return ADV_ERROR; 4814 } 4815 4816 warn_code = 0; 4817 iop_base = asc_dvc->iop_base; 4818 4819 /* 4820 * Save the RISC memory BIOS region before writing the microcode. 4821 * The BIOS may already be loaded and using its RISC LRAM region 4822 * so its region must be saved and restored. 4823 * 4824 * Note: This code makes the assumption, which is currently true, 4825 * that a chip reset does not clear RISC LRAM. 4826 */ 4827 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4828 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4829 bios_mem[i]); 4830 } 4831 4832 /* 4833 * Save current per TID negotiated values. 4834 */ 4835 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 4836 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 4837 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 4838 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 4839 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 4840 max_cmd[tid]); 4841 } 4842 4843 /* 4844 * RAM BIST (RAM Built-In Self Test) 4845 * 4846 * Address : I/O base + offset 0x38h register (byte). 4847 * Function: Bit 7-6(RW) : RAM mode 4848 * Normal Mode : 0x00 4849 * Pre-test Mode : 0x40 4850 * RAM Test Mode : 0x80 4851 * Bit 5 : unused 4852 * Bit 4(RO) : Done bit 4853 * Bit 3-0(RO) : Status 4854 * Host Error : 0x08 4855 * Int_RAM Error : 0x04 4856 * RISC Error : 0x02 4857 * SCSI Error : 0x01 4858 * No Error : 0x00 4859 * 4860 * Note: RAM BIST code should be put right here, before loading the 4861 * microcode and after saving the RISC memory BIOS region. 4862 */ 4863 4864 /* 4865 * LRAM Pre-test 4866 * 4867 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 4868 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 4869 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 4870 * to NORMAL_MODE, return an error too. 4871 */ 4872 for (i = 0; i < 2; i++) { 4873 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); 4874 mdelay(10); /* Wait for 10ms before reading back. */ 4875 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 4876 if ((byte & RAM_TEST_DONE) == 0 4877 || (byte & 0x0F) != PRE_TEST_VALUE) { 4878 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 4879 return ADV_ERROR; 4880 } 4881 4882 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 4883 mdelay(10); /* Wait for 10ms before reading back. */ 4884 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) 4885 != NORMAL_VALUE) { 4886 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 4887 return ADV_ERROR; 4888 } 4889 } 4890 4891 /* 4892 * LRAM Test - It takes about 1.5 ms to run through the test. 4893 * 4894 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 4895 * If Done bit not set or Status not 0, save register byte, set the 4896 * err_code, and return an error. 4897 */ 4898 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); 4899 mdelay(10); /* Wait for 10ms before checking status. */ 4900 4901 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 4902 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 4903 /* Get here if Done bit not set or Status not 0. */ 4904 asc_dvc->bist_err_code = byte; /* for BIOS display message */ 4905 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; 4906 return ADV_ERROR; 4907 } 4908 4909 /* We need to reset back to normal mode after LRAM test passes. */ 4910 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 4911 4912 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4913 if (err) { 4914 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4915 fwname, err); 4916 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4917 return err; 4918 } 4919 if (fw->size < 4) { 4920 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4921 fw->size, fwname); 4922 release_firmware(fw); 4923 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 4924 return -EINVAL; 4925 } 4926 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4927 (fw->data[1] << 8) | fw->data[0]; 4928 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 4929 fw->size - 4, ADV_38C0800_MEMSIZE, 4930 chksum); 4931 release_firmware(fw); 4932 if (asc_dvc->err_code) 4933 return ADV_ERROR; 4934 4935 /* 4936 * Restore the RISC memory BIOS region. 4937 */ 4938 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 4939 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 4940 bios_mem[i]); 4941 } 4942 4943 /* 4944 * Calculate and write the microcode code checksum to the microcode 4945 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 4946 */ 4947 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 4948 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 4949 code_sum = 0; 4950 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 4951 for (word = begin_addr; word < end_addr; word += 2) { 4952 code_sum += AdvReadWordAutoIncLram(iop_base); 4953 } 4954 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 4955 4956 /* 4957 * Read microcode version and date. 4958 */ 4959 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 4960 asc_dvc->cfg->mcode_date); 4961 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 4962 asc_dvc->cfg->mcode_version); 4963 4964 /* 4965 * Set the chip type to indicate the ASC38C0800. 4966 */ 4967 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800); 4968 4969 /* 4970 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 4971 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 4972 * cable detection and then we are able to read C_DET[3:0]. 4973 * 4974 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 4975 * Microcode Default Value' section below. 4976 */ 4977 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 4978 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, 4979 scsi_cfg1 | DIS_TERM_DRV); 4980 4981 /* 4982 * If the PCI Configuration Command Register "Parity Error Response 4983 * Control" Bit was clear (0), then set the microcode variable 4984 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 4985 * to ignore DMA parity errors. 4986 */ 4987 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 4988 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4989 word |= CONTROL_FLAG_IGNORE_PERR; 4990 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 4991 } 4992 4993 /* 4994 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2] 4995 * bits for the default FIFO threshold. 4996 * 4997 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 4998 * 4999 * For DMA Errata #4 set the BC_THRESH_ENB bit. 5000 */ 5001 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 5002 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | 5003 READ_CMD_MRM); 5004 5005 /* 5006 * Microcode operating variables for WDTR, SDTR, and command tag 5007 * queuing will be set in slave_configure() based on what a 5008 * device reports it is capable of in Inquiry byte 7. 5009 * 5010 * If SCSI Bus Resets have been disabled, then directly set 5011 * SDTR and WDTR from the EEPROM configuration. This will allow 5012 * the BIOS and warm boot to work without a SCSI bus hang on 5013 * the Inquiry caused by host and target mismatched DTR values. 5014 * Without the SCSI Bus Reset, before an Inquiry a device can't 5015 * be assumed to be in Asynchronous, Narrow mode. 5016 */ 5017 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 5018 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 5019 asc_dvc->wdtr_able); 5020 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 5021 asc_dvc->sdtr_able); 5022 } 5023 5024 /* 5025 * Set microcode operating variables for DISC and SDTR_SPEED1, 5026 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 5027 * configuration values. 5028 * 5029 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 5030 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 5031 * without determining here whether the device supports SDTR. 5032 */ 5033 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 5034 asc_dvc->cfg->disc_enable); 5035 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); 5036 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); 5037 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); 5038 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); 5039 5040 /* 5041 * Set SCSI_CFG0 Microcode Default Value. 5042 * 5043 * The microcode will set the SCSI_CFG0 register using this value 5044 * after it is started below. 5045 */ 5046 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 5047 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 5048 asc_dvc->chip_scsi_id); 5049 5050 /* 5051 * Determine SCSI_CFG1 Microcode Default Value. 5052 * 5053 * The microcode will set the SCSI_CFG1 register using this value 5054 * after it is started below. 5055 */ 5056 5057 /* Read current SCSI_CFG1 Register value. */ 5058 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5059 5060 /* 5061 * If the internal narrow cable is reversed all of the SCSI_CTRL 5062 * register signals will be set. Check for and return an error if 5063 * this condition is found. 5064 */ 5065 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 5066 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 5067 return ADV_ERROR; 5068 } 5069 5070 /* 5071 * All kind of combinations of devices attached to one of four 5072 * connectors are acceptable except HVD device attached. For example, 5073 * LVD device can be attached to SE connector while SE device attached 5074 * to LVD connector. If LVD device attached to SE connector, it only 5075 * runs up to Ultra speed. 5076 * 5077 * If an HVD device is attached to one of LVD connectors, return an 5078 * error. However, there is no way to detect HVD device attached to 5079 * SE connectors. 5080 */ 5081 if (scsi_cfg1 & HVD) { 5082 asc_dvc->err_code = ASC_IERR_HVD_DEVICE; 5083 return ADV_ERROR; 5084 } 5085 5086 /* 5087 * If either SE or LVD automatic termination control is enabled, then 5088 * set the termination value based on a table listed in a_condor.h. 5089 * 5090 * If manual termination was specified with an EEPROM setting then 5091 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready 5092 * to be 'ored' into SCSI_CFG1. 5093 */ 5094 if ((asc_dvc->cfg->termination & TERM_SE) == 0) { 5095 /* SE automatic termination control is enabled. */ 5096 switch (scsi_cfg1 & C_DET_SE) { 5097 /* TERM_SE_HI: on, TERM_SE_LO: on */ 5098 case 0x1: 5099 case 0x2: 5100 case 0x3: 5101 asc_dvc->cfg->termination |= TERM_SE; 5102 break; 5103 5104 /* TERM_SE_HI: on, TERM_SE_LO: off */ 5105 case 0x0: 5106 asc_dvc->cfg->termination |= TERM_SE_HI; 5107 break; 5108 } 5109 } 5110 5111 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) { 5112 /* LVD automatic termination control is enabled. */ 5113 switch (scsi_cfg1 & C_DET_LVD) { 5114 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 5115 case 0x4: 5116 case 0x8: 5117 case 0xC: 5118 asc_dvc->cfg->termination |= TERM_LVD; 5119 break; 5120 5121 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 5122 case 0x0: 5123 break; 5124 } 5125 } 5126 5127 /* 5128 * Clear any set TERM_SE and TERM_LVD bits. 5129 */ 5130 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD); 5131 5132 /* 5133 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 5134 */ 5135 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0); 5136 5137 /* 5138 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE 5139 * bits and set possibly modified termination control bits in the 5140 * Microcode SCSI_CFG1 Register Value. 5141 */ 5142 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE); 5143 5144 /* 5145 * Set SCSI_CFG1 Microcode Default Value 5146 * 5147 * Set possibly modified termination control and reset DIS_TERM_DRV 5148 * bits in the Microcode SCSI_CFG1 Register Value. 5149 * 5150 * The microcode will set the SCSI_CFG1 register using this value 5151 * after it is started below. 5152 */ 5153 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 5154 5155 /* 5156 * Set MEM_CFG Microcode Default Value 5157 * 5158 * The microcode will set the MEM_CFG register using this value 5159 * after it is started below. 5160 * 5161 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 5162 * are defined. 5163 * 5164 * ASC-38C0800 has 16KB internal memory. 5165 */ 5166 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5167 BIOS_EN | RAM_SZ_16KB); 5168 5169 /* 5170 * Set SEL_MASK Microcode Default Value 5171 * 5172 * The microcode will set the SEL_MASK register using this value 5173 * after it is started below. 5174 */ 5175 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 5176 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 5177 5178 AdvBuildCarrierFreelist(asc_dvc); 5179 5180 /* 5181 * Set-up the Host->RISC Initiator Command Queue (ICQ). 5182 */ 5183 5184 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc); 5185 if (!asc_dvc->icq_sp) { 5186 ASC_DBG(0, "Failed to get ICQ carrier\n"); 5187 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5188 return ADV_ERROR; 5189 } 5190 5191 /* 5192 * Set RISC ICQ physical address start value. 5193 * carr_pa is LE, must be native before write 5194 */ 5195 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 5196 5197 /* 5198 * Set-up the RISC->Host Initiator Response Queue (IRQ). 5199 */ 5200 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc); 5201 if (!asc_dvc->irq_sp) { 5202 ASC_DBG(0, "Failed to get IRQ carrier\n"); 5203 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5204 return ADV_ERROR; 5205 } 5206 5207 /* 5208 * Set RISC IRQ physical address start value. 5209 * 5210 * carr_pa is LE, must be native before write * 5211 */ 5212 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 5213 asc_dvc->carr_pending_cnt = 0; 5214 5215 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 5216 (ADV_INTR_ENABLE_HOST_INTR | 5217 ADV_INTR_ENABLE_GLOBAL_INTR)); 5218 5219 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 5220 AdvWriteWordRegister(iop_base, IOPW_PC, word); 5221 5222 /* finally, finally, gentlemen, start your engine */ 5223 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 5224 5225 /* 5226 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 5227 * Resets should be performed. The RISC has to be running 5228 * to issue a SCSI Bus Reset. 5229 */ 5230 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 5231 /* 5232 * If the BIOS Signature is present in memory, restore the 5233 * BIOS Handshake Configuration Table and do not perform 5234 * a SCSI Bus Reset. 5235 */ 5236 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 5237 0x55AA) { 5238 /* 5239 * Restore per TID negotiated values. 5240 */ 5241 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5242 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5243 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 5244 tagqng_able); 5245 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5246 AdvWriteByteLram(iop_base, 5247 ASC_MC_NUMBER_OF_MAX_CMD + tid, 5248 max_cmd[tid]); 5249 } 5250 } else { 5251 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 5252 warn_code = ASC_WARN_BUSRESET_ERROR; 5253 } 5254 } 5255 } 5256 5257 return warn_code; 5258 } 5259 5260 /* 5261 * Initialize the ASC-38C1600. 5262 * 5263 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 5264 * 5265 * For a non-fatal error return a warning code. If there are no warnings 5266 * then 0 is returned. 5267 * 5268 * Needed after initialization for error recovery. 5269 */ 5270 static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc) 5271 { 5272 const struct firmware *fw; 5273 const char fwname[] = "advansys/38C1600.bin"; 5274 AdvPortAddr iop_base; 5275 ushort warn_code; 5276 int begin_addr; 5277 int end_addr; 5278 ushort code_sum; 5279 long word; 5280 int i; 5281 int err; 5282 unsigned long chksum; 5283 ushort scsi_cfg1; 5284 uchar byte; 5285 uchar tid; 5286 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 5287 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able; 5288 uchar max_cmd[ASC_MAX_TID + 1]; 5289 5290 /* If there is already an error, don't continue. */ 5291 if (asc_dvc->err_code != 0) { 5292 return ADV_ERROR; 5293 } 5294 5295 /* 5296 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600. 5297 */ 5298 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { 5299 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 5300 return ADV_ERROR; 5301 } 5302 5303 warn_code = 0; 5304 iop_base = asc_dvc->iop_base; 5305 5306 /* 5307 * Save the RISC memory BIOS region before writing the microcode. 5308 * The BIOS may already be loaded and using its RISC LRAM region 5309 * so its region must be saved and restored. 5310 * 5311 * Note: This code makes the assumption, which is currently true, 5312 * that a chip reset does not clear RISC LRAM. 5313 */ 5314 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5315 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5316 bios_mem[i]); 5317 } 5318 5319 /* 5320 * Save current per TID negotiated values. 5321 */ 5322 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5323 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5324 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5325 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5326 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 5327 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5328 max_cmd[tid]); 5329 } 5330 5331 /* 5332 * RAM BIST (Built-In Self Test) 5333 * 5334 * Address : I/O base + offset 0x38h register (byte). 5335 * Function: Bit 7-6(RW) : RAM mode 5336 * Normal Mode : 0x00 5337 * Pre-test Mode : 0x40 5338 * RAM Test Mode : 0x80 5339 * Bit 5 : unused 5340 * Bit 4(RO) : Done bit 5341 * Bit 3-0(RO) : Status 5342 * Host Error : 0x08 5343 * Int_RAM Error : 0x04 5344 * RISC Error : 0x02 5345 * SCSI Error : 0x01 5346 * No Error : 0x00 5347 * 5348 * Note: RAM BIST code should be put right here, before loading the 5349 * microcode and after saving the RISC memory BIOS region. 5350 */ 5351 5352 /* 5353 * LRAM Pre-test 5354 * 5355 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 5356 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 5357 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 5358 * to NORMAL_MODE, return an error too. 5359 */ 5360 for (i = 0; i < 2; i++) { 5361 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); 5362 mdelay(10); /* Wait for 10ms before reading back. */ 5363 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 5364 if ((byte & RAM_TEST_DONE) == 0 5365 || (byte & 0x0F) != PRE_TEST_VALUE) { 5366 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 5367 return ADV_ERROR; 5368 } 5369 5370 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 5371 mdelay(10); /* Wait for 10ms before reading back. */ 5372 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) 5373 != NORMAL_VALUE) { 5374 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 5375 return ADV_ERROR; 5376 } 5377 } 5378 5379 /* 5380 * LRAM Test - It takes about 1.5 ms to run through the test. 5381 * 5382 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 5383 * If Done bit not set or Status not 0, save register byte, set the 5384 * err_code, and return an error. 5385 */ 5386 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); 5387 mdelay(10); /* Wait for 10ms before checking status. */ 5388 5389 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 5390 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 5391 /* Get here if Done bit not set or Status not 0. */ 5392 asc_dvc->bist_err_code = byte; /* for BIOS display message */ 5393 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; 5394 return ADV_ERROR; 5395 } 5396 5397 /* We need to reset back to normal mode after LRAM test passes. */ 5398 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 5399 5400 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 5401 if (err) { 5402 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 5403 fwname, err); 5404 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5405 return err; 5406 } 5407 if (fw->size < 4) { 5408 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 5409 fw->size, fwname); 5410 release_firmware(fw); 5411 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5412 return -EINVAL; 5413 } 5414 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 5415 (fw->data[1] << 8) | fw->data[0]; 5416 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 5417 fw->size - 4, ADV_38C1600_MEMSIZE, 5418 chksum); 5419 release_firmware(fw); 5420 if (asc_dvc->err_code) 5421 return ADV_ERROR; 5422 5423 /* 5424 * Restore the RISC memory BIOS region. 5425 */ 5426 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5427 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5428 bios_mem[i]); 5429 } 5430 5431 /* 5432 * Calculate and write the microcode code checksum to the microcode 5433 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 5434 */ 5435 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 5436 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 5437 code_sum = 0; 5438 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 5439 for (word = begin_addr; word < end_addr; word += 2) { 5440 code_sum += AdvReadWordAutoIncLram(iop_base); 5441 } 5442 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 5443 5444 /* 5445 * Read microcode version and date. 5446 */ 5447 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 5448 asc_dvc->cfg->mcode_date); 5449 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 5450 asc_dvc->cfg->mcode_version); 5451 5452 /* 5453 * Set the chip type to indicate the ASC38C1600. 5454 */ 5455 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600); 5456 5457 /* 5458 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 5459 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 5460 * cable detection and then we are able to read C_DET[3:0]. 5461 * 5462 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 5463 * Microcode Default Value' section below. 5464 */ 5465 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5466 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, 5467 scsi_cfg1 | DIS_TERM_DRV); 5468 5469 /* 5470 * If the PCI Configuration Command Register "Parity Error Response 5471 * Control" Bit was clear (0), then set the microcode variable 5472 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 5473 * to ignore DMA parity errors. 5474 */ 5475 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 5476 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5477 word |= CONTROL_FLAG_IGNORE_PERR; 5478 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5479 } 5480 5481 /* 5482 * If the BIOS control flag AIPP (Asynchronous Information 5483 * Phase Protection) disable bit is not set, then set the firmware 5484 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable 5485 * AIPP checking and encoding. 5486 */ 5487 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 5488 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5489 word |= CONTROL_FLAG_ENABLE_AIPP; 5490 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5491 } 5492 5493 /* 5494 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4], 5495 * and START_CTL_TH [3:2]. 5496 */ 5497 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 5498 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 5499 5500 /* 5501 * Microcode operating variables for WDTR, SDTR, and command tag 5502 * queuing will be set in slave_configure() based on what a 5503 * device reports it is capable of in Inquiry byte 7. 5504 * 5505 * If SCSI Bus Resets have been disabled, then directly set 5506 * SDTR and WDTR from the EEPROM configuration. This will allow 5507 * the BIOS and warm boot to work without a SCSI bus hang on 5508 * the Inquiry caused by host and target mismatched DTR values. 5509 * Without the SCSI Bus Reset, before an Inquiry a device can't 5510 * be assumed to be in Asynchronous, Narrow mode. 5511 */ 5512 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 5513 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 5514 asc_dvc->wdtr_able); 5515 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 5516 asc_dvc->sdtr_able); 5517 } 5518 5519 /* 5520 * Set microcode operating variables for DISC and SDTR_SPEED1, 5521 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 5522 * configuration values. 5523 * 5524 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 5525 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 5526 * without determining here whether the device supports SDTR. 5527 */ 5528 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 5529 asc_dvc->cfg->disc_enable); 5530 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); 5531 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); 5532 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); 5533 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); 5534 5535 /* 5536 * Set SCSI_CFG0 Microcode Default Value. 5537 * 5538 * The microcode will set the SCSI_CFG0 register using this value 5539 * after it is started below. 5540 */ 5541 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 5542 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 5543 asc_dvc->chip_scsi_id); 5544 5545 /* 5546 * Calculate SCSI_CFG1 Microcode Default Value. 5547 * 5548 * The microcode will set the SCSI_CFG1 register using this value 5549 * after it is started below. 5550 * 5551 * Each ASC-38C1600 function has only two cable detect bits. 5552 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 5553 */ 5554 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5555 5556 /* 5557 * If the cable is reversed all of the SCSI_CTRL register signals 5558 * will be set. Check for and return an error if this condition is 5559 * found. 5560 */ 5561 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 5562 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 5563 return ADV_ERROR; 5564 } 5565 5566 /* 5567 * Each ASC-38C1600 function has two connectors. Only an HVD device 5568 * can not be connected to either connector. An LVD device or SE device 5569 * may be connected to either connecor. If an SE device is connected, 5570 * then at most Ultra speed (20 Mhz) can be used on both connectors. 5571 * 5572 * If an HVD device is attached, return an error. 5573 */ 5574 if (scsi_cfg1 & HVD) { 5575 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE; 5576 return ADV_ERROR; 5577 } 5578 5579 /* 5580 * Each function in the ASC-38C1600 uses only the SE cable detect and 5581 * termination because there are two connectors for each function. Each 5582 * function may use either LVD or SE mode. Corresponding the SE automatic 5583 * termination control EEPROM bits are used for each function. Each 5584 * function has its own EEPROM. If SE automatic control is enabled for 5585 * the function, then set the termination value based on a table listed 5586 * in a_condor.h. 5587 * 5588 * If manual termination is specified in the EEPROM for the function, 5589 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is 5590 * ready to be 'ored' into SCSI_CFG1. 5591 */ 5592 if ((asc_dvc->cfg->termination & TERM_SE) == 0) { 5593 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); 5594 /* SE automatic termination control is enabled. */ 5595 switch (scsi_cfg1 & C_DET_SE) { 5596 /* TERM_SE_HI: on, TERM_SE_LO: on */ 5597 case 0x1: 5598 case 0x2: 5599 case 0x3: 5600 asc_dvc->cfg->termination |= TERM_SE; 5601 break; 5602 5603 case 0x0: 5604 if (PCI_FUNC(pdev->devfn) == 0) { 5605 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 5606 } else { 5607 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 5608 asc_dvc->cfg->termination |= TERM_SE_HI; 5609 } 5610 break; 5611 } 5612 } 5613 5614 /* 5615 * Clear any set TERM_SE bits. 5616 */ 5617 scsi_cfg1 &= ~TERM_SE; 5618 5619 /* 5620 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 5621 */ 5622 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE); 5623 5624 /* 5625 * Clear Big Endian and Terminator Polarity bits and set possibly 5626 * modified termination control bits in the Microcode SCSI_CFG1 5627 * Register Value. 5628 * 5629 * Big Endian bit is not used even on big endian machines. 5630 */ 5631 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL); 5632 5633 /* 5634 * Set SCSI_CFG1 Microcode Default Value 5635 * 5636 * Set possibly modified termination control bits in the Microcode 5637 * SCSI_CFG1 Register Value. 5638 * 5639 * The microcode will set the SCSI_CFG1 register using this value 5640 * after it is started below. 5641 */ 5642 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 5643 5644 /* 5645 * Set MEM_CFG Microcode Default Value 5646 * 5647 * The microcode will set the MEM_CFG register using this value 5648 * after it is started below. 5649 * 5650 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 5651 * are defined. 5652 * 5653 * ASC-38C1600 has 32KB internal memory. 5654 * 5655 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come 5656 * out a special 16K Adv Library and Microcode version. After the issue 5657 * resolved, we should turn back to the 32K support. Both a_condor.h and 5658 * mcode.sas files also need to be updated. 5659 * 5660 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5661 * BIOS_EN | RAM_SZ_32KB); 5662 */ 5663 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5664 BIOS_EN | RAM_SZ_16KB); 5665 5666 /* 5667 * Set SEL_MASK Microcode Default Value 5668 * 5669 * The microcode will set the SEL_MASK register using this value 5670 * after it is started below. 5671 */ 5672 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 5673 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 5674 5675 AdvBuildCarrierFreelist(asc_dvc); 5676 5677 /* 5678 * Set-up the Host->RISC Initiator Command Queue (ICQ). 5679 */ 5680 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc); 5681 if (!asc_dvc->icq_sp) { 5682 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5683 return ADV_ERROR; 5684 } 5685 5686 /* 5687 * Set RISC ICQ physical address start value. Initialize the 5688 * COMMA register to the same value otherwise the RISC will 5689 * prematurely detect a command is available. 5690 */ 5691 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 5692 AdvWriteDWordRegister(iop_base, IOPDW_COMMA, 5693 le32_to_cpu(asc_dvc->icq_sp->carr_pa)); 5694 5695 /* 5696 * Set-up the RISC->Host Initiator Response Queue (IRQ). 5697 */ 5698 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc); 5699 if (!asc_dvc->irq_sp) { 5700 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5701 return ADV_ERROR; 5702 } 5703 5704 /* 5705 * Set RISC IRQ physical address start value. 5706 */ 5707 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 5708 asc_dvc->carr_pending_cnt = 0; 5709 5710 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 5711 (ADV_INTR_ENABLE_HOST_INTR | 5712 ADV_INTR_ENABLE_GLOBAL_INTR)); 5713 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 5714 AdvWriteWordRegister(iop_base, IOPW_PC, word); 5715 5716 /* finally, finally, gentlemen, start your engine */ 5717 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 5718 5719 /* 5720 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 5721 * Resets should be performed. The RISC has to be running 5722 * to issue a SCSI Bus Reset. 5723 */ 5724 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 5725 /* 5726 * If the BIOS Signature is present in memory, restore the 5727 * per TID microcode operating variables. 5728 */ 5729 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 5730 0x55AA) { 5731 /* 5732 * Restore per TID negotiated values. 5733 */ 5734 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5735 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5736 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5737 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 5738 tagqng_able); 5739 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 5740 AdvWriteByteLram(iop_base, 5741 ASC_MC_NUMBER_OF_MAX_CMD + tid, 5742 max_cmd[tid]); 5743 } 5744 } else { 5745 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 5746 warn_code = ASC_WARN_BUSRESET_ERROR; 5747 } 5748 } 5749 } 5750 5751 return warn_code; 5752 } 5753 5754 /* 5755 * Reset chip and SCSI Bus. 5756 * 5757 * Return Value: 5758 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 5759 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 5760 */ 5761 static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc) 5762 { 5763 int status; 5764 ushort wdtr_able, sdtr_able, tagqng_able; 5765 ushort ppr_able = 0; 5766 uchar tid, max_cmd[ADV_MAX_TID + 1]; 5767 AdvPortAddr iop_base; 5768 ushort bios_sig; 5769 5770 iop_base = asc_dvc->iop_base; 5771 5772 /* 5773 * Save current per TID negotiated values. 5774 */ 5775 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5776 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5777 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 5778 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5779 } 5780 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5781 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5782 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5783 max_cmd[tid]); 5784 } 5785 5786 /* 5787 * Force the AdvInitAsc3550/38C0800Driver() function to 5788 * perform a SCSI Bus Reset by clearing the BIOS signature word. 5789 * The initialization functions assumes a SCSI Bus Reset is not 5790 * needed if the BIOS signature word is present. 5791 */ 5792 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); 5793 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0); 5794 5795 /* 5796 * Stop chip and reset it. 5797 */ 5798 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP); 5799 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET); 5800 mdelay(100); 5801 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 5802 ADV_CTRL_REG_CMD_WR_IO_REG); 5803 5804 /* 5805 * Reset Adv Library error code, if any, and try 5806 * re-initializing the chip. 5807 */ 5808 asc_dvc->err_code = 0; 5809 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 5810 status = AdvInitAsc38C1600Driver(asc_dvc); 5811 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 5812 status = AdvInitAsc38C0800Driver(asc_dvc); 5813 } else { 5814 status = AdvInitAsc3550Driver(asc_dvc); 5815 } 5816 5817 /* Translate initialization return value to status value. */ 5818 if (status == 0) { 5819 status = ADV_TRUE; 5820 } else { 5821 status = ADV_FALSE; 5822 } 5823 5824 /* 5825 * Restore the BIOS signature word. 5826 */ 5827 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); 5828 5829 /* 5830 * Restore per TID negotiated values. 5831 */ 5832 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5833 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5834 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 5835 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 5836 } 5837 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5838 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5839 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5840 max_cmd[tid]); 5841 } 5842 5843 return status; 5844 } 5845 5846 /* 5847 * adv_async_callback() - Adv Library asynchronous event callback function. 5848 */ 5849 static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code) 5850 { 5851 switch (code) { 5852 case ADV_ASYNC_SCSI_BUS_RESET_DET: 5853 /* 5854 * The firmware detected a SCSI Bus reset. 5855 */ 5856 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n"); 5857 break; 5858 5859 case ADV_ASYNC_RDMA_FAILURE: 5860 /* 5861 * Handle RDMA failure by resetting the SCSI Bus and 5862 * possibly the chip if it is unresponsive. Log the error 5863 * with a unique code. 5864 */ 5865 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n"); 5866 AdvResetChipAndSB(adv_dvc_varp); 5867 break; 5868 5869 case ADV_HOST_SCSI_BUS_RESET: 5870 /* 5871 * Host generated SCSI bus reset occurred. 5872 */ 5873 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n"); 5874 break; 5875 5876 default: 5877 ASC_DBG(0, "unknown code 0x%x\n", code); 5878 break; 5879 } 5880 } 5881 5882 /* 5883 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR(). 5884 * 5885 * Callback function for the Wide SCSI Adv Library. 5886 */ 5887 static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp) 5888 { 5889 struct asc_board *boardp = adv_dvc_varp->drv_ptr; 5890 adv_req_t *reqp; 5891 adv_sgblk_t *sgblkp; 5892 struct scsi_cmnd *scp; 5893 u32 resid_cnt; 5894 dma_addr_t sense_addr; 5895 5896 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n", 5897 adv_dvc_varp, scsiqp); 5898 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); 5899 5900 /* 5901 * Get the adv_req_t structure for the command that has been 5902 * completed. The adv_req_t structure actually contains the 5903 * completed ADV_SCSI_REQ_Q structure. 5904 */ 5905 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag); 5906 5907 ASC_DBG(1, "scp 0x%p\n", scp); 5908 if (scp == NULL) { 5909 ASC_PRINT 5910 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n"); 5911 return; 5912 } 5913 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); 5914 5915 reqp = (adv_req_t *)scp->host_scribble; 5916 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp); 5917 if (reqp == NULL) { 5918 ASC_PRINT("adv_isr_callback: reqp is NULL\n"); 5919 return; 5920 } 5921 /* 5922 * Remove backreferences to avoid duplicate 5923 * command completions. 5924 */ 5925 scp->host_scribble = NULL; 5926 reqp->cmndp = NULL; 5927 5928 ASC_STATS(boardp->shost, callback); 5929 ASC_DBG(1, "shost 0x%p\n", boardp->shost); 5930 5931 sense_addr = le32_to_cpu(scsiqp->sense_addr); 5932 dma_unmap_single(boardp->dev, sense_addr, 5933 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 5934 5935 /* 5936 * 'done_status' contains the command's ending status. 5937 */ 5938 scp->result = 0; 5939 switch (scsiqp->done_status) { 5940 case QD_NO_ERROR: 5941 ASC_DBG(2, "QD_NO_ERROR\n"); 5942 5943 /* 5944 * Check for an underrun condition. 5945 * 5946 * If there was no error and an underrun condition, then 5947 * then return the number of underrun bytes. 5948 */ 5949 resid_cnt = le32_to_cpu(scsiqp->data_cnt); 5950 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 && 5951 resid_cnt <= scsi_bufflen(scp)) { 5952 ASC_DBG(1, "underrun condition %lu bytes\n", 5953 (ulong)resid_cnt); 5954 scsi_set_resid(scp, resid_cnt); 5955 } 5956 break; 5957 5958 case QD_WITH_ERROR: 5959 ASC_DBG(2, "QD_WITH_ERROR\n"); 5960 switch (scsiqp->host_status) { 5961 case QHSTA_NO_ERROR: 5962 set_status_byte(scp, scsiqp->scsi_status); 5963 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) { 5964 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n"); 5965 ASC_DBG_PRT_SENSE(2, scp->sense_buffer, 5966 SCSI_SENSE_BUFFERSIZE); 5967 set_driver_byte(scp, DRIVER_SENSE); 5968 } 5969 break; 5970 5971 default: 5972 /* Some other QHSTA error occurred. */ 5973 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status); 5974 set_host_byte(scp, DID_BAD_TARGET); 5975 break; 5976 } 5977 break; 5978 5979 case QD_ABORTED_BY_HOST: 5980 ASC_DBG(1, "QD_ABORTED_BY_HOST\n"); 5981 set_status_byte(scp, scsiqp->scsi_status); 5982 set_host_byte(scp, DID_ABORT); 5983 break; 5984 5985 default: 5986 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status); 5987 set_status_byte(scp, scsiqp->scsi_status); 5988 set_host_byte(scp, DID_ERROR); 5989 break; 5990 } 5991 5992 /* 5993 * If the 'init_tidmask' bit isn't already set for the target and the 5994 * current request finished normally, then set the bit for the target 5995 * to indicate that a device is present. 5996 */ 5997 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && 5998 scsiqp->done_status == QD_NO_ERROR && 5999 scsiqp->host_status == QHSTA_NO_ERROR) { 6000 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); 6001 } 6002 6003 asc_scsi_done(scp); 6004 6005 /* 6006 * Free all 'adv_sgblk_t' structures allocated for the request. 6007 */ 6008 while ((sgblkp = reqp->sgblkp) != NULL) { 6009 /* Remove 'sgblkp' from the request list. */ 6010 reqp->sgblkp = sgblkp->next_sgblkp; 6011 6012 dma_pool_free(boardp->adv_sgblk_pool, sgblkp, 6013 sgblkp->sg_addr); 6014 } 6015 6016 ASC_DBG(1, "done\n"); 6017 } 6018 6019 /* 6020 * Adv Library Interrupt Service Routine 6021 * 6022 * This function is called by a driver's interrupt service routine. 6023 * The function disables and re-enables interrupts. 6024 * 6025 * When a microcode idle command is completed, the ADV_DVC_VAR 6026 * 'idle_cmd_done' field is set to ADV_TRUE. 6027 * 6028 * Note: AdvISR() can be called when interrupts are disabled or even 6029 * when there is no hardware interrupt condition present. It will 6030 * always check for completed idle commands and microcode requests. 6031 * This is an important feature that shouldn't be changed because it 6032 * allows commands to be completed from polling mode loops. 6033 * 6034 * Return: 6035 * ADV_TRUE(1) - interrupt was pending 6036 * ADV_FALSE(0) - no interrupt was pending 6037 */ 6038 static int AdvISR(ADV_DVC_VAR *asc_dvc) 6039 { 6040 AdvPortAddr iop_base; 6041 uchar int_stat; 6042 ADV_CARR_T *free_carrp; 6043 __le32 irq_next_vpa; 6044 ADV_SCSI_REQ_Q *scsiq; 6045 adv_req_t *reqp; 6046 6047 iop_base = asc_dvc->iop_base; 6048 6049 /* Reading the register clears the interrupt. */ 6050 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG); 6051 6052 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB | 6053 ADV_INTR_STATUS_INTRC)) == 0) { 6054 return ADV_FALSE; 6055 } 6056 6057 /* 6058 * Notify the driver of an asynchronous microcode condition by 6059 * calling the adv_async_callback function. The function 6060 * is passed the microcode ASC_MC_INTRB_CODE byte value. 6061 */ 6062 if (int_stat & ADV_INTR_STATUS_INTRB) { 6063 uchar intrb_code; 6064 6065 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code); 6066 6067 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || 6068 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 6069 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 6070 asc_dvc->carr_pending_cnt != 0) { 6071 AdvWriteByteRegister(iop_base, IOPB_TICKLE, 6072 ADV_TICKLE_A); 6073 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 6074 AdvWriteByteRegister(iop_base, 6075 IOPB_TICKLE, 6076 ADV_TICKLE_NOP); 6077 } 6078 } 6079 } 6080 6081 adv_async_callback(asc_dvc, intrb_code); 6082 } 6083 6084 /* 6085 * Check if the IRQ stopper carrier contains a completed request. 6086 */ 6087 while (((irq_next_vpa = 6088 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ADV_RQ_DONE) != 0) { 6089 /* 6090 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure. 6091 * The RISC will have set 'areq_vpa' to a virtual address. 6092 * 6093 * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr 6094 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion 6095 * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr' 6096 * in AdvExeScsiQueue(). 6097 */ 6098 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa); 6099 ASC_DBG(1, "irq_sp %p areq_vpa %u\n", 6100 asc_dvc->irq_sp, pa_offset); 6101 reqp = adv_get_reqp(asc_dvc, pa_offset); 6102 scsiq = &reqp->scsi_req_q; 6103 6104 /* 6105 * Request finished with good status and the queue was not 6106 * DMAed to host memory by the firmware. Set all status fields 6107 * to indicate good status. 6108 */ 6109 if ((irq_next_vpa & ADV_RQ_GOOD) != 0) { 6110 scsiq->done_status = QD_NO_ERROR; 6111 scsiq->host_status = scsiq->scsi_status = 0; 6112 scsiq->data_cnt = 0L; 6113 } 6114 6115 /* 6116 * Advance the stopper pointer to the next carrier 6117 * ignoring the lower four bits. Free the previous 6118 * stopper carrier. 6119 */ 6120 free_carrp = asc_dvc->irq_sp; 6121 asc_dvc->irq_sp = adv_get_carrier(asc_dvc, 6122 ADV_GET_CARRP(irq_next_vpa)); 6123 6124 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va; 6125 asc_dvc->carr_freelist = free_carrp; 6126 asc_dvc->carr_pending_cnt--; 6127 6128 /* 6129 * Clear request microcode control flag. 6130 */ 6131 scsiq->cntl = 0; 6132 6133 /* 6134 * Notify the driver of the completed request by passing 6135 * the ADV_SCSI_REQ_Q pointer to its callback function. 6136 */ 6137 adv_isr_callback(asc_dvc, scsiq); 6138 /* 6139 * Note: After the driver callback function is called, 'scsiq' 6140 * can no longer be referenced. 6141 * 6142 * Fall through and continue processing other completed 6143 * requests... 6144 */ 6145 } 6146 return ADV_TRUE; 6147 } 6148 6149 static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code) 6150 { 6151 if (asc_dvc->err_code == 0) { 6152 asc_dvc->err_code = err_code; 6153 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W, 6154 err_code); 6155 } 6156 return err_code; 6157 } 6158 6159 static void AscAckInterrupt(PortAddr iop_base) 6160 { 6161 uchar host_flag; 6162 uchar risc_flag; 6163 ushort loop; 6164 6165 loop = 0; 6166 do { 6167 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B); 6168 if (loop++ > 0x7FFF) { 6169 break; 6170 } 6171 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 6172 host_flag = 6173 AscReadLramByte(iop_base, 6174 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT); 6175 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, 6176 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT)); 6177 AscSetChipStatus(iop_base, CIW_INT_ACK); 6178 loop = 0; 6179 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) { 6180 AscSetChipStatus(iop_base, CIW_INT_ACK); 6181 if (loop++ > 3) { 6182 break; 6183 } 6184 } 6185 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); 6186 } 6187 6188 static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time) 6189 { 6190 const uchar *period_table; 6191 int max_index; 6192 int min_index; 6193 int i; 6194 6195 period_table = asc_dvc->sdtr_period_tbl; 6196 max_index = (int)asc_dvc->max_sdtr_index; 6197 min_index = (int)asc_dvc->min_sdtr_index; 6198 if ((syn_time <= period_table[max_index])) { 6199 for (i = min_index; i < (max_index - 1); i++) { 6200 if (syn_time <= period_table[i]) { 6201 return (uchar)i; 6202 } 6203 } 6204 return (uchar)max_index; 6205 } else { 6206 return (uchar)(max_index + 1); 6207 } 6208 } 6209 6210 static uchar 6211 AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset) 6212 { 6213 PortAddr iop_base = asc_dvc->iop_base; 6214 uchar sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period); 6215 EXT_MSG sdtr_buf = { 6216 .msg_type = EXTENDED_MESSAGE, 6217 .msg_len = MS_SDTR_LEN, 6218 .msg_req = EXTENDED_SDTR, 6219 .xfer_period = sdtr_period, 6220 .req_ack_offset = sdtr_offset, 6221 }; 6222 sdtr_offset &= ASC_SYN_MAX_OFFSET; 6223 6224 if (sdtr_period_index <= asc_dvc->max_sdtr_index) { 6225 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, 6226 (uchar *)&sdtr_buf, 6227 sizeof(EXT_MSG) >> 1); 6228 return ((sdtr_period_index << 4) | sdtr_offset); 6229 } else { 6230 sdtr_buf.req_ack_offset = 0; 6231 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, 6232 (uchar *)&sdtr_buf, 6233 sizeof(EXT_MSG) >> 1); 6234 return 0; 6235 } 6236 } 6237 6238 static uchar 6239 AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset) 6240 { 6241 uchar byte; 6242 uchar sdtr_period_ix; 6243 6244 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period); 6245 if (sdtr_period_ix > asc_dvc->max_sdtr_index) 6246 return 0xFF; 6247 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 6248 return byte; 6249 } 6250 6251 static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data) 6252 { 6253 ASC_SCSI_BIT_ID_TYPE org_id; 6254 int i; 6255 bool sta = true; 6256 6257 AscSetBank(iop_base, 1); 6258 org_id = AscReadChipDvcID(iop_base); 6259 for (i = 0; i <= ASC_MAX_TID; i++) { 6260 if (org_id == (0x01 << i)) 6261 break; 6262 } 6263 org_id = (ASC_SCSI_BIT_ID_TYPE) i; 6264 AscWriteChipDvcID(iop_base, id); 6265 if (AscReadChipDvcID(iop_base) == (0x01 << id)) { 6266 AscSetBank(iop_base, 0); 6267 AscSetChipSyn(iop_base, sdtr_data); 6268 if (AscGetChipSyn(iop_base) != sdtr_data) { 6269 sta = false; 6270 } 6271 } else { 6272 sta = false; 6273 } 6274 AscSetBank(iop_base, 1); 6275 AscWriteChipDvcID(iop_base, org_id); 6276 AscSetBank(iop_base, 0); 6277 return (sta); 6278 } 6279 6280 static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no) 6281 { 6282 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); 6283 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data); 6284 } 6285 6286 static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) 6287 { 6288 EXT_MSG ext_msg; 6289 EXT_MSG out_msg; 6290 ushort halt_q_addr; 6291 bool sdtr_accept; 6292 ushort int_halt_code; 6293 ASC_SCSI_BIT_ID_TYPE scsi_busy; 6294 ASC_SCSI_BIT_ID_TYPE target_id; 6295 PortAddr iop_base; 6296 uchar tag_code; 6297 uchar q_status; 6298 uchar halt_qp; 6299 uchar sdtr_data; 6300 uchar target_ix; 6301 uchar q_cntl, tid_no; 6302 uchar cur_dvc_qng; 6303 uchar asyn_sdtr; 6304 uchar scsi_status; 6305 struct asc_board *boardp; 6306 6307 BUG_ON(!asc_dvc->drv_ptr); 6308 boardp = asc_dvc->drv_ptr; 6309 6310 iop_base = asc_dvc->iop_base; 6311 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W); 6312 6313 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B); 6314 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 6315 target_ix = AscReadLramByte(iop_base, 6316 (ushort)(halt_q_addr + 6317 (ushort)ASC_SCSIQ_B_TARGET_IX)); 6318 q_cntl = AscReadLramByte(iop_base, 6319 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL)); 6320 tid_no = ASC_TIX_TO_TID(target_ix); 6321 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no); 6322 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 6323 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 6324 } else { 6325 asyn_sdtr = 0; 6326 } 6327 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 6328 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 6329 AscSetChipSDTR(iop_base, 0, tid_no); 6330 boardp->sdtr_data[tid_no] = 0; 6331 } 6332 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6333 return; 6334 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 6335 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 6336 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 6337 boardp->sdtr_data[tid_no] = asyn_sdtr; 6338 } 6339 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6340 return; 6341 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 6342 AscMemWordCopyPtrFromLram(iop_base, 6343 ASCV_MSGIN_BEG, 6344 (uchar *)&ext_msg, 6345 sizeof(EXT_MSG) >> 1); 6346 6347 if (ext_msg.msg_type == EXTENDED_MESSAGE && 6348 ext_msg.msg_req == EXTENDED_SDTR && 6349 ext_msg.msg_len == MS_SDTR_LEN) { 6350 sdtr_accept = true; 6351 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) { 6352 6353 sdtr_accept = false; 6354 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 6355 } 6356 if ((ext_msg.xfer_period < 6357 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index]) 6358 || (ext_msg.xfer_period > 6359 asc_dvc->sdtr_period_tbl[asc_dvc-> 6360 max_sdtr_index])) { 6361 sdtr_accept = false; 6362 ext_msg.xfer_period = 6363 asc_dvc->sdtr_period_tbl[asc_dvc-> 6364 min_sdtr_index]; 6365 } 6366 if (sdtr_accept) { 6367 sdtr_data = 6368 AscCalSDTRData(asc_dvc, ext_msg.xfer_period, 6369 ext_msg.req_ack_offset); 6370 if (sdtr_data == 0xFF) { 6371 6372 q_cntl |= QC_MSG_OUT; 6373 asc_dvc->init_sdtr &= ~target_id; 6374 asc_dvc->sdtr_done &= ~target_id; 6375 AscSetChipSDTR(iop_base, asyn_sdtr, 6376 tid_no); 6377 boardp->sdtr_data[tid_no] = asyn_sdtr; 6378 } 6379 } 6380 if (ext_msg.req_ack_offset == 0) { 6381 6382 q_cntl &= ~QC_MSG_OUT; 6383 asc_dvc->init_sdtr &= ~target_id; 6384 asc_dvc->sdtr_done &= ~target_id; 6385 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 6386 } else { 6387 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) { 6388 q_cntl &= ~QC_MSG_OUT; 6389 asc_dvc->sdtr_done |= target_id; 6390 asc_dvc->init_sdtr |= target_id; 6391 asc_dvc->pci_fix_asyn_xfer &= 6392 ~target_id; 6393 sdtr_data = 6394 AscCalSDTRData(asc_dvc, 6395 ext_msg.xfer_period, 6396 ext_msg. 6397 req_ack_offset); 6398 AscSetChipSDTR(iop_base, sdtr_data, 6399 tid_no); 6400 boardp->sdtr_data[tid_no] = sdtr_data; 6401 } else { 6402 q_cntl |= QC_MSG_OUT; 6403 AscMsgOutSDTR(asc_dvc, 6404 ext_msg.xfer_period, 6405 ext_msg.req_ack_offset); 6406 asc_dvc->pci_fix_asyn_xfer &= 6407 ~target_id; 6408 sdtr_data = 6409 AscCalSDTRData(asc_dvc, 6410 ext_msg.xfer_period, 6411 ext_msg. 6412 req_ack_offset); 6413 AscSetChipSDTR(iop_base, sdtr_data, 6414 tid_no); 6415 boardp->sdtr_data[tid_no] = sdtr_data; 6416 asc_dvc->sdtr_done |= target_id; 6417 asc_dvc->init_sdtr |= target_id; 6418 } 6419 } 6420 6421 AscWriteLramByte(iop_base, 6422 (ushort)(halt_q_addr + 6423 (ushort)ASC_SCSIQ_B_CNTL), 6424 q_cntl); 6425 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6426 return; 6427 } else if (ext_msg.msg_type == EXTENDED_MESSAGE && 6428 ext_msg.msg_req == EXTENDED_WDTR && 6429 ext_msg.msg_len == MS_WDTR_LEN) { 6430 6431 ext_msg.wdtr_width = 0; 6432 AscMemWordCopyPtrToLram(iop_base, 6433 ASCV_MSGOUT_BEG, 6434 (uchar *)&ext_msg, 6435 sizeof(EXT_MSG) >> 1); 6436 q_cntl |= QC_MSG_OUT; 6437 AscWriteLramByte(iop_base, 6438 (ushort)(halt_q_addr + 6439 (ushort)ASC_SCSIQ_B_CNTL), 6440 q_cntl); 6441 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6442 return; 6443 } else { 6444 6445 ext_msg.msg_type = MESSAGE_REJECT; 6446 AscMemWordCopyPtrToLram(iop_base, 6447 ASCV_MSGOUT_BEG, 6448 (uchar *)&ext_msg, 6449 sizeof(EXT_MSG) >> 1); 6450 q_cntl |= QC_MSG_OUT; 6451 AscWriteLramByte(iop_base, 6452 (ushort)(halt_q_addr + 6453 (ushort)ASC_SCSIQ_B_CNTL), 6454 q_cntl); 6455 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6456 return; 6457 } 6458 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 6459 6460 q_cntl |= QC_REQ_SENSE; 6461 6462 if ((asc_dvc->init_sdtr & target_id) != 0) { 6463 6464 asc_dvc->sdtr_done &= ~target_id; 6465 6466 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 6467 q_cntl |= QC_MSG_OUT; 6468 AscMsgOutSDTR(asc_dvc, 6469 asc_dvc-> 6470 sdtr_period_tbl[(sdtr_data >> 4) & 6471 (uchar)(asc_dvc-> 6472 max_sdtr_index - 6473 1)], 6474 (uchar)(sdtr_data & (uchar) 6475 ASC_SYN_MAX_OFFSET)); 6476 } 6477 6478 AscWriteLramByte(iop_base, 6479 (ushort)(halt_q_addr + 6480 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); 6481 6482 tag_code = AscReadLramByte(iop_base, 6483 (ushort)(halt_q_addr + (ushort) 6484 ASC_SCSIQ_B_TAG_CODE)); 6485 tag_code &= 0xDC; 6486 if ((asc_dvc->pci_fix_asyn_xfer & target_id) 6487 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id) 6488 ) { 6489 6490 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT 6491 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 6492 6493 } 6494 AscWriteLramByte(iop_base, 6495 (ushort)(halt_q_addr + 6496 (ushort)ASC_SCSIQ_B_TAG_CODE), 6497 tag_code); 6498 6499 q_status = AscReadLramByte(iop_base, 6500 (ushort)(halt_q_addr + (ushort) 6501 ASC_SCSIQ_B_STATUS)); 6502 q_status |= (QS_READY | QS_BUSY); 6503 AscWriteLramByte(iop_base, 6504 (ushort)(halt_q_addr + 6505 (ushort)ASC_SCSIQ_B_STATUS), 6506 q_status); 6507 6508 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B); 6509 scsi_busy &= ~target_id; 6510 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy); 6511 6512 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6513 return; 6514 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 6515 6516 AscMemWordCopyPtrFromLram(iop_base, 6517 ASCV_MSGOUT_BEG, 6518 (uchar *)&out_msg, 6519 sizeof(EXT_MSG) >> 1); 6520 6521 if ((out_msg.msg_type == EXTENDED_MESSAGE) && 6522 (out_msg.msg_len == MS_SDTR_LEN) && 6523 (out_msg.msg_req == EXTENDED_SDTR)) { 6524 6525 asc_dvc->init_sdtr &= ~target_id; 6526 asc_dvc->sdtr_done &= ~target_id; 6527 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 6528 boardp->sdtr_data[tid_no] = asyn_sdtr; 6529 } 6530 q_cntl &= ~QC_MSG_OUT; 6531 AscWriteLramByte(iop_base, 6532 (ushort)(halt_q_addr + 6533 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); 6534 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6535 return; 6536 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 6537 6538 scsi_status = AscReadLramByte(iop_base, 6539 (ushort)((ushort)halt_q_addr + 6540 (ushort) 6541 ASC_SCSIQ_SCSI_STATUS)); 6542 cur_dvc_qng = 6543 AscReadLramByte(iop_base, 6544 (ushort)((ushort)ASC_QADR_BEG + 6545 (ushort)target_ix)); 6546 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) { 6547 6548 scsi_busy = AscReadLramByte(iop_base, 6549 (ushort)ASCV_SCSIBUSY_B); 6550 scsi_busy |= target_id; 6551 AscWriteLramByte(iop_base, 6552 (ushort)ASCV_SCSIBUSY_B, scsi_busy); 6553 asc_dvc->queue_full_or_busy |= target_id; 6554 6555 if (scsi_status == SAM_STAT_TASK_SET_FULL) { 6556 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 6557 cur_dvc_qng -= 1; 6558 asc_dvc->max_dvc_qng[tid_no] = 6559 cur_dvc_qng; 6560 6561 AscWriteLramByte(iop_base, 6562 (ushort)((ushort) 6563 ASCV_MAX_DVC_QNG_BEG 6564 + (ushort) 6565 tid_no), 6566 cur_dvc_qng); 6567 6568 /* 6569 * Set the device queue depth to the 6570 * number of active requests when the 6571 * QUEUE FULL condition was encountered. 6572 */ 6573 boardp->queue_full |= target_id; 6574 boardp->queue_full_cnt[tid_no] = 6575 cur_dvc_qng; 6576 } 6577 } 6578 } 6579 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 6580 return; 6581 } 6582 return; 6583 } 6584 6585 /* 6586 * void 6587 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) 6588 * 6589 * Calling/Exit State: 6590 * none 6591 * 6592 * Description: 6593 * Input an ASC_QDONE_INFO structure from the chip 6594 */ 6595 static void 6596 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) 6597 { 6598 int i; 6599 ushort word; 6600 6601 AscSetChipLramAddr(iop_base, s_addr); 6602 for (i = 0; i < 2 * words; i += 2) { 6603 if (i == 10) { 6604 continue; 6605 } 6606 word = inpw(iop_base + IOP_RAM_DATA); 6607 inbuf[i] = word & 0xff; 6608 inbuf[i + 1] = (word >> 8) & 0xff; 6609 } 6610 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words); 6611 } 6612 6613 static uchar 6614 _AscCopyLramScsiDoneQ(PortAddr iop_base, 6615 ushort q_addr, 6616 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count) 6617 { 6618 ushort _val; 6619 uchar sg_queue_cnt; 6620 6621 DvcGetQinfo(iop_base, 6622 q_addr + ASC_SCSIQ_DONE_INFO_BEG, 6623 (uchar *)scsiq, 6624 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2); 6625 6626 _val = AscReadLramWord(iop_base, 6627 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS)); 6628 scsiq->q_status = (uchar)_val; 6629 scsiq->q_no = (uchar)(_val >> 8); 6630 _val = AscReadLramWord(iop_base, 6631 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL)); 6632 scsiq->cntl = (uchar)_val; 6633 sg_queue_cnt = (uchar)(_val >> 8); 6634 _val = AscReadLramWord(iop_base, 6635 (ushort)(q_addr + 6636 (ushort)ASC_SCSIQ_B_SENSE_LEN)); 6637 scsiq->sense_len = (uchar)_val; 6638 scsiq->extra_bytes = (uchar)(_val >> 8); 6639 6640 /* 6641 * Read high word of remain bytes from alternate location. 6642 */ 6643 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base, 6644 (ushort)(q_addr + 6645 (ushort) 6646 ASC_SCSIQ_W_ALT_DC1))) 6647 << 16); 6648 /* 6649 * Read low word of remain bytes from original location. 6650 */ 6651 scsiq->remain_bytes += AscReadLramWord(iop_base, 6652 (ushort)(q_addr + (ushort) 6653 ASC_SCSIQ_DW_REMAIN_XFER_CNT)); 6654 6655 scsiq->remain_bytes &= max_dma_count; 6656 return sg_queue_cnt; 6657 } 6658 6659 /* 6660 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR(). 6661 * 6662 * Interrupt callback function for the Narrow SCSI Asc Library. 6663 */ 6664 static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep) 6665 { 6666 struct asc_board *boardp = asc_dvc_varp->drv_ptr; 6667 u32 srb_tag; 6668 struct scsi_cmnd *scp; 6669 6670 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep); 6671 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep); 6672 6673 /* 6674 * Decrease the srb_tag by 1 to find the SCSI command 6675 */ 6676 srb_tag = qdonep->d2.srb_tag - 1; 6677 scp = scsi_host_find_tag(boardp->shost, srb_tag); 6678 if (!scp) 6679 return; 6680 6681 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); 6682 6683 ASC_STATS(boardp->shost, callback); 6684 6685 dma_unmap_single(boardp->dev, scp->SCp.dma_handle, 6686 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 6687 /* 6688 * 'qdonep' contains the command's ending status. 6689 */ 6690 scp->result = 0; 6691 switch (qdonep->d3.done_stat) { 6692 case QD_NO_ERROR: 6693 ASC_DBG(2, "QD_NO_ERROR\n"); 6694 6695 /* 6696 * Check for an underrun condition. 6697 * 6698 * If there was no error and an underrun condition, then 6699 * return the number of underrun bytes. 6700 */ 6701 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 && 6702 qdonep->remain_bytes <= scsi_bufflen(scp)) { 6703 ASC_DBG(1, "underrun condition %u bytes\n", 6704 (unsigned)qdonep->remain_bytes); 6705 scsi_set_resid(scp, qdonep->remain_bytes); 6706 } 6707 break; 6708 6709 case QD_WITH_ERROR: 6710 ASC_DBG(2, "QD_WITH_ERROR\n"); 6711 switch (qdonep->d3.host_stat) { 6712 case QHSTA_NO_ERROR: 6713 set_status_byte(scp, qdonep->d3.scsi_stat); 6714 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) { 6715 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n"); 6716 ASC_DBG_PRT_SENSE(2, scp->sense_buffer, 6717 SCSI_SENSE_BUFFERSIZE); 6718 set_driver_byte(scp, DRIVER_SENSE); 6719 } 6720 break; 6721 6722 default: 6723 /* QHSTA error occurred */ 6724 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat); 6725 set_host_byte(scp, DID_BAD_TARGET); 6726 break; 6727 } 6728 break; 6729 6730 case QD_ABORTED_BY_HOST: 6731 ASC_DBG(1, "QD_ABORTED_BY_HOST\n"); 6732 set_status_byte(scp, qdonep->d3.scsi_stat); 6733 set_msg_byte(scp, qdonep->d3.scsi_msg); 6734 set_host_byte(scp, DID_ABORT); 6735 break; 6736 6737 default: 6738 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat); 6739 set_status_byte(scp, qdonep->d3.scsi_stat); 6740 set_msg_byte(scp, qdonep->d3.scsi_msg); 6741 set_host_byte(scp, DID_ERROR); 6742 break; 6743 } 6744 6745 /* 6746 * If the 'init_tidmask' bit isn't already set for the target and the 6747 * current request finished normally, then set the bit for the target 6748 * to indicate that a device is present. 6749 */ 6750 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && 6751 qdonep->d3.done_stat == QD_NO_ERROR && 6752 qdonep->d3.host_stat == QHSTA_NO_ERROR) { 6753 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); 6754 } 6755 6756 asc_scsi_done(scp); 6757 } 6758 6759 static int AscIsrQDone(ASC_DVC_VAR *asc_dvc) 6760 { 6761 uchar next_qp; 6762 uchar n_q_used; 6763 uchar sg_list_qp; 6764 uchar sg_queue_cnt; 6765 uchar q_cnt; 6766 uchar done_q_tail; 6767 uchar tid_no; 6768 ASC_SCSI_BIT_ID_TYPE scsi_busy; 6769 ASC_SCSI_BIT_ID_TYPE target_id; 6770 PortAddr iop_base; 6771 ushort q_addr; 6772 ushort sg_q_addr; 6773 uchar cur_target_qng; 6774 ASC_QDONE_INFO scsiq_buf; 6775 ASC_QDONE_INFO *scsiq; 6776 bool false_overrun; 6777 6778 iop_base = asc_dvc->iop_base; 6779 n_q_used = 1; 6780 scsiq = (ASC_QDONE_INFO *)&scsiq_buf; 6781 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base); 6782 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 6783 next_qp = AscReadLramByte(iop_base, 6784 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD)); 6785 if (next_qp != ASC_QLINK_END) { 6786 AscPutVarDoneQTail(iop_base, next_qp); 6787 q_addr = ASC_QNO_TO_QADDR(next_qp); 6788 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq, 6789 asc_dvc->max_dma_count); 6790 AscWriteLramByte(iop_base, 6791 (ushort)(q_addr + 6792 (ushort)ASC_SCSIQ_B_STATUS), 6793 (uchar)(scsiq-> 6794 q_status & (uchar)~(QS_READY | 6795 QS_ABORTED))); 6796 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 6797 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 6798 if ((scsiq->cntl & QC_SG_HEAD) != 0) { 6799 sg_q_addr = q_addr; 6800 sg_list_qp = next_qp; 6801 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 6802 sg_list_qp = AscReadLramByte(iop_base, 6803 (ushort)(sg_q_addr 6804 + (ushort) 6805 ASC_SCSIQ_B_FWD)); 6806 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 6807 if (sg_list_qp == ASC_QLINK_END) { 6808 AscSetLibErrorCode(asc_dvc, 6809 ASCQ_ERR_SG_Q_LINKS); 6810 scsiq->d3.done_stat = QD_WITH_ERROR; 6811 scsiq->d3.host_stat = 6812 QHSTA_D_QDONE_SG_LIST_CORRUPTED; 6813 goto FATAL_ERR_QDONE; 6814 } 6815 AscWriteLramByte(iop_base, 6816 (ushort)(sg_q_addr + (ushort) 6817 ASC_SCSIQ_B_STATUS), 6818 QS_FREE); 6819 } 6820 n_q_used = sg_queue_cnt + 1; 6821 AscPutVarDoneQTail(iop_base, sg_list_qp); 6822 } 6823 if (asc_dvc->queue_full_or_busy & target_id) { 6824 cur_target_qng = AscReadLramByte(iop_base, 6825 (ushort)((ushort) 6826 ASC_QADR_BEG 6827 + (ushort) 6828 scsiq->d2. 6829 target_ix)); 6830 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) { 6831 scsi_busy = AscReadLramByte(iop_base, (ushort) 6832 ASCV_SCSIBUSY_B); 6833 scsi_busy &= ~target_id; 6834 AscWriteLramByte(iop_base, 6835 (ushort)ASCV_SCSIBUSY_B, 6836 scsi_busy); 6837 asc_dvc->queue_full_or_busy &= ~target_id; 6838 } 6839 } 6840 if (asc_dvc->cur_total_qng >= n_q_used) { 6841 asc_dvc->cur_total_qng -= n_q_used; 6842 if (asc_dvc->cur_dvc_qng[tid_no] != 0) { 6843 asc_dvc->cur_dvc_qng[tid_no]--; 6844 } 6845 } else { 6846 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG); 6847 scsiq->d3.done_stat = QD_WITH_ERROR; 6848 goto FATAL_ERR_QDONE; 6849 } 6850 if ((scsiq->d2.srb_tag == 0UL) || 6851 ((scsiq->q_status & QS_ABORTED) != 0)) { 6852 return (0x11); 6853 } else if (scsiq->q_status == QS_DONE) { 6854 /* 6855 * This is also curious. 6856 * false_overrun will _always_ be set to 'false' 6857 */ 6858 false_overrun = false; 6859 if (scsiq->extra_bytes != 0) { 6860 scsiq->remain_bytes += scsiq->extra_bytes; 6861 } 6862 if (scsiq->d3.done_stat == QD_WITH_ERROR) { 6863 if (scsiq->d3.host_stat == 6864 QHSTA_M_DATA_OVER_RUN) { 6865 if ((scsiq-> 6866 cntl & (QC_DATA_IN | QC_DATA_OUT)) 6867 == 0) { 6868 scsiq->d3.done_stat = 6869 QD_NO_ERROR; 6870 scsiq->d3.host_stat = 6871 QHSTA_NO_ERROR; 6872 } else if (false_overrun) { 6873 scsiq->d3.done_stat = 6874 QD_NO_ERROR; 6875 scsiq->d3.host_stat = 6876 QHSTA_NO_ERROR; 6877 } 6878 } else if (scsiq->d3.host_stat == 6879 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 6880 AscStopChip(iop_base); 6881 AscSetChipControl(iop_base, 6882 (uchar)(CC_SCSI_RESET 6883 | CC_HALT)); 6884 udelay(60); 6885 AscSetChipControl(iop_base, CC_HALT); 6886 AscSetChipStatus(iop_base, 6887 CIW_CLR_SCSI_RESET_INT); 6888 AscSetChipStatus(iop_base, 0); 6889 AscSetChipControl(iop_base, 0); 6890 } 6891 } 6892 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { 6893 asc_isr_callback(asc_dvc, scsiq); 6894 } else { 6895 if ((AscReadLramByte(iop_base, 6896 (ushort)(q_addr + (ushort) 6897 ASC_SCSIQ_CDB_BEG)) 6898 == START_STOP)) { 6899 asc_dvc->unit_not_ready &= ~target_id; 6900 if (scsiq->d3.done_stat != QD_NO_ERROR) { 6901 asc_dvc->start_motor &= 6902 ~target_id; 6903 } 6904 } 6905 } 6906 return (1); 6907 } else { 6908 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS); 6909 FATAL_ERR_QDONE: 6910 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { 6911 asc_isr_callback(asc_dvc, scsiq); 6912 } 6913 return (0x80); 6914 } 6915 } 6916 return (0); 6917 } 6918 6919 static int AscISR(ASC_DVC_VAR *asc_dvc) 6920 { 6921 ASC_CS_TYPE chipstat; 6922 PortAddr iop_base; 6923 ushort saved_ram_addr; 6924 uchar ctrl_reg; 6925 uchar saved_ctrl_reg; 6926 int int_pending; 6927 int status; 6928 uchar host_flag; 6929 6930 iop_base = asc_dvc->iop_base; 6931 int_pending = ASC_FALSE; 6932 6933 if (AscIsIntPending(iop_base) == 0) 6934 return int_pending; 6935 6936 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) { 6937 return ASC_ERROR; 6938 } 6939 if (asc_dvc->in_critical_cnt != 0) { 6940 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL); 6941 return ASC_ERROR; 6942 } 6943 if (asc_dvc->is_in_int) { 6944 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY); 6945 return ASC_ERROR; 6946 } 6947 asc_dvc->is_in_int = true; 6948 ctrl_reg = AscGetChipControl(iop_base); 6949 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET | 6950 CC_SINGLE_STEP | CC_DIAG | CC_TEST)); 6951 chipstat = AscGetChipStatus(iop_base); 6952 if (chipstat & CSW_SCSI_RESET_LATCH) { 6953 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 6954 int i = 10; 6955 int_pending = ASC_TRUE; 6956 asc_dvc->sdtr_done = 0; 6957 saved_ctrl_reg &= (uchar)(~CC_HALT); 6958 while ((AscGetChipStatus(iop_base) & 6959 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) { 6960 mdelay(100); 6961 } 6962 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT)); 6963 AscSetChipControl(iop_base, CC_HALT); 6964 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); 6965 AscSetChipStatus(iop_base, 0); 6966 chipstat = AscGetChipStatus(iop_base); 6967 } 6968 } 6969 saved_ram_addr = AscGetChipLramAddr(iop_base); 6970 host_flag = AscReadLramByte(iop_base, 6971 ASCV_HOST_FLAG_B) & 6972 (uchar)(~ASC_HOST_FLAG_IN_ISR); 6973 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, 6974 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR)); 6975 if ((chipstat & CSW_INT_PENDING) || (int_pending)) { 6976 AscAckInterrupt(iop_base); 6977 int_pending = ASC_TRUE; 6978 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) { 6979 AscIsrChipHalted(asc_dvc); 6980 saved_ctrl_reg &= (uchar)(~CC_HALT); 6981 } else { 6982 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) { 6983 while (((status = 6984 AscIsrQDone(asc_dvc)) & 0x01) != 0) { 6985 } 6986 } else { 6987 do { 6988 if ((status = 6989 AscIsrQDone(asc_dvc)) == 1) { 6990 break; 6991 } 6992 } while (status == 0x11); 6993 } 6994 if ((status & 0x80) != 0) 6995 int_pending = ASC_ERROR; 6996 } 6997 } 6998 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); 6999 AscSetChipLramAddr(iop_base, saved_ram_addr); 7000 AscSetChipControl(iop_base, saved_ctrl_reg); 7001 asc_dvc->is_in_int = false; 7002 return int_pending; 7003 } 7004 7005 /* 7006 * advansys_reset() 7007 * 7008 * Reset the host associated with the command 'scp'. 7009 * 7010 * This function runs its own thread. Interrupts must be blocked but 7011 * sleeping is allowed and no locking other than for host structures is 7012 * required. Returns SUCCESS or FAILED. 7013 */ 7014 static int advansys_reset(struct scsi_cmnd *scp) 7015 { 7016 struct Scsi_Host *shost = scp->device->host; 7017 struct asc_board *boardp = shost_priv(shost); 7018 unsigned long flags; 7019 int status; 7020 int ret = SUCCESS; 7021 7022 ASC_DBG(1, "0x%p\n", scp); 7023 7024 ASC_STATS(shost, reset); 7025 7026 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n"); 7027 7028 if (ASC_NARROW_BOARD(boardp)) { 7029 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; 7030 7031 /* Reset the chip and SCSI bus. */ 7032 ASC_DBG(1, "before AscInitAsc1000Driver()\n"); 7033 status = AscInitAsc1000Driver(asc_dvc); 7034 7035 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */ 7036 if (asc_dvc->err_code || !asc_dvc->overrun_dma) { 7037 scmd_printk(KERN_INFO, scp, "SCSI host reset error: " 7038 "0x%x, status: 0x%x\n", asc_dvc->err_code, 7039 status); 7040 ret = FAILED; 7041 } else if (status) { 7042 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: " 7043 "0x%x\n", status); 7044 } else { 7045 scmd_printk(KERN_INFO, scp, "SCSI host reset " 7046 "successful\n"); 7047 } 7048 7049 ASC_DBG(1, "after AscInitAsc1000Driver()\n"); 7050 } else { 7051 /* 7052 * If the suggest reset bus flags are set, then reset the bus. 7053 * Otherwise only reset the device. 7054 */ 7055 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var; 7056 7057 /* 7058 * Reset the chip and SCSI bus. 7059 */ 7060 ASC_DBG(1, "before AdvResetChipAndSB()\n"); 7061 switch (AdvResetChipAndSB(adv_dvc)) { 7062 case ASC_TRUE: 7063 scmd_printk(KERN_INFO, scp, "SCSI host reset " 7064 "successful\n"); 7065 break; 7066 case ASC_FALSE: 7067 default: 7068 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n"); 7069 ret = FAILED; 7070 break; 7071 } 7072 spin_lock_irqsave(shost->host_lock, flags); 7073 AdvISR(adv_dvc); 7074 spin_unlock_irqrestore(shost->host_lock, flags); 7075 } 7076 7077 ASC_DBG(1, "ret %d\n", ret); 7078 7079 return ret; 7080 } 7081 7082 /* 7083 * advansys_biosparam() 7084 * 7085 * Translate disk drive geometry if the "BIOS greater than 1 GB" 7086 * support is enabled for a drive. 7087 * 7088 * ip (information pointer) is an int array with the following definition: 7089 * ip[0]: heads 7090 * ip[1]: sectors 7091 * ip[2]: cylinders 7092 */ 7093 static int 7094 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev, 7095 sector_t capacity, int ip[]) 7096 { 7097 struct asc_board *boardp = shost_priv(sdev->host); 7098 7099 ASC_DBG(1, "begin\n"); 7100 ASC_STATS(sdev->host, biosparam); 7101 if (ASC_NARROW_BOARD(boardp)) { 7102 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl & 7103 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) { 7104 ip[0] = 255; 7105 ip[1] = 63; 7106 } else { 7107 ip[0] = 64; 7108 ip[1] = 32; 7109 } 7110 } else { 7111 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl & 7112 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) { 7113 ip[0] = 255; 7114 ip[1] = 63; 7115 } else { 7116 ip[0] = 64; 7117 ip[1] = 32; 7118 } 7119 } 7120 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]); 7121 ASC_DBG(1, "end\n"); 7122 return 0; 7123 } 7124 7125 /* 7126 * First-level interrupt handler. 7127 * 7128 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host. 7129 */ 7130 static irqreturn_t advansys_interrupt(int irq, void *dev_id) 7131 { 7132 struct Scsi_Host *shost = dev_id; 7133 struct asc_board *boardp = shost_priv(shost); 7134 irqreturn_t result = IRQ_NONE; 7135 unsigned long flags; 7136 7137 ASC_DBG(2, "boardp 0x%p\n", boardp); 7138 spin_lock_irqsave(shost->host_lock, flags); 7139 if (ASC_NARROW_BOARD(boardp)) { 7140 if (AscIsIntPending(shost->io_port)) { 7141 result = IRQ_HANDLED; 7142 ASC_STATS(shost, interrupt); 7143 ASC_DBG(1, "before AscISR()\n"); 7144 AscISR(&boardp->dvc_var.asc_dvc_var); 7145 } 7146 } else { 7147 ASC_DBG(1, "before AdvISR()\n"); 7148 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) { 7149 result = IRQ_HANDLED; 7150 ASC_STATS(shost, interrupt); 7151 } 7152 } 7153 spin_unlock_irqrestore(shost->host_lock, flags); 7154 7155 ASC_DBG(1, "end\n"); 7156 return result; 7157 } 7158 7159 static bool AscHostReqRiscHalt(PortAddr iop_base) 7160 { 7161 int count = 0; 7162 bool sta = false; 7163 uchar saved_stop_code; 7164 7165 if (AscIsChipHalted(iop_base)) 7166 return true; 7167 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B); 7168 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 7169 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 7170 do { 7171 if (AscIsChipHalted(iop_base)) { 7172 sta = true; 7173 break; 7174 } 7175 mdelay(100); 7176 } while (count++ < 20); 7177 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code); 7178 return sta; 7179 } 7180 7181 static bool 7182 AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data) 7183 { 7184 bool sta = false; 7185 7186 if (AscHostReqRiscHalt(iop_base)) { 7187 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); 7188 AscStartChip(iop_base); 7189 } 7190 return sta; 7191 } 7192 7193 static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev) 7194 { 7195 char type = sdev->type; 7196 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id; 7197 7198 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)) 7199 return; 7200 if (asc_dvc->init_sdtr & tid_bits) 7201 return; 7202 7203 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0)) 7204 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits; 7205 7206 asc_dvc->pci_fix_asyn_xfer |= tid_bits; 7207 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) || 7208 (type == TYPE_ROM) || (type == TYPE_TAPE)) 7209 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits; 7210 7211 if (asc_dvc->pci_fix_asyn_xfer & tid_bits) 7212 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id, 7213 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 7214 } 7215 7216 static void 7217 advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc) 7218 { 7219 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id; 7220 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng; 7221 7222 if (sdev->lun == 0) { 7223 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr; 7224 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) { 7225 asc_dvc->init_sdtr |= tid_bit; 7226 } else { 7227 asc_dvc->init_sdtr &= ~tid_bit; 7228 } 7229 7230 if (orig_init_sdtr != asc_dvc->init_sdtr) 7231 AscAsyncFix(asc_dvc, sdev); 7232 } 7233 7234 if (sdev->tagged_supported) { 7235 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) { 7236 if (sdev->lun == 0) { 7237 asc_dvc->cfg->can_tagged_qng |= tid_bit; 7238 asc_dvc->use_tagged_qng |= tid_bit; 7239 } 7240 scsi_change_queue_depth(sdev, 7241 asc_dvc->max_dvc_qng[sdev->id]); 7242 } 7243 } else { 7244 if (sdev->lun == 0) { 7245 asc_dvc->cfg->can_tagged_qng &= ~tid_bit; 7246 asc_dvc->use_tagged_qng &= ~tid_bit; 7247 } 7248 } 7249 7250 if ((sdev->lun == 0) && 7251 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) { 7252 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B, 7253 asc_dvc->cfg->disc_enable); 7254 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B, 7255 asc_dvc->use_tagged_qng); 7256 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B, 7257 asc_dvc->cfg->can_tagged_qng); 7258 7259 asc_dvc->max_dvc_qng[sdev->id] = 7260 asc_dvc->cfg->max_tag_qng[sdev->id]; 7261 AscWriteLramByte(asc_dvc->iop_base, 7262 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id), 7263 asc_dvc->max_dvc_qng[sdev->id]); 7264 } 7265 } 7266 7267 /* 7268 * Wide Transfers 7269 * 7270 * If the EEPROM enabled WDTR for the device and the device supports wide 7271 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and 7272 * write the new value to the microcode. 7273 */ 7274 static void 7275 advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask) 7276 { 7277 unsigned short cfg_word; 7278 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); 7279 if ((cfg_word & tidmask) != 0) 7280 return; 7281 7282 cfg_word |= tidmask; 7283 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); 7284 7285 /* 7286 * Clear the microcode SDTR and WDTR negotiation done indicators for 7287 * the target to cause it to negotiate with the new setting set above. 7288 * WDTR when accepted causes the target to enter asynchronous mode, so 7289 * SDTR must be negotiated. 7290 */ 7291 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7292 cfg_word &= ~tidmask; 7293 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7294 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); 7295 cfg_word &= ~tidmask; 7296 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); 7297 } 7298 7299 /* 7300 * Synchronous Transfers 7301 * 7302 * If the EEPROM enabled SDTR for the device and the device 7303 * supports synchronous transfers, then turn on the device's 7304 * 'sdtr_able' bit. Write the new value to the microcode. 7305 */ 7306 static void 7307 advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask) 7308 { 7309 unsigned short cfg_word; 7310 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); 7311 if ((cfg_word & tidmask) != 0) 7312 return; 7313 7314 cfg_word |= tidmask; 7315 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); 7316 7317 /* 7318 * Clear the microcode "SDTR negotiation" done indicator for the 7319 * target to cause it to negotiate with the new setting set above. 7320 */ 7321 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7322 cfg_word &= ~tidmask; 7323 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 7324 } 7325 7326 /* 7327 * PPR (Parallel Protocol Request) Capable 7328 * 7329 * If the device supports DT mode, then it must be PPR capable. 7330 * The PPR message will be used in place of the SDTR and WDTR 7331 * messages to negotiate synchronous speed and offset, transfer 7332 * width, and protocol options. 7333 */ 7334 static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc, 7335 AdvPortAddr iop_base, unsigned short tidmask) 7336 { 7337 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); 7338 adv_dvc->ppr_able |= tidmask; 7339 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); 7340 } 7341 7342 static void 7343 advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc) 7344 { 7345 AdvPortAddr iop_base = adv_dvc->iop_base; 7346 unsigned short tidmask = 1 << sdev->id; 7347 7348 if (sdev->lun == 0) { 7349 /* 7350 * Handle WDTR, SDTR, and Tag Queuing. If the feature 7351 * is enabled in the EEPROM and the device supports the 7352 * feature, then enable it in the microcode. 7353 */ 7354 7355 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr) 7356 advansys_wide_enable_wdtr(iop_base, tidmask); 7357 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr) 7358 advansys_wide_enable_sdtr(iop_base, tidmask); 7359 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr) 7360 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask); 7361 7362 /* 7363 * Tag Queuing is disabled for the BIOS which runs in polled 7364 * mode and would see no benefit from Tag Queuing. Also by 7365 * disabling Tag Queuing in the BIOS devices with Tag Queuing 7366 * bugs will at least work with the BIOS. 7367 */ 7368 if ((adv_dvc->tagqng_able & tidmask) && 7369 sdev->tagged_supported) { 7370 unsigned short cfg_word; 7371 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word); 7372 cfg_word |= tidmask; 7373 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 7374 cfg_word); 7375 AdvWriteByteLram(iop_base, 7376 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id, 7377 adv_dvc->max_dvc_qng); 7378 } 7379 } 7380 7381 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) 7382 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng); 7383 } 7384 7385 /* 7386 * Set the number of commands to queue per device for the 7387 * specified host adapter. 7388 */ 7389 static int advansys_slave_configure(struct scsi_device *sdev) 7390 { 7391 struct asc_board *boardp = shost_priv(sdev->host); 7392 7393 if (ASC_NARROW_BOARD(boardp)) 7394 advansys_narrow_slave_configure(sdev, 7395 &boardp->dvc_var.asc_dvc_var); 7396 else 7397 advansys_wide_slave_configure(sdev, 7398 &boardp->dvc_var.adv_dvc_var); 7399 7400 return 0; 7401 } 7402 7403 static __le32 asc_get_sense_buffer_dma(struct scsi_cmnd *scp) 7404 { 7405 struct asc_board *board = shost_priv(scp->device->host); 7406 7407 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer, 7408 SCSI_SENSE_BUFFERSIZE, 7409 DMA_FROM_DEVICE); 7410 if (dma_mapping_error(board->dev, scp->SCp.dma_handle)) { 7411 ASC_DBG(1, "failed to map sense buffer\n"); 7412 return 0; 7413 } 7414 return cpu_to_le32(scp->SCp.dma_handle); 7415 } 7416 7417 static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, 7418 struct asc_scsi_q *asc_scsi_q) 7419 { 7420 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var; 7421 int use_sg; 7422 u32 srb_tag; 7423 7424 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q)); 7425 7426 /* 7427 * Set the srb_tag to the command tag + 1, as 7428 * srb_tag '0' is used internally by the chip. 7429 */ 7430 srb_tag = scp->request->tag + 1; 7431 asc_scsi_q->q2.srb_tag = srb_tag; 7432 7433 /* 7434 * Build the ASC_SCSI_Q request. 7435 */ 7436 asc_scsi_q->cdbptr = &scp->cmnd[0]; 7437 asc_scsi_q->q2.cdb_len = scp->cmd_len; 7438 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id); 7439 asc_scsi_q->q1.target_lun = scp->device->lun; 7440 asc_scsi_q->q2.target_ix = 7441 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun); 7442 asc_scsi_q->q1.sense_addr = asc_get_sense_buffer_dma(scp); 7443 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE; 7444 if (!asc_scsi_q->q1.sense_addr) 7445 return ASC_BUSY; 7446 7447 /* 7448 * If there are any outstanding requests for the current target, 7449 * then every 255th request send an ORDERED request. This heuristic 7450 * tries to retain the benefit of request sorting while preventing 7451 * request starvation. 255 is the max number of tags or pending commands 7452 * a device may have outstanding. 7453 * 7454 * The request count is incremented below for every successfully 7455 * started request. 7456 * 7457 */ 7458 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) && 7459 (boardp->reqcnt[scp->device->id] % 255) == 0) { 7460 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG; 7461 } else { 7462 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG; 7463 } 7464 7465 /* Build ASC_SCSI_Q */ 7466 use_sg = scsi_dma_map(scp); 7467 if (use_sg < 0) { 7468 ASC_DBG(1, "failed to map sglist\n"); 7469 return ASC_BUSY; 7470 } else if (use_sg > 0) { 7471 int sgcnt; 7472 struct scatterlist *slp; 7473 struct asc_sg_head *asc_sg_head; 7474 7475 if (use_sg > scp->device->host->sg_tablesize) { 7476 scmd_printk(KERN_ERR, scp, "use_sg %d > " 7477 "sg_tablesize %d\n", use_sg, 7478 scp->device->host->sg_tablesize); 7479 scsi_dma_unmap(scp); 7480 set_host_byte(scp, DID_ERROR); 7481 return ASC_ERROR; 7482 } 7483 7484 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) + 7485 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC); 7486 if (!asc_sg_head) { 7487 scsi_dma_unmap(scp); 7488 set_host_byte(scp, DID_SOFT_ERROR); 7489 return ASC_ERROR; 7490 } 7491 7492 asc_scsi_q->q1.cntl |= QC_SG_HEAD; 7493 asc_scsi_q->sg_head = asc_sg_head; 7494 asc_scsi_q->q1.data_cnt = 0; 7495 asc_scsi_q->q1.data_addr = 0; 7496 /* This is a byte value, otherwise it would need to be swapped. */ 7497 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg; 7498 ASC_STATS_ADD(scp->device->host, xfer_elem, 7499 asc_sg_head->entry_cnt); 7500 7501 /* 7502 * Convert scatter-gather list into ASC_SG_HEAD list. 7503 */ 7504 scsi_for_each_sg(scp, slp, use_sg, sgcnt) { 7505 asc_sg_head->sg_list[sgcnt].addr = 7506 cpu_to_le32(sg_dma_address(slp)); 7507 asc_sg_head->sg_list[sgcnt].bytes = 7508 cpu_to_le32(sg_dma_len(slp)); 7509 ASC_STATS_ADD(scp->device->host, xfer_sect, 7510 DIV_ROUND_UP(sg_dma_len(slp), 512)); 7511 } 7512 } 7513 7514 ASC_STATS(scp->device->host, xfer_cnt); 7515 7516 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q); 7517 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); 7518 7519 return ASC_NOERROR; 7520 } 7521 7522 /* 7523 * Build scatter-gather list for Adv Library (Wide Board). 7524 * 7525 * Additional ADV_SG_BLOCK structures will need to be allocated 7526 * if the total number of scatter-gather elements exceeds 7527 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are 7528 * assumed to be physically contiguous. 7529 * 7530 * Return: 7531 * ADV_SUCCESS(1) - SG List successfully created 7532 * ADV_ERROR(-1) - SG List creation failed 7533 */ 7534 static int 7535 adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, 7536 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg) 7537 { 7538 adv_sgblk_t *sgblkp, *prev_sgblkp; 7539 struct scatterlist *slp; 7540 int sg_elem_cnt; 7541 ADV_SG_BLOCK *sg_block, *prev_sg_block; 7542 dma_addr_t sgblk_paddr; 7543 int i; 7544 7545 slp = scsi_sglist(scp); 7546 sg_elem_cnt = use_sg; 7547 prev_sgblkp = NULL; 7548 prev_sg_block = NULL; 7549 reqp->sgblkp = NULL; 7550 7551 for (;;) { 7552 /* 7553 * Allocate a 'adv_sgblk_t' structure from the board free 7554 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK 7555 * (15) scatter-gather elements. 7556 */ 7557 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC, 7558 &sgblk_paddr); 7559 if (!sgblkp) { 7560 ASC_DBG(1, "no free adv_sgblk_t\n"); 7561 ASC_STATS(scp->device->host, adv_build_nosg); 7562 7563 /* 7564 * Allocation failed. Free 'adv_sgblk_t' structures 7565 * already allocated for the request. 7566 */ 7567 while ((sgblkp = reqp->sgblkp) != NULL) { 7568 /* Remove 'sgblkp' from the request list. */ 7569 reqp->sgblkp = sgblkp->next_sgblkp; 7570 sgblkp->next_sgblkp = NULL; 7571 dma_pool_free(boardp->adv_sgblk_pool, sgblkp, 7572 sgblkp->sg_addr); 7573 } 7574 return ASC_BUSY; 7575 } 7576 /* Complete 'adv_sgblk_t' board allocation. */ 7577 sgblkp->sg_addr = sgblk_paddr; 7578 sgblkp->next_sgblkp = NULL; 7579 sg_block = &sgblkp->sg_block; 7580 7581 /* 7582 * Check if this is the first 'adv_sgblk_t' for the 7583 * request. 7584 */ 7585 if (reqp->sgblkp == NULL) { 7586 /* Request's first scatter-gather block. */ 7587 reqp->sgblkp = sgblkp; 7588 7589 /* 7590 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical 7591 * address pointers. 7592 */ 7593 scsiqp->sg_list_ptr = sg_block; 7594 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr); 7595 } else { 7596 /* Request's second or later scatter-gather block. */ 7597 prev_sgblkp->next_sgblkp = sgblkp; 7598 7599 /* 7600 * Point the previous ADV_SG_BLOCK structure to 7601 * the newly allocated ADV_SG_BLOCK structure. 7602 */ 7603 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr); 7604 } 7605 7606 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 7607 sg_block->sg_list[i].sg_addr = 7608 cpu_to_le32(sg_dma_address(slp)); 7609 sg_block->sg_list[i].sg_count = 7610 cpu_to_le32(sg_dma_len(slp)); 7611 ASC_STATS_ADD(scp->device->host, xfer_sect, 7612 DIV_ROUND_UP(sg_dma_len(slp), 512)); 7613 7614 if (--sg_elem_cnt == 0) { 7615 /* 7616 * Last ADV_SG_BLOCK and scatter-gather entry. 7617 */ 7618 sg_block->sg_cnt = i + 1; 7619 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */ 7620 return ADV_SUCCESS; 7621 } 7622 slp = sg_next(slp); 7623 } 7624 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 7625 prev_sg_block = sg_block; 7626 prev_sgblkp = sgblkp; 7627 } 7628 } 7629 7630 /* 7631 * Build a request structure for the Adv Library (Wide Board). 7632 * 7633 * If an adv_req_t can not be allocated to issue the request, 7634 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR. 7635 * 7636 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the 7637 * microcode for DMA addresses or math operations are byte swapped 7638 * to little-endian order. 7639 */ 7640 static int 7641 adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, 7642 adv_req_t **adv_reqpp) 7643 { 7644 u32 srb_tag = scp->request->tag; 7645 adv_req_t *reqp; 7646 ADV_SCSI_REQ_Q *scsiqp; 7647 int ret; 7648 int use_sg; 7649 dma_addr_t sense_addr; 7650 7651 /* 7652 * Allocate an adv_req_t structure from the board to execute 7653 * the command. 7654 */ 7655 reqp = &boardp->adv_reqp[srb_tag]; 7656 if (reqp->cmndp && reqp->cmndp != scp ) { 7657 ASC_DBG(1, "no free adv_req_t\n"); 7658 ASC_STATS(scp->device->host, adv_build_noreq); 7659 return ASC_BUSY; 7660 } 7661 7662 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t)); 7663 7664 scsiqp = &reqp->scsi_req_q; 7665 7666 /* 7667 * Initialize the structure. 7668 */ 7669 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0; 7670 7671 /* 7672 * Set the srb_tag to the command tag. 7673 */ 7674 scsiqp->srb_tag = srb_tag; 7675 7676 /* 7677 * Set 'host_scribble' to point to the adv_req_t structure. 7678 */ 7679 reqp->cmndp = scp; 7680 scp->host_scribble = (void *)reqp; 7681 7682 /* 7683 * Build the ADV_SCSI_REQ_Q request. 7684 */ 7685 7686 /* Set CDB length and copy it to the request structure. */ 7687 scsiqp->cdb_len = scp->cmd_len; 7688 /* Copy first 12 CDB bytes to cdb[]. */ 7689 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12); 7690 /* Copy last 4 CDB bytes, if present, to cdb16[]. */ 7691 if (scp->cmd_len > 12) { 7692 int cdb16_len = scp->cmd_len - 12; 7693 7694 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len); 7695 } 7696 7697 scsiqp->target_id = scp->device->id; 7698 scsiqp->target_lun = scp->device->lun; 7699 7700 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer, 7701 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 7702 if (dma_mapping_error(boardp->dev, sense_addr)) { 7703 ASC_DBG(1, "failed to map sense buffer\n"); 7704 ASC_STATS(scp->device->host, adv_build_noreq); 7705 return ASC_BUSY; 7706 } 7707 scsiqp->sense_addr = cpu_to_le32(sense_addr); 7708 scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE; 7709 7710 /* Build ADV_SCSI_REQ_Q */ 7711 7712 use_sg = scsi_dma_map(scp); 7713 if (use_sg < 0) { 7714 ASC_DBG(1, "failed to map SG list\n"); 7715 ASC_STATS(scp->device->host, adv_build_noreq); 7716 return ASC_BUSY; 7717 } else if (use_sg == 0) { 7718 /* Zero-length transfer */ 7719 reqp->sgblkp = NULL; 7720 scsiqp->data_cnt = 0; 7721 7722 scsiqp->data_addr = 0; 7723 scsiqp->sg_list_ptr = NULL; 7724 scsiqp->sg_real_addr = 0; 7725 } else { 7726 if (use_sg > ADV_MAX_SG_LIST) { 7727 scmd_printk(KERN_ERR, scp, "use_sg %d > " 7728 "ADV_MAX_SG_LIST %d\n", use_sg, 7729 scp->device->host->sg_tablesize); 7730 scsi_dma_unmap(scp); 7731 set_host_byte(scp, DID_ERROR); 7732 reqp->cmndp = NULL; 7733 scp->host_scribble = NULL; 7734 7735 return ASC_ERROR; 7736 } 7737 7738 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp)); 7739 7740 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg); 7741 if (ret != ADV_SUCCESS) { 7742 scsi_dma_unmap(scp); 7743 set_host_byte(scp, DID_ERROR); 7744 reqp->cmndp = NULL; 7745 scp->host_scribble = NULL; 7746 7747 return ret; 7748 } 7749 7750 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg); 7751 } 7752 7753 ASC_STATS(scp->device->host, xfer_cnt); 7754 7755 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); 7756 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); 7757 7758 *adv_reqpp = reqp; 7759 7760 return ASC_NOERROR; 7761 } 7762 7763 static int AscSgListToQueue(int sg_list) 7764 { 7765 int n_sg_list_qs; 7766 7767 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 7768 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 7769 n_sg_list_qs++; 7770 return n_sg_list_qs + 1; 7771 } 7772 7773 static uint 7774 AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs) 7775 { 7776 uint cur_used_qs; 7777 uint cur_free_qs; 7778 ASC_SCSI_BIT_ID_TYPE target_id; 7779 uchar tid_no; 7780 7781 target_id = ASC_TIX_TO_TARGET_ID(target_ix); 7782 tid_no = ASC_TIX_TO_TID(target_ix); 7783 if ((asc_dvc->unit_not_ready & target_id) || 7784 (asc_dvc->queue_full_or_busy & target_id)) { 7785 return 0; 7786 } 7787 if (n_qs == 1) { 7788 cur_used_qs = (uint) asc_dvc->cur_total_qng + 7789 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q; 7790 } else { 7791 cur_used_qs = (uint) asc_dvc->cur_total_qng + 7792 (uint) ASC_MIN_FREE_Q; 7793 } 7794 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) { 7795 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs; 7796 if (asc_dvc->cur_dvc_qng[tid_no] >= 7797 asc_dvc->max_dvc_qng[tid_no]) { 7798 return 0; 7799 } 7800 return cur_free_qs; 7801 } 7802 if (n_qs > 1) { 7803 if ((n_qs > asc_dvc->last_q_shortage) 7804 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) { 7805 asc_dvc->last_q_shortage = n_qs; 7806 } 7807 } 7808 return 0; 7809 } 7810 7811 static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head) 7812 { 7813 ushort q_addr; 7814 uchar next_qp; 7815 uchar q_status; 7816 7817 q_addr = ASC_QNO_TO_QADDR(free_q_head); 7818 q_status = (uchar)AscReadLramByte(iop_base, 7819 (ushort)(q_addr + 7820 ASC_SCSIQ_B_STATUS)); 7821 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD)); 7822 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 7823 return next_qp; 7824 return ASC_QLINK_END; 7825 } 7826 7827 static uchar 7828 AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q) 7829 { 7830 uchar i; 7831 7832 for (i = 0; i < n_free_q; i++) { 7833 free_q_head = AscAllocFreeQueue(iop_base, free_q_head); 7834 if (free_q_head == ASC_QLINK_END) 7835 break; 7836 } 7837 return free_q_head; 7838 } 7839 7840 /* 7841 * void 7842 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) 7843 * 7844 * Calling/Exit State: 7845 * none 7846 * 7847 * Description: 7848 * Output an ASC_SCSI_Q structure to the chip 7849 */ 7850 static void 7851 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) 7852 { 7853 int i; 7854 7855 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words); 7856 AscSetChipLramAddr(iop_base, s_addr); 7857 for (i = 0; i < 2 * words; i += 2) { 7858 if (i == 4 || i == 20) { 7859 continue; 7860 } 7861 outpw(iop_base + IOP_RAM_DATA, 7862 ((ushort)outbuf[i + 1] << 8) | outbuf[i]); 7863 } 7864 } 7865 7866 static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) 7867 { 7868 ushort q_addr; 7869 uchar tid_no; 7870 uchar sdtr_data; 7871 uchar syn_period_ix; 7872 uchar syn_offset; 7873 PortAddr iop_base; 7874 7875 iop_base = asc_dvc->iop_base; 7876 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) && 7877 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) { 7878 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 7879 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 7880 syn_period_ix = 7881 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1); 7882 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 7883 AscMsgOutSDTR(asc_dvc, 7884 asc_dvc->sdtr_period_tbl[syn_period_ix], 7885 syn_offset); 7886 scsiq->q1.cntl |= QC_MSG_OUT; 7887 } 7888 q_addr = ASC_QNO_TO_QADDR(q_no); 7889 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) { 7890 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG; 7891 } 7892 scsiq->q1.status = QS_FREE; 7893 AscMemWordCopyPtrToLram(iop_base, 7894 q_addr + ASC_SCSIQ_CDB_BEG, 7895 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 7896 7897 DvcPutScsiQ(iop_base, 7898 q_addr + ASC_SCSIQ_CPY_BEG, 7899 (uchar *)&scsiq->q1.cntl, 7900 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1); 7901 AscWriteLramWord(iop_base, 7902 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS), 7903 (ushort)(((ushort)scsiq->q1. 7904 q_no << 8) | (ushort)QS_READY)); 7905 return 1; 7906 } 7907 7908 static int 7909 AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) 7910 { 7911 int sta; 7912 int i; 7913 ASC_SG_HEAD *sg_head; 7914 ASC_SG_LIST_Q scsi_sg_q; 7915 __le32 saved_data_addr; 7916 __le32 saved_data_cnt; 7917 PortAddr iop_base; 7918 ushort sg_list_dwords; 7919 ushort sg_index; 7920 ushort sg_entry_cnt; 7921 ushort q_addr; 7922 uchar next_qp; 7923 7924 iop_base = asc_dvc->iop_base; 7925 sg_head = scsiq->sg_head; 7926 saved_data_addr = scsiq->q1.data_addr; 7927 saved_data_cnt = scsiq->q1.data_cnt; 7928 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr); 7929 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes); 7930 /* 7931 * Set sg_entry_cnt to be the number of SG elements that 7932 * will fit in the allocated SG queues. It is minus 1, because 7933 * the first SG element is handled above. 7934 */ 7935 sg_entry_cnt = sg_head->entry_cnt - 1; 7936 7937 if (sg_entry_cnt != 0) { 7938 scsiq->q1.cntl |= QC_SG_HEAD; 7939 q_addr = ASC_QNO_TO_QADDR(q_no); 7940 sg_index = 1; 7941 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 7942 scsi_sg_q.sg_head_qp = q_no; 7943 scsi_sg_q.cntl = QCSG_SG_XFER_LIST; 7944 for (i = 0; i < sg_head->queue_cnt; i++) { 7945 scsi_sg_q.seq_no = i + 1; 7946 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 7947 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2); 7948 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 7949 if (i == 0) { 7950 scsi_sg_q.sg_list_cnt = 7951 ASC_SG_LIST_PER_Q; 7952 scsi_sg_q.sg_cur_list_cnt = 7953 ASC_SG_LIST_PER_Q; 7954 } else { 7955 scsi_sg_q.sg_list_cnt = 7956 ASC_SG_LIST_PER_Q - 1; 7957 scsi_sg_q.sg_cur_list_cnt = 7958 ASC_SG_LIST_PER_Q - 1; 7959 } 7960 } else { 7961 scsi_sg_q.cntl |= QCSG_SG_XFER_END; 7962 sg_list_dwords = sg_entry_cnt << 1; 7963 if (i == 0) { 7964 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 7965 scsi_sg_q.sg_cur_list_cnt = 7966 sg_entry_cnt; 7967 } else { 7968 scsi_sg_q.sg_list_cnt = 7969 sg_entry_cnt - 1; 7970 scsi_sg_q.sg_cur_list_cnt = 7971 sg_entry_cnt - 1; 7972 } 7973 sg_entry_cnt = 0; 7974 } 7975 next_qp = AscReadLramByte(iop_base, 7976 (ushort)(q_addr + 7977 ASC_SCSIQ_B_FWD)); 7978 scsi_sg_q.q_no = next_qp; 7979 q_addr = ASC_QNO_TO_QADDR(next_qp); 7980 AscMemWordCopyPtrToLram(iop_base, 7981 q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 7982 (uchar *)&scsi_sg_q, 7983 sizeof(ASC_SG_LIST_Q) >> 1); 7984 AscMemDWordCopyPtrToLram(iop_base, 7985 q_addr + ASC_SGQ_LIST_BEG, 7986 (uchar *)&sg_head-> 7987 sg_list[sg_index], 7988 sg_list_dwords); 7989 sg_index += ASC_SG_LIST_PER_Q; 7990 scsiq->next_sg_index = sg_index; 7991 } 7992 } else { 7993 scsiq->q1.cntl &= ~QC_SG_HEAD; 7994 } 7995 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no); 7996 scsiq->q1.data_addr = saved_data_addr; 7997 scsiq->q1.data_cnt = saved_data_cnt; 7998 return (sta); 7999 } 8000 8001 static int 8002 AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required) 8003 { 8004 PortAddr iop_base; 8005 uchar free_q_head; 8006 uchar next_qp; 8007 uchar tid_no; 8008 uchar target_ix; 8009 int sta; 8010 8011 iop_base = asc_dvc->iop_base; 8012 target_ix = scsiq->q2.target_ix; 8013 tid_no = ASC_TIX_TO_TID(target_ix); 8014 sta = 0; 8015 free_q_head = (uchar)AscGetVarFreeQHead(iop_base); 8016 if (n_q_required > 1) { 8017 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head, 8018 (uchar)n_q_required); 8019 if (next_qp != ASC_QLINK_END) { 8020 asc_dvc->last_q_shortage = 0; 8021 scsiq->sg_head->queue_cnt = n_q_required - 1; 8022 scsiq->q1.q_no = free_q_head; 8023 sta = AscPutReadySgListQueue(asc_dvc, scsiq, 8024 free_q_head); 8025 } 8026 } else if (n_q_required == 1) { 8027 next_qp = AscAllocFreeQueue(iop_base, free_q_head); 8028 if (next_qp != ASC_QLINK_END) { 8029 scsiq->q1.q_no = free_q_head; 8030 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head); 8031 } 8032 } 8033 if (sta == 1) { 8034 AscPutVarFreeQHead(iop_base, next_qp); 8035 asc_dvc->cur_total_qng += n_q_required; 8036 asc_dvc->cur_dvc_qng[tid_no]++; 8037 } 8038 return sta; 8039 } 8040 8041 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16 8042 static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = { 8043 INQUIRY, 8044 REQUEST_SENSE, 8045 READ_CAPACITY, 8046 READ_TOC, 8047 MODE_SELECT, 8048 MODE_SENSE, 8049 MODE_SELECT_10, 8050 MODE_SENSE_10, 8051 0xFF, 8052 0xFF, 8053 0xFF, 8054 0xFF, 8055 0xFF, 8056 0xFF, 8057 0xFF, 8058 0xFF 8059 }; 8060 8061 static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) 8062 { 8063 PortAddr iop_base; 8064 int sta; 8065 int n_q_required; 8066 bool disable_syn_offset_one_fix; 8067 int i; 8068 u32 addr; 8069 ushort sg_entry_cnt = 0; 8070 ushort sg_entry_cnt_minus_one = 0; 8071 uchar target_ix; 8072 uchar tid_no; 8073 uchar sdtr_data; 8074 uchar extra_bytes; 8075 uchar scsi_cmd; 8076 uchar disable_cmd; 8077 ASC_SG_HEAD *sg_head; 8078 unsigned long data_cnt; 8079 8080 iop_base = asc_dvc->iop_base; 8081 sg_head = scsiq->sg_head; 8082 if (asc_dvc->err_code != 0) 8083 return ASC_ERROR; 8084 scsiq->q1.q_no = 0; 8085 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) { 8086 scsiq->q1.extra_bytes = 0; 8087 } 8088 sta = 0; 8089 target_ix = scsiq->q2.target_ix; 8090 tid_no = ASC_TIX_TO_TID(target_ix); 8091 n_q_required = 1; 8092 if (scsiq->cdbptr[0] == REQUEST_SENSE) { 8093 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) { 8094 asc_dvc->sdtr_done &= ~scsiq->q1.target_id; 8095 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 8096 AscMsgOutSDTR(asc_dvc, 8097 asc_dvc-> 8098 sdtr_period_tbl[(sdtr_data >> 4) & 8099 (uchar)(asc_dvc-> 8100 max_sdtr_index - 8101 1)], 8102 (uchar)(sdtr_data & (uchar) 8103 ASC_SYN_MAX_OFFSET)); 8104 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT); 8105 } 8106 } 8107 if (asc_dvc->in_critical_cnt != 0) { 8108 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY); 8109 return ASC_ERROR; 8110 } 8111 asc_dvc->in_critical_cnt++; 8112 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { 8113 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) { 8114 asc_dvc->in_critical_cnt--; 8115 return ASC_ERROR; 8116 } 8117 if (sg_entry_cnt > ASC_MAX_SG_LIST) { 8118 asc_dvc->in_critical_cnt--; 8119 return ASC_ERROR; 8120 } 8121 if (sg_entry_cnt == 1) { 8122 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr); 8123 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes); 8124 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE); 8125 } 8126 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 8127 } 8128 scsi_cmd = scsiq->cdbptr[0]; 8129 disable_syn_offset_one_fix = false; 8130 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 8131 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 8132 if (scsiq->q1.cntl & QC_SG_HEAD) { 8133 data_cnt = 0; 8134 for (i = 0; i < sg_entry_cnt; i++) { 8135 data_cnt += le32_to_cpu(sg_head->sg_list[i]. 8136 bytes); 8137 } 8138 } else { 8139 data_cnt = le32_to_cpu(scsiq->q1.data_cnt); 8140 } 8141 if (data_cnt != 0UL) { 8142 if (data_cnt < 512UL) { 8143 disable_syn_offset_one_fix = true; 8144 } else { 8145 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; 8146 i++) { 8147 disable_cmd = 8148 _syn_offset_one_disable_cmd[i]; 8149 if (disable_cmd == 0xFF) { 8150 break; 8151 } 8152 if (scsi_cmd == disable_cmd) { 8153 disable_syn_offset_one_fix = 8154 true; 8155 break; 8156 } 8157 } 8158 } 8159 } 8160 } 8161 if (disable_syn_offset_one_fix) { 8162 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG; 8163 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 8164 ASC_TAG_FLAG_DISABLE_DISCONNECT); 8165 } else { 8166 scsiq->q2.tag_code &= 0x27; 8167 } 8168 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { 8169 if (asc_dvc->bug_fix_cntl) { 8170 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 8171 if ((scsi_cmd == READ_6) || 8172 (scsi_cmd == READ_10)) { 8173 addr = le32_to_cpu(sg_head-> 8174 sg_list 8175 [sg_entry_cnt_minus_one]. 8176 addr) + 8177 le32_to_cpu(sg_head-> 8178 sg_list 8179 [sg_entry_cnt_minus_one]. 8180 bytes); 8181 extra_bytes = 8182 (uchar)((ushort)addr & 0x0003); 8183 if ((extra_bytes != 0) 8184 && 8185 ((scsiq->q2. 8186 tag_code & 8187 ASC_TAG_FLAG_EXTRA_BYTES) 8188 == 0)) { 8189 scsiq->q2.tag_code |= 8190 ASC_TAG_FLAG_EXTRA_BYTES; 8191 scsiq->q1.extra_bytes = 8192 extra_bytes; 8193 data_cnt = 8194 le32_to_cpu(sg_head-> 8195 sg_list 8196 [sg_entry_cnt_minus_one]. 8197 bytes); 8198 data_cnt -= extra_bytes; 8199 sg_head-> 8200 sg_list 8201 [sg_entry_cnt_minus_one]. 8202 bytes = 8203 cpu_to_le32(data_cnt); 8204 } 8205 } 8206 } 8207 } 8208 sg_head->entry_to_copy = sg_head->entry_cnt; 8209 n_q_required = AscSgListToQueue(sg_entry_cnt); 8210 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >= 8211 (uint) n_q_required) 8212 || ((scsiq->q1.cntl & QC_URGENT) != 0)) { 8213 if ((sta = 8214 AscSendScsiQueue(asc_dvc, scsiq, 8215 n_q_required)) == 1) { 8216 asc_dvc->in_critical_cnt--; 8217 return (sta); 8218 } 8219 } 8220 } else { 8221 if (asc_dvc->bug_fix_cntl) { 8222 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 8223 if ((scsi_cmd == READ_6) || 8224 (scsi_cmd == READ_10)) { 8225 addr = 8226 le32_to_cpu(scsiq->q1.data_addr) + 8227 le32_to_cpu(scsiq->q1.data_cnt); 8228 extra_bytes = 8229 (uchar)((ushort)addr & 0x0003); 8230 if ((extra_bytes != 0) 8231 && 8232 ((scsiq->q2. 8233 tag_code & 8234 ASC_TAG_FLAG_EXTRA_BYTES) 8235 == 0)) { 8236 data_cnt = 8237 le32_to_cpu(scsiq->q1. 8238 data_cnt); 8239 if (((ushort)data_cnt & 0x01FF) 8240 == 0) { 8241 scsiq->q2.tag_code |= 8242 ASC_TAG_FLAG_EXTRA_BYTES; 8243 data_cnt -= extra_bytes; 8244 scsiq->q1.data_cnt = 8245 cpu_to_le32 8246 (data_cnt); 8247 scsiq->q1.extra_bytes = 8248 extra_bytes; 8249 } 8250 } 8251 } 8252 } 8253 } 8254 n_q_required = 1; 8255 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) || 8256 ((scsiq->q1.cntl & QC_URGENT) != 0)) { 8257 if ((sta = AscSendScsiQueue(asc_dvc, scsiq, 8258 n_q_required)) == 1) { 8259 asc_dvc->in_critical_cnt--; 8260 return (sta); 8261 } 8262 } 8263 } 8264 asc_dvc->in_critical_cnt--; 8265 return (sta); 8266 } 8267 8268 /* 8269 * AdvExeScsiQueue() - Send a request to the RISC microcode program. 8270 * 8271 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q, 8272 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 8273 * RISC to notify it a new command is ready to be executed. 8274 * 8275 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 8276 * set to SCSI_MAX_RETRY. 8277 * 8278 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode 8279 * for DMA addresses or math operations are byte swapped to little-endian 8280 * order. 8281 * 8282 * Return: 8283 * ADV_SUCCESS(1) - The request was successfully queued. 8284 * ADV_BUSY(0) - Resource unavailable; Retry again after pending 8285 * request completes. 8286 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure 8287 * host IC error. 8288 */ 8289 static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp) 8290 { 8291 AdvPortAddr iop_base; 8292 ADV_CARR_T *new_carrp; 8293 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q; 8294 8295 /* 8296 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID. 8297 */ 8298 if (scsiq->target_id > ADV_MAX_TID) { 8299 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 8300 scsiq->done_status = QD_WITH_ERROR; 8301 return ADV_ERROR; 8302 } 8303 8304 iop_base = asc_dvc->iop_base; 8305 8306 /* 8307 * Allocate a carrier ensuring at least one carrier always 8308 * remains on the freelist and initialize fields. 8309 */ 8310 new_carrp = adv_get_next_carrier(asc_dvc); 8311 if (!new_carrp) { 8312 ASC_DBG(1, "No free carriers\n"); 8313 return ADV_BUSY; 8314 } 8315 8316 asc_dvc->carr_pending_cnt++; 8317 8318 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */ 8319 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag); 8320 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr); 8321 8322 scsiq->carr_va = asc_dvc->icq_sp->carr_va; 8323 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa; 8324 8325 /* 8326 * Use the current stopper to send the ADV_SCSI_REQ_Q command to 8327 * the microcode. The newly allocated stopper will become the new 8328 * stopper. 8329 */ 8330 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr; 8331 8332 /* 8333 * Set the 'next_vpa' pointer for the old stopper to be the 8334 * physical address of the new stopper. The RISC can only 8335 * follow physical addresses. 8336 */ 8337 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa; 8338 8339 /* 8340 * Set the host adapter stopper pointer to point to the new carrier. 8341 */ 8342 asc_dvc->icq_sp = new_carrp; 8343 8344 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || 8345 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 8346 /* 8347 * Tickle the RISC to tell it to read its Command Queue Head pointer. 8348 */ 8349 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A); 8350 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 8351 /* 8352 * Clear the tickle value. In the ASC-3550 the RISC flag 8353 * command 'clr_tickle_a' does not work unless the host 8354 * value is cleared. 8355 */ 8356 AdvWriteByteRegister(iop_base, IOPB_TICKLE, 8357 ADV_TICKLE_NOP); 8358 } 8359 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 8360 /* 8361 * Notify the RISC a carrier is ready by writing the physical 8362 * address of the new carrier stopper to the COMMA register. 8363 */ 8364 AdvWriteDWordRegister(iop_base, IOPDW_COMMA, 8365 le32_to_cpu(new_carrp->carr_pa)); 8366 } 8367 8368 return ADV_SUCCESS; 8369 } 8370 8371 /* 8372 * Execute a single 'struct scsi_cmnd'. 8373 */ 8374 static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp) 8375 { 8376 int ret, err_code; 8377 struct asc_board *boardp = shost_priv(scp->device->host); 8378 8379 ASC_DBG(1, "scp 0x%p\n", scp); 8380 8381 if (ASC_NARROW_BOARD(boardp)) { 8382 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; 8383 struct asc_scsi_q asc_scsi_q; 8384 8385 ret = asc_build_req(boardp, scp, &asc_scsi_q); 8386 if (ret != ASC_NOERROR) { 8387 ASC_STATS(scp->device->host, build_error); 8388 return ret; 8389 } 8390 8391 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q); 8392 kfree(asc_scsi_q.sg_head); 8393 err_code = asc_dvc->err_code; 8394 } else { 8395 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var; 8396 adv_req_t *adv_reqp; 8397 8398 switch (adv_build_req(boardp, scp, &adv_reqp)) { 8399 case ASC_NOERROR: 8400 ASC_DBG(3, "adv_build_req ASC_NOERROR\n"); 8401 break; 8402 case ASC_BUSY: 8403 ASC_DBG(1, "adv_build_req ASC_BUSY\n"); 8404 /* 8405 * The asc_stats fields 'adv_build_noreq' and 8406 * 'adv_build_nosg' count wide board busy conditions. 8407 * They are updated in adv_build_req and 8408 * adv_get_sglist, respectively. 8409 */ 8410 return ASC_BUSY; 8411 case ASC_ERROR: 8412 default: 8413 ASC_DBG(1, "adv_build_req ASC_ERROR\n"); 8414 ASC_STATS(scp->device->host, build_error); 8415 return ASC_ERROR; 8416 } 8417 8418 ret = AdvExeScsiQueue(adv_dvc, adv_reqp); 8419 err_code = adv_dvc->err_code; 8420 } 8421 8422 switch (ret) { 8423 case ASC_NOERROR: 8424 ASC_STATS(scp->device->host, exe_noerror); 8425 /* 8426 * Increment monotonically increasing per device 8427 * successful request counter. Wrapping doesn't matter. 8428 */ 8429 boardp->reqcnt[scp->device->id]++; 8430 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n"); 8431 break; 8432 case ASC_BUSY: 8433 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n"); 8434 ASC_STATS(scp->device->host, exe_busy); 8435 break; 8436 case ASC_ERROR: 8437 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, " 8438 "err_code 0x%x\n", err_code); 8439 ASC_STATS(scp->device->host, exe_error); 8440 set_host_byte(scp, DID_ERROR); 8441 break; 8442 default: 8443 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, " 8444 "err_code 0x%x\n", err_code); 8445 ASC_STATS(scp->device->host, exe_unknown); 8446 set_host_byte(scp, DID_ERROR); 8447 break; 8448 } 8449 8450 ASC_DBG(1, "end\n"); 8451 return ret; 8452 } 8453 8454 /* 8455 * advansys_queuecommand() - interrupt-driven I/O entrypoint. 8456 * 8457 * This function always returns 0. Command return status is saved 8458 * in the 'scp' result field. 8459 */ 8460 static int 8461 advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *)) 8462 { 8463 struct Scsi_Host *shost = scp->device->host; 8464 int asc_res, result = 0; 8465 8466 ASC_STATS(shost, queuecommand); 8467 scp->scsi_done = done; 8468 8469 asc_res = asc_execute_scsi_cmnd(scp); 8470 8471 switch (asc_res) { 8472 case ASC_NOERROR: 8473 break; 8474 case ASC_BUSY: 8475 result = SCSI_MLQUEUE_HOST_BUSY; 8476 break; 8477 case ASC_ERROR: 8478 default: 8479 asc_scsi_done(scp); 8480 break; 8481 } 8482 8483 return result; 8484 } 8485 8486 static DEF_SCSI_QCMD(advansys_queuecommand) 8487 8488 static ushort AscGetEisaChipCfg(PortAddr iop_base) 8489 { 8490 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | 8491 (PortAddr) (ASC_EISA_CFG_IOP_MASK); 8492 return inpw(eisa_cfg_iop); 8493 } 8494 8495 /* 8496 * Return the BIOS address of the adapter at the specified 8497 * I/O port and with the specified bus type. 8498 */ 8499 static unsigned short AscGetChipBiosAddress(PortAddr iop_base, 8500 unsigned short bus_type) 8501 { 8502 unsigned short cfg_lsw; 8503 unsigned short bios_addr; 8504 8505 /* 8506 * The PCI BIOS is re-located by the motherboard BIOS. Because 8507 * of this the driver can not determine where a PCI BIOS is 8508 * loaded and executes. 8509 */ 8510 if (bus_type & ASC_IS_PCI) 8511 return 0; 8512 8513 if ((bus_type & ASC_IS_EISA) != 0) { 8514 cfg_lsw = AscGetEisaChipCfg(iop_base); 8515 cfg_lsw &= 0x000F; 8516 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE; 8517 return bios_addr; 8518 } 8519 8520 cfg_lsw = AscGetChipCfgLsw(iop_base); 8521 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE; 8522 return bios_addr; 8523 } 8524 8525 static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id) 8526 { 8527 ushort cfg_lsw; 8528 8529 if (AscGetChipScsiID(iop_base) == new_host_id) { 8530 return (new_host_id); 8531 } 8532 cfg_lsw = AscGetChipCfgLsw(iop_base); 8533 cfg_lsw &= 0xF8FF; 8534 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8); 8535 AscSetChipCfgLsw(iop_base, cfg_lsw); 8536 return (AscGetChipScsiID(iop_base)); 8537 } 8538 8539 static unsigned char AscGetChipScsiCtrl(PortAddr iop_base) 8540 { 8541 unsigned char sc; 8542 8543 AscSetBank(iop_base, 1); 8544 sc = inp(iop_base + IOP_REG_SC); 8545 AscSetBank(iop_base, 0); 8546 return sc; 8547 } 8548 8549 static unsigned char AscGetChipVersion(PortAddr iop_base, 8550 unsigned short bus_type) 8551 { 8552 if (bus_type & ASC_IS_EISA) { 8553 PortAddr eisa_iop; 8554 unsigned char revision; 8555 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | 8556 (PortAddr) ASC_EISA_REV_IOP_MASK; 8557 revision = inp(eisa_iop); 8558 return ASC_CHIP_MIN_VER_EISA - 1 + revision; 8559 } 8560 return AscGetChipVerNo(iop_base); 8561 } 8562 8563 static int AscStopQueueExe(PortAddr iop_base) 8564 { 8565 int count = 0; 8566 8567 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) { 8568 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 8569 ASC_STOP_REQ_RISC_STOP); 8570 do { 8571 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) & 8572 ASC_STOP_ACK_RISC_STOP) { 8573 return (1); 8574 } 8575 mdelay(100); 8576 } while (count++ < 20); 8577 } 8578 return (0); 8579 } 8580 8581 static unsigned int AscGetMaxDmaCount(ushort bus_type) 8582 { 8583 if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 8584 return ASC_MAX_VL_DMA_COUNT; 8585 return ASC_MAX_PCI_DMA_COUNT; 8586 } 8587 8588 static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc) 8589 { 8590 int i; 8591 PortAddr iop_base; 8592 uchar chip_version; 8593 8594 iop_base = asc_dvc->iop_base; 8595 asc_dvc->err_code = 0; 8596 if ((asc_dvc->bus_type & 8597 (ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) { 8598 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE; 8599 } 8600 AscSetChipControl(iop_base, CC_HALT); 8601 AscSetChipStatus(iop_base, 0); 8602 asc_dvc->bug_fix_cntl = 0; 8603 asc_dvc->pci_fix_asyn_xfer = 0; 8604 asc_dvc->pci_fix_asyn_xfer_always = 0; 8605 /* asc_dvc->init_state initialized in AscInitGetConfig(). */ 8606 asc_dvc->sdtr_done = 0; 8607 asc_dvc->cur_total_qng = 0; 8608 asc_dvc->is_in_int = false; 8609 asc_dvc->in_critical_cnt = 0; 8610 asc_dvc->last_q_shortage = 0; 8611 asc_dvc->use_tagged_qng = 0; 8612 asc_dvc->no_scam = 0; 8613 asc_dvc->unit_not_ready = 0; 8614 asc_dvc->queue_full_or_busy = 0; 8615 asc_dvc->redo_scam = 0; 8616 asc_dvc->res2 = 0; 8617 asc_dvc->min_sdtr_index = 0; 8618 asc_dvc->cfg->can_tagged_qng = 0; 8619 asc_dvc->cfg->cmd_qng_enabled = 0; 8620 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL; 8621 asc_dvc->init_sdtr = 0; 8622 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 8623 asc_dvc->scsi_reset_wait = 3; 8624 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 8625 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type); 8626 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 8627 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 8628 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 8629 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type); 8630 asc_dvc->cfg->chip_version = chip_version; 8631 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period; 8632 asc_dvc->max_sdtr_index = 7; 8633 if ((asc_dvc->bus_type & ASC_IS_PCI) && 8634 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 8635 asc_dvc->bus_type = ASC_IS_PCI_ULTRA; 8636 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period; 8637 asc_dvc->max_sdtr_index = 15; 8638 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) { 8639 AscSetExtraControl(iop_base, 8640 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 8641 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) { 8642 AscSetExtraControl(iop_base, 8643 (SEC_ACTIVE_NEGATE | 8644 SEC_ENABLE_FILTER)); 8645 } 8646 } 8647 if (asc_dvc->bus_type == ASC_IS_PCI) { 8648 AscSetExtraControl(iop_base, 8649 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 8650 } 8651 8652 for (i = 0; i <= ASC_MAX_TID; i++) { 8653 asc_dvc->cur_dvc_qng[i] = 0; 8654 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 8655 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L; 8656 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L; 8657 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 8658 } 8659 } 8660 8661 static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg) 8662 { 8663 int retry; 8664 8665 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) { 8666 unsigned char read_back; 8667 AscSetChipEEPCmd(iop_base, cmd_reg); 8668 mdelay(1); 8669 read_back = AscGetChipEEPCmd(iop_base); 8670 if (read_back == cmd_reg) 8671 return 1; 8672 } 8673 return 0; 8674 } 8675 8676 static void AscWaitEEPRead(void) 8677 { 8678 mdelay(1); 8679 } 8680 8681 static ushort AscReadEEPWord(PortAddr iop_base, uchar addr) 8682 { 8683 ushort read_wval; 8684 uchar cmd_reg; 8685 8686 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); 8687 AscWaitEEPRead(); 8688 cmd_reg = addr | ASC_EEP_CMD_READ; 8689 AscWriteEEPCmdReg(iop_base, cmd_reg); 8690 AscWaitEEPRead(); 8691 read_wval = AscGetChipEEPData(iop_base); 8692 AscWaitEEPRead(); 8693 return read_wval; 8694 } 8695 8696 static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, 8697 ushort bus_type) 8698 { 8699 ushort wval; 8700 ushort sum; 8701 ushort *wbuf; 8702 int cfg_beg; 8703 int cfg_end; 8704 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; 8705 int s_addr; 8706 8707 wbuf = (ushort *)cfg_buf; 8708 sum = 0; 8709 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */ 8710 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 8711 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); 8712 sum += *wbuf; 8713 } 8714 if (bus_type & ASC_IS_VL) { 8715 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 8716 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 8717 } else { 8718 cfg_beg = ASC_EEP_DVC_CFG_BEG; 8719 cfg_end = ASC_EEP_MAX_DVC_ADDR; 8720 } 8721 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 8722 wval = AscReadEEPWord(iop_base, (uchar)s_addr); 8723 if (s_addr <= uchar_end_in_config) { 8724 /* 8725 * Swap all char fields - must unswap bytes already swapped 8726 * by AscReadEEPWord(). 8727 */ 8728 *wbuf = le16_to_cpu(wval); 8729 } else { 8730 /* Don't swap word field at the end - cntl field. */ 8731 *wbuf = wval; 8732 } 8733 sum += wval; /* Checksum treats all EEPROM data as words. */ 8734 } 8735 /* 8736 * Read the checksum word which will be compared against 'sum' 8737 * by the caller. Word field already swapped. 8738 */ 8739 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); 8740 return sum; 8741 } 8742 8743 static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc) 8744 { 8745 PortAddr iop_base; 8746 ushort q_addr; 8747 ushort saved_word; 8748 int sta; 8749 8750 iop_base = asc_dvc->iop_base; 8751 sta = 0; 8752 q_addr = ASC_QNO_TO_QADDR(241); 8753 saved_word = AscReadLramWord(iop_base, q_addr); 8754 AscSetChipLramAddr(iop_base, q_addr); 8755 AscSetChipLramData(iop_base, 0x55AA); 8756 mdelay(10); 8757 AscSetChipLramAddr(iop_base, q_addr); 8758 if (AscGetChipLramData(iop_base) == 0x55AA) { 8759 sta = 1; 8760 AscWriteLramWord(iop_base, q_addr, saved_word); 8761 } 8762 return (sta); 8763 } 8764 8765 static void AscWaitEEPWrite(void) 8766 { 8767 mdelay(20); 8768 } 8769 8770 static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) 8771 { 8772 ushort read_back; 8773 int retry; 8774 8775 retry = 0; 8776 while (true) { 8777 AscSetChipEEPData(iop_base, data_reg); 8778 mdelay(1); 8779 read_back = AscGetChipEEPData(iop_base); 8780 if (read_back == data_reg) { 8781 return (1); 8782 } 8783 if (retry++ > ASC_EEP_MAX_RETRY) { 8784 return (0); 8785 } 8786 } 8787 } 8788 8789 static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val) 8790 { 8791 ushort read_wval; 8792 8793 read_wval = AscReadEEPWord(iop_base, addr); 8794 if (read_wval != word_val) { 8795 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE); 8796 AscWaitEEPRead(); 8797 AscWriteEEPDataReg(iop_base, word_val); 8798 AscWaitEEPRead(); 8799 AscWriteEEPCmdReg(iop_base, 8800 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr)); 8801 AscWaitEEPWrite(); 8802 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); 8803 AscWaitEEPRead(); 8804 return (AscReadEEPWord(iop_base, addr)); 8805 } 8806 return (read_wval); 8807 } 8808 8809 static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, 8810 ushort bus_type) 8811 { 8812 int n_error; 8813 ushort *wbuf; 8814 ushort word; 8815 ushort sum; 8816 int s_addr; 8817 int cfg_beg; 8818 int cfg_end; 8819 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; 8820 8821 wbuf = (ushort *)cfg_buf; 8822 n_error = 0; 8823 sum = 0; 8824 /* Write two config words; AscWriteEEPWord() will swap bytes. */ 8825 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 8826 sum += *wbuf; 8827 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { 8828 n_error++; 8829 } 8830 } 8831 if (bus_type & ASC_IS_VL) { 8832 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 8833 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 8834 } else { 8835 cfg_beg = ASC_EEP_DVC_CFG_BEG; 8836 cfg_end = ASC_EEP_MAX_DVC_ADDR; 8837 } 8838 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 8839 if (s_addr <= uchar_end_in_config) { 8840 /* 8841 * This is a char field. Swap char fields before they are 8842 * swapped again by AscWriteEEPWord(). 8843 */ 8844 word = cpu_to_le16(*wbuf); 8845 if (word != 8846 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) { 8847 n_error++; 8848 } 8849 } else { 8850 /* Don't swap word field at the end - cntl field. */ 8851 if (*wbuf != 8852 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { 8853 n_error++; 8854 } 8855 } 8856 sum += *wbuf; /* Checksum calculated from word values. */ 8857 } 8858 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */ 8859 *wbuf = sum; 8860 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) { 8861 n_error++; 8862 } 8863 8864 /* Read EEPROM back again. */ 8865 wbuf = (ushort *)cfg_buf; 8866 /* 8867 * Read two config words; Byte-swapping done by AscReadEEPWord(). 8868 */ 8869 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 8870 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) { 8871 n_error++; 8872 } 8873 } 8874 if (bus_type & ASC_IS_VL) { 8875 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 8876 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 8877 } else { 8878 cfg_beg = ASC_EEP_DVC_CFG_BEG; 8879 cfg_end = ASC_EEP_MAX_DVC_ADDR; 8880 } 8881 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 8882 if (s_addr <= uchar_end_in_config) { 8883 /* 8884 * Swap all char fields. Must unswap bytes already swapped 8885 * by AscReadEEPWord(). 8886 */ 8887 word = 8888 le16_to_cpu(AscReadEEPWord 8889 (iop_base, (uchar)s_addr)); 8890 } else { 8891 /* Don't swap word field at the end - cntl field. */ 8892 word = AscReadEEPWord(iop_base, (uchar)s_addr); 8893 } 8894 if (*wbuf != word) { 8895 n_error++; 8896 } 8897 } 8898 /* Read checksum; Byte swapping not needed. */ 8899 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) { 8900 n_error++; 8901 } 8902 return n_error; 8903 } 8904 8905 static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, 8906 ushort bus_type) 8907 { 8908 int retry; 8909 int n_error; 8910 8911 retry = 0; 8912 while (true) { 8913 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf, 8914 bus_type)) == 0) { 8915 break; 8916 } 8917 if (++retry > ASC_EEP_MAX_RETRY) { 8918 break; 8919 } 8920 } 8921 return n_error; 8922 } 8923 8924 static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc) 8925 { 8926 ASCEEP_CONFIG eep_config_buf; 8927 ASCEEP_CONFIG *eep_config; 8928 PortAddr iop_base; 8929 ushort chksum; 8930 ushort warn_code; 8931 ushort cfg_msw, cfg_lsw; 8932 int i; 8933 int write_eep = 0; 8934 8935 iop_base = asc_dvc->iop_base; 8936 warn_code = 0; 8937 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE); 8938 AscStopQueueExe(iop_base); 8939 if ((AscStopChip(iop_base)) || 8940 (AscGetChipScsiCtrl(iop_base) != 0)) { 8941 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE; 8942 AscResetChipAndScsiBus(asc_dvc); 8943 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ 8944 } 8945 if (!AscIsChipHalted(iop_base)) { 8946 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; 8947 return (warn_code); 8948 } 8949 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); 8950 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { 8951 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; 8952 return (warn_code); 8953 } 8954 eep_config = (ASCEEP_CONFIG *)&eep_config_buf; 8955 cfg_msw = AscGetChipCfgMsw(iop_base); 8956 cfg_lsw = AscGetChipCfgLsw(iop_base); 8957 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 8958 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 8959 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 8960 AscSetChipCfgMsw(iop_base, cfg_msw); 8961 } 8962 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type); 8963 ASC_DBG(1, "chksum 0x%x\n", chksum); 8964 if (chksum == 0) { 8965 chksum = 0xaa55; 8966 } 8967 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { 8968 warn_code |= ASC_WARN_AUTO_CONFIG; 8969 if (asc_dvc->cfg->chip_version == 3) { 8970 if (eep_config->cfg_lsw != cfg_lsw) { 8971 warn_code |= ASC_WARN_EEPROM_RECOVER; 8972 eep_config->cfg_lsw = 8973 AscGetChipCfgLsw(iop_base); 8974 } 8975 if (eep_config->cfg_msw != cfg_msw) { 8976 warn_code |= ASC_WARN_EEPROM_RECOVER; 8977 eep_config->cfg_msw = 8978 AscGetChipCfgMsw(iop_base); 8979 } 8980 } 8981 } 8982 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 8983 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 8984 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum); 8985 if (chksum != eep_config->chksum) { 8986 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) == 8987 ASC_CHIP_VER_PCI_ULTRA_3050) { 8988 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n"); 8989 eep_config->init_sdtr = 0xFF; 8990 eep_config->disc_enable = 0xFF; 8991 eep_config->start_motor = 0xFF; 8992 eep_config->use_cmd_qng = 0; 8993 eep_config->max_total_qng = 0xF0; 8994 eep_config->max_tag_qng = 0x20; 8995 eep_config->cntl = 0xBFFF; 8996 ASC_EEP_SET_CHIP_ID(eep_config, 7); 8997 eep_config->no_scam = 0; 8998 eep_config->adapter_info[0] = 0; 8999 eep_config->adapter_info[1] = 0; 9000 eep_config->adapter_info[2] = 0; 9001 eep_config->adapter_info[3] = 0; 9002 eep_config->adapter_info[4] = 0; 9003 /* Indicate EEPROM-less board. */ 9004 eep_config->adapter_info[5] = 0xBB; 9005 } else { 9006 ASC_PRINT 9007 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n"); 9008 write_eep = 1; 9009 warn_code |= ASC_WARN_EEPROM_CHKSUM; 9010 } 9011 } 9012 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr; 9013 asc_dvc->cfg->disc_enable = eep_config->disc_enable; 9014 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng; 9015 asc_dvc->start_motor = eep_config->start_motor; 9016 asc_dvc->dvc_cntl = eep_config->cntl; 9017 asc_dvc->no_scam = eep_config->no_scam; 9018 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0]; 9019 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1]; 9020 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2]; 9021 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3]; 9022 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4]; 9023 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5]; 9024 if (!AscTestExternalLram(asc_dvc)) { 9025 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == 9026 ASC_IS_PCI_ULTRA)) { 9027 eep_config->max_total_qng = 9028 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 9029 eep_config->max_tag_qng = 9030 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 9031 } else { 9032 eep_config->cfg_msw |= 0x0800; 9033 cfg_msw |= 0x0800; 9034 AscSetChipCfgMsw(iop_base, cfg_msw); 9035 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 9036 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 9037 } 9038 } else { 9039 } 9040 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) { 9041 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 9042 } 9043 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) { 9044 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 9045 } 9046 if (eep_config->max_tag_qng > eep_config->max_total_qng) { 9047 eep_config->max_tag_qng = eep_config->max_total_qng; 9048 } 9049 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) { 9050 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 9051 } 9052 asc_dvc->max_total_qng = eep_config->max_total_qng; 9053 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 9054 eep_config->use_cmd_qng) { 9055 eep_config->disc_enable = eep_config->use_cmd_qng; 9056 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 9057 } 9058 ASC_EEP_SET_CHIP_ID(eep_config, 9059 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID); 9060 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config); 9061 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 9062 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 9063 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 9064 } 9065 9066 for (i = 0; i <= ASC_MAX_TID; i++) { 9067 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i]; 9068 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng; 9069 asc_dvc->cfg->sdtr_period_offset[i] = 9070 (uchar)(ASC_DEF_SDTR_OFFSET | 9071 (asc_dvc->min_sdtr_index << 4)); 9072 } 9073 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base); 9074 if (write_eep) { 9075 if ((i = AscSetEEPConfig(iop_base, eep_config, 9076 asc_dvc->bus_type)) != 0) { 9077 ASC_PRINT1 9078 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", 9079 i); 9080 } else { 9081 ASC_PRINT 9082 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n"); 9083 } 9084 } 9085 return (warn_code); 9086 } 9087 9088 static int AscInitGetConfig(struct Scsi_Host *shost) 9089 { 9090 struct asc_board *board = shost_priv(shost); 9091 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var; 9092 unsigned short warn_code = 0; 9093 9094 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG; 9095 if (asc_dvc->err_code != 0) 9096 return asc_dvc->err_code; 9097 9098 if (AscFindSignature(asc_dvc->iop_base)) { 9099 AscInitAscDvcVar(asc_dvc); 9100 warn_code = AscInitFromEEP(asc_dvc); 9101 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG; 9102 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) 9103 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT; 9104 } else { 9105 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 9106 } 9107 9108 switch (warn_code) { 9109 case 0: /* No error */ 9110 break; 9111 case ASC_WARN_IO_PORT_ROTATE: 9112 shost_printk(KERN_WARNING, shost, "I/O port address " 9113 "modified\n"); 9114 break; 9115 case ASC_WARN_AUTO_CONFIG: 9116 shost_printk(KERN_WARNING, shost, "I/O port increment switch " 9117 "enabled\n"); 9118 break; 9119 case ASC_WARN_EEPROM_CHKSUM: 9120 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n"); 9121 break; 9122 case ASC_WARN_IRQ_MODIFIED: 9123 shost_printk(KERN_WARNING, shost, "IRQ modified\n"); 9124 break; 9125 case ASC_WARN_CMD_QNG_CONFLICT: 9126 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o " 9127 "disconnects\n"); 9128 break; 9129 default: 9130 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n", 9131 warn_code); 9132 break; 9133 } 9134 9135 if (asc_dvc->err_code != 0) 9136 shost_printk(KERN_ERR, shost, "error 0x%x at init_state " 9137 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state); 9138 9139 return asc_dvc->err_code; 9140 } 9141 9142 static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) 9143 { 9144 struct asc_board *board = shost_priv(shost); 9145 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var; 9146 PortAddr iop_base = asc_dvc->iop_base; 9147 unsigned short cfg_msw; 9148 unsigned short warn_code = 0; 9149 9150 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG; 9151 if (asc_dvc->err_code != 0) 9152 return asc_dvc->err_code; 9153 if (!AscFindSignature(asc_dvc->iop_base)) { 9154 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 9155 return asc_dvc->err_code; 9156 } 9157 9158 cfg_msw = AscGetChipCfgMsw(iop_base); 9159 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 9160 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 9161 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 9162 AscSetChipCfgMsw(iop_base, cfg_msw); 9163 } 9164 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) != 9165 asc_dvc->cfg->cmd_qng_enabled) { 9166 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled; 9167 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 9168 } 9169 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { 9170 warn_code |= ASC_WARN_AUTO_CONFIG; 9171 } 9172 #ifdef CONFIG_PCI 9173 if (asc_dvc->bus_type & ASC_IS_PCI) { 9174 cfg_msw &= 0xFFC0; 9175 AscSetChipCfgMsw(iop_base, cfg_msw); 9176 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) { 9177 } else { 9178 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || 9179 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { 9180 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 9181 asc_dvc->bug_fix_cntl |= 9182 ASC_BUG_FIX_ASYN_USE_SYN; 9183 } 9184 } 9185 } else 9186 #endif /* CONFIG_PCI */ 9187 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) != 9188 asc_dvc->cfg->chip_scsi_id) { 9189 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID; 9190 } 9191 9192 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG; 9193 9194 switch (warn_code) { 9195 case 0: /* No error. */ 9196 break; 9197 case ASC_WARN_IO_PORT_ROTATE: 9198 shost_printk(KERN_WARNING, shost, "I/O port address " 9199 "modified\n"); 9200 break; 9201 case ASC_WARN_AUTO_CONFIG: 9202 shost_printk(KERN_WARNING, shost, "I/O port increment switch " 9203 "enabled\n"); 9204 break; 9205 case ASC_WARN_EEPROM_CHKSUM: 9206 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n"); 9207 break; 9208 case ASC_WARN_IRQ_MODIFIED: 9209 shost_printk(KERN_WARNING, shost, "IRQ modified\n"); 9210 break; 9211 case ASC_WARN_CMD_QNG_CONFLICT: 9212 shost_printk(KERN_WARNING, shost, "tag queuing w/o " 9213 "disconnects\n"); 9214 break; 9215 default: 9216 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n", 9217 warn_code); 9218 break; 9219 } 9220 9221 if (asc_dvc->err_code != 0) 9222 shost_printk(KERN_ERR, shost, "error 0x%x at init_state " 9223 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state); 9224 9225 return asc_dvc->err_code; 9226 } 9227 9228 /* 9229 * EEPROM Configuration. 9230 * 9231 * All drivers should use this structure to set the default EEPROM 9232 * configuration. The BIOS now uses this structure when it is built. 9233 * Additional structure information can be found in a_condor.h where 9234 * the structure is defined. 9235 * 9236 * The *_Field_IsChar structs are needed to correct for endianness. 9237 * These values are read from the board 16 bits at a time directly 9238 * into the structs. Because some fields are char, the values will be 9239 * in the wrong order. The *_Field_IsChar tells when to flip the 9240 * bytes. Data read and written to PCI memory is automatically swapped 9241 * on big-endian platforms so char fields read as words are actually being 9242 * unswapped on big-endian platforms. 9243 */ 9244 #ifdef CONFIG_PCI 9245 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = { 9246 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 9247 0x0000, /* cfg_msw */ 9248 0xFFFF, /* disc_enable */ 9249 0xFFFF, /* wdtr_able */ 9250 0xFFFF, /* sdtr_able */ 9251 0xFFFF, /* start_motor */ 9252 0xFFFF, /* tagqng_able */ 9253 0xFFFF, /* bios_scan */ 9254 0, /* scam_tolerant */ 9255 7, /* adapter_scsi_id */ 9256 0, /* bios_boot_delay */ 9257 3, /* scsi_reset_delay */ 9258 0, /* bios_id_lun */ 9259 0, /* termination */ 9260 0, /* reserved1 */ 9261 0xFFE7, /* bios_ctrl */ 9262 0xFFFF, /* ultra_able */ 9263 0, /* reserved2 */ 9264 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ 9265 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 9266 0, /* dvc_cntl */ 9267 0, /* bug_fix */ 9268 0, /* serial_number_word1 */ 9269 0, /* serial_number_word2 */ 9270 0, /* serial_number_word3 */ 9271 0, /* check_sum */ 9272 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 9273 , /* oem_name[16] */ 9274 0, /* dvc_err_code */ 9275 0, /* adv_err_code */ 9276 0, /* adv_err_addr */ 9277 0, /* saved_dvc_err_code */ 9278 0, /* saved_adv_err_code */ 9279 0, /* saved_adv_err_addr */ 9280 0 /* num_of_err */ 9281 }; 9282 9283 static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = { 9284 0, /* cfg_lsw */ 9285 0, /* cfg_msw */ 9286 0, /* -disc_enable */ 9287 0, /* wdtr_able */ 9288 0, /* sdtr_able */ 9289 0, /* start_motor */ 9290 0, /* tagqng_able */ 9291 0, /* bios_scan */ 9292 0, /* scam_tolerant */ 9293 1, /* adapter_scsi_id */ 9294 1, /* bios_boot_delay */ 9295 1, /* scsi_reset_delay */ 9296 1, /* bios_id_lun */ 9297 1, /* termination */ 9298 1, /* reserved1 */ 9299 0, /* bios_ctrl */ 9300 0, /* ultra_able */ 9301 0, /* reserved2 */ 9302 1, /* max_host_qng */ 9303 1, /* max_dvc_qng */ 9304 0, /* dvc_cntl */ 9305 0, /* bug_fix */ 9306 0, /* serial_number_word1 */ 9307 0, /* serial_number_word2 */ 9308 0, /* serial_number_word3 */ 9309 0, /* check_sum */ 9310 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 9311 , /* oem_name[16] */ 9312 0, /* dvc_err_code */ 9313 0, /* adv_err_code */ 9314 0, /* adv_err_addr */ 9315 0, /* saved_dvc_err_code */ 9316 0, /* saved_adv_err_code */ 9317 0, /* saved_adv_err_addr */ 9318 0 /* num_of_err */ 9319 }; 9320 9321 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = { 9322 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 9323 0x0000, /* 01 cfg_msw */ 9324 0xFFFF, /* 02 disc_enable */ 9325 0xFFFF, /* 03 wdtr_able */ 9326 0x4444, /* 04 sdtr_speed1 */ 9327 0xFFFF, /* 05 start_motor */ 9328 0xFFFF, /* 06 tagqng_able */ 9329 0xFFFF, /* 07 bios_scan */ 9330 0, /* 08 scam_tolerant */ 9331 7, /* 09 adapter_scsi_id */ 9332 0, /* bios_boot_delay */ 9333 3, /* 10 scsi_reset_delay */ 9334 0, /* bios_id_lun */ 9335 0, /* 11 termination_se */ 9336 0, /* termination_lvd */ 9337 0xFFE7, /* 12 bios_ctrl */ 9338 0x4444, /* 13 sdtr_speed2 */ 9339 0x4444, /* 14 sdtr_speed3 */ 9340 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 9341 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 9342 0, /* 16 dvc_cntl */ 9343 0x4444, /* 17 sdtr_speed4 */ 9344 0, /* 18 serial_number_word1 */ 9345 0, /* 19 serial_number_word2 */ 9346 0, /* 20 serial_number_word3 */ 9347 0, /* 21 check_sum */ 9348 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 9349 , /* 22-29 oem_name[16] */ 9350 0, /* 30 dvc_err_code */ 9351 0, /* 31 adv_err_code */ 9352 0, /* 32 adv_err_addr */ 9353 0, /* 33 saved_dvc_err_code */ 9354 0, /* 34 saved_adv_err_code */ 9355 0, /* 35 saved_adv_err_addr */ 9356 0, /* 36 reserved */ 9357 0, /* 37 reserved */ 9358 0, /* 38 reserved */ 9359 0, /* 39 reserved */ 9360 0, /* 40 reserved */ 9361 0, /* 41 reserved */ 9362 0, /* 42 reserved */ 9363 0, /* 43 reserved */ 9364 0, /* 44 reserved */ 9365 0, /* 45 reserved */ 9366 0, /* 46 reserved */ 9367 0, /* 47 reserved */ 9368 0, /* 48 reserved */ 9369 0, /* 49 reserved */ 9370 0, /* 50 reserved */ 9371 0, /* 51 reserved */ 9372 0, /* 52 reserved */ 9373 0, /* 53 reserved */ 9374 0, /* 54 reserved */ 9375 0, /* 55 reserved */ 9376 0, /* 56 cisptr_lsw */ 9377 0, /* 57 cisprt_msw */ 9378 PCI_VENDOR_ID_ASP, /* 58 subsysvid */ 9379 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */ 9380 0, /* 60 reserved */ 9381 0, /* 61 reserved */ 9382 0, /* 62 reserved */ 9383 0 /* 63 reserved */ 9384 }; 9385 9386 static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = { 9387 0, /* 00 cfg_lsw */ 9388 0, /* 01 cfg_msw */ 9389 0, /* 02 disc_enable */ 9390 0, /* 03 wdtr_able */ 9391 0, /* 04 sdtr_speed1 */ 9392 0, /* 05 start_motor */ 9393 0, /* 06 tagqng_able */ 9394 0, /* 07 bios_scan */ 9395 0, /* 08 scam_tolerant */ 9396 1, /* 09 adapter_scsi_id */ 9397 1, /* bios_boot_delay */ 9398 1, /* 10 scsi_reset_delay */ 9399 1, /* bios_id_lun */ 9400 1, /* 11 termination_se */ 9401 1, /* termination_lvd */ 9402 0, /* 12 bios_ctrl */ 9403 0, /* 13 sdtr_speed2 */ 9404 0, /* 14 sdtr_speed3 */ 9405 1, /* 15 max_host_qng */ 9406 1, /* max_dvc_qng */ 9407 0, /* 16 dvc_cntl */ 9408 0, /* 17 sdtr_speed4 */ 9409 0, /* 18 serial_number_word1 */ 9410 0, /* 19 serial_number_word2 */ 9411 0, /* 20 serial_number_word3 */ 9412 0, /* 21 check_sum */ 9413 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 9414 , /* 22-29 oem_name[16] */ 9415 0, /* 30 dvc_err_code */ 9416 0, /* 31 adv_err_code */ 9417 0, /* 32 adv_err_addr */ 9418 0, /* 33 saved_dvc_err_code */ 9419 0, /* 34 saved_adv_err_code */ 9420 0, /* 35 saved_adv_err_addr */ 9421 0, /* 36 reserved */ 9422 0, /* 37 reserved */ 9423 0, /* 38 reserved */ 9424 0, /* 39 reserved */ 9425 0, /* 40 reserved */ 9426 0, /* 41 reserved */ 9427 0, /* 42 reserved */ 9428 0, /* 43 reserved */ 9429 0, /* 44 reserved */ 9430 0, /* 45 reserved */ 9431 0, /* 46 reserved */ 9432 0, /* 47 reserved */ 9433 0, /* 48 reserved */ 9434 0, /* 49 reserved */ 9435 0, /* 50 reserved */ 9436 0, /* 51 reserved */ 9437 0, /* 52 reserved */ 9438 0, /* 53 reserved */ 9439 0, /* 54 reserved */ 9440 0, /* 55 reserved */ 9441 0, /* 56 cisptr_lsw */ 9442 0, /* 57 cisprt_msw */ 9443 0, /* 58 subsysvid */ 9444 0, /* 59 subsysid */ 9445 0, /* 60 reserved */ 9446 0, /* 61 reserved */ 9447 0, /* 62 reserved */ 9448 0 /* 63 reserved */ 9449 }; 9450 9451 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = { 9452 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 9453 0x0000, /* 01 cfg_msw */ 9454 0xFFFF, /* 02 disc_enable */ 9455 0xFFFF, /* 03 wdtr_able */ 9456 0x5555, /* 04 sdtr_speed1 */ 9457 0xFFFF, /* 05 start_motor */ 9458 0xFFFF, /* 06 tagqng_able */ 9459 0xFFFF, /* 07 bios_scan */ 9460 0, /* 08 scam_tolerant */ 9461 7, /* 09 adapter_scsi_id */ 9462 0, /* bios_boot_delay */ 9463 3, /* 10 scsi_reset_delay */ 9464 0, /* bios_id_lun */ 9465 0, /* 11 termination_se */ 9466 0, /* termination_lvd */ 9467 0xFFE7, /* 12 bios_ctrl */ 9468 0x5555, /* 13 sdtr_speed2 */ 9469 0x5555, /* 14 sdtr_speed3 */ 9470 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 9471 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 9472 0, /* 16 dvc_cntl */ 9473 0x5555, /* 17 sdtr_speed4 */ 9474 0, /* 18 serial_number_word1 */ 9475 0, /* 19 serial_number_word2 */ 9476 0, /* 20 serial_number_word3 */ 9477 0, /* 21 check_sum */ 9478 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 9479 , /* 22-29 oem_name[16] */ 9480 0, /* 30 dvc_err_code */ 9481 0, /* 31 adv_err_code */ 9482 0, /* 32 adv_err_addr */ 9483 0, /* 33 saved_dvc_err_code */ 9484 0, /* 34 saved_adv_err_code */ 9485 0, /* 35 saved_adv_err_addr */ 9486 0, /* 36 reserved */ 9487 0, /* 37 reserved */ 9488 0, /* 38 reserved */ 9489 0, /* 39 reserved */ 9490 0, /* 40 reserved */ 9491 0, /* 41 reserved */ 9492 0, /* 42 reserved */ 9493 0, /* 43 reserved */ 9494 0, /* 44 reserved */ 9495 0, /* 45 reserved */ 9496 0, /* 46 reserved */ 9497 0, /* 47 reserved */ 9498 0, /* 48 reserved */ 9499 0, /* 49 reserved */ 9500 0, /* 50 reserved */ 9501 0, /* 51 reserved */ 9502 0, /* 52 reserved */ 9503 0, /* 53 reserved */ 9504 0, /* 54 reserved */ 9505 0, /* 55 reserved */ 9506 0, /* 56 cisptr_lsw */ 9507 0, /* 57 cisprt_msw */ 9508 PCI_VENDOR_ID_ASP, /* 58 subsysvid */ 9509 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */ 9510 0, /* 60 reserved */ 9511 0, /* 61 reserved */ 9512 0, /* 62 reserved */ 9513 0 /* 63 reserved */ 9514 }; 9515 9516 static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = { 9517 0, /* 00 cfg_lsw */ 9518 0, /* 01 cfg_msw */ 9519 0, /* 02 disc_enable */ 9520 0, /* 03 wdtr_able */ 9521 0, /* 04 sdtr_speed1 */ 9522 0, /* 05 start_motor */ 9523 0, /* 06 tagqng_able */ 9524 0, /* 07 bios_scan */ 9525 0, /* 08 scam_tolerant */ 9526 1, /* 09 adapter_scsi_id */ 9527 1, /* bios_boot_delay */ 9528 1, /* 10 scsi_reset_delay */ 9529 1, /* bios_id_lun */ 9530 1, /* 11 termination_se */ 9531 1, /* termination_lvd */ 9532 0, /* 12 bios_ctrl */ 9533 0, /* 13 sdtr_speed2 */ 9534 0, /* 14 sdtr_speed3 */ 9535 1, /* 15 max_host_qng */ 9536 1, /* max_dvc_qng */ 9537 0, /* 16 dvc_cntl */ 9538 0, /* 17 sdtr_speed4 */ 9539 0, /* 18 serial_number_word1 */ 9540 0, /* 19 serial_number_word2 */ 9541 0, /* 20 serial_number_word3 */ 9542 0, /* 21 check_sum */ 9543 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 9544 , /* 22-29 oem_name[16] */ 9545 0, /* 30 dvc_err_code */ 9546 0, /* 31 adv_err_code */ 9547 0, /* 32 adv_err_addr */ 9548 0, /* 33 saved_dvc_err_code */ 9549 0, /* 34 saved_adv_err_code */ 9550 0, /* 35 saved_adv_err_addr */ 9551 0, /* 36 reserved */ 9552 0, /* 37 reserved */ 9553 0, /* 38 reserved */ 9554 0, /* 39 reserved */ 9555 0, /* 40 reserved */ 9556 0, /* 41 reserved */ 9557 0, /* 42 reserved */ 9558 0, /* 43 reserved */ 9559 0, /* 44 reserved */ 9560 0, /* 45 reserved */ 9561 0, /* 46 reserved */ 9562 0, /* 47 reserved */ 9563 0, /* 48 reserved */ 9564 0, /* 49 reserved */ 9565 0, /* 50 reserved */ 9566 0, /* 51 reserved */ 9567 0, /* 52 reserved */ 9568 0, /* 53 reserved */ 9569 0, /* 54 reserved */ 9570 0, /* 55 reserved */ 9571 0, /* 56 cisptr_lsw */ 9572 0, /* 57 cisprt_msw */ 9573 0, /* 58 subsysvid */ 9574 0, /* 59 subsysid */ 9575 0, /* 60 reserved */ 9576 0, /* 61 reserved */ 9577 0, /* 62 reserved */ 9578 0 /* 63 reserved */ 9579 }; 9580 9581 /* 9582 * Wait for EEPROM command to complete 9583 */ 9584 static void AdvWaitEEPCmd(AdvPortAddr iop_base) 9585 { 9586 int eep_delay_ms; 9587 9588 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) { 9589 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & 9590 ASC_EEP_CMD_DONE) { 9591 break; 9592 } 9593 mdelay(1); 9594 } 9595 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 9596 0) 9597 BUG(); 9598 } 9599 9600 /* 9601 * Read the EEPROM from specified location 9602 */ 9603 static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr) 9604 { 9605 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9606 ASC_EEP_CMD_READ | eep_word_addr); 9607 AdvWaitEEPCmd(iop_base); 9608 return AdvReadWordRegister(iop_base, IOPW_EE_DATA); 9609 } 9610 9611 /* 9612 * Write the EEPROM from 'cfg_buf'. 9613 */ 9614 static void AdvSet3550EEPConfig(AdvPortAddr iop_base, 9615 ADVEEP_3550_CONFIG *cfg_buf) 9616 { 9617 ushort *wbuf; 9618 ushort addr, chksum; 9619 ushort *charfields; 9620 9621 wbuf = (ushort *)cfg_buf; 9622 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; 9623 chksum = 0; 9624 9625 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 9626 AdvWaitEEPCmd(iop_base); 9627 9628 /* 9629 * Write EEPROM from word 0 to word 20. 9630 */ 9631 for (addr = ADV_EEP_DVC_CFG_BEGIN; 9632 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 9633 ushort word; 9634 9635 if (*charfields++) { 9636 word = cpu_to_le16(*wbuf); 9637 } else { 9638 word = *wbuf; 9639 } 9640 chksum += *wbuf; /* Checksum is calculated from word values. */ 9641 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9642 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9643 ASC_EEP_CMD_WRITE | addr); 9644 AdvWaitEEPCmd(iop_base); 9645 mdelay(ADV_EEP_DELAY_MS); 9646 } 9647 9648 /* 9649 * Write EEPROM checksum at word 21. 9650 */ 9651 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 9652 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 9653 AdvWaitEEPCmd(iop_base); 9654 wbuf++; 9655 charfields++; 9656 9657 /* 9658 * Write EEPROM OEM name at words 22 to 29. 9659 */ 9660 for (addr = ADV_EEP_DVC_CTL_BEGIN; 9661 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 9662 ushort word; 9663 9664 if (*charfields++) { 9665 word = cpu_to_le16(*wbuf); 9666 } else { 9667 word = *wbuf; 9668 } 9669 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9670 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9671 ASC_EEP_CMD_WRITE | addr); 9672 AdvWaitEEPCmd(iop_base); 9673 } 9674 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 9675 AdvWaitEEPCmd(iop_base); 9676 } 9677 9678 /* 9679 * Write the EEPROM from 'cfg_buf'. 9680 */ 9681 static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base, 9682 ADVEEP_38C0800_CONFIG *cfg_buf) 9683 { 9684 ushort *wbuf; 9685 ushort *charfields; 9686 ushort addr, chksum; 9687 9688 wbuf = (ushort *)cfg_buf; 9689 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; 9690 chksum = 0; 9691 9692 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 9693 AdvWaitEEPCmd(iop_base); 9694 9695 /* 9696 * Write EEPROM from word 0 to word 20. 9697 */ 9698 for (addr = ADV_EEP_DVC_CFG_BEGIN; 9699 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 9700 ushort word; 9701 9702 if (*charfields++) { 9703 word = cpu_to_le16(*wbuf); 9704 } else { 9705 word = *wbuf; 9706 } 9707 chksum += *wbuf; /* Checksum is calculated from word values. */ 9708 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9709 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9710 ASC_EEP_CMD_WRITE | addr); 9711 AdvWaitEEPCmd(iop_base); 9712 mdelay(ADV_EEP_DELAY_MS); 9713 } 9714 9715 /* 9716 * Write EEPROM checksum at word 21. 9717 */ 9718 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 9719 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 9720 AdvWaitEEPCmd(iop_base); 9721 wbuf++; 9722 charfields++; 9723 9724 /* 9725 * Write EEPROM OEM name at words 22 to 29. 9726 */ 9727 for (addr = ADV_EEP_DVC_CTL_BEGIN; 9728 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 9729 ushort word; 9730 9731 if (*charfields++) { 9732 word = cpu_to_le16(*wbuf); 9733 } else { 9734 word = *wbuf; 9735 } 9736 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9737 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9738 ASC_EEP_CMD_WRITE | addr); 9739 AdvWaitEEPCmd(iop_base); 9740 } 9741 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 9742 AdvWaitEEPCmd(iop_base); 9743 } 9744 9745 /* 9746 * Write the EEPROM from 'cfg_buf'. 9747 */ 9748 static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base, 9749 ADVEEP_38C1600_CONFIG *cfg_buf) 9750 { 9751 ushort *wbuf; 9752 ushort *charfields; 9753 ushort addr, chksum; 9754 9755 wbuf = (ushort *)cfg_buf; 9756 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; 9757 chksum = 0; 9758 9759 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 9760 AdvWaitEEPCmd(iop_base); 9761 9762 /* 9763 * Write EEPROM from word 0 to word 20. 9764 */ 9765 for (addr = ADV_EEP_DVC_CFG_BEGIN; 9766 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 9767 ushort word; 9768 9769 if (*charfields++) { 9770 word = cpu_to_le16(*wbuf); 9771 } else { 9772 word = *wbuf; 9773 } 9774 chksum += *wbuf; /* Checksum is calculated from word values. */ 9775 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9776 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9777 ASC_EEP_CMD_WRITE | addr); 9778 AdvWaitEEPCmd(iop_base); 9779 mdelay(ADV_EEP_DELAY_MS); 9780 } 9781 9782 /* 9783 * Write EEPROM checksum at word 21. 9784 */ 9785 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 9786 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 9787 AdvWaitEEPCmd(iop_base); 9788 wbuf++; 9789 charfields++; 9790 9791 /* 9792 * Write EEPROM OEM name at words 22 to 29. 9793 */ 9794 for (addr = ADV_EEP_DVC_CTL_BEGIN; 9795 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 9796 ushort word; 9797 9798 if (*charfields++) { 9799 word = cpu_to_le16(*wbuf); 9800 } else { 9801 word = *wbuf; 9802 } 9803 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 9804 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 9805 ASC_EEP_CMD_WRITE | addr); 9806 AdvWaitEEPCmd(iop_base); 9807 } 9808 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 9809 AdvWaitEEPCmd(iop_base); 9810 } 9811 9812 /* 9813 * Read EEPROM configuration into the specified buffer. 9814 * 9815 * Return a checksum based on the EEPROM configuration read. 9816 */ 9817 static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base, 9818 ADVEEP_3550_CONFIG *cfg_buf) 9819 { 9820 ushort wval, chksum; 9821 ushort *wbuf; 9822 int eep_addr; 9823 ushort *charfields; 9824 9825 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; 9826 wbuf = (ushort *)cfg_buf; 9827 chksum = 0; 9828 9829 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 9830 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 9831 wval = AdvReadEEPWord(iop_base, eep_addr); 9832 chksum += wval; /* Checksum is calculated from word values. */ 9833 if (*charfields++) { 9834 *wbuf = le16_to_cpu(wval); 9835 } else { 9836 *wbuf = wval; 9837 } 9838 } 9839 /* Read checksum word. */ 9840 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9841 wbuf++; 9842 charfields++; 9843 9844 /* Read rest of EEPROM not covered by the checksum. */ 9845 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 9846 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 9847 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9848 if (*charfields++) { 9849 *wbuf = le16_to_cpu(*wbuf); 9850 } 9851 } 9852 return chksum; 9853 } 9854 9855 /* 9856 * Read EEPROM configuration into the specified buffer. 9857 * 9858 * Return a checksum based on the EEPROM configuration read. 9859 */ 9860 static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base, 9861 ADVEEP_38C0800_CONFIG *cfg_buf) 9862 { 9863 ushort wval, chksum; 9864 ushort *wbuf; 9865 int eep_addr; 9866 ushort *charfields; 9867 9868 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; 9869 wbuf = (ushort *)cfg_buf; 9870 chksum = 0; 9871 9872 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 9873 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 9874 wval = AdvReadEEPWord(iop_base, eep_addr); 9875 chksum += wval; /* Checksum is calculated from word values. */ 9876 if (*charfields++) { 9877 *wbuf = le16_to_cpu(wval); 9878 } else { 9879 *wbuf = wval; 9880 } 9881 } 9882 /* Read checksum word. */ 9883 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9884 wbuf++; 9885 charfields++; 9886 9887 /* Read rest of EEPROM not covered by the checksum. */ 9888 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 9889 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 9890 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9891 if (*charfields++) { 9892 *wbuf = le16_to_cpu(*wbuf); 9893 } 9894 } 9895 return chksum; 9896 } 9897 9898 /* 9899 * Read EEPROM configuration into the specified buffer. 9900 * 9901 * Return a checksum based on the EEPROM configuration read. 9902 */ 9903 static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base, 9904 ADVEEP_38C1600_CONFIG *cfg_buf) 9905 { 9906 ushort wval, chksum; 9907 ushort *wbuf; 9908 int eep_addr; 9909 ushort *charfields; 9910 9911 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; 9912 wbuf = (ushort *)cfg_buf; 9913 chksum = 0; 9914 9915 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 9916 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 9917 wval = AdvReadEEPWord(iop_base, eep_addr); 9918 chksum += wval; /* Checksum is calculated from word values. */ 9919 if (*charfields++) { 9920 *wbuf = le16_to_cpu(wval); 9921 } else { 9922 *wbuf = wval; 9923 } 9924 } 9925 /* Read checksum word. */ 9926 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9927 wbuf++; 9928 charfields++; 9929 9930 /* Read rest of EEPROM not covered by the checksum. */ 9931 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 9932 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 9933 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 9934 if (*charfields++) { 9935 *wbuf = le16_to_cpu(*wbuf); 9936 } 9937 } 9938 return chksum; 9939 } 9940 9941 /* 9942 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 9943 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 9944 * all of this is done. 9945 * 9946 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 9947 * 9948 * For a non-fatal error return a warning code. If there are no warnings 9949 * then 0 is returned. 9950 * 9951 * Note: Chip is stopped on entry. 9952 */ 9953 static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc) 9954 { 9955 AdvPortAddr iop_base; 9956 ushort warn_code; 9957 ADVEEP_3550_CONFIG eep_config; 9958 9959 iop_base = asc_dvc->iop_base; 9960 9961 warn_code = 0; 9962 9963 /* 9964 * Read the board's EEPROM configuration. 9965 * 9966 * Set default values if a bad checksum is found. 9967 */ 9968 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) { 9969 warn_code |= ASC_WARN_EEPROM_CHKSUM; 9970 9971 /* 9972 * Set EEPROM default values. 9973 */ 9974 memcpy(&eep_config, &Default_3550_EEPROM_Config, 9975 sizeof(ADVEEP_3550_CONFIG)); 9976 9977 /* 9978 * Assume the 6 byte board serial number that was read from 9979 * EEPROM is correct even if the EEPROM checksum failed. 9980 */ 9981 eep_config.serial_number_word3 = 9982 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 9983 9984 eep_config.serial_number_word2 = 9985 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 9986 9987 eep_config.serial_number_word1 = 9988 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 9989 9990 AdvSet3550EEPConfig(iop_base, &eep_config); 9991 } 9992 /* 9993 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 9994 * EEPROM configuration that was read. 9995 * 9996 * This is the mapping of EEPROM fields to Adv Library fields. 9997 */ 9998 asc_dvc->wdtr_able = eep_config.wdtr_able; 9999 asc_dvc->sdtr_able = eep_config.sdtr_able; 10000 asc_dvc->ultra_able = eep_config.ultra_able; 10001 asc_dvc->tagqng_able = eep_config.tagqng_able; 10002 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 10003 asc_dvc->max_host_qng = eep_config.max_host_qng; 10004 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10005 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); 10006 asc_dvc->start_motor = eep_config.start_motor; 10007 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 10008 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 10009 asc_dvc->no_scam = eep_config.scam_tolerant; 10010 asc_dvc->cfg->serial1 = eep_config.serial_number_word1; 10011 asc_dvc->cfg->serial2 = eep_config.serial_number_word2; 10012 asc_dvc->cfg->serial3 = eep_config.serial_number_word3; 10013 10014 /* 10015 * Set the host maximum queuing (max. 253, min. 16) and the per device 10016 * maximum queuing (max. 63, min. 4). 10017 */ 10018 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 10019 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10020 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 10021 /* If the value is zero, assume it is uninitialized. */ 10022 if (eep_config.max_host_qng == 0) { 10023 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10024 } else { 10025 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 10026 } 10027 } 10028 10029 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 10030 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10031 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 10032 /* If the value is zero, assume it is uninitialized. */ 10033 if (eep_config.max_dvc_qng == 0) { 10034 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10035 } else { 10036 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 10037 } 10038 } 10039 10040 /* 10041 * If 'max_dvc_qng' is greater than 'max_host_qng', then 10042 * set 'max_dvc_qng' to 'max_host_qng'. 10043 */ 10044 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 10045 eep_config.max_dvc_qng = eep_config.max_host_qng; 10046 } 10047 10048 /* 10049 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 10050 * values based on possibly adjusted EEPROM values. 10051 */ 10052 asc_dvc->max_host_qng = eep_config.max_host_qng; 10053 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10054 10055 /* 10056 * If the EEPROM 'termination' field is set to automatic (0), then set 10057 * the ADV_DVC_CFG 'termination' field to automatic also. 10058 * 10059 * If the termination is specified with a non-zero 'termination' 10060 * value check that a legal value is set and set the ADV_DVC_CFG 10061 * 'termination' field appropriately. 10062 */ 10063 if (eep_config.termination == 0) { 10064 asc_dvc->cfg->termination = 0; /* auto termination */ 10065 } else { 10066 /* Enable manual control with low off / high off. */ 10067 if (eep_config.termination == 1) { 10068 asc_dvc->cfg->termination = TERM_CTL_SEL; 10069 10070 /* Enable manual control with low off / high on. */ 10071 } else if (eep_config.termination == 2) { 10072 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H; 10073 10074 /* Enable manual control with low on / high on. */ 10075 } else if (eep_config.termination == 3) { 10076 asc_dvc->cfg->termination = 10077 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L; 10078 } else { 10079 /* 10080 * The EEPROM 'termination' field contains a bad value. Use 10081 * automatic termination instead. 10082 */ 10083 asc_dvc->cfg->termination = 0; 10084 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10085 } 10086 } 10087 10088 return warn_code; 10089 } 10090 10091 /* 10092 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 10093 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 10094 * all of this is done. 10095 * 10096 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 10097 * 10098 * For a non-fatal error return a warning code. If there are no warnings 10099 * then 0 is returned. 10100 * 10101 * Note: Chip is stopped on entry. 10102 */ 10103 static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc) 10104 { 10105 AdvPortAddr iop_base; 10106 ushort warn_code; 10107 ADVEEP_38C0800_CONFIG eep_config; 10108 uchar tid, termination; 10109 ushort sdtr_speed = 0; 10110 10111 iop_base = asc_dvc->iop_base; 10112 10113 warn_code = 0; 10114 10115 /* 10116 * Read the board's EEPROM configuration. 10117 * 10118 * Set default values if a bad checksum is found. 10119 */ 10120 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != 10121 eep_config.check_sum) { 10122 warn_code |= ASC_WARN_EEPROM_CHKSUM; 10123 10124 /* 10125 * Set EEPROM default values. 10126 */ 10127 memcpy(&eep_config, &Default_38C0800_EEPROM_Config, 10128 sizeof(ADVEEP_38C0800_CONFIG)); 10129 10130 /* 10131 * Assume the 6 byte board serial number that was read from 10132 * EEPROM is correct even if the EEPROM checksum failed. 10133 */ 10134 eep_config.serial_number_word3 = 10135 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 10136 10137 eep_config.serial_number_word2 = 10138 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 10139 10140 eep_config.serial_number_word1 = 10141 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 10142 10143 AdvSet38C0800EEPConfig(iop_base, &eep_config); 10144 } 10145 /* 10146 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the 10147 * EEPROM configuration that was read. 10148 * 10149 * This is the mapping of EEPROM fields to Adv Library fields. 10150 */ 10151 asc_dvc->wdtr_able = eep_config.wdtr_able; 10152 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; 10153 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; 10154 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; 10155 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; 10156 asc_dvc->tagqng_able = eep_config.tagqng_able; 10157 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 10158 asc_dvc->max_host_qng = eep_config.max_host_qng; 10159 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10160 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); 10161 asc_dvc->start_motor = eep_config.start_motor; 10162 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 10163 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 10164 asc_dvc->no_scam = eep_config.scam_tolerant; 10165 asc_dvc->cfg->serial1 = eep_config.serial_number_word1; 10166 asc_dvc->cfg->serial2 = eep_config.serial_number_word2; 10167 asc_dvc->cfg->serial3 = eep_config.serial_number_word3; 10168 10169 /* 10170 * For every Target ID if any of its 'sdtr_speed[1234]' bits 10171 * are set, then set an 'sdtr_able' bit for it. 10172 */ 10173 asc_dvc->sdtr_able = 0; 10174 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 10175 if (tid == 0) { 10176 sdtr_speed = asc_dvc->sdtr_speed1; 10177 } else if (tid == 4) { 10178 sdtr_speed = asc_dvc->sdtr_speed2; 10179 } else if (tid == 8) { 10180 sdtr_speed = asc_dvc->sdtr_speed3; 10181 } else if (tid == 12) { 10182 sdtr_speed = asc_dvc->sdtr_speed4; 10183 } 10184 if (sdtr_speed & ADV_MAX_TID) { 10185 asc_dvc->sdtr_able |= (1 << tid); 10186 } 10187 sdtr_speed >>= 4; 10188 } 10189 10190 /* 10191 * Set the host maximum queuing (max. 253, min. 16) and the per device 10192 * maximum queuing (max. 63, min. 4). 10193 */ 10194 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 10195 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10196 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 10197 /* If the value is zero, assume it is uninitialized. */ 10198 if (eep_config.max_host_qng == 0) { 10199 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10200 } else { 10201 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 10202 } 10203 } 10204 10205 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 10206 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10207 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 10208 /* If the value is zero, assume it is uninitialized. */ 10209 if (eep_config.max_dvc_qng == 0) { 10210 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10211 } else { 10212 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 10213 } 10214 } 10215 10216 /* 10217 * If 'max_dvc_qng' is greater than 'max_host_qng', then 10218 * set 'max_dvc_qng' to 'max_host_qng'. 10219 */ 10220 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 10221 eep_config.max_dvc_qng = eep_config.max_host_qng; 10222 } 10223 10224 /* 10225 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 10226 * values based on possibly adjusted EEPROM values. 10227 */ 10228 asc_dvc->max_host_qng = eep_config.max_host_qng; 10229 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10230 10231 /* 10232 * If the EEPROM 'termination' field is set to automatic (0), then set 10233 * the ADV_DVC_CFG 'termination' field to automatic also. 10234 * 10235 * If the termination is specified with a non-zero 'termination' 10236 * value check that a legal value is set and set the ADV_DVC_CFG 10237 * 'termination' field appropriately. 10238 */ 10239 if (eep_config.termination_se == 0) { 10240 termination = 0; /* auto termination for SE */ 10241 } else { 10242 /* Enable manual control with low off / high off. */ 10243 if (eep_config.termination_se == 1) { 10244 termination = 0; 10245 10246 /* Enable manual control with low off / high on. */ 10247 } else if (eep_config.termination_se == 2) { 10248 termination = TERM_SE_HI; 10249 10250 /* Enable manual control with low on / high on. */ 10251 } else if (eep_config.termination_se == 3) { 10252 termination = TERM_SE; 10253 } else { 10254 /* 10255 * The EEPROM 'termination_se' field contains a bad value. 10256 * Use automatic termination instead. 10257 */ 10258 termination = 0; 10259 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10260 } 10261 } 10262 10263 if (eep_config.termination_lvd == 0) { 10264 asc_dvc->cfg->termination = termination; /* auto termination for LVD */ 10265 } else { 10266 /* Enable manual control with low off / high off. */ 10267 if (eep_config.termination_lvd == 1) { 10268 asc_dvc->cfg->termination = termination; 10269 10270 /* Enable manual control with low off / high on. */ 10271 } else if (eep_config.termination_lvd == 2) { 10272 asc_dvc->cfg->termination = termination | TERM_LVD_HI; 10273 10274 /* Enable manual control with low on / high on. */ 10275 } else if (eep_config.termination_lvd == 3) { 10276 asc_dvc->cfg->termination = termination | TERM_LVD; 10277 } else { 10278 /* 10279 * The EEPROM 'termination_lvd' field contains a bad value. 10280 * Use automatic termination instead. 10281 */ 10282 asc_dvc->cfg->termination = termination; 10283 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10284 } 10285 } 10286 10287 return warn_code; 10288 } 10289 10290 /* 10291 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and 10292 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while 10293 * all of this is done. 10294 * 10295 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 10296 * 10297 * For a non-fatal error return a warning code. If there are no warnings 10298 * then 0 is returned. 10299 * 10300 * Note: Chip is stopped on entry. 10301 */ 10302 static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc) 10303 { 10304 AdvPortAddr iop_base; 10305 ushort warn_code; 10306 ADVEEP_38C1600_CONFIG eep_config; 10307 uchar tid, termination; 10308 ushort sdtr_speed = 0; 10309 10310 iop_base = asc_dvc->iop_base; 10311 10312 warn_code = 0; 10313 10314 /* 10315 * Read the board's EEPROM configuration. 10316 * 10317 * Set default values if a bad checksum is found. 10318 */ 10319 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != 10320 eep_config.check_sum) { 10321 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); 10322 warn_code |= ASC_WARN_EEPROM_CHKSUM; 10323 10324 /* 10325 * Set EEPROM default values. 10326 */ 10327 memcpy(&eep_config, &Default_38C1600_EEPROM_Config, 10328 sizeof(ADVEEP_38C1600_CONFIG)); 10329 10330 if (PCI_FUNC(pdev->devfn) != 0) { 10331 u8 ints; 10332 /* 10333 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 10334 * and old Mac system booting problem. The Expansion 10335 * ROM must be disabled in Function 1 for these systems 10336 */ 10337 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE; 10338 /* 10339 * Clear the INTAB (bit 11) if the GPIO 0 input 10340 * indicates the Function 1 interrupt line is wired 10341 * to INTB. 10342 * 10343 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input: 10344 * 1 - Function 1 interrupt line wired to INT A. 10345 * 0 - Function 1 interrupt line wired to INT B. 10346 * 10347 * Note: Function 0 is always wired to INTA. 10348 * Put all 5 GPIO bits in input mode and then read 10349 * their input values. 10350 */ 10351 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0); 10352 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA); 10353 if ((ints & 0x01) == 0) 10354 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB; 10355 } 10356 10357 /* 10358 * Assume the 6 byte board serial number that was read from 10359 * EEPROM is correct even if the EEPROM checksum failed. 10360 */ 10361 eep_config.serial_number_word3 = 10362 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 10363 eep_config.serial_number_word2 = 10364 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 10365 eep_config.serial_number_word1 = 10366 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 10367 10368 AdvSet38C1600EEPConfig(iop_base, &eep_config); 10369 } 10370 10371 /* 10372 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 10373 * EEPROM configuration that was read. 10374 * 10375 * This is the mapping of EEPROM fields to Adv Library fields. 10376 */ 10377 asc_dvc->wdtr_able = eep_config.wdtr_able; 10378 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; 10379 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; 10380 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; 10381 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; 10382 asc_dvc->ppr_able = 0; 10383 asc_dvc->tagqng_able = eep_config.tagqng_able; 10384 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 10385 asc_dvc->max_host_qng = eep_config.max_host_qng; 10386 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10387 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID); 10388 asc_dvc->start_motor = eep_config.start_motor; 10389 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 10390 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 10391 asc_dvc->no_scam = eep_config.scam_tolerant; 10392 10393 /* 10394 * For every Target ID if any of its 'sdtr_speed[1234]' bits 10395 * are set, then set an 'sdtr_able' bit for it. 10396 */ 10397 asc_dvc->sdtr_able = 0; 10398 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 10399 if (tid == 0) { 10400 sdtr_speed = asc_dvc->sdtr_speed1; 10401 } else if (tid == 4) { 10402 sdtr_speed = asc_dvc->sdtr_speed2; 10403 } else if (tid == 8) { 10404 sdtr_speed = asc_dvc->sdtr_speed3; 10405 } else if (tid == 12) { 10406 sdtr_speed = asc_dvc->sdtr_speed4; 10407 } 10408 if (sdtr_speed & ASC_MAX_TID) { 10409 asc_dvc->sdtr_able |= (1 << tid); 10410 } 10411 sdtr_speed >>= 4; 10412 } 10413 10414 /* 10415 * Set the host maximum queuing (max. 253, min. 16) and the per device 10416 * maximum queuing (max. 63, min. 4). 10417 */ 10418 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 10419 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10420 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 10421 /* If the value is zero, assume it is uninitialized. */ 10422 if (eep_config.max_host_qng == 0) { 10423 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 10424 } else { 10425 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 10426 } 10427 } 10428 10429 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 10430 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10431 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 10432 /* If the value is zero, assume it is uninitialized. */ 10433 if (eep_config.max_dvc_qng == 0) { 10434 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 10435 } else { 10436 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 10437 } 10438 } 10439 10440 /* 10441 * If 'max_dvc_qng' is greater than 'max_host_qng', then 10442 * set 'max_dvc_qng' to 'max_host_qng'. 10443 */ 10444 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 10445 eep_config.max_dvc_qng = eep_config.max_host_qng; 10446 } 10447 10448 /* 10449 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng' 10450 * values based on possibly adjusted EEPROM values. 10451 */ 10452 asc_dvc->max_host_qng = eep_config.max_host_qng; 10453 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 10454 10455 /* 10456 * If the EEPROM 'termination' field is set to automatic (0), then set 10457 * the ASC_DVC_CFG 'termination' field to automatic also. 10458 * 10459 * If the termination is specified with a non-zero 'termination' 10460 * value check that a legal value is set and set the ASC_DVC_CFG 10461 * 'termination' field appropriately. 10462 */ 10463 if (eep_config.termination_se == 0) { 10464 termination = 0; /* auto termination for SE */ 10465 } else { 10466 /* Enable manual control with low off / high off. */ 10467 if (eep_config.termination_se == 1) { 10468 termination = 0; 10469 10470 /* Enable manual control with low off / high on. */ 10471 } else if (eep_config.termination_se == 2) { 10472 termination = TERM_SE_HI; 10473 10474 /* Enable manual control with low on / high on. */ 10475 } else if (eep_config.termination_se == 3) { 10476 termination = TERM_SE; 10477 } else { 10478 /* 10479 * The EEPROM 'termination_se' field contains a bad value. 10480 * Use automatic termination instead. 10481 */ 10482 termination = 0; 10483 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10484 } 10485 } 10486 10487 if (eep_config.termination_lvd == 0) { 10488 asc_dvc->cfg->termination = termination; /* auto termination for LVD */ 10489 } else { 10490 /* Enable manual control with low off / high off. */ 10491 if (eep_config.termination_lvd == 1) { 10492 asc_dvc->cfg->termination = termination; 10493 10494 /* Enable manual control with low off / high on. */ 10495 } else if (eep_config.termination_lvd == 2) { 10496 asc_dvc->cfg->termination = termination | TERM_LVD_HI; 10497 10498 /* Enable manual control with low on / high on. */ 10499 } else if (eep_config.termination_lvd == 3) { 10500 asc_dvc->cfg->termination = termination | TERM_LVD; 10501 } else { 10502 /* 10503 * The EEPROM 'termination_lvd' field contains a bad value. 10504 * Use automatic termination instead. 10505 */ 10506 asc_dvc->cfg->termination = termination; 10507 warn_code |= ASC_WARN_EEPROM_TERMINATION; 10508 } 10509 } 10510 10511 return warn_code; 10512 } 10513 10514 /* 10515 * Initialize the ADV_DVC_VAR structure. 10516 * 10517 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 10518 * 10519 * For a non-fatal error return a warning code. If there are no warnings 10520 * then 0 is returned. 10521 */ 10522 static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) 10523 { 10524 struct asc_board *board = shost_priv(shost); 10525 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var; 10526 unsigned short warn_code = 0; 10527 AdvPortAddr iop_base = asc_dvc->iop_base; 10528 u16 cmd; 10529 int status; 10530 10531 asc_dvc->err_code = 0; 10532 10533 /* 10534 * Save the state of the PCI Configuration Command Register 10535 * "Parity Error Response Control" Bit. If the bit is clear (0), 10536 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore 10537 * DMA parity errors. 10538 */ 10539 asc_dvc->cfg->control_flag = 0; 10540 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 10541 if ((cmd & PCI_COMMAND_PARITY) == 0) 10542 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR; 10543 10544 asc_dvc->cfg->chip_version = 10545 AdvGetChipVersion(iop_base, asc_dvc->bus_type); 10546 10547 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n", 10548 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1), 10549 (ushort)ADV_CHIP_ID_BYTE); 10550 10551 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n", 10552 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0), 10553 (ushort)ADV_CHIP_ID_WORD); 10554 10555 /* 10556 * Reset the chip to start and allow register writes. 10557 */ 10558 if (AdvFindSignature(iop_base) == 0) { 10559 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 10560 return ADV_ERROR; 10561 } else { 10562 /* 10563 * The caller must set 'chip_type' to a valid setting. 10564 */ 10565 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 && 10566 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 && 10567 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { 10568 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE; 10569 return ADV_ERROR; 10570 } 10571 10572 /* 10573 * Reset Chip. 10574 */ 10575 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 10576 ADV_CTRL_REG_CMD_RESET); 10577 mdelay(100); 10578 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 10579 ADV_CTRL_REG_CMD_WR_IO_REG); 10580 10581 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 10582 status = AdvInitFrom38C1600EEP(asc_dvc); 10583 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 10584 status = AdvInitFrom38C0800EEP(asc_dvc); 10585 } else { 10586 status = AdvInitFrom3550EEP(asc_dvc); 10587 } 10588 warn_code |= status; 10589 } 10590 10591 if (warn_code != 0) 10592 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code); 10593 10594 if (asc_dvc->err_code) 10595 shost_printk(KERN_ERR, shost, "error code 0x%x\n", 10596 asc_dvc->err_code); 10597 10598 return asc_dvc->err_code; 10599 } 10600 #endif 10601 10602 static struct scsi_host_template advansys_template = { 10603 .proc_name = DRV_NAME, 10604 #ifdef CONFIG_PROC_FS 10605 .show_info = advansys_show_info, 10606 #endif 10607 .name = DRV_NAME, 10608 .info = advansys_info, 10609 .queuecommand = advansys_queuecommand, 10610 .eh_host_reset_handler = advansys_reset, 10611 .bios_param = advansys_biosparam, 10612 .slave_configure = advansys_slave_configure, 10613 }; 10614 10615 static int advansys_wide_init_chip(struct Scsi_Host *shost) 10616 { 10617 struct asc_board *board = shost_priv(shost); 10618 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var; 10619 size_t sgblk_pool_size; 10620 int warn_code, err_code; 10621 10622 /* 10623 * Allocate buffer carrier structures. The total size 10624 * is about 8 KB, so allocate all at once. 10625 */ 10626 adv_dvc->carrier = dma_alloc_coherent(board->dev, 10627 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL); 10628 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier); 10629 10630 if (!adv_dvc->carrier) 10631 goto kmalloc_failed; 10632 10633 /* 10634 * Allocate up to 'max_host_qng' request structures for the Wide 10635 * board. The total size is about 16 KB, so allocate all at once. 10636 * If the allocation fails decrement and try again. 10637 */ 10638 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t); 10639 if (board->adv_reqp_size & 0x1f) { 10640 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t)); 10641 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size); 10642 } 10643 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size, 10644 &board->adv_reqp_addr, GFP_KERNEL); 10645 10646 if (!board->adv_reqp) 10647 goto kmalloc_failed; 10648 10649 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp, 10650 adv_dvc->max_host_qng, board->adv_reqp_size); 10651 10652 /* 10653 * Allocate up to ADV_TOT_SG_BLOCK request structures for 10654 * the Wide board. Each structure is about 136 bytes. 10655 */ 10656 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK; 10657 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev, 10658 sgblk_pool_size, 32, 0); 10659 10660 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK, 10661 sizeof(adv_sgblk_t), sgblk_pool_size); 10662 10663 if (!board->adv_sgblk_pool) 10664 goto kmalloc_failed; 10665 10666 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) { 10667 ASC_DBG(2, "AdvInitAsc3550Driver()\n"); 10668 warn_code = AdvInitAsc3550Driver(adv_dvc); 10669 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) { 10670 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n"); 10671 warn_code = AdvInitAsc38C0800Driver(adv_dvc); 10672 } else { 10673 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n"); 10674 warn_code = AdvInitAsc38C1600Driver(adv_dvc); 10675 } 10676 err_code = adv_dvc->err_code; 10677 10678 if (warn_code || err_code) { 10679 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error " 10680 "0x%x\n", warn_code, err_code); 10681 } 10682 10683 goto exit; 10684 10685 kmalloc_failed: 10686 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n"); 10687 err_code = ADV_ERROR; 10688 exit: 10689 return err_code; 10690 } 10691 10692 static void advansys_wide_free_mem(struct asc_board *board) 10693 { 10694 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var; 10695 10696 if (adv_dvc->carrier) { 10697 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE, 10698 adv_dvc->carrier, adv_dvc->carrier_addr); 10699 adv_dvc->carrier = NULL; 10700 } 10701 if (board->adv_reqp) { 10702 dma_free_coherent(board->dev, board->adv_reqp_size, 10703 board->adv_reqp, board->adv_reqp_addr); 10704 board->adv_reqp = NULL; 10705 } 10706 if (board->adv_sgblk_pool) { 10707 dma_pool_destroy(board->adv_sgblk_pool); 10708 board->adv_sgblk_pool = NULL; 10709 } 10710 } 10711 10712 static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop, 10713 int bus_type) 10714 { 10715 struct pci_dev *pdev; 10716 struct asc_board *boardp = shost_priv(shost); 10717 ASC_DVC_VAR *asc_dvc_varp = NULL; 10718 ADV_DVC_VAR *adv_dvc_varp = NULL; 10719 int share_irq, warn_code, ret; 10720 10721 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL; 10722 10723 if (ASC_NARROW_BOARD(boardp)) { 10724 ASC_DBG(1, "narrow board\n"); 10725 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 10726 asc_dvc_varp->bus_type = bus_type; 10727 asc_dvc_varp->drv_ptr = boardp; 10728 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg; 10729 asc_dvc_varp->iop_base = iop; 10730 } else { 10731 #ifdef CONFIG_PCI 10732 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 10733 adv_dvc_varp->drv_ptr = boardp; 10734 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg; 10735 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) { 10736 ASC_DBG(1, "wide board ASC-3550\n"); 10737 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550; 10738 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) { 10739 ASC_DBG(1, "wide board ASC-38C0800\n"); 10740 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800; 10741 } else { 10742 ASC_DBG(1, "wide board ASC-38C1600\n"); 10743 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600; 10744 } 10745 10746 boardp->asc_n_io_port = pci_resource_len(pdev, 1); 10747 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1); 10748 if (!boardp->ioremap_addr) { 10749 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) " 10750 "returned NULL\n", 10751 (long)pci_resource_start(pdev, 1), 10752 boardp->asc_n_io_port); 10753 ret = -ENODEV; 10754 goto err_shost; 10755 } 10756 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr; 10757 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base); 10758 10759 /* 10760 * Even though it isn't used to access wide boards, other 10761 * than for the debug line below, save I/O Port address so 10762 * that it can be reported. 10763 */ 10764 boardp->ioport = iop; 10765 10766 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n", 10767 (ushort)inp(iop + 1), (ushort)inpw(iop)); 10768 #endif /* CONFIG_PCI */ 10769 } 10770 10771 if (ASC_NARROW_BOARD(boardp)) { 10772 /* 10773 * Set the board bus type and PCI IRQ before 10774 * calling AscInitGetConfig(). 10775 */ 10776 switch (asc_dvc_varp->bus_type) { 10777 #ifdef CONFIG_ISA 10778 case ASC_IS_VL: 10779 share_irq = 0; 10780 break; 10781 case ASC_IS_EISA: 10782 share_irq = IRQF_SHARED; 10783 break; 10784 #endif /* CONFIG_ISA */ 10785 #ifdef CONFIG_PCI 10786 case ASC_IS_PCI: 10787 share_irq = IRQF_SHARED; 10788 break; 10789 #endif /* CONFIG_PCI */ 10790 default: 10791 shost_printk(KERN_ERR, shost, "unknown adapter type: " 10792 "%d\n", asc_dvc_varp->bus_type); 10793 share_irq = 0; 10794 break; 10795 } 10796 10797 /* 10798 * NOTE: AscInitGetConfig() may change the board's 10799 * bus_type value. The bus_type value should no 10800 * longer be used. If the bus_type field must be 10801 * referenced only use the bit-wise AND operator "&". 10802 */ 10803 ASC_DBG(2, "AscInitGetConfig()\n"); 10804 ret = AscInitGetConfig(shost) ? -ENODEV : 0; 10805 } else { 10806 #ifdef CONFIG_PCI 10807 /* 10808 * For Wide boards set PCI information before calling 10809 * AdvInitGetConfig(). 10810 */ 10811 share_irq = IRQF_SHARED; 10812 ASC_DBG(2, "AdvInitGetConfig()\n"); 10813 10814 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0; 10815 #else 10816 share_irq = 0; 10817 ret = -ENODEV; 10818 #endif /* CONFIG_PCI */ 10819 } 10820 10821 if (ret) 10822 goto err_unmap; 10823 10824 /* 10825 * Save the EEPROM configuration so that it can be displayed 10826 * from /proc/scsi/advansys/[0...]. 10827 */ 10828 if (ASC_NARROW_BOARD(boardp)) { 10829 10830 ASCEEP_CONFIG *ep; 10831 10832 /* 10833 * Set the adapter's target id bit in the 'init_tidmask' field. 10834 */ 10835 boardp->init_tidmask |= 10836 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id); 10837 10838 /* 10839 * Save EEPROM settings for the board. 10840 */ 10841 ep = &boardp->eep_config.asc_eep; 10842 10843 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable; 10844 ep->disc_enable = asc_dvc_varp->cfg->disc_enable; 10845 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled; 10846 ASC_EEP_SET_DMA_SPD(ep, ASC_DEF_ISA_DMA_SPEED); 10847 ep->start_motor = asc_dvc_varp->start_motor; 10848 ep->cntl = asc_dvc_varp->dvc_cntl; 10849 ep->no_scam = asc_dvc_varp->no_scam; 10850 ep->max_total_qng = asc_dvc_varp->max_total_qng; 10851 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id); 10852 /* 'max_tag_qng' is set to the same value for every device. */ 10853 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0]; 10854 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0]; 10855 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1]; 10856 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2]; 10857 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3]; 10858 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4]; 10859 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5]; 10860 10861 /* 10862 * Modify board configuration. 10863 */ 10864 ASC_DBG(2, "AscInitSetConfig()\n"); 10865 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0; 10866 if (ret) 10867 goto err_unmap; 10868 } else { 10869 ADVEEP_3550_CONFIG *ep_3550; 10870 ADVEEP_38C0800_CONFIG *ep_38C0800; 10871 ADVEEP_38C1600_CONFIG *ep_38C1600; 10872 10873 /* 10874 * Save Wide EEP Configuration Information. 10875 */ 10876 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 10877 ep_3550 = &boardp->eep_config.adv_3550_eep; 10878 10879 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id; 10880 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng; 10881 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 10882 ep_3550->termination = adv_dvc_varp->cfg->termination; 10883 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable; 10884 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl; 10885 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able; 10886 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able; 10887 ep_3550->ultra_able = adv_dvc_varp->ultra_able; 10888 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able; 10889 ep_3550->start_motor = adv_dvc_varp->start_motor; 10890 ep_3550->scsi_reset_delay = 10891 adv_dvc_varp->scsi_reset_wait; 10892 ep_3550->serial_number_word1 = 10893 adv_dvc_varp->cfg->serial1; 10894 ep_3550->serial_number_word2 = 10895 adv_dvc_varp->cfg->serial2; 10896 ep_3550->serial_number_word3 = 10897 adv_dvc_varp->cfg->serial3; 10898 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 10899 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; 10900 10901 ep_38C0800->adapter_scsi_id = 10902 adv_dvc_varp->chip_scsi_id; 10903 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng; 10904 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 10905 ep_38C0800->termination_lvd = 10906 adv_dvc_varp->cfg->termination; 10907 ep_38C0800->disc_enable = 10908 adv_dvc_varp->cfg->disc_enable; 10909 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl; 10910 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able; 10911 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; 10912 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; 10913 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; 10914 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; 10915 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; 10916 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; 10917 ep_38C0800->start_motor = adv_dvc_varp->start_motor; 10918 ep_38C0800->scsi_reset_delay = 10919 adv_dvc_varp->scsi_reset_wait; 10920 ep_38C0800->serial_number_word1 = 10921 adv_dvc_varp->cfg->serial1; 10922 ep_38C0800->serial_number_word2 = 10923 adv_dvc_varp->cfg->serial2; 10924 ep_38C0800->serial_number_word3 = 10925 adv_dvc_varp->cfg->serial3; 10926 } else { 10927 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; 10928 10929 ep_38C1600->adapter_scsi_id = 10930 adv_dvc_varp->chip_scsi_id; 10931 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng; 10932 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 10933 ep_38C1600->termination_lvd = 10934 adv_dvc_varp->cfg->termination; 10935 ep_38C1600->disc_enable = 10936 adv_dvc_varp->cfg->disc_enable; 10937 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl; 10938 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able; 10939 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; 10940 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; 10941 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; 10942 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; 10943 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; 10944 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; 10945 ep_38C1600->start_motor = adv_dvc_varp->start_motor; 10946 ep_38C1600->scsi_reset_delay = 10947 adv_dvc_varp->scsi_reset_wait; 10948 ep_38C1600->serial_number_word1 = 10949 adv_dvc_varp->cfg->serial1; 10950 ep_38C1600->serial_number_word2 = 10951 adv_dvc_varp->cfg->serial2; 10952 ep_38C1600->serial_number_word3 = 10953 adv_dvc_varp->cfg->serial3; 10954 } 10955 10956 /* 10957 * Set the adapter's target id bit in the 'init_tidmask' field. 10958 */ 10959 boardp->init_tidmask |= 10960 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id); 10961 } 10962 10963 /* 10964 * Channels are numbered beginning with 0. For AdvanSys one host 10965 * structure supports one channel. Multi-channel boards have a 10966 * separate host structure for each channel. 10967 */ 10968 shost->max_channel = 0; 10969 if (ASC_NARROW_BOARD(boardp)) { 10970 shost->max_id = ASC_MAX_TID + 1; 10971 shost->max_lun = ASC_MAX_LUN + 1; 10972 shost->max_cmd_len = ASC_MAX_CDB_LEN; 10973 10974 shost->io_port = asc_dvc_varp->iop_base; 10975 boardp->asc_n_io_port = ASC_IOADR_GAP; 10976 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id; 10977 10978 /* Set maximum number of queues the adapter can handle. */ 10979 shost->can_queue = asc_dvc_varp->max_total_qng; 10980 } else { 10981 shost->max_id = ADV_MAX_TID + 1; 10982 shost->max_lun = ADV_MAX_LUN + 1; 10983 shost->max_cmd_len = ADV_MAX_CDB_LEN; 10984 10985 /* 10986 * Save the I/O Port address and length even though 10987 * I/O ports are not used to access Wide boards. 10988 * Instead the Wide boards are accessed with 10989 * PCI Memory Mapped I/O. 10990 */ 10991 shost->io_port = iop; 10992 10993 shost->this_id = adv_dvc_varp->chip_scsi_id; 10994 10995 /* Set maximum number of queues the adapter can handle. */ 10996 shost->can_queue = adv_dvc_varp->max_host_qng; 10997 } 10998 10999 /* 11000 * Set the maximum number of scatter-gather elements the 11001 * adapter can handle. 11002 */ 11003 if (ASC_NARROW_BOARD(boardp)) { 11004 /* 11005 * Allow two commands with 'sg_tablesize' scatter-gather 11006 * elements to be executed simultaneously. This value is 11007 * the theoretical hardware limit. It may be decreased 11008 * below. 11009 */ 11010 shost->sg_tablesize = 11011 (((asc_dvc_varp->max_total_qng - 2) / 2) * 11012 ASC_SG_LIST_PER_Q) + 1; 11013 } else { 11014 shost->sg_tablesize = ADV_MAX_SG_LIST; 11015 } 11016 11017 /* 11018 * The value of 'sg_tablesize' can not exceed the SCSI 11019 * mid-level driver definition of SG_ALL. SG_ALL also 11020 * must not be exceeded, because it is used to define the 11021 * size of the scatter-gather table in 'struct asc_sg_head'. 11022 */ 11023 if (shost->sg_tablesize > SG_ALL) { 11024 shost->sg_tablesize = SG_ALL; 11025 } 11026 11027 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize); 11028 11029 /* BIOS start address. */ 11030 if (ASC_NARROW_BOARD(boardp)) { 11031 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base, 11032 asc_dvc_varp->bus_type); 11033 } else { 11034 /* 11035 * Fill-in BIOS board variables. The Wide BIOS saves 11036 * information in LRAM that is used by the driver. 11037 */ 11038 AdvReadWordLram(adv_dvc_varp->iop_base, 11039 BIOS_SIGNATURE, boardp->bios_signature); 11040 AdvReadWordLram(adv_dvc_varp->iop_base, 11041 BIOS_VERSION, boardp->bios_version); 11042 AdvReadWordLram(adv_dvc_varp->iop_base, 11043 BIOS_CODESEG, boardp->bios_codeseg); 11044 AdvReadWordLram(adv_dvc_varp->iop_base, 11045 BIOS_CODELEN, boardp->bios_codelen); 11046 11047 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n", 11048 boardp->bios_signature, boardp->bios_version); 11049 11050 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n", 11051 boardp->bios_codeseg, boardp->bios_codelen); 11052 11053 /* 11054 * If the BIOS saved a valid signature, then fill in 11055 * the BIOS code segment base address. 11056 */ 11057 if (boardp->bios_signature == 0x55AA) { 11058 /* 11059 * Convert x86 realmode code segment to a linear 11060 * address by shifting left 4. 11061 */ 11062 shost->base = ((ulong)boardp->bios_codeseg << 4); 11063 } else { 11064 shost->base = 0; 11065 } 11066 } 11067 11068 /* 11069 * Register Board Resources - I/O Port, DMA, IRQ 11070 */ 11071 11072 /* Register DMA Channel for Narrow boards. */ 11073 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */ 11074 11075 /* Register IRQ Number. */ 11076 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost); 11077 11078 ret = request_irq(boardp->irq, advansys_interrupt, share_irq, 11079 DRV_NAME, shost); 11080 11081 if (ret) { 11082 if (ret == -EBUSY) { 11083 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 11084 "already in use\n", boardp->irq); 11085 } else if (ret == -EINVAL) { 11086 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 11087 "not valid\n", boardp->irq); 11088 } else { 11089 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 11090 "failed with %d\n", boardp->irq, ret); 11091 } 11092 goto err_unmap; 11093 } 11094 11095 /* 11096 * Initialize board RISC chip and enable interrupts. 11097 */ 11098 if (ASC_NARROW_BOARD(boardp)) { 11099 ASC_DBG(2, "AscInitAsc1000Driver()\n"); 11100 11101 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL); 11102 if (!asc_dvc_varp->overrun_buf) { 11103 ret = -ENOMEM; 11104 goto err_free_irq; 11105 } 11106 warn_code = AscInitAsc1000Driver(asc_dvc_varp); 11107 11108 if (warn_code || asc_dvc_varp->err_code) { 11109 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, " 11110 "warn 0x%x, error 0x%x\n", 11111 asc_dvc_varp->init_state, warn_code, 11112 asc_dvc_varp->err_code); 11113 if (!asc_dvc_varp->overrun_dma) { 11114 ret = -ENODEV; 11115 goto err_free_mem; 11116 } 11117 } 11118 } else { 11119 if (advansys_wide_init_chip(shost)) { 11120 ret = -ENODEV; 11121 goto err_free_mem; 11122 } 11123 } 11124 11125 ASC_DBG_PRT_SCSI_HOST(2, shost); 11126 11127 ret = scsi_add_host(shost, boardp->dev); 11128 if (ret) 11129 goto err_free_mem; 11130 11131 scsi_scan_host(shost); 11132 return 0; 11133 11134 err_free_mem: 11135 if (ASC_NARROW_BOARD(boardp)) { 11136 if (asc_dvc_varp->overrun_dma) 11137 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma, 11138 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 11139 kfree(asc_dvc_varp->overrun_buf); 11140 } else 11141 advansys_wide_free_mem(boardp); 11142 err_free_irq: 11143 free_irq(boardp->irq, shost); 11144 err_unmap: 11145 if (boardp->ioremap_addr) 11146 iounmap(boardp->ioremap_addr); 11147 #ifdef CONFIG_PCI 11148 err_shost: 11149 #endif 11150 return ret; 11151 } 11152 11153 /* 11154 * advansys_release() 11155 * 11156 * Release resources allocated for a single AdvanSys adapter. 11157 */ 11158 static int advansys_release(struct Scsi_Host *shost) 11159 { 11160 struct asc_board *board = shost_priv(shost); 11161 ASC_DBG(1, "begin\n"); 11162 scsi_remove_host(shost); 11163 free_irq(board->irq, shost); 11164 11165 if (ASC_NARROW_BOARD(board)) { 11166 dma_unmap_single(board->dev, 11167 board->dvc_var.asc_dvc_var.overrun_dma, 11168 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 11169 kfree(board->dvc_var.asc_dvc_var.overrun_buf); 11170 } else { 11171 iounmap(board->ioremap_addr); 11172 advansys_wide_free_mem(board); 11173 } 11174 scsi_host_put(shost); 11175 ASC_DBG(1, "end\n"); 11176 return 0; 11177 } 11178 11179 #define ASC_IOADR_TABLE_MAX_IX 11 11180 11181 static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = { 11182 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190, 11183 0x0210, 0x0230, 0x0250, 0x0330 11184 }; 11185 11186 static void advansys_vlb_remove(struct device *dev, unsigned int id) 11187 { 11188 int ioport = _asc_def_iop_base[id]; 11189 advansys_release(dev_get_drvdata(dev)); 11190 release_region(ioport, ASC_IOADR_GAP); 11191 } 11192 11193 /* 11194 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as: 11195 * 000: invalid 11196 * 001: 10 11197 * 010: 11 11198 * 011: 12 11199 * 100: invalid 11200 * 101: 14 11201 * 110: 15 11202 * 111: invalid 11203 */ 11204 static unsigned int advansys_vlb_irq_no(PortAddr iop_base) 11205 { 11206 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base); 11207 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9; 11208 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15)) 11209 return 0; 11210 return chip_irq; 11211 } 11212 11213 static int advansys_vlb_probe(struct device *dev, unsigned int id) 11214 { 11215 int err = -ENODEV; 11216 PortAddr iop_base = _asc_def_iop_base[id]; 11217 struct Scsi_Host *shost; 11218 struct asc_board *board; 11219 11220 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) { 11221 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base); 11222 return -ENODEV; 11223 } 11224 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base); 11225 if (!AscFindSignature(iop_base)) 11226 goto release_region; 11227 /* 11228 * I don't think this condition can actually happen, but the old 11229 * driver did it, and the chances of finding a VLB setup in 2007 11230 * to do testing with is slight to none. 11231 */ 11232 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL) 11233 goto release_region; 11234 11235 err = -ENOMEM; 11236 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11237 if (!shost) 11238 goto release_region; 11239 11240 board = shost_priv(shost); 11241 board->irq = advansys_vlb_irq_no(iop_base); 11242 board->dev = dev; 11243 board->shost = shost; 11244 11245 err = advansys_board_found(shost, iop_base, ASC_IS_VL); 11246 if (err) 11247 goto free_host; 11248 11249 dev_set_drvdata(dev, shost); 11250 return 0; 11251 11252 free_host: 11253 scsi_host_put(shost); 11254 release_region: 11255 release_region(iop_base, ASC_IOADR_GAP); 11256 return -ENODEV; 11257 } 11258 11259 static struct isa_driver advansys_vlb_driver = { 11260 .probe = advansys_vlb_probe, 11261 .remove = advansys_vlb_remove, 11262 .driver = { 11263 .owner = THIS_MODULE, 11264 .name = "advansys_vlb", 11265 }, 11266 }; 11267 11268 static struct eisa_device_id advansys_eisa_table[] = { 11269 { "ABP7401" }, 11270 { "ABP7501" }, 11271 { "" } 11272 }; 11273 11274 MODULE_DEVICE_TABLE(eisa, advansys_eisa_table); 11275 11276 /* 11277 * EISA is a little more tricky than PCI; each EISA device may have two 11278 * channels, and this driver is written to make each channel its own Scsi_Host 11279 */ 11280 struct eisa_scsi_data { 11281 struct Scsi_Host *host[2]; 11282 }; 11283 11284 /* 11285 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as: 11286 * 000: 10 11287 * 001: 11 11288 * 010: 12 11289 * 011: invalid 11290 * 100: 14 11291 * 101: 15 11292 * 110: invalid 11293 * 111: invalid 11294 */ 11295 static unsigned int advansys_eisa_irq_no(struct eisa_device *edev) 11296 { 11297 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86); 11298 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10; 11299 if ((chip_irq == 13) || (chip_irq > 15)) 11300 return 0; 11301 return chip_irq; 11302 } 11303 11304 static int advansys_eisa_probe(struct device *dev) 11305 { 11306 int i, ioport, irq = 0; 11307 int err; 11308 struct eisa_device *edev = to_eisa_device(dev); 11309 struct eisa_scsi_data *data; 11310 11311 err = -ENOMEM; 11312 data = kzalloc(sizeof(*data), GFP_KERNEL); 11313 if (!data) 11314 goto fail; 11315 ioport = edev->base_addr + 0xc30; 11316 11317 err = -ENODEV; 11318 for (i = 0; i < 2; i++, ioport += 0x20) { 11319 struct asc_board *board; 11320 struct Scsi_Host *shost; 11321 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) { 11322 printk(KERN_WARNING "Region %x-%x busy\n", ioport, 11323 ioport + ASC_IOADR_GAP - 1); 11324 continue; 11325 } 11326 if (!AscFindSignature(ioport)) { 11327 release_region(ioport, ASC_IOADR_GAP); 11328 continue; 11329 } 11330 11331 /* 11332 * I don't know why we need to do this for EISA chips, but 11333 * not for any others. It looks to be equivalent to 11334 * AscGetChipCfgMsw, but I may have overlooked something, 11335 * so I'm not converting it until I get an EISA board to 11336 * test with. 11337 */ 11338 inw(ioport + 4); 11339 11340 if (!irq) 11341 irq = advansys_eisa_irq_no(edev); 11342 11343 err = -ENOMEM; 11344 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11345 if (!shost) 11346 goto release_region; 11347 11348 board = shost_priv(shost); 11349 board->irq = irq; 11350 board->dev = dev; 11351 board->shost = shost; 11352 11353 err = advansys_board_found(shost, ioport, ASC_IS_EISA); 11354 if (!err) { 11355 data->host[i] = shost; 11356 continue; 11357 } 11358 11359 scsi_host_put(shost); 11360 release_region: 11361 release_region(ioport, ASC_IOADR_GAP); 11362 break; 11363 } 11364 11365 if (err) 11366 goto free_data; 11367 dev_set_drvdata(dev, data); 11368 return 0; 11369 11370 free_data: 11371 kfree(data->host[0]); 11372 kfree(data->host[1]); 11373 kfree(data); 11374 fail: 11375 return err; 11376 } 11377 11378 static int advansys_eisa_remove(struct device *dev) 11379 { 11380 int i; 11381 struct eisa_scsi_data *data = dev_get_drvdata(dev); 11382 11383 for (i = 0; i < 2; i++) { 11384 int ioport; 11385 struct Scsi_Host *shost = data->host[i]; 11386 if (!shost) 11387 continue; 11388 ioport = shost->io_port; 11389 advansys_release(shost); 11390 release_region(ioport, ASC_IOADR_GAP); 11391 } 11392 11393 kfree(data); 11394 return 0; 11395 } 11396 11397 static struct eisa_driver advansys_eisa_driver = { 11398 .id_table = advansys_eisa_table, 11399 .driver = { 11400 .name = DRV_NAME, 11401 .probe = advansys_eisa_probe, 11402 .remove = advansys_eisa_remove, 11403 } 11404 }; 11405 11406 /* PCI Devices supported by this driver */ 11407 static struct pci_device_id advansys_pci_tbl[] = { 11408 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A, 11409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11410 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940, 11411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11412 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U, 11413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11414 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW, 11415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11416 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1, 11417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11418 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1, 11419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 11420 {} 11421 }; 11422 11423 MODULE_DEVICE_TABLE(pci, advansys_pci_tbl); 11424 11425 static void advansys_set_latency(struct pci_dev *pdev) 11426 { 11427 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || 11428 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { 11429 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0); 11430 } else { 11431 u8 latency; 11432 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency); 11433 if (latency < 0x20) 11434 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20); 11435 } 11436 } 11437 11438 static int advansys_pci_probe(struct pci_dev *pdev, 11439 const struct pci_device_id *ent) 11440 { 11441 int err, ioport; 11442 struct Scsi_Host *shost; 11443 struct asc_board *board; 11444 11445 err = pci_enable_device(pdev); 11446 if (err) 11447 goto fail; 11448 err = pci_request_regions(pdev, DRV_NAME); 11449 if (err) 11450 goto disable_device; 11451 pci_set_master(pdev); 11452 advansys_set_latency(pdev); 11453 11454 err = -ENODEV; 11455 if (pci_resource_len(pdev, 0) == 0) 11456 goto release_region; 11457 11458 ioport = pci_resource_start(pdev, 0); 11459 11460 err = -ENOMEM; 11461 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 11462 if (!shost) 11463 goto release_region; 11464 11465 board = shost_priv(shost); 11466 board->irq = pdev->irq; 11467 board->dev = &pdev->dev; 11468 board->shost = shost; 11469 11470 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW || 11471 pdev->device == PCI_DEVICE_ID_38C0800_REV1 || 11472 pdev->device == PCI_DEVICE_ID_38C1600_REV1) { 11473 board->flags |= ASC_IS_WIDE_BOARD; 11474 } 11475 11476 err = advansys_board_found(shost, ioport, ASC_IS_PCI); 11477 if (err) 11478 goto free_host; 11479 11480 pci_set_drvdata(pdev, shost); 11481 return 0; 11482 11483 free_host: 11484 scsi_host_put(shost); 11485 release_region: 11486 pci_release_regions(pdev); 11487 disable_device: 11488 pci_disable_device(pdev); 11489 fail: 11490 return err; 11491 } 11492 11493 static void advansys_pci_remove(struct pci_dev *pdev) 11494 { 11495 advansys_release(pci_get_drvdata(pdev)); 11496 pci_release_regions(pdev); 11497 pci_disable_device(pdev); 11498 } 11499 11500 static struct pci_driver advansys_pci_driver = { 11501 .name = DRV_NAME, 11502 .id_table = advansys_pci_tbl, 11503 .probe = advansys_pci_probe, 11504 .remove = advansys_pci_remove, 11505 }; 11506 11507 static int __init advansys_init(void) 11508 { 11509 int error; 11510 11511 error = isa_register_driver(&advansys_vlb_driver, 11512 ASC_IOADR_TABLE_MAX_IX); 11513 if (error) 11514 goto fail; 11515 11516 error = eisa_driver_register(&advansys_eisa_driver); 11517 if (error) 11518 goto unregister_vlb; 11519 11520 error = pci_register_driver(&advansys_pci_driver); 11521 if (error) 11522 goto unregister_eisa; 11523 11524 return 0; 11525 11526 unregister_eisa: 11527 eisa_driver_unregister(&advansys_eisa_driver); 11528 unregister_vlb: 11529 isa_unregister_driver(&advansys_vlb_driver); 11530 fail: 11531 return error; 11532 } 11533 11534 static void __exit advansys_exit(void) 11535 { 11536 pci_unregister_driver(&advansys_pci_driver); 11537 eisa_driver_unregister(&advansys_eisa_driver); 11538 isa_unregister_driver(&advansys_vlb_driver); 11539 } 11540 11541 module_init(advansys_init); 11542 module_exit(advansys_exit); 11543 11544 MODULE_LICENSE("GPL"); 11545 MODULE_FIRMWARE("advansys/mcode.bin"); 11546 MODULE_FIRMWARE("advansys/3550.bin"); 11547 MODULE_FIRMWARE("advansys/38C0800.bin"); 11548 MODULE_FIRMWARE("advansys/38C1600.bin"); 11549