1 /* 2 * Adaptec AAC series RAID controller driver 3 * (c) Copyright 2001 Red Hat Inc. <alan@redhat.com> 4 * 5 * based on the old aacraid driver that is.. 6 * Adaptec aacraid device driver for Linux. 7 * 8 * Copyright (c) 2000-2010 Adaptec, Inc. 9 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com) 10 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Module Name: 27 * aacraid.h 28 * 29 * Abstract: Contains all routines for control of the aacraid driver 30 * 31 */ 32 33 #ifndef _AACRAID_H_ 34 #define _AACRAID_H_ 35 #ifndef dprintk 36 # define dprintk(x) 37 #endif 38 /* eg: if (nblank(dprintk(x))) */ 39 #define _nblank(x) #x 40 #define nblank(x) _nblank(x)[0] 41 42 #include <linux/interrupt.h> 43 #include <linux/pci.h> 44 45 /*------------------------------------------------------------------------------ 46 * D E F I N E S 47 *----------------------------------------------------------------------------*/ 48 49 #define AAC_MAX_MSIX 32 /* vectors */ 50 #define AAC_PCI_MSI_ENABLE 0x8000 51 52 enum { 53 AAC_ENABLE_INTERRUPT = 0x0, 54 AAC_DISABLE_INTERRUPT, 55 AAC_ENABLE_MSIX, 56 AAC_DISABLE_MSIX, 57 AAC_CLEAR_AIF_BIT, 58 AAC_CLEAR_SYNC_BIT, 59 AAC_ENABLE_INTX 60 }; 61 62 #define AAC_INT_MODE_INTX (1<<0) 63 #define AAC_INT_MODE_MSI (1<<1) 64 #define AAC_INT_MODE_AIF (1<<2) 65 #define AAC_INT_MODE_SYNC (1<<3) 66 #define AAC_INT_MODE_MSIX (1<<16) 67 68 #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb 69 #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa 70 #define AAC_INT_DISABLE_ALL 0xffffffff 71 72 /* Bit definitions in IOA->Host Interrupt Register */ 73 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31) 74 #define PMC_IOARCB_TRANSFER_FAILED (1<<28) 75 #define PMC_IOA_UNIT_CHECK (1<<27) 76 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26) 77 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25) 78 #define PMC_IOARRIN_LOST (1<<4) 79 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3) 80 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2) 81 #define PMC_HOST_RRQ_VALID (1<<1) 82 #define PMC_OPERATIONAL_STATUS (1<<31) 83 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0) 84 85 #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \ 86 PMC_IOA_UNIT_CHECK | \ 87 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \ 88 PMC_IOARRIN_LOST | \ 89 PMC_SYSTEM_BUS_MMIO_ERROR | \ 90 PMC_IOA_PROCESSOR_IN_ERROR_STATE) 91 92 #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \ 93 PMC_HOST_RRQ_VALID | \ 94 PMC_TRANSITION_TO_OPERATIONAL | \ 95 PMC_ALLOW_MSIX_VECTOR0) 96 #define PMC_GLOBAL_INT_BIT2 0x00000004 97 #define PMC_GLOBAL_INT_BIT0 0x00000001 98 99 #ifndef AAC_DRIVER_BUILD 100 # define AAC_DRIVER_BUILD 50834 101 # define AAC_DRIVER_BRANCH "-custom" 102 #endif 103 #define MAXIMUM_NUM_CONTAINERS 32 104 105 #define AAC_NUM_MGT_FIB 8 106 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB) 107 #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB) 108 109 #define AAC_MAX_LUN 256 110 111 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff) 112 #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256) 113 114 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE 115 116 #define AAC_MAX_NATIVE_TARGETS 1024 117 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */ 118 #define AAC_MAX_BUSES 5 119 #define AAC_MAX_TARGETS 256 120 #define AAC_BUS_TARGET_LOOP (AAC_MAX_BUSES * AAC_MAX_TARGETS) 121 #define AAC_MAX_NATIVE_SIZE 2048 122 #define FW_ERROR_BUFFER_SIZE 512 123 124 #define get_bus_number(x) (x/AAC_MAX_TARGETS) 125 #define get_target_number(x) (x%AAC_MAX_TARGETS) 126 127 /* Thor AIF events */ 128 #define SA_AIF_HOTPLUG (1<<1) 129 #define SA_AIF_HARDWARE (1<<2) 130 #define SA_AIF_PDEV_CHANGE (1<<4) 131 #define SA_AIF_LDEV_CHANGE (1<<5) 132 #define SA_AIF_BPSTAT_CHANGE (1<<30) 133 #define SA_AIF_BPCFG_CHANGE (1<<31) 134 135 #define HBA_MAX_SG_EMBEDDED 28 136 #define HBA_MAX_SG_SEPARATE 90 137 #define HBA_SENSE_DATA_LEN_MAX 32 138 #define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002 139 #define HBA_SGL_FLAGS_EXT 0x80000000UL 140 141 struct aac_hba_sgl { 142 u32 addr_lo; /* Lower 32-bits of SGL element address */ 143 u32 addr_hi; /* Upper 32-bits of SGL element address */ 144 u32 len; /* Length of SGL element in bytes */ 145 u32 flags; /* SGL element flags */ 146 }; 147 148 enum { 149 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40, 150 HBA_IU_TYPE_SCSI_TM_REQ = 0x41, 151 HBA_IU_TYPE_SATA_REQ = 0x42, 152 HBA_IU_TYPE_RESP = 0x60, 153 HBA_IU_TYPE_COALESCED_RESP = 0x61, 154 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70 155 }; 156 157 enum { 158 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1, 159 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2, 160 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4, 161 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8 162 }; 163 164 enum { 165 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0, 166 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT, 167 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR, 168 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE 169 }; 170 171 enum { 172 HBA_RESP_DATAPRES_NO_DATA = 0x0, 173 HBA_RESP_DATAPRES_RESPONSE_DATA, 174 HBA_RESP_DATAPRES_SENSE_DATA 175 }; 176 177 enum { 178 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0, 179 HBA_RESP_SVCRES_FAILURE, 180 HBA_RESP_SVCRES_TMF_COMPLETE, 181 HBA_RESP_SVCRES_TMF_SUCCEEDED, 182 HBA_RESP_SVCRES_TMF_REJECTED, 183 HBA_RESP_SVCRES_TMF_LUN_INVALID 184 }; 185 186 enum { 187 HBA_RESP_STAT_IO_ERROR = 0x1, 188 HBA_RESP_STAT_IO_ABORTED, 189 HBA_RESP_STAT_NO_PATH_TO_DEVICE, 190 HBA_RESP_STAT_INVALID_DEVICE, 191 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE, 192 HBA_RESP_STAT_UNDERRUN = 0x51, 193 HBA_RESP_STAT_OVERRUN = 0x75 194 }; 195 196 struct aac_hba_cmd_req { 197 u8 iu_type; /* HBA information unit type */ 198 /* 199 * byte1: 200 * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT 201 * [2] TYPE - 0=PCI, 1=DDR 202 * [3] CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled 203 */ 204 u8 byte1; 205 u8 reply_qid; /* Host reply queue to post response to */ 206 u8 reserved1; 207 __le32 it_nexus; /* Device handle for the request */ 208 __le32 request_id; /* Sender context */ 209 /* Lower 32-bits of tweak value for crypto enabled IOs */ 210 __le32 tweak_value_lo; 211 u8 cdb[16]; /* SCSI CDB of the command */ 212 u8 lun[8]; /* SCSI LUN of the command */ 213 214 /* Total data length in bytes to be read/written (if any) */ 215 __le32 data_length; 216 217 /* [2:0] Task Attribute, [6:3] Command Priority */ 218 u8 attr_prio; 219 220 /* Number of SGL elements embedded in the HBA req */ 221 u8 emb_data_desc_count; 222 223 __le16 dek_index; /* DEK index for crypto enabled IOs */ 224 225 /* Lower 32-bits of reserved error data target location on the host */ 226 __le32 error_ptr_lo; 227 228 /* Upper 32-bits of reserved error data target location on the host */ 229 __le32 error_ptr_hi; 230 231 /* Length of reserved error data area on the host in bytes */ 232 __le32 error_length; 233 234 /* Upper 32-bits of tweak value for crypto enabled IOs */ 235 __le32 tweak_value_hi; 236 237 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */ 238 239 /* 240 * structure must not exceed 241 * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE 242 */ 243 }; 244 245 /* Task Management Functions (TMF) */ 246 #define HBA_TMF_ABORT_TASK 0x01 247 #define HBA_TMF_LUN_RESET 0x08 248 249 struct aac_hba_tm_req { 250 u8 iu_type; /* HBA information unit type */ 251 u8 reply_qid; /* Host reply queue to post response to */ 252 u8 tmf; /* Task management function */ 253 u8 reserved1; 254 255 __le32 it_nexus; /* Device handle for the command */ 256 257 u8 lun[8]; /* SCSI LUN */ 258 259 /* Used to hold sender context. */ 260 __le32 request_id; /* Sender context */ 261 __le32 reserved2; 262 263 /* Request identifier of managed task */ 264 __le32 managed_request_id; /* Sender context being managed */ 265 __le32 reserved3; 266 267 /* Lower 32-bits of reserved error data target location on the host */ 268 __le32 error_ptr_lo; 269 /* Upper 32-bits of reserved error data target location on the host */ 270 __le32 error_ptr_hi; 271 /* Length of reserved error data area on the host in bytes */ 272 __le32 error_length; 273 }; 274 275 struct aac_hba_reset_req { 276 u8 iu_type; /* HBA information unit type */ 277 /* 0 - reset specified device, 1 - reset all devices */ 278 u8 reset_type; 279 u8 reply_qid; /* Host reply queue to post response to */ 280 u8 reserved1; 281 282 __le32 it_nexus; /* Device handle for the command */ 283 __le32 request_id; /* Sender context */ 284 /* Lower 32-bits of reserved error data target location on the host */ 285 __le32 error_ptr_lo; 286 /* Upper 32-bits of reserved error data target location on the host */ 287 __le32 error_ptr_hi; 288 /* Length of reserved error data area on the host in bytes */ 289 __le32 error_length; 290 }; 291 292 struct aac_hba_resp { 293 u8 iu_type; /* HBA information unit type */ 294 u8 reserved1[3]; 295 __le32 request_identifier; /* sender context */ 296 __le32 reserved2; 297 u8 service_response; /* SCSI service response */ 298 u8 status; /* SCSI status */ 299 u8 datapres; /* [1:0] - data present, [7:2] - reserved */ 300 u8 sense_response_data_len; /* Sense/response data length */ 301 __le32 residual_count; /* Residual data length in bytes */ 302 /* Sense/response data */ 303 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX]; 304 }; 305 306 struct aac_native_hba { 307 union { 308 struct aac_hba_cmd_req cmd; 309 struct aac_hba_tm_req tmr; 310 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE]; 311 } cmd; 312 union { 313 struct aac_hba_resp err; 314 u8 resp_bytes[FW_ERROR_BUFFER_SIZE]; 315 } resp; 316 }; 317 318 #define CISS_REPORT_PHYSICAL_LUNS 0xc3 319 #define WRITE_HOST_WELLNESS 0xa5 320 #define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15 321 #define BMIC_IN 0x26 322 #define BMIC_OUT 0x27 323 324 struct aac_ciss_phys_luns_resp { 325 u8 list_length[4]; /* LUN list length (N-7, big endian) */ 326 u8 resp_flag; /* extended response_flag */ 327 u8 reserved[3]; 328 struct _ciss_lun { 329 u8 tid[3]; /* Target ID */ 330 u8 bus; /* Bus, flag (bits 6,7) */ 331 u8 level3[2]; 332 u8 level2[2]; 333 u8 node_ident[16]; /* phys. node identifier */ 334 } lun[1]; /* List of phys. devices */ 335 }; 336 337 /* 338 * Interrupts 339 */ 340 #define AAC_MAX_HRRQ 64 341 342 struct aac_ciss_identify_pd { 343 u8 scsi_bus; /* SCSI Bus number on controller */ 344 u8 scsi_id; /* SCSI ID on this bus */ 345 u16 block_size; /* sector size in bytes */ 346 u32 total_blocks; /* number for sectors on drive */ 347 u32 reserved_blocks; /* controller reserved (RIS) */ 348 u8 model[40]; /* Physical Drive Model */ 349 u8 serial_number[40]; /* Drive Serial Number */ 350 u8 firmware_revision[8]; /* drive firmware revision */ 351 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ 352 u8 compaq_drive_stamp; /* 0 means drive not stamped */ 353 u8 last_failure_reason; 354 355 u8 flags; 356 u8 more_flags; 357 u8 scsi_lun; /* SCSI LUN for phys drive */ 358 u8 yet_more_flags; 359 u8 even_more_flags; 360 u32 spi_speed_rules; /* SPI Speed :Ultra disable diagnose */ 361 u8 phys_connector[2]; /* connector number on controller */ 362 u8 phys_box_on_bus; /* phys enclosure this drive resides */ 363 u8 phys_bay_in_box; /* phys drv bay this drive resides */ 364 u32 rpm; /* Drive rotational speed in rpm */ 365 u8 device_type; /* type of drive */ 366 u8 sata_version; /* only valid when drive_type is SATA */ 367 u64 big_total_block_count; 368 u64 ris_starting_lba; 369 u32 ris_size; 370 u8 wwid[20]; 371 u8 controller_phy_map[32]; 372 u16 phy_count; 373 u8 phy_connected_dev_type[256]; 374 u8 phy_to_drive_bay_num[256]; 375 u16 phy_to_attached_dev_index[256]; 376 u8 box_index; 377 u8 spitfire_support; 378 u16 extra_physical_drive_flags; 379 u8 negotiated_link_rate[256]; 380 u8 phy_to_phy_map[256]; 381 u8 redundant_path_present_map; 382 u8 redundant_path_failure_map; 383 u8 active_path_number; 384 u16 alternate_paths_phys_connector[8]; 385 u8 alternate_paths_phys_box_on_port[8]; 386 u8 multi_lun_device_lun_count; 387 u8 minimum_good_fw_revision[8]; 388 u8 unique_inquiry_bytes[20]; 389 u8 current_temperature_degreesC; 390 u8 temperature_threshold_degreesC; 391 u8 max_temperature_degreesC; 392 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512 * 2^exp */ 393 u16 current_queue_depth_limit; 394 u8 switch_name[10]; 395 u16 switch_port; 396 u8 alternate_paths_switch_name[40]; 397 u8 alternate_paths_switch_port[8]; 398 u16 power_on_hours; /* valid only if gas gauge supported */ 399 u16 percent_endurance_used; /* valid only if gas gauge supported. */ 400 u8 drive_authentication; 401 u8 smart_carrier_authentication; 402 u8 smart_carrier_app_fw_version; 403 u8 smart_carrier_bootloader_fw_version; 404 u8 SanitizeSecureEraseSupport; 405 u8 DriveKeyFlags; 406 u8 encryption_key_name[64]; 407 u32 misc_drive_flags; 408 u16 dek_index; 409 u16 drive_encryption_flags; 410 u8 sanitize_maximum_time[6]; 411 u8 connector_info_mode; 412 u8 connector_info_number[4]; 413 u8 long_connector_name[64]; 414 u8 device_unique_identifier[16]; 415 u8 padto_2K[17]; 416 } __packed; 417 418 /* 419 * These macros convert from physical channels to virtual channels 420 */ 421 #define CONTAINER_CHANNEL (0) 422 #define NATIVE_CHANNEL (1) 423 #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL) 424 #define CONTAINER_TO_ID(cont) (cont) 425 #define CONTAINER_TO_LUN(cont) (0) 426 #define ENCLOSURE_CHANNEL (3) 427 428 #define PMC_DEVICE_S6 0x28b 429 #define PMC_DEVICE_S7 0x28c 430 #define PMC_DEVICE_S8 0x28d 431 432 #define aac_phys_to_logical(x) ((x)+1) 433 #define aac_logical_to_phys(x) ((x)?(x)-1:0) 434 435 /* 436 * These macros are for keeping track of 437 * character device state. 438 */ 439 #define AAC_CHARDEV_UNREGISTERED (-1) 440 #define AAC_CHARDEV_NEEDS_REINIT (-2) 441 442 /* #define AAC_DETAILED_STATUS_INFO */ 443 444 struct diskparm 445 { 446 int heads; 447 int sectors; 448 int cylinders; 449 }; 450 451 452 /* 453 * Firmware constants 454 */ 455 456 #define CT_NONE 0 457 #define CT_OK 218 458 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */ 459 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */ 460 461 /* 462 * Host side memory scatter gather list 463 * Used by the adapter for read, write, and readdirplus operations 464 * We have separate 32 and 64 bit version because even 465 * on 64 bit systems not all cards support the 64 bit version 466 */ 467 struct sgentry { 468 __le32 addr; /* 32-bit address. */ 469 __le32 count; /* Length. */ 470 }; 471 472 struct user_sgentry { 473 u32 addr; /* 32-bit address. */ 474 u32 count; /* Length. */ 475 }; 476 477 struct sgentry64 { 478 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 479 __le32 count; /* Length. */ 480 }; 481 482 struct user_sgentry64 { 483 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 484 u32 count; /* Length. */ 485 }; 486 487 struct sgentryraw { 488 __le32 next; /* reserved for F/W use */ 489 __le32 prev; /* reserved for F/W use */ 490 __le32 addr[2]; 491 __le32 count; 492 __le32 flags; /* reserved for F/W use */ 493 }; 494 495 struct user_sgentryraw { 496 u32 next; /* reserved for F/W use */ 497 u32 prev; /* reserved for F/W use */ 498 u32 addr[2]; 499 u32 count; 500 u32 flags; /* reserved for F/W use */ 501 }; 502 503 struct sge_ieee1212 { 504 u32 addrLow; 505 u32 addrHigh; 506 u32 length; 507 u32 flags; 508 }; 509 510 /* 511 * SGMAP 512 * 513 * This is the SGMAP structure for all commands that use 514 * 32-bit addressing. 515 */ 516 517 struct sgmap { 518 __le32 count; 519 struct sgentry sg[1]; 520 }; 521 522 struct user_sgmap { 523 u32 count; 524 struct user_sgentry sg[1]; 525 }; 526 527 struct sgmap64 { 528 __le32 count; 529 struct sgentry64 sg[1]; 530 }; 531 532 struct user_sgmap64 { 533 u32 count; 534 struct user_sgentry64 sg[1]; 535 }; 536 537 struct sgmapraw { 538 __le32 count; 539 struct sgentryraw sg[1]; 540 }; 541 542 struct user_sgmapraw { 543 u32 count; 544 struct user_sgentryraw sg[1]; 545 }; 546 547 struct creation_info 548 { 549 u8 buildnum; /* e.g., 588 */ 550 u8 usec; /* e.g., 588 */ 551 u8 via; /* e.g., 1 = FSU, 552 * 2 = API 553 */ 554 u8 year; /* e.g., 1997 = 97 */ 555 __le32 date; /* 556 * unsigned Month :4; // 1 - 12 557 * unsigned Day :6; // 1 - 32 558 * unsigned Hour :6; // 0 - 23 559 * unsigned Minute :6; // 0 - 60 560 * unsigned Second :6; // 0 - 60 561 */ 562 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */ 563 }; 564 565 566 /* 567 * Define all the constants needed for the communication interface 568 */ 569 570 /* 571 * Define how many queue entries each queue will have and the total 572 * number of entries for the entire communication interface. Also define 573 * how many queues we support. 574 * 575 * This has to match the controller 576 */ 577 578 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response 579 #define HOST_HIGH_CMD_ENTRIES 4 580 #define HOST_NORM_CMD_ENTRIES 8 581 #define ADAP_HIGH_CMD_ENTRIES 4 582 #define ADAP_NORM_CMD_ENTRIES 512 583 #define HOST_HIGH_RESP_ENTRIES 4 584 #define HOST_NORM_RESP_ENTRIES 512 585 #define ADAP_HIGH_RESP_ENTRIES 4 586 #define ADAP_NORM_RESP_ENTRIES 8 587 588 #define TOTAL_QUEUE_ENTRIES \ 589 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \ 590 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES) 591 592 593 /* 594 * Set the queues on a 16 byte alignment 595 */ 596 597 #define QUEUE_ALIGNMENT 16 598 599 /* 600 * The queue headers define the Communication Region queues. These 601 * are physically contiguous and accessible by both the adapter and the 602 * host. Even though all queue headers are in the same contiguous block 603 * they will be represented as individual units in the data structures. 604 */ 605 606 struct aac_entry { 607 __le32 size; /* Size in bytes of Fib which this QE points to */ 608 __le32 addr; /* Receiver address of the FIB */ 609 }; 610 611 /* 612 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped 613 * adjacently and in that order. 614 */ 615 616 struct aac_qhdr { 617 __le64 header_addr;/* Address to hand the adapter to access 618 to this queue head */ 619 __le32 *producer; /* The producer index for this queue (host address) */ 620 __le32 *consumer; /* The consumer index for this queue (host address) */ 621 }; 622 623 /* 624 * Define all the events which the adapter would like to notify 625 * the host of. 626 */ 627 628 #define HostNormCmdQue 1 /* Change in host normal priority command queue */ 629 #define HostHighCmdQue 2 /* Change in host high priority command queue */ 630 #define HostNormRespQue 3 /* Change in host normal priority response queue */ 631 #define HostHighRespQue 4 /* Change in host high priority response queue */ 632 #define AdapNormRespNotFull 5 633 #define AdapHighRespNotFull 6 634 #define AdapNormCmdNotFull 7 635 #define AdapHighCmdNotFull 8 636 #define SynchCommandComplete 9 637 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */ 638 639 /* 640 * Define all the events the host wishes to notify the 641 * adapter of. The first four values much match the Qid the 642 * corresponding queue. 643 */ 644 645 #define AdapNormCmdQue 2 646 #define AdapHighCmdQue 3 647 #define AdapNormRespQue 6 648 #define AdapHighRespQue 7 649 #define HostShutdown 8 650 #define HostPowerFail 9 651 #define FatalCommError 10 652 #define HostNormRespNotFull 11 653 #define HostHighRespNotFull 12 654 #define HostNormCmdNotFull 13 655 #define HostHighCmdNotFull 14 656 #define FastIo 15 657 #define AdapPrintfDone 16 658 659 /* 660 * Define all the queues that the adapter and host use to communicate 661 * Number them to match the physical queue layout. 662 */ 663 664 enum aac_queue_types { 665 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */ 666 HostHighCmdQueue, /* Adapter to host high priority command traffic */ 667 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */ 668 AdapHighCmdQueue, /* Host to adapter high priority command traffic */ 669 HostNormRespQueue, /* Adapter to host normal priority response traffic */ 670 HostHighRespQueue, /* Adapter to host high priority response traffic */ 671 AdapNormRespQueue, /* Host to adapter normal priority response traffic */ 672 AdapHighRespQueue /* Host to adapter high priority response traffic */ 673 }; 674 675 /* 676 * Assign type values to the FSA communication data structures 677 */ 678 679 #define FIB_MAGIC 0x0001 680 #define FIB_MAGIC2 0x0004 681 #define FIB_MAGIC2_64 0x0005 682 683 /* 684 * Define the priority levels the FSA communication routines support. 685 */ 686 687 #define FsaNormal 1 688 689 /* transport FIB header (PMC) */ 690 struct aac_fib_xporthdr { 691 __le64 HostAddress; /* FIB host address w/o xport header */ 692 __le32 Size; /* FIB size excluding xport header */ 693 __le32 Handle; /* driver handle to reference the FIB */ 694 __le64 Reserved[2]; 695 }; 696 697 #define ALIGN32 32 698 699 /* 700 * Define the FIB. The FIB is the where all the requested data and 701 * command information are put to the application on the FSA adapter. 702 */ 703 704 struct aac_fibhdr { 705 __le32 XferState; /* Current transfer state for this CCB */ 706 __le16 Command; /* Routing information for the destination */ 707 u8 StructType; /* Type FIB */ 708 u8 Unused; /* Unused */ 709 __le16 Size; /* Size of this FIB in bytes */ 710 __le16 SenderSize; /* Size of the FIB in the sender 711 (for response sizing) */ 712 __le32 SenderFibAddress; /* Host defined data in the FIB */ 713 union { 714 __le32 ReceiverFibAddress;/* Logical address of this FIB for 715 the adapter (old) */ 716 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */ 717 __le32 TimeStamp; /* otherwise timestamp for FW internal use */ 718 } u; 719 __le32 Handle; /* FIB handle used for MSGU commnunication */ 720 u32 Previous; /* FW internal use */ 721 u32 Next; /* FW internal use */ 722 }; 723 724 struct hw_fib { 725 struct aac_fibhdr header; 726 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data 727 }; 728 729 /* 730 * FIB commands 731 */ 732 733 #define TestCommandResponse 1 734 #define TestAdapterCommand 2 735 /* 736 * Lowlevel and comm commands 737 */ 738 #define LastTestCommand 100 739 #define ReinitHostNormCommandQueue 101 740 #define ReinitHostHighCommandQueue 102 741 #define ReinitHostHighRespQueue 103 742 #define ReinitHostNormRespQueue 104 743 #define ReinitAdapNormCommandQueue 105 744 #define ReinitAdapHighCommandQueue 107 745 #define ReinitAdapHighRespQueue 108 746 #define ReinitAdapNormRespQueue 109 747 #define InterfaceShutdown 110 748 #define DmaCommandFib 120 749 #define StartProfile 121 750 #define TermProfile 122 751 #define SpeedTest 123 752 #define TakeABreakPt 124 753 #define RequestPerfData 125 754 #define SetInterruptDefTimer 126 755 #define SetInterruptDefCount 127 756 #define GetInterruptDefStatus 128 757 #define LastCommCommand 129 758 /* 759 * Filesystem commands 760 */ 761 #define NuFileSystem 300 762 #define UFS 301 763 #define HostFileSystem 302 764 #define LastFileSystemCommand 303 765 /* 766 * Container Commands 767 */ 768 #define ContainerCommand 500 769 #define ContainerCommand64 501 770 #define ContainerRawIo 502 771 #define ContainerRawIo2 503 772 /* 773 * Scsi Port commands (scsi passthrough) 774 */ 775 #define ScsiPortCommand 600 776 #define ScsiPortCommand64 601 777 /* 778 * Misc house keeping and generic adapter initiated commands 779 */ 780 #define AifRequest 700 781 #define CheckRevision 701 782 #define FsaHostShutdown 702 783 #define RequestAdapterInfo 703 784 #define IsAdapterPaused 704 785 #define SendHostTime 705 786 #define RequestSupplementAdapterInfo 706 787 #define LastMiscCommand 707 788 789 /* 790 * Commands that will target the failover level on the FSA adapter 791 */ 792 793 enum fib_xfer_state { 794 HostOwned = (1<<0), 795 AdapterOwned = (1<<1), 796 FibInitialized = (1<<2), 797 FibEmpty = (1<<3), 798 AllocatedFromPool = (1<<4), 799 SentFromHost = (1<<5), 800 SentFromAdapter = (1<<6), 801 ResponseExpected = (1<<7), 802 NoResponseExpected = (1<<8), 803 AdapterProcessed = (1<<9), 804 HostProcessed = (1<<10), 805 HighPriority = (1<<11), 806 NormalPriority = (1<<12), 807 Async = (1<<13), 808 AsyncIo = (1<<13), // rpbfix: remove with new regime 809 PageFileIo = (1<<14), // rpbfix: remove with new regime 810 ShutdownRequest = (1<<15), 811 LazyWrite = (1<<16), // rpbfix: remove with new regime 812 AdapterMicroFib = (1<<17), 813 BIOSFibPath = (1<<18), 814 FastResponseCapable = (1<<19), 815 ApiFib = (1<<20), /* Its an API Fib */ 816 /* PMC NEW COMM: There is no more AIF data pending */ 817 NoMoreAifDataAvailable = (1<<21) 818 }; 819 820 /* 821 * The following defines needs to be updated any time there is an 822 * incompatible change made to the aac_init structure. 823 */ 824 825 #define ADAPTER_INIT_STRUCT_REVISION 3 826 #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science 827 #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */ 828 #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */ 829 #define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor 830 831 union aac_init 832 { 833 struct _r7 { 834 __le32 init_struct_revision; 835 __le32 no_of_msix_vectors; 836 __le32 fsrev; 837 __le32 comm_header_address; 838 __le32 fast_io_comm_area_address; 839 __le32 adapter_fibs_physical_address; 840 __le32 adapter_fibs_virtual_address; 841 __le32 adapter_fibs_size; 842 __le32 adapter_fib_align; 843 __le32 printfbuf; 844 __le32 printfbufsiz; 845 /* number of 4k pages of host phys. mem. */ 846 __le32 host_phys_mem_pages; 847 /* number of seconds since 1970. */ 848 __le32 host_elapsed_seconds; 849 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */ 850 __le32 init_flags; /* flags for supported features */ 851 #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001 852 #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010 853 #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020 854 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040 855 #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080 856 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100 857 #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400 858 __le32 max_io_commands; /* max outstanding commands */ 859 __le32 max_io_size; /* largest I/O command */ 860 __le32 max_fib_size; /* largest FIB to adapter */ 861 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */ 862 __le32 max_num_aif; /* max number of aif */ 863 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */ 864 /* Host RRQ (response queue) for SRC */ 865 __le32 host_rrq_addr_low; 866 __le32 host_rrq_addr_high; 867 } r7; 868 struct _r8 { 869 /* ADAPTER_INIT_STRUCT_REVISION_8 */ 870 __le32 init_struct_revision; 871 __le32 rr_queue_count; 872 __le32 host_elapsed_seconds; /* number of secs since 1970. */ 873 __le32 init_flags; 874 __le32 max_io_size; /* largest I/O command */ 875 __le32 max_num_aif; /* max number of aif */ 876 __le32 reserved1; 877 __le32 reserved2; 878 struct _rrq { 879 __le32 host_addr_low; 880 __le32 host_addr_high; 881 __le16 msix_id; 882 __le16 element_count; 883 __le16 comp_thresh; 884 __le16 unused; 885 } rrq[1]; /* up to 64 RRQ addresses */ 886 } r8; 887 }; 888 889 enum aac_log_level { 890 LOG_AAC_INIT = 10, 891 LOG_AAC_INFORMATIONAL = 20, 892 LOG_AAC_WARNING = 30, 893 LOG_AAC_LOW_ERROR = 40, 894 LOG_AAC_MEDIUM_ERROR = 50, 895 LOG_AAC_HIGH_ERROR = 60, 896 LOG_AAC_PANIC = 70, 897 LOG_AAC_DEBUG = 80, 898 LOG_AAC_WINDBG_PRINT = 90 899 }; 900 901 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b 902 #define FSAFS_NTC_FIB_CONTEXT 0x030c 903 904 struct aac_dev; 905 struct fib; 906 struct scsi_cmnd; 907 908 struct adapter_ops 909 { 910 /* Low level operations */ 911 void (*adapter_interrupt)(struct aac_dev *dev); 912 void (*adapter_notify)(struct aac_dev *dev, u32 event); 913 void (*adapter_disable_int)(struct aac_dev *dev); 914 void (*adapter_enable_int)(struct aac_dev *dev); 915 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4); 916 int (*adapter_check_health)(struct aac_dev *dev); 917 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type); 918 void (*adapter_start)(struct aac_dev *dev); 919 /* Transport operations */ 920 int (*adapter_ioremap)(struct aac_dev * dev, u32 size); 921 irq_handler_t adapter_intr; 922 /* Packet operations */ 923 int (*adapter_deliver)(struct fib * fib); 924 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba); 925 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count); 926 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua); 927 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd); 928 /* Administrative operations */ 929 int (*adapter_comm)(struct aac_dev * dev, int comm); 930 }; 931 932 /* 933 * Define which interrupt handler needs to be installed 934 */ 935 936 struct aac_driver_ident 937 { 938 int (*init)(struct aac_dev *dev); 939 char * name; 940 char * vname; 941 char * model; 942 u16 channels; 943 int quirks; 944 }; 945 /* 946 * Some adapter firmware needs communication memory 947 * below 2gig. This tells the init function to set the 948 * dma mask such that fib memory will be allocated where the 949 * adapter firmware can get to it. 950 */ 951 #define AAC_QUIRK_31BIT 0x0001 952 953 /* 954 * Some adapter firmware, when the raid card's cache is turned off, can not 955 * split up scatter gathers in order to deal with the limits of the 956 * underlying CHIM. This limit is 34 scatter gather elements. 957 */ 958 #define AAC_QUIRK_34SG 0x0002 959 960 /* 961 * This adapter is a slave (no Firmware) 962 */ 963 #define AAC_QUIRK_SLAVE 0x0004 964 965 /* 966 * This adapter is a master. 967 */ 968 #define AAC_QUIRK_MASTER 0x0008 969 970 /* 971 * Some adapter firmware perform poorly when it must split up scatter gathers 972 * in order to deal with the limits of the underlying CHIM. This limit in this 973 * class of adapters is 17 scatter gather elements. 974 */ 975 #define AAC_QUIRK_17SG 0x0010 976 977 /* 978 * Some adapter firmware does not support 64 bit scsi passthrough 979 * commands. 980 */ 981 #define AAC_QUIRK_SCSI_32 0x0020 982 983 /* 984 * SRC based adapters support the AifReqEvent functions 985 */ 986 #define AAC_QUIRK_SRC 0x0040 987 988 /* 989 * The adapter interface specs all queues to be located in the same 990 * physically contiguous block. The host structure that defines the 991 * commuication queues will assume they are each a separate physically 992 * contiguous memory region that will support them all being one big 993 * contiguous block. 994 * There is a command and response queue for each level and direction of 995 * commuication. These regions are accessed by both the host and adapter. 996 */ 997 998 struct aac_queue { 999 u64 logical; /*address we give the adapter */ 1000 struct aac_entry *base; /*system virtual address */ 1001 struct aac_qhdr headers; /*producer,consumer q headers*/ 1002 u32 entries; /*Number of queue entries */ 1003 wait_queue_head_t qfull; /*Event to wait on if q full */ 1004 wait_queue_head_t cmdready; /*Cmd ready from the adapter */ 1005 /* This is only valid for adapter to host command queues. */ 1006 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */ 1007 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */ 1008 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */ 1009 /* only valid for command queues which receive entries from the adapter. */ 1010 /* Number of entries on outstanding queue. */ 1011 atomic_t numpending; 1012 struct aac_dev * dev; /* Back pointer to adapter structure */ 1013 }; 1014 1015 /* 1016 * Message queues. The order here is important, see also the 1017 * queue type ordering 1018 */ 1019 1020 struct aac_queue_block 1021 { 1022 struct aac_queue queue[8]; 1023 }; 1024 1025 /* 1026 * SaP1 Message Unit Registers 1027 */ 1028 1029 struct sa_drawbridge_CSR { 1030 /* Offset | Name */ 1031 __le32 reserved[10]; /* 00h-27h | Reserved */ 1032 u8 LUT_Offset; /* 28h | Lookup Table Offset */ 1033 u8 reserved1[3]; /* 29h-2bh | Reserved */ 1034 __le32 LUT_Data; /* 2ch | Looup Table Data */ 1035 __le32 reserved2[26]; /* 30h-97h | Reserved */ 1036 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */ 1037 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */ 1038 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */ 1039 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */ 1040 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */ 1041 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */ 1042 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */ 1043 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */ 1044 __le32 MAILBOX0; /* a8h | Scratchpad 0 */ 1045 __le32 MAILBOX1; /* ach | Scratchpad 1 */ 1046 __le32 MAILBOX2; /* b0h | Scratchpad 2 */ 1047 __le32 MAILBOX3; /* b4h | Scratchpad 3 */ 1048 __le32 MAILBOX4; /* b8h | Scratchpad 4 */ 1049 __le32 MAILBOX5; /* bch | Scratchpad 5 */ 1050 __le32 MAILBOX6; /* c0h | Scratchpad 6 */ 1051 __le32 MAILBOX7; /* c4h | Scratchpad 7 */ 1052 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */ 1053 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */ 1054 __le32 reserved3[12]; /* d0h-ffh | reserved */ 1055 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */ 1056 }; 1057 1058 #define Mailbox0 SaDbCSR.MAILBOX0 1059 #define Mailbox1 SaDbCSR.MAILBOX1 1060 #define Mailbox2 SaDbCSR.MAILBOX2 1061 #define Mailbox3 SaDbCSR.MAILBOX3 1062 #define Mailbox4 SaDbCSR.MAILBOX4 1063 #define Mailbox5 SaDbCSR.MAILBOX5 1064 #define Mailbox6 SaDbCSR.MAILBOX6 1065 #define Mailbox7 SaDbCSR.MAILBOX7 1066 1067 #define DoorbellReg_p SaDbCSR.PRISETIRQ 1068 #define DoorbellReg_s SaDbCSR.SECSETIRQ 1069 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ 1070 1071 1072 #define DOORBELL_0 0x0001 1073 #define DOORBELL_1 0x0002 1074 #define DOORBELL_2 0x0004 1075 #define DOORBELL_3 0x0008 1076 #define DOORBELL_4 0x0010 1077 #define DOORBELL_5 0x0020 1078 #define DOORBELL_6 0x0040 1079 1080 1081 #define PrintfReady DOORBELL_5 1082 #define PrintfDone DOORBELL_5 1083 1084 struct sa_registers { 1085 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */ 1086 }; 1087 1088 1089 #define SA_INIT_NUM_MSIXVECTORS 1 1090 #define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS 1091 1092 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 1093 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 1094 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) 1095 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) 1096 1097 /* 1098 * Rx Message Unit Registers 1099 */ 1100 1101 struct rx_mu_registers { 1102 /* Local | PCI*| Name */ 1103 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */ 1104 __le32 reserved0; /* 1304h | 04h | Reserved */ 1105 __le32 AWR; /* 1308h | 08h | APIC Window Register */ 1106 __le32 reserved1; /* 130Ch | 0Ch | Reserved */ 1107 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */ 1108 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */ 1109 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */ 1110 __le32 IISR; /* 1324h | 24h | Inbound Interrupt 1111 Status Register */ 1112 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt 1113 Mask Register */ 1114 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */ 1115 __le32 OISR; /* 1330h | 30h | Outbound Interrupt 1116 Status Register */ 1117 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt 1118 Mask Register */ 1119 __le32 reserved2; /* 1338h | 38h | Reserved */ 1120 __le32 reserved3; /* 133Ch | 3Ch | Reserved */ 1121 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */ 1122 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */ 1123 /* * Must access through ATU Inbound 1124 Translation Window */ 1125 }; 1126 1127 struct rx_inbound { 1128 __le32 Mailbox[8]; 1129 }; 1130 1131 #define INBOUNDDOORBELL_0 0x00000001 1132 #define INBOUNDDOORBELL_1 0x00000002 1133 #define INBOUNDDOORBELL_2 0x00000004 1134 #define INBOUNDDOORBELL_3 0x00000008 1135 #define INBOUNDDOORBELL_4 0x00000010 1136 #define INBOUNDDOORBELL_5 0x00000020 1137 #define INBOUNDDOORBELL_6 0x00000040 1138 1139 #define OUTBOUNDDOORBELL_0 0x00000001 1140 #define OUTBOUNDDOORBELL_1 0x00000002 1141 #define OUTBOUNDDOORBELL_2 0x00000004 1142 #define OUTBOUNDDOORBELL_3 0x00000008 1143 #define OUTBOUNDDOORBELL_4 0x00000010 1144 1145 #define InboundDoorbellReg MUnit.IDR 1146 #define OutboundDoorbellReg MUnit.ODR 1147 1148 struct rx_registers { 1149 struct rx_mu_registers MUnit; /* 1300h - 1347h */ 1150 __le32 reserved1[2]; /* 1348h - 134ch */ 1151 struct rx_inbound IndexRegs; 1152 }; 1153 1154 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) 1155 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) 1156 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) 1157 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) 1158 1159 /* 1160 * Rkt Message Unit Registers (same as Rx, except a larger reserve region) 1161 */ 1162 1163 #define rkt_mu_registers rx_mu_registers 1164 #define rkt_inbound rx_inbound 1165 1166 struct rkt_registers { 1167 struct rkt_mu_registers MUnit; /* 1300h - 1347h */ 1168 __le32 reserved1[1006]; /* 1348h - 22fch */ 1169 struct rkt_inbound IndexRegs; /* 2300h - */ 1170 }; 1171 1172 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) 1173 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) 1174 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR)) 1175 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR)) 1176 1177 /* 1178 * PMC SRC message unit registers 1179 */ 1180 1181 #define src_inbound rx_inbound 1182 1183 struct src_mu_registers { 1184 /* PCI*| Name */ 1185 __le32 reserved0[6]; /* 00h | Reserved */ 1186 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */ 1187 __le32 IDR; /* 20h | Inbound Doorbell Register */ 1188 __le32 IISR; /* 24h | Inbound Int. Status Register */ 1189 __le32 reserved1[3]; /* 28h | Reserved */ 1190 __le32 OIMR; /* 34h | Outbound Int. Mask Register */ 1191 __le32 reserved2[25]; /* 38h | Reserved */ 1192 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */ 1193 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */ 1194 __le32 reserved3[3]; /* a4h | Reserved */ 1195 __le32 SCR0; /* b0h | Scratchpad 0 */ 1196 __le32 reserved4[2]; /* b4h | Reserved */ 1197 __le32 OMR; /* bch | Outbound Message Register */ 1198 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */ 1199 __le32 IQ_H; /* c4h | Inbound Queue (High address) */ 1200 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */ 1201 __le32 reserved5; /* cch | Reserved */ 1202 __le32 IQN_L; /* d0h | Inbound (native cmd) low */ 1203 __le32 IQN_H; /* d4h | Inbound (native cmd) high */ 1204 }; 1205 1206 struct src_registers { 1207 struct src_mu_registers MUnit; /* 00h - cbh */ 1208 union { 1209 struct { 1210 __le32 reserved1[130786]; /* d8h - 7fc5fh */ 1211 struct src_inbound IndexRegs; /* 7fc60h */ 1212 } tupelo; 1213 struct { 1214 __le32 reserved1[970]; /* d8h - fffh */ 1215 struct src_inbound IndexRegs; /* 1000h */ 1216 } denali; 1217 } u; 1218 }; 1219 1220 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR)) 1221 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR)) 1222 #define src_writeb(AEP, CSR, value) writeb(value, \ 1223 &((AEP)->regs.src.bar0->CSR)) 1224 #define src_writel(AEP, CSR, value) writel(value, \ 1225 &((AEP)->regs.src.bar0->CSR)) 1226 #if defined(writeq) 1227 #define src_writeq(AEP, CSR, value) writeq(value, \ 1228 &((AEP)->regs.src.bar0->CSR)) 1229 #endif 1230 1231 #define SRC_ODR_SHIFT 12 1232 #define SRC_IDR_SHIFT 9 1233 1234 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx); 1235 1236 struct aac_fib_context { 1237 s16 type; // used for verification of structure 1238 s16 size; 1239 u32 unique; // unique value representing this context 1240 ulong jiffies; // used for cleanup - dmb changed to ulong 1241 struct list_head next; // used to link context's into a linked list 1242 struct semaphore wait_sem; // this is used to wait for the next fib to arrive. 1243 int wait; // Set to true when thread is in WaitForSingleObject 1244 unsigned long count; // total number of FIBs on FibList 1245 struct list_head fib_list; // this holds fibs and their attachd hw_fibs 1246 }; 1247 1248 struct sense_data { 1249 u8 error_code; /* 70h (current errors), 71h(deferred errors) */ 1250 u8 valid:1; /* A valid bit of one indicates that the information */ 1251 /* field contains valid information as defined in the 1252 * SCSI-2 Standard. 1253 */ 1254 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */ 1255 u8 sense_key:4; /* Sense Key */ 1256 u8 reserved:1; 1257 u8 ILI:1; /* Incorrect Length Indicator */ 1258 u8 EOM:1; /* End Of Medium - reserved for random access devices */ 1259 u8 filemark:1; /* Filemark - reserved for random access devices */ 1260 1261 u8 information[4]; /* for direct-access devices, contains the unsigned 1262 * logical block address or residue associated with 1263 * the sense key 1264 */ 1265 u8 add_sense_len; /* number of additional sense bytes to follow this field */ 1266 u8 cmnd_info[4]; /* not used */ 1267 u8 ASC; /* Additional Sense Code */ 1268 u8 ASCQ; /* Additional Sense Code Qualifier */ 1269 u8 FRUC; /* Field Replaceable Unit Code - not used */ 1270 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data 1271 * was in error 1272 */ 1273 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that 1274 * the bit_ptr field has valid value 1275 */ 1276 u8 reserved2:2; 1277 u8 CD:1; /* command data bit: 1- illegal parameter in CDB. 1278 * 0- illegal parameter in data. 1279 */ 1280 u8 SKSV:1; 1281 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */ 1282 }; 1283 1284 struct fsa_dev_info { 1285 u64 last; 1286 u64 size; 1287 u32 type; 1288 u32 config_waiting_on; 1289 unsigned long config_waiting_stamp; 1290 u16 queue_depth; 1291 u8 config_needed; 1292 u8 valid; 1293 u8 ro; 1294 u8 locked; 1295 u8 deleted; 1296 char devname[8]; 1297 struct sense_data sense_data; 1298 u32 block_size; 1299 u8 identifier[16]; 1300 }; 1301 1302 struct fib { 1303 void *next; /* this is used by the allocator */ 1304 s16 type; 1305 s16 size; 1306 /* 1307 * The Adapter that this I/O is destined for. 1308 */ 1309 struct aac_dev *dev; 1310 /* 1311 * This is the event the sendfib routine will wait on if the 1312 * caller did not pass one and this is synch io. 1313 */ 1314 struct semaphore event_wait; 1315 spinlock_t event_lock; 1316 1317 u32 done; /* gets set to 1 when fib is complete */ 1318 fib_callback callback; 1319 void *callback_data; 1320 u32 flags; // u32 dmb was ulong 1321 /* 1322 * And for the internal issue/reply queues (we may be able 1323 * to merge these two) 1324 */ 1325 struct list_head fiblink; 1326 void *data; 1327 u32 vector_no; 1328 struct hw_fib *hw_fib_va; /* also used for native */ 1329 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/ 1330 dma_addr_t hw_sgl_pa; /* extra sgl for native */ 1331 dma_addr_t hw_error_pa; /* error buffer for native */ 1332 u32 hbacmd_size; /* cmd size for native */ 1333 }; 1334 1335 #define AAC_INIT 0 1336 #define AAC_RESCAN 1 1337 1338 #define AAC_DEVTYPE_RAID_MEMBER 1 1339 #define AAC_DEVTYPE_ARC_RAW 2 1340 #define AAC_DEVTYPE_NATIVE_RAW 3 1341 #define AAC_EXPOSE_DISK 0 1342 #define AAC_HIDE_DISK 3 1343 1344 #define AAC_SAFW_RESCAN_DELAY 10 1345 1346 struct aac_hba_map_info { 1347 __le32 rmw_nexus; /* nexus for native HBA devices */ 1348 u8 devtype; /* device type */ 1349 u8 reset_state; /* 0 - no reset, 1..x - */ 1350 /* after xth TM LUN reset */ 1351 u16 qd_limit; 1352 u8 expose; /*checks if to expose or not*/ 1353 u32 scan_counter; 1354 struct aac_ciss_identify_pd *safw_identify_resp; 1355 }; 1356 1357 /* 1358 * Adapter Information Block 1359 * 1360 * This is returned by the RequestAdapterInfo block 1361 */ 1362 1363 struct aac_adapter_info 1364 { 1365 __le32 platform; 1366 __le32 cpu; 1367 __le32 subcpu; 1368 __le32 clock; 1369 __le32 execmem; 1370 __le32 buffermem; 1371 __le32 totalmem; 1372 __le32 kernelrev; 1373 __le32 kernelbuild; 1374 __le32 monitorrev; 1375 __le32 monitorbuild; 1376 __le32 hwrev; 1377 __le32 hwbuild; 1378 __le32 biosrev; 1379 __le32 biosbuild; 1380 __le32 cluster; 1381 __le32 clusterchannelmask; 1382 __le32 serial[2]; 1383 __le32 battery; 1384 __le32 options; 1385 __le32 OEM; 1386 }; 1387 1388 struct aac_supplement_adapter_info 1389 { 1390 u8 adapter_type_text[17+1]; 1391 u8 pad[2]; 1392 __le32 flash_memory_byte_size; 1393 __le32 flash_image_id; 1394 __le32 max_number_ports; 1395 __le32 version; 1396 __le32 feature_bits; 1397 u8 slot_number; 1398 u8 reserved_pad0[3]; 1399 u8 build_date[12]; 1400 __le32 current_number_ports; 1401 struct { 1402 u8 assembly_pn[8]; 1403 u8 fru_pn[8]; 1404 u8 battery_fru_pn[8]; 1405 u8 ec_version_string[8]; 1406 u8 tsid[12]; 1407 } vpd_info; 1408 __le32 flash_firmware_revision; 1409 __le32 flash_firmware_build; 1410 __le32 raid_type_morph_options; 1411 __le32 flash_firmware_boot_revision; 1412 __le32 flash_firmware_boot_build; 1413 u8 mfg_pcba_serial_no[12]; 1414 u8 mfg_wwn_name[8]; 1415 __le32 supported_options2; 1416 __le32 struct_expansion; 1417 /* StructExpansion == 1 */ 1418 __le32 feature_bits3; 1419 __le32 supported_performance_modes; 1420 u8 host_bus_type; /* uses HOST_BUS_TYPE_xxx defines */ 1421 u8 host_bus_width; /* actual width in bits or links */ 1422 u16 host_bus_speed; /* actual bus speed/link rate in MHz */ 1423 u8 max_rrc_drives; /* max. number of ITP-RRC drives/pool */ 1424 u8 max_disk_xtasks; /* max. possible num of DiskX Tasks */ 1425 1426 u8 cpld_ver_loaded; 1427 u8 cpld_ver_in_flash; 1428 1429 __le64 max_rrc_capacity; 1430 __le32 compiled_max_hist_log_level; 1431 u8 custom_board_name[12]; 1432 u16 supported_cntlr_mode; /* identify supported controller mode */ 1433 u16 reserved_for_future16; 1434 __le32 supported_options3; /* reserved for future options */ 1435 1436 __le16 virt_device_bus; /* virt. SCSI device for Thor */ 1437 __le16 virt_device_target; 1438 __le16 virt_device_lun; 1439 __le16 unused; 1440 __le32 reserved_for_future_growth[68]; 1441 1442 }; 1443 #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010) 1444 #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000) 1445 /* SupportedOptions2 */ 1446 #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001) 1447 #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002) 1448 #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004) 1449 #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000) 1450 /* 4KB sector size */ 1451 #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000) 1452 /* 240 simple volume support */ 1453 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000) 1454 /* 1455 * Supports FIB dump sync command send prior to IOP_RESET 1456 */ 1457 #define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000) 1458 #define AAC_SIS_VERSION_V3 3 1459 #define AAC_SIS_SLOT_UNKNOWN 0xFF 1460 1461 #define GetBusInfo 0x00000009 1462 struct aac_bus_info { 1463 __le32 Command; /* VM_Ioctl */ 1464 __le32 ObjType; /* FT_DRIVE */ 1465 __le32 MethodId; /* 1 = SCSI Layer */ 1466 __le32 ObjectId; /* Handle */ 1467 __le32 CtlCmd; /* GetBusInfo */ 1468 }; 1469 1470 struct aac_bus_info_response { 1471 __le32 Status; /* ST_OK */ 1472 __le32 ObjType; 1473 __le32 MethodId; /* unused */ 1474 __le32 ObjectId; /* unused */ 1475 __le32 CtlCmd; /* unused */ 1476 __le32 ProbeComplete; 1477 __le32 BusCount; 1478 __le32 TargetsPerBus; 1479 u8 InitiatorBusId[10]; 1480 u8 BusValid[10]; 1481 }; 1482 1483 /* 1484 * Battery platforms 1485 */ 1486 #define AAC_BAT_REQ_PRESENT (1) 1487 #define AAC_BAT_REQ_NOTPRESENT (2) 1488 #define AAC_BAT_OPT_PRESENT (3) 1489 #define AAC_BAT_OPT_NOTPRESENT (4) 1490 #define AAC_BAT_NOT_SUPPORTED (5) 1491 /* 1492 * cpu types 1493 */ 1494 #define AAC_CPU_SIMULATOR (1) 1495 #define AAC_CPU_I960 (2) 1496 #define AAC_CPU_STRONGARM (3) 1497 1498 /* 1499 * Supported Options 1500 */ 1501 #define AAC_OPT_SNAPSHOT cpu_to_le32(1) 1502 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1) 1503 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2) 1504 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3) 1505 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4) 1506 #define AAC_OPT_RAID50 cpu_to_le32(1<<5) 1507 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6) 1508 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7) 1509 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8) 1510 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9) 1511 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10) 1512 #define AAC_OPT_ALARM cpu_to_le32(1<<11) 1513 #define AAC_OPT_NONDASD cpu_to_le32(1<<12) 1514 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13) 1515 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14) 1516 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16) 1517 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17) 1518 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18) 1519 #define AAC_OPT_EXTENDED cpu_to_le32(1<<23) 1520 #define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25) 1521 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28) 1522 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29) 1523 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30) 1524 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31) 1525 1526 #define AAC_COMM_PRODUCER 0 1527 #define AAC_COMM_MESSAGE 1 1528 #define AAC_COMM_MESSAGE_TYPE1 3 1529 #define AAC_COMM_MESSAGE_TYPE2 4 1530 #define AAC_COMM_MESSAGE_TYPE3 5 1531 1532 #define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1) 1533 1534 /* MSIX context */ 1535 struct aac_msix_ctx { 1536 int vector_no; 1537 struct aac_dev *dev; 1538 }; 1539 1540 struct aac_dev 1541 { 1542 struct list_head entry; 1543 const char *name; 1544 int id; 1545 1546 /* 1547 * negotiated FIB settings 1548 */ 1549 unsigned int max_fib_size; 1550 unsigned int sg_tablesize; 1551 unsigned int max_num_aif; 1552 1553 unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */ 1554 1555 /* 1556 * Map for 128 fib objects (64k) 1557 */ 1558 dma_addr_t hw_fib_pa; /* also used for native cmd */ 1559 struct hw_fib *hw_fib_va; /* also used for native cmd */ 1560 struct hw_fib *aif_base_va; 1561 /* 1562 * Fib Headers 1563 */ 1564 struct fib *fibs; 1565 1566 struct fib *free_fib; 1567 spinlock_t fib_lock; 1568 1569 struct mutex ioctl_mutex; 1570 struct mutex scan_mutex; 1571 struct aac_queue_block *queues; 1572 /* 1573 * The user API will use an IOCTL to register itself to receive 1574 * FIBs from the adapter. The following list is used to keep 1575 * track of all the threads that have requested these FIBs. The 1576 * mutex is used to synchronize access to all data associated 1577 * with the adapter fibs. 1578 */ 1579 struct list_head fib_list; 1580 1581 struct adapter_ops a_ops; 1582 unsigned long fsrev; /* Main driver's revision number */ 1583 1584 resource_size_t base_start; /* main IO base */ 1585 resource_size_t dbg_base; /* address of UART 1586 * debug buffer */ 1587 1588 resource_size_t base_size, dbg_size; /* Size of 1589 * mapped in region */ 1590 /* 1591 * Holds initialization info 1592 * to communicate with adapter 1593 */ 1594 union aac_init *init; 1595 dma_addr_t init_pa; /* Holds physical address of the init struct */ 1596 /* response queue (if AAC_COMM_MESSAGE_TYPE1) */ 1597 __le32 *host_rrq; 1598 dma_addr_t host_rrq_pa; /* phys. address */ 1599 /* index into rrq buffer */ 1600 u32 host_rrq_idx[AAC_MAX_MSIX]; 1601 atomic_t rrq_outstanding[AAC_MAX_MSIX]; 1602 u32 fibs_pushed_no; 1603 struct pci_dev *pdev; /* Our PCI interface */ 1604 /* pointer to buffer used for printf's from the adapter */ 1605 void *printfbuf; 1606 void *comm_addr; /* Base address of Comm area */ 1607 dma_addr_t comm_phys; /* Physical Address of Comm area */ 1608 size_t comm_size; 1609 1610 struct Scsi_Host *scsi_host_ptr; 1611 int maximum_num_containers; 1612 int maximum_num_physicals; 1613 int maximum_num_channels; 1614 struct fsa_dev_info *fsa_dev; 1615 struct task_struct *thread; 1616 struct delayed_work safw_rescan_work; 1617 int cardtype; 1618 /* 1619 *This lock will protect the two 32-bit 1620 *writes to the Inbound Queue 1621 */ 1622 spinlock_t iq_lock; 1623 1624 /* 1625 * The following is the device specific extension. 1626 */ 1627 #ifndef AAC_MIN_FOOTPRINT_SIZE 1628 # define AAC_MIN_FOOTPRINT_SIZE 8192 1629 # define AAC_MIN_SRC_BAR0_SIZE 0x400000 1630 # define AAC_MIN_SRC_BAR1_SIZE 0x800 1631 # define AAC_MIN_SRCV_BAR0_SIZE 0x100000 1632 # define AAC_MIN_SRCV_BAR1_SIZE 0x400 1633 #endif 1634 union 1635 { 1636 struct sa_registers __iomem *sa; 1637 struct rx_registers __iomem *rx; 1638 struct rkt_registers __iomem *rkt; 1639 struct { 1640 struct src_registers __iomem *bar0; 1641 char __iomem *bar1; 1642 } src; 1643 } regs; 1644 volatile void __iomem *base, *dbg_base_mapped; 1645 volatile struct rx_inbound __iomem *IndexRegs; 1646 u32 OIMR; /* Mask Register Cache */ 1647 /* 1648 * AIF thread states 1649 */ 1650 u32 aif_thread; 1651 struct aac_adapter_info adapter_info; 1652 struct aac_supplement_adapter_info supplement_adapter_info; 1653 /* These are in adapter info but they are in the io flow so 1654 * lets break them out so we don't have to do an AND to check them 1655 */ 1656 u8 nondasd_support; 1657 u8 jbod; 1658 u8 cache_protected; 1659 u8 dac_support; 1660 u8 needs_dac; 1661 u8 raid_scsi_mode; 1662 u8 comm_interface; 1663 u8 raw_io_interface; 1664 u8 raw_io_64; 1665 u8 printf_enabled; 1666 u8 in_reset; 1667 u8 msi; 1668 u8 sa_firmware; 1669 int management_fib_count; 1670 spinlock_t manage_lock; 1671 spinlock_t sync_lock; 1672 int sync_mode; 1673 struct fib *sync_fib; 1674 struct list_head sync_fib_list; 1675 u32 doorbell_mask; 1676 u32 max_msix; /* max. MSI-X vectors */ 1677 u32 vector_cap; /* MSI-X vector capab.*/ 1678 int msi_enabled; /* MSI/MSI-X enabled */ 1679 atomic_t msix_counter; 1680 u32 scan_counter; 1681 struct msix_entry msixentry[AAC_MAX_MSIX]; 1682 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */ 1683 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS]; 1684 struct aac_ciss_phys_luns_resp *safw_phys_luns; 1685 u8 adapter_shutdown; 1686 u32 handle_pci_error; 1687 }; 1688 1689 #define aac_adapter_interrupt(dev) \ 1690 (dev)->a_ops.adapter_interrupt(dev) 1691 1692 #define aac_adapter_notify(dev, event) \ 1693 (dev)->a_ops.adapter_notify(dev, event) 1694 1695 #define aac_adapter_disable_int(dev) \ 1696 (dev)->a_ops.adapter_disable_int(dev) 1697 1698 #define aac_adapter_enable_int(dev) \ 1699 (dev)->a_ops.adapter_enable_int(dev) 1700 1701 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \ 1702 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) 1703 1704 #define aac_adapter_restart(dev, bled, reset_type) \ 1705 ((dev)->a_ops.adapter_restart(dev, bled, reset_type)) 1706 1707 #define aac_adapter_start(dev) \ 1708 ((dev)->a_ops.adapter_start(dev)) 1709 1710 #define aac_adapter_ioremap(dev, size) \ 1711 (dev)->a_ops.adapter_ioremap(dev, size) 1712 1713 #define aac_adapter_deliver(fib) \ 1714 ((fib)->dev)->a_ops.adapter_deliver(fib) 1715 1716 #define aac_adapter_bounds(dev,cmd,lba) \ 1717 dev->a_ops.adapter_bounds(dev,cmd,lba) 1718 1719 #define aac_adapter_read(fib,cmd,lba,count) \ 1720 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count) 1721 1722 #define aac_adapter_write(fib,cmd,lba,count,fua) \ 1723 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua) 1724 1725 #define aac_adapter_scsi(fib,cmd) \ 1726 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd) 1727 1728 #define aac_adapter_comm(dev,comm) \ 1729 (dev)->a_ops.adapter_comm(dev, comm) 1730 1731 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001) 1732 #define FIB_CONTEXT_FLAG (0x00000002) 1733 #define FIB_CONTEXT_FLAG_WAIT (0x00000004) 1734 #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008) 1735 #define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010) 1736 #define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020) 1737 #define FIB_CONTEXT_FLAG_SCSI_CMD (0x00000040) 1738 1739 /* 1740 * Define the command values 1741 */ 1742 1743 #define Null 0 1744 #define GetAttributes 1 1745 #define SetAttributes 2 1746 #define Lookup 3 1747 #define ReadLink 4 1748 #define Read 5 1749 #define Write 6 1750 #define Create 7 1751 #define MakeDirectory 8 1752 #define SymbolicLink 9 1753 #define MakeNode 10 1754 #define Removex 11 1755 #define RemoveDirectoryx 12 1756 #define Rename 13 1757 #define Link 14 1758 #define ReadDirectory 15 1759 #define ReadDirectoryPlus 16 1760 #define FileSystemStatus 17 1761 #define FileSystemInfo 18 1762 #define PathConfigure 19 1763 #define Commit 20 1764 #define Mount 21 1765 #define UnMount 22 1766 #define Newfs 23 1767 #define FsCheck 24 1768 #define FsSync 25 1769 #define SimReadWrite 26 1770 #define SetFileSystemStatus 27 1771 #define BlockRead 28 1772 #define BlockWrite 29 1773 #define NvramIoctl 30 1774 #define FsSyncWait 31 1775 #define ClearArchiveBit 32 1776 #define SetAcl 33 1777 #define GetAcl 34 1778 #define AssignAcl 35 1779 #define FaultInsertion 36 /* Fault Insertion Command */ 1780 #define CrazyCache 37 /* Crazycache */ 1781 1782 #define MAX_FSACOMMAND_NUM 38 1783 1784 1785 /* 1786 * Define the status returns. These are very unixlike although 1787 * most are not in fact used 1788 */ 1789 1790 #define ST_OK 0 1791 #define ST_PERM 1 1792 #define ST_NOENT 2 1793 #define ST_IO 5 1794 #define ST_NXIO 6 1795 #define ST_E2BIG 7 1796 #define ST_MEDERR 8 1797 #define ST_ACCES 13 1798 #define ST_EXIST 17 1799 #define ST_XDEV 18 1800 #define ST_NODEV 19 1801 #define ST_NOTDIR 20 1802 #define ST_ISDIR 21 1803 #define ST_INVAL 22 1804 #define ST_FBIG 27 1805 #define ST_NOSPC 28 1806 #define ST_ROFS 30 1807 #define ST_MLINK 31 1808 #define ST_WOULDBLOCK 35 1809 #define ST_NAMETOOLONG 63 1810 #define ST_NOTEMPTY 66 1811 #define ST_DQUOT 69 1812 #define ST_STALE 70 1813 #define ST_REMOTE 71 1814 #define ST_NOT_READY 72 1815 #define ST_BADHANDLE 10001 1816 #define ST_NOT_SYNC 10002 1817 #define ST_BAD_COOKIE 10003 1818 #define ST_NOTSUPP 10004 1819 #define ST_TOOSMALL 10005 1820 #define ST_SERVERFAULT 10006 1821 #define ST_BADTYPE 10007 1822 #define ST_JUKEBOX 10008 1823 #define ST_NOTMOUNTED 10009 1824 #define ST_MAINTMODE 10010 1825 #define ST_STALEACL 10011 1826 1827 /* 1828 * On writes how does the client want the data written. 1829 */ 1830 1831 #define CACHE_CSTABLE 1 1832 #define CACHE_UNSTABLE 2 1833 1834 /* 1835 * Lets the client know at which level the data was committed on 1836 * a write request 1837 */ 1838 1839 #define CMFILE_SYNCH_NVRAM 1 1840 #define CMDATA_SYNCH_NVRAM 2 1841 #define CMFILE_SYNCH 3 1842 #define CMDATA_SYNCH 4 1843 #define CMUNSTABLE 5 1844 1845 #define RIO_TYPE_WRITE 0x0000 1846 #define RIO_TYPE_READ 0x0001 1847 #define RIO_SUREWRITE 0x0008 1848 1849 #define RIO2_IO_TYPE 0x0003 1850 #define RIO2_IO_TYPE_WRITE 0x0000 1851 #define RIO2_IO_TYPE_READ 0x0001 1852 #define RIO2_IO_TYPE_VERIFY 0x0002 1853 #define RIO2_IO_ERROR 0x0004 1854 #define RIO2_IO_SUREWRITE 0x0008 1855 #define RIO2_SGL_CONFORMANT 0x0010 1856 #define RIO2_SG_FORMAT 0xF000 1857 #define RIO2_SG_FORMAT_ARC 0x0000 1858 #define RIO2_SG_FORMAT_SRL 0x1000 1859 #define RIO2_SG_FORMAT_IEEE1212 0x2000 1860 1861 struct aac_read 1862 { 1863 __le32 command; 1864 __le32 cid; 1865 __le32 block; 1866 __le32 count; 1867 struct sgmap sg; // Must be last in struct because it is variable 1868 }; 1869 1870 struct aac_read64 1871 { 1872 __le32 command; 1873 __le16 cid; 1874 __le16 sector_count; 1875 __le32 block; 1876 __le16 pad; 1877 __le16 flags; 1878 struct sgmap64 sg; // Must be last in struct because it is variable 1879 }; 1880 1881 struct aac_read_reply 1882 { 1883 __le32 status; 1884 __le32 count; 1885 }; 1886 1887 struct aac_write 1888 { 1889 __le32 command; 1890 __le32 cid; 1891 __le32 block; 1892 __le32 count; 1893 __le32 stable; // Not used 1894 struct sgmap sg; // Must be last in struct because it is variable 1895 }; 1896 1897 struct aac_write64 1898 { 1899 __le32 command; 1900 __le16 cid; 1901 __le16 sector_count; 1902 __le32 block; 1903 __le16 pad; 1904 __le16 flags; 1905 struct sgmap64 sg; // Must be last in struct because it is variable 1906 }; 1907 struct aac_write_reply 1908 { 1909 __le32 status; 1910 __le32 count; 1911 __le32 committed; 1912 }; 1913 1914 struct aac_raw_io 1915 { 1916 __le32 block[2]; 1917 __le32 count; 1918 __le16 cid; 1919 __le16 flags; /* 00 W, 01 R */ 1920 __le16 bpTotal; /* reserved for F/W use */ 1921 __le16 bpComplete; /* reserved for F/W use */ 1922 struct sgmapraw sg; 1923 }; 1924 1925 struct aac_raw_io2 { 1926 __le32 blockLow; 1927 __le32 blockHigh; 1928 __le32 byteCount; 1929 __le16 cid; 1930 __le16 flags; /* RIO2 flags */ 1931 __le32 sgeFirstSize; /* size of first sge el. */ 1932 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */ 1933 u8 sgeCnt; /* only 8 bits required */ 1934 u8 bpTotal; /* reserved for F/W use */ 1935 u8 bpComplete; /* reserved for F/W use */ 1936 u8 sgeFirstIndex; /* reserved for F/W use */ 1937 u8 unused[4]; 1938 struct sge_ieee1212 sge[1]; 1939 }; 1940 1941 #define CT_FLUSH_CACHE 129 1942 struct aac_synchronize { 1943 __le32 command; /* VM_ContainerConfig */ 1944 __le32 type; /* CT_FLUSH_CACHE */ 1945 __le32 cid; 1946 __le32 parm1; 1947 __le32 parm2; 1948 __le32 parm3; 1949 __le32 parm4; 1950 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */ 1951 }; 1952 1953 struct aac_synchronize_reply { 1954 __le32 dummy0; 1955 __le32 dummy1; 1956 __le32 status; /* CT_OK */ 1957 __le32 parm1; 1958 __le32 parm2; 1959 __le32 parm3; 1960 __le32 parm4; 1961 __le32 parm5; 1962 u8 data[16]; 1963 }; 1964 1965 #define CT_POWER_MANAGEMENT 245 1966 #define CT_PM_START_UNIT 2 1967 #define CT_PM_STOP_UNIT 3 1968 #define CT_PM_UNIT_IMMEDIATE 1 1969 struct aac_power_management { 1970 __le32 command; /* VM_ContainerConfig */ 1971 __le32 type; /* CT_POWER_MANAGEMENT */ 1972 __le32 sub; /* CT_PM_* */ 1973 __le32 cid; 1974 __le32 parm; /* CT_PM_sub_* */ 1975 }; 1976 1977 #define CT_PAUSE_IO 65 1978 #define CT_RELEASE_IO 66 1979 struct aac_pause { 1980 __le32 command; /* VM_ContainerConfig */ 1981 __le32 type; /* CT_PAUSE_IO */ 1982 __le32 timeout; /* 10ms ticks */ 1983 __le32 min; 1984 __le32 noRescan; 1985 __le32 parm3; 1986 __le32 parm4; 1987 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */ 1988 }; 1989 1990 struct aac_srb 1991 { 1992 __le32 function; 1993 __le32 channel; 1994 __le32 id; 1995 __le32 lun; 1996 __le32 timeout; 1997 __le32 flags; 1998 __le32 count; // Data xfer size 1999 __le32 retry_limit; 2000 __le32 cdb_size; 2001 u8 cdb[16]; 2002 struct sgmap sg; 2003 }; 2004 2005 /* 2006 * This and associated data structs are used by the 2007 * ioctl caller and are in cpu order. 2008 */ 2009 struct user_aac_srb 2010 { 2011 u32 function; 2012 u32 channel; 2013 u32 id; 2014 u32 lun; 2015 u32 timeout; 2016 u32 flags; 2017 u32 count; // Data xfer size 2018 u32 retry_limit; 2019 u32 cdb_size; 2020 u8 cdb[16]; 2021 struct user_sgmap sg; 2022 }; 2023 2024 #define AAC_SENSE_BUFFERSIZE 30 2025 2026 struct aac_srb_reply 2027 { 2028 __le32 status; 2029 __le32 srb_status; 2030 __le32 scsi_status; 2031 __le32 data_xfer_length; 2032 __le32 sense_data_size; 2033 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE 2034 }; 2035 2036 struct aac_srb_unit { 2037 struct aac_srb srb; 2038 struct aac_srb_reply srb_reply; 2039 }; 2040 2041 /* 2042 * SRB Flags 2043 */ 2044 #define SRB_NoDataXfer 0x0000 2045 #define SRB_DisableDisconnect 0x0004 2046 #define SRB_DisableSynchTransfer 0x0008 2047 #define SRB_BypassFrozenQueue 0x0010 2048 #define SRB_DisableAutosense 0x0020 2049 #define SRB_DataIn 0x0040 2050 #define SRB_DataOut 0x0080 2051 2052 /* 2053 * SRB Functions - set in aac_srb->function 2054 */ 2055 #define SRBF_ExecuteScsi 0x0000 2056 #define SRBF_ClaimDevice 0x0001 2057 #define SRBF_IO_Control 0x0002 2058 #define SRBF_ReceiveEvent 0x0003 2059 #define SRBF_ReleaseQueue 0x0004 2060 #define SRBF_AttachDevice 0x0005 2061 #define SRBF_ReleaseDevice 0x0006 2062 #define SRBF_Shutdown 0x0007 2063 #define SRBF_Flush 0x0008 2064 #define SRBF_AbortCommand 0x0010 2065 #define SRBF_ReleaseRecovery 0x0011 2066 #define SRBF_ResetBus 0x0012 2067 #define SRBF_ResetDevice 0x0013 2068 #define SRBF_TerminateIO 0x0014 2069 #define SRBF_FlushQueue 0x0015 2070 #define SRBF_RemoveDevice 0x0016 2071 #define SRBF_DomainValidation 0x0017 2072 2073 /* 2074 * SRB SCSI Status - set in aac_srb->scsi_status 2075 */ 2076 #define SRB_STATUS_PENDING 0x00 2077 #define SRB_STATUS_SUCCESS 0x01 2078 #define SRB_STATUS_ABORTED 0x02 2079 #define SRB_STATUS_ABORT_FAILED 0x03 2080 #define SRB_STATUS_ERROR 0x04 2081 #define SRB_STATUS_BUSY 0x05 2082 #define SRB_STATUS_INVALID_REQUEST 0x06 2083 #define SRB_STATUS_INVALID_PATH_ID 0x07 2084 #define SRB_STATUS_NO_DEVICE 0x08 2085 #define SRB_STATUS_TIMEOUT 0x09 2086 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A 2087 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B 2088 #define SRB_STATUS_MESSAGE_REJECTED 0x0D 2089 #define SRB_STATUS_BUS_RESET 0x0E 2090 #define SRB_STATUS_PARITY_ERROR 0x0F 2091 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10 2092 #define SRB_STATUS_NO_HBA 0x11 2093 #define SRB_STATUS_DATA_OVERRUN 0x12 2094 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13 2095 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14 2096 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15 2097 #define SRB_STATUS_REQUEST_FLUSHED 0x16 2098 #define SRB_STATUS_DELAYED_RETRY 0x17 2099 #define SRB_STATUS_INVALID_LUN 0x20 2100 #define SRB_STATUS_INVALID_TARGET_ID 0x21 2101 #define SRB_STATUS_BAD_FUNCTION 0x22 2102 #define SRB_STATUS_ERROR_RECOVERY 0x23 2103 #define SRB_STATUS_NOT_STARTED 0x24 2104 #define SRB_STATUS_NOT_IN_USE 0x30 2105 #define SRB_STATUS_FORCE_ABORT 0x31 2106 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32 2107 2108 /* 2109 * Object-Server / Volume-Manager Dispatch Classes 2110 */ 2111 2112 #define VM_Null 0 2113 #define VM_NameServe 1 2114 #define VM_ContainerConfig 2 2115 #define VM_Ioctl 3 2116 #define VM_FilesystemIoctl 4 2117 #define VM_CloseAll 5 2118 #define VM_CtBlockRead 6 2119 #define VM_CtBlockWrite 7 2120 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */ 2121 #define VM_SliceBlockWrite 9 2122 #define VM_DriveBlockRead 10 /* raw access to physical devices */ 2123 #define VM_DriveBlockWrite 11 2124 #define VM_EnclosureMgt 12 /* enclosure management */ 2125 #define VM_Unused 13 /* used to be diskset management */ 2126 #define VM_CtBlockVerify 14 2127 #define VM_CtPerf 15 /* performance test */ 2128 #define VM_CtBlockRead64 16 2129 #define VM_CtBlockWrite64 17 2130 #define VM_CtBlockVerify64 18 2131 #define VM_CtHostRead64 19 2132 #define VM_CtHostWrite64 20 2133 #define VM_DrvErrTblLog 21 2134 #define VM_NameServe64 22 2135 #define VM_NameServeAllBlk 30 2136 2137 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */ 2138 2139 /* 2140 * Descriptive information (eg, vital stats) 2141 * that a content manager might report. The 2142 * FileArray filesystem component is one example 2143 * of a content manager. Raw mode might be 2144 * another. 2145 */ 2146 2147 struct aac_fsinfo { 2148 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */ 2149 __le32 fsBlockSize; 2150 __le32 fsFragSize; 2151 __le32 fsMaxExtendSize; 2152 __le32 fsSpaceUnits; 2153 __le32 fsMaxNumFiles; 2154 __le32 fsNumFreeFiles; 2155 __le32 fsInodeDensity; 2156 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */ 2157 2158 struct aac_blockdevinfo { 2159 __le32 block_size; 2160 __le32 logical_phys_map; 2161 u8 identifier[16]; 2162 }; 2163 2164 union aac_contentinfo { 2165 struct aac_fsinfo filesys; 2166 struct aac_blockdevinfo bdevinfo; 2167 }; 2168 2169 /* 2170 * Query for Container Configuration Status 2171 */ 2172 2173 #define CT_GET_CONFIG_STATUS 147 2174 struct aac_get_config_status { 2175 __le32 command; /* VM_ContainerConfig */ 2176 __le32 type; /* CT_GET_CONFIG_STATUS */ 2177 __le32 parm1; 2178 __le32 parm2; 2179 __le32 parm3; 2180 __le32 parm4; 2181 __le32 parm5; 2182 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */ 2183 }; 2184 2185 #define CFACT_CONTINUE 0 2186 #define CFACT_PAUSE 1 2187 #define CFACT_ABORT 2 2188 struct aac_get_config_status_resp { 2189 __le32 response; /* ST_OK */ 2190 __le32 dummy0; 2191 __le32 status; /* CT_OK */ 2192 __le32 parm1; 2193 __le32 parm2; 2194 __le32 parm3; 2195 __le32 parm4; 2196 __le32 parm5; 2197 struct { 2198 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */ 2199 __le16 flags; 2200 __le16 count; 2201 } data; 2202 }; 2203 2204 /* 2205 * Accept the configuration as-is 2206 */ 2207 2208 #define CT_COMMIT_CONFIG 152 2209 2210 struct aac_commit_config { 2211 __le32 command; /* VM_ContainerConfig */ 2212 __le32 type; /* CT_COMMIT_CONFIG */ 2213 }; 2214 2215 /* 2216 * Query for Container Configuration Status 2217 */ 2218 2219 #define CT_GET_CONTAINER_COUNT 4 2220 struct aac_get_container_count { 2221 __le32 command; /* VM_ContainerConfig */ 2222 __le32 type; /* CT_GET_CONTAINER_COUNT */ 2223 }; 2224 2225 struct aac_get_container_count_resp { 2226 __le32 response; /* ST_OK */ 2227 __le32 dummy0; 2228 __le32 MaxContainers; 2229 __le32 ContainerSwitchEntries; 2230 __le32 MaxPartitions; 2231 __le32 MaxSimpleVolumes; 2232 }; 2233 2234 2235 /* 2236 * Query for "mountable" objects, ie, objects that are typically 2237 * associated with a drive letter on the client (host) side. 2238 */ 2239 2240 struct aac_mntent { 2241 __le32 oid; 2242 u8 name[16]; /* if applicable */ 2243 struct creation_info create_info; /* if applicable */ 2244 __le32 capacity; 2245 __le32 vol; /* substrate structure */ 2246 __le32 obj; /* FT_FILESYS, etc. */ 2247 __le32 state; /* unready for mounting, 2248 readonly, etc. */ 2249 union aac_contentinfo fileinfo; /* Info specific to content 2250 manager (eg, filesystem) */ 2251 __le32 altoid; /* != oid <==> snapshot or 2252 broken mirror exists */ 2253 __le32 capacityhigh; 2254 }; 2255 2256 #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */ 2257 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */ 2258 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */ 2259 #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */ 2260 2261 struct aac_query_mount { 2262 __le32 command; 2263 __le32 type; 2264 __le32 count; 2265 }; 2266 2267 struct aac_mount { 2268 __le32 status; 2269 __le32 type; /* should be same as that requested */ 2270 __le32 count; 2271 struct aac_mntent mnt[1]; 2272 }; 2273 2274 #define CT_READ_NAME 130 2275 struct aac_get_name { 2276 __le32 command; /* VM_ContainerConfig */ 2277 __le32 type; /* CT_READ_NAME */ 2278 __le32 cid; 2279 __le32 parm1; 2280 __le32 parm2; 2281 __le32 parm3; 2282 __le32 parm4; 2283 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */ 2284 }; 2285 2286 struct aac_get_name_resp { 2287 __le32 dummy0; 2288 __le32 dummy1; 2289 __le32 status; /* CT_OK */ 2290 __le32 parm1; 2291 __le32 parm2; 2292 __le32 parm3; 2293 __le32 parm4; 2294 __le32 parm5; 2295 u8 data[17]; 2296 }; 2297 2298 #define CT_CID_TO_32BITS_UID 165 2299 struct aac_get_serial { 2300 __le32 command; /* VM_ContainerConfig */ 2301 __le32 type; /* CT_CID_TO_32BITS_UID */ 2302 __le32 cid; 2303 }; 2304 2305 struct aac_get_serial_resp { 2306 __le32 dummy0; 2307 __le32 dummy1; 2308 __le32 status; /* CT_OK */ 2309 __le32 uid; 2310 }; 2311 2312 /* 2313 * The following command is sent to shut down each container. 2314 */ 2315 2316 struct aac_close { 2317 __le32 command; 2318 __le32 cid; 2319 }; 2320 2321 struct aac_query_disk 2322 { 2323 s32 cnum; 2324 s32 bus; 2325 s32 id; 2326 s32 lun; 2327 u32 valid; 2328 u32 locked; 2329 u32 deleted; 2330 s32 instance; 2331 s8 name[10]; 2332 u32 unmapped; 2333 }; 2334 2335 struct aac_delete_disk { 2336 u32 disknum; 2337 u32 cnum; 2338 }; 2339 2340 struct fib_ioctl 2341 { 2342 u32 fibctx; 2343 s32 wait; 2344 char __user *fib; 2345 }; 2346 2347 struct revision 2348 { 2349 u32 compat; 2350 __le32 version; 2351 __le32 build; 2352 }; 2353 2354 2355 /* 2356 * Ugly - non Linux like ioctl coding for back compat. 2357 */ 2358 2359 #define CTL_CODE(function, method) ( \ 2360 (4<< 16) | ((function) << 2) | (method) \ 2361 ) 2362 2363 /* 2364 * Define the method codes for how buffers are passed for I/O and FS 2365 * controls 2366 */ 2367 2368 #define METHOD_BUFFERED 0 2369 #define METHOD_NEITHER 3 2370 2371 /* 2372 * Filesystem ioctls 2373 */ 2374 2375 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED) 2376 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED) 2377 #define FSACTL_DELETE_DISK 0x163 2378 #define FSACTL_QUERY_DISK 0x173 2379 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED) 2380 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED) 2381 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED) 2382 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED) 2383 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED) 2384 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER) 2385 #define FSACTL_GET_CONTAINERS 2131 2386 #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED) 2387 #define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED) 2388 #define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED) 2389 /* flags defined for IOP & HW SOFT RESET */ 2390 #define HW_IOP_RESET 0x01 2391 #define HW_SOFT_RESET 0x02 2392 #define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET) 2393 /* HW Soft Reset register offset */ 2394 #define IBW_SWR_OFFSET 0x4000 2395 #define SOFT_RESET_TIME 60 2396 2397 2398 2399 struct aac_common 2400 { 2401 /* 2402 * If this value is set to 1 then interrupt moderation will occur 2403 * in the base commuication support. 2404 */ 2405 u32 irq_mod; 2406 u32 peak_fibs; 2407 u32 zero_fibs; 2408 u32 fib_timeouts; 2409 /* 2410 * Statistical counters in debug mode 2411 */ 2412 #ifdef DBG 2413 u32 FibsSent; 2414 u32 FibRecved; 2415 u32 NativeSent; 2416 u32 NativeRecved; 2417 u32 NoResponseSent; 2418 u32 NoResponseRecved; 2419 u32 AsyncSent; 2420 u32 AsyncRecved; 2421 u32 NormalSent; 2422 u32 NormalRecved; 2423 #endif 2424 }; 2425 2426 extern struct aac_common aac_config; 2427 2428 /* 2429 * This is for management ioctl purpose only. 2430 */ 2431 struct aac_hba_info { 2432 2433 u8 driver_name[50]; 2434 u8 adapter_number; 2435 u8 system_io_bus_number; 2436 u8 device_number; 2437 u32 function_number; 2438 u32 vendor_id; 2439 u32 device_id; 2440 u32 sub_vendor_id; 2441 u32 sub_system_id; 2442 u32 mapped_base_address_size; 2443 u32 base_physical_address_high_part; 2444 u32 base_physical_address_low_part; 2445 2446 u32 max_command_size; 2447 u32 max_fib_size; 2448 u32 max_scatter_gather_from_os; 2449 u32 max_scatter_gather_to_fw; 2450 u32 max_outstanding_fibs; 2451 2452 u32 queue_start_threshold; 2453 u32 queue_dump_threshold; 2454 u32 max_io_size_queued; 2455 u32 outstanding_io; 2456 2457 u32 firmware_build_number; 2458 u32 bios_build_number; 2459 u32 driver_build_number; 2460 u32 serial_number_high_part; 2461 u32 serial_number_low_part; 2462 u32 supported_options; 2463 u32 feature_bits; 2464 u32 currentnumber_ports; 2465 2466 u8 new_comm_interface:1; 2467 u8 new_commands_supported:1; 2468 u8 disable_passthrough:1; 2469 u8 expose_non_dasd:1; 2470 u8 queue_allowed:1; 2471 u8 bled_check_enabled:1; 2472 u8 reserved1:1; 2473 u8 reserted2:1; 2474 2475 u32 reserved3[10]; 2476 2477 }; 2478 2479 /* 2480 * The following macro is used when sending and receiving FIBs. It is 2481 * only used for debugging. 2482 */ 2483 2484 #ifdef DBG 2485 #define FIB_COUNTER_INCREMENT(counter) (counter)++ 2486 #else 2487 #define FIB_COUNTER_INCREMENT(counter) 2488 #endif 2489 2490 /* 2491 * Adapter direct commands 2492 * Monitor/Kernel API 2493 */ 2494 2495 #define BREAKPOINT_REQUEST 0x00000004 2496 #define INIT_STRUCT_BASE_ADDRESS 0x00000005 2497 #define READ_PERMANENT_PARAMETERS 0x0000000a 2498 #define WRITE_PERMANENT_PARAMETERS 0x0000000b 2499 #define HOST_CRASHING 0x0000000d 2500 #define SEND_SYNCHRONOUS_FIB 0x0000000c 2501 #define COMMAND_POST_RESULTS 0x00000014 2502 #define GET_ADAPTER_PROPERTIES 0x00000019 2503 #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023 2504 #define RCV_TEMP_READINGS 0x00000025 2505 #define GET_COMM_PREFERRED_SETTINGS 0x00000026 2506 #define IOP_RESET_FW_FIB_DUMP 0x00000034 2507 #define IOP_RESET 0x00001000 2508 #define IOP_RESET_ALWAYS 0x00001001 2509 #define RE_INIT_ADAPTER 0x000000ee 2510 2511 #define IOP_SRC_RESET_MASK 0x00000100 2512 2513 /* 2514 * Adapter Status Register 2515 * 2516 * Phase Staus mailbox is 32bits: 2517 * <31:16> = Phase Status 2518 * <15:0> = Phase 2519 * 2520 * The adapter reports is present state through the phase. Only 2521 * a single phase should be ever be set. Each phase can have multiple 2522 * phase status bits to provide more detailed information about the 2523 * state of the board. Care should be taken to ensure that any phase 2524 * status bits that are set when changing the phase are also valid 2525 * for the new phase or be cleared out. Adapter software (monitor, 2526 * iflash, kernel) is responsible for properly maintining the phase 2527 * status mailbox when it is running. 2528 * 2529 * MONKER_API Phases 2530 * 2531 * Phases are bit oriented. It is NOT valid to have multiple bits set 2532 */ 2533 2534 #define SELF_TEST_FAILED 0x00000004 2535 #define MONITOR_PANIC 0x00000020 2536 #define KERNEL_BOOTING 0x00000040 2537 #define KERNEL_UP_AND_RUNNING 0x00000080 2538 #define KERNEL_PANIC 0x00000100 2539 #define FLASH_UPD_PENDING 0x00002000 2540 #define FLASH_UPD_SUCCESS 0x00004000 2541 #define FLASH_UPD_FAILED 0x00008000 2542 #define FWUPD_TIMEOUT (5 * 60) 2543 2544 /* 2545 * Doorbell bit defines 2546 */ 2547 2548 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */ 2549 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */ 2550 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */ 2551 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */ 2552 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */ 2553 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */ 2554 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */ 2555 #define DoorBellAifPending (1<<6) /* Adapter -> Host */ 2556 2557 /* PMC specific outbound doorbell bits */ 2558 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */ 2559 2560 /* 2561 * For FIB communication, we need all of the following things 2562 * to send back to the user. 2563 */ 2564 2565 #define AifCmdEventNotify 1 /* Notify of event */ 2566 #define AifEnConfigChange 3 /* Adapter configuration change */ 2567 #define AifEnContainerChange 4 /* Container configuration change */ 2568 #define AifEnDeviceFailure 5 /* SCSI device failed */ 2569 #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */ 2570 #define EM_DRIVE_INSERTION 31 2571 #define EM_DRIVE_REMOVAL 32 2572 #define EM_SES_DRIVE_INSERTION 33 2573 #define EM_SES_DRIVE_REMOVAL 26 2574 #define AifEnBatteryEvent 14 /* Change in Battery State */ 2575 #define AifEnAddContainer 15 /* A new array was created */ 2576 #define AifEnDeleteContainer 16 /* A container was deleted */ 2577 #define AifEnExpEvent 23 /* Firmware Event Log */ 2578 #define AifExeFirmwarePanic 3 /* Firmware Event Panic */ 2579 #define AifHighPriority 3 /* Highest Priority Event */ 2580 #define AifEnAddJBOD 30 /* JBOD created */ 2581 #define AifEnDeleteJBOD 31 /* JBOD deleted */ 2582 2583 #define AifBuManagerEvent 42 /* Bu management*/ 2584 #define AifBuCacheDataLoss 10 2585 #define AifBuCacheDataRecover 11 2586 2587 #define AifCmdJobProgress 2 /* Progress report */ 2588 #define AifJobCtrZero 101 /* Array Zero progress */ 2589 #define AifJobStsSuccess 1 /* Job completes */ 2590 #define AifJobStsRunning 102 /* Job running */ 2591 #define AifCmdAPIReport 3 /* Report from other user of API */ 2592 #define AifCmdDriverNotify 4 /* Notify host driver of event */ 2593 #define AifDenMorphComplete 200 /* A morph operation completed */ 2594 #define AifDenVolumeExtendComplete 201 /* A volume extend completed */ 2595 #define AifReqJobList 100 /* Gets back complete job list */ 2596 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */ 2597 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */ 2598 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */ 2599 #define AifReqTerminateJob 104 /* Terminates job */ 2600 #define AifReqSuspendJob 105 /* Suspends a job */ 2601 #define AifReqResumeJob 106 /* Resumes a job */ 2602 #define AifReqSendAPIReport 107 /* API generic report requests */ 2603 #define AifReqAPIJobStart 108 /* Start a job from the API */ 2604 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */ 2605 #define AifReqAPIJobFinish 110 /* Finish a job from the API */ 2606 2607 /* PMC NEW COMM: Request the event data */ 2608 #define AifReqEvent 200 2609 #define AifRawDeviceRemove 203 /* RAW device deleted */ 2610 #define AifNativeDeviceAdd 204 /* native HBA device added */ 2611 #define AifNativeDeviceRemove 205 /* native HBA device removed */ 2612 2613 2614 /* 2615 * Adapter Initiated FIB command structures. Start with the adapter 2616 * initiated FIBs that really come from the adapter, and get responded 2617 * to by the host. 2618 */ 2619 2620 struct aac_aifcmd { 2621 __le32 command; /* Tell host what type of notify this is */ 2622 __le32 seqnum; /* To allow ordering of reports (if necessary) */ 2623 u8 data[1]; /* Undefined length (from kernel viewpoint) */ 2624 }; 2625 2626 /** 2627 * Convert capacity to cylinders 2628 * accounting for the fact capacity could be a 64 bit value 2629 * 2630 */ 2631 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor) 2632 { 2633 sector_div(capacity, divisor); 2634 return capacity; 2635 } 2636 2637 static inline int aac_adapter_check_health(struct aac_dev *dev) 2638 { 2639 if (unlikely(pci_channel_offline(dev->pdev))) 2640 return -1; 2641 2642 return (dev)->a_ops.adapter_check_health(dev); 2643 } 2644 2645 2646 int aac_scan_host(struct aac_dev *dev, int rescan); 2647 2648 static inline void aac_schedule_safw_scan_worker(struct aac_dev *dev) 2649 { 2650 schedule_delayed_work(&dev->safw_rescan_work, AAC_SAFW_RESCAN_DELAY); 2651 } 2652 2653 static inline void aac_safw_rescan_worker(struct work_struct *work) 2654 { 2655 struct aac_dev *dev = container_of(to_delayed_work(work), 2656 struct aac_dev, safw_rescan_work); 2657 2658 aac_scan_host(dev, AAC_RESCAN); 2659 } 2660 2661 static inline void aac_cancel_safw_rescan_worker(struct aac_dev *dev) 2662 { 2663 if (dev->sa_firmware) 2664 cancel_delayed_work_sync(&dev->safw_rescan_work); 2665 } 2666 2667 /* SCp.phase values */ 2668 #define AAC_OWNER_MIDLEVEL 0x101 2669 #define AAC_OWNER_LOWLEVEL 0x102 2670 #define AAC_OWNER_ERROR_HANDLER 0x103 2671 #define AAC_OWNER_FIRMWARE 0x106 2672 2673 void aac_safw_rescan_worker(struct work_struct *work); 2674 int aac_acquire_irq(struct aac_dev *dev); 2675 void aac_free_irq(struct aac_dev *dev); 2676 int aac_setup_safw_adapter(struct aac_dev *dev, int rescan); 2677 const char *aac_driverinfo(struct Scsi_Host *); 2678 void aac_fib_vector_assign(struct aac_dev *dev); 2679 struct fib *aac_fib_alloc(struct aac_dev *dev); 2680 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd); 2681 int aac_fib_setup(struct aac_dev *dev); 2682 void aac_fib_map_free(struct aac_dev *dev); 2683 void aac_fib_free(struct fib * context); 2684 void aac_fib_init(struct fib * context); 2685 void aac_printf(struct aac_dev *dev, u32 val); 2686 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt); 2687 int aac_hba_send(u8 command, struct fib *context, 2688 fib_callback callback, void *ctxt); 2689 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry); 2690 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum); 2691 int aac_fib_complete(struct fib * context); 2692 void aac_hba_callback(void *context, struct fib *fibptr); 2693 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data) 2694 struct aac_dev *aac_init_adapter(struct aac_dev *dev); 2695 void aac_src_access_devreg(struct aac_dev *dev, int mode); 2696 void aac_set_intx_mode(struct aac_dev *dev); 2697 int aac_get_config_status(struct aac_dev *dev, int commit_flag); 2698 int aac_get_containers(struct aac_dev *dev); 2699 int aac_scsi_cmd(struct scsi_cmnd *cmd); 2700 int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg); 2701 #ifndef shost_to_class 2702 #define shost_to_class(shost) &shost->shost_dev 2703 #endif 2704 ssize_t aac_get_serial_number(struct device *dev, char *buf); 2705 int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg); 2706 int aac_rx_init(struct aac_dev *dev); 2707 int aac_rkt_init(struct aac_dev *dev); 2708 int aac_nark_init(struct aac_dev *dev); 2709 int aac_sa_init(struct aac_dev *dev); 2710 int aac_src_init(struct aac_dev *dev); 2711 int aac_srcv_init(struct aac_dev *dev); 2712 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify); 2713 void aac_define_int_mode(struct aac_dev *dev); 2714 unsigned int aac_response_normal(struct aac_queue * q); 2715 unsigned int aac_command_normal(struct aac_queue * q); 2716 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index, 2717 int isAif, int isFastResponse, 2718 struct hw_fib *aif_fib); 2719 int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type); 2720 int aac_check_health(struct aac_dev * dev); 2721 int aac_command_thread(void *data); 2722 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx); 2723 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size); 2724 struct aac_driver_ident* aac_get_driver_ident(int devtype); 2725 int aac_get_adapter_info(struct aac_dev* dev); 2726 int aac_send_shutdown(struct aac_dev *dev); 2727 int aac_probe_container(struct aac_dev *dev, int cid); 2728 int _aac_rx_init(struct aac_dev *dev); 2729 int aac_rx_select_comm(struct aac_dev *dev, int comm); 2730 int aac_rx_deliver_producer(struct fib * fib); 2731 2732 static inline int aac_is_src(struct aac_dev *dev) 2733 { 2734 u16 device = dev->pdev->device; 2735 2736 if (device == PMC_DEVICE_S6 || 2737 device == PMC_DEVICE_S7 || 2738 device == PMC_DEVICE_S8) 2739 return 1; 2740 return 0; 2741 } 2742 2743 static inline int aac_supports_2T(struct aac_dev *dev) 2744 { 2745 return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64); 2746 } 2747 2748 char * get_container_type(unsigned type); 2749 extern int numacb; 2750 extern char aac_driver_version[]; 2751 extern int startup_timeout; 2752 extern int aif_timeout; 2753 extern int expose_physicals; 2754 extern int aac_reset_devices; 2755 extern int aac_msi; 2756 extern int aac_commit; 2757 extern int update_interval; 2758 extern int check_interval; 2759 extern int aac_check_reset; 2760 extern int aac_fib_dump; 2761 #endif 2762