1 #ifndef dprintk 2 # define dprintk(x) 3 #endif 4 /* eg: if (nblank(dprintk(x))) */ 5 #define _nblank(x) #x 6 #define nblank(x) _nblank(x)[0] 7 8 #include <linux/interrupt.h> 9 #include <linux/pci.h> 10 11 /*------------------------------------------------------------------------------ 12 * D E F I N E S 13 *----------------------------------------------------------------------------*/ 14 15 #define AAC_MAX_MSIX 32 /* vectors */ 16 #define AAC_PCI_MSI_ENABLE 0x8000 17 18 enum { 19 AAC_ENABLE_INTERRUPT = 0x0, 20 AAC_DISABLE_INTERRUPT, 21 AAC_ENABLE_MSIX, 22 AAC_DISABLE_MSIX, 23 AAC_CLEAR_AIF_BIT, 24 AAC_CLEAR_SYNC_BIT, 25 AAC_ENABLE_INTX 26 }; 27 28 #define AAC_INT_MODE_INTX (1<<0) 29 #define AAC_INT_MODE_MSI (1<<1) 30 #define AAC_INT_MODE_AIF (1<<2) 31 #define AAC_INT_MODE_SYNC (1<<3) 32 #define AAC_INT_MODE_MSIX (1<<16) 33 34 #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb 35 #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa 36 #define AAC_INT_DISABLE_ALL 0xffffffff 37 38 /* Bit definitions in IOA->Host Interrupt Register */ 39 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31) 40 #define PMC_IOARCB_TRANSFER_FAILED (1<<28) 41 #define PMC_IOA_UNIT_CHECK (1<<27) 42 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26) 43 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25) 44 #define PMC_IOARRIN_LOST (1<<4) 45 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3) 46 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2) 47 #define PMC_HOST_RRQ_VALID (1<<1) 48 #define PMC_OPERATIONAL_STATUS (1<<31) 49 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0) 50 51 #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \ 52 PMC_IOA_UNIT_CHECK | \ 53 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \ 54 PMC_IOARRIN_LOST | \ 55 PMC_SYSTEM_BUS_MMIO_ERROR | \ 56 PMC_IOA_PROCESSOR_IN_ERROR_STATE) 57 58 #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \ 59 PMC_HOST_RRQ_VALID | \ 60 PMC_TRANSITION_TO_OPERATIONAL | \ 61 PMC_ALLOW_MSIX_VECTOR0) 62 #define PMC_GLOBAL_INT_BIT2 0x00000004 63 #define PMC_GLOBAL_INT_BIT0 0x00000001 64 65 #ifndef AAC_DRIVER_BUILD 66 # define AAC_DRIVER_BUILD 41066 67 # define AAC_DRIVER_BRANCH "-ms" 68 #endif 69 #define MAXIMUM_NUM_CONTAINERS 32 70 71 #define AAC_NUM_MGT_FIB 8 72 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB) 73 #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB) 74 75 #define AAC_MAX_LUN (8) 76 77 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff) 78 #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256) 79 80 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE 81 82 /* 83 * These macros convert from physical channels to virtual channels 84 */ 85 #define CONTAINER_CHANNEL (0) 86 #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL) 87 #define CONTAINER_TO_ID(cont) (cont) 88 #define CONTAINER_TO_LUN(cont) (0) 89 90 #define PMC_DEVICE_S6 0x28b 91 #define PMC_DEVICE_S7 0x28c 92 #define PMC_DEVICE_S8 0x28d 93 #define PMC_DEVICE_S9 0x28f 94 95 #define aac_phys_to_logical(x) ((x)+1) 96 #define aac_logical_to_phys(x) ((x)?(x)-1:0) 97 98 /* 99 * These macros are for keeping track of 100 * character device state. 101 */ 102 #define AAC_CHARDEV_UNREGISTERED (-1) 103 #define AAC_CHARDEV_NEEDS_REINIT (-2) 104 105 /* #define AAC_DETAILED_STATUS_INFO */ 106 107 struct diskparm 108 { 109 int heads; 110 int sectors; 111 int cylinders; 112 }; 113 114 115 /* 116 * Firmware constants 117 */ 118 119 #define CT_NONE 0 120 #define CT_OK 218 121 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */ 122 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */ 123 124 /* 125 * Host side memory scatter gather list 126 * Used by the adapter for read, write, and readdirplus operations 127 * We have separate 32 and 64 bit version because even 128 * on 64 bit systems not all cards support the 64 bit version 129 */ 130 struct sgentry { 131 __le32 addr; /* 32-bit address. */ 132 __le32 count; /* Length. */ 133 }; 134 135 struct user_sgentry { 136 u32 addr; /* 32-bit address. */ 137 u32 count; /* Length. */ 138 }; 139 140 struct sgentry64 { 141 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 142 __le32 count; /* Length. */ 143 }; 144 145 struct user_sgentry64 { 146 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 147 u32 count; /* Length. */ 148 }; 149 150 struct sgentryraw { 151 __le32 next; /* reserved for F/W use */ 152 __le32 prev; /* reserved for F/W use */ 153 __le32 addr[2]; 154 __le32 count; 155 __le32 flags; /* reserved for F/W use */ 156 }; 157 158 struct user_sgentryraw { 159 u32 next; /* reserved for F/W use */ 160 u32 prev; /* reserved for F/W use */ 161 u32 addr[2]; 162 u32 count; 163 u32 flags; /* reserved for F/W use */ 164 }; 165 166 struct sge_ieee1212 { 167 u32 addrLow; 168 u32 addrHigh; 169 u32 length; 170 u32 flags; 171 }; 172 173 /* 174 * SGMAP 175 * 176 * This is the SGMAP structure for all commands that use 177 * 32-bit addressing. 178 */ 179 180 struct sgmap { 181 __le32 count; 182 struct sgentry sg[1]; 183 }; 184 185 struct user_sgmap { 186 u32 count; 187 struct user_sgentry sg[1]; 188 }; 189 190 struct sgmap64 { 191 __le32 count; 192 struct sgentry64 sg[1]; 193 }; 194 195 struct user_sgmap64 { 196 u32 count; 197 struct user_sgentry64 sg[1]; 198 }; 199 200 struct sgmapraw { 201 __le32 count; 202 struct sgentryraw sg[1]; 203 }; 204 205 struct user_sgmapraw { 206 u32 count; 207 struct user_sgentryraw sg[1]; 208 }; 209 210 struct creation_info 211 { 212 u8 buildnum; /* e.g., 588 */ 213 u8 usec; /* e.g., 588 */ 214 u8 via; /* e.g., 1 = FSU, 215 * 2 = API 216 */ 217 u8 year; /* e.g., 1997 = 97 */ 218 __le32 date; /* 219 * unsigned Month :4; // 1 - 12 220 * unsigned Day :6; // 1 - 32 221 * unsigned Hour :6; // 0 - 23 222 * unsigned Minute :6; // 0 - 60 223 * unsigned Second :6; // 0 - 60 224 */ 225 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */ 226 }; 227 228 229 /* 230 * Define all the constants needed for the communication interface 231 */ 232 233 /* 234 * Define how many queue entries each queue will have and the total 235 * number of entries for the entire communication interface. Also define 236 * how many queues we support. 237 * 238 * This has to match the controller 239 */ 240 241 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response 242 #define HOST_HIGH_CMD_ENTRIES 4 243 #define HOST_NORM_CMD_ENTRIES 8 244 #define ADAP_HIGH_CMD_ENTRIES 4 245 #define ADAP_NORM_CMD_ENTRIES 512 246 #define HOST_HIGH_RESP_ENTRIES 4 247 #define HOST_NORM_RESP_ENTRIES 512 248 #define ADAP_HIGH_RESP_ENTRIES 4 249 #define ADAP_NORM_RESP_ENTRIES 8 250 251 #define TOTAL_QUEUE_ENTRIES \ 252 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \ 253 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES) 254 255 256 /* 257 * Set the queues on a 16 byte alignment 258 */ 259 260 #define QUEUE_ALIGNMENT 16 261 262 /* 263 * The queue headers define the Communication Region queues. These 264 * are physically contiguous and accessible by both the adapter and the 265 * host. Even though all queue headers are in the same contiguous block 266 * they will be represented as individual units in the data structures. 267 */ 268 269 struct aac_entry { 270 __le32 size; /* Size in bytes of Fib which this QE points to */ 271 __le32 addr; /* Receiver address of the FIB */ 272 }; 273 274 /* 275 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped 276 * adjacently and in that order. 277 */ 278 279 struct aac_qhdr { 280 __le64 header_addr;/* Address to hand the adapter to access 281 to this queue head */ 282 __le32 *producer; /* The producer index for this queue (host address) */ 283 __le32 *consumer; /* The consumer index for this queue (host address) */ 284 }; 285 286 /* 287 * Define all the events which the adapter would like to notify 288 * the host of. 289 */ 290 291 #define HostNormCmdQue 1 /* Change in host normal priority command queue */ 292 #define HostHighCmdQue 2 /* Change in host high priority command queue */ 293 #define HostNormRespQue 3 /* Change in host normal priority response queue */ 294 #define HostHighRespQue 4 /* Change in host high priority response queue */ 295 #define AdapNormRespNotFull 5 296 #define AdapHighRespNotFull 6 297 #define AdapNormCmdNotFull 7 298 #define AdapHighCmdNotFull 8 299 #define SynchCommandComplete 9 300 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */ 301 302 /* 303 * Define all the events the host wishes to notify the 304 * adapter of. The first four values much match the Qid the 305 * corresponding queue. 306 */ 307 308 #define AdapNormCmdQue 2 309 #define AdapHighCmdQue 3 310 #define AdapNormRespQue 6 311 #define AdapHighRespQue 7 312 #define HostShutdown 8 313 #define HostPowerFail 9 314 #define FatalCommError 10 315 #define HostNormRespNotFull 11 316 #define HostHighRespNotFull 12 317 #define HostNormCmdNotFull 13 318 #define HostHighCmdNotFull 14 319 #define FastIo 15 320 #define AdapPrintfDone 16 321 322 /* 323 * Define all the queues that the adapter and host use to communicate 324 * Number them to match the physical queue layout. 325 */ 326 327 enum aac_queue_types { 328 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */ 329 HostHighCmdQueue, /* Adapter to host high priority command traffic */ 330 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */ 331 AdapHighCmdQueue, /* Host to adapter high priority command traffic */ 332 HostNormRespQueue, /* Adapter to host normal priority response traffic */ 333 HostHighRespQueue, /* Adapter to host high priority response traffic */ 334 AdapNormRespQueue, /* Host to adapter normal priority response traffic */ 335 AdapHighRespQueue /* Host to adapter high priority response traffic */ 336 }; 337 338 /* 339 * Assign type values to the FSA communication data structures 340 */ 341 342 #define FIB_MAGIC 0x0001 343 #define FIB_MAGIC2 0x0004 344 #define FIB_MAGIC2_64 0x0005 345 346 /* 347 * Define the priority levels the FSA communication routines support. 348 */ 349 350 #define FsaNormal 1 351 352 /* transport FIB header (PMC) */ 353 struct aac_fib_xporthdr { 354 u64 HostAddress; /* FIB host address w/o xport header */ 355 u32 Size; /* FIB size excluding xport header */ 356 u32 Handle; /* driver handle to reference the FIB */ 357 u64 Reserved[2]; 358 }; 359 360 #define ALIGN32 32 361 362 /* 363 * Define the FIB. The FIB is the where all the requested data and 364 * command information are put to the application on the FSA adapter. 365 */ 366 367 struct aac_fibhdr { 368 __le32 XferState; /* Current transfer state for this CCB */ 369 __le16 Command; /* Routing information for the destination */ 370 u8 StructType; /* Type FIB */ 371 u8 Unused; /* Unused */ 372 __le16 Size; /* Size of this FIB in bytes */ 373 __le16 SenderSize; /* Size of the FIB in the sender 374 (for response sizing) */ 375 __le32 SenderFibAddress; /* Host defined data in the FIB */ 376 union { 377 __le32 ReceiverFibAddress;/* Logical address of this FIB for 378 the adapter (old) */ 379 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */ 380 __le32 TimeStamp; /* otherwise timestamp for FW internal use */ 381 } u; 382 u32 Handle; /* FIB handle used for MSGU commnunication */ 383 u32 Previous; /* FW internal use */ 384 u32 Next; /* FW internal use */ 385 }; 386 387 struct hw_fib { 388 struct aac_fibhdr header; 389 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data 390 }; 391 392 /* 393 * FIB commands 394 */ 395 396 #define TestCommandResponse 1 397 #define TestAdapterCommand 2 398 /* 399 * Lowlevel and comm commands 400 */ 401 #define LastTestCommand 100 402 #define ReinitHostNormCommandQueue 101 403 #define ReinitHostHighCommandQueue 102 404 #define ReinitHostHighRespQueue 103 405 #define ReinitHostNormRespQueue 104 406 #define ReinitAdapNormCommandQueue 105 407 #define ReinitAdapHighCommandQueue 107 408 #define ReinitAdapHighRespQueue 108 409 #define ReinitAdapNormRespQueue 109 410 #define InterfaceShutdown 110 411 #define DmaCommandFib 120 412 #define StartProfile 121 413 #define TermProfile 122 414 #define SpeedTest 123 415 #define TakeABreakPt 124 416 #define RequestPerfData 125 417 #define SetInterruptDefTimer 126 418 #define SetInterruptDefCount 127 419 #define GetInterruptDefStatus 128 420 #define LastCommCommand 129 421 /* 422 * Filesystem commands 423 */ 424 #define NuFileSystem 300 425 #define UFS 301 426 #define HostFileSystem 302 427 #define LastFileSystemCommand 303 428 /* 429 * Container Commands 430 */ 431 #define ContainerCommand 500 432 #define ContainerCommand64 501 433 #define ContainerRawIo 502 434 #define ContainerRawIo2 503 435 /* 436 * Scsi Port commands (scsi passthrough) 437 */ 438 #define ScsiPortCommand 600 439 #define ScsiPortCommand64 601 440 /* 441 * Misc house keeping and generic adapter initiated commands 442 */ 443 #define AifRequest 700 444 #define CheckRevision 701 445 #define FsaHostShutdown 702 446 #define RequestAdapterInfo 703 447 #define IsAdapterPaused 704 448 #define SendHostTime 705 449 #define RequestSupplementAdapterInfo 706 450 #define LastMiscCommand 707 451 452 /* 453 * Commands that will target the failover level on the FSA adapter 454 */ 455 456 enum fib_xfer_state { 457 HostOwned = (1<<0), 458 AdapterOwned = (1<<1), 459 FibInitialized = (1<<2), 460 FibEmpty = (1<<3), 461 AllocatedFromPool = (1<<4), 462 SentFromHost = (1<<5), 463 SentFromAdapter = (1<<6), 464 ResponseExpected = (1<<7), 465 NoResponseExpected = (1<<8), 466 AdapterProcessed = (1<<9), 467 HostProcessed = (1<<10), 468 HighPriority = (1<<11), 469 NormalPriority = (1<<12), 470 Async = (1<<13), 471 AsyncIo = (1<<13), // rpbfix: remove with new regime 472 PageFileIo = (1<<14), // rpbfix: remove with new regime 473 ShutdownRequest = (1<<15), 474 LazyWrite = (1<<16), // rpbfix: remove with new regime 475 AdapterMicroFib = (1<<17), 476 BIOSFibPath = (1<<18), 477 FastResponseCapable = (1<<19), 478 ApiFib = (1<<20), /* Its an API Fib */ 479 /* PMC NEW COMM: There is no more AIF data pending */ 480 NoMoreAifDataAvailable = (1<<21) 481 }; 482 483 /* 484 * The following defines needs to be updated any time there is an 485 * incompatible change made to the aac_init structure. 486 */ 487 488 #define ADAPTER_INIT_STRUCT_REVISION 3 489 #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science 490 #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */ 491 #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */ 492 493 struct aac_init 494 { 495 __le32 InitStructRevision; 496 __le32 Sa_MSIXVectors; 497 __le32 fsrev; 498 __le32 CommHeaderAddress; 499 __le32 FastIoCommAreaAddress; 500 __le32 AdapterFibsPhysicalAddress; 501 __le32 AdapterFibsVirtualAddress; 502 __le32 AdapterFibsSize; 503 __le32 AdapterFibAlign; 504 __le32 printfbuf; 505 __le32 printfbufsiz; 506 __le32 HostPhysMemPages; /* number of 4k pages of host 507 physical memory */ 508 __le32 HostElapsedSeconds; /* number of seconds since 1970. */ 509 /* 510 * ADAPTER_INIT_STRUCT_REVISION_4 begins here 511 */ 512 __le32 InitFlags; /* flags for supported features */ 513 #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001 514 #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010 515 #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020 516 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040 517 #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080 518 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100 519 __le32 MaxIoCommands; /* max outstanding commands */ 520 __le32 MaxIoSize; /* largest I/O command */ 521 __le32 MaxFibSize; /* largest FIB to adapter */ 522 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */ 523 __le32 MaxNumAif; /* max number of aif */ 524 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */ 525 __le32 HostRRQ_AddrLow; 526 __le32 HostRRQ_AddrHigh; /* Host RRQ (response queue) for SRC */ 527 }; 528 529 enum aac_log_level { 530 LOG_AAC_INIT = 10, 531 LOG_AAC_INFORMATIONAL = 20, 532 LOG_AAC_WARNING = 30, 533 LOG_AAC_LOW_ERROR = 40, 534 LOG_AAC_MEDIUM_ERROR = 50, 535 LOG_AAC_HIGH_ERROR = 60, 536 LOG_AAC_PANIC = 70, 537 LOG_AAC_DEBUG = 80, 538 LOG_AAC_WINDBG_PRINT = 90 539 }; 540 541 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b 542 #define FSAFS_NTC_FIB_CONTEXT 0x030c 543 544 struct aac_dev; 545 struct fib; 546 struct scsi_cmnd; 547 548 struct adapter_ops 549 { 550 /* Low level operations */ 551 void (*adapter_interrupt)(struct aac_dev *dev); 552 void (*adapter_notify)(struct aac_dev *dev, u32 event); 553 void (*adapter_disable_int)(struct aac_dev *dev); 554 void (*adapter_enable_int)(struct aac_dev *dev); 555 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4); 556 int (*adapter_check_health)(struct aac_dev *dev); 557 int (*adapter_restart)(struct aac_dev *dev, int bled); 558 void (*adapter_start)(struct aac_dev *dev); 559 /* Transport operations */ 560 int (*adapter_ioremap)(struct aac_dev * dev, u32 size); 561 irq_handler_t adapter_intr; 562 /* Packet operations */ 563 int (*adapter_deliver)(struct fib * fib); 564 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba); 565 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count); 566 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua); 567 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd); 568 /* Administrative operations */ 569 int (*adapter_comm)(struct aac_dev * dev, int comm); 570 }; 571 572 /* 573 * Define which interrupt handler needs to be installed 574 */ 575 576 struct aac_driver_ident 577 { 578 int (*init)(struct aac_dev *dev); 579 char * name; 580 char * vname; 581 char * model; 582 u16 channels; 583 int quirks; 584 }; 585 /* 586 * Some adapter firmware needs communication memory 587 * below 2gig. This tells the init function to set the 588 * dma mask such that fib memory will be allocated where the 589 * adapter firmware can get to it. 590 */ 591 #define AAC_QUIRK_31BIT 0x0001 592 593 /* 594 * Some adapter firmware, when the raid card's cache is turned off, can not 595 * split up scatter gathers in order to deal with the limits of the 596 * underlying CHIM. This limit is 34 scatter gather elements. 597 */ 598 #define AAC_QUIRK_34SG 0x0002 599 600 /* 601 * This adapter is a slave (no Firmware) 602 */ 603 #define AAC_QUIRK_SLAVE 0x0004 604 605 /* 606 * This adapter is a master. 607 */ 608 #define AAC_QUIRK_MASTER 0x0008 609 610 /* 611 * Some adapter firmware perform poorly when it must split up scatter gathers 612 * in order to deal with the limits of the underlying CHIM. This limit in this 613 * class of adapters is 17 scatter gather elements. 614 */ 615 #define AAC_QUIRK_17SG 0x0010 616 617 /* 618 * Some adapter firmware does not support 64 bit scsi passthrough 619 * commands. 620 */ 621 #define AAC_QUIRK_SCSI_32 0x0020 622 623 /* 624 * The adapter interface specs all queues to be located in the same 625 * physically contiguous block. The host structure that defines the 626 * commuication queues will assume they are each a separate physically 627 * contiguous memory region that will support them all being one big 628 * contiguous block. 629 * There is a command and response queue for each level and direction of 630 * commuication. These regions are accessed by both the host and adapter. 631 */ 632 633 struct aac_queue { 634 u64 logical; /*address we give the adapter */ 635 struct aac_entry *base; /*system virtual address */ 636 struct aac_qhdr headers; /*producer,consumer q headers*/ 637 u32 entries; /*Number of queue entries */ 638 wait_queue_head_t qfull; /*Event to wait on if q full */ 639 wait_queue_head_t cmdready; /*Cmd ready from the adapter */ 640 /* This is only valid for adapter to host command queues. */ 641 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */ 642 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */ 643 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */ 644 /* only valid for command queues which receive entries from the adapter. */ 645 /* Number of entries on outstanding queue. */ 646 atomic_t numpending; 647 struct aac_dev * dev; /* Back pointer to adapter structure */ 648 }; 649 650 /* 651 * Message queues. The order here is important, see also the 652 * queue type ordering 653 */ 654 655 struct aac_queue_block 656 { 657 struct aac_queue queue[8]; 658 }; 659 660 /* 661 * SaP1 Message Unit Registers 662 */ 663 664 struct sa_drawbridge_CSR { 665 /* Offset | Name */ 666 __le32 reserved[10]; /* 00h-27h | Reserved */ 667 u8 LUT_Offset; /* 28h | Lookup Table Offset */ 668 u8 reserved1[3]; /* 29h-2bh | Reserved */ 669 __le32 LUT_Data; /* 2ch | Looup Table Data */ 670 __le32 reserved2[26]; /* 30h-97h | Reserved */ 671 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */ 672 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */ 673 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */ 674 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */ 675 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */ 676 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */ 677 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */ 678 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */ 679 __le32 MAILBOX0; /* a8h | Scratchpad 0 */ 680 __le32 MAILBOX1; /* ach | Scratchpad 1 */ 681 __le32 MAILBOX2; /* b0h | Scratchpad 2 */ 682 __le32 MAILBOX3; /* b4h | Scratchpad 3 */ 683 __le32 MAILBOX4; /* b8h | Scratchpad 4 */ 684 __le32 MAILBOX5; /* bch | Scratchpad 5 */ 685 __le32 MAILBOX6; /* c0h | Scratchpad 6 */ 686 __le32 MAILBOX7; /* c4h | Scratchpad 7 */ 687 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */ 688 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */ 689 __le32 reserved3[12]; /* d0h-ffh | reserved */ 690 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */ 691 }; 692 693 #define Mailbox0 SaDbCSR.MAILBOX0 694 #define Mailbox1 SaDbCSR.MAILBOX1 695 #define Mailbox2 SaDbCSR.MAILBOX2 696 #define Mailbox3 SaDbCSR.MAILBOX3 697 #define Mailbox4 SaDbCSR.MAILBOX4 698 #define Mailbox5 SaDbCSR.MAILBOX5 699 #define Mailbox6 SaDbCSR.MAILBOX6 700 #define Mailbox7 SaDbCSR.MAILBOX7 701 702 #define DoorbellReg_p SaDbCSR.PRISETIRQ 703 #define DoorbellReg_s SaDbCSR.SECSETIRQ 704 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ 705 706 707 #define DOORBELL_0 0x0001 708 #define DOORBELL_1 0x0002 709 #define DOORBELL_2 0x0004 710 #define DOORBELL_3 0x0008 711 #define DOORBELL_4 0x0010 712 #define DOORBELL_5 0x0020 713 #define DOORBELL_6 0x0040 714 715 716 #define PrintfReady DOORBELL_5 717 #define PrintfDone DOORBELL_5 718 719 struct sa_registers { 720 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */ 721 }; 722 723 724 #define SA_INIT_NUM_MSIXVECTORS 1 725 726 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 727 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 728 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) 729 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) 730 731 /* 732 * Rx Message Unit Registers 733 */ 734 735 struct rx_mu_registers { 736 /* Local | PCI*| Name */ 737 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */ 738 __le32 reserved0; /* 1304h | 04h | Reserved */ 739 __le32 AWR; /* 1308h | 08h | APIC Window Register */ 740 __le32 reserved1; /* 130Ch | 0Ch | Reserved */ 741 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */ 742 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */ 743 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */ 744 __le32 IISR; /* 1324h | 24h | Inbound Interrupt 745 Status Register */ 746 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt 747 Mask Register */ 748 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */ 749 __le32 OISR; /* 1330h | 30h | Outbound Interrupt 750 Status Register */ 751 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt 752 Mask Register */ 753 __le32 reserved2; /* 1338h | 38h | Reserved */ 754 __le32 reserved3; /* 133Ch | 3Ch | Reserved */ 755 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */ 756 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */ 757 /* * Must access through ATU Inbound 758 Translation Window */ 759 }; 760 761 struct rx_inbound { 762 __le32 Mailbox[8]; 763 }; 764 765 #define INBOUNDDOORBELL_0 0x00000001 766 #define INBOUNDDOORBELL_1 0x00000002 767 #define INBOUNDDOORBELL_2 0x00000004 768 #define INBOUNDDOORBELL_3 0x00000008 769 #define INBOUNDDOORBELL_4 0x00000010 770 #define INBOUNDDOORBELL_5 0x00000020 771 #define INBOUNDDOORBELL_6 0x00000040 772 773 #define OUTBOUNDDOORBELL_0 0x00000001 774 #define OUTBOUNDDOORBELL_1 0x00000002 775 #define OUTBOUNDDOORBELL_2 0x00000004 776 #define OUTBOUNDDOORBELL_3 0x00000008 777 #define OUTBOUNDDOORBELL_4 0x00000010 778 779 #define InboundDoorbellReg MUnit.IDR 780 #define OutboundDoorbellReg MUnit.ODR 781 782 struct rx_registers { 783 struct rx_mu_registers MUnit; /* 1300h - 1347h */ 784 __le32 reserved1[2]; /* 1348h - 134ch */ 785 struct rx_inbound IndexRegs; 786 }; 787 788 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) 789 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) 790 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) 791 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) 792 793 /* 794 * Rkt Message Unit Registers (same as Rx, except a larger reserve region) 795 */ 796 797 #define rkt_mu_registers rx_mu_registers 798 #define rkt_inbound rx_inbound 799 800 struct rkt_registers { 801 struct rkt_mu_registers MUnit; /* 1300h - 1347h */ 802 __le32 reserved1[1006]; /* 1348h - 22fch */ 803 struct rkt_inbound IndexRegs; /* 2300h - */ 804 }; 805 806 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) 807 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) 808 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR)) 809 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR)) 810 811 /* 812 * PMC SRC message unit registers 813 */ 814 815 #define src_inbound rx_inbound 816 817 struct src_mu_registers { 818 /* PCI*| Name */ 819 __le32 reserved0[6]; /* 00h | Reserved */ 820 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */ 821 __le32 IDR; /* 20h | Inbound Doorbell Register */ 822 __le32 IISR; /* 24h | Inbound Int. Status Register */ 823 __le32 reserved1[3]; /* 28h | Reserved */ 824 __le32 OIMR; /* 34h | Outbound Int. Mask Register */ 825 __le32 reserved2[25]; /* 38h | Reserved */ 826 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */ 827 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */ 828 __le32 reserved3[6]; /* a4h | Reserved */ 829 __le32 OMR; /* bch | Outbound Message Register */ 830 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */ 831 __le32 IQ_H; /* c4h | Inbound Queue (High address) */ 832 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */ 833 }; 834 835 struct src_registers { 836 struct src_mu_registers MUnit; /* 00h - cbh */ 837 union { 838 struct { 839 __le32 reserved1[130789]; /* cch - 7fc5fh */ 840 struct src_inbound IndexRegs; /* 7fc60h */ 841 } tupelo; 842 struct { 843 __le32 reserved1[973]; /* cch - fffh */ 844 struct src_inbound IndexRegs; /* 1000h */ 845 } denali; 846 } u; 847 }; 848 849 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR)) 850 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR)) 851 #define src_writeb(AEP, CSR, value) writeb(value, \ 852 &((AEP)->regs.src.bar0->CSR)) 853 #define src_writel(AEP, CSR, value) writel(value, \ 854 &((AEP)->regs.src.bar0->CSR)) 855 #if defined(writeq) 856 #define src_writeq(AEP, CSR, value) writeq(value, \ 857 &((AEP)->regs.src.bar0->CSR)) 858 #endif 859 860 #define SRC_ODR_SHIFT 12 861 #define SRC_IDR_SHIFT 9 862 863 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx); 864 865 struct aac_fib_context { 866 s16 type; // used for verification of structure 867 s16 size; 868 u32 unique; // unique value representing this context 869 ulong jiffies; // used for cleanup - dmb changed to ulong 870 struct list_head next; // used to link context's into a linked list 871 struct semaphore wait_sem; // this is used to wait for the next fib to arrive. 872 int wait; // Set to true when thread is in WaitForSingleObject 873 unsigned long count; // total number of FIBs on FibList 874 struct list_head fib_list; // this holds fibs and their attachd hw_fibs 875 }; 876 877 struct sense_data { 878 u8 error_code; /* 70h (current errors), 71h(deferred errors) */ 879 u8 valid:1; /* A valid bit of one indicates that the information */ 880 /* field contains valid information as defined in the 881 * SCSI-2 Standard. 882 */ 883 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */ 884 u8 sense_key:4; /* Sense Key */ 885 u8 reserved:1; 886 u8 ILI:1; /* Incorrect Length Indicator */ 887 u8 EOM:1; /* End Of Medium - reserved for random access devices */ 888 u8 filemark:1; /* Filemark - reserved for random access devices */ 889 890 u8 information[4]; /* for direct-access devices, contains the unsigned 891 * logical block address or residue associated with 892 * the sense key 893 */ 894 u8 add_sense_len; /* number of additional sense bytes to follow this field */ 895 u8 cmnd_info[4]; /* not used */ 896 u8 ASC; /* Additional Sense Code */ 897 u8 ASCQ; /* Additional Sense Code Qualifier */ 898 u8 FRUC; /* Field Replaceable Unit Code - not used */ 899 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data 900 * was in error 901 */ 902 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that 903 * the bit_ptr field has valid value 904 */ 905 u8 reserved2:2; 906 u8 CD:1; /* command data bit: 1- illegal parameter in CDB. 907 * 0- illegal parameter in data. 908 */ 909 u8 SKSV:1; 910 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */ 911 }; 912 913 struct fsa_dev_info { 914 u64 last; 915 u64 size; 916 u32 type; 917 u32 config_waiting_on; 918 unsigned long config_waiting_stamp; 919 u16 queue_depth; 920 u8 config_needed; 921 u8 valid; 922 u8 ro; 923 u8 locked; 924 u8 deleted; 925 char devname[8]; 926 struct sense_data sense_data; 927 u32 block_size; 928 }; 929 930 struct fib { 931 void *next; /* this is used by the allocator */ 932 s16 type; 933 s16 size; 934 /* 935 * The Adapter that this I/O is destined for. 936 */ 937 struct aac_dev *dev; 938 /* 939 * This is the event the sendfib routine will wait on if the 940 * caller did not pass one and this is synch io. 941 */ 942 struct semaphore event_wait; 943 spinlock_t event_lock; 944 945 u32 done; /* gets set to 1 when fib is complete */ 946 fib_callback callback; 947 void *callback_data; 948 u32 flags; // u32 dmb was ulong 949 /* 950 * And for the internal issue/reply queues (we may be able 951 * to merge these two) 952 */ 953 struct list_head fiblink; 954 void *data; 955 u32 vector_no; 956 struct hw_fib *hw_fib_va; /* Actual shared object */ 957 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/ 958 }; 959 960 /* 961 * Adapter Information Block 962 * 963 * This is returned by the RequestAdapterInfo block 964 */ 965 966 struct aac_adapter_info 967 { 968 __le32 platform; 969 __le32 cpu; 970 __le32 subcpu; 971 __le32 clock; 972 __le32 execmem; 973 __le32 buffermem; 974 __le32 totalmem; 975 __le32 kernelrev; 976 __le32 kernelbuild; 977 __le32 monitorrev; 978 __le32 monitorbuild; 979 __le32 hwrev; 980 __le32 hwbuild; 981 __le32 biosrev; 982 __le32 biosbuild; 983 __le32 cluster; 984 __le32 clusterchannelmask; 985 __le32 serial[2]; 986 __le32 battery; 987 __le32 options; 988 __le32 OEM; 989 }; 990 991 struct aac_supplement_adapter_info 992 { 993 u8 AdapterTypeText[17+1]; 994 u8 Pad[2]; 995 __le32 FlashMemoryByteSize; 996 __le32 FlashImageId; 997 __le32 MaxNumberPorts; 998 __le32 Version; 999 __le32 FeatureBits; 1000 u8 SlotNumber; 1001 u8 ReservedPad0[3]; 1002 u8 BuildDate[12]; 1003 __le32 CurrentNumberPorts; 1004 struct { 1005 u8 AssemblyPn[8]; 1006 u8 FruPn[8]; 1007 u8 BatteryFruPn[8]; 1008 u8 EcVersionString[8]; 1009 u8 Tsid[12]; 1010 } VpdInfo; 1011 __le32 FlashFirmwareRevision; 1012 __le32 FlashFirmwareBuild; 1013 __le32 RaidTypeMorphOptions; 1014 __le32 FlashFirmwareBootRevision; 1015 __le32 FlashFirmwareBootBuild; 1016 u8 MfgPcbaSerialNo[12]; 1017 u8 MfgWWNName[8]; 1018 __le32 SupportedOptions2; 1019 __le32 StructExpansion; 1020 /* StructExpansion == 1 */ 1021 __le32 FeatureBits3; 1022 __le32 SupportedPerformanceModes; 1023 __le32 ReservedForFutureGrowth[80]; 1024 }; 1025 #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010) 1026 #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000) 1027 /* SupportedOptions2 */ 1028 #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001) 1029 #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002) 1030 #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004) 1031 #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000) 1032 /* 4KB sector size */ 1033 #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000) 1034 /* 240 simple volume support */ 1035 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000) 1036 #define AAC_SIS_VERSION_V3 3 1037 #define AAC_SIS_SLOT_UNKNOWN 0xFF 1038 1039 #define GetBusInfo 0x00000009 1040 struct aac_bus_info { 1041 __le32 Command; /* VM_Ioctl */ 1042 __le32 ObjType; /* FT_DRIVE */ 1043 __le32 MethodId; /* 1 = SCSI Layer */ 1044 __le32 ObjectId; /* Handle */ 1045 __le32 CtlCmd; /* GetBusInfo */ 1046 }; 1047 1048 struct aac_bus_info_response { 1049 __le32 Status; /* ST_OK */ 1050 __le32 ObjType; 1051 __le32 MethodId; /* unused */ 1052 __le32 ObjectId; /* unused */ 1053 __le32 CtlCmd; /* unused */ 1054 __le32 ProbeComplete; 1055 __le32 BusCount; 1056 __le32 TargetsPerBus; 1057 u8 InitiatorBusId[10]; 1058 u8 BusValid[10]; 1059 }; 1060 1061 /* 1062 * Battery platforms 1063 */ 1064 #define AAC_BAT_REQ_PRESENT (1) 1065 #define AAC_BAT_REQ_NOTPRESENT (2) 1066 #define AAC_BAT_OPT_PRESENT (3) 1067 #define AAC_BAT_OPT_NOTPRESENT (4) 1068 #define AAC_BAT_NOT_SUPPORTED (5) 1069 /* 1070 * cpu types 1071 */ 1072 #define AAC_CPU_SIMULATOR (1) 1073 #define AAC_CPU_I960 (2) 1074 #define AAC_CPU_STRONGARM (3) 1075 1076 /* 1077 * Supported Options 1078 */ 1079 #define AAC_OPT_SNAPSHOT cpu_to_le32(1) 1080 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1) 1081 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2) 1082 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3) 1083 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4) 1084 #define AAC_OPT_RAID50 cpu_to_le32(1<<5) 1085 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6) 1086 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7) 1087 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8) 1088 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9) 1089 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10) 1090 #define AAC_OPT_ALARM cpu_to_le32(1<<11) 1091 #define AAC_OPT_NONDASD cpu_to_le32(1<<12) 1092 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13) 1093 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14) 1094 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16) 1095 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17) 1096 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18) 1097 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28) 1098 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29) 1099 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30) 1100 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31) 1101 1102 /* MSIX context */ 1103 struct aac_msix_ctx { 1104 int vector_no; 1105 struct aac_dev *dev; 1106 }; 1107 1108 struct aac_dev 1109 { 1110 struct list_head entry; 1111 const char *name; 1112 int id; 1113 1114 /* 1115 * negotiated FIB settings 1116 */ 1117 unsigned max_fib_size; 1118 unsigned sg_tablesize; 1119 unsigned max_num_aif; 1120 1121 /* 1122 * Map for 128 fib objects (64k) 1123 */ 1124 dma_addr_t hw_fib_pa; 1125 struct hw_fib *hw_fib_va; 1126 struct hw_fib *aif_base_va; 1127 /* 1128 * Fib Headers 1129 */ 1130 struct fib *fibs; 1131 1132 struct fib *free_fib; 1133 spinlock_t fib_lock; 1134 1135 struct mutex ioctl_mutex; 1136 struct aac_queue_block *queues; 1137 /* 1138 * The user API will use an IOCTL to register itself to receive 1139 * FIBs from the adapter. The following list is used to keep 1140 * track of all the threads that have requested these FIBs. The 1141 * mutex is used to synchronize access to all data associated 1142 * with the adapter fibs. 1143 */ 1144 struct list_head fib_list; 1145 1146 struct adapter_ops a_ops; 1147 unsigned long fsrev; /* Main driver's revision number */ 1148 1149 resource_size_t base_start; /* main IO base */ 1150 resource_size_t dbg_base; /* address of UART 1151 * debug buffer */ 1152 1153 resource_size_t base_size, dbg_size; /* Size of 1154 * mapped in region */ 1155 1156 struct aac_init *init; /* Holds initialization info to communicate with adapter */ 1157 dma_addr_t init_pa; /* Holds physical address of the init struct */ 1158 1159 u32 *host_rrq; /* response queue 1160 * if AAC_COMM_MESSAGE_TYPE1 */ 1161 1162 dma_addr_t host_rrq_pa; /* phys. address */ 1163 /* index into rrq buffer */ 1164 u32 host_rrq_idx[AAC_MAX_MSIX]; 1165 atomic_t rrq_outstanding[AAC_MAX_MSIX]; 1166 u32 fibs_pushed_no; 1167 struct pci_dev *pdev; /* Our PCI interface */ 1168 void * printfbuf; /* pointer to buffer used for printf's from the adapter */ 1169 void * comm_addr; /* Base address of Comm area */ 1170 dma_addr_t comm_phys; /* Physical Address of Comm area */ 1171 size_t comm_size; 1172 1173 struct Scsi_Host *scsi_host_ptr; 1174 int maximum_num_containers; 1175 int maximum_num_physicals; 1176 int maximum_num_channels; 1177 struct fsa_dev_info *fsa_dev; 1178 struct task_struct *thread; 1179 int cardtype; 1180 /* 1181 *This lock will protect the two 32-bit 1182 *writes to the Inbound Queue 1183 */ 1184 spinlock_t iq_lock; 1185 1186 /* 1187 * The following is the device specific extension. 1188 */ 1189 #ifndef AAC_MIN_FOOTPRINT_SIZE 1190 # define AAC_MIN_FOOTPRINT_SIZE 8192 1191 # define AAC_MIN_SRC_BAR0_SIZE 0x400000 1192 # define AAC_MIN_SRC_BAR1_SIZE 0x800 1193 # define AAC_MIN_SRCV_BAR0_SIZE 0x100000 1194 # define AAC_MIN_SRCV_BAR1_SIZE 0x400 1195 #endif 1196 union 1197 { 1198 struct sa_registers __iomem *sa; 1199 struct rx_registers __iomem *rx; 1200 struct rkt_registers __iomem *rkt; 1201 struct { 1202 struct src_registers __iomem *bar0; 1203 char __iomem *bar1; 1204 } src; 1205 } regs; 1206 volatile void __iomem *base, *dbg_base_mapped; 1207 volatile struct rx_inbound __iomem *IndexRegs; 1208 u32 OIMR; /* Mask Register Cache */ 1209 /* 1210 * AIF thread states 1211 */ 1212 u32 aif_thread; 1213 struct aac_adapter_info adapter_info; 1214 struct aac_supplement_adapter_info supplement_adapter_info; 1215 /* These are in adapter info but they are in the io flow so 1216 * lets break them out so we don't have to do an AND to check them 1217 */ 1218 u8 nondasd_support; 1219 u8 jbod; 1220 u8 cache_protected; 1221 u8 dac_support; 1222 u8 needs_dac; 1223 u8 raid_scsi_mode; 1224 u8 comm_interface; 1225 # define AAC_COMM_PRODUCER 0 1226 # define AAC_COMM_MESSAGE 1 1227 # define AAC_COMM_MESSAGE_TYPE1 3 1228 # define AAC_COMM_MESSAGE_TYPE2 4 1229 u8 raw_io_interface; 1230 u8 raw_io_64; 1231 u8 printf_enabled; 1232 u8 in_reset; 1233 u8 msi; 1234 int management_fib_count; 1235 spinlock_t manage_lock; 1236 spinlock_t sync_lock; 1237 int sync_mode; 1238 struct fib *sync_fib; 1239 struct list_head sync_fib_list; 1240 u32 doorbell_mask; 1241 u32 max_msix; /* max. MSI-X vectors */ 1242 u32 vector_cap; /* MSI-X vector capab.*/ 1243 int msi_enabled; /* MSI/MSI-X enabled */ 1244 struct msix_entry msixentry[AAC_MAX_MSIX]; 1245 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */ 1246 u8 adapter_shutdown; 1247 u32 handle_pci_error; 1248 }; 1249 1250 #define aac_adapter_interrupt(dev) \ 1251 (dev)->a_ops.adapter_interrupt(dev) 1252 1253 #define aac_adapter_notify(dev, event) \ 1254 (dev)->a_ops.adapter_notify(dev, event) 1255 1256 #define aac_adapter_disable_int(dev) \ 1257 (dev)->a_ops.adapter_disable_int(dev) 1258 1259 #define aac_adapter_enable_int(dev) \ 1260 (dev)->a_ops.adapter_enable_int(dev) 1261 1262 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \ 1263 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) 1264 1265 #define aac_adapter_check_health(dev) \ 1266 (dev)->a_ops.adapter_check_health(dev) 1267 1268 #define aac_adapter_restart(dev,bled) \ 1269 (dev)->a_ops.adapter_restart(dev,bled) 1270 1271 #define aac_adapter_start(dev) \ 1272 ((dev)->a_ops.adapter_start(dev)) 1273 1274 #define aac_adapter_ioremap(dev, size) \ 1275 (dev)->a_ops.adapter_ioremap(dev, size) 1276 1277 #define aac_adapter_deliver(fib) \ 1278 ((fib)->dev)->a_ops.adapter_deliver(fib) 1279 1280 #define aac_adapter_bounds(dev,cmd,lba) \ 1281 dev->a_ops.adapter_bounds(dev,cmd,lba) 1282 1283 #define aac_adapter_read(fib,cmd,lba,count) \ 1284 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count) 1285 1286 #define aac_adapter_write(fib,cmd,lba,count,fua) \ 1287 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua) 1288 1289 #define aac_adapter_scsi(fib,cmd) \ 1290 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd) 1291 1292 #define aac_adapter_comm(dev,comm) \ 1293 (dev)->a_ops.adapter_comm(dev, comm) 1294 1295 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001) 1296 #define FIB_CONTEXT_FLAG (0x00000002) 1297 #define FIB_CONTEXT_FLAG_WAIT (0x00000004) 1298 #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008) 1299 1300 /* 1301 * Define the command values 1302 */ 1303 1304 #define Null 0 1305 #define GetAttributes 1 1306 #define SetAttributes 2 1307 #define Lookup 3 1308 #define ReadLink 4 1309 #define Read 5 1310 #define Write 6 1311 #define Create 7 1312 #define MakeDirectory 8 1313 #define SymbolicLink 9 1314 #define MakeNode 10 1315 #define Removex 11 1316 #define RemoveDirectoryx 12 1317 #define Rename 13 1318 #define Link 14 1319 #define ReadDirectory 15 1320 #define ReadDirectoryPlus 16 1321 #define FileSystemStatus 17 1322 #define FileSystemInfo 18 1323 #define PathConfigure 19 1324 #define Commit 20 1325 #define Mount 21 1326 #define UnMount 22 1327 #define Newfs 23 1328 #define FsCheck 24 1329 #define FsSync 25 1330 #define SimReadWrite 26 1331 #define SetFileSystemStatus 27 1332 #define BlockRead 28 1333 #define BlockWrite 29 1334 #define NvramIoctl 30 1335 #define FsSyncWait 31 1336 #define ClearArchiveBit 32 1337 #define SetAcl 33 1338 #define GetAcl 34 1339 #define AssignAcl 35 1340 #define FaultInsertion 36 /* Fault Insertion Command */ 1341 #define CrazyCache 37 /* Crazycache */ 1342 1343 #define MAX_FSACOMMAND_NUM 38 1344 1345 1346 /* 1347 * Define the status returns. These are very unixlike although 1348 * most are not in fact used 1349 */ 1350 1351 #define ST_OK 0 1352 #define ST_PERM 1 1353 #define ST_NOENT 2 1354 #define ST_IO 5 1355 #define ST_NXIO 6 1356 #define ST_E2BIG 7 1357 #define ST_ACCES 13 1358 #define ST_EXIST 17 1359 #define ST_XDEV 18 1360 #define ST_NODEV 19 1361 #define ST_NOTDIR 20 1362 #define ST_ISDIR 21 1363 #define ST_INVAL 22 1364 #define ST_FBIG 27 1365 #define ST_NOSPC 28 1366 #define ST_ROFS 30 1367 #define ST_MLINK 31 1368 #define ST_WOULDBLOCK 35 1369 #define ST_NAMETOOLONG 63 1370 #define ST_NOTEMPTY 66 1371 #define ST_DQUOT 69 1372 #define ST_STALE 70 1373 #define ST_REMOTE 71 1374 #define ST_NOT_READY 72 1375 #define ST_BADHANDLE 10001 1376 #define ST_NOT_SYNC 10002 1377 #define ST_BAD_COOKIE 10003 1378 #define ST_NOTSUPP 10004 1379 #define ST_TOOSMALL 10005 1380 #define ST_SERVERFAULT 10006 1381 #define ST_BADTYPE 10007 1382 #define ST_JUKEBOX 10008 1383 #define ST_NOTMOUNTED 10009 1384 #define ST_MAINTMODE 10010 1385 #define ST_STALEACL 10011 1386 1387 /* 1388 * On writes how does the client want the data written. 1389 */ 1390 1391 #define CACHE_CSTABLE 1 1392 #define CACHE_UNSTABLE 2 1393 1394 /* 1395 * Lets the client know at which level the data was committed on 1396 * a write request 1397 */ 1398 1399 #define CMFILE_SYNCH_NVRAM 1 1400 #define CMDATA_SYNCH_NVRAM 2 1401 #define CMFILE_SYNCH 3 1402 #define CMDATA_SYNCH 4 1403 #define CMUNSTABLE 5 1404 1405 #define RIO_TYPE_WRITE 0x0000 1406 #define RIO_TYPE_READ 0x0001 1407 #define RIO_SUREWRITE 0x0008 1408 1409 #define RIO2_IO_TYPE 0x0003 1410 #define RIO2_IO_TYPE_WRITE 0x0000 1411 #define RIO2_IO_TYPE_READ 0x0001 1412 #define RIO2_IO_TYPE_VERIFY 0x0002 1413 #define RIO2_IO_ERROR 0x0004 1414 #define RIO2_IO_SUREWRITE 0x0008 1415 #define RIO2_SGL_CONFORMANT 0x0010 1416 #define RIO2_SG_FORMAT 0xF000 1417 #define RIO2_SG_FORMAT_ARC 0x0000 1418 #define RIO2_SG_FORMAT_SRL 0x1000 1419 #define RIO2_SG_FORMAT_IEEE1212 0x2000 1420 1421 struct aac_read 1422 { 1423 __le32 command; 1424 __le32 cid; 1425 __le32 block; 1426 __le32 count; 1427 struct sgmap sg; // Must be last in struct because it is variable 1428 }; 1429 1430 struct aac_read64 1431 { 1432 __le32 command; 1433 __le16 cid; 1434 __le16 sector_count; 1435 __le32 block; 1436 __le16 pad; 1437 __le16 flags; 1438 struct sgmap64 sg; // Must be last in struct because it is variable 1439 }; 1440 1441 struct aac_read_reply 1442 { 1443 __le32 status; 1444 __le32 count; 1445 }; 1446 1447 struct aac_write 1448 { 1449 __le32 command; 1450 __le32 cid; 1451 __le32 block; 1452 __le32 count; 1453 __le32 stable; // Not used 1454 struct sgmap sg; // Must be last in struct because it is variable 1455 }; 1456 1457 struct aac_write64 1458 { 1459 __le32 command; 1460 __le16 cid; 1461 __le16 sector_count; 1462 __le32 block; 1463 __le16 pad; 1464 __le16 flags; 1465 struct sgmap64 sg; // Must be last in struct because it is variable 1466 }; 1467 struct aac_write_reply 1468 { 1469 __le32 status; 1470 __le32 count; 1471 __le32 committed; 1472 }; 1473 1474 struct aac_raw_io 1475 { 1476 __le32 block[2]; 1477 __le32 count; 1478 __le16 cid; 1479 __le16 flags; /* 00 W, 01 R */ 1480 __le16 bpTotal; /* reserved for F/W use */ 1481 __le16 bpComplete; /* reserved for F/W use */ 1482 struct sgmapraw sg; 1483 }; 1484 1485 struct aac_raw_io2 { 1486 __le32 blockLow; 1487 __le32 blockHigh; 1488 __le32 byteCount; 1489 __le16 cid; 1490 __le16 flags; /* RIO2 flags */ 1491 __le32 sgeFirstSize; /* size of first sge el. */ 1492 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */ 1493 u8 sgeCnt; /* only 8 bits required */ 1494 u8 bpTotal; /* reserved for F/W use */ 1495 u8 bpComplete; /* reserved for F/W use */ 1496 u8 sgeFirstIndex; /* reserved for F/W use */ 1497 u8 unused[4]; 1498 struct sge_ieee1212 sge[1]; 1499 }; 1500 1501 #define CT_FLUSH_CACHE 129 1502 struct aac_synchronize { 1503 __le32 command; /* VM_ContainerConfig */ 1504 __le32 type; /* CT_FLUSH_CACHE */ 1505 __le32 cid; 1506 __le32 parm1; 1507 __le32 parm2; 1508 __le32 parm3; 1509 __le32 parm4; 1510 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */ 1511 }; 1512 1513 struct aac_synchronize_reply { 1514 __le32 dummy0; 1515 __le32 dummy1; 1516 __le32 status; /* CT_OK */ 1517 __le32 parm1; 1518 __le32 parm2; 1519 __le32 parm3; 1520 __le32 parm4; 1521 __le32 parm5; 1522 u8 data[16]; 1523 }; 1524 1525 #define CT_POWER_MANAGEMENT 245 1526 #define CT_PM_START_UNIT 2 1527 #define CT_PM_STOP_UNIT 3 1528 #define CT_PM_UNIT_IMMEDIATE 1 1529 struct aac_power_management { 1530 __le32 command; /* VM_ContainerConfig */ 1531 __le32 type; /* CT_POWER_MANAGEMENT */ 1532 __le32 sub; /* CT_PM_* */ 1533 __le32 cid; 1534 __le32 parm; /* CT_PM_sub_* */ 1535 }; 1536 1537 #define CT_PAUSE_IO 65 1538 #define CT_RELEASE_IO 66 1539 struct aac_pause { 1540 __le32 command; /* VM_ContainerConfig */ 1541 __le32 type; /* CT_PAUSE_IO */ 1542 __le32 timeout; /* 10ms ticks */ 1543 __le32 min; 1544 __le32 noRescan; 1545 __le32 parm3; 1546 __le32 parm4; 1547 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */ 1548 }; 1549 1550 struct aac_srb 1551 { 1552 __le32 function; 1553 __le32 channel; 1554 __le32 id; 1555 __le32 lun; 1556 __le32 timeout; 1557 __le32 flags; 1558 __le32 count; // Data xfer size 1559 __le32 retry_limit; 1560 __le32 cdb_size; 1561 u8 cdb[16]; 1562 struct sgmap sg; 1563 }; 1564 1565 /* 1566 * This and associated data structs are used by the 1567 * ioctl caller and are in cpu order. 1568 */ 1569 struct user_aac_srb 1570 { 1571 u32 function; 1572 u32 channel; 1573 u32 id; 1574 u32 lun; 1575 u32 timeout; 1576 u32 flags; 1577 u32 count; // Data xfer size 1578 u32 retry_limit; 1579 u32 cdb_size; 1580 u8 cdb[16]; 1581 struct user_sgmap sg; 1582 }; 1583 1584 #define AAC_SENSE_BUFFERSIZE 30 1585 1586 struct aac_srb_reply 1587 { 1588 __le32 status; 1589 __le32 srb_status; 1590 __le32 scsi_status; 1591 __le32 data_xfer_length; 1592 __le32 sense_data_size; 1593 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE 1594 }; 1595 /* 1596 * SRB Flags 1597 */ 1598 #define SRB_NoDataXfer 0x0000 1599 #define SRB_DisableDisconnect 0x0004 1600 #define SRB_DisableSynchTransfer 0x0008 1601 #define SRB_BypassFrozenQueue 0x0010 1602 #define SRB_DisableAutosense 0x0020 1603 #define SRB_DataIn 0x0040 1604 #define SRB_DataOut 0x0080 1605 1606 /* 1607 * SRB Functions - set in aac_srb->function 1608 */ 1609 #define SRBF_ExecuteScsi 0x0000 1610 #define SRBF_ClaimDevice 0x0001 1611 #define SRBF_IO_Control 0x0002 1612 #define SRBF_ReceiveEvent 0x0003 1613 #define SRBF_ReleaseQueue 0x0004 1614 #define SRBF_AttachDevice 0x0005 1615 #define SRBF_ReleaseDevice 0x0006 1616 #define SRBF_Shutdown 0x0007 1617 #define SRBF_Flush 0x0008 1618 #define SRBF_AbortCommand 0x0010 1619 #define SRBF_ReleaseRecovery 0x0011 1620 #define SRBF_ResetBus 0x0012 1621 #define SRBF_ResetDevice 0x0013 1622 #define SRBF_TerminateIO 0x0014 1623 #define SRBF_FlushQueue 0x0015 1624 #define SRBF_RemoveDevice 0x0016 1625 #define SRBF_DomainValidation 0x0017 1626 1627 /* 1628 * SRB SCSI Status - set in aac_srb->scsi_status 1629 */ 1630 #define SRB_STATUS_PENDING 0x00 1631 #define SRB_STATUS_SUCCESS 0x01 1632 #define SRB_STATUS_ABORTED 0x02 1633 #define SRB_STATUS_ABORT_FAILED 0x03 1634 #define SRB_STATUS_ERROR 0x04 1635 #define SRB_STATUS_BUSY 0x05 1636 #define SRB_STATUS_INVALID_REQUEST 0x06 1637 #define SRB_STATUS_INVALID_PATH_ID 0x07 1638 #define SRB_STATUS_NO_DEVICE 0x08 1639 #define SRB_STATUS_TIMEOUT 0x09 1640 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A 1641 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B 1642 #define SRB_STATUS_MESSAGE_REJECTED 0x0D 1643 #define SRB_STATUS_BUS_RESET 0x0E 1644 #define SRB_STATUS_PARITY_ERROR 0x0F 1645 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10 1646 #define SRB_STATUS_NO_HBA 0x11 1647 #define SRB_STATUS_DATA_OVERRUN 0x12 1648 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13 1649 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14 1650 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15 1651 #define SRB_STATUS_REQUEST_FLUSHED 0x16 1652 #define SRB_STATUS_DELAYED_RETRY 0x17 1653 #define SRB_STATUS_INVALID_LUN 0x20 1654 #define SRB_STATUS_INVALID_TARGET_ID 0x21 1655 #define SRB_STATUS_BAD_FUNCTION 0x22 1656 #define SRB_STATUS_ERROR_RECOVERY 0x23 1657 #define SRB_STATUS_NOT_STARTED 0x24 1658 #define SRB_STATUS_NOT_IN_USE 0x30 1659 #define SRB_STATUS_FORCE_ABORT 0x31 1660 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32 1661 1662 /* 1663 * Object-Server / Volume-Manager Dispatch Classes 1664 */ 1665 1666 #define VM_Null 0 1667 #define VM_NameServe 1 1668 #define VM_ContainerConfig 2 1669 #define VM_Ioctl 3 1670 #define VM_FilesystemIoctl 4 1671 #define VM_CloseAll 5 1672 #define VM_CtBlockRead 6 1673 #define VM_CtBlockWrite 7 1674 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */ 1675 #define VM_SliceBlockWrite 9 1676 #define VM_DriveBlockRead 10 /* raw access to physical devices */ 1677 #define VM_DriveBlockWrite 11 1678 #define VM_EnclosureMgt 12 /* enclosure management */ 1679 #define VM_Unused 13 /* used to be diskset management */ 1680 #define VM_CtBlockVerify 14 1681 #define VM_CtPerf 15 /* performance test */ 1682 #define VM_CtBlockRead64 16 1683 #define VM_CtBlockWrite64 17 1684 #define VM_CtBlockVerify64 18 1685 #define VM_CtHostRead64 19 1686 #define VM_CtHostWrite64 20 1687 #define VM_DrvErrTblLog 21 1688 #define VM_NameServe64 22 1689 #define VM_NameServeAllBlk 30 1690 1691 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */ 1692 1693 /* 1694 * Descriptive information (eg, vital stats) 1695 * that a content manager might report. The 1696 * FileArray filesystem component is one example 1697 * of a content manager. Raw mode might be 1698 * another. 1699 */ 1700 1701 struct aac_fsinfo { 1702 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */ 1703 __le32 fsBlockSize; 1704 __le32 fsFragSize; 1705 __le32 fsMaxExtendSize; 1706 __le32 fsSpaceUnits; 1707 __le32 fsMaxNumFiles; 1708 __le32 fsNumFreeFiles; 1709 __le32 fsInodeDensity; 1710 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */ 1711 1712 struct aac_blockdevinfo { 1713 __le32 block_size; 1714 }; 1715 1716 union aac_contentinfo { 1717 struct aac_fsinfo filesys; 1718 struct aac_blockdevinfo bdevinfo; 1719 }; 1720 1721 /* 1722 * Query for Container Configuration Status 1723 */ 1724 1725 #define CT_GET_CONFIG_STATUS 147 1726 struct aac_get_config_status { 1727 __le32 command; /* VM_ContainerConfig */ 1728 __le32 type; /* CT_GET_CONFIG_STATUS */ 1729 __le32 parm1; 1730 __le32 parm2; 1731 __le32 parm3; 1732 __le32 parm4; 1733 __le32 parm5; 1734 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */ 1735 }; 1736 1737 #define CFACT_CONTINUE 0 1738 #define CFACT_PAUSE 1 1739 #define CFACT_ABORT 2 1740 struct aac_get_config_status_resp { 1741 __le32 response; /* ST_OK */ 1742 __le32 dummy0; 1743 __le32 status; /* CT_OK */ 1744 __le32 parm1; 1745 __le32 parm2; 1746 __le32 parm3; 1747 __le32 parm4; 1748 __le32 parm5; 1749 struct { 1750 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */ 1751 __le16 flags; 1752 __le16 count; 1753 } data; 1754 }; 1755 1756 /* 1757 * Accept the configuration as-is 1758 */ 1759 1760 #define CT_COMMIT_CONFIG 152 1761 1762 struct aac_commit_config { 1763 __le32 command; /* VM_ContainerConfig */ 1764 __le32 type; /* CT_COMMIT_CONFIG */ 1765 }; 1766 1767 /* 1768 * Query for Container Configuration Status 1769 */ 1770 1771 #define CT_GET_CONTAINER_COUNT 4 1772 struct aac_get_container_count { 1773 __le32 command; /* VM_ContainerConfig */ 1774 __le32 type; /* CT_GET_CONTAINER_COUNT */ 1775 }; 1776 1777 struct aac_get_container_count_resp { 1778 __le32 response; /* ST_OK */ 1779 __le32 dummy0; 1780 __le32 MaxContainers; 1781 __le32 ContainerSwitchEntries; 1782 __le32 MaxPartitions; 1783 __le32 MaxSimpleVolumes; 1784 }; 1785 1786 1787 /* 1788 * Query for "mountable" objects, ie, objects that are typically 1789 * associated with a drive letter on the client (host) side. 1790 */ 1791 1792 struct aac_mntent { 1793 __le32 oid; 1794 u8 name[16]; /* if applicable */ 1795 struct creation_info create_info; /* if applicable */ 1796 __le32 capacity; 1797 __le32 vol; /* substrate structure */ 1798 __le32 obj; /* FT_FILESYS, etc. */ 1799 __le32 state; /* unready for mounting, 1800 readonly, etc. */ 1801 union aac_contentinfo fileinfo; /* Info specific to content 1802 manager (eg, filesystem) */ 1803 __le32 altoid; /* != oid <==> snapshot or 1804 broken mirror exists */ 1805 __le32 capacityhigh; 1806 }; 1807 1808 #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */ 1809 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */ 1810 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */ 1811 #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */ 1812 1813 struct aac_query_mount { 1814 __le32 command; 1815 __le32 type; 1816 __le32 count; 1817 }; 1818 1819 struct aac_mount { 1820 __le32 status; 1821 __le32 type; /* should be same as that requested */ 1822 __le32 count; 1823 struct aac_mntent mnt[1]; 1824 }; 1825 1826 #define CT_READ_NAME 130 1827 struct aac_get_name { 1828 __le32 command; /* VM_ContainerConfig */ 1829 __le32 type; /* CT_READ_NAME */ 1830 __le32 cid; 1831 __le32 parm1; 1832 __le32 parm2; 1833 __le32 parm3; 1834 __le32 parm4; 1835 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */ 1836 }; 1837 1838 struct aac_get_name_resp { 1839 __le32 dummy0; 1840 __le32 dummy1; 1841 __le32 status; /* CT_OK */ 1842 __le32 parm1; 1843 __le32 parm2; 1844 __le32 parm3; 1845 __le32 parm4; 1846 __le32 parm5; 1847 u8 data[16]; 1848 }; 1849 1850 #define CT_CID_TO_32BITS_UID 165 1851 struct aac_get_serial { 1852 __le32 command; /* VM_ContainerConfig */ 1853 __le32 type; /* CT_CID_TO_32BITS_UID */ 1854 __le32 cid; 1855 }; 1856 1857 struct aac_get_serial_resp { 1858 __le32 dummy0; 1859 __le32 dummy1; 1860 __le32 status; /* CT_OK */ 1861 __le32 uid; 1862 }; 1863 1864 /* 1865 * The following command is sent to shut down each container. 1866 */ 1867 1868 struct aac_close { 1869 __le32 command; 1870 __le32 cid; 1871 }; 1872 1873 struct aac_query_disk 1874 { 1875 s32 cnum; 1876 s32 bus; 1877 s32 id; 1878 s32 lun; 1879 u32 valid; 1880 u32 locked; 1881 u32 deleted; 1882 s32 instance; 1883 s8 name[10]; 1884 u32 unmapped; 1885 }; 1886 1887 struct aac_delete_disk { 1888 u32 disknum; 1889 u32 cnum; 1890 }; 1891 1892 struct fib_ioctl 1893 { 1894 u32 fibctx; 1895 s32 wait; 1896 char __user *fib; 1897 }; 1898 1899 struct revision 1900 { 1901 u32 compat; 1902 __le32 version; 1903 __le32 build; 1904 }; 1905 1906 1907 /* 1908 * Ugly - non Linux like ioctl coding for back compat. 1909 */ 1910 1911 #define CTL_CODE(function, method) ( \ 1912 (4<< 16) | ((function) << 2) | (method) \ 1913 ) 1914 1915 /* 1916 * Define the method codes for how buffers are passed for I/O and FS 1917 * controls 1918 */ 1919 1920 #define METHOD_BUFFERED 0 1921 #define METHOD_NEITHER 3 1922 1923 /* 1924 * Filesystem ioctls 1925 */ 1926 1927 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED) 1928 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED) 1929 #define FSACTL_DELETE_DISK 0x163 1930 #define FSACTL_QUERY_DISK 0x173 1931 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED) 1932 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED) 1933 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED) 1934 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED) 1935 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED) 1936 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER) 1937 #define FSACTL_GET_CONTAINERS 2131 1938 #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED) 1939 1940 1941 struct aac_common 1942 { 1943 /* 1944 * If this value is set to 1 then interrupt moderation will occur 1945 * in the base commuication support. 1946 */ 1947 u32 irq_mod; 1948 u32 peak_fibs; 1949 u32 zero_fibs; 1950 u32 fib_timeouts; 1951 /* 1952 * Statistical counters in debug mode 1953 */ 1954 #ifdef DBG 1955 u32 FibsSent; 1956 u32 FibRecved; 1957 u32 NoResponseSent; 1958 u32 NoResponseRecved; 1959 u32 AsyncSent; 1960 u32 AsyncRecved; 1961 u32 NormalSent; 1962 u32 NormalRecved; 1963 #endif 1964 }; 1965 1966 extern struct aac_common aac_config; 1967 1968 1969 /* 1970 * The following macro is used when sending and receiving FIBs. It is 1971 * only used for debugging. 1972 */ 1973 1974 #ifdef DBG 1975 #define FIB_COUNTER_INCREMENT(counter) (counter)++ 1976 #else 1977 #define FIB_COUNTER_INCREMENT(counter) 1978 #endif 1979 1980 /* 1981 * Adapter direct commands 1982 * Monitor/Kernel API 1983 */ 1984 1985 #define BREAKPOINT_REQUEST 0x00000004 1986 #define INIT_STRUCT_BASE_ADDRESS 0x00000005 1987 #define READ_PERMANENT_PARAMETERS 0x0000000a 1988 #define WRITE_PERMANENT_PARAMETERS 0x0000000b 1989 #define HOST_CRASHING 0x0000000d 1990 #define SEND_SYNCHRONOUS_FIB 0x0000000c 1991 #define COMMAND_POST_RESULTS 0x00000014 1992 #define GET_ADAPTER_PROPERTIES 0x00000019 1993 #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023 1994 #define RCV_TEMP_READINGS 0x00000025 1995 #define GET_COMM_PREFERRED_SETTINGS 0x00000026 1996 #define IOP_RESET 0x00001000 1997 #define IOP_RESET_ALWAYS 0x00001001 1998 #define RE_INIT_ADAPTER 0x000000ee 1999 2000 /* 2001 * Adapter Status Register 2002 * 2003 * Phase Staus mailbox is 32bits: 2004 * <31:16> = Phase Status 2005 * <15:0> = Phase 2006 * 2007 * The adapter reports is present state through the phase. Only 2008 * a single phase should be ever be set. Each phase can have multiple 2009 * phase status bits to provide more detailed information about the 2010 * state of the board. Care should be taken to ensure that any phase 2011 * status bits that are set when changing the phase are also valid 2012 * for the new phase or be cleared out. Adapter software (monitor, 2013 * iflash, kernel) is responsible for properly maintining the phase 2014 * status mailbox when it is running. 2015 * 2016 * MONKER_API Phases 2017 * 2018 * Phases are bit oriented. It is NOT valid to have multiple bits set 2019 */ 2020 2021 #define SELF_TEST_FAILED 0x00000004 2022 #define MONITOR_PANIC 0x00000020 2023 #define KERNEL_UP_AND_RUNNING 0x00000080 2024 #define KERNEL_PANIC 0x00000100 2025 #define FLASH_UPD_PENDING 0x00002000 2026 #define FLASH_UPD_SUCCESS 0x00004000 2027 #define FLASH_UPD_FAILED 0x00008000 2028 #define FWUPD_TIMEOUT (5 * 60) 2029 2030 /* 2031 * Doorbell bit defines 2032 */ 2033 2034 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */ 2035 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */ 2036 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */ 2037 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */ 2038 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */ 2039 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */ 2040 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */ 2041 #define DoorBellAifPending (1<<6) /* Adapter -> Host */ 2042 2043 /* PMC specific outbound doorbell bits */ 2044 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */ 2045 2046 /* 2047 * For FIB communication, we need all of the following things 2048 * to send back to the user. 2049 */ 2050 2051 #define AifCmdEventNotify 1 /* Notify of event */ 2052 #define AifEnConfigChange 3 /* Adapter configuration change */ 2053 #define AifEnContainerChange 4 /* Container configuration change */ 2054 #define AifEnDeviceFailure 5 /* SCSI device failed */ 2055 #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */ 2056 #define EM_DRIVE_INSERTION 31 2057 #define EM_DRIVE_REMOVAL 32 2058 #define EM_SES_DRIVE_INSERTION 33 2059 #define EM_SES_DRIVE_REMOVAL 26 2060 #define AifEnBatteryEvent 14 /* Change in Battery State */ 2061 #define AifEnAddContainer 15 /* A new array was created */ 2062 #define AifEnDeleteContainer 16 /* A container was deleted */ 2063 #define AifEnExpEvent 23 /* Firmware Event Log */ 2064 #define AifExeFirmwarePanic 3 /* Firmware Event Panic */ 2065 #define AifHighPriority 3 /* Highest Priority Event */ 2066 #define AifEnAddJBOD 30 /* JBOD created */ 2067 #define AifEnDeleteJBOD 31 /* JBOD deleted */ 2068 2069 #define AifBuManagerEvent 42 /* Bu management*/ 2070 #define AifBuCacheDataLoss 10 2071 #define AifBuCacheDataRecover 11 2072 2073 #define AifCmdJobProgress 2 /* Progress report */ 2074 #define AifJobCtrZero 101 /* Array Zero progress */ 2075 #define AifJobStsSuccess 1 /* Job completes */ 2076 #define AifJobStsRunning 102 /* Job running */ 2077 #define AifCmdAPIReport 3 /* Report from other user of API */ 2078 #define AifCmdDriverNotify 4 /* Notify host driver of event */ 2079 #define AifDenMorphComplete 200 /* A morph operation completed */ 2080 #define AifDenVolumeExtendComplete 201 /* A volume extend completed */ 2081 #define AifReqJobList 100 /* Gets back complete job list */ 2082 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */ 2083 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */ 2084 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */ 2085 #define AifReqTerminateJob 104 /* Terminates job */ 2086 #define AifReqSuspendJob 105 /* Suspends a job */ 2087 #define AifReqResumeJob 106 /* Resumes a job */ 2088 #define AifReqSendAPIReport 107 /* API generic report requests */ 2089 #define AifReqAPIJobStart 108 /* Start a job from the API */ 2090 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */ 2091 #define AifReqAPIJobFinish 110 /* Finish a job from the API */ 2092 2093 /* PMC NEW COMM: Request the event data */ 2094 #define AifReqEvent 200 2095 2096 /* RAW device deleted */ 2097 #define AifRawDeviceRemove 203 2098 2099 /* 2100 * Adapter Initiated FIB command structures. Start with the adapter 2101 * initiated FIBs that really come from the adapter, and get responded 2102 * to by the host. 2103 */ 2104 2105 struct aac_aifcmd { 2106 __le32 command; /* Tell host what type of notify this is */ 2107 __le32 seqnum; /* To allow ordering of reports (if necessary) */ 2108 u8 data[1]; /* Undefined length (from kernel viewpoint) */ 2109 }; 2110 2111 /** 2112 * Convert capacity to cylinders 2113 * accounting for the fact capacity could be a 64 bit value 2114 * 2115 */ 2116 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor) 2117 { 2118 sector_div(capacity, divisor); 2119 return capacity; 2120 } 2121 2122 /* SCp.phase values */ 2123 #define AAC_OWNER_MIDLEVEL 0x101 2124 #define AAC_OWNER_LOWLEVEL 0x102 2125 #define AAC_OWNER_ERROR_HANDLER 0x103 2126 #define AAC_OWNER_FIRMWARE 0x106 2127 2128 int aac_acquire_irq(struct aac_dev *dev); 2129 void aac_free_irq(struct aac_dev *dev); 2130 const char *aac_driverinfo(struct Scsi_Host *); 2131 void aac_fib_vector_assign(struct aac_dev *dev); 2132 struct fib *aac_fib_alloc(struct aac_dev *dev); 2133 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd); 2134 int aac_fib_setup(struct aac_dev *dev); 2135 void aac_fib_map_free(struct aac_dev *dev); 2136 void aac_fib_free(struct fib * context); 2137 void aac_fib_init(struct fib * context); 2138 void aac_printf(struct aac_dev *dev, u32 val); 2139 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt); 2140 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry); 2141 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum); 2142 int aac_fib_complete(struct fib * context); 2143 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data) 2144 struct aac_dev *aac_init_adapter(struct aac_dev *dev); 2145 void aac_src_access_devreg(struct aac_dev *dev, int mode); 2146 int aac_get_config_status(struct aac_dev *dev, int commit_flag); 2147 int aac_get_containers(struct aac_dev *dev); 2148 int aac_scsi_cmd(struct scsi_cmnd *cmd); 2149 int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg); 2150 #ifndef shost_to_class 2151 #define shost_to_class(shost) &shost->shost_dev 2152 #endif 2153 ssize_t aac_get_serial_number(struct device *dev, char *buf); 2154 int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg); 2155 int aac_rx_init(struct aac_dev *dev); 2156 int aac_rkt_init(struct aac_dev *dev); 2157 int aac_nark_init(struct aac_dev *dev); 2158 int aac_sa_init(struct aac_dev *dev); 2159 int aac_src_init(struct aac_dev *dev); 2160 int aac_srcv_init(struct aac_dev *dev); 2161 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify); 2162 void aac_define_int_mode(struct aac_dev *dev); 2163 unsigned int aac_response_normal(struct aac_queue * q); 2164 unsigned int aac_command_normal(struct aac_queue * q); 2165 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index, 2166 int isAif, int isFastResponse, 2167 struct hw_fib *aif_fib); 2168 int aac_reset_adapter(struct aac_dev * dev, int forced); 2169 int aac_check_health(struct aac_dev * dev); 2170 int aac_command_thread(void *data); 2171 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx); 2172 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size); 2173 struct aac_driver_ident* aac_get_driver_ident(int devtype); 2174 int aac_get_adapter_info(struct aac_dev* dev); 2175 int aac_send_shutdown(struct aac_dev *dev); 2176 int aac_probe_container(struct aac_dev *dev, int cid); 2177 int _aac_rx_init(struct aac_dev *dev); 2178 int aac_rx_select_comm(struct aac_dev *dev, int comm); 2179 int aac_rx_deliver_producer(struct fib * fib); 2180 char * get_container_type(unsigned type); 2181 extern int numacb; 2182 extern int acbsize; 2183 extern char aac_driver_version[]; 2184 extern int startup_timeout; 2185 extern int aif_timeout; 2186 extern int expose_physicals; 2187 extern int aac_reset_devices; 2188 extern int aac_msi; 2189 extern int aac_commit; 2190 extern int update_interval; 2191 extern int check_interval; 2192 extern int aac_check_reset; 2193