1 /* 2 * Adaptec AAC series RAID controller driver 3 * (c) Copyright 2001 Red Hat Inc. <alan@redhat.com> 4 * 5 * based on the old aacraid driver that is.. 6 * Adaptec aacraid device driver for Linux. 7 * 8 * Copyright (c) 2000-2010 Adaptec, Inc. 9 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com) 10 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com) 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Module Name: 27 * aacraid.h 28 * 29 * Abstract: Contains all routines for control of the aacraid driver 30 * 31 */ 32 33 #ifndef _AACRAID_H_ 34 #define _AACRAID_H_ 35 #ifndef dprintk 36 # define dprintk(x) 37 #endif 38 /* eg: if (nblank(dprintk(x))) */ 39 #define _nblank(x) #x 40 #define nblank(x) _nblank(x)[0] 41 42 #include <linux/interrupt.h> 43 #include <linux/pci.h> 44 45 /*------------------------------------------------------------------------------ 46 * D E F I N E S 47 *----------------------------------------------------------------------------*/ 48 49 #define AAC_MAX_MSIX 32 /* vectors */ 50 #define AAC_PCI_MSI_ENABLE 0x8000 51 52 enum { 53 AAC_ENABLE_INTERRUPT = 0x0, 54 AAC_DISABLE_INTERRUPT, 55 AAC_ENABLE_MSIX, 56 AAC_DISABLE_MSIX, 57 AAC_CLEAR_AIF_BIT, 58 AAC_CLEAR_SYNC_BIT, 59 AAC_ENABLE_INTX 60 }; 61 62 #define AAC_INT_MODE_INTX (1<<0) 63 #define AAC_INT_MODE_MSI (1<<1) 64 #define AAC_INT_MODE_AIF (1<<2) 65 #define AAC_INT_MODE_SYNC (1<<3) 66 #define AAC_INT_MODE_MSIX (1<<16) 67 68 #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb 69 #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa 70 #define AAC_INT_DISABLE_ALL 0xffffffff 71 72 /* Bit definitions in IOA->Host Interrupt Register */ 73 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31) 74 #define PMC_IOARCB_TRANSFER_FAILED (1<<28) 75 #define PMC_IOA_UNIT_CHECK (1<<27) 76 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26) 77 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25) 78 #define PMC_IOARRIN_LOST (1<<4) 79 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3) 80 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2) 81 #define PMC_HOST_RRQ_VALID (1<<1) 82 #define PMC_OPERATIONAL_STATUS (1<<31) 83 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0) 84 85 #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \ 86 PMC_IOA_UNIT_CHECK | \ 87 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \ 88 PMC_IOARRIN_LOST | \ 89 PMC_SYSTEM_BUS_MMIO_ERROR | \ 90 PMC_IOA_PROCESSOR_IN_ERROR_STATE) 91 92 #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \ 93 PMC_HOST_RRQ_VALID | \ 94 PMC_TRANSITION_TO_OPERATIONAL | \ 95 PMC_ALLOW_MSIX_VECTOR0) 96 #define PMC_GLOBAL_INT_BIT2 0x00000004 97 #define PMC_GLOBAL_INT_BIT0 0x00000001 98 99 #ifndef AAC_DRIVER_BUILD 100 # define AAC_DRIVER_BUILD 50834 101 # define AAC_DRIVER_BRANCH "-custom" 102 #endif 103 #define MAXIMUM_NUM_CONTAINERS 32 104 105 #define AAC_NUM_MGT_FIB 8 106 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB) 107 #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB) 108 109 #define AAC_MAX_LUN 256 110 111 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff) 112 #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256) 113 114 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE 115 116 #define AAC_MAX_NATIVE_TARGETS 1024 117 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */ 118 #define AAC_MAX_BUSES 5 119 #define AAC_MAX_TARGETS 256 120 #define AAC_MAX_NATIVE_SIZE 2048 121 #define FW_ERROR_BUFFER_SIZE 512 122 123 /* Thor AIF events */ 124 #define SA_AIF_HOTPLUG (1<<1) 125 #define SA_AIF_HARDWARE (1<<2) 126 #define SA_AIF_PDEV_CHANGE (1<<4) 127 #define SA_AIF_LDEV_CHANGE (1<<5) 128 #define SA_AIF_BPSTAT_CHANGE (1<<30) 129 #define SA_AIF_BPCFG_CHANGE (1<<31) 130 131 #define HBA_MAX_SG_EMBEDDED 28 132 #define HBA_MAX_SG_SEPARATE 90 133 #define HBA_SENSE_DATA_LEN_MAX 32 134 #define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002 135 #define HBA_SGL_FLAGS_EXT 0x80000000UL 136 137 struct aac_hba_sgl { 138 u32 addr_lo; /* Lower 32-bits of SGL element address */ 139 u32 addr_hi; /* Upper 32-bits of SGL element address */ 140 u32 len; /* Length of SGL element in bytes */ 141 u32 flags; /* SGL element flags */ 142 }; 143 144 enum { 145 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40, 146 HBA_IU_TYPE_SCSI_TM_REQ = 0x41, 147 HBA_IU_TYPE_SATA_REQ = 0x42, 148 HBA_IU_TYPE_RESP = 0x60, 149 HBA_IU_TYPE_COALESCED_RESP = 0x61, 150 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70 151 }; 152 153 enum { 154 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1, 155 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2, 156 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4, 157 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8 158 }; 159 160 enum { 161 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0, 162 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT, 163 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR, 164 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE 165 }; 166 167 enum { 168 HBA_RESP_DATAPRES_NO_DATA = 0x0, 169 HBA_RESP_DATAPRES_RESPONSE_DATA, 170 HBA_RESP_DATAPRES_SENSE_DATA 171 }; 172 173 enum { 174 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0, 175 HBA_RESP_SVCRES_FAILURE, 176 HBA_RESP_SVCRES_TMF_COMPLETE, 177 HBA_RESP_SVCRES_TMF_SUCCEEDED, 178 HBA_RESP_SVCRES_TMF_REJECTED, 179 HBA_RESP_SVCRES_TMF_LUN_INVALID 180 }; 181 182 enum { 183 HBA_RESP_STAT_IO_ERROR = 0x1, 184 HBA_RESP_STAT_IO_ABORTED, 185 HBA_RESP_STAT_NO_PATH_TO_DEVICE, 186 HBA_RESP_STAT_INVALID_DEVICE, 187 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE, 188 HBA_RESP_STAT_UNDERRUN = 0x51, 189 HBA_RESP_STAT_OVERRUN = 0x75 190 }; 191 192 struct aac_hba_cmd_req { 193 u8 iu_type; /* HBA information unit type */ 194 /* 195 * byte1: 196 * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT 197 * [2] TYPE - 0=PCI, 1=DDR 198 * [3] CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled 199 */ 200 u8 byte1; 201 u8 reply_qid; /* Host reply queue to post response to */ 202 u8 reserved1; 203 __le32 it_nexus; /* Device handle for the request */ 204 __le32 request_id; /* Sender context */ 205 /* Lower 32-bits of tweak value for crypto enabled IOs */ 206 __le32 tweak_value_lo; 207 u8 cdb[16]; /* SCSI CDB of the command */ 208 u8 lun[8]; /* SCSI LUN of the command */ 209 210 /* Total data length in bytes to be read/written (if any) */ 211 __le32 data_length; 212 213 /* [2:0] Task Attribute, [6:3] Command Priority */ 214 u8 attr_prio; 215 216 /* Number of SGL elements embedded in the HBA req */ 217 u8 emb_data_desc_count; 218 219 __le16 dek_index; /* DEK index for crypto enabled IOs */ 220 221 /* Lower 32-bits of reserved error data target location on the host */ 222 __le32 error_ptr_lo; 223 224 /* Upper 32-bits of reserved error data target location on the host */ 225 __le32 error_ptr_hi; 226 227 /* Length of reserved error data area on the host in bytes */ 228 __le32 error_length; 229 230 /* Upper 32-bits of tweak value for crypto enabled IOs */ 231 __le32 tweak_value_hi; 232 233 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */ 234 235 /* 236 * structure must not exceed 237 * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE 238 */ 239 }; 240 241 /* Task Management Functions (TMF) */ 242 #define HBA_TMF_ABORT_TASK 0x01 243 #define HBA_TMF_LUN_RESET 0x08 244 245 struct aac_hba_tm_req { 246 u8 iu_type; /* HBA information unit type */ 247 u8 reply_qid; /* Host reply queue to post response to */ 248 u8 tmf; /* Task management function */ 249 u8 reserved1; 250 251 __le32 it_nexus; /* Device handle for the command */ 252 253 u8 lun[8]; /* SCSI LUN */ 254 255 /* Used to hold sender context. */ 256 __le32 request_id; /* Sender context */ 257 __le32 reserved2; 258 259 /* Request identifier of managed task */ 260 __le32 managed_request_id; /* Sender context being managed */ 261 __le32 reserved3; 262 263 /* Lower 32-bits of reserved error data target location on the host */ 264 __le32 error_ptr_lo; 265 /* Upper 32-bits of reserved error data target location on the host */ 266 __le32 error_ptr_hi; 267 /* Length of reserved error data area on the host in bytes */ 268 __le32 error_length; 269 }; 270 271 struct aac_hba_reset_req { 272 u8 iu_type; /* HBA information unit type */ 273 /* 0 - reset specified device, 1 - reset all devices */ 274 u8 reset_type; 275 u8 reply_qid; /* Host reply queue to post response to */ 276 u8 reserved1; 277 278 __le32 it_nexus; /* Device handle for the command */ 279 __le32 request_id; /* Sender context */ 280 /* Lower 32-bits of reserved error data target location on the host */ 281 __le32 error_ptr_lo; 282 /* Upper 32-bits of reserved error data target location on the host */ 283 __le32 error_ptr_hi; 284 /* Length of reserved error data area on the host in bytes */ 285 __le32 error_length; 286 }; 287 288 struct aac_hba_resp { 289 u8 iu_type; /* HBA information unit type */ 290 u8 reserved1[3]; 291 __le32 request_identifier; /* sender context */ 292 __le32 reserved2; 293 u8 service_response; /* SCSI service response */ 294 u8 status; /* SCSI status */ 295 u8 datapres; /* [1:0] - data present, [7:2] - reserved */ 296 u8 sense_response_data_len; /* Sense/response data length */ 297 __le32 residual_count; /* Residual data length in bytes */ 298 /* Sense/response data */ 299 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX]; 300 }; 301 302 struct aac_native_hba { 303 union { 304 struct aac_hba_cmd_req cmd; 305 struct aac_hba_tm_req tmr; 306 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE]; 307 } cmd; 308 union { 309 struct aac_hba_resp err; 310 u8 resp_bytes[FW_ERROR_BUFFER_SIZE]; 311 } resp; 312 }; 313 314 #define CISS_REPORT_PHYSICAL_LUNS 0xc3 315 #define WRITE_HOST_WELLNESS 0xa5 316 #define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15 317 #define BMIC_IN 0x26 318 #define BMIC_OUT 0x27 319 320 struct aac_ciss_phys_luns_resp { 321 u8 list_length[4]; /* LUN list length (N-7, big endian) */ 322 u8 resp_flag; /* extended response_flag */ 323 u8 reserved[3]; 324 struct _ciss_lun { 325 u8 tid[3]; /* Target ID */ 326 u8 bus; /* Bus, flag (bits 6,7) */ 327 u8 level3[2]; 328 u8 level2[2]; 329 u8 node_ident[16]; /* phys. node identifier */ 330 } lun[1]; /* List of phys. devices */ 331 }; 332 333 /* 334 * Interrupts 335 */ 336 #define AAC_MAX_HRRQ 64 337 338 struct aac_ciss_identify_pd { 339 u8 scsi_bus; /* SCSI Bus number on controller */ 340 u8 scsi_id; /* SCSI ID on this bus */ 341 u16 block_size; /* sector size in bytes */ 342 u32 total_blocks; /* number for sectors on drive */ 343 u32 reserved_blocks; /* controller reserved (RIS) */ 344 u8 model[40]; /* Physical Drive Model */ 345 u8 serial_number[40]; /* Drive Serial Number */ 346 u8 firmware_revision[8]; /* drive firmware revision */ 347 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ 348 u8 compaq_drive_stamp; /* 0 means drive not stamped */ 349 u8 last_failure_reason; 350 351 u8 flags; 352 u8 more_flags; 353 u8 scsi_lun; /* SCSI LUN for phys drive */ 354 u8 yet_more_flags; 355 u8 even_more_flags; 356 u32 spi_speed_rules; /* SPI Speed :Ultra disable diagnose */ 357 u8 phys_connector[2]; /* connector number on controller */ 358 u8 phys_box_on_bus; /* phys enclosure this drive resides */ 359 u8 phys_bay_in_box; /* phys drv bay this drive resides */ 360 u32 rpm; /* Drive rotational speed in rpm */ 361 u8 device_type; /* type of drive */ 362 u8 sata_version; /* only valid when drive_type is SATA */ 363 u64 big_total_block_count; 364 u64 ris_starting_lba; 365 u32 ris_size; 366 u8 wwid[20]; 367 u8 controller_phy_map[32]; 368 u16 phy_count; 369 u8 phy_connected_dev_type[256]; 370 u8 phy_to_drive_bay_num[256]; 371 u16 phy_to_attached_dev_index[256]; 372 u8 box_index; 373 u8 spitfire_support; 374 u16 extra_physical_drive_flags; 375 u8 negotiated_link_rate[256]; 376 u8 phy_to_phy_map[256]; 377 u8 redundant_path_present_map; 378 u8 redundant_path_failure_map; 379 u8 active_path_number; 380 u16 alternate_paths_phys_connector[8]; 381 u8 alternate_paths_phys_box_on_port[8]; 382 u8 multi_lun_device_lun_count; 383 u8 minimum_good_fw_revision[8]; 384 u8 unique_inquiry_bytes[20]; 385 u8 current_temperature_degreesC; 386 u8 temperature_threshold_degreesC; 387 u8 max_temperature_degreesC; 388 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512 * 2^exp */ 389 u16 current_queue_depth_limit; 390 u8 switch_name[10]; 391 u16 switch_port; 392 u8 alternate_paths_switch_name[40]; 393 u8 alternate_paths_switch_port[8]; 394 u16 power_on_hours; /* valid only if gas gauge supported */ 395 u16 percent_endurance_used; /* valid only if gas gauge supported. */ 396 u8 drive_authentication; 397 u8 smart_carrier_authentication; 398 u8 smart_carrier_app_fw_version; 399 u8 smart_carrier_bootloader_fw_version; 400 u8 SanitizeSecureEraseSupport; 401 u8 DriveKeyFlags; 402 u8 encryption_key_name[64]; 403 u32 misc_drive_flags; 404 u16 dek_index; 405 u16 drive_encryption_flags; 406 u8 sanitize_maximum_time[6]; 407 u8 connector_info_mode; 408 u8 connector_info_number[4]; 409 u8 long_connector_name[64]; 410 u8 device_unique_identifier[16]; 411 u8 padto_2K[17]; 412 } __packed; 413 414 /* 415 * These macros convert from physical channels to virtual channels 416 */ 417 #define CONTAINER_CHANNEL (0) 418 #define NATIVE_CHANNEL (1) 419 #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL) 420 #define CONTAINER_TO_ID(cont) (cont) 421 #define CONTAINER_TO_LUN(cont) (0) 422 #define ENCLOSURE_CHANNEL (3) 423 424 #define PMC_DEVICE_S6 0x28b 425 #define PMC_DEVICE_S7 0x28c 426 #define PMC_DEVICE_S8 0x28d 427 428 #define aac_phys_to_logical(x) ((x)+1) 429 #define aac_logical_to_phys(x) ((x)?(x)-1:0) 430 431 /* 432 * These macros are for keeping track of 433 * character device state. 434 */ 435 #define AAC_CHARDEV_UNREGISTERED (-1) 436 #define AAC_CHARDEV_NEEDS_REINIT (-2) 437 438 /* #define AAC_DETAILED_STATUS_INFO */ 439 440 struct diskparm 441 { 442 int heads; 443 int sectors; 444 int cylinders; 445 }; 446 447 448 /* 449 * Firmware constants 450 */ 451 452 #define CT_NONE 0 453 #define CT_OK 218 454 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */ 455 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */ 456 457 /* 458 * Host side memory scatter gather list 459 * Used by the adapter for read, write, and readdirplus operations 460 * We have separate 32 and 64 bit version because even 461 * on 64 bit systems not all cards support the 64 bit version 462 */ 463 struct sgentry { 464 __le32 addr; /* 32-bit address. */ 465 __le32 count; /* Length. */ 466 }; 467 468 struct user_sgentry { 469 u32 addr; /* 32-bit address. */ 470 u32 count; /* Length. */ 471 }; 472 473 struct sgentry64 { 474 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 475 __le32 count; /* Length. */ 476 }; 477 478 struct user_sgentry64 { 479 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 480 u32 count; /* Length. */ 481 }; 482 483 struct sgentryraw { 484 __le32 next; /* reserved for F/W use */ 485 __le32 prev; /* reserved for F/W use */ 486 __le32 addr[2]; 487 __le32 count; 488 __le32 flags; /* reserved for F/W use */ 489 }; 490 491 struct user_sgentryraw { 492 u32 next; /* reserved for F/W use */ 493 u32 prev; /* reserved for F/W use */ 494 u32 addr[2]; 495 u32 count; 496 u32 flags; /* reserved for F/W use */ 497 }; 498 499 struct sge_ieee1212 { 500 u32 addrLow; 501 u32 addrHigh; 502 u32 length; 503 u32 flags; 504 }; 505 506 /* 507 * SGMAP 508 * 509 * This is the SGMAP structure for all commands that use 510 * 32-bit addressing. 511 */ 512 513 struct sgmap { 514 __le32 count; 515 struct sgentry sg[1]; 516 }; 517 518 struct user_sgmap { 519 u32 count; 520 struct user_sgentry sg[1]; 521 }; 522 523 struct sgmap64 { 524 __le32 count; 525 struct sgentry64 sg[1]; 526 }; 527 528 struct user_sgmap64 { 529 u32 count; 530 struct user_sgentry64 sg[1]; 531 }; 532 533 struct sgmapraw { 534 __le32 count; 535 struct sgentryraw sg[1]; 536 }; 537 538 struct user_sgmapraw { 539 u32 count; 540 struct user_sgentryraw sg[1]; 541 }; 542 543 struct creation_info 544 { 545 u8 buildnum; /* e.g., 588 */ 546 u8 usec; /* e.g., 588 */ 547 u8 via; /* e.g., 1 = FSU, 548 * 2 = API 549 */ 550 u8 year; /* e.g., 1997 = 97 */ 551 __le32 date; /* 552 * unsigned Month :4; // 1 - 12 553 * unsigned Day :6; // 1 - 32 554 * unsigned Hour :6; // 0 - 23 555 * unsigned Minute :6; // 0 - 60 556 * unsigned Second :6; // 0 - 60 557 */ 558 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */ 559 }; 560 561 562 /* 563 * Define all the constants needed for the communication interface 564 */ 565 566 /* 567 * Define how many queue entries each queue will have and the total 568 * number of entries for the entire communication interface. Also define 569 * how many queues we support. 570 * 571 * This has to match the controller 572 */ 573 574 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response 575 #define HOST_HIGH_CMD_ENTRIES 4 576 #define HOST_NORM_CMD_ENTRIES 8 577 #define ADAP_HIGH_CMD_ENTRIES 4 578 #define ADAP_NORM_CMD_ENTRIES 512 579 #define HOST_HIGH_RESP_ENTRIES 4 580 #define HOST_NORM_RESP_ENTRIES 512 581 #define ADAP_HIGH_RESP_ENTRIES 4 582 #define ADAP_NORM_RESP_ENTRIES 8 583 584 #define TOTAL_QUEUE_ENTRIES \ 585 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \ 586 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES) 587 588 589 /* 590 * Set the queues on a 16 byte alignment 591 */ 592 593 #define QUEUE_ALIGNMENT 16 594 595 /* 596 * The queue headers define the Communication Region queues. These 597 * are physically contiguous and accessible by both the adapter and the 598 * host. Even though all queue headers are in the same contiguous block 599 * they will be represented as individual units in the data structures. 600 */ 601 602 struct aac_entry { 603 __le32 size; /* Size in bytes of Fib which this QE points to */ 604 __le32 addr; /* Receiver address of the FIB */ 605 }; 606 607 /* 608 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped 609 * adjacently and in that order. 610 */ 611 612 struct aac_qhdr { 613 __le64 header_addr;/* Address to hand the adapter to access 614 to this queue head */ 615 __le32 *producer; /* The producer index for this queue (host address) */ 616 __le32 *consumer; /* The consumer index for this queue (host address) */ 617 }; 618 619 /* 620 * Define all the events which the adapter would like to notify 621 * the host of. 622 */ 623 624 #define HostNormCmdQue 1 /* Change in host normal priority command queue */ 625 #define HostHighCmdQue 2 /* Change in host high priority command queue */ 626 #define HostNormRespQue 3 /* Change in host normal priority response queue */ 627 #define HostHighRespQue 4 /* Change in host high priority response queue */ 628 #define AdapNormRespNotFull 5 629 #define AdapHighRespNotFull 6 630 #define AdapNormCmdNotFull 7 631 #define AdapHighCmdNotFull 8 632 #define SynchCommandComplete 9 633 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */ 634 635 /* 636 * Define all the events the host wishes to notify the 637 * adapter of. The first four values much match the Qid the 638 * corresponding queue. 639 */ 640 641 #define AdapNormCmdQue 2 642 #define AdapHighCmdQue 3 643 #define AdapNormRespQue 6 644 #define AdapHighRespQue 7 645 #define HostShutdown 8 646 #define HostPowerFail 9 647 #define FatalCommError 10 648 #define HostNormRespNotFull 11 649 #define HostHighRespNotFull 12 650 #define HostNormCmdNotFull 13 651 #define HostHighCmdNotFull 14 652 #define FastIo 15 653 #define AdapPrintfDone 16 654 655 /* 656 * Define all the queues that the adapter and host use to communicate 657 * Number them to match the physical queue layout. 658 */ 659 660 enum aac_queue_types { 661 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */ 662 HostHighCmdQueue, /* Adapter to host high priority command traffic */ 663 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */ 664 AdapHighCmdQueue, /* Host to adapter high priority command traffic */ 665 HostNormRespQueue, /* Adapter to host normal priority response traffic */ 666 HostHighRespQueue, /* Adapter to host high priority response traffic */ 667 AdapNormRespQueue, /* Host to adapter normal priority response traffic */ 668 AdapHighRespQueue /* Host to adapter high priority response traffic */ 669 }; 670 671 /* 672 * Assign type values to the FSA communication data structures 673 */ 674 675 #define FIB_MAGIC 0x0001 676 #define FIB_MAGIC2 0x0004 677 #define FIB_MAGIC2_64 0x0005 678 679 /* 680 * Define the priority levels the FSA communication routines support. 681 */ 682 683 #define FsaNormal 1 684 685 /* transport FIB header (PMC) */ 686 struct aac_fib_xporthdr { 687 __le64 HostAddress; /* FIB host address w/o xport header */ 688 __le32 Size; /* FIB size excluding xport header */ 689 __le32 Handle; /* driver handle to reference the FIB */ 690 __le64 Reserved[2]; 691 }; 692 693 #define ALIGN32 32 694 695 /* 696 * Define the FIB. The FIB is the where all the requested data and 697 * command information are put to the application on the FSA adapter. 698 */ 699 700 struct aac_fibhdr { 701 __le32 XferState; /* Current transfer state for this CCB */ 702 __le16 Command; /* Routing information for the destination */ 703 u8 StructType; /* Type FIB */ 704 u8 Unused; /* Unused */ 705 __le16 Size; /* Size of this FIB in bytes */ 706 __le16 SenderSize; /* Size of the FIB in the sender 707 (for response sizing) */ 708 __le32 SenderFibAddress; /* Host defined data in the FIB */ 709 union { 710 __le32 ReceiverFibAddress;/* Logical address of this FIB for 711 the adapter (old) */ 712 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */ 713 __le32 TimeStamp; /* otherwise timestamp for FW internal use */ 714 } u; 715 __le32 Handle; /* FIB handle used for MSGU commnunication */ 716 u32 Previous; /* FW internal use */ 717 u32 Next; /* FW internal use */ 718 }; 719 720 struct hw_fib { 721 struct aac_fibhdr header; 722 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data 723 }; 724 725 /* 726 * FIB commands 727 */ 728 729 #define TestCommandResponse 1 730 #define TestAdapterCommand 2 731 /* 732 * Lowlevel and comm commands 733 */ 734 #define LastTestCommand 100 735 #define ReinitHostNormCommandQueue 101 736 #define ReinitHostHighCommandQueue 102 737 #define ReinitHostHighRespQueue 103 738 #define ReinitHostNormRespQueue 104 739 #define ReinitAdapNormCommandQueue 105 740 #define ReinitAdapHighCommandQueue 107 741 #define ReinitAdapHighRespQueue 108 742 #define ReinitAdapNormRespQueue 109 743 #define InterfaceShutdown 110 744 #define DmaCommandFib 120 745 #define StartProfile 121 746 #define TermProfile 122 747 #define SpeedTest 123 748 #define TakeABreakPt 124 749 #define RequestPerfData 125 750 #define SetInterruptDefTimer 126 751 #define SetInterruptDefCount 127 752 #define GetInterruptDefStatus 128 753 #define LastCommCommand 129 754 /* 755 * Filesystem commands 756 */ 757 #define NuFileSystem 300 758 #define UFS 301 759 #define HostFileSystem 302 760 #define LastFileSystemCommand 303 761 /* 762 * Container Commands 763 */ 764 #define ContainerCommand 500 765 #define ContainerCommand64 501 766 #define ContainerRawIo 502 767 #define ContainerRawIo2 503 768 /* 769 * Scsi Port commands (scsi passthrough) 770 */ 771 #define ScsiPortCommand 600 772 #define ScsiPortCommand64 601 773 /* 774 * Misc house keeping and generic adapter initiated commands 775 */ 776 #define AifRequest 700 777 #define CheckRevision 701 778 #define FsaHostShutdown 702 779 #define RequestAdapterInfo 703 780 #define IsAdapterPaused 704 781 #define SendHostTime 705 782 #define RequestSupplementAdapterInfo 706 783 #define LastMiscCommand 707 784 785 /* 786 * Commands that will target the failover level on the FSA adapter 787 */ 788 789 enum fib_xfer_state { 790 HostOwned = (1<<0), 791 AdapterOwned = (1<<1), 792 FibInitialized = (1<<2), 793 FibEmpty = (1<<3), 794 AllocatedFromPool = (1<<4), 795 SentFromHost = (1<<5), 796 SentFromAdapter = (1<<6), 797 ResponseExpected = (1<<7), 798 NoResponseExpected = (1<<8), 799 AdapterProcessed = (1<<9), 800 HostProcessed = (1<<10), 801 HighPriority = (1<<11), 802 NormalPriority = (1<<12), 803 Async = (1<<13), 804 AsyncIo = (1<<13), // rpbfix: remove with new regime 805 PageFileIo = (1<<14), // rpbfix: remove with new regime 806 ShutdownRequest = (1<<15), 807 LazyWrite = (1<<16), // rpbfix: remove with new regime 808 AdapterMicroFib = (1<<17), 809 BIOSFibPath = (1<<18), 810 FastResponseCapable = (1<<19), 811 ApiFib = (1<<20), /* Its an API Fib */ 812 /* PMC NEW COMM: There is no more AIF data pending */ 813 NoMoreAifDataAvailable = (1<<21) 814 }; 815 816 /* 817 * The following defines needs to be updated any time there is an 818 * incompatible change made to the aac_init structure. 819 */ 820 821 #define ADAPTER_INIT_STRUCT_REVISION 3 822 #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science 823 #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */ 824 #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */ 825 #define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor 826 827 union aac_init 828 { 829 struct _r7 { 830 __le32 init_struct_revision; 831 __le32 no_of_msix_vectors; 832 __le32 fsrev; 833 __le32 comm_header_address; 834 __le32 fast_io_comm_area_address; 835 __le32 adapter_fibs_physical_address; 836 __le32 adapter_fibs_virtual_address; 837 __le32 adapter_fibs_size; 838 __le32 adapter_fib_align; 839 __le32 printfbuf; 840 __le32 printfbufsiz; 841 /* number of 4k pages of host phys. mem. */ 842 __le32 host_phys_mem_pages; 843 /* number of seconds since 1970. */ 844 __le32 host_elapsed_seconds; 845 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */ 846 __le32 init_flags; /* flags for supported features */ 847 #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001 848 #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010 849 #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020 850 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040 851 #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080 852 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100 853 #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400 854 __le32 max_io_commands; /* max outstanding commands */ 855 __le32 max_io_size; /* largest I/O command */ 856 __le32 max_fib_size; /* largest FIB to adapter */ 857 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */ 858 __le32 max_num_aif; /* max number of aif */ 859 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */ 860 /* Host RRQ (response queue) for SRC */ 861 __le32 host_rrq_addr_low; 862 __le32 host_rrq_addr_high; 863 } r7; 864 struct _r8 { 865 /* ADAPTER_INIT_STRUCT_REVISION_8 */ 866 __le32 init_struct_revision; 867 __le32 rr_queue_count; 868 __le32 host_elapsed_seconds; /* number of secs since 1970. */ 869 __le32 init_flags; 870 __le32 max_io_size; /* largest I/O command */ 871 __le32 max_num_aif; /* max number of aif */ 872 __le32 reserved1; 873 __le32 reserved2; 874 struct _rrq { 875 __le32 host_addr_low; 876 __le32 host_addr_high; 877 __le16 msix_id; 878 __le16 element_count; 879 __le16 comp_thresh; 880 __le16 unused; 881 } rrq[1]; /* up to 64 RRQ addresses */ 882 } r8; 883 }; 884 885 enum aac_log_level { 886 LOG_AAC_INIT = 10, 887 LOG_AAC_INFORMATIONAL = 20, 888 LOG_AAC_WARNING = 30, 889 LOG_AAC_LOW_ERROR = 40, 890 LOG_AAC_MEDIUM_ERROR = 50, 891 LOG_AAC_HIGH_ERROR = 60, 892 LOG_AAC_PANIC = 70, 893 LOG_AAC_DEBUG = 80, 894 LOG_AAC_WINDBG_PRINT = 90 895 }; 896 897 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b 898 #define FSAFS_NTC_FIB_CONTEXT 0x030c 899 900 struct aac_dev; 901 struct fib; 902 struct scsi_cmnd; 903 904 struct adapter_ops 905 { 906 /* Low level operations */ 907 void (*adapter_interrupt)(struct aac_dev *dev); 908 void (*adapter_notify)(struct aac_dev *dev, u32 event); 909 void (*adapter_disable_int)(struct aac_dev *dev); 910 void (*adapter_enable_int)(struct aac_dev *dev); 911 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4); 912 int (*adapter_check_health)(struct aac_dev *dev); 913 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type); 914 void (*adapter_start)(struct aac_dev *dev); 915 /* Transport operations */ 916 int (*adapter_ioremap)(struct aac_dev * dev, u32 size); 917 irq_handler_t adapter_intr; 918 /* Packet operations */ 919 int (*adapter_deliver)(struct fib * fib); 920 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba); 921 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count); 922 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua); 923 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd); 924 /* Administrative operations */ 925 int (*adapter_comm)(struct aac_dev * dev, int comm); 926 }; 927 928 /* 929 * Define which interrupt handler needs to be installed 930 */ 931 932 struct aac_driver_ident 933 { 934 int (*init)(struct aac_dev *dev); 935 char * name; 936 char * vname; 937 char * model; 938 u16 channels; 939 int quirks; 940 }; 941 /* 942 * Some adapter firmware needs communication memory 943 * below 2gig. This tells the init function to set the 944 * dma mask such that fib memory will be allocated where the 945 * adapter firmware can get to it. 946 */ 947 #define AAC_QUIRK_31BIT 0x0001 948 949 /* 950 * Some adapter firmware, when the raid card's cache is turned off, can not 951 * split up scatter gathers in order to deal with the limits of the 952 * underlying CHIM. This limit is 34 scatter gather elements. 953 */ 954 #define AAC_QUIRK_34SG 0x0002 955 956 /* 957 * This adapter is a slave (no Firmware) 958 */ 959 #define AAC_QUIRK_SLAVE 0x0004 960 961 /* 962 * This adapter is a master. 963 */ 964 #define AAC_QUIRK_MASTER 0x0008 965 966 /* 967 * Some adapter firmware perform poorly when it must split up scatter gathers 968 * in order to deal with the limits of the underlying CHIM. This limit in this 969 * class of adapters is 17 scatter gather elements. 970 */ 971 #define AAC_QUIRK_17SG 0x0010 972 973 /* 974 * Some adapter firmware does not support 64 bit scsi passthrough 975 * commands. 976 */ 977 #define AAC_QUIRK_SCSI_32 0x0020 978 979 /* 980 * SRC based adapters support the AifReqEvent functions 981 */ 982 #define AAC_QUIRK_SRC 0x0040 983 984 /* 985 * The adapter interface specs all queues to be located in the same 986 * physically contiguous block. The host structure that defines the 987 * commuication queues will assume they are each a separate physically 988 * contiguous memory region that will support them all being one big 989 * contiguous block. 990 * There is a command and response queue for each level and direction of 991 * commuication. These regions are accessed by both the host and adapter. 992 */ 993 994 struct aac_queue { 995 u64 logical; /*address we give the adapter */ 996 struct aac_entry *base; /*system virtual address */ 997 struct aac_qhdr headers; /*producer,consumer q headers*/ 998 u32 entries; /*Number of queue entries */ 999 wait_queue_head_t qfull; /*Event to wait on if q full */ 1000 wait_queue_head_t cmdready; /*Cmd ready from the adapter */ 1001 /* This is only valid for adapter to host command queues. */ 1002 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */ 1003 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */ 1004 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */ 1005 /* only valid for command queues which receive entries from the adapter. */ 1006 /* Number of entries on outstanding queue. */ 1007 atomic_t numpending; 1008 struct aac_dev * dev; /* Back pointer to adapter structure */ 1009 }; 1010 1011 /* 1012 * Message queues. The order here is important, see also the 1013 * queue type ordering 1014 */ 1015 1016 struct aac_queue_block 1017 { 1018 struct aac_queue queue[8]; 1019 }; 1020 1021 /* 1022 * SaP1 Message Unit Registers 1023 */ 1024 1025 struct sa_drawbridge_CSR { 1026 /* Offset | Name */ 1027 __le32 reserved[10]; /* 00h-27h | Reserved */ 1028 u8 LUT_Offset; /* 28h | Lookup Table Offset */ 1029 u8 reserved1[3]; /* 29h-2bh | Reserved */ 1030 __le32 LUT_Data; /* 2ch | Looup Table Data */ 1031 __le32 reserved2[26]; /* 30h-97h | Reserved */ 1032 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */ 1033 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */ 1034 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */ 1035 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */ 1036 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */ 1037 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */ 1038 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */ 1039 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */ 1040 __le32 MAILBOX0; /* a8h | Scratchpad 0 */ 1041 __le32 MAILBOX1; /* ach | Scratchpad 1 */ 1042 __le32 MAILBOX2; /* b0h | Scratchpad 2 */ 1043 __le32 MAILBOX3; /* b4h | Scratchpad 3 */ 1044 __le32 MAILBOX4; /* b8h | Scratchpad 4 */ 1045 __le32 MAILBOX5; /* bch | Scratchpad 5 */ 1046 __le32 MAILBOX6; /* c0h | Scratchpad 6 */ 1047 __le32 MAILBOX7; /* c4h | Scratchpad 7 */ 1048 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */ 1049 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */ 1050 __le32 reserved3[12]; /* d0h-ffh | reserved */ 1051 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */ 1052 }; 1053 1054 #define Mailbox0 SaDbCSR.MAILBOX0 1055 #define Mailbox1 SaDbCSR.MAILBOX1 1056 #define Mailbox2 SaDbCSR.MAILBOX2 1057 #define Mailbox3 SaDbCSR.MAILBOX3 1058 #define Mailbox4 SaDbCSR.MAILBOX4 1059 #define Mailbox5 SaDbCSR.MAILBOX5 1060 #define Mailbox6 SaDbCSR.MAILBOX6 1061 #define Mailbox7 SaDbCSR.MAILBOX7 1062 1063 #define DoorbellReg_p SaDbCSR.PRISETIRQ 1064 #define DoorbellReg_s SaDbCSR.SECSETIRQ 1065 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ 1066 1067 1068 #define DOORBELL_0 0x0001 1069 #define DOORBELL_1 0x0002 1070 #define DOORBELL_2 0x0004 1071 #define DOORBELL_3 0x0008 1072 #define DOORBELL_4 0x0010 1073 #define DOORBELL_5 0x0020 1074 #define DOORBELL_6 0x0040 1075 1076 1077 #define PrintfReady DOORBELL_5 1078 #define PrintfDone DOORBELL_5 1079 1080 struct sa_registers { 1081 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */ 1082 }; 1083 1084 1085 #define SA_INIT_NUM_MSIXVECTORS 1 1086 #define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS 1087 1088 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 1089 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 1090 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) 1091 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) 1092 1093 /* 1094 * Rx Message Unit Registers 1095 */ 1096 1097 struct rx_mu_registers { 1098 /* Local | PCI*| Name */ 1099 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */ 1100 __le32 reserved0; /* 1304h | 04h | Reserved */ 1101 __le32 AWR; /* 1308h | 08h | APIC Window Register */ 1102 __le32 reserved1; /* 130Ch | 0Ch | Reserved */ 1103 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */ 1104 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */ 1105 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */ 1106 __le32 IISR; /* 1324h | 24h | Inbound Interrupt 1107 Status Register */ 1108 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt 1109 Mask Register */ 1110 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */ 1111 __le32 OISR; /* 1330h | 30h | Outbound Interrupt 1112 Status Register */ 1113 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt 1114 Mask Register */ 1115 __le32 reserved2; /* 1338h | 38h | Reserved */ 1116 __le32 reserved3; /* 133Ch | 3Ch | Reserved */ 1117 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */ 1118 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */ 1119 /* * Must access through ATU Inbound 1120 Translation Window */ 1121 }; 1122 1123 struct rx_inbound { 1124 __le32 Mailbox[8]; 1125 }; 1126 1127 #define INBOUNDDOORBELL_0 0x00000001 1128 #define INBOUNDDOORBELL_1 0x00000002 1129 #define INBOUNDDOORBELL_2 0x00000004 1130 #define INBOUNDDOORBELL_3 0x00000008 1131 #define INBOUNDDOORBELL_4 0x00000010 1132 #define INBOUNDDOORBELL_5 0x00000020 1133 #define INBOUNDDOORBELL_6 0x00000040 1134 1135 #define OUTBOUNDDOORBELL_0 0x00000001 1136 #define OUTBOUNDDOORBELL_1 0x00000002 1137 #define OUTBOUNDDOORBELL_2 0x00000004 1138 #define OUTBOUNDDOORBELL_3 0x00000008 1139 #define OUTBOUNDDOORBELL_4 0x00000010 1140 1141 #define InboundDoorbellReg MUnit.IDR 1142 #define OutboundDoorbellReg MUnit.ODR 1143 1144 struct rx_registers { 1145 struct rx_mu_registers MUnit; /* 1300h - 1347h */ 1146 __le32 reserved1[2]; /* 1348h - 134ch */ 1147 struct rx_inbound IndexRegs; 1148 }; 1149 1150 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) 1151 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) 1152 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) 1153 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) 1154 1155 /* 1156 * Rkt Message Unit Registers (same as Rx, except a larger reserve region) 1157 */ 1158 1159 #define rkt_mu_registers rx_mu_registers 1160 #define rkt_inbound rx_inbound 1161 1162 struct rkt_registers { 1163 struct rkt_mu_registers MUnit; /* 1300h - 1347h */ 1164 __le32 reserved1[1006]; /* 1348h - 22fch */ 1165 struct rkt_inbound IndexRegs; /* 2300h - */ 1166 }; 1167 1168 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) 1169 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) 1170 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR)) 1171 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR)) 1172 1173 /* 1174 * PMC SRC message unit registers 1175 */ 1176 1177 #define src_inbound rx_inbound 1178 1179 struct src_mu_registers { 1180 /* PCI*| Name */ 1181 __le32 reserved0[6]; /* 00h | Reserved */ 1182 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */ 1183 __le32 IDR; /* 20h | Inbound Doorbell Register */ 1184 __le32 IISR; /* 24h | Inbound Int. Status Register */ 1185 __le32 reserved1[3]; /* 28h | Reserved */ 1186 __le32 OIMR; /* 34h | Outbound Int. Mask Register */ 1187 __le32 reserved2[25]; /* 38h | Reserved */ 1188 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */ 1189 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */ 1190 __le32 reserved3[3]; /* a4h | Reserved */ 1191 __le32 SCR0; /* b0h | Scratchpad 0 */ 1192 __le32 reserved4[2]; /* b4h | Reserved */ 1193 __le32 OMR; /* bch | Outbound Message Register */ 1194 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */ 1195 __le32 IQ_H; /* c4h | Inbound Queue (High address) */ 1196 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */ 1197 __le32 reserved5; /* cch | Reserved */ 1198 __le32 IQN_L; /* d0h | Inbound (native cmd) low */ 1199 __le32 IQN_H; /* d4h | Inbound (native cmd) high */ 1200 }; 1201 1202 struct src_registers { 1203 struct src_mu_registers MUnit; /* 00h - cbh */ 1204 union { 1205 struct { 1206 __le32 reserved1[130786]; /* d8h - 7fc5fh */ 1207 struct src_inbound IndexRegs; /* 7fc60h */ 1208 } tupelo; 1209 struct { 1210 __le32 reserved1[970]; /* d8h - fffh */ 1211 struct src_inbound IndexRegs; /* 1000h */ 1212 } denali; 1213 } u; 1214 }; 1215 1216 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR)) 1217 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR)) 1218 #define src_writeb(AEP, CSR, value) writeb(value, \ 1219 &((AEP)->regs.src.bar0->CSR)) 1220 #define src_writel(AEP, CSR, value) writel(value, \ 1221 &((AEP)->regs.src.bar0->CSR)) 1222 #if defined(writeq) 1223 #define src_writeq(AEP, CSR, value) writeq(value, \ 1224 &((AEP)->regs.src.bar0->CSR)) 1225 #endif 1226 1227 #define SRC_ODR_SHIFT 12 1228 #define SRC_IDR_SHIFT 9 1229 1230 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx); 1231 1232 struct aac_fib_context { 1233 s16 type; // used for verification of structure 1234 s16 size; 1235 u32 unique; // unique value representing this context 1236 ulong jiffies; // used for cleanup - dmb changed to ulong 1237 struct list_head next; // used to link context's into a linked list 1238 struct semaphore wait_sem; // this is used to wait for the next fib to arrive. 1239 int wait; // Set to true when thread is in WaitForSingleObject 1240 unsigned long count; // total number of FIBs on FibList 1241 struct list_head fib_list; // this holds fibs and their attachd hw_fibs 1242 }; 1243 1244 struct sense_data { 1245 u8 error_code; /* 70h (current errors), 71h(deferred errors) */ 1246 u8 valid:1; /* A valid bit of one indicates that the information */ 1247 /* field contains valid information as defined in the 1248 * SCSI-2 Standard. 1249 */ 1250 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */ 1251 u8 sense_key:4; /* Sense Key */ 1252 u8 reserved:1; 1253 u8 ILI:1; /* Incorrect Length Indicator */ 1254 u8 EOM:1; /* End Of Medium - reserved for random access devices */ 1255 u8 filemark:1; /* Filemark - reserved for random access devices */ 1256 1257 u8 information[4]; /* for direct-access devices, contains the unsigned 1258 * logical block address or residue associated with 1259 * the sense key 1260 */ 1261 u8 add_sense_len; /* number of additional sense bytes to follow this field */ 1262 u8 cmnd_info[4]; /* not used */ 1263 u8 ASC; /* Additional Sense Code */ 1264 u8 ASCQ; /* Additional Sense Code Qualifier */ 1265 u8 FRUC; /* Field Replaceable Unit Code - not used */ 1266 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data 1267 * was in error 1268 */ 1269 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that 1270 * the bit_ptr field has valid value 1271 */ 1272 u8 reserved2:2; 1273 u8 CD:1; /* command data bit: 1- illegal parameter in CDB. 1274 * 0- illegal parameter in data. 1275 */ 1276 u8 SKSV:1; 1277 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */ 1278 }; 1279 1280 struct fsa_dev_info { 1281 u64 last; 1282 u64 size; 1283 u32 type; 1284 u32 config_waiting_on; 1285 unsigned long config_waiting_stamp; 1286 u16 queue_depth; 1287 u8 config_needed; 1288 u8 valid; 1289 u8 ro; 1290 u8 locked; 1291 u8 deleted; 1292 char devname[8]; 1293 struct sense_data sense_data; 1294 u32 block_size; 1295 u8 identifier[16]; 1296 }; 1297 1298 struct fib { 1299 void *next; /* this is used by the allocator */ 1300 s16 type; 1301 s16 size; 1302 /* 1303 * The Adapter that this I/O is destined for. 1304 */ 1305 struct aac_dev *dev; 1306 /* 1307 * This is the event the sendfib routine will wait on if the 1308 * caller did not pass one and this is synch io. 1309 */ 1310 struct semaphore event_wait; 1311 spinlock_t event_lock; 1312 1313 u32 done; /* gets set to 1 when fib is complete */ 1314 fib_callback callback; 1315 void *callback_data; 1316 u32 flags; // u32 dmb was ulong 1317 /* 1318 * And for the internal issue/reply queues (we may be able 1319 * to merge these two) 1320 */ 1321 struct list_head fiblink; 1322 void *data; 1323 u32 vector_no; 1324 struct hw_fib *hw_fib_va; /* also used for native */ 1325 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/ 1326 dma_addr_t hw_sgl_pa; /* extra sgl for native */ 1327 dma_addr_t hw_error_pa; /* error buffer for native */ 1328 u32 hbacmd_size; /* cmd size for native */ 1329 }; 1330 1331 #define AAC_INIT 0 1332 #define AAC_RESCAN 1 1333 1334 #define AAC_DEVTYPE_RAID_MEMBER 1 1335 #define AAC_DEVTYPE_ARC_RAW 2 1336 #define AAC_DEVTYPE_NATIVE_RAW 3 1337 #define AAC_EXPOSE_DISK 0 1338 #define AAC_HIDE_DISK 3 1339 1340 struct aac_hba_map_info { 1341 __le32 rmw_nexus; /* nexus for native HBA devices */ 1342 u8 devtype; /* device type */ 1343 u8 new_devtype; 1344 u8 reset_state; /* 0 - no reset, 1..x - */ 1345 /* after xth TM LUN reset */ 1346 u16 qd_limit; 1347 u8 expose; /*checks if to expose or not*/ 1348 }; 1349 1350 /* 1351 * Adapter Information Block 1352 * 1353 * This is returned by the RequestAdapterInfo block 1354 */ 1355 1356 struct aac_adapter_info 1357 { 1358 __le32 platform; 1359 __le32 cpu; 1360 __le32 subcpu; 1361 __le32 clock; 1362 __le32 execmem; 1363 __le32 buffermem; 1364 __le32 totalmem; 1365 __le32 kernelrev; 1366 __le32 kernelbuild; 1367 __le32 monitorrev; 1368 __le32 monitorbuild; 1369 __le32 hwrev; 1370 __le32 hwbuild; 1371 __le32 biosrev; 1372 __le32 biosbuild; 1373 __le32 cluster; 1374 __le32 clusterchannelmask; 1375 __le32 serial[2]; 1376 __le32 battery; 1377 __le32 options; 1378 __le32 OEM; 1379 }; 1380 1381 struct aac_supplement_adapter_info 1382 { 1383 u8 adapter_type_text[17+1]; 1384 u8 pad[2]; 1385 __le32 flash_memory_byte_size; 1386 __le32 flash_image_id; 1387 __le32 max_number_ports; 1388 __le32 version; 1389 __le32 feature_bits; 1390 u8 slot_number; 1391 u8 reserved_pad0[3]; 1392 u8 build_date[12]; 1393 __le32 current_number_ports; 1394 struct { 1395 u8 assembly_pn[8]; 1396 u8 fru_pn[8]; 1397 u8 battery_fru_pn[8]; 1398 u8 ec_version_string[8]; 1399 u8 tsid[12]; 1400 } vpd_info; 1401 __le32 flash_firmware_revision; 1402 __le32 flash_firmware_build; 1403 __le32 raid_type_morph_options; 1404 __le32 flash_firmware_boot_revision; 1405 __le32 flash_firmware_boot_build; 1406 u8 mfg_pcba_serial_no[12]; 1407 u8 mfg_wwn_name[8]; 1408 __le32 supported_options2; 1409 __le32 struct_expansion; 1410 /* StructExpansion == 1 */ 1411 __le32 feature_bits3; 1412 __le32 supported_performance_modes; 1413 u8 host_bus_type; /* uses HOST_BUS_TYPE_xxx defines */ 1414 u8 host_bus_width; /* actual width in bits or links */ 1415 u16 host_bus_speed; /* actual bus speed/link rate in MHz */ 1416 u8 max_rrc_drives; /* max. number of ITP-RRC drives/pool */ 1417 u8 max_disk_xtasks; /* max. possible num of DiskX Tasks */ 1418 1419 u8 cpld_ver_loaded; 1420 u8 cpld_ver_in_flash; 1421 1422 __le64 max_rrc_capacity; 1423 __le32 compiled_max_hist_log_level; 1424 u8 custom_board_name[12]; 1425 u16 supported_cntlr_mode; /* identify supported controller mode */ 1426 u16 reserved_for_future16; 1427 __le32 supported_options3; /* reserved for future options */ 1428 1429 __le16 virt_device_bus; /* virt. SCSI device for Thor */ 1430 __le16 virt_device_target; 1431 __le16 virt_device_lun; 1432 __le16 unused; 1433 __le32 reserved_for_future_growth[68]; 1434 1435 }; 1436 #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010) 1437 #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000) 1438 /* SupportedOptions2 */ 1439 #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001) 1440 #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002) 1441 #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004) 1442 #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000) 1443 /* 4KB sector size */ 1444 #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000) 1445 /* 240 simple volume support */ 1446 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000) 1447 /* 1448 * Supports FIB dump sync command send prior to IOP_RESET 1449 */ 1450 #define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000) 1451 #define AAC_SIS_VERSION_V3 3 1452 #define AAC_SIS_SLOT_UNKNOWN 0xFF 1453 1454 #define GetBusInfo 0x00000009 1455 struct aac_bus_info { 1456 __le32 Command; /* VM_Ioctl */ 1457 __le32 ObjType; /* FT_DRIVE */ 1458 __le32 MethodId; /* 1 = SCSI Layer */ 1459 __le32 ObjectId; /* Handle */ 1460 __le32 CtlCmd; /* GetBusInfo */ 1461 }; 1462 1463 struct aac_bus_info_response { 1464 __le32 Status; /* ST_OK */ 1465 __le32 ObjType; 1466 __le32 MethodId; /* unused */ 1467 __le32 ObjectId; /* unused */ 1468 __le32 CtlCmd; /* unused */ 1469 __le32 ProbeComplete; 1470 __le32 BusCount; 1471 __le32 TargetsPerBus; 1472 u8 InitiatorBusId[10]; 1473 u8 BusValid[10]; 1474 }; 1475 1476 /* 1477 * Battery platforms 1478 */ 1479 #define AAC_BAT_REQ_PRESENT (1) 1480 #define AAC_BAT_REQ_NOTPRESENT (2) 1481 #define AAC_BAT_OPT_PRESENT (3) 1482 #define AAC_BAT_OPT_NOTPRESENT (4) 1483 #define AAC_BAT_NOT_SUPPORTED (5) 1484 /* 1485 * cpu types 1486 */ 1487 #define AAC_CPU_SIMULATOR (1) 1488 #define AAC_CPU_I960 (2) 1489 #define AAC_CPU_STRONGARM (3) 1490 1491 /* 1492 * Supported Options 1493 */ 1494 #define AAC_OPT_SNAPSHOT cpu_to_le32(1) 1495 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1) 1496 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2) 1497 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3) 1498 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4) 1499 #define AAC_OPT_RAID50 cpu_to_le32(1<<5) 1500 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6) 1501 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7) 1502 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8) 1503 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9) 1504 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10) 1505 #define AAC_OPT_ALARM cpu_to_le32(1<<11) 1506 #define AAC_OPT_NONDASD cpu_to_le32(1<<12) 1507 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13) 1508 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14) 1509 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16) 1510 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17) 1511 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18) 1512 #define AAC_OPT_EXTENDED cpu_to_le32(1<<23) 1513 #define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25) 1514 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28) 1515 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29) 1516 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30) 1517 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31) 1518 1519 #define AAC_COMM_PRODUCER 0 1520 #define AAC_COMM_MESSAGE 1 1521 #define AAC_COMM_MESSAGE_TYPE1 3 1522 #define AAC_COMM_MESSAGE_TYPE2 4 1523 #define AAC_COMM_MESSAGE_TYPE3 5 1524 1525 #define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1) 1526 1527 /* MSIX context */ 1528 struct aac_msix_ctx { 1529 int vector_no; 1530 struct aac_dev *dev; 1531 }; 1532 1533 struct aac_dev 1534 { 1535 struct list_head entry; 1536 const char *name; 1537 int id; 1538 1539 /* 1540 * negotiated FIB settings 1541 */ 1542 unsigned int max_fib_size; 1543 unsigned int sg_tablesize; 1544 unsigned int max_num_aif; 1545 1546 unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */ 1547 1548 /* 1549 * Map for 128 fib objects (64k) 1550 */ 1551 dma_addr_t hw_fib_pa; /* also used for native cmd */ 1552 struct hw_fib *hw_fib_va; /* also used for native cmd */ 1553 struct hw_fib *aif_base_va; 1554 /* 1555 * Fib Headers 1556 */ 1557 struct fib *fibs; 1558 1559 struct fib *free_fib; 1560 spinlock_t fib_lock; 1561 1562 struct mutex ioctl_mutex; 1563 struct aac_queue_block *queues; 1564 /* 1565 * The user API will use an IOCTL to register itself to receive 1566 * FIBs from the adapter. The following list is used to keep 1567 * track of all the threads that have requested these FIBs. The 1568 * mutex is used to synchronize access to all data associated 1569 * with the adapter fibs. 1570 */ 1571 struct list_head fib_list; 1572 1573 struct adapter_ops a_ops; 1574 unsigned long fsrev; /* Main driver's revision number */ 1575 1576 resource_size_t base_start; /* main IO base */ 1577 resource_size_t dbg_base; /* address of UART 1578 * debug buffer */ 1579 1580 resource_size_t base_size, dbg_size; /* Size of 1581 * mapped in region */ 1582 /* 1583 * Holds initialization info 1584 * to communicate with adapter 1585 */ 1586 union aac_init *init; 1587 dma_addr_t init_pa; /* Holds physical address of the init struct */ 1588 /* response queue (if AAC_COMM_MESSAGE_TYPE1) */ 1589 __le32 *host_rrq; 1590 dma_addr_t host_rrq_pa; /* phys. address */ 1591 /* index into rrq buffer */ 1592 u32 host_rrq_idx[AAC_MAX_MSIX]; 1593 atomic_t rrq_outstanding[AAC_MAX_MSIX]; 1594 u32 fibs_pushed_no; 1595 struct pci_dev *pdev; /* Our PCI interface */ 1596 /* pointer to buffer used for printf's from the adapter */ 1597 void *printfbuf; 1598 void *comm_addr; /* Base address of Comm area */ 1599 dma_addr_t comm_phys; /* Physical Address of Comm area */ 1600 size_t comm_size; 1601 1602 struct Scsi_Host *scsi_host_ptr; 1603 int maximum_num_containers; 1604 int maximum_num_physicals; 1605 int maximum_num_channels; 1606 struct fsa_dev_info *fsa_dev; 1607 struct task_struct *thread; 1608 int cardtype; 1609 /* 1610 *This lock will protect the two 32-bit 1611 *writes to the Inbound Queue 1612 */ 1613 spinlock_t iq_lock; 1614 1615 /* 1616 * The following is the device specific extension. 1617 */ 1618 #ifndef AAC_MIN_FOOTPRINT_SIZE 1619 # define AAC_MIN_FOOTPRINT_SIZE 8192 1620 # define AAC_MIN_SRC_BAR0_SIZE 0x400000 1621 # define AAC_MIN_SRC_BAR1_SIZE 0x800 1622 # define AAC_MIN_SRCV_BAR0_SIZE 0x100000 1623 # define AAC_MIN_SRCV_BAR1_SIZE 0x400 1624 #endif 1625 union 1626 { 1627 struct sa_registers __iomem *sa; 1628 struct rx_registers __iomem *rx; 1629 struct rkt_registers __iomem *rkt; 1630 struct { 1631 struct src_registers __iomem *bar0; 1632 char __iomem *bar1; 1633 } src; 1634 } regs; 1635 volatile void __iomem *base, *dbg_base_mapped; 1636 volatile struct rx_inbound __iomem *IndexRegs; 1637 u32 OIMR; /* Mask Register Cache */ 1638 /* 1639 * AIF thread states 1640 */ 1641 u32 aif_thread; 1642 struct aac_adapter_info adapter_info; 1643 struct aac_supplement_adapter_info supplement_adapter_info; 1644 /* These are in adapter info but they are in the io flow so 1645 * lets break them out so we don't have to do an AND to check them 1646 */ 1647 u8 nondasd_support; 1648 u8 jbod; 1649 u8 cache_protected; 1650 u8 dac_support; 1651 u8 needs_dac; 1652 u8 raid_scsi_mode; 1653 u8 comm_interface; 1654 u8 raw_io_interface; 1655 u8 raw_io_64; 1656 u8 printf_enabled; 1657 u8 in_reset; 1658 u8 msi; 1659 u8 sa_firmware; 1660 int management_fib_count; 1661 spinlock_t manage_lock; 1662 spinlock_t sync_lock; 1663 int sync_mode; 1664 struct fib *sync_fib; 1665 struct list_head sync_fib_list; 1666 u32 doorbell_mask; 1667 u32 max_msix; /* max. MSI-X vectors */ 1668 u32 vector_cap; /* MSI-X vector capab.*/ 1669 int msi_enabled; /* MSI/MSI-X enabled */ 1670 atomic_t msix_counter; 1671 struct msix_entry msixentry[AAC_MAX_MSIX]; 1672 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */ 1673 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS]; 1674 u8 adapter_shutdown; 1675 u32 handle_pci_error; 1676 }; 1677 1678 #define aac_adapter_interrupt(dev) \ 1679 (dev)->a_ops.adapter_interrupt(dev) 1680 1681 #define aac_adapter_notify(dev, event) \ 1682 (dev)->a_ops.adapter_notify(dev, event) 1683 1684 #define aac_adapter_disable_int(dev) \ 1685 (dev)->a_ops.adapter_disable_int(dev) 1686 1687 #define aac_adapter_enable_int(dev) \ 1688 (dev)->a_ops.adapter_enable_int(dev) 1689 1690 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \ 1691 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) 1692 1693 #define aac_adapter_restart(dev, bled, reset_type) \ 1694 ((dev)->a_ops.adapter_restart(dev, bled, reset_type)) 1695 1696 #define aac_adapter_start(dev) \ 1697 ((dev)->a_ops.adapter_start(dev)) 1698 1699 #define aac_adapter_ioremap(dev, size) \ 1700 (dev)->a_ops.adapter_ioremap(dev, size) 1701 1702 #define aac_adapter_deliver(fib) \ 1703 ((fib)->dev)->a_ops.adapter_deliver(fib) 1704 1705 #define aac_adapter_bounds(dev,cmd,lba) \ 1706 dev->a_ops.adapter_bounds(dev,cmd,lba) 1707 1708 #define aac_adapter_read(fib,cmd,lba,count) \ 1709 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count) 1710 1711 #define aac_adapter_write(fib,cmd,lba,count,fua) \ 1712 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua) 1713 1714 #define aac_adapter_scsi(fib,cmd) \ 1715 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd) 1716 1717 #define aac_adapter_comm(dev,comm) \ 1718 (dev)->a_ops.adapter_comm(dev, comm) 1719 1720 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001) 1721 #define FIB_CONTEXT_FLAG (0x00000002) 1722 #define FIB_CONTEXT_FLAG_WAIT (0x00000004) 1723 #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008) 1724 #define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010) 1725 #define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020) 1726 1727 /* 1728 * Define the command values 1729 */ 1730 1731 #define Null 0 1732 #define GetAttributes 1 1733 #define SetAttributes 2 1734 #define Lookup 3 1735 #define ReadLink 4 1736 #define Read 5 1737 #define Write 6 1738 #define Create 7 1739 #define MakeDirectory 8 1740 #define SymbolicLink 9 1741 #define MakeNode 10 1742 #define Removex 11 1743 #define RemoveDirectoryx 12 1744 #define Rename 13 1745 #define Link 14 1746 #define ReadDirectory 15 1747 #define ReadDirectoryPlus 16 1748 #define FileSystemStatus 17 1749 #define FileSystemInfo 18 1750 #define PathConfigure 19 1751 #define Commit 20 1752 #define Mount 21 1753 #define UnMount 22 1754 #define Newfs 23 1755 #define FsCheck 24 1756 #define FsSync 25 1757 #define SimReadWrite 26 1758 #define SetFileSystemStatus 27 1759 #define BlockRead 28 1760 #define BlockWrite 29 1761 #define NvramIoctl 30 1762 #define FsSyncWait 31 1763 #define ClearArchiveBit 32 1764 #define SetAcl 33 1765 #define GetAcl 34 1766 #define AssignAcl 35 1767 #define FaultInsertion 36 /* Fault Insertion Command */ 1768 #define CrazyCache 37 /* Crazycache */ 1769 1770 #define MAX_FSACOMMAND_NUM 38 1771 1772 1773 /* 1774 * Define the status returns. These are very unixlike although 1775 * most are not in fact used 1776 */ 1777 1778 #define ST_OK 0 1779 #define ST_PERM 1 1780 #define ST_NOENT 2 1781 #define ST_IO 5 1782 #define ST_NXIO 6 1783 #define ST_E2BIG 7 1784 #define ST_MEDERR 8 1785 #define ST_ACCES 13 1786 #define ST_EXIST 17 1787 #define ST_XDEV 18 1788 #define ST_NODEV 19 1789 #define ST_NOTDIR 20 1790 #define ST_ISDIR 21 1791 #define ST_INVAL 22 1792 #define ST_FBIG 27 1793 #define ST_NOSPC 28 1794 #define ST_ROFS 30 1795 #define ST_MLINK 31 1796 #define ST_WOULDBLOCK 35 1797 #define ST_NAMETOOLONG 63 1798 #define ST_NOTEMPTY 66 1799 #define ST_DQUOT 69 1800 #define ST_STALE 70 1801 #define ST_REMOTE 71 1802 #define ST_NOT_READY 72 1803 #define ST_BADHANDLE 10001 1804 #define ST_NOT_SYNC 10002 1805 #define ST_BAD_COOKIE 10003 1806 #define ST_NOTSUPP 10004 1807 #define ST_TOOSMALL 10005 1808 #define ST_SERVERFAULT 10006 1809 #define ST_BADTYPE 10007 1810 #define ST_JUKEBOX 10008 1811 #define ST_NOTMOUNTED 10009 1812 #define ST_MAINTMODE 10010 1813 #define ST_STALEACL 10011 1814 1815 /* 1816 * On writes how does the client want the data written. 1817 */ 1818 1819 #define CACHE_CSTABLE 1 1820 #define CACHE_UNSTABLE 2 1821 1822 /* 1823 * Lets the client know at which level the data was committed on 1824 * a write request 1825 */ 1826 1827 #define CMFILE_SYNCH_NVRAM 1 1828 #define CMDATA_SYNCH_NVRAM 2 1829 #define CMFILE_SYNCH 3 1830 #define CMDATA_SYNCH 4 1831 #define CMUNSTABLE 5 1832 1833 #define RIO_TYPE_WRITE 0x0000 1834 #define RIO_TYPE_READ 0x0001 1835 #define RIO_SUREWRITE 0x0008 1836 1837 #define RIO2_IO_TYPE 0x0003 1838 #define RIO2_IO_TYPE_WRITE 0x0000 1839 #define RIO2_IO_TYPE_READ 0x0001 1840 #define RIO2_IO_TYPE_VERIFY 0x0002 1841 #define RIO2_IO_ERROR 0x0004 1842 #define RIO2_IO_SUREWRITE 0x0008 1843 #define RIO2_SGL_CONFORMANT 0x0010 1844 #define RIO2_SG_FORMAT 0xF000 1845 #define RIO2_SG_FORMAT_ARC 0x0000 1846 #define RIO2_SG_FORMAT_SRL 0x1000 1847 #define RIO2_SG_FORMAT_IEEE1212 0x2000 1848 1849 struct aac_read 1850 { 1851 __le32 command; 1852 __le32 cid; 1853 __le32 block; 1854 __le32 count; 1855 struct sgmap sg; // Must be last in struct because it is variable 1856 }; 1857 1858 struct aac_read64 1859 { 1860 __le32 command; 1861 __le16 cid; 1862 __le16 sector_count; 1863 __le32 block; 1864 __le16 pad; 1865 __le16 flags; 1866 struct sgmap64 sg; // Must be last in struct because it is variable 1867 }; 1868 1869 struct aac_read_reply 1870 { 1871 __le32 status; 1872 __le32 count; 1873 }; 1874 1875 struct aac_write 1876 { 1877 __le32 command; 1878 __le32 cid; 1879 __le32 block; 1880 __le32 count; 1881 __le32 stable; // Not used 1882 struct sgmap sg; // Must be last in struct because it is variable 1883 }; 1884 1885 struct aac_write64 1886 { 1887 __le32 command; 1888 __le16 cid; 1889 __le16 sector_count; 1890 __le32 block; 1891 __le16 pad; 1892 __le16 flags; 1893 struct sgmap64 sg; // Must be last in struct because it is variable 1894 }; 1895 struct aac_write_reply 1896 { 1897 __le32 status; 1898 __le32 count; 1899 __le32 committed; 1900 }; 1901 1902 struct aac_raw_io 1903 { 1904 __le32 block[2]; 1905 __le32 count; 1906 __le16 cid; 1907 __le16 flags; /* 00 W, 01 R */ 1908 __le16 bpTotal; /* reserved for F/W use */ 1909 __le16 bpComplete; /* reserved for F/W use */ 1910 struct sgmapraw sg; 1911 }; 1912 1913 struct aac_raw_io2 { 1914 __le32 blockLow; 1915 __le32 blockHigh; 1916 __le32 byteCount; 1917 __le16 cid; 1918 __le16 flags; /* RIO2 flags */ 1919 __le32 sgeFirstSize; /* size of first sge el. */ 1920 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */ 1921 u8 sgeCnt; /* only 8 bits required */ 1922 u8 bpTotal; /* reserved for F/W use */ 1923 u8 bpComplete; /* reserved for F/W use */ 1924 u8 sgeFirstIndex; /* reserved for F/W use */ 1925 u8 unused[4]; 1926 struct sge_ieee1212 sge[1]; 1927 }; 1928 1929 #define CT_FLUSH_CACHE 129 1930 struct aac_synchronize { 1931 __le32 command; /* VM_ContainerConfig */ 1932 __le32 type; /* CT_FLUSH_CACHE */ 1933 __le32 cid; 1934 __le32 parm1; 1935 __le32 parm2; 1936 __le32 parm3; 1937 __le32 parm4; 1938 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */ 1939 }; 1940 1941 struct aac_synchronize_reply { 1942 __le32 dummy0; 1943 __le32 dummy1; 1944 __le32 status; /* CT_OK */ 1945 __le32 parm1; 1946 __le32 parm2; 1947 __le32 parm3; 1948 __le32 parm4; 1949 __le32 parm5; 1950 u8 data[16]; 1951 }; 1952 1953 #define CT_POWER_MANAGEMENT 245 1954 #define CT_PM_START_UNIT 2 1955 #define CT_PM_STOP_UNIT 3 1956 #define CT_PM_UNIT_IMMEDIATE 1 1957 struct aac_power_management { 1958 __le32 command; /* VM_ContainerConfig */ 1959 __le32 type; /* CT_POWER_MANAGEMENT */ 1960 __le32 sub; /* CT_PM_* */ 1961 __le32 cid; 1962 __le32 parm; /* CT_PM_sub_* */ 1963 }; 1964 1965 #define CT_PAUSE_IO 65 1966 #define CT_RELEASE_IO 66 1967 struct aac_pause { 1968 __le32 command; /* VM_ContainerConfig */ 1969 __le32 type; /* CT_PAUSE_IO */ 1970 __le32 timeout; /* 10ms ticks */ 1971 __le32 min; 1972 __le32 noRescan; 1973 __le32 parm3; 1974 __le32 parm4; 1975 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */ 1976 }; 1977 1978 struct aac_srb 1979 { 1980 __le32 function; 1981 __le32 channel; 1982 __le32 id; 1983 __le32 lun; 1984 __le32 timeout; 1985 __le32 flags; 1986 __le32 count; // Data xfer size 1987 __le32 retry_limit; 1988 __le32 cdb_size; 1989 u8 cdb[16]; 1990 struct sgmap sg; 1991 }; 1992 1993 /* 1994 * This and associated data structs are used by the 1995 * ioctl caller and are in cpu order. 1996 */ 1997 struct user_aac_srb 1998 { 1999 u32 function; 2000 u32 channel; 2001 u32 id; 2002 u32 lun; 2003 u32 timeout; 2004 u32 flags; 2005 u32 count; // Data xfer size 2006 u32 retry_limit; 2007 u32 cdb_size; 2008 u8 cdb[16]; 2009 struct user_sgmap sg; 2010 }; 2011 2012 #define AAC_SENSE_BUFFERSIZE 30 2013 2014 struct aac_srb_reply 2015 { 2016 __le32 status; 2017 __le32 srb_status; 2018 __le32 scsi_status; 2019 __le32 data_xfer_length; 2020 __le32 sense_data_size; 2021 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE 2022 }; 2023 /* 2024 * SRB Flags 2025 */ 2026 #define SRB_NoDataXfer 0x0000 2027 #define SRB_DisableDisconnect 0x0004 2028 #define SRB_DisableSynchTransfer 0x0008 2029 #define SRB_BypassFrozenQueue 0x0010 2030 #define SRB_DisableAutosense 0x0020 2031 #define SRB_DataIn 0x0040 2032 #define SRB_DataOut 0x0080 2033 2034 /* 2035 * SRB Functions - set in aac_srb->function 2036 */ 2037 #define SRBF_ExecuteScsi 0x0000 2038 #define SRBF_ClaimDevice 0x0001 2039 #define SRBF_IO_Control 0x0002 2040 #define SRBF_ReceiveEvent 0x0003 2041 #define SRBF_ReleaseQueue 0x0004 2042 #define SRBF_AttachDevice 0x0005 2043 #define SRBF_ReleaseDevice 0x0006 2044 #define SRBF_Shutdown 0x0007 2045 #define SRBF_Flush 0x0008 2046 #define SRBF_AbortCommand 0x0010 2047 #define SRBF_ReleaseRecovery 0x0011 2048 #define SRBF_ResetBus 0x0012 2049 #define SRBF_ResetDevice 0x0013 2050 #define SRBF_TerminateIO 0x0014 2051 #define SRBF_FlushQueue 0x0015 2052 #define SRBF_RemoveDevice 0x0016 2053 #define SRBF_DomainValidation 0x0017 2054 2055 /* 2056 * SRB SCSI Status - set in aac_srb->scsi_status 2057 */ 2058 #define SRB_STATUS_PENDING 0x00 2059 #define SRB_STATUS_SUCCESS 0x01 2060 #define SRB_STATUS_ABORTED 0x02 2061 #define SRB_STATUS_ABORT_FAILED 0x03 2062 #define SRB_STATUS_ERROR 0x04 2063 #define SRB_STATUS_BUSY 0x05 2064 #define SRB_STATUS_INVALID_REQUEST 0x06 2065 #define SRB_STATUS_INVALID_PATH_ID 0x07 2066 #define SRB_STATUS_NO_DEVICE 0x08 2067 #define SRB_STATUS_TIMEOUT 0x09 2068 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A 2069 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B 2070 #define SRB_STATUS_MESSAGE_REJECTED 0x0D 2071 #define SRB_STATUS_BUS_RESET 0x0E 2072 #define SRB_STATUS_PARITY_ERROR 0x0F 2073 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10 2074 #define SRB_STATUS_NO_HBA 0x11 2075 #define SRB_STATUS_DATA_OVERRUN 0x12 2076 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13 2077 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14 2078 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15 2079 #define SRB_STATUS_REQUEST_FLUSHED 0x16 2080 #define SRB_STATUS_DELAYED_RETRY 0x17 2081 #define SRB_STATUS_INVALID_LUN 0x20 2082 #define SRB_STATUS_INVALID_TARGET_ID 0x21 2083 #define SRB_STATUS_BAD_FUNCTION 0x22 2084 #define SRB_STATUS_ERROR_RECOVERY 0x23 2085 #define SRB_STATUS_NOT_STARTED 0x24 2086 #define SRB_STATUS_NOT_IN_USE 0x30 2087 #define SRB_STATUS_FORCE_ABORT 0x31 2088 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32 2089 2090 /* 2091 * Object-Server / Volume-Manager Dispatch Classes 2092 */ 2093 2094 #define VM_Null 0 2095 #define VM_NameServe 1 2096 #define VM_ContainerConfig 2 2097 #define VM_Ioctl 3 2098 #define VM_FilesystemIoctl 4 2099 #define VM_CloseAll 5 2100 #define VM_CtBlockRead 6 2101 #define VM_CtBlockWrite 7 2102 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */ 2103 #define VM_SliceBlockWrite 9 2104 #define VM_DriveBlockRead 10 /* raw access to physical devices */ 2105 #define VM_DriveBlockWrite 11 2106 #define VM_EnclosureMgt 12 /* enclosure management */ 2107 #define VM_Unused 13 /* used to be diskset management */ 2108 #define VM_CtBlockVerify 14 2109 #define VM_CtPerf 15 /* performance test */ 2110 #define VM_CtBlockRead64 16 2111 #define VM_CtBlockWrite64 17 2112 #define VM_CtBlockVerify64 18 2113 #define VM_CtHostRead64 19 2114 #define VM_CtHostWrite64 20 2115 #define VM_DrvErrTblLog 21 2116 #define VM_NameServe64 22 2117 #define VM_NameServeAllBlk 30 2118 2119 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */ 2120 2121 /* 2122 * Descriptive information (eg, vital stats) 2123 * that a content manager might report. The 2124 * FileArray filesystem component is one example 2125 * of a content manager. Raw mode might be 2126 * another. 2127 */ 2128 2129 struct aac_fsinfo { 2130 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */ 2131 __le32 fsBlockSize; 2132 __le32 fsFragSize; 2133 __le32 fsMaxExtendSize; 2134 __le32 fsSpaceUnits; 2135 __le32 fsMaxNumFiles; 2136 __le32 fsNumFreeFiles; 2137 __le32 fsInodeDensity; 2138 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */ 2139 2140 struct aac_blockdevinfo { 2141 __le32 block_size; 2142 __le32 logical_phys_map; 2143 u8 identifier[16]; 2144 }; 2145 2146 union aac_contentinfo { 2147 struct aac_fsinfo filesys; 2148 struct aac_blockdevinfo bdevinfo; 2149 }; 2150 2151 /* 2152 * Query for Container Configuration Status 2153 */ 2154 2155 #define CT_GET_CONFIG_STATUS 147 2156 struct aac_get_config_status { 2157 __le32 command; /* VM_ContainerConfig */ 2158 __le32 type; /* CT_GET_CONFIG_STATUS */ 2159 __le32 parm1; 2160 __le32 parm2; 2161 __le32 parm3; 2162 __le32 parm4; 2163 __le32 parm5; 2164 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */ 2165 }; 2166 2167 #define CFACT_CONTINUE 0 2168 #define CFACT_PAUSE 1 2169 #define CFACT_ABORT 2 2170 struct aac_get_config_status_resp { 2171 __le32 response; /* ST_OK */ 2172 __le32 dummy0; 2173 __le32 status; /* CT_OK */ 2174 __le32 parm1; 2175 __le32 parm2; 2176 __le32 parm3; 2177 __le32 parm4; 2178 __le32 parm5; 2179 struct { 2180 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */ 2181 __le16 flags; 2182 __le16 count; 2183 } data; 2184 }; 2185 2186 /* 2187 * Accept the configuration as-is 2188 */ 2189 2190 #define CT_COMMIT_CONFIG 152 2191 2192 struct aac_commit_config { 2193 __le32 command; /* VM_ContainerConfig */ 2194 __le32 type; /* CT_COMMIT_CONFIG */ 2195 }; 2196 2197 /* 2198 * Query for Container Configuration Status 2199 */ 2200 2201 #define CT_GET_CONTAINER_COUNT 4 2202 struct aac_get_container_count { 2203 __le32 command; /* VM_ContainerConfig */ 2204 __le32 type; /* CT_GET_CONTAINER_COUNT */ 2205 }; 2206 2207 struct aac_get_container_count_resp { 2208 __le32 response; /* ST_OK */ 2209 __le32 dummy0; 2210 __le32 MaxContainers; 2211 __le32 ContainerSwitchEntries; 2212 __le32 MaxPartitions; 2213 __le32 MaxSimpleVolumes; 2214 }; 2215 2216 2217 /* 2218 * Query for "mountable" objects, ie, objects that are typically 2219 * associated with a drive letter on the client (host) side. 2220 */ 2221 2222 struct aac_mntent { 2223 __le32 oid; 2224 u8 name[16]; /* if applicable */ 2225 struct creation_info create_info; /* if applicable */ 2226 __le32 capacity; 2227 __le32 vol; /* substrate structure */ 2228 __le32 obj; /* FT_FILESYS, etc. */ 2229 __le32 state; /* unready for mounting, 2230 readonly, etc. */ 2231 union aac_contentinfo fileinfo; /* Info specific to content 2232 manager (eg, filesystem) */ 2233 __le32 altoid; /* != oid <==> snapshot or 2234 broken mirror exists */ 2235 __le32 capacityhigh; 2236 }; 2237 2238 #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */ 2239 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */ 2240 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */ 2241 #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */ 2242 2243 struct aac_query_mount { 2244 __le32 command; 2245 __le32 type; 2246 __le32 count; 2247 }; 2248 2249 struct aac_mount { 2250 __le32 status; 2251 __le32 type; /* should be same as that requested */ 2252 __le32 count; 2253 struct aac_mntent mnt[1]; 2254 }; 2255 2256 #define CT_READ_NAME 130 2257 struct aac_get_name { 2258 __le32 command; /* VM_ContainerConfig */ 2259 __le32 type; /* CT_READ_NAME */ 2260 __le32 cid; 2261 __le32 parm1; 2262 __le32 parm2; 2263 __le32 parm3; 2264 __le32 parm4; 2265 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */ 2266 }; 2267 2268 struct aac_get_name_resp { 2269 __le32 dummy0; 2270 __le32 dummy1; 2271 __le32 status; /* CT_OK */ 2272 __le32 parm1; 2273 __le32 parm2; 2274 __le32 parm3; 2275 __le32 parm4; 2276 __le32 parm5; 2277 u8 data[16]; 2278 }; 2279 2280 #define CT_CID_TO_32BITS_UID 165 2281 struct aac_get_serial { 2282 __le32 command; /* VM_ContainerConfig */ 2283 __le32 type; /* CT_CID_TO_32BITS_UID */ 2284 __le32 cid; 2285 }; 2286 2287 struct aac_get_serial_resp { 2288 __le32 dummy0; 2289 __le32 dummy1; 2290 __le32 status; /* CT_OK */ 2291 __le32 uid; 2292 }; 2293 2294 /* 2295 * The following command is sent to shut down each container. 2296 */ 2297 2298 struct aac_close { 2299 __le32 command; 2300 __le32 cid; 2301 }; 2302 2303 struct aac_query_disk 2304 { 2305 s32 cnum; 2306 s32 bus; 2307 s32 id; 2308 s32 lun; 2309 u32 valid; 2310 u32 locked; 2311 u32 deleted; 2312 s32 instance; 2313 s8 name[10]; 2314 u32 unmapped; 2315 }; 2316 2317 struct aac_delete_disk { 2318 u32 disknum; 2319 u32 cnum; 2320 }; 2321 2322 struct fib_ioctl 2323 { 2324 u32 fibctx; 2325 s32 wait; 2326 char __user *fib; 2327 }; 2328 2329 struct revision 2330 { 2331 u32 compat; 2332 __le32 version; 2333 __le32 build; 2334 }; 2335 2336 2337 /* 2338 * Ugly - non Linux like ioctl coding for back compat. 2339 */ 2340 2341 #define CTL_CODE(function, method) ( \ 2342 (4<< 16) | ((function) << 2) | (method) \ 2343 ) 2344 2345 /* 2346 * Define the method codes for how buffers are passed for I/O and FS 2347 * controls 2348 */ 2349 2350 #define METHOD_BUFFERED 0 2351 #define METHOD_NEITHER 3 2352 2353 /* 2354 * Filesystem ioctls 2355 */ 2356 2357 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED) 2358 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED) 2359 #define FSACTL_DELETE_DISK 0x163 2360 #define FSACTL_QUERY_DISK 0x173 2361 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED) 2362 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED) 2363 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED) 2364 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED) 2365 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED) 2366 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER) 2367 #define FSACTL_GET_CONTAINERS 2131 2368 #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED) 2369 #define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED) 2370 #define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED) 2371 /* flags defined for IOP & HW SOFT RESET */ 2372 #define HW_IOP_RESET 0x01 2373 #define HW_SOFT_RESET 0x02 2374 #define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET) 2375 /* HW Soft Reset register offset */ 2376 #define IBW_SWR_OFFSET 0x4000 2377 #define SOFT_RESET_TIME 60 2378 2379 2380 2381 struct aac_common 2382 { 2383 /* 2384 * If this value is set to 1 then interrupt moderation will occur 2385 * in the base commuication support. 2386 */ 2387 u32 irq_mod; 2388 u32 peak_fibs; 2389 u32 zero_fibs; 2390 u32 fib_timeouts; 2391 /* 2392 * Statistical counters in debug mode 2393 */ 2394 #ifdef DBG 2395 u32 FibsSent; 2396 u32 FibRecved; 2397 u32 NativeSent; 2398 u32 NativeRecved; 2399 u32 NoResponseSent; 2400 u32 NoResponseRecved; 2401 u32 AsyncSent; 2402 u32 AsyncRecved; 2403 u32 NormalSent; 2404 u32 NormalRecved; 2405 #endif 2406 }; 2407 2408 extern struct aac_common aac_config; 2409 2410 /* 2411 * This is for management ioctl purpose only. 2412 */ 2413 struct aac_hba_info { 2414 2415 u8 driver_name[50]; 2416 u8 adapter_number; 2417 u8 system_io_bus_number; 2418 u8 device_number; 2419 u32 function_number; 2420 u32 vendor_id; 2421 u32 device_id; 2422 u32 sub_vendor_id; 2423 u32 sub_system_id; 2424 u32 mapped_base_address_size; 2425 u32 base_physical_address_high_part; 2426 u32 base_physical_address_low_part; 2427 2428 u32 max_command_size; 2429 u32 max_fib_size; 2430 u32 max_scatter_gather_from_os; 2431 u32 max_scatter_gather_to_fw; 2432 u32 max_outstanding_fibs; 2433 2434 u32 queue_start_threshold; 2435 u32 queue_dump_threshold; 2436 u32 max_io_size_queued; 2437 u32 outstanding_io; 2438 2439 u32 firmware_build_number; 2440 u32 bios_build_number; 2441 u32 driver_build_number; 2442 u32 serial_number_high_part; 2443 u32 serial_number_low_part; 2444 u32 supported_options; 2445 u32 feature_bits; 2446 u32 currentnumber_ports; 2447 2448 u8 new_comm_interface:1; 2449 u8 new_commands_supported:1; 2450 u8 disable_passthrough:1; 2451 u8 expose_non_dasd:1; 2452 u8 queue_allowed:1; 2453 u8 bled_check_enabled:1; 2454 u8 reserved1:1; 2455 u8 reserted2:1; 2456 2457 u32 reserved3[10]; 2458 2459 }; 2460 2461 /* 2462 * The following macro is used when sending and receiving FIBs. It is 2463 * only used for debugging. 2464 */ 2465 2466 #ifdef DBG 2467 #define FIB_COUNTER_INCREMENT(counter) (counter)++ 2468 #else 2469 #define FIB_COUNTER_INCREMENT(counter) 2470 #endif 2471 2472 /* 2473 * Adapter direct commands 2474 * Monitor/Kernel API 2475 */ 2476 2477 #define BREAKPOINT_REQUEST 0x00000004 2478 #define INIT_STRUCT_BASE_ADDRESS 0x00000005 2479 #define READ_PERMANENT_PARAMETERS 0x0000000a 2480 #define WRITE_PERMANENT_PARAMETERS 0x0000000b 2481 #define HOST_CRASHING 0x0000000d 2482 #define SEND_SYNCHRONOUS_FIB 0x0000000c 2483 #define COMMAND_POST_RESULTS 0x00000014 2484 #define GET_ADAPTER_PROPERTIES 0x00000019 2485 #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023 2486 #define RCV_TEMP_READINGS 0x00000025 2487 #define GET_COMM_PREFERRED_SETTINGS 0x00000026 2488 #define IOP_RESET_FW_FIB_DUMP 0x00000034 2489 #define IOP_RESET 0x00001000 2490 #define IOP_RESET_ALWAYS 0x00001001 2491 #define RE_INIT_ADAPTER 0x000000ee 2492 2493 #define IOP_SRC_RESET_MASK 0x00000100 2494 2495 /* 2496 * Adapter Status Register 2497 * 2498 * Phase Staus mailbox is 32bits: 2499 * <31:16> = Phase Status 2500 * <15:0> = Phase 2501 * 2502 * The adapter reports is present state through the phase. Only 2503 * a single phase should be ever be set. Each phase can have multiple 2504 * phase status bits to provide more detailed information about the 2505 * state of the board. Care should be taken to ensure that any phase 2506 * status bits that are set when changing the phase are also valid 2507 * for the new phase or be cleared out. Adapter software (monitor, 2508 * iflash, kernel) is responsible for properly maintining the phase 2509 * status mailbox when it is running. 2510 * 2511 * MONKER_API Phases 2512 * 2513 * Phases are bit oriented. It is NOT valid to have multiple bits set 2514 */ 2515 2516 #define SELF_TEST_FAILED 0x00000004 2517 #define MONITOR_PANIC 0x00000020 2518 #define KERNEL_BOOTING 0x00000040 2519 #define KERNEL_UP_AND_RUNNING 0x00000080 2520 #define KERNEL_PANIC 0x00000100 2521 #define FLASH_UPD_PENDING 0x00002000 2522 #define FLASH_UPD_SUCCESS 0x00004000 2523 #define FLASH_UPD_FAILED 0x00008000 2524 #define FWUPD_TIMEOUT (5 * 60) 2525 2526 /* 2527 * Doorbell bit defines 2528 */ 2529 2530 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */ 2531 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */ 2532 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */ 2533 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */ 2534 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */ 2535 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */ 2536 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */ 2537 #define DoorBellAifPending (1<<6) /* Adapter -> Host */ 2538 2539 /* PMC specific outbound doorbell bits */ 2540 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */ 2541 2542 /* 2543 * For FIB communication, we need all of the following things 2544 * to send back to the user. 2545 */ 2546 2547 #define AifCmdEventNotify 1 /* Notify of event */ 2548 #define AifEnConfigChange 3 /* Adapter configuration change */ 2549 #define AifEnContainerChange 4 /* Container configuration change */ 2550 #define AifEnDeviceFailure 5 /* SCSI device failed */ 2551 #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */ 2552 #define EM_DRIVE_INSERTION 31 2553 #define EM_DRIVE_REMOVAL 32 2554 #define EM_SES_DRIVE_INSERTION 33 2555 #define EM_SES_DRIVE_REMOVAL 26 2556 #define AifEnBatteryEvent 14 /* Change in Battery State */ 2557 #define AifEnAddContainer 15 /* A new array was created */ 2558 #define AifEnDeleteContainer 16 /* A container was deleted */ 2559 #define AifEnExpEvent 23 /* Firmware Event Log */ 2560 #define AifExeFirmwarePanic 3 /* Firmware Event Panic */ 2561 #define AifHighPriority 3 /* Highest Priority Event */ 2562 #define AifEnAddJBOD 30 /* JBOD created */ 2563 #define AifEnDeleteJBOD 31 /* JBOD deleted */ 2564 2565 #define AifBuManagerEvent 42 /* Bu management*/ 2566 #define AifBuCacheDataLoss 10 2567 #define AifBuCacheDataRecover 11 2568 2569 #define AifCmdJobProgress 2 /* Progress report */ 2570 #define AifJobCtrZero 101 /* Array Zero progress */ 2571 #define AifJobStsSuccess 1 /* Job completes */ 2572 #define AifJobStsRunning 102 /* Job running */ 2573 #define AifCmdAPIReport 3 /* Report from other user of API */ 2574 #define AifCmdDriverNotify 4 /* Notify host driver of event */ 2575 #define AifDenMorphComplete 200 /* A morph operation completed */ 2576 #define AifDenVolumeExtendComplete 201 /* A volume extend completed */ 2577 #define AifReqJobList 100 /* Gets back complete job list */ 2578 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */ 2579 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */ 2580 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */ 2581 #define AifReqTerminateJob 104 /* Terminates job */ 2582 #define AifReqSuspendJob 105 /* Suspends a job */ 2583 #define AifReqResumeJob 106 /* Resumes a job */ 2584 #define AifReqSendAPIReport 107 /* API generic report requests */ 2585 #define AifReqAPIJobStart 108 /* Start a job from the API */ 2586 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */ 2587 #define AifReqAPIJobFinish 110 /* Finish a job from the API */ 2588 2589 /* PMC NEW COMM: Request the event data */ 2590 #define AifReqEvent 200 2591 #define AifRawDeviceRemove 203 /* RAW device deleted */ 2592 #define AifNativeDeviceAdd 204 /* native HBA device added */ 2593 #define AifNativeDeviceRemove 205 /* native HBA device removed */ 2594 2595 2596 /* 2597 * Adapter Initiated FIB command structures. Start with the adapter 2598 * initiated FIBs that really come from the adapter, and get responded 2599 * to by the host. 2600 */ 2601 2602 struct aac_aifcmd { 2603 __le32 command; /* Tell host what type of notify this is */ 2604 __le32 seqnum; /* To allow ordering of reports (if necessary) */ 2605 u8 data[1]; /* Undefined length (from kernel viewpoint) */ 2606 }; 2607 2608 /** 2609 * Convert capacity to cylinders 2610 * accounting for the fact capacity could be a 64 bit value 2611 * 2612 */ 2613 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor) 2614 { 2615 sector_div(capacity, divisor); 2616 return capacity; 2617 } 2618 2619 static inline int aac_adapter_check_health(struct aac_dev *dev) 2620 { 2621 if (unlikely(pci_channel_offline(dev->pdev))) 2622 return -1; 2623 2624 return (dev)->a_ops.adapter_check_health(dev); 2625 } 2626 2627 /* SCp.phase values */ 2628 #define AAC_OWNER_MIDLEVEL 0x101 2629 #define AAC_OWNER_LOWLEVEL 0x102 2630 #define AAC_OWNER_ERROR_HANDLER 0x103 2631 #define AAC_OWNER_FIRMWARE 0x106 2632 2633 int aac_acquire_irq(struct aac_dev *dev); 2634 void aac_free_irq(struct aac_dev *dev); 2635 int aac_report_phys_luns(struct aac_dev *dev, struct fib *fibptr, int rescan); 2636 int aac_issue_bmic_identify(struct aac_dev *dev, u32 bus, u32 target); 2637 const char *aac_driverinfo(struct Scsi_Host *); 2638 void aac_fib_vector_assign(struct aac_dev *dev); 2639 struct fib *aac_fib_alloc(struct aac_dev *dev); 2640 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd); 2641 int aac_fib_setup(struct aac_dev *dev); 2642 void aac_fib_map_free(struct aac_dev *dev); 2643 void aac_fib_free(struct fib * context); 2644 void aac_fib_init(struct fib * context); 2645 void aac_printf(struct aac_dev *dev, u32 val); 2646 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt); 2647 int aac_hba_send(u8 command, struct fib *context, 2648 fib_callback callback, void *ctxt); 2649 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry); 2650 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum); 2651 int aac_fib_complete(struct fib * context); 2652 void aac_hba_callback(void *context, struct fib *fibptr); 2653 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data) 2654 struct aac_dev *aac_init_adapter(struct aac_dev *dev); 2655 void aac_src_access_devreg(struct aac_dev *dev, int mode); 2656 void aac_set_intx_mode(struct aac_dev *dev); 2657 int aac_get_config_status(struct aac_dev *dev, int commit_flag); 2658 int aac_get_containers(struct aac_dev *dev); 2659 int aac_scsi_cmd(struct scsi_cmnd *cmd); 2660 int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg); 2661 #ifndef shost_to_class 2662 #define shost_to_class(shost) &shost->shost_dev 2663 #endif 2664 ssize_t aac_get_serial_number(struct device *dev, char *buf); 2665 int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg); 2666 int aac_rx_init(struct aac_dev *dev); 2667 int aac_rkt_init(struct aac_dev *dev); 2668 int aac_nark_init(struct aac_dev *dev); 2669 int aac_sa_init(struct aac_dev *dev); 2670 int aac_src_init(struct aac_dev *dev); 2671 int aac_srcv_init(struct aac_dev *dev); 2672 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify); 2673 void aac_define_int_mode(struct aac_dev *dev); 2674 unsigned int aac_response_normal(struct aac_queue * q); 2675 unsigned int aac_command_normal(struct aac_queue * q); 2676 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index, 2677 int isAif, int isFastResponse, 2678 struct hw_fib *aif_fib); 2679 int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type); 2680 int aac_check_health(struct aac_dev * dev); 2681 int aac_command_thread(void *data); 2682 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx); 2683 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size); 2684 struct aac_driver_ident* aac_get_driver_ident(int devtype); 2685 int aac_get_adapter_info(struct aac_dev* dev); 2686 int aac_send_shutdown(struct aac_dev *dev); 2687 int aac_probe_container(struct aac_dev *dev, int cid); 2688 int _aac_rx_init(struct aac_dev *dev); 2689 int aac_rx_select_comm(struct aac_dev *dev, int comm); 2690 int aac_rx_deliver_producer(struct fib * fib); 2691 2692 static inline int aac_is_src(struct aac_dev *dev) 2693 { 2694 u16 device = dev->pdev->device; 2695 2696 if (device == PMC_DEVICE_S6 || 2697 device == PMC_DEVICE_S7 || 2698 device == PMC_DEVICE_S8) 2699 return 1; 2700 return 0; 2701 } 2702 2703 char * get_container_type(unsigned type); 2704 extern int numacb; 2705 extern char aac_driver_version[]; 2706 extern int startup_timeout; 2707 extern int aif_timeout; 2708 extern int expose_physicals; 2709 extern int aac_reset_devices; 2710 extern int aac_msi; 2711 extern int aac_commit; 2712 extern int update_interval; 2713 extern int check_interval; 2714 extern int aac_check_reset; 2715 extern int aac_fib_dump; 2716 #endif 2717