1 #ifndef _AACRAID_H_ 2 #define _AACRAID_H_ 3 #ifndef dprintk 4 # define dprintk(x) 5 #endif 6 /* eg: if (nblank(dprintk(x))) */ 7 #define _nblank(x) #x 8 #define nblank(x) _nblank(x)[0] 9 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 13 /*------------------------------------------------------------------------------ 14 * D E F I N E S 15 *----------------------------------------------------------------------------*/ 16 17 #define AAC_MAX_MSIX 32 /* vectors */ 18 #define AAC_PCI_MSI_ENABLE 0x8000 19 20 enum { 21 AAC_ENABLE_INTERRUPT = 0x0, 22 AAC_DISABLE_INTERRUPT, 23 AAC_ENABLE_MSIX, 24 AAC_DISABLE_MSIX, 25 AAC_CLEAR_AIF_BIT, 26 AAC_CLEAR_SYNC_BIT, 27 AAC_ENABLE_INTX 28 }; 29 30 #define AAC_INT_MODE_INTX (1<<0) 31 #define AAC_INT_MODE_MSI (1<<1) 32 #define AAC_INT_MODE_AIF (1<<2) 33 #define AAC_INT_MODE_SYNC (1<<3) 34 #define AAC_INT_MODE_MSIX (1<<16) 35 36 #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb 37 #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa 38 #define AAC_INT_DISABLE_ALL 0xffffffff 39 40 /* Bit definitions in IOA->Host Interrupt Register */ 41 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31) 42 #define PMC_IOARCB_TRANSFER_FAILED (1<<28) 43 #define PMC_IOA_UNIT_CHECK (1<<27) 44 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26) 45 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25) 46 #define PMC_IOARRIN_LOST (1<<4) 47 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3) 48 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2) 49 #define PMC_HOST_RRQ_VALID (1<<1) 50 #define PMC_OPERATIONAL_STATUS (1<<31) 51 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0) 52 53 #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \ 54 PMC_IOA_UNIT_CHECK | \ 55 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \ 56 PMC_IOARRIN_LOST | \ 57 PMC_SYSTEM_BUS_MMIO_ERROR | \ 58 PMC_IOA_PROCESSOR_IN_ERROR_STATE) 59 60 #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \ 61 PMC_HOST_RRQ_VALID | \ 62 PMC_TRANSITION_TO_OPERATIONAL | \ 63 PMC_ALLOW_MSIX_VECTOR0) 64 #define PMC_GLOBAL_INT_BIT2 0x00000004 65 #define PMC_GLOBAL_INT_BIT0 0x00000001 66 67 #ifndef AAC_DRIVER_BUILD 68 # define AAC_DRIVER_BUILD 41066 69 # define AAC_DRIVER_BRANCH "-ms" 70 #endif 71 #define MAXIMUM_NUM_CONTAINERS 32 72 73 #define AAC_NUM_MGT_FIB 8 74 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB) 75 #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB) 76 77 #define AAC_MAX_LUN 256 78 79 #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff) 80 #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256) 81 82 #define AAC_DEBUG_INSTRUMENT_AIF_DELETE 83 84 #define AAC_MAX_NATIVE_TARGETS 1024 85 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */ 86 #define AAC_MAX_BUSES 5 87 #define AAC_MAX_TARGETS 256 88 #define AAC_MAX_NATIVE_SIZE 2048 89 #define FW_ERROR_BUFFER_SIZE 512 90 91 /* Thor AIF events */ 92 #define SA_AIF_HOTPLUG (1<<1) 93 #define SA_AIF_HARDWARE (1<<2) 94 #define SA_AIF_PDEV_CHANGE (1<<4) 95 #define SA_AIF_LDEV_CHANGE (1<<5) 96 #define SA_AIF_BPSTAT_CHANGE (1<<30) 97 #define SA_AIF_BPCFG_CHANGE (1<<31) 98 99 #define HBA_MAX_SG_EMBEDDED 28 100 #define HBA_MAX_SG_SEPARATE 90 101 #define HBA_SENSE_DATA_LEN_MAX 32 102 #define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002 103 #define HBA_SGL_FLAGS_EXT 0x80000000UL 104 105 struct aac_hba_sgl { 106 u32 addr_lo; /* Lower 32-bits of SGL element address */ 107 u32 addr_hi; /* Upper 32-bits of SGL element address */ 108 u32 len; /* Length of SGL element in bytes */ 109 u32 flags; /* SGL element flags */ 110 }; 111 112 enum { 113 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40, 114 HBA_IU_TYPE_SCSI_TM_REQ = 0x41, 115 HBA_IU_TYPE_SATA_REQ = 0x42, 116 HBA_IU_TYPE_RESP = 0x60, 117 HBA_IU_TYPE_COALESCED_RESP = 0x61, 118 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70 119 }; 120 121 enum { 122 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1, 123 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2, 124 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4, 125 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8 126 }; 127 128 enum { 129 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0, 130 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT, 131 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR, 132 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE 133 }; 134 135 enum { 136 HBA_RESP_DATAPRES_NO_DATA = 0x0, 137 HBA_RESP_DATAPRES_RESPONSE_DATA, 138 HBA_RESP_DATAPRES_SENSE_DATA 139 }; 140 141 enum { 142 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0, 143 HBA_RESP_SVCRES_FAILURE, 144 HBA_RESP_SVCRES_TMF_COMPLETE, 145 HBA_RESP_SVCRES_TMF_SUCCEEDED, 146 HBA_RESP_SVCRES_TMF_REJECTED, 147 HBA_RESP_SVCRES_TMF_LUN_INVALID 148 }; 149 150 enum { 151 HBA_RESP_STAT_IO_ERROR = 0x1, 152 HBA_RESP_STAT_IO_ABORTED, 153 HBA_RESP_STAT_NO_PATH_TO_DEVICE, 154 HBA_RESP_STAT_INVALID_DEVICE, 155 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE, 156 HBA_RESP_STAT_UNDERRUN = 0x51, 157 HBA_RESP_STAT_OVERRUN = 0x75 158 }; 159 160 struct aac_hba_cmd_req { 161 u8 iu_type; /* HBA information unit type */ 162 /* 163 * byte1: 164 * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT 165 * [2] TYPE - 0=PCI, 1=DDR 166 * [3] CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled 167 */ 168 u8 byte1; 169 u8 reply_qid; /* Host reply queue to post response to */ 170 u8 reserved1; 171 __le32 it_nexus; /* Device handle for the request */ 172 __le32 request_id; /* Sender context */ 173 /* Lower 32-bits of tweak value for crypto enabled IOs */ 174 __le32 tweak_value_lo; 175 u8 cdb[16]; /* SCSI CDB of the command */ 176 u8 lun[8]; /* SCSI LUN of the command */ 177 178 /* Total data length in bytes to be read/written (if any) */ 179 __le32 data_length; 180 181 /* [2:0] Task Attribute, [6:3] Command Priority */ 182 u8 attr_prio; 183 184 /* Number of SGL elements embedded in the HBA req */ 185 u8 emb_data_desc_count; 186 187 __le16 dek_index; /* DEK index for crypto enabled IOs */ 188 189 /* Lower 32-bits of reserved error data target location on the host */ 190 __le32 error_ptr_lo; 191 192 /* Upper 32-bits of reserved error data target location on the host */ 193 __le32 error_ptr_hi; 194 195 /* Length of reserved error data area on the host in bytes */ 196 __le32 error_length; 197 198 /* Upper 32-bits of tweak value for crypto enabled IOs */ 199 __le32 tweak_value_hi; 200 201 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */ 202 203 /* 204 * structure must not exceed 205 * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE 206 */ 207 }; 208 209 /* Task Management Functions (TMF) */ 210 #define HBA_TMF_ABORT_TASK 0x01 211 #define HBA_TMF_LUN_RESET 0x08 212 213 struct aac_hba_tm_req { 214 u8 iu_type; /* HBA information unit type */ 215 u8 reply_qid; /* Host reply queue to post response to */ 216 u8 tmf; /* Task management function */ 217 u8 reserved1; 218 219 __le32 it_nexus; /* Device handle for the command */ 220 221 u8 lun[8]; /* SCSI LUN */ 222 223 /* Used to hold sender context. */ 224 __le32 request_id; /* Sender context */ 225 __le32 reserved2; 226 227 /* Request identifier of managed task */ 228 __le32 managed_request_id; /* Sender context being managed */ 229 __le32 reserved3; 230 231 /* Lower 32-bits of reserved error data target location on the host */ 232 __le32 error_ptr_lo; 233 /* Upper 32-bits of reserved error data target location on the host */ 234 __le32 error_ptr_hi; 235 /* Length of reserved error data area on the host in bytes */ 236 __le32 error_length; 237 }; 238 239 struct aac_hba_reset_req { 240 u8 iu_type; /* HBA information unit type */ 241 /* 0 - reset specified device, 1 - reset all devices */ 242 u8 reset_type; 243 u8 reply_qid; /* Host reply queue to post response to */ 244 u8 reserved1; 245 246 __le32 it_nexus; /* Device handle for the command */ 247 __le32 request_id; /* Sender context */ 248 /* Lower 32-bits of reserved error data target location on the host */ 249 __le32 error_ptr_lo; 250 /* Upper 32-bits of reserved error data target location on the host */ 251 __le32 error_ptr_hi; 252 /* Length of reserved error data area on the host in bytes */ 253 __le32 error_length; 254 }; 255 256 struct aac_hba_resp { 257 u8 iu_type; /* HBA information unit type */ 258 u8 reserved1[3]; 259 __le32 request_identifier; /* sender context */ 260 __le32 reserved2; 261 u8 service_response; /* SCSI service response */ 262 u8 status; /* SCSI status */ 263 u8 datapres; /* [1:0] - data present, [7:2] - reserved */ 264 u8 sense_response_data_len; /* Sense/response data length */ 265 __le32 residual_count; /* Residual data length in bytes */ 266 /* Sense/response data */ 267 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX]; 268 }; 269 270 struct aac_native_hba { 271 union { 272 struct aac_hba_cmd_req cmd; 273 struct aac_hba_tm_req tmr; 274 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE]; 275 } cmd; 276 union { 277 struct aac_hba_resp err; 278 u8 resp_bytes[FW_ERROR_BUFFER_SIZE]; 279 } resp; 280 }; 281 282 #define CISS_REPORT_PHYSICAL_LUNS 0xc3 283 #define WRITE_HOST_WELLNESS 0xa5 284 #define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15 285 #define BMIC_IN 0x26 286 #define BMIC_OUT 0x27 287 288 struct aac_ciss_phys_luns_resp { 289 u8 list_length[4]; /* LUN list length (N-7, big endian) */ 290 u8 resp_flag; /* extended response_flag */ 291 u8 reserved[3]; 292 struct _ciss_lun { 293 u8 tid[3]; /* Target ID */ 294 u8 bus; /* Bus, flag (bits 6,7) */ 295 u8 level3[2]; 296 u8 level2[2]; 297 u8 node_ident[16]; /* phys. node identifier */ 298 } lun[1]; /* List of phys. devices */ 299 }; 300 301 /* 302 * Interrupts 303 */ 304 #define AAC_MAX_HRRQ 64 305 306 struct aac_ciss_identify_pd { 307 u8 scsi_bus; /* SCSI Bus number on controller */ 308 u8 scsi_id; /* SCSI ID on this bus */ 309 u16 block_size; /* sector size in bytes */ 310 u32 total_blocks; /* number for sectors on drive */ 311 u32 reserved_blocks; /* controller reserved (RIS) */ 312 u8 model[40]; /* Physical Drive Model */ 313 u8 serial_number[40]; /* Drive Serial Number */ 314 u8 firmware_revision[8]; /* drive firmware revision */ 315 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ 316 u8 compaq_drive_stamp; /* 0 means drive not stamped */ 317 u8 last_failure_reason; 318 319 u8 flags; 320 u8 more_flags; 321 u8 scsi_lun; /* SCSI LUN for phys drive */ 322 u8 yet_more_flags; 323 u8 even_more_flags; 324 u32 spi_speed_rules; /* SPI Speed :Ultra disable diagnose */ 325 u8 phys_connector[2]; /* connector number on controller */ 326 u8 phys_box_on_bus; /* phys enclosure this drive resides */ 327 u8 phys_bay_in_box; /* phys drv bay this drive resides */ 328 u32 rpm; /* Drive rotational speed in rpm */ 329 u8 device_type; /* type of drive */ 330 u8 sata_version; /* only valid when drive_type is SATA */ 331 u64 big_total_block_count; 332 u64 ris_starting_lba; 333 u32 ris_size; 334 u8 wwid[20]; 335 u8 controller_phy_map[32]; 336 u16 phy_count; 337 u8 phy_connected_dev_type[256]; 338 u8 phy_to_drive_bay_num[256]; 339 u16 phy_to_attached_dev_index[256]; 340 u8 box_index; 341 u8 spitfire_support; 342 u16 extra_physical_drive_flags; 343 u8 negotiated_link_rate[256]; 344 u8 phy_to_phy_map[256]; 345 u8 redundant_path_present_map; 346 u8 redundant_path_failure_map; 347 u8 active_path_number; 348 u16 alternate_paths_phys_connector[8]; 349 u8 alternate_paths_phys_box_on_port[8]; 350 u8 multi_lun_device_lun_count; 351 u8 minimum_good_fw_revision[8]; 352 u8 unique_inquiry_bytes[20]; 353 u8 current_temperature_degreesC; 354 u8 temperature_threshold_degreesC; 355 u8 max_temperature_degreesC; 356 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512 * 2^exp */ 357 u16 current_queue_depth_limit; 358 u8 switch_name[10]; 359 u16 switch_port; 360 u8 alternate_paths_switch_name[40]; 361 u8 alternate_paths_switch_port[8]; 362 u16 power_on_hours; /* valid only if gas gauge supported */ 363 u16 percent_endurance_used; /* valid only if gas gauge supported. */ 364 u8 drive_authentication; 365 u8 smart_carrier_authentication; 366 u8 smart_carrier_app_fw_version; 367 u8 smart_carrier_bootloader_fw_version; 368 u8 SanitizeSecureEraseSupport; 369 u8 DriveKeyFlags; 370 u8 encryption_key_name[64]; 371 u32 misc_drive_flags; 372 u16 dek_index; 373 u16 drive_encryption_flags; 374 u8 sanitize_maximum_time[6]; 375 u8 connector_info_mode; 376 u8 connector_info_number[4]; 377 u8 long_connector_name[64]; 378 u8 device_unique_identifier[16]; 379 u8 padto_2K[17]; 380 } __packed; 381 382 /* 383 * These macros convert from physical channels to virtual channels 384 */ 385 #define CONTAINER_CHANNEL (0) 386 #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL) 387 #define CONTAINER_TO_ID(cont) (cont) 388 #define CONTAINER_TO_LUN(cont) (0) 389 #define ENCLOSURE_CHANNEL (3) 390 391 #define PMC_DEVICE_S6 0x28b 392 #define PMC_DEVICE_S7 0x28c 393 #define PMC_DEVICE_S8 0x28d 394 #define PMC_DEVICE_S9 0x28f 395 396 #define aac_phys_to_logical(x) ((x)+1) 397 #define aac_logical_to_phys(x) ((x)?(x)-1:0) 398 399 /* 400 * These macros are for keeping track of 401 * character device state. 402 */ 403 #define AAC_CHARDEV_UNREGISTERED (-1) 404 #define AAC_CHARDEV_NEEDS_REINIT (-2) 405 406 /* #define AAC_DETAILED_STATUS_INFO */ 407 408 struct diskparm 409 { 410 int heads; 411 int sectors; 412 int cylinders; 413 }; 414 415 416 /* 417 * Firmware constants 418 */ 419 420 #define CT_NONE 0 421 #define CT_OK 218 422 #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */ 423 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */ 424 425 /* 426 * Host side memory scatter gather list 427 * Used by the adapter for read, write, and readdirplus operations 428 * We have separate 32 and 64 bit version because even 429 * on 64 bit systems not all cards support the 64 bit version 430 */ 431 struct sgentry { 432 __le32 addr; /* 32-bit address. */ 433 __le32 count; /* Length. */ 434 }; 435 436 struct user_sgentry { 437 u32 addr; /* 32-bit address. */ 438 u32 count; /* Length. */ 439 }; 440 441 struct sgentry64 { 442 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 443 __le32 count; /* Length. */ 444 }; 445 446 struct user_sgentry64 { 447 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ 448 u32 count; /* Length. */ 449 }; 450 451 struct sgentryraw { 452 __le32 next; /* reserved for F/W use */ 453 __le32 prev; /* reserved for F/W use */ 454 __le32 addr[2]; 455 __le32 count; 456 __le32 flags; /* reserved for F/W use */ 457 }; 458 459 struct user_sgentryraw { 460 u32 next; /* reserved for F/W use */ 461 u32 prev; /* reserved for F/W use */ 462 u32 addr[2]; 463 u32 count; 464 u32 flags; /* reserved for F/W use */ 465 }; 466 467 struct sge_ieee1212 { 468 u32 addrLow; 469 u32 addrHigh; 470 u32 length; 471 u32 flags; 472 }; 473 474 /* 475 * SGMAP 476 * 477 * This is the SGMAP structure for all commands that use 478 * 32-bit addressing. 479 */ 480 481 struct sgmap { 482 __le32 count; 483 struct sgentry sg[1]; 484 }; 485 486 struct user_sgmap { 487 u32 count; 488 struct user_sgentry sg[1]; 489 }; 490 491 struct sgmap64 { 492 __le32 count; 493 struct sgentry64 sg[1]; 494 }; 495 496 struct user_sgmap64 { 497 u32 count; 498 struct user_sgentry64 sg[1]; 499 }; 500 501 struct sgmapraw { 502 __le32 count; 503 struct sgentryraw sg[1]; 504 }; 505 506 struct user_sgmapraw { 507 u32 count; 508 struct user_sgentryraw sg[1]; 509 }; 510 511 struct creation_info 512 { 513 u8 buildnum; /* e.g., 588 */ 514 u8 usec; /* e.g., 588 */ 515 u8 via; /* e.g., 1 = FSU, 516 * 2 = API 517 */ 518 u8 year; /* e.g., 1997 = 97 */ 519 __le32 date; /* 520 * unsigned Month :4; // 1 - 12 521 * unsigned Day :6; // 1 - 32 522 * unsigned Hour :6; // 0 - 23 523 * unsigned Minute :6; // 0 - 60 524 * unsigned Second :6; // 0 - 60 525 */ 526 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */ 527 }; 528 529 530 /* 531 * Define all the constants needed for the communication interface 532 */ 533 534 /* 535 * Define how many queue entries each queue will have and the total 536 * number of entries for the entire communication interface. Also define 537 * how many queues we support. 538 * 539 * This has to match the controller 540 */ 541 542 #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response 543 #define HOST_HIGH_CMD_ENTRIES 4 544 #define HOST_NORM_CMD_ENTRIES 8 545 #define ADAP_HIGH_CMD_ENTRIES 4 546 #define ADAP_NORM_CMD_ENTRIES 512 547 #define HOST_HIGH_RESP_ENTRIES 4 548 #define HOST_NORM_RESP_ENTRIES 512 549 #define ADAP_HIGH_RESP_ENTRIES 4 550 #define ADAP_NORM_RESP_ENTRIES 8 551 552 #define TOTAL_QUEUE_ENTRIES \ 553 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \ 554 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES) 555 556 557 /* 558 * Set the queues on a 16 byte alignment 559 */ 560 561 #define QUEUE_ALIGNMENT 16 562 563 /* 564 * The queue headers define the Communication Region queues. These 565 * are physically contiguous and accessible by both the adapter and the 566 * host. Even though all queue headers are in the same contiguous block 567 * they will be represented as individual units in the data structures. 568 */ 569 570 struct aac_entry { 571 __le32 size; /* Size in bytes of Fib which this QE points to */ 572 __le32 addr; /* Receiver address of the FIB */ 573 }; 574 575 /* 576 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped 577 * adjacently and in that order. 578 */ 579 580 struct aac_qhdr { 581 __le64 header_addr;/* Address to hand the adapter to access 582 to this queue head */ 583 __le32 *producer; /* The producer index for this queue (host address) */ 584 __le32 *consumer; /* The consumer index for this queue (host address) */ 585 }; 586 587 /* 588 * Define all the events which the adapter would like to notify 589 * the host of. 590 */ 591 592 #define HostNormCmdQue 1 /* Change in host normal priority command queue */ 593 #define HostHighCmdQue 2 /* Change in host high priority command queue */ 594 #define HostNormRespQue 3 /* Change in host normal priority response queue */ 595 #define HostHighRespQue 4 /* Change in host high priority response queue */ 596 #define AdapNormRespNotFull 5 597 #define AdapHighRespNotFull 6 598 #define AdapNormCmdNotFull 7 599 #define AdapHighCmdNotFull 8 600 #define SynchCommandComplete 9 601 #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */ 602 603 /* 604 * Define all the events the host wishes to notify the 605 * adapter of. The first four values much match the Qid the 606 * corresponding queue. 607 */ 608 609 #define AdapNormCmdQue 2 610 #define AdapHighCmdQue 3 611 #define AdapNormRespQue 6 612 #define AdapHighRespQue 7 613 #define HostShutdown 8 614 #define HostPowerFail 9 615 #define FatalCommError 10 616 #define HostNormRespNotFull 11 617 #define HostHighRespNotFull 12 618 #define HostNormCmdNotFull 13 619 #define HostHighCmdNotFull 14 620 #define FastIo 15 621 #define AdapPrintfDone 16 622 623 /* 624 * Define all the queues that the adapter and host use to communicate 625 * Number them to match the physical queue layout. 626 */ 627 628 enum aac_queue_types { 629 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */ 630 HostHighCmdQueue, /* Adapter to host high priority command traffic */ 631 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */ 632 AdapHighCmdQueue, /* Host to adapter high priority command traffic */ 633 HostNormRespQueue, /* Adapter to host normal priority response traffic */ 634 HostHighRespQueue, /* Adapter to host high priority response traffic */ 635 AdapNormRespQueue, /* Host to adapter normal priority response traffic */ 636 AdapHighRespQueue /* Host to adapter high priority response traffic */ 637 }; 638 639 /* 640 * Assign type values to the FSA communication data structures 641 */ 642 643 #define FIB_MAGIC 0x0001 644 #define FIB_MAGIC2 0x0004 645 #define FIB_MAGIC2_64 0x0005 646 647 /* 648 * Define the priority levels the FSA communication routines support. 649 */ 650 651 #define FsaNormal 1 652 653 /* transport FIB header (PMC) */ 654 struct aac_fib_xporthdr { 655 __le64 HostAddress; /* FIB host address w/o xport header */ 656 __le32 Size; /* FIB size excluding xport header */ 657 __le32 Handle; /* driver handle to reference the FIB */ 658 __le64 Reserved[2]; 659 }; 660 661 #define ALIGN32 32 662 663 /* 664 * Define the FIB. The FIB is the where all the requested data and 665 * command information are put to the application on the FSA adapter. 666 */ 667 668 struct aac_fibhdr { 669 __le32 XferState; /* Current transfer state for this CCB */ 670 __le16 Command; /* Routing information for the destination */ 671 u8 StructType; /* Type FIB */ 672 u8 Unused; /* Unused */ 673 __le16 Size; /* Size of this FIB in bytes */ 674 __le16 SenderSize; /* Size of the FIB in the sender 675 (for response sizing) */ 676 __le32 SenderFibAddress; /* Host defined data in the FIB */ 677 union { 678 __le32 ReceiverFibAddress;/* Logical address of this FIB for 679 the adapter (old) */ 680 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */ 681 __le32 TimeStamp; /* otherwise timestamp for FW internal use */ 682 } u; 683 __le32 Handle; /* FIB handle used for MSGU commnunication */ 684 u32 Previous; /* FW internal use */ 685 u32 Next; /* FW internal use */ 686 }; 687 688 struct hw_fib { 689 struct aac_fibhdr header; 690 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data 691 }; 692 693 /* 694 * FIB commands 695 */ 696 697 #define TestCommandResponse 1 698 #define TestAdapterCommand 2 699 /* 700 * Lowlevel and comm commands 701 */ 702 #define LastTestCommand 100 703 #define ReinitHostNormCommandQueue 101 704 #define ReinitHostHighCommandQueue 102 705 #define ReinitHostHighRespQueue 103 706 #define ReinitHostNormRespQueue 104 707 #define ReinitAdapNormCommandQueue 105 708 #define ReinitAdapHighCommandQueue 107 709 #define ReinitAdapHighRespQueue 108 710 #define ReinitAdapNormRespQueue 109 711 #define InterfaceShutdown 110 712 #define DmaCommandFib 120 713 #define StartProfile 121 714 #define TermProfile 122 715 #define SpeedTest 123 716 #define TakeABreakPt 124 717 #define RequestPerfData 125 718 #define SetInterruptDefTimer 126 719 #define SetInterruptDefCount 127 720 #define GetInterruptDefStatus 128 721 #define LastCommCommand 129 722 /* 723 * Filesystem commands 724 */ 725 #define NuFileSystem 300 726 #define UFS 301 727 #define HostFileSystem 302 728 #define LastFileSystemCommand 303 729 /* 730 * Container Commands 731 */ 732 #define ContainerCommand 500 733 #define ContainerCommand64 501 734 #define ContainerRawIo 502 735 #define ContainerRawIo2 503 736 /* 737 * Scsi Port commands (scsi passthrough) 738 */ 739 #define ScsiPortCommand 600 740 #define ScsiPortCommand64 601 741 /* 742 * Misc house keeping and generic adapter initiated commands 743 */ 744 #define AifRequest 700 745 #define CheckRevision 701 746 #define FsaHostShutdown 702 747 #define RequestAdapterInfo 703 748 #define IsAdapterPaused 704 749 #define SendHostTime 705 750 #define RequestSupplementAdapterInfo 706 751 #define LastMiscCommand 707 752 753 /* 754 * Commands that will target the failover level on the FSA adapter 755 */ 756 757 enum fib_xfer_state { 758 HostOwned = (1<<0), 759 AdapterOwned = (1<<1), 760 FibInitialized = (1<<2), 761 FibEmpty = (1<<3), 762 AllocatedFromPool = (1<<4), 763 SentFromHost = (1<<5), 764 SentFromAdapter = (1<<6), 765 ResponseExpected = (1<<7), 766 NoResponseExpected = (1<<8), 767 AdapterProcessed = (1<<9), 768 HostProcessed = (1<<10), 769 HighPriority = (1<<11), 770 NormalPriority = (1<<12), 771 Async = (1<<13), 772 AsyncIo = (1<<13), // rpbfix: remove with new regime 773 PageFileIo = (1<<14), // rpbfix: remove with new regime 774 ShutdownRequest = (1<<15), 775 LazyWrite = (1<<16), // rpbfix: remove with new regime 776 AdapterMicroFib = (1<<17), 777 BIOSFibPath = (1<<18), 778 FastResponseCapable = (1<<19), 779 ApiFib = (1<<20), /* Its an API Fib */ 780 /* PMC NEW COMM: There is no more AIF data pending */ 781 NoMoreAifDataAvailable = (1<<21) 782 }; 783 784 /* 785 * The following defines needs to be updated any time there is an 786 * incompatible change made to the aac_init structure. 787 */ 788 789 #define ADAPTER_INIT_STRUCT_REVISION 3 790 #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science 791 #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */ 792 #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */ 793 #define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor 794 795 union aac_init 796 { 797 struct _r7 { 798 __le32 init_struct_revision; 799 __le32 no_of_msix_vectors; 800 __le32 fsrev; 801 __le32 comm_header_address; 802 __le32 fast_io_comm_area_address; 803 __le32 adapter_fibs_physical_address; 804 __le32 adapter_fibs_virtual_address; 805 __le32 adapter_fibs_size; 806 __le32 adapter_fib_align; 807 __le32 printfbuf; 808 __le32 printfbufsiz; 809 /* number of 4k pages of host phys. mem. */ 810 __le32 host_phys_mem_pages; 811 /* number of seconds since 1970. */ 812 __le32 host_elapsed_seconds; 813 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */ 814 __le32 init_flags; /* flags for supported features */ 815 #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001 816 #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010 817 #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020 818 #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040 819 #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080 820 #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100 821 #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400 822 __le32 max_io_commands; /* max outstanding commands */ 823 __le32 max_io_size; /* largest I/O command */ 824 __le32 max_fib_size; /* largest FIB to adapter */ 825 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */ 826 __le32 max_num_aif; /* max number of aif */ 827 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */ 828 /* Host RRQ (response queue) for SRC */ 829 __le32 host_rrq_addr_low; 830 __le32 host_rrq_addr_high; 831 } r7; 832 struct _r8 { 833 /* ADAPTER_INIT_STRUCT_REVISION_8 */ 834 __le32 init_struct_revision; 835 __le32 rr_queue_count; 836 __le32 host_elapsed_seconds; /* number of secs since 1970. */ 837 __le32 init_flags; 838 __le32 max_io_size; /* largest I/O command */ 839 __le32 max_num_aif; /* max number of aif */ 840 __le32 reserved1; 841 __le32 reserved2; 842 struct _rrq { 843 __le32 host_addr_low; 844 __le32 host_addr_high; 845 __le16 msix_id; 846 __le16 element_count; 847 __le16 comp_thresh; 848 __le16 unused; 849 } rrq[1]; /* up to 64 RRQ addresses */ 850 } r8; 851 }; 852 853 enum aac_log_level { 854 LOG_AAC_INIT = 10, 855 LOG_AAC_INFORMATIONAL = 20, 856 LOG_AAC_WARNING = 30, 857 LOG_AAC_LOW_ERROR = 40, 858 LOG_AAC_MEDIUM_ERROR = 50, 859 LOG_AAC_HIGH_ERROR = 60, 860 LOG_AAC_PANIC = 70, 861 LOG_AAC_DEBUG = 80, 862 LOG_AAC_WINDBG_PRINT = 90 863 }; 864 865 #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b 866 #define FSAFS_NTC_FIB_CONTEXT 0x030c 867 868 struct aac_dev; 869 struct fib; 870 struct scsi_cmnd; 871 872 struct adapter_ops 873 { 874 /* Low level operations */ 875 void (*adapter_interrupt)(struct aac_dev *dev); 876 void (*adapter_notify)(struct aac_dev *dev, u32 event); 877 void (*adapter_disable_int)(struct aac_dev *dev); 878 void (*adapter_enable_int)(struct aac_dev *dev); 879 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4); 880 int (*adapter_check_health)(struct aac_dev *dev); 881 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type); 882 void (*adapter_start)(struct aac_dev *dev); 883 /* Transport operations */ 884 int (*adapter_ioremap)(struct aac_dev * dev, u32 size); 885 irq_handler_t adapter_intr; 886 /* Packet operations */ 887 int (*adapter_deliver)(struct fib * fib); 888 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba); 889 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count); 890 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua); 891 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd); 892 /* Administrative operations */ 893 int (*adapter_comm)(struct aac_dev * dev, int comm); 894 }; 895 896 /* 897 * Define which interrupt handler needs to be installed 898 */ 899 900 struct aac_driver_ident 901 { 902 int (*init)(struct aac_dev *dev); 903 char * name; 904 char * vname; 905 char * model; 906 u16 channels; 907 int quirks; 908 }; 909 /* 910 * Some adapter firmware needs communication memory 911 * below 2gig. This tells the init function to set the 912 * dma mask such that fib memory will be allocated where the 913 * adapter firmware can get to it. 914 */ 915 #define AAC_QUIRK_31BIT 0x0001 916 917 /* 918 * Some adapter firmware, when the raid card's cache is turned off, can not 919 * split up scatter gathers in order to deal with the limits of the 920 * underlying CHIM. This limit is 34 scatter gather elements. 921 */ 922 #define AAC_QUIRK_34SG 0x0002 923 924 /* 925 * This adapter is a slave (no Firmware) 926 */ 927 #define AAC_QUIRK_SLAVE 0x0004 928 929 /* 930 * This adapter is a master. 931 */ 932 #define AAC_QUIRK_MASTER 0x0008 933 934 /* 935 * Some adapter firmware perform poorly when it must split up scatter gathers 936 * in order to deal with the limits of the underlying CHIM. This limit in this 937 * class of adapters is 17 scatter gather elements. 938 */ 939 #define AAC_QUIRK_17SG 0x0010 940 941 /* 942 * Some adapter firmware does not support 64 bit scsi passthrough 943 * commands. 944 */ 945 #define AAC_QUIRK_SCSI_32 0x0020 946 947 /* 948 * SRC based adapters support the AifReqEvent functions 949 */ 950 #define AAC_QUIRK_SRC 0x0040 951 952 /* 953 * The adapter interface specs all queues to be located in the same 954 * physically contiguous block. The host structure that defines the 955 * commuication queues will assume they are each a separate physically 956 * contiguous memory region that will support them all being one big 957 * contiguous block. 958 * There is a command and response queue for each level and direction of 959 * commuication. These regions are accessed by both the host and adapter. 960 */ 961 962 struct aac_queue { 963 u64 logical; /*address we give the adapter */ 964 struct aac_entry *base; /*system virtual address */ 965 struct aac_qhdr headers; /*producer,consumer q headers*/ 966 u32 entries; /*Number of queue entries */ 967 wait_queue_head_t qfull; /*Event to wait on if q full */ 968 wait_queue_head_t cmdready; /*Cmd ready from the adapter */ 969 /* This is only valid for adapter to host command queues. */ 970 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */ 971 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */ 972 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */ 973 /* only valid for command queues which receive entries from the adapter. */ 974 /* Number of entries on outstanding queue. */ 975 atomic_t numpending; 976 struct aac_dev * dev; /* Back pointer to adapter structure */ 977 }; 978 979 /* 980 * Message queues. The order here is important, see also the 981 * queue type ordering 982 */ 983 984 struct aac_queue_block 985 { 986 struct aac_queue queue[8]; 987 }; 988 989 /* 990 * SaP1 Message Unit Registers 991 */ 992 993 struct sa_drawbridge_CSR { 994 /* Offset | Name */ 995 __le32 reserved[10]; /* 00h-27h | Reserved */ 996 u8 LUT_Offset; /* 28h | Lookup Table Offset */ 997 u8 reserved1[3]; /* 29h-2bh | Reserved */ 998 __le32 LUT_Data; /* 2ch | Looup Table Data */ 999 __le32 reserved2[26]; /* 30h-97h | Reserved */ 1000 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */ 1001 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */ 1002 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */ 1003 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */ 1004 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */ 1005 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */ 1006 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */ 1007 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */ 1008 __le32 MAILBOX0; /* a8h | Scratchpad 0 */ 1009 __le32 MAILBOX1; /* ach | Scratchpad 1 */ 1010 __le32 MAILBOX2; /* b0h | Scratchpad 2 */ 1011 __le32 MAILBOX3; /* b4h | Scratchpad 3 */ 1012 __le32 MAILBOX4; /* b8h | Scratchpad 4 */ 1013 __le32 MAILBOX5; /* bch | Scratchpad 5 */ 1014 __le32 MAILBOX6; /* c0h | Scratchpad 6 */ 1015 __le32 MAILBOX7; /* c4h | Scratchpad 7 */ 1016 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */ 1017 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */ 1018 __le32 reserved3[12]; /* d0h-ffh | reserved */ 1019 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */ 1020 }; 1021 1022 #define Mailbox0 SaDbCSR.MAILBOX0 1023 #define Mailbox1 SaDbCSR.MAILBOX1 1024 #define Mailbox2 SaDbCSR.MAILBOX2 1025 #define Mailbox3 SaDbCSR.MAILBOX3 1026 #define Mailbox4 SaDbCSR.MAILBOX4 1027 #define Mailbox5 SaDbCSR.MAILBOX5 1028 #define Mailbox6 SaDbCSR.MAILBOX6 1029 #define Mailbox7 SaDbCSR.MAILBOX7 1030 1031 #define DoorbellReg_p SaDbCSR.PRISETIRQ 1032 #define DoorbellReg_s SaDbCSR.SECSETIRQ 1033 #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ 1034 1035 1036 #define DOORBELL_0 0x0001 1037 #define DOORBELL_1 0x0002 1038 #define DOORBELL_2 0x0004 1039 #define DOORBELL_3 0x0008 1040 #define DOORBELL_4 0x0010 1041 #define DOORBELL_5 0x0020 1042 #define DOORBELL_6 0x0040 1043 1044 1045 #define PrintfReady DOORBELL_5 1046 #define PrintfDone DOORBELL_5 1047 1048 struct sa_registers { 1049 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */ 1050 }; 1051 1052 1053 #define SA_INIT_NUM_MSIXVECTORS 1 1054 #define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS 1055 1056 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 1057 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) 1058 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) 1059 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) 1060 1061 /* 1062 * Rx Message Unit Registers 1063 */ 1064 1065 struct rx_mu_registers { 1066 /* Local | PCI*| Name */ 1067 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */ 1068 __le32 reserved0; /* 1304h | 04h | Reserved */ 1069 __le32 AWR; /* 1308h | 08h | APIC Window Register */ 1070 __le32 reserved1; /* 130Ch | 0Ch | Reserved */ 1071 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */ 1072 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */ 1073 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */ 1074 __le32 IISR; /* 1324h | 24h | Inbound Interrupt 1075 Status Register */ 1076 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt 1077 Mask Register */ 1078 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */ 1079 __le32 OISR; /* 1330h | 30h | Outbound Interrupt 1080 Status Register */ 1081 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt 1082 Mask Register */ 1083 __le32 reserved2; /* 1338h | 38h | Reserved */ 1084 __le32 reserved3; /* 133Ch | 3Ch | Reserved */ 1085 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */ 1086 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */ 1087 /* * Must access through ATU Inbound 1088 Translation Window */ 1089 }; 1090 1091 struct rx_inbound { 1092 __le32 Mailbox[8]; 1093 }; 1094 1095 #define INBOUNDDOORBELL_0 0x00000001 1096 #define INBOUNDDOORBELL_1 0x00000002 1097 #define INBOUNDDOORBELL_2 0x00000004 1098 #define INBOUNDDOORBELL_3 0x00000008 1099 #define INBOUNDDOORBELL_4 0x00000010 1100 #define INBOUNDDOORBELL_5 0x00000020 1101 #define INBOUNDDOORBELL_6 0x00000040 1102 1103 #define OUTBOUNDDOORBELL_0 0x00000001 1104 #define OUTBOUNDDOORBELL_1 0x00000002 1105 #define OUTBOUNDDOORBELL_2 0x00000004 1106 #define OUTBOUNDDOORBELL_3 0x00000008 1107 #define OUTBOUNDDOORBELL_4 0x00000010 1108 1109 #define InboundDoorbellReg MUnit.IDR 1110 #define OutboundDoorbellReg MUnit.ODR 1111 1112 struct rx_registers { 1113 struct rx_mu_registers MUnit; /* 1300h - 1347h */ 1114 __le32 reserved1[2]; /* 1348h - 134ch */ 1115 struct rx_inbound IndexRegs; 1116 }; 1117 1118 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) 1119 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) 1120 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) 1121 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) 1122 1123 /* 1124 * Rkt Message Unit Registers (same as Rx, except a larger reserve region) 1125 */ 1126 1127 #define rkt_mu_registers rx_mu_registers 1128 #define rkt_inbound rx_inbound 1129 1130 struct rkt_registers { 1131 struct rkt_mu_registers MUnit; /* 1300h - 1347h */ 1132 __le32 reserved1[1006]; /* 1348h - 22fch */ 1133 struct rkt_inbound IndexRegs; /* 2300h - */ 1134 }; 1135 1136 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) 1137 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) 1138 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR)) 1139 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR)) 1140 1141 /* 1142 * PMC SRC message unit registers 1143 */ 1144 1145 #define src_inbound rx_inbound 1146 1147 struct src_mu_registers { 1148 /* PCI*| Name */ 1149 __le32 reserved0[6]; /* 00h | Reserved */ 1150 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */ 1151 __le32 IDR; /* 20h | Inbound Doorbell Register */ 1152 __le32 IISR; /* 24h | Inbound Int. Status Register */ 1153 __le32 reserved1[3]; /* 28h | Reserved */ 1154 __le32 OIMR; /* 34h | Outbound Int. Mask Register */ 1155 __le32 reserved2[25]; /* 38h | Reserved */ 1156 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */ 1157 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */ 1158 __le32 reserved3[3]; /* a4h | Reserved */ 1159 __le32 SCR0; /* b0h | Scratchpad 0 */ 1160 __le32 reserved4[2]; /* b4h | Reserved */ 1161 __le32 OMR; /* bch | Outbound Message Register */ 1162 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */ 1163 __le32 IQ_H; /* c4h | Inbound Queue (High address) */ 1164 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */ 1165 __le32 reserved5; /* cch | Reserved */ 1166 __le32 IQN_L; /* d0h | Inbound (native cmd) low */ 1167 __le32 IQN_H; /* d4h | Inbound (native cmd) high */ 1168 }; 1169 1170 struct src_registers { 1171 struct src_mu_registers MUnit; /* 00h - cbh */ 1172 union { 1173 struct { 1174 __le32 reserved1[130786]; /* d8h - 7fc5fh */ 1175 struct src_inbound IndexRegs; /* 7fc60h */ 1176 } tupelo; 1177 struct { 1178 __le32 reserved1[970]; /* d8h - fffh */ 1179 struct src_inbound IndexRegs; /* 1000h */ 1180 } denali; 1181 } u; 1182 }; 1183 1184 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR)) 1185 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR)) 1186 #define src_writeb(AEP, CSR, value) writeb(value, \ 1187 &((AEP)->regs.src.bar0->CSR)) 1188 #define src_writel(AEP, CSR, value) writel(value, \ 1189 &((AEP)->regs.src.bar0->CSR)) 1190 #if defined(writeq) 1191 #define src_writeq(AEP, CSR, value) writeq(value, \ 1192 &((AEP)->regs.src.bar0->CSR)) 1193 #endif 1194 1195 #define SRC_ODR_SHIFT 12 1196 #define SRC_IDR_SHIFT 9 1197 1198 typedef void (*fib_callback)(void *ctxt, struct fib *fibctx); 1199 1200 struct aac_fib_context { 1201 s16 type; // used for verification of structure 1202 s16 size; 1203 u32 unique; // unique value representing this context 1204 ulong jiffies; // used for cleanup - dmb changed to ulong 1205 struct list_head next; // used to link context's into a linked list 1206 struct semaphore wait_sem; // this is used to wait for the next fib to arrive. 1207 int wait; // Set to true when thread is in WaitForSingleObject 1208 unsigned long count; // total number of FIBs on FibList 1209 struct list_head fib_list; // this holds fibs and their attachd hw_fibs 1210 }; 1211 1212 struct sense_data { 1213 u8 error_code; /* 70h (current errors), 71h(deferred errors) */ 1214 u8 valid:1; /* A valid bit of one indicates that the information */ 1215 /* field contains valid information as defined in the 1216 * SCSI-2 Standard. 1217 */ 1218 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */ 1219 u8 sense_key:4; /* Sense Key */ 1220 u8 reserved:1; 1221 u8 ILI:1; /* Incorrect Length Indicator */ 1222 u8 EOM:1; /* End Of Medium - reserved for random access devices */ 1223 u8 filemark:1; /* Filemark - reserved for random access devices */ 1224 1225 u8 information[4]; /* for direct-access devices, contains the unsigned 1226 * logical block address or residue associated with 1227 * the sense key 1228 */ 1229 u8 add_sense_len; /* number of additional sense bytes to follow this field */ 1230 u8 cmnd_info[4]; /* not used */ 1231 u8 ASC; /* Additional Sense Code */ 1232 u8 ASCQ; /* Additional Sense Code Qualifier */ 1233 u8 FRUC; /* Field Replaceable Unit Code - not used */ 1234 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data 1235 * was in error 1236 */ 1237 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that 1238 * the bit_ptr field has valid value 1239 */ 1240 u8 reserved2:2; 1241 u8 CD:1; /* command data bit: 1- illegal parameter in CDB. 1242 * 0- illegal parameter in data. 1243 */ 1244 u8 SKSV:1; 1245 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */ 1246 }; 1247 1248 struct fsa_dev_info { 1249 u64 last; 1250 u64 size; 1251 u32 type; 1252 u32 config_waiting_on; 1253 unsigned long config_waiting_stamp; 1254 u16 queue_depth; 1255 u8 config_needed; 1256 u8 valid; 1257 u8 ro; 1258 u8 locked; 1259 u8 deleted; 1260 char devname[8]; 1261 struct sense_data sense_data; 1262 u32 block_size; 1263 u8 identifier[16]; 1264 }; 1265 1266 struct fib { 1267 void *next; /* this is used by the allocator */ 1268 s16 type; 1269 s16 size; 1270 /* 1271 * The Adapter that this I/O is destined for. 1272 */ 1273 struct aac_dev *dev; 1274 /* 1275 * This is the event the sendfib routine will wait on if the 1276 * caller did not pass one and this is synch io. 1277 */ 1278 struct semaphore event_wait; 1279 spinlock_t event_lock; 1280 1281 u32 done; /* gets set to 1 when fib is complete */ 1282 fib_callback callback; 1283 void *callback_data; 1284 u32 flags; // u32 dmb was ulong 1285 /* 1286 * And for the internal issue/reply queues (we may be able 1287 * to merge these two) 1288 */ 1289 struct list_head fiblink; 1290 void *data; 1291 u32 vector_no; 1292 struct hw_fib *hw_fib_va; /* also used for native */ 1293 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/ 1294 dma_addr_t hw_sgl_pa; /* extra sgl for native */ 1295 dma_addr_t hw_error_pa; /* error buffer for native */ 1296 u32 hbacmd_size; /* cmd size for native */ 1297 }; 1298 1299 #define AAC_INIT 0 1300 #define AAC_RESCAN 1 1301 1302 #define AAC_DEVTYPE_RAID_MEMBER 1 1303 #define AAC_DEVTYPE_ARC_RAW 2 1304 #define AAC_DEVTYPE_NATIVE_RAW 3 1305 #define AAC_EXPOSE_DISK 0 1306 #define AAC_HIDE_DISK 3 1307 1308 struct aac_hba_map_info { 1309 __le32 rmw_nexus; /* nexus for native HBA devices */ 1310 u8 devtype; /* device type */ 1311 u8 new_devtype; 1312 u8 reset_state; /* 0 - no reset, 1..x - */ 1313 /* after xth TM LUN reset */ 1314 u16 qd_limit; 1315 u8 expose; /*checks if to expose or not*/ 1316 }; 1317 1318 /* 1319 * Adapter Information Block 1320 * 1321 * This is returned by the RequestAdapterInfo block 1322 */ 1323 1324 struct aac_adapter_info 1325 { 1326 __le32 platform; 1327 __le32 cpu; 1328 __le32 subcpu; 1329 __le32 clock; 1330 __le32 execmem; 1331 __le32 buffermem; 1332 __le32 totalmem; 1333 __le32 kernelrev; 1334 __le32 kernelbuild; 1335 __le32 monitorrev; 1336 __le32 monitorbuild; 1337 __le32 hwrev; 1338 __le32 hwbuild; 1339 __le32 biosrev; 1340 __le32 biosbuild; 1341 __le32 cluster; 1342 __le32 clusterchannelmask; 1343 __le32 serial[2]; 1344 __le32 battery; 1345 __le32 options; 1346 __le32 OEM; 1347 }; 1348 1349 struct aac_supplement_adapter_info 1350 { 1351 u8 AdapterTypeText[17+1]; 1352 u8 Pad[2]; 1353 __le32 FlashMemoryByteSize; 1354 __le32 FlashImageId; 1355 __le32 MaxNumberPorts; 1356 __le32 Version; 1357 __le32 FeatureBits; 1358 u8 SlotNumber; 1359 u8 ReservedPad0[3]; 1360 u8 BuildDate[12]; 1361 __le32 CurrentNumberPorts; 1362 struct { 1363 u8 AssemblyPn[8]; 1364 u8 FruPn[8]; 1365 u8 BatteryFruPn[8]; 1366 u8 EcVersionString[8]; 1367 u8 Tsid[12]; 1368 } VpdInfo; 1369 __le32 FlashFirmwareRevision; 1370 __le32 FlashFirmwareBuild; 1371 __le32 RaidTypeMorphOptions; 1372 __le32 FlashFirmwareBootRevision; 1373 __le32 FlashFirmwareBootBuild; 1374 u8 MfgPcbaSerialNo[12]; 1375 u8 MfgWWNName[8]; 1376 __le32 SupportedOptions2; 1377 __le32 StructExpansion; 1378 /* StructExpansion == 1 */ 1379 __le32 FeatureBits3; 1380 __le32 SupportedPerformanceModes; 1381 u8 HostBusType; /* uses HOST_BUS_TYPE_xxx defines */ 1382 u8 HostBusWidth; /* actual width in bits or links */ 1383 u16 HostBusSpeed; /* actual bus speed/link rate in MHz */ 1384 u8 MaxRRCDrives; /* max. number of ITP-RRC drives/pool */ 1385 u8 MaxDiskXtasks; /* max. possible num of DiskX Tasks */ 1386 1387 u8 CpldVerLoaded; 1388 u8 CpldVerInFlash; 1389 1390 __le64 MaxRRCCapacity; 1391 __le32 CompiledMaxHistLogLevel; 1392 u8 CustomBoardName[12]; 1393 u16 SupportedCntlrMode; /* identify supported controller mode */ 1394 u16 ReservedForFuture16; 1395 __le32 SupportedOptions3; /* reserved for future options */ 1396 1397 __le16 VirtDeviceBus; /* virt. SCSI device for Thor */ 1398 __le16 VirtDeviceTarget; 1399 __le16 VirtDeviceLUN; 1400 __le16 Unused; 1401 __le32 ReservedForFutureGrowth[68]; 1402 1403 }; 1404 #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010) 1405 #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000) 1406 /* SupportedOptions2 */ 1407 #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001) 1408 #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002) 1409 #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004) 1410 #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000) 1411 /* 4KB sector size */ 1412 #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000) 1413 /* 240 simple volume support */ 1414 #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000) 1415 #define AAC_SIS_VERSION_V3 3 1416 #define AAC_SIS_SLOT_UNKNOWN 0xFF 1417 1418 #define GetBusInfo 0x00000009 1419 struct aac_bus_info { 1420 __le32 Command; /* VM_Ioctl */ 1421 __le32 ObjType; /* FT_DRIVE */ 1422 __le32 MethodId; /* 1 = SCSI Layer */ 1423 __le32 ObjectId; /* Handle */ 1424 __le32 CtlCmd; /* GetBusInfo */ 1425 }; 1426 1427 struct aac_bus_info_response { 1428 __le32 Status; /* ST_OK */ 1429 __le32 ObjType; 1430 __le32 MethodId; /* unused */ 1431 __le32 ObjectId; /* unused */ 1432 __le32 CtlCmd; /* unused */ 1433 __le32 ProbeComplete; 1434 __le32 BusCount; 1435 __le32 TargetsPerBus; 1436 u8 InitiatorBusId[10]; 1437 u8 BusValid[10]; 1438 }; 1439 1440 /* 1441 * Battery platforms 1442 */ 1443 #define AAC_BAT_REQ_PRESENT (1) 1444 #define AAC_BAT_REQ_NOTPRESENT (2) 1445 #define AAC_BAT_OPT_PRESENT (3) 1446 #define AAC_BAT_OPT_NOTPRESENT (4) 1447 #define AAC_BAT_NOT_SUPPORTED (5) 1448 /* 1449 * cpu types 1450 */ 1451 #define AAC_CPU_SIMULATOR (1) 1452 #define AAC_CPU_I960 (2) 1453 #define AAC_CPU_STRONGARM (3) 1454 1455 /* 1456 * Supported Options 1457 */ 1458 #define AAC_OPT_SNAPSHOT cpu_to_le32(1) 1459 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1) 1460 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2) 1461 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3) 1462 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4) 1463 #define AAC_OPT_RAID50 cpu_to_le32(1<<5) 1464 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6) 1465 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7) 1466 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8) 1467 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9) 1468 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10) 1469 #define AAC_OPT_ALARM cpu_to_le32(1<<11) 1470 #define AAC_OPT_NONDASD cpu_to_le32(1<<12) 1471 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13) 1472 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14) 1473 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16) 1474 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17) 1475 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18) 1476 #define AAC_OPT_EXTENDED cpu_to_le32(1<<23) 1477 #define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25) 1478 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28) 1479 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29) 1480 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30) 1481 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31) 1482 1483 #define AAC_COMM_PRODUCER 0 1484 #define AAC_COMM_MESSAGE 1 1485 #define AAC_COMM_MESSAGE_TYPE1 3 1486 #define AAC_COMM_MESSAGE_TYPE2 4 1487 #define AAC_COMM_MESSAGE_TYPE3 5 1488 1489 #define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1) 1490 1491 /* MSIX context */ 1492 struct aac_msix_ctx { 1493 int vector_no; 1494 struct aac_dev *dev; 1495 }; 1496 1497 struct aac_dev 1498 { 1499 struct list_head entry; 1500 const char *name; 1501 int id; 1502 1503 /* 1504 * negotiated FIB settings 1505 */ 1506 unsigned int max_fib_size; 1507 unsigned int sg_tablesize; 1508 unsigned int max_num_aif; 1509 1510 unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */ 1511 1512 /* 1513 * Map for 128 fib objects (64k) 1514 */ 1515 dma_addr_t hw_fib_pa; /* also used for native cmd */ 1516 struct hw_fib *hw_fib_va; /* also used for native cmd */ 1517 struct hw_fib *aif_base_va; 1518 /* 1519 * Fib Headers 1520 */ 1521 struct fib *fibs; 1522 1523 struct fib *free_fib; 1524 spinlock_t fib_lock; 1525 1526 struct mutex ioctl_mutex; 1527 struct aac_queue_block *queues; 1528 /* 1529 * The user API will use an IOCTL to register itself to receive 1530 * FIBs from the adapter. The following list is used to keep 1531 * track of all the threads that have requested these FIBs. The 1532 * mutex is used to synchronize access to all data associated 1533 * with the adapter fibs. 1534 */ 1535 struct list_head fib_list; 1536 1537 struct adapter_ops a_ops; 1538 unsigned long fsrev; /* Main driver's revision number */ 1539 1540 resource_size_t base_start; /* main IO base */ 1541 resource_size_t dbg_base; /* address of UART 1542 * debug buffer */ 1543 1544 resource_size_t base_size, dbg_size; /* Size of 1545 * mapped in region */ 1546 /* 1547 * Holds initialization info 1548 * to communicate with adapter 1549 */ 1550 union aac_init *init; 1551 dma_addr_t init_pa; /* Holds physical address of the init struct */ 1552 /* response queue (if AAC_COMM_MESSAGE_TYPE1) */ 1553 __le32 *host_rrq; 1554 dma_addr_t host_rrq_pa; /* phys. address */ 1555 /* index into rrq buffer */ 1556 u32 host_rrq_idx[AAC_MAX_MSIX]; 1557 atomic_t rrq_outstanding[AAC_MAX_MSIX]; 1558 u32 fibs_pushed_no; 1559 struct pci_dev *pdev; /* Our PCI interface */ 1560 /* pointer to buffer used for printf's from the adapter */ 1561 void *printfbuf; 1562 void *comm_addr; /* Base address of Comm area */ 1563 dma_addr_t comm_phys; /* Physical Address of Comm area */ 1564 size_t comm_size; 1565 1566 struct Scsi_Host *scsi_host_ptr; 1567 int maximum_num_containers; 1568 int maximum_num_physicals; 1569 int maximum_num_channels; 1570 struct fsa_dev_info *fsa_dev; 1571 struct task_struct *thread; 1572 int cardtype; 1573 /* 1574 *This lock will protect the two 32-bit 1575 *writes to the Inbound Queue 1576 */ 1577 spinlock_t iq_lock; 1578 1579 /* 1580 * The following is the device specific extension. 1581 */ 1582 #ifndef AAC_MIN_FOOTPRINT_SIZE 1583 # define AAC_MIN_FOOTPRINT_SIZE 8192 1584 # define AAC_MIN_SRC_BAR0_SIZE 0x400000 1585 # define AAC_MIN_SRC_BAR1_SIZE 0x800 1586 # define AAC_MIN_SRCV_BAR0_SIZE 0x100000 1587 # define AAC_MIN_SRCV_BAR1_SIZE 0x400 1588 #endif 1589 union 1590 { 1591 struct sa_registers __iomem *sa; 1592 struct rx_registers __iomem *rx; 1593 struct rkt_registers __iomem *rkt; 1594 struct { 1595 struct src_registers __iomem *bar0; 1596 char __iomem *bar1; 1597 } src; 1598 } regs; 1599 volatile void __iomem *base, *dbg_base_mapped; 1600 volatile struct rx_inbound __iomem *IndexRegs; 1601 u32 OIMR; /* Mask Register Cache */ 1602 /* 1603 * AIF thread states 1604 */ 1605 u32 aif_thread; 1606 struct aac_adapter_info adapter_info; 1607 struct aac_supplement_adapter_info supplement_adapter_info; 1608 /* These are in adapter info but they are in the io flow so 1609 * lets break them out so we don't have to do an AND to check them 1610 */ 1611 u8 nondasd_support; 1612 u8 jbod; 1613 u8 cache_protected; 1614 u8 dac_support; 1615 u8 needs_dac; 1616 u8 raid_scsi_mode; 1617 u8 comm_interface; 1618 u8 raw_io_interface; 1619 u8 raw_io_64; 1620 u8 printf_enabled; 1621 u8 in_reset; 1622 u8 msi; 1623 u8 sa_firmware; 1624 int management_fib_count; 1625 spinlock_t manage_lock; 1626 spinlock_t sync_lock; 1627 int sync_mode; 1628 struct fib *sync_fib; 1629 struct list_head sync_fib_list; 1630 u32 doorbell_mask; 1631 u32 max_msix; /* max. MSI-X vectors */ 1632 u32 vector_cap; /* MSI-X vector capab.*/ 1633 int msi_enabled; /* MSI/MSI-X enabled */ 1634 atomic_t msix_counter; 1635 struct msix_entry msixentry[AAC_MAX_MSIX]; 1636 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */ 1637 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS]; 1638 u8 adapter_shutdown; 1639 u32 handle_pci_error; 1640 }; 1641 1642 #define aac_adapter_interrupt(dev) \ 1643 (dev)->a_ops.adapter_interrupt(dev) 1644 1645 #define aac_adapter_notify(dev, event) \ 1646 (dev)->a_ops.adapter_notify(dev, event) 1647 1648 #define aac_adapter_disable_int(dev) \ 1649 (dev)->a_ops.adapter_disable_int(dev) 1650 1651 #define aac_adapter_enable_int(dev) \ 1652 (dev)->a_ops.adapter_enable_int(dev) 1653 1654 #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \ 1655 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) 1656 1657 #define aac_adapter_check_health(dev) \ 1658 (dev)->a_ops.adapter_check_health(dev) 1659 1660 #define aac_adapter_restart(dev, bled, reset_type) \ 1661 ((dev)->a_ops.adapter_restart(dev, bled, reset_type)) 1662 1663 #define aac_adapter_start(dev) \ 1664 ((dev)->a_ops.adapter_start(dev)) 1665 1666 #define aac_adapter_ioremap(dev, size) \ 1667 (dev)->a_ops.adapter_ioremap(dev, size) 1668 1669 #define aac_adapter_deliver(fib) \ 1670 ((fib)->dev)->a_ops.adapter_deliver(fib) 1671 1672 #define aac_adapter_bounds(dev,cmd,lba) \ 1673 dev->a_ops.adapter_bounds(dev,cmd,lba) 1674 1675 #define aac_adapter_read(fib,cmd,lba,count) \ 1676 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count) 1677 1678 #define aac_adapter_write(fib,cmd,lba,count,fua) \ 1679 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua) 1680 1681 #define aac_adapter_scsi(fib,cmd) \ 1682 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd) 1683 1684 #define aac_adapter_comm(dev,comm) \ 1685 (dev)->a_ops.adapter_comm(dev, comm) 1686 1687 #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001) 1688 #define FIB_CONTEXT_FLAG (0x00000002) 1689 #define FIB_CONTEXT_FLAG_WAIT (0x00000004) 1690 #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008) 1691 #define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010) 1692 #define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020) 1693 1694 /* 1695 * Define the command values 1696 */ 1697 1698 #define Null 0 1699 #define GetAttributes 1 1700 #define SetAttributes 2 1701 #define Lookup 3 1702 #define ReadLink 4 1703 #define Read 5 1704 #define Write 6 1705 #define Create 7 1706 #define MakeDirectory 8 1707 #define SymbolicLink 9 1708 #define MakeNode 10 1709 #define Removex 11 1710 #define RemoveDirectoryx 12 1711 #define Rename 13 1712 #define Link 14 1713 #define ReadDirectory 15 1714 #define ReadDirectoryPlus 16 1715 #define FileSystemStatus 17 1716 #define FileSystemInfo 18 1717 #define PathConfigure 19 1718 #define Commit 20 1719 #define Mount 21 1720 #define UnMount 22 1721 #define Newfs 23 1722 #define FsCheck 24 1723 #define FsSync 25 1724 #define SimReadWrite 26 1725 #define SetFileSystemStatus 27 1726 #define BlockRead 28 1727 #define BlockWrite 29 1728 #define NvramIoctl 30 1729 #define FsSyncWait 31 1730 #define ClearArchiveBit 32 1731 #define SetAcl 33 1732 #define GetAcl 34 1733 #define AssignAcl 35 1734 #define FaultInsertion 36 /* Fault Insertion Command */ 1735 #define CrazyCache 37 /* Crazycache */ 1736 1737 #define MAX_FSACOMMAND_NUM 38 1738 1739 1740 /* 1741 * Define the status returns. These are very unixlike although 1742 * most are not in fact used 1743 */ 1744 1745 #define ST_OK 0 1746 #define ST_PERM 1 1747 #define ST_NOENT 2 1748 #define ST_IO 5 1749 #define ST_NXIO 6 1750 #define ST_E2BIG 7 1751 #define ST_MEDERR 8 1752 #define ST_ACCES 13 1753 #define ST_EXIST 17 1754 #define ST_XDEV 18 1755 #define ST_NODEV 19 1756 #define ST_NOTDIR 20 1757 #define ST_ISDIR 21 1758 #define ST_INVAL 22 1759 #define ST_FBIG 27 1760 #define ST_NOSPC 28 1761 #define ST_ROFS 30 1762 #define ST_MLINK 31 1763 #define ST_WOULDBLOCK 35 1764 #define ST_NAMETOOLONG 63 1765 #define ST_NOTEMPTY 66 1766 #define ST_DQUOT 69 1767 #define ST_STALE 70 1768 #define ST_REMOTE 71 1769 #define ST_NOT_READY 72 1770 #define ST_BADHANDLE 10001 1771 #define ST_NOT_SYNC 10002 1772 #define ST_BAD_COOKIE 10003 1773 #define ST_NOTSUPP 10004 1774 #define ST_TOOSMALL 10005 1775 #define ST_SERVERFAULT 10006 1776 #define ST_BADTYPE 10007 1777 #define ST_JUKEBOX 10008 1778 #define ST_NOTMOUNTED 10009 1779 #define ST_MAINTMODE 10010 1780 #define ST_STALEACL 10011 1781 1782 /* 1783 * On writes how does the client want the data written. 1784 */ 1785 1786 #define CACHE_CSTABLE 1 1787 #define CACHE_UNSTABLE 2 1788 1789 /* 1790 * Lets the client know at which level the data was committed on 1791 * a write request 1792 */ 1793 1794 #define CMFILE_SYNCH_NVRAM 1 1795 #define CMDATA_SYNCH_NVRAM 2 1796 #define CMFILE_SYNCH 3 1797 #define CMDATA_SYNCH 4 1798 #define CMUNSTABLE 5 1799 1800 #define RIO_TYPE_WRITE 0x0000 1801 #define RIO_TYPE_READ 0x0001 1802 #define RIO_SUREWRITE 0x0008 1803 1804 #define RIO2_IO_TYPE 0x0003 1805 #define RIO2_IO_TYPE_WRITE 0x0000 1806 #define RIO2_IO_TYPE_READ 0x0001 1807 #define RIO2_IO_TYPE_VERIFY 0x0002 1808 #define RIO2_IO_ERROR 0x0004 1809 #define RIO2_IO_SUREWRITE 0x0008 1810 #define RIO2_SGL_CONFORMANT 0x0010 1811 #define RIO2_SG_FORMAT 0xF000 1812 #define RIO2_SG_FORMAT_ARC 0x0000 1813 #define RIO2_SG_FORMAT_SRL 0x1000 1814 #define RIO2_SG_FORMAT_IEEE1212 0x2000 1815 1816 struct aac_read 1817 { 1818 __le32 command; 1819 __le32 cid; 1820 __le32 block; 1821 __le32 count; 1822 struct sgmap sg; // Must be last in struct because it is variable 1823 }; 1824 1825 struct aac_read64 1826 { 1827 __le32 command; 1828 __le16 cid; 1829 __le16 sector_count; 1830 __le32 block; 1831 __le16 pad; 1832 __le16 flags; 1833 struct sgmap64 sg; // Must be last in struct because it is variable 1834 }; 1835 1836 struct aac_read_reply 1837 { 1838 __le32 status; 1839 __le32 count; 1840 }; 1841 1842 struct aac_write 1843 { 1844 __le32 command; 1845 __le32 cid; 1846 __le32 block; 1847 __le32 count; 1848 __le32 stable; // Not used 1849 struct sgmap sg; // Must be last in struct because it is variable 1850 }; 1851 1852 struct aac_write64 1853 { 1854 __le32 command; 1855 __le16 cid; 1856 __le16 sector_count; 1857 __le32 block; 1858 __le16 pad; 1859 __le16 flags; 1860 struct sgmap64 sg; // Must be last in struct because it is variable 1861 }; 1862 struct aac_write_reply 1863 { 1864 __le32 status; 1865 __le32 count; 1866 __le32 committed; 1867 }; 1868 1869 struct aac_raw_io 1870 { 1871 __le32 block[2]; 1872 __le32 count; 1873 __le16 cid; 1874 __le16 flags; /* 00 W, 01 R */ 1875 __le16 bpTotal; /* reserved for F/W use */ 1876 __le16 bpComplete; /* reserved for F/W use */ 1877 struct sgmapraw sg; 1878 }; 1879 1880 struct aac_raw_io2 { 1881 __le32 blockLow; 1882 __le32 blockHigh; 1883 __le32 byteCount; 1884 __le16 cid; 1885 __le16 flags; /* RIO2 flags */ 1886 __le32 sgeFirstSize; /* size of first sge el. */ 1887 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */ 1888 u8 sgeCnt; /* only 8 bits required */ 1889 u8 bpTotal; /* reserved for F/W use */ 1890 u8 bpComplete; /* reserved for F/W use */ 1891 u8 sgeFirstIndex; /* reserved for F/W use */ 1892 u8 unused[4]; 1893 struct sge_ieee1212 sge[1]; 1894 }; 1895 1896 #define CT_FLUSH_CACHE 129 1897 struct aac_synchronize { 1898 __le32 command; /* VM_ContainerConfig */ 1899 __le32 type; /* CT_FLUSH_CACHE */ 1900 __le32 cid; 1901 __le32 parm1; 1902 __le32 parm2; 1903 __le32 parm3; 1904 __le32 parm4; 1905 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */ 1906 }; 1907 1908 struct aac_synchronize_reply { 1909 __le32 dummy0; 1910 __le32 dummy1; 1911 __le32 status; /* CT_OK */ 1912 __le32 parm1; 1913 __le32 parm2; 1914 __le32 parm3; 1915 __le32 parm4; 1916 __le32 parm5; 1917 u8 data[16]; 1918 }; 1919 1920 #define CT_POWER_MANAGEMENT 245 1921 #define CT_PM_START_UNIT 2 1922 #define CT_PM_STOP_UNIT 3 1923 #define CT_PM_UNIT_IMMEDIATE 1 1924 struct aac_power_management { 1925 __le32 command; /* VM_ContainerConfig */ 1926 __le32 type; /* CT_POWER_MANAGEMENT */ 1927 __le32 sub; /* CT_PM_* */ 1928 __le32 cid; 1929 __le32 parm; /* CT_PM_sub_* */ 1930 }; 1931 1932 #define CT_PAUSE_IO 65 1933 #define CT_RELEASE_IO 66 1934 struct aac_pause { 1935 __le32 command; /* VM_ContainerConfig */ 1936 __le32 type; /* CT_PAUSE_IO */ 1937 __le32 timeout; /* 10ms ticks */ 1938 __le32 min; 1939 __le32 noRescan; 1940 __le32 parm3; 1941 __le32 parm4; 1942 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */ 1943 }; 1944 1945 struct aac_srb 1946 { 1947 __le32 function; 1948 __le32 channel; 1949 __le32 id; 1950 __le32 lun; 1951 __le32 timeout; 1952 __le32 flags; 1953 __le32 count; // Data xfer size 1954 __le32 retry_limit; 1955 __le32 cdb_size; 1956 u8 cdb[16]; 1957 struct sgmap sg; 1958 }; 1959 1960 /* 1961 * This and associated data structs are used by the 1962 * ioctl caller and are in cpu order. 1963 */ 1964 struct user_aac_srb 1965 { 1966 u32 function; 1967 u32 channel; 1968 u32 id; 1969 u32 lun; 1970 u32 timeout; 1971 u32 flags; 1972 u32 count; // Data xfer size 1973 u32 retry_limit; 1974 u32 cdb_size; 1975 u8 cdb[16]; 1976 struct user_sgmap sg; 1977 }; 1978 1979 #define AAC_SENSE_BUFFERSIZE 30 1980 1981 struct aac_srb_reply 1982 { 1983 __le32 status; 1984 __le32 srb_status; 1985 __le32 scsi_status; 1986 __le32 data_xfer_length; 1987 __le32 sense_data_size; 1988 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE 1989 }; 1990 /* 1991 * SRB Flags 1992 */ 1993 #define SRB_NoDataXfer 0x0000 1994 #define SRB_DisableDisconnect 0x0004 1995 #define SRB_DisableSynchTransfer 0x0008 1996 #define SRB_BypassFrozenQueue 0x0010 1997 #define SRB_DisableAutosense 0x0020 1998 #define SRB_DataIn 0x0040 1999 #define SRB_DataOut 0x0080 2000 2001 /* 2002 * SRB Functions - set in aac_srb->function 2003 */ 2004 #define SRBF_ExecuteScsi 0x0000 2005 #define SRBF_ClaimDevice 0x0001 2006 #define SRBF_IO_Control 0x0002 2007 #define SRBF_ReceiveEvent 0x0003 2008 #define SRBF_ReleaseQueue 0x0004 2009 #define SRBF_AttachDevice 0x0005 2010 #define SRBF_ReleaseDevice 0x0006 2011 #define SRBF_Shutdown 0x0007 2012 #define SRBF_Flush 0x0008 2013 #define SRBF_AbortCommand 0x0010 2014 #define SRBF_ReleaseRecovery 0x0011 2015 #define SRBF_ResetBus 0x0012 2016 #define SRBF_ResetDevice 0x0013 2017 #define SRBF_TerminateIO 0x0014 2018 #define SRBF_FlushQueue 0x0015 2019 #define SRBF_RemoveDevice 0x0016 2020 #define SRBF_DomainValidation 0x0017 2021 2022 /* 2023 * SRB SCSI Status - set in aac_srb->scsi_status 2024 */ 2025 #define SRB_STATUS_PENDING 0x00 2026 #define SRB_STATUS_SUCCESS 0x01 2027 #define SRB_STATUS_ABORTED 0x02 2028 #define SRB_STATUS_ABORT_FAILED 0x03 2029 #define SRB_STATUS_ERROR 0x04 2030 #define SRB_STATUS_BUSY 0x05 2031 #define SRB_STATUS_INVALID_REQUEST 0x06 2032 #define SRB_STATUS_INVALID_PATH_ID 0x07 2033 #define SRB_STATUS_NO_DEVICE 0x08 2034 #define SRB_STATUS_TIMEOUT 0x09 2035 #define SRB_STATUS_SELECTION_TIMEOUT 0x0A 2036 #define SRB_STATUS_COMMAND_TIMEOUT 0x0B 2037 #define SRB_STATUS_MESSAGE_REJECTED 0x0D 2038 #define SRB_STATUS_BUS_RESET 0x0E 2039 #define SRB_STATUS_PARITY_ERROR 0x0F 2040 #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10 2041 #define SRB_STATUS_NO_HBA 0x11 2042 #define SRB_STATUS_DATA_OVERRUN 0x12 2043 #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13 2044 #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14 2045 #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15 2046 #define SRB_STATUS_REQUEST_FLUSHED 0x16 2047 #define SRB_STATUS_DELAYED_RETRY 0x17 2048 #define SRB_STATUS_INVALID_LUN 0x20 2049 #define SRB_STATUS_INVALID_TARGET_ID 0x21 2050 #define SRB_STATUS_BAD_FUNCTION 0x22 2051 #define SRB_STATUS_ERROR_RECOVERY 0x23 2052 #define SRB_STATUS_NOT_STARTED 0x24 2053 #define SRB_STATUS_NOT_IN_USE 0x30 2054 #define SRB_STATUS_FORCE_ABORT 0x31 2055 #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32 2056 2057 /* 2058 * Object-Server / Volume-Manager Dispatch Classes 2059 */ 2060 2061 #define VM_Null 0 2062 #define VM_NameServe 1 2063 #define VM_ContainerConfig 2 2064 #define VM_Ioctl 3 2065 #define VM_FilesystemIoctl 4 2066 #define VM_CloseAll 5 2067 #define VM_CtBlockRead 6 2068 #define VM_CtBlockWrite 7 2069 #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */ 2070 #define VM_SliceBlockWrite 9 2071 #define VM_DriveBlockRead 10 /* raw access to physical devices */ 2072 #define VM_DriveBlockWrite 11 2073 #define VM_EnclosureMgt 12 /* enclosure management */ 2074 #define VM_Unused 13 /* used to be diskset management */ 2075 #define VM_CtBlockVerify 14 2076 #define VM_CtPerf 15 /* performance test */ 2077 #define VM_CtBlockRead64 16 2078 #define VM_CtBlockWrite64 17 2079 #define VM_CtBlockVerify64 18 2080 #define VM_CtHostRead64 19 2081 #define VM_CtHostWrite64 20 2082 #define VM_DrvErrTblLog 21 2083 #define VM_NameServe64 22 2084 #define VM_NameServeAllBlk 30 2085 2086 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */ 2087 2088 /* 2089 * Descriptive information (eg, vital stats) 2090 * that a content manager might report. The 2091 * FileArray filesystem component is one example 2092 * of a content manager. Raw mode might be 2093 * another. 2094 */ 2095 2096 struct aac_fsinfo { 2097 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */ 2098 __le32 fsBlockSize; 2099 __le32 fsFragSize; 2100 __le32 fsMaxExtendSize; 2101 __le32 fsSpaceUnits; 2102 __le32 fsMaxNumFiles; 2103 __le32 fsNumFreeFiles; 2104 __le32 fsInodeDensity; 2105 }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */ 2106 2107 struct aac_blockdevinfo { 2108 __le32 block_size; 2109 __le32 logical_phys_map; 2110 u8 identifier[16]; 2111 }; 2112 2113 union aac_contentinfo { 2114 struct aac_fsinfo filesys; 2115 struct aac_blockdevinfo bdevinfo; 2116 }; 2117 2118 /* 2119 * Query for Container Configuration Status 2120 */ 2121 2122 #define CT_GET_CONFIG_STATUS 147 2123 struct aac_get_config_status { 2124 __le32 command; /* VM_ContainerConfig */ 2125 __le32 type; /* CT_GET_CONFIG_STATUS */ 2126 __le32 parm1; 2127 __le32 parm2; 2128 __le32 parm3; 2129 __le32 parm4; 2130 __le32 parm5; 2131 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */ 2132 }; 2133 2134 #define CFACT_CONTINUE 0 2135 #define CFACT_PAUSE 1 2136 #define CFACT_ABORT 2 2137 struct aac_get_config_status_resp { 2138 __le32 response; /* ST_OK */ 2139 __le32 dummy0; 2140 __le32 status; /* CT_OK */ 2141 __le32 parm1; 2142 __le32 parm2; 2143 __le32 parm3; 2144 __le32 parm4; 2145 __le32 parm5; 2146 struct { 2147 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */ 2148 __le16 flags; 2149 __le16 count; 2150 } data; 2151 }; 2152 2153 /* 2154 * Accept the configuration as-is 2155 */ 2156 2157 #define CT_COMMIT_CONFIG 152 2158 2159 struct aac_commit_config { 2160 __le32 command; /* VM_ContainerConfig */ 2161 __le32 type; /* CT_COMMIT_CONFIG */ 2162 }; 2163 2164 /* 2165 * Query for Container Configuration Status 2166 */ 2167 2168 #define CT_GET_CONTAINER_COUNT 4 2169 struct aac_get_container_count { 2170 __le32 command; /* VM_ContainerConfig */ 2171 __le32 type; /* CT_GET_CONTAINER_COUNT */ 2172 }; 2173 2174 struct aac_get_container_count_resp { 2175 __le32 response; /* ST_OK */ 2176 __le32 dummy0; 2177 __le32 MaxContainers; 2178 __le32 ContainerSwitchEntries; 2179 __le32 MaxPartitions; 2180 __le32 MaxSimpleVolumes; 2181 }; 2182 2183 2184 /* 2185 * Query for "mountable" objects, ie, objects that are typically 2186 * associated with a drive letter on the client (host) side. 2187 */ 2188 2189 struct aac_mntent { 2190 __le32 oid; 2191 u8 name[16]; /* if applicable */ 2192 struct creation_info create_info; /* if applicable */ 2193 __le32 capacity; 2194 __le32 vol; /* substrate structure */ 2195 __le32 obj; /* FT_FILESYS, etc. */ 2196 __le32 state; /* unready for mounting, 2197 readonly, etc. */ 2198 union aac_contentinfo fileinfo; /* Info specific to content 2199 manager (eg, filesystem) */ 2200 __le32 altoid; /* != oid <==> snapshot or 2201 broken mirror exists */ 2202 __le32 capacityhigh; 2203 }; 2204 2205 #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */ 2206 #define FSCS_READONLY 0x0002 /* possible result of broken mirror */ 2207 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */ 2208 #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */ 2209 2210 struct aac_query_mount { 2211 __le32 command; 2212 __le32 type; 2213 __le32 count; 2214 }; 2215 2216 struct aac_mount { 2217 __le32 status; 2218 __le32 type; /* should be same as that requested */ 2219 __le32 count; 2220 struct aac_mntent mnt[1]; 2221 }; 2222 2223 #define CT_READ_NAME 130 2224 struct aac_get_name { 2225 __le32 command; /* VM_ContainerConfig */ 2226 __le32 type; /* CT_READ_NAME */ 2227 __le32 cid; 2228 __le32 parm1; 2229 __le32 parm2; 2230 __le32 parm3; 2231 __le32 parm4; 2232 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */ 2233 }; 2234 2235 struct aac_get_name_resp { 2236 __le32 dummy0; 2237 __le32 dummy1; 2238 __le32 status; /* CT_OK */ 2239 __le32 parm1; 2240 __le32 parm2; 2241 __le32 parm3; 2242 __le32 parm4; 2243 __le32 parm5; 2244 u8 data[16]; 2245 }; 2246 2247 #define CT_CID_TO_32BITS_UID 165 2248 struct aac_get_serial { 2249 __le32 command; /* VM_ContainerConfig */ 2250 __le32 type; /* CT_CID_TO_32BITS_UID */ 2251 __le32 cid; 2252 }; 2253 2254 struct aac_get_serial_resp { 2255 __le32 dummy0; 2256 __le32 dummy1; 2257 __le32 status; /* CT_OK */ 2258 __le32 uid; 2259 }; 2260 2261 /* 2262 * The following command is sent to shut down each container. 2263 */ 2264 2265 struct aac_close { 2266 __le32 command; 2267 __le32 cid; 2268 }; 2269 2270 struct aac_query_disk 2271 { 2272 s32 cnum; 2273 s32 bus; 2274 s32 id; 2275 s32 lun; 2276 u32 valid; 2277 u32 locked; 2278 u32 deleted; 2279 s32 instance; 2280 s8 name[10]; 2281 u32 unmapped; 2282 }; 2283 2284 struct aac_delete_disk { 2285 u32 disknum; 2286 u32 cnum; 2287 }; 2288 2289 struct fib_ioctl 2290 { 2291 u32 fibctx; 2292 s32 wait; 2293 char __user *fib; 2294 }; 2295 2296 struct revision 2297 { 2298 u32 compat; 2299 __le32 version; 2300 __le32 build; 2301 }; 2302 2303 2304 /* 2305 * Ugly - non Linux like ioctl coding for back compat. 2306 */ 2307 2308 #define CTL_CODE(function, method) ( \ 2309 (4<< 16) | ((function) << 2) | (method) \ 2310 ) 2311 2312 /* 2313 * Define the method codes for how buffers are passed for I/O and FS 2314 * controls 2315 */ 2316 2317 #define METHOD_BUFFERED 0 2318 #define METHOD_NEITHER 3 2319 2320 /* 2321 * Filesystem ioctls 2322 */ 2323 2324 #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED) 2325 #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED) 2326 #define FSACTL_DELETE_DISK 0x163 2327 #define FSACTL_QUERY_DISK 0x173 2328 #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED) 2329 #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED) 2330 #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED) 2331 #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED) 2332 #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED) 2333 #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER) 2334 #define FSACTL_GET_CONTAINERS 2131 2335 #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED) 2336 /* flags defined for IOP & HW SOFT RESET */ 2337 #define HW_IOP_RESET 0x01 2338 #define HW_SOFT_RESET 0x02 2339 #define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET) 2340 /* HW Soft Reset register offset */ 2341 #define IBW_SWR_OFFSET 0x4000 2342 #define SOFT_RESET_TIME 60 2343 2344 2345 struct aac_common 2346 { 2347 /* 2348 * If this value is set to 1 then interrupt moderation will occur 2349 * in the base commuication support. 2350 */ 2351 u32 irq_mod; 2352 u32 peak_fibs; 2353 u32 zero_fibs; 2354 u32 fib_timeouts; 2355 /* 2356 * Statistical counters in debug mode 2357 */ 2358 #ifdef DBG 2359 u32 FibsSent; 2360 u32 FibRecved; 2361 u32 NativeSent; 2362 u32 NativeRecved; 2363 u32 NoResponseSent; 2364 u32 NoResponseRecved; 2365 u32 AsyncSent; 2366 u32 AsyncRecved; 2367 u32 NormalSent; 2368 u32 NormalRecved; 2369 #endif 2370 }; 2371 2372 extern struct aac_common aac_config; 2373 2374 /* 2375 * The following macro is used when sending and receiving FIBs. It is 2376 * only used for debugging. 2377 */ 2378 2379 #ifdef DBG 2380 #define FIB_COUNTER_INCREMENT(counter) (counter)++ 2381 #else 2382 #define FIB_COUNTER_INCREMENT(counter) 2383 #endif 2384 2385 /* 2386 * Adapter direct commands 2387 * Monitor/Kernel API 2388 */ 2389 2390 #define BREAKPOINT_REQUEST 0x00000004 2391 #define INIT_STRUCT_BASE_ADDRESS 0x00000005 2392 #define READ_PERMANENT_PARAMETERS 0x0000000a 2393 #define WRITE_PERMANENT_PARAMETERS 0x0000000b 2394 #define HOST_CRASHING 0x0000000d 2395 #define SEND_SYNCHRONOUS_FIB 0x0000000c 2396 #define COMMAND_POST_RESULTS 0x00000014 2397 #define GET_ADAPTER_PROPERTIES 0x00000019 2398 #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023 2399 #define RCV_TEMP_READINGS 0x00000025 2400 #define GET_COMM_PREFERRED_SETTINGS 0x00000026 2401 #define IOP_RESET 0x00001000 2402 #define IOP_RESET_ALWAYS 0x00001001 2403 #define RE_INIT_ADAPTER 0x000000ee 2404 2405 /* 2406 * Adapter Status Register 2407 * 2408 * Phase Staus mailbox is 32bits: 2409 * <31:16> = Phase Status 2410 * <15:0> = Phase 2411 * 2412 * The adapter reports is present state through the phase. Only 2413 * a single phase should be ever be set. Each phase can have multiple 2414 * phase status bits to provide more detailed information about the 2415 * state of the board. Care should be taken to ensure that any phase 2416 * status bits that are set when changing the phase are also valid 2417 * for the new phase or be cleared out. Adapter software (monitor, 2418 * iflash, kernel) is responsible for properly maintining the phase 2419 * status mailbox when it is running. 2420 * 2421 * MONKER_API Phases 2422 * 2423 * Phases are bit oriented. It is NOT valid to have multiple bits set 2424 */ 2425 2426 #define SELF_TEST_FAILED 0x00000004 2427 #define MONITOR_PANIC 0x00000020 2428 #define KERNEL_UP_AND_RUNNING 0x00000080 2429 #define KERNEL_PANIC 0x00000100 2430 #define FLASH_UPD_PENDING 0x00002000 2431 #define FLASH_UPD_SUCCESS 0x00004000 2432 #define FLASH_UPD_FAILED 0x00008000 2433 #define FWUPD_TIMEOUT (5 * 60) 2434 2435 /* 2436 * Doorbell bit defines 2437 */ 2438 2439 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */ 2440 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */ 2441 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */ 2442 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */ 2443 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */ 2444 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */ 2445 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */ 2446 #define DoorBellAifPending (1<<6) /* Adapter -> Host */ 2447 2448 /* PMC specific outbound doorbell bits */ 2449 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */ 2450 2451 /* 2452 * For FIB communication, we need all of the following things 2453 * to send back to the user. 2454 */ 2455 2456 #define AifCmdEventNotify 1 /* Notify of event */ 2457 #define AifEnConfigChange 3 /* Adapter configuration change */ 2458 #define AifEnContainerChange 4 /* Container configuration change */ 2459 #define AifEnDeviceFailure 5 /* SCSI device failed */ 2460 #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */ 2461 #define EM_DRIVE_INSERTION 31 2462 #define EM_DRIVE_REMOVAL 32 2463 #define EM_SES_DRIVE_INSERTION 33 2464 #define EM_SES_DRIVE_REMOVAL 26 2465 #define AifEnBatteryEvent 14 /* Change in Battery State */ 2466 #define AifEnAddContainer 15 /* A new array was created */ 2467 #define AifEnDeleteContainer 16 /* A container was deleted */ 2468 #define AifEnExpEvent 23 /* Firmware Event Log */ 2469 #define AifExeFirmwarePanic 3 /* Firmware Event Panic */ 2470 #define AifHighPriority 3 /* Highest Priority Event */ 2471 #define AifEnAddJBOD 30 /* JBOD created */ 2472 #define AifEnDeleteJBOD 31 /* JBOD deleted */ 2473 2474 #define AifBuManagerEvent 42 /* Bu management*/ 2475 #define AifBuCacheDataLoss 10 2476 #define AifBuCacheDataRecover 11 2477 2478 #define AifCmdJobProgress 2 /* Progress report */ 2479 #define AifJobCtrZero 101 /* Array Zero progress */ 2480 #define AifJobStsSuccess 1 /* Job completes */ 2481 #define AifJobStsRunning 102 /* Job running */ 2482 #define AifCmdAPIReport 3 /* Report from other user of API */ 2483 #define AifCmdDriverNotify 4 /* Notify host driver of event */ 2484 #define AifDenMorphComplete 200 /* A morph operation completed */ 2485 #define AifDenVolumeExtendComplete 201 /* A volume extend completed */ 2486 #define AifReqJobList 100 /* Gets back complete job list */ 2487 #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */ 2488 #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */ 2489 #define AifReqJobReport 103 /* Gets back a specific job report or list of them */ 2490 #define AifReqTerminateJob 104 /* Terminates job */ 2491 #define AifReqSuspendJob 105 /* Suspends a job */ 2492 #define AifReqResumeJob 106 /* Resumes a job */ 2493 #define AifReqSendAPIReport 107 /* API generic report requests */ 2494 #define AifReqAPIJobStart 108 /* Start a job from the API */ 2495 #define AifReqAPIJobUpdate 109 /* Update a job report from the API */ 2496 #define AifReqAPIJobFinish 110 /* Finish a job from the API */ 2497 2498 /* PMC NEW COMM: Request the event data */ 2499 #define AifReqEvent 200 2500 #define AifRawDeviceRemove 203 /* RAW device deleted */ 2501 #define AifNativeDeviceAdd 204 /* native HBA device added */ 2502 #define AifNativeDeviceRemove 205 /* native HBA device removed */ 2503 2504 2505 /* 2506 * Adapter Initiated FIB command structures. Start with the adapter 2507 * initiated FIBs that really come from the adapter, and get responded 2508 * to by the host. 2509 */ 2510 2511 struct aac_aifcmd { 2512 __le32 command; /* Tell host what type of notify this is */ 2513 __le32 seqnum; /* To allow ordering of reports (if necessary) */ 2514 u8 data[1]; /* Undefined length (from kernel viewpoint) */ 2515 }; 2516 2517 /** 2518 * Convert capacity to cylinders 2519 * accounting for the fact capacity could be a 64 bit value 2520 * 2521 */ 2522 static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor) 2523 { 2524 sector_div(capacity, divisor); 2525 return capacity; 2526 } 2527 2528 /* SCp.phase values */ 2529 #define AAC_OWNER_MIDLEVEL 0x101 2530 #define AAC_OWNER_LOWLEVEL 0x102 2531 #define AAC_OWNER_ERROR_HANDLER 0x103 2532 #define AAC_OWNER_FIRMWARE 0x106 2533 2534 int aac_acquire_irq(struct aac_dev *dev); 2535 void aac_free_irq(struct aac_dev *dev); 2536 int aac_report_phys_luns(struct aac_dev *dev, struct fib *fibptr, int rescan); 2537 int aac_issue_bmic_identify(struct aac_dev *dev, u32 bus, u32 target); 2538 const char *aac_driverinfo(struct Scsi_Host *); 2539 void aac_fib_vector_assign(struct aac_dev *dev); 2540 struct fib *aac_fib_alloc(struct aac_dev *dev); 2541 struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd); 2542 int aac_fib_setup(struct aac_dev *dev); 2543 void aac_fib_map_free(struct aac_dev *dev); 2544 void aac_fib_free(struct fib * context); 2545 void aac_fib_init(struct fib * context); 2546 void aac_printf(struct aac_dev *dev, u32 val); 2547 int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt); 2548 int aac_hba_send(u8 command, struct fib *context, 2549 fib_callback callback, void *ctxt); 2550 int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry); 2551 void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum); 2552 int aac_fib_complete(struct fib * context); 2553 void aac_hba_callback(void *context, struct fib *fibptr); 2554 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data) 2555 struct aac_dev *aac_init_adapter(struct aac_dev *dev); 2556 void aac_src_access_devreg(struct aac_dev *dev, int mode); 2557 int aac_get_config_status(struct aac_dev *dev, int commit_flag); 2558 int aac_get_containers(struct aac_dev *dev); 2559 int aac_scsi_cmd(struct scsi_cmnd *cmd); 2560 int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg); 2561 #ifndef shost_to_class 2562 #define shost_to_class(shost) &shost->shost_dev 2563 #endif 2564 ssize_t aac_get_serial_number(struct device *dev, char *buf); 2565 int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg); 2566 int aac_rx_init(struct aac_dev *dev); 2567 int aac_rkt_init(struct aac_dev *dev); 2568 int aac_nark_init(struct aac_dev *dev); 2569 int aac_sa_init(struct aac_dev *dev); 2570 int aac_src_init(struct aac_dev *dev); 2571 int aac_srcv_init(struct aac_dev *dev); 2572 int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify); 2573 void aac_define_int_mode(struct aac_dev *dev); 2574 unsigned int aac_response_normal(struct aac_queue * q); 2575 unsigned int aac_command_normal(struct aac_queue * q); 2576 unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index, 2577 int isAif, int isFastResponse, 2578 struct hw_fib *aif_fib); 2579 int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type); 2580 int aac_check_health(struct aac_dev * dev); 2581 int aac_command_thread(void *data); 2582 int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx); 2583 int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size); 2584 struct aac_driver_ident* aac_get_driver_ident(int devtype); 2585 int aac_get_adapter_info(struct aac_dev* dev); 2586 int aac_send_shutdown(struct aac_dev *dev); 2587 int aac_probe_container(struct aac_dev *dev, int cid); 2588 int _aac_rx_init(struct aac_dev *dev); 2589 int aac_rx_select_comm(struct aac_dev *dev, int comm); 2590 int aac_rx_deliver_producer(struct fib * fib); 2591 char * get_container_type(unsigned type); 2592 extern int numacb; 2593 extern char aac_driver_version[]; 2594 extern int startup_timeout; 2595 extern int aif_timeout; 2596 extern int expose_physicals; 2597 extern int aac_reset_devices; 2598 extern int aac_msi; 2599 extern int aac_commit; 2600 extern int update_interval; 2601 extern int check_interval; 2602 extern int aac_check_reset; 2603 #endif 2604