1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * NCR 5380 defines 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Copyright 1993, Drew Eckhardt 61da177e4SLinus Torvalds * Visionary Computing 71da177e4SLinus Torvalds * (Unix consulting and custom programming) 81da177e4SLinus Torvalds * drew@colorado.edu 91da177e4SLinus Torvalds * +1 (303) 666-5836 101da177e4SLinus Torvalds * 111da177e4SLinus Torvalds * For more information, please consult 121da177e4SLinus Torvalds * 131da177e4SLinus Torvalds * NCR 5380 Family 141da177e4SLinus Torvalds * SCSI Protocol Controller 151da177e4SLinus Torvalds * Databook 161da177e4SLinus Torvalds * NCR Microelectronics 171da177e4SLinus Torvalds * 1635 Aeroplaza Drive 181da177e4SLinus Torvalds * Colorado Springs, CO 80916 191da177e4SLinus Torvalds * 1+ (719) 578-3400 201da177e4SLinus Torvalds * 1+ (800) 334-5454 211da177e4SLinus Torvalds */ 221da177e4SLinus Torvalds 231da177e4SLinus Torvalds #ifndef NCR5380_H 241da177e4SLinus Torvalds #define NCR5380_H 251da177e4SLinus Torvalds 26161c0059SFinn Thain #include <linux/delay.h> 271da177e4SLinus Torvalds #include <linux/interrupt.h> 2832b26a10SFinn Thain #include <linux/list.h> 29161c0059SFinn Thain #include <linux/workqueue.h> 30161c0059SFinn Thain #include <scsi/scsi_dbg.h> 3128424d3aSBoaz Harrosh #include <scsi/scsi_eh.h> 32161c0059SFinn Thain #include <scsi/scsi_transport_spi.h> 3328424d3aSBoaz Harrosh 341da177e4SLinus Torvalds #define NDEBUG_ARBITRATION 0x1 351da177e4SLinus Torvalds #define NDEBUG_AUTOSENSE 0x2 361da177e4SLinus Torvalds #define NDEBUG_DMA 0x4 371da177e4SLinus Torvalds #define NDEBUG_HANDSHAKE 0x8 381da177e4SLinus Torvalds #define NDEBUG_INFORMATION 0x10 391da177e4SLinus Torvalds #define NDEBUG_INIT 0x20 401da177e4SLinus Torvalds #define NDEBUG_INTR 0x40 411da177e4SLinus Torvalds #define NDEBUG_LINKED 0x80 421da177e4SLinus Torvalds #define NDEBUG_MAIN 0x100 431da177e4SLinus Torvalds #define NDEBUG_NO_DATAOUT 0x200 441da177e4SLinus Torvalds #define NDEBUG_NO_WRITE 0x400 451da177e4SLinus Torvalds #define NDEBUG_PIO 0x800 461da177e4SLinus Torvalds #define NDEBUG_PSEUDO_DMA 0x1000 471da177e4SLinus Torvalds #define NDEBUG_QUEUES 0x2000 481da177e4SLinus Torvalds #define NDEBUG_RESELECTION 0x4000 491da177e4SLinus Torvalds #define NDEBUG_SELECTION 0x8000 501da177e4SLinus Torvalds #define NDEBUG_USLEEP 0x10000 511da177e4SLinus Torvalds #define NDEBUG_LAST_BYTE_SENT 0x20000 521da177e4SLinus Torvalds #define NDEBUG_RESTART_SELECT 0x40000 531da177e4SLinus Torvalds #define NDEBUG_EXTENDED 0x80000 541da177e4SLinus Torvalds #define NDEBUG_C400_PREAD 0x100000 551da177e4SLinus Torvalds #define NDEBUG_C400_PWRITE 0x200000 561da177e4SLinus Torvalds #define NDEBUG_LISTS 0x400000 579829e528SFinn Thain #define NDEBUG_ABORT 0x800000 589829e528SFinn Thain #define NDEBUG_TAGS 0x1000000 599829e528SFinn Thain #define NDEBUG_MERGING 0x2000000 601da177e4SLinus Torvalds 611da177e4SLinus Torvalds #define NDEBUG_ANY 0xFFFFFFFFUL 621da177e4SLinus Torvalds 631da177e4SLinus Torvalds /* 641da177e4SLinus Torvalds * The contents of the OUTPUT DATA register are asserted on the bus when 651da177e4SLinus Torvalds * either arbitration is occurring or the phase-indicating signals ( 661da177e4SLinus Torvalds * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA 671da177e4SLinus Torvalds * bit in the INITIATOR COMMAND register is set. 681da177e4SLinus Torvalds */ 691da177e4SLinus Torvalds 701da177e4SLinus Torvalds #define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */ 711da177e4SLinus Torvalds #define CURRENT_SCSI_DATA_REG 0 /* ro same */ 721da177e4SLinus Torvalds 731da177e4SLinus Torvalds #define INITIATOR_COMMAND_REG 1 /* rw */ 741da177e4SLinus Torvalds #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */ 751da177e4SLinus Torvalds #define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */ 761da177e4SLinus Torvalds #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */ 771da177e4SLinus Torvalds #define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */ 781da177e4SLinus Torvalds #define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */ 791da177e4SLinus Torvalds #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */ 801da177e4SLinus Torvalds #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */ 811da177e4SLinus Torvalds #define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */ 821da177e4SLinus Torvalds #define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */ 831da177e4SLinus Torvalds #define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */ 841da177e4SLinus Torvalds 851da177e4SLinus Torvalds #define ICR_BASE 0 861da177e4SLinus Torvalds 871da177e4SLinus Torvalds #define MODE_REG 2 881da177e4SLinus Torvalds /* 891da177e4SLinus Torvalds * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 901da177e4SLinus Torvalds * transfer, causing the chip to hog the bus. You probably don't want 911da177e4SLinus Torvalds * this. 921da177e4SLinus Torvalds */ 931da177e4SLinus Torvalds #define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */ 941da177e4SLinus Torvalds #define MR_TARGET 0x40 /* rw target mode */ 951da177e4SLinus Torvalds #define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */ 961da177e4SLinus Torvalds #define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */ 971da177e4SLinus Torvalds #define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */ 981da177e4SLinus Torvalds #define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */ 991da177e4SLinus Torvalds #define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */ 1001da177e4SLinus Torvalds #define MR_ARBITRATE 0x01 /* rw start arbitration */ 1011da177e4SLinus Torvalds 1021da177e4SLinus Torvalds #define MR_BASE 0 1031da177e4SLinus Torvalds 1041da177e4SLinus Torvalds #define TARGET_COMMAND_REG 3 1051da177e4SLinus Torvalds #define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */ 1061da177e4SLinus Torvalds #define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */ 1071da177e4SLinus Torvalds #define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */ 1081da177e4SLinus Torvalds #define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */ 1091da177e4SLinus Torvalds #define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */ 1101da177e4SLinus Torvalds 1111da177e4SLinus Torvalds #define STATUS_REG 4 /* ro */ 1121da177e4SLinus Torvalds /* 1131da177e4SLinus Torvalds * Note : a set bit indicates an active signal, driven by us or another 1141da177e4SLinus Torvalds * device. 1151da177e4SLinus Torvalds */ 1161da177e4SLinus Torvalds #define SR_RST 0x80 1171da177e4SLinus Torvalds #define SR_BSY 0x40 1181da177e4SLinus Torvalds #define SR_REQ 0x20 1191da177e4SLinus Torvalds #define SR_MSG 0x10 1201da177e4SLinus Torvalds #define SR_CD 0x08 1211da177e4SLinus Torvalds #define SR_IO 0x04 1221da177e4SLinus Torvalds #define SR_SEL 0x02 1231da177e4SLinus Torvalds #define SR_DBP 0x01 1241da177e4SLinus Torvalds 1251da177e4SLinus Torvalds /* 1261da177e4SLinus Torvalds * Setting a bit in this register will cause an interrupt to be generated when 1271da177e4SLinus Torvalds * BSY is false and SEL true and this bit is asserted on the bus. 1281da177e4SLinus Torvalds */ 1291da177e4SLinus Torvalds #define SELECT_ENABLE_REG 4 /* wo */ 1301da177e4SLinus Torvalds 1311da177e4SLinus Torvalds #define BUS_AND_STATUS_REG 5 /* ro */ 1321da177e4SLinus Torvalds #define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */ 1331da177e4SLinus Torvalds #define BASR_DRQ 0x40 /* ro mirror of DRQ pin */ 1341da177e4SLinus Torvalds #define BASR_PARITY_ERROR 0x20 /* ro parity error detected */ 1351da177e4SLinus Torvalds #define BASR_IRQ 0x10 /* ro mirror of IRQ pin */ 1361da177e4SLinus Torvalds #define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */ 1371da177e4SLinus Torvalds #define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */ 1381da177e4SLinus Torvalds #define BASR_ATN 0x02 /* ro BUS status */ 1391da177e4SLinus Torvalds #define BASR_ACK 0x01 /* ro BUS status */ 1401da177e4SLinus Torvalds 1411da177e4SLinus Torvalds /* Write any value to this register to start a DMA send */ 1421da177e4SLinus Torvalds #define START_DMA_SEND_REG 5 /* wo */ 1431da177e4SLinus Torvalds 1441da177e4SLinus Torvalds /* 1451da177e4SLinus Torvalds * Used in DMA transfer mode, data is latched from the SCSI bus on 1461da177e4SLinus Torvalds * the falling edge of REQ (ini) or ACK (tgt) 1471da177e4SLinus Torvalds */ 1481da177e4SLinus Torvalds #define INPUT_DATA_REG 6 /* ro */ 1491da177e4SLinus Torvalds 1501da177e4SLinus Torvalds /* Write any value to this register to start a DMA receive */ 1511da177e4SLinus Torvalds #define START_DMA_TARGET_RECEIVE_REG 6 /* wo */ 1521da177e4SLinus Torvalds 1531da177e4SLinus Torvalds /* Read this register to clear interrupt conditions */ 1541da177e4SLinus Torvalds #define RESET_PARITY_INTERRUPT_REG 7 /* ro */ 1551da177e4SLinus Torvalds 1561da177e4SLinus Torvalds /* Write any value to this register to start an ini mode DMA receive */ 1571da177e4SLinus Torvalds #define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */ 1581da177e4SLinus Torvalds 15912150797SOndrej Zary /* NCR 53C400(A) Control Status Register bits: */ 1601da177e4SLinus Torvalds #define CSR_RESET 0x80 /* wo Resets 53c400 */ 1611da177e4SLinus Torvalds #define CSR_53C80_REG 0x80 /* ro 5380 registers busy */ 1621da177e4SLinus Torvalds #define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */ 1631da177e4SLinus Torvalds #define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */ 1641da177e4SLinus Torvalds #define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */ 1651da177e4SLinus Torvalds #define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */ 1661da177e4SLinus Torvalds #define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */ 1671da177e4SLinus Torvalds #define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */ 1681da177e4SLinus Torvalds #define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */ 1691da177e4SLinus Torvalds 1701da177e4SLinus Torvalds #define CSR_BASE CSR_53C80_INTR 1711da177e4SLinus Torvalds 1721da177e4SLinus Torvalds /* Note : PHASE_* macros are based on the values of the STATUS register */ 1731da177e4SLinus Torvalds #define PHASE_MASK (SR_MSG | SR_CD | SR_IO) 1741da177e4SLinus Torvalds 1751da177e4SLinus Torvalds #define PHASE_DATAOUT 0 1761da177e4SLinus Torvalds #define PHASE_DATAIN SR_IO 1771da177e4SLinus Torvalds #define PHASE_CMDOUT SR_CD 1781da177e4SLinus Torvalds #define PHASE_STATIN (SR_CD | SR_IO) 1791da177e4SLinus Torvalds #define PHASE_MSGOUT (SR_MSG | SR_CD) 1801da177e4SLinus Torvalds #define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO) 1811da177e4SLinus Torvalds #define PHASE_UNKNOWN 0xff 1821da177e4SLinus Torvalds 1831da177e4SLinus Torvalds /* 1841da177e4SLinus Torvalds * Convert status register phase to something we can use to set phase in 1851da177e4SLinus Torvalds * the target register so we can get phase mismatch interrupts on DMA 1861da177e4SLinus Torvalds * transfers. 1871da177e4SLinus Torvalds */ 1881da177e4SLinus Torvalds 1891da177e4SLinus Torvalds #define PHASE_SR_TO_TCR(phase) ((phase) >> 2) 1901da177e4SLinus Torvalds 19122f5f10dSFinn Thain #ifndef NO_IRQ 19222f5f10dSFinn Thain #define NO_IRQ 0 19322f5f10dSFinn Thain #endif 19422f5f10dSFinn Thain 1951bb46002SFinn Thain #define FLAG_DMA_FIXUP 1 /* Use DMA errata workarounds */ 1961da177e4SLinus Torvalds #define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */ 197ef1081cbSFinn Thain #define FLAG_LATE_DMA_SETUP 32 /* Setup NCR before DMA H/W */ 1989c3f0e2bSFinn Thain #define FLAG_TOSHIBA_DELAY 128 /* Allow for borken CD-ROMs */ 1991da177e4SLinus Torvalds 2001da177e4SLinus Torvalds struct NCR5380_hostdata { 20125894d1fSFinn Thain NCR5380_implementation_fields; /* Board-specific data */ 202820682b1SFinn Thain u8 __iomem *io; /* Remapped 5380 address */ 203820682b1SFinn Thain u8 __iomem *pdma_io; /* Remapped PDMA address */ 20425894d1fSFinn Thain unsigned long poll_loops; /* Register polling limit */ 20525894d1fSFinn Thain spinlock_t lock; /* Protects this struct */ 20625894d1fSFinn Thain struct scsi_cmnd *connected; /* Currently connected cmnd */ 20725894d1fSFinn Thain struct list_head disconnected; /* Waiting for reconnect */ 20825894d1fSFinn Thain struct Scsi_Host *host; /* SCSI host backpointer */ 20925894d1fSFinn Thain struct workqueue_struct *work_q; /* SCSI host work queue */ 21025894d1fSFinn Thain struct work_struct main_task; /* Work item for main loop */ 21125894d1fSFinn Thain int flags; /* Board-specific quirks */ 21225894d1fSFinn Thain int dma_len; /* Requested length of DMA */ 21325894d1fSFinn Thain int read_overruns; /* Transfer size reduction for DMA erratum */ 214820682b1SFinn Thain unsigned long io_port; /* Device IO port */ 215820682b1SFinn Thain unsigned long base; /* Device base address */ 21625894d1fSFinn Thain struct list_head unissued; /* Waiting to be issued */ 21725894d1fSFinn Thain struct scsi_cmnd *selecting; /* Cmnd to be connected */ 21825894d1fSFinn Thain struct list_head autosense; /* Priority cmnd queue */ 21925894d1fSFinn Thain struct scsi_cmnd *sensing; /* Cmnd needing autosense */ 22025894d1fSFinn Thain struct scsi_eh_save ses; /* Cmnd state saved for EH */ 22125894d1fSFinn Thain unsigned char busy[8]; /* Index = target, bit = lun */ 22225894d1fSFinn Thain unsigned char id_mask; /* 1 << Host ID */ 22325894d1fSFinn Thain unsigned char id_higher_mask; /* All bits above id_mask */ 22425894d1fSFinn Thain unsigned char last_message; /* Last Message Out */ 225820682b1SFinn Thain unsigned long region_size; /* Size of address/port range */ 22609028461SFinn Thain char info[168]; /* Host banner message */ 2271da177e4SLinus Torvalds }; 2281da177e4SLinus Torvalds 22932b26a10SFinn Thain struct NCR5380_cmd { 23032b26a10SFinn Thain struct list_head list; 23132b26a10SFinn Thain }; 23232b26a10SFinn Thain 23332b26a10SFinn Thain #define NCR5380_CMD_SIZE (sizeof(struct NCR5380_cmd)) 23432b26a10SFinn Thain 23508348b1cSFinn Thain #define NCR5380_PIO_CHUNK_SIZE 256 23608348b1cSFinn Thain 237d4408dd7SFinn Thain /* Time limit (ms) to poll registers when IRQs are disabled, e.g. during PDMA */ 23825fcf94aSFinn Thain #define NCR5380_REG_POLL_TIME 10 239d4408dd7SFinn Thain 24032b26a10SFinn Thain static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr) 24132b26a10SFinn Thain { 24232b26a10SFinn Thain return ((struct scsi_cmnd *)ncmd_ptr) - 1; 24332b26a10SFinn Thain } 24432b26a10SFinn Thain 2459829e528SFinn Thain #ifndef NDEBUG 2469829e528SFinn Thain #define NDEBUG (0) 2479829e528SFinn Thain #endif 2489829e528SFinn Thain 24916b9d870SFinn Thain #define dprintk(flg, fmt, ...) \ 250d61c5427SFinn Thain do { if ((NDEBUG) & (flg)) \ 251d61c5427SFinn Thain printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0) 25216b9d870SFinn Thain 253dbb6b350SFinn Thain #define dsprintk(flg, host, fmt, ...) \ 254dbb6b350SFinn Thain do { if ((NDEBUG) & (flg)) \ 255dbb6b350SFinn Thain shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \ 256dbb6b350SFinn Thain } while (0) 257dbb6b350SFinn Thain 2589829e528SFinn Thain #if NDEBUG 2599829e528SFinn Thain #define NCR5380_dprint(flg, arg) \ 2609829e528SFinn Thain do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0) 2619829e528SFinn Thain #define NCR5380_dprint_phase(flg, arg) \ 2629829e528SFinn Thain do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0) 2639829e528SFinn Thain static void NCR5380_print_phase(struct Scsi_Host *instance); 2649829e528SFinn Thain static void NCR5380_print(struct Scsi_Host *instance); 2659829e528SFinn Thain #else 26652a6a1cbSFinn Thain #define NCR5380_dprint(flg, arg) do {} while (0) 26752a6a1cbSFinn Thain #define NCR5380_dprint_phase(flg, arg) do {} while (0) 2689829e528SFinn Thain #endif 2691da177e4SLinus Torvalds 2701da177e4SLinus Torvalds static int NCR5380_init(struct Scsi_Host *instance, int flags); 271b6488f97SFinn Thain static int NCR5380_maybe_reset_bus(struct Scsi_Host *); 2721da177e4SLinus Torvalds static void NCR5380_exit(struct Scsi_Host *instance); 2731da177e4SLinus Torvalds static void NCR5380_information_transfer(struct Scsi_Host *instance); 2747d12e780SDavid Howells static irqreturn_t NCR5380_intr(int irq, void *dev_id); 275c4028958SDavid Howells static void NCR5380_main(struct work_struct *work); 2768c32513bSFinn Thain static const char *NCR5380_info(struct Scsi_Host *instance); 2771da177e4SLinus Torvalds static void NCR5380_reselect(struct Scsi_Host *instance); 278dad8261eSFinn Thain static bool NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *); 2791da177e4SLinus Torvalds static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data); 2801da177e4SLinus Torvalds static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data); 281d5d37a0aSFinn Thain static int NCR5380_poll_politely2(struct NCR5380_hostdata *, 28261e1ce58SFinn Thain unsigned int, u8, u8, 28361e1ce58SFinn Thain unsigned int, u8, u8, unsigned long); 2841da177e4SLinus Torvalds 285d5d37a0aSFinn Thain static inline int NCR5380_poll_politely(struct NCR5380_hostdata *hostdata, 28661e1ce58SFinn Thain unsigned int reg, u8 bit, u8 val, 28761e1ce58SFinn Thain unsigned long wait) 28801f17641SFinn Thain { 2897c606631SFinn Thain if ((NCR5380_read(reg) & bit) == val) 2907c606631SFinn Thain return 0; 2917c606631SFinn Thain 292d5d37a0aSFinn Thain return NCR5380_poll_politely2(hostdata, reg, bit, val, 29301f17641SFinn Thain reg, bit, val, wait); 29401f17641SFinn Thain } 29501f17641SFinn Thain 2964a98f896SFinn Thain static int NCR5380_dma_xfer_len(struct NCR5380_hostdata *, 2974a98f896SFinn Thain struct scsi_cmnd *); 2984a98f896SFinn Thain static int NCR5380_dma_send_setup(struct NCR5380_hostdata *, 2994a98f896SFinn Thain unsigned char *, int); 3004a98f896SFinn Thain static int NCR5380_dma_recv_setup(struct NCR5380_hostdata *, 3014a98f896SFinn Thain unsigned char *, int); 3024a98f896SFinn Thain static int NCR5380_dma_residual(struct NCR5380_hostdata *); 3034a98f896SFinn Thain 3044a98f896SFinn Thain static inline int NCR5380_dma_xfer_none(struct NCR5380_hostdata *hostdata, 3054a98f896SFinn Thain struct scsi_cmnd *cmd) 3064a98f896SFinn Thain { 3074a98f896SFinn Thain return 0; 3084a98f896SFinn Thain } 3094a98f896SFinn Thain 3104a98f896SFinn Thain static inline int NCR5380_dma_setup_none(struct NCR5380_hostdata *hostdata, 3114a98f896SFinn Thain unsigned char *data, int count) 3124a98f896SFinn Thain { 3134a98f896SFinn Thain return 0; 3144a98f896SFinn Thain } 3154a98f896SFinn Thain 3164a98f896SFinn Thain static inline int NCR5380_dma_residual_none(struct NCR5380_hostdata *hostdata) 3174a98f896SFinn Thain { 3184a98f896SFinn Thain return 0; 3194a98f896SFinn Thain } 3204a98f896SFinn Thain 3211da177e4SLinus Torvalds #endif /* NCR5380_H */ 322