1 /* -*- mode: c; c-basic-offset: 8 -*- */ 2 3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios 4 * 5 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com 6 */ 7 8 #ifndef _53C700_H 9 #define _53C700_H 10 11 #include <linux/interrupt.h> 12 #include <asm/io.h> 13 14 #include <scsi/scsi_device.h> 15 #include <scsi/scsi_cmnd.h> 16 17 /* Turn on for general debugging---too verbose for normal use */ 18 #undef NCR_700_DEBUG 19 /* Debug the tag queues, checking hash queue allocation and deallocation 20 * and search for duplicate tags */ 21 #undef NCR_700_TAG_DEBUG 22 23 #ifdef NCR_700_DEBUG 24 #define DEBUG(x) printk x 25 #define DDEBUG(prefix, sdev, fmt, a...) \ 26 sdev_printk(prefix, sdev, fmt, ##a) 27 #define CDEBUG(prefix, scmd, fmt, a...) \ 28 scmd_printk(prefix, scmd, fmt, ##a) 29 #else 30 #define DEBUG(x) do {} while (0) 31 #define DDEBUG(prefix, scmd, fmt, a...) do {} while (0) 32 #define CDEBUG(prefix, scmd, fmt, a...) do {} while (0) 33 #endif 34 35 /* The number of available command slots */ 36 #define NCR_700_COMMAND_SLOTS_PER_HOST 64 37 /* The maximum number of Scatter Gathers we allow */ 38 #define NCR_700_SG_SEGMENTS 32 39 /* The maximum number of luns (make this of the form 2^n) */ 40 #define NCR_700_MAX_LUNS 32 41 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1) 42 /* Maximum number of tags the driver ever allows per device */ 43 #define NCR_700_MAX_TAGS 16 44 /* Tag depth the driver starts out with (can be altered in sysfs) */ 45 #define NCR_700_DEFAULT_TAGS 4 46 /* This is the default number of commands per LUN in the untagged case. 47 * two is a good value because it means we can have one command active and 48 * one command fully prepared and waiting 49 */ 50 #define NCR_700_CMD_PER_LUN 2 51 /* magic byte identifying an internally generated REQUEST_SENSE command */ 52 #define NCR_700_INTERNAL_SENSE_MAGIC 0x42 53 54 struct NCR_700_Host_Parameters; 55 56 /* These are the externally used routines */ 57 struct Scsi_Host *NCR_700_detect(struct scsi_host_template *, 58 struct NCR_700_Host_Parameters *, struct device *); 59 int NCR_700_release(struct Scsi_Host *host); 60 irqreturn_t NCR_700_intr(int, void *); 61 62 63 enum NCR_700_Host_State { 64 NCR_700_HOST_BUSY, 65 NCR_700_HOST_FREE, 66 }; 67 68 struct NCR_700_SG_List { 69 /* The following is a script fragment to move the buffer onto the 70 * bus and then link the next fragment or return */ 71 #define SCRIPT_MOVE_DATA_IN 0x09000000 72 #define SCRIPT_MOVE_DATA_OUT 0x08000000 73 __u32 ins; 74 __u32 pAddr; 75 #define SCRIPT_NOP 0x80000000 76 #define SCRIPT_RETURN 0x90080000 77 }; 78 79 struct NCR_700_Device_Parameters { 80 /* space for creating a request sense command. Really, except 81 * for the annoying SCSI-2 requirement for LUN information in 82 * cmnd[1], this could be in static storage */ 83 unsigned char cmnd[MAX_COMMAND_SIZE]; 84 __u8 depth; 85 }; 86 87 88 /* The SYNC negotiation sequence looks like: 89 * 90 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the 91 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION 92 * If we get an SDTR reply, work out the SXFER parameters, squirrel 93 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set 94 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel 95 * 96 * 97 * 0:7 SXFER_REG negotiated value for this device 98 * 8:15 Current queue depth 99 * 16 negotiated SYNC flag 100 * 17 begin SYNC negotiation flag 101 * 18 device supports tag queueing */ 102 #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16) 103 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17) 104 #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19) 105 106 static inline char *NCR_700_get_sense_cmnd(struct scsi_device *SDp) 107 { 108 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; 109 110 return hostdata->cmnd; 111 } 112 113 static inline void 114 NCR_700_set_depth(struct scsi_device *SDp, __u8 depth) 115 { 116 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; 117 118 hostdata->depth = depth; 119 } 120 static inline __u8 121 NCR_700_get_depth(struct scsi_device *SDp) 122 { 123 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; 124 125 return hostdata->depth; 126 } 127 static inline int 128 NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag) 129 { 130 return (spi_flags(SDp->sdev_target) & flag) == flag; 131 } 132 static inline int 133 NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag) 134 { 135 return (spi_flags(SDp->sdev_target) & flag) == 0; 136 } 137 static inline void 138 NCR_700_set_flag(struct scsi_device *SDp, __u32 flag) 139 { 140 spi_flags(SDp->sdev_target) |= flag; 141 } 142 static inline void 143 NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag) 144 { 145 spi_flags(SDp->sdev_target) &= ~flag; 146 } 147 148 enum NCR_700_tag_neg_state { 149 NCR_700_START_TAG_NEGOTIATION = 0, 150 NCR_700_DURING_TAG_NEGOTIATION = 1, 151 NCR_700_FINISHED_TAG_NEGOTIATION = 2, 152 }; 153 154 static inline enum NCR_700_tag_neg_state 155 NCR_700_get_tag_neg_state(struct scsi_device *SDp) 156 { 157 return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3); 158 } 159 160 static inline void 161 NCR_700_set_tag_neg_state(struct scsi_device *SDp, 162 enum NCR_700_tag_neg_state state) 163 { 164 /* clear the slot */ 165 spi_flags(SDp->sdev_target) &= ~(0x3 << 20); 166 spi_flags(SDp->sdev_target) |= ((__u32)state) << 20; 167 } 168 169 struct NCR_700_command_slot { 170 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1]; 171 struct NCR_700_SG_List *pSG; 172 #define NCR_700_SLOT_MASK 0xFC 173 #define NCR_700_SLOT_MAGIC 0xb8 174 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */ 175 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */ 176 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */ 177 __u8 state; 178 #define NCR_700_FLAG_AUTOSENSE 0x01 179 __u8 flags; 180 __u8 pad1[2]; /* Needed for m68k where min alignment is 2 bytes */ 181 int tag; 182 __u32 resume_offset; 183 struct scsi_cmnd *cmnd; 184 /* The pci_mapped address of the actual command in cmnd */ 185 dma_addr_t pCmd; 186 __u32 temp; 187 /* if this command is a pci_single mapping, holds the dma address 188 * for later unmapping in the done routine */ 189 dma_addr_t dma_handle; 190 /* historical remnant, now used to link free commands */ 191 struct NCR_700_command_slot *ITL_forw; 192 }; 193 194 struct NCR_700_Host_Parameters { 195 /* These must be filled in by the calling driver */ 196 int clock; /* board clock speed in MHz */ 197 void __iomem *base; /* the base for the port (copied to host) */ 198 struct device *dev; 199 __u32 dmode_extra; /* adjustable bus settings */ 200 __u32 dcntl_extra; /* adjustable bus settings */ 201 __u32 ctest7_extra; /* adjustable bus settings */ 202 __u32 differential:1; /* if we are differential */ 203 #ifdef CONFIG_53C700_LE_ON_BE 204 /* This option is for HP only. Set it if your chip is wired for 205 * little endian on this platform (which is big endian) */ 206 __u32 force_le_on_be:1; 207 #endif 208 __u32 chip710:1; /* set if really a 710 not 700 */ 209 __u32 burst_length:4; /* set to 0 to disable 710 bursting */ 210 211 /* NOTHING BELOW HERE NEEDS ALTERING */ 212 __u32 fast:1; /* if we can alter the SCSI bus clock 213 speed (so can negiotiate sync) */ 214 int sync_clock; /* The speed of the SYNC core */ 215 216 __u32 *script; /* pointer to script location */ 217 __u32 pScript; /* physical mem addr of script */ 218 219 enum NCR_700_Host_State state; /* protected by state lock */ 220 struct scsi_cmnd *cmd; 221 /* Note: pScript contains the single consistent block of 222 * memory. All the msgin, msgout and status are allocated in 223 * this memory too (at separate cache lines). TOTAL_MEM_SIZE 224 * represents the total size of this area */ 225 #define MSG_ARRAY_SIZE 8 226 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT))) 227 __u8 *msgout; 228 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 229 __u8 *msgin; 230 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 231 __u8 *status; 232 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 233 struct NCR_700_command_slot *slots; 234 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST)) 235 int saved_slot_position; 236 int command_slot_count; /* protected by state lock */ 237 __u8 tag_negotiated; 238 __u8 rev; 239 __u8 reselection_id; 240 __u8 min_period; 241 242 /* Free list, singly linked by ITL_forw elements */ 243 struct NCR_700_command_slot *free_list; 244 /* Completion for waited for ops, like reset, abort or 245 * device reset. 246 * 247 * NOTE: relies on single threading in the error handler to 248 * have only one outstanding at once */ 249 struct completion *eh_complete; 250 }; 251 252 /* 253 * 53C700 Register Interface - the offset from the Selected base 254 * I/O address */ 255 #ifdef CONFIG_53C700_LE_ON_BE 256 #define bE (hostdata->force_le_on_be ? 0 : 3) 257 #define bSWAP (hostdata->force_le_on_be) 258 #define bEBus (!hostdata->force_le_on_be) 259 #elif defined(__BIG_ENDIAN) 260 #define bE 3 261 #define bSWAP 0 262 #elif defined(__LITTLE_ENDIAN) 263 #define bE 0 264 #define bSWAP 0 265 #else 266 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?" 267 #endif 268 #ifndef bEBus 269 #ifdef CONFIG_53C700_BE_BUS 270 #define bEBus 1 271 #else 272 #define bEBus 0 273 #endif 274 #endif 275 #define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x)) 276 #define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x)) 277 278 /* NOTE: These registers are in the LE register space only, the required byte 279 * swapping is done by the NCR_700_{read|write}[b] functions */ 280 #define SCNTL0_REG 0x00 281 #define FULL_ARBITRATION 0xc0 282 #define PARITY 0x08 283 #define ENABLE_PARITY 0x04 284 #define AUTO_ATN 0x02 285 #define SCNTL1_REG 0x01 286 #define SLOW_BUS 0x80 287 #define ENABLE_SELECT 0x20 288 #define ASSERT_RST 0x08 289 #define ASSERT_EVEN_PARITY 0x04 290 #define SDID_REG 0x02 291 #define SIEN_REG 0x03 292 #define PHASE_MM_INT 0x80 293 #define FUNC_COMP_INT 0x40 294 #define SEL_TIMEOUT_INT 0x20 295 #define SELECT_INT 0x10 296 #define GROSS_ERR_INT 0x08 297 #define UX_DISC_INT 0x04 298 #define RST_INT 0x02 299 #define PAR_ERR_INT 0x01 300 #define SCID_REG 0x04 301 #define SXFER_REG 0x05 302 #define ASYNC_OPERATION 0x00 303 #define SODL_REG 0x06 304 #define SOCL_REG 0x07 305 #define SFBR_REG 0x08 306 #define SIDL_REG 0x09 307 #define SBDL_REG 0x0A 308 #define SBCL_REG 0x0B 309 /* read bits */ 310 #define SBCL_IO 0x01 311 /*write bits */ 312 #define SYNC_DIV_AS_ASYNC 0x00 313 #define SYNC_DIV_1_0 0x01 314 #define SYNC_DIV_1_5 0x02 315 #define SYNC_DIV_2_0 0x03 316 #define DSTAT_REG 0x0C 317 #define ILGL_INST_DETECTED 0x01 318 #define WATCH_DOG_INTERRUPT 0x02 319 #define SCRIPT_INT_RECEIVED 0x04 320 #define ABORTED 0x10 321 #define SSTAT0_REG 0x0D 322 #define PARITY_ERROR 0x01 323 #define SCSI_RESET_DETECTED 0x02 324 #define UNEXPECTED_DISCONNECT 0x04 325 #define SCSI_GROSS_ERROR 0x08 326 #define SELECTED 0x10 327 #define SELECTION_TIMEOUT 0x20 328 #define FUNCTION_COMPLETE 0x40 329 #define PHASE_MISMATCH 0x80 330 #define SSTAT1_REG 0x0E 331 #define SIDL_REG_FULL 0x80 332 #define SODR_REG_FULL 0x40 333 #define SODL_REG_FULL 0x20 334 #define SSTAT2_REG 0x0F 335 #define CTEST0_REG 0x14 336 #define BTB_TIMER_DISABLE 0x40 337 #define CTEST1_REG 0x15 338 #define CTEST2_REG 0x16 339 #define CTEST3_REG 0x17 340 #define CTEST4_REG 0x18 341 #define DISABLE_FIFO 0x00 342 #define SLBE 0x10 343 #define SFWR 0x08 344 #define BYTE_LANE0 0x04 345 #define BYTE_LANE1 0x05 346 #define BYTE_LANE2 0x06 347 #define BYTE_LANE3 0x07 348 #define SCSI_ZMODE 0x20 349 #define ZMODE 0x40 350 #define CTEST5_REG 0x19 351 #define MASTER_CONTROL 0x10 352 #define DMA_DIRECTION 0x08 353 #define CTEST7_REG 0x1B 354 #define BURST_DISABLE 0x80 /* 710 only */ 355 #define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */ 356 #define DFP 0x08 357 #define EVP 0x04 358 #define CTEST7_TT1 0x02 359 #define DIFF 0x01 360 #define CTEST6_REG 0x1A 361 #define TEMP_REG 0x1C 362 #define DFIFO_REG 0x20 363 #define FLUSH_DMA_FIFO 0x80 364 #define CLR_FIFO 0x40 365 #define ISTAT_REG 0x21 366 #define ABORT_OPERATION 0x80 367 #define SOFTWARE_RESET_710 0x40 368 #define DMA_INT_PENDING 0x01 369 #define SCSI_INT_PENDING 0x02 370 #define CONNECTED 0x08 371 #define CTEST8_REG 0x22 372 #define LAST_DIS_ENBL 0x01 373 #define SHORTEN_FILTERING 0x04 374 #define ENABLE_ACTIVE_NEGATION 0x10 375 #define GENERATE_RECEIVE_PARITY 0x20 376 #define CLR_FIFO_710 0x04 377 #define FLUSH_DMA_FIFO_710 0x08 378 #define CTEST9_REG 0x23 379 #define DBC_REG 0x24 380 #define DCMD_REG 0x27 381 #define DNAD_REG 0x28 382 #define DIEN_REG 0x39 383 #define BUS_FAULT 0x20 384 #define ABORT_INT 0x10 385 #define INT_INST_INT 0x04 386 #define WD_INT 0x02 387 #define ILGL_INST_INT 0x01 388 #define DCNTL_REG 0x3B 389 #define SOFTWARE_RESET 0x01 390 #define COMPAT_700_MODE 0x01 391 #define SCRPTS_16BITS 0x20 392 #define EA_710 0x20 393 #define ASYNC_DIV_2_0 0x00 394 #define ASYNC_DIV_1_5 0x40 395 #define ASYNC_DIV_1_0 0x80 396 #define ASYNC_DIV_3_0 0xc0 397 #define DMODE_710_REG 0x38 398 #define DMODE_700_REG 0x34 399 #define BURST_LENGTH_1 0x00 400 #define BURST_LENGTH_2 0x40 401 #define BURST_LENGTH_4 0x80 402 #define BURST_LENGTH_8 0xC0 403 #define DMODE_FC1 0x10 404 #define DMODE_FC2 0x20 405 #define BW16 32 406 #define MODE_286 16 407 #define IO_XFER 8 408 #define FIXED_ADDR 4 409 410 #define DSP_REG 0x2C 411 #define DSPS_REG 0x30 412 413 /* Parameters to begin SDTR negotiations. Empirically, I find that 414 * the 53c700-66 cannot handle an offset >8, so don't change this */ 415 #define NCR_700_MAX_OFFSET 8 416 /* Was hoping the max offset would be greater for the 710, but 417 * empirically it seems to be 8 also */ 418 #define NCR_710_MAX_OFFSET 8 419 #define NCR_700_MIN_XFERP 1 420 #define NCR_710_MIN_XFERP 0 421 #define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */ 422 423 #define script_patch_32(dev, script, symbol, value) \ 424 { \ 425 int i; \ 426 dma_addr_t da = value; \ 427 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 428 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + da; \ 429 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 430 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 431 DEBUG((" script, patching %s at %d to %pad\n", \ 432 #symbol, A_##symbol##_used[i], &da)); \ 433 } \ 434 } 435 436 #define script_patch_32_abs(dev, script, symbol, value) \ 437 { \ 438 int i; \ 439 dma_addr_t da = value; \ 440 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 441 (script)[A_##symbol##_used[i]] = bS_to_host(da); \ 442 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 443 DEBUG((" script, patching %s at %d to %pad\n", \ 444 #symbol, A_##symbol##_used[i], &da)); \ 445 } \ 446 } 447 448 /* Used for patching the SCSI ID in the SELECT instruction */ 449 #define script_patch_ID(dev, script, symbol, value) \ 450 { \ 451 int i; \ 452 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 453 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ 454 val &= 0xff00ffff; \ 455 val |= ((value) & 0xff) << 16; \ 456 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 457 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 458 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \ 459 #symbol, A_##symbol##_used[i], val)); \ 460 } \ 461 } 462 463 #define script_patch_16(dev, script, symbol, value) \ 464 { \ 465 int i; \ 466 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 467 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ 468 val &= 0xffff0000; \ 469 val |= ((value) & 0xffff); \ 470 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 471 dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 472 DEBUG((" script, patching short field %s at %d to 0x%x\n", \ 473 #symbol, A_##symbol##_used[i], val)); \ 474 } \ 475 } 476 477 478 static inline __u8 479 NCR_700_readb(struct Scsi_Host *host, __u32 reg) 480 { 481 const struct NCR_700_Host_Parameters *hostdata 482 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 483 484 return ioread8(hostdata->base + (reg^bE)); 485 } 486 487 static inline __u32 488 NCR_700_readl(struct Scsi_Host *host, __u32 reg) 489 { 490 const struct NCR_700_Host_Parameters *hostdata 491 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 492 __u32 value = bEBus ? ioread32be(hostdata->base + reg) : 493 ioread32(hostdata->base + reg); 494 #if 1 495 /* sanity check the register */ 496 BUG_ON((reg & 0x3) != 0); 497 #endif 498 499 return value; 500 } 501 502 static inline void 503 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg) 504 { 505 const struct NCR_700_Host_Parameters *hostdata 506 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 507 508 iowrite8(value, hostdata->base + (reg^bE)); 509 } 510 511 static inline void 512 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg) 513 { 514 const struct NCR_700_Host_Parameters *hostdata 515 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 516 517 #if 1 518 /* sanity check the register */ 519 BUG_ON((reg & 0x3) != 0); 520 #endif 521 522 bEBus ? iowrite32be(value, hostdata->base + reg): 523 iowrite32(value, hostdata->base + reg); 524 } 525 526 #endif 527