1 /* -*- mode: c; c-basic-offset: 8 -*- */ 2 3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios 4 * 5 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com 6 */ 7 8 #ifndef _53C700_H 9 #define _53C700_H 10 11 #include <linux/interrupt.h> 12 #include <asm/io.h> 13 14 #include <scsi/scsi_device.h> 15 16 17 #if defined(CONFIG_53C700_MEM_MAPPED) && defined(CONFIG_53C700_IO_MAPPED) 18 #define CONFIG_53C700_BOTH_MAPPED 19 #endif 20 21 /* Turn on for general debugging---too verbose for normal use */ 22 #undef NCR_700_DEBUG 23 /* Debug the tag queues, checking hash queue allocation and deallocation 24 * and search for duplicate tags */ 25 #undef NCR_700_TAG_DEBUG 26 27 #ifdef NCR_700_DEBUG 28 #define DEBUG(x) printk x 29 #else 30 #define DEBUG(x) 31 #endif 32 33 /* The number of available command slots */ 34 #define NCR_700_COMMAND_SLOTS_PER_HOST 64 35 /* The maximum number of Scatter Gathers we allow */ 36 #define NCR_700_SG_SEGMENTS 32 37 /* The maximum number of luns (make this of the form 2^n) */ 38 #define NCR_700_MAX_LUNS 32 39 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1) 40 /* Maximum number of tags the driver ever allows per device */ 41 #define NCR_700_MAX_TAGS 16 42 /* Tag depth the driver starts out with (can be altered in sysfs) */ 43 #define NCR_700_DEFAULT_TAGS 4 44 /* This is the default number of commands per LUN in the untagged case. 45 * two is a good value because it means we can have one command active and 46 * one command fully prepared and waiting 47 */ 48 #define NCR_700_CMD_PER_LUN 2 49 /* magic byte identifying an internally generated REQUEST_SENSE command */ 50 #define NCR_700_INTERNAL_SENSE_MAGIC 0x42 51 52 /* WARNING: Leave this in for now: the dependency preprocessor doesn't 53 * pick up file specific flags, so must define here if they are not 54 * set */ 55 #if !defined(CONFIG_53C700_IO_MAPPED) && !defined(CONFIG_53C700_MEM_MAPPED) 56 #error "Config.in must define either CONFIG_53C700_IO_MAPPED or CONFIG_53C700_MEM_MAPPED to use this scsi core." 57 #endif 58 59 struct NCR_700_Host_Parameters; 60 61 /* These are the externally used routines */ 62 struct Scsi_Host *NCR_700_detect(struct scsi_host_template *, 63 struct NCR_700_Host_Parameters *, struct device *); 64 int NCR_700_release(struct Scsi_Host *host); 65 irqreturn_t NCR_700_intr(int, void *, struct pt_regs *); 66 67 68 enum NCR_700_Host_State { 69 NCR_700_HOST_BUSY, 70 NCR_700_HOST_FREE, 71 }; 72 73 struct NCR_700_SG_List { 74 /* The following is a script fragment to move the buffer onto the 75 * bus and then link the next fragment or return */ 76 #define SCRIPT_MOVE_DATA_IN 0x09000000 77 #define SCRIPT_MOVE_DATA_OUT 0x08000000 78 __u32 ins; 79 __u32 pAddr; 80 #define SCRIPT_NOP 0x80000000 81 #define SCRIPT_RETURN 0x90080000 82 }; 83 84 /* We use device->hostdata to store negotiated parameters. This is 85 * supposed to be a pointer to a device private area, but we cannot 86 * really use it as such since it will never be freed, so just use the 87 * 32 bits to cram the information. The SYNC negotiation sequence looks 88 * like: 89 * 90 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the 91 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION 92 * If we get an SDTR reply, work out the SXFER parameters, squirrel 93 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set 94 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel 95 * 96 * 97 * 0:7 SXFER_REG negotiated value for this device 98 * 8:15 Current queue depth 99 * 16 negotiated SYNC flag 100 * 17 begin SYNC negotiation flag 101 * 18 device supports tag queueing */ 102 #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16) 103 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17) 104 #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19) 105 106 static inline void 107 NCR_700_set_depth(struct scsi_device *SDp, __u8 depth) 108 { 109 long l = (long)SDp->hostdata; 110 111 l &= 0xffff00ff; 112 l |= 0xff00 & (depth << 8); 113 SDp->hostdata = (void *)l; 114 } 115 static inline __u8 116 NCR_700_get_depth(struct scsi_device *SDp) 117 { 118 return ((((unsigned long)SDp->hostdata) & 0xff00)>>8); 119 } 120 static inline int 121 NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag) 122 { 123 return (spi_flags(SDp->sdev_target) & flag) == flag; 124 } 125 static inline int 126 NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag) 127 { 128 return (spi_flags(SDp->sdev_target) & flag) == 0; 129 } 130 static inline void 131 NCR_700_set_flag(struct scsi_device *SDp, __u32 flag) 132 { 133 spi_flags(SDp->sdev_target) |= flag; 134 } 135 static inline void 136 NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag) 137 { 138 spi_flags(SDp->sdev_target) &= ~flag; 139 } 140 141 enum NCR_700_tag_neg_state { 142 NCR_700_START_TAG_NEGOTIATION = 0, 143 NCR_700_DURING_TAG_NEGOTIATION = 1, 144 NCR_700_FINISHED_TAG_NEGOTIATION = 2, 145 }; 146 147 static inline enum NCR_700_tag_neg_state 148 NCR_700_get_tag_neg_state(struct scsi_device *SDp) 149 { 150 return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3); 151 } 152 153 static inline void 154 NCR_700_set_tag_neg_state(struct scsi_device *SDp, 155 enum NCR_700_tag_neg_state state) 156 { 157 /* clear the slot */ 158 spi_flags(SDp->sdev_target) &= ~(0x3 << 20); 159 spi_flags(SDp->sdev_target) |= ((__u32)state) << 20; 160 } 161 162 struct NCR_700_command_slot { 163 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1]; 164 struct NCR_700_SG_List *pSG; 165 #define NCR_700_SLOT_MASK 0xFC 166 #define NCR_700_SLOT_MAGIC 0xb8 167 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */ 168 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */ 169 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */ 170 __u8 state; 171 int tag; 172 __u32 resume_offset; 173 struct scsi_cmnd *cmnd; 174 /* The pci_mapped address of the actual command in cmnd */ 175 dma_addr_t pCmd; 176 __u32 temp; 177 /* if this command is a pci_single mapping, holds the dma address 178 * for later unmapping in the done routine */ 179 dma_addr_t dma_handle; 180 /* historical remnant, now used to link free commands */ 181 struct NCR_700_command_slot *ITL_forw; 182 }; 183 184 struct NCR_700_Host_Parameters { 185 /* These must be filled in by the calling driver */ 186 int clock; /* board clock speed in MHz */ 187 unsigned long base; /* the base for the port (copied to host) */ 188 struct device *dev; 189 __u32 dmode_extra; /* adjustable bus settings */ 190 __u32 differential:1; /* if we are differential */ 191 #ifdef CONFIG_53C700_LE_ON_BE 192 /* This option is for HP only. Set it if your chip is wired for 193 * little endian on this platform (which is big endian) */ 194 __u32 force_le_on_be:1; 195 #endif 196 __u32 chip710:1; /* set if really a 710 not 700 */ 197 __u32 burst_disable:1; /* set to 1 to disable 710 bursting */ 198 199 /* NOTHING BELOW HERE NEEDS ALTERING */ 200 __u32 fast:1; /* if we can alter the SCSI bus clock 201 speed (so can negiotiate sync) */ 202 #ifdef CONFIG_53C700_BOTH_MAPPED 203 __u32 mem_mapped; /* set if memory mapped */ 204 #endif 205 int sync_clock; /* The speed of the SYNC core */ 206 207 __u32 *script; /* pointer to script location */ 208 __u32 pScript; /* physical mem addr of script */ 209 210 enum NCR_700_Host_State state; /* protected by state lock */ 211 struct scsi_cmnd *cmd; 212 /* Note: pScript contains the single consistent block of 213 * memory. All the msgin, msgout and status are allocated in 214 * this memory too (at separate cache lines). TOTAL_MEM_SIZE 215 * represents the total size of this area */ 216 #define MSG_ARRAY_SIZE 8 217 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT))) 218 __u8 *msgout; 219 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 220 __u8 *msgin; 221 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 222 __u8 *status; 223 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 224 struct NCR_700_command_slot *slots; 225 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST)) 226 int saved_slot_position; 227 int command_slot_count; /* protected by state lock */ 228 __u8 tag_negotiated; 229 __u8 rev; 230 __u8 reselection_id; 231 __u8 min_period; 232 233 /* Free list, singly linked by ITL_forw elements */ 234 struct NCR_700_command_slot *free_list; 235 /* Completion for waited for ops, like reset, abort or 236 * device reset. 237 * 238 * NOTE: relies on single threading in the error handler to 239 * have only one outstanding at once */ 240 struct completion *eh_complete; 241 }; 242 243 /* 244 * 53C700 Register Interface - the offset from the Selected base 245 * I/O address */ 246 #ifdef CONFIG_53C700_LE_ON_BE 247 #define bE (hostdata->force_le_on_be ? 0 : 3) 248 #define bSWAP (hostdata->force_le_on_be) 249 #elif defined(__BIG_ENDIAN) 250 #define bE 3 251 #define bSWAP 0 252 #elif defined(__LITTLE_ENDIAN) 253 #define bE 0 254 #define bSWAP 0 255 #else 256 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?" 257 #endif 258 #define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x)) 259 #define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x)) 260 261 /* NOTE: These registers are in the LE register space only, the required byte 262 * swapping is done by the NCR_700_{read|write}[b] functions */ 263 #define SCNTL0_REG 0x00 264 #define FULL_ARBITRATION 0xc0 265 #define PARITY 0x08 266 #define ENABLE_PARITY 0x04 267 #define AUTO_ATN 0x02 268 #define SCNTL1_REG 0x01 269 #define SLOW_BUS 0x80 270 #define ENABLE_SELECT 0x20 271 #define ASSERT_RST 0x08 272 #define ASSERT_EVEN_PARITY 0x04 273 #define SDID_REG 0x02 274 #define SIEN_REG 0x03 275 #define PHASE_MM_INT 0x80 276 #define FUNC_COMP_INT 0x40 277 #define SEL_TIMEOUT_INT 0x20 278 #define SELECT_INT 0x10 279 #define GROSS_ERR_INT 0x08 280 #define UX_DISC_INT 0x04 281 #define RST_INT 0x02 282 #define PAR_ERR_INT 0x01 283 #define SCID_REG 0x04 284 #define SXFER_REG 0x05 285 #define ASYNC_OPERATION 0x00 286 #define SODL_REG 0x06 287 #define SOCL_REG 0x07 288 #define SFBR_REG 0x08 289 #define SIDL_REG 0x09 290 #define SBDL_REG 0x0A 291 #define SBCL_REG 0x0B 292 /* read bits */ 293 #define SBCL_IO 0x01 294 /*write bits */ 295 #define SYNC_DIV_AS_ASYNC 0x00 296 #define SYNC_DIV_1_0 0x01 297 #define SYNC_DIV_1_5 0x02 298 #define SYNC_DIV_2_0 0x03 299 #define DSTAT_REG 0x0C 300 #define ILGL_INST_DETECTED 0x01 301 #define WATCH_DOG_INTERRUPT 0x02 302 #define SCRIPT_INT_RECEIVED 0x04 303 #define ABORTED 0x10 304 #define SSTAT0_REG 0x0D 305 #define PARITY_ERROR 0x01 306 #define SCSI_RESET_DETECTED 0x02 307 #define UNEXPECTED_DISCONNECT 0x04 308 #define SCSI_GROSS_ERROR 0x08 309 #define SELECTED 0x10 310 #define SELECTION_TIMEOUT 0x20 311 #define FUNCTION_COMPLETE 0x40 312 #define PHASE_MISMATCH 0x80 313 #define SSTAT1_REG 0x0E 314 #define SIDL_REG_FULL 0x80 315 #define SODR_REG_FULL 0x40 316 #define SODL_REG_FULL 0x20 317 #define SSTAT2_REG 0x0F 318 #define CTEST0_REG 0x14 319 #define BTB_TIMER_DISABLE 0x40 320 #define CTEST1_REG 0x15 321 #define CTEST2_REG 0x16 322 #define CTEST3_REG 0x17 323 #define CTEST4_REG 0x18 324 #define DISABLE_FIFO 0x00 325 #define SLBE 0x10 326 #define SFWR 0x08 327 #define BYTE_LANE0 0x04 328 #define BYTE_LANE1 0x05 329 #define BYTE_LANE2 0x06 330 #define BYTE_LANE3 0x07 331 #define SCSI_ZMODE 0x20 332 #define ZMODE 0x40 333 #define CTEST5_REG 0x19 334 #define MASTER_CONTROL 0x10 335 #define DMA_DIRECTION 0x08 336 #define CTEST7_REG 0x1B 337 #define BURST_DISABLE 0x80 /* 710 only */ 338 #define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */ 339 #define DFP 0x08 340 #define EVP 0x04 341 #define DIFF 0x01 342 #define CTEST6_REG 0x1A 343 #define TEMP_REG 0x1C 344 #define DFIFO_REG 0x20 345 #define FLUSH_DMA_FIFO 0x80 346 #define CLR_FIFO 0x40 347 #define ISTAT_REG 0x21 348 #define ABORT_OPERATION 0x80 349 #define SOFTWARE_RESET_710 0x40 350 #define DMA_INT_PENDING 0x01 351 #define SCSI_INT_PENDING 0x02 352 #define CONNECTED 0x08 353 #define CTEST8_REG 0x22 354 #define LAST_DIS_ENBL 0x01 355 #define SHORTEN_FILTERING 0x04 356 #define ENABLE_ACTIVE_NEGATION 0x10 357 #define GENERATE_RECEIVE_PARITY 0x20 358 #define CLR_FIFO_710 0x04 359 #define FLUSH_DMA_FIFO_710 0x08 360 #define CTEST9_REG 0x23 361 #define DBC_REG 0x24 362 #define DCMD_REG 0x27 363 #define DNAD_REG 0x28 364 #define DIEN_REG 0x39 365 #define BUS_FAULT 0x20 366 #define ABORT_INT 0x10 367 #define INT_INST_INT 0x04 368 #define WD_INT 0x02 369 #define ILGL_INST_INT 0x01 370 #define DCNTL_REG 0x3B 371 #define SOFTWARE_RESET 0x01 372 #define COMPAT_700_MODE 0x01 373 #define SCRPTS_16BITS 0x20 374 #define ASYNC_DIV_2_0 0x00 375 #define ASYNC_DIV_1_5 0x40 376 #define ASYNC_DIV_1_0 0x80 377 #define ASYNC_DIV_3_0 0xc0 378 #define DMODE_710_REG 0x38 379 #define DMODE_700_REG 0x34 380 #define BURST_LENGTH_1 0x00 381 #define BURST_LENGTH_2 0x40 382 #define BURST_LENGTH_4 0x80 383 #define BURST_LENGTH_8 0xC0 384 #define DMODE_FC1 0x10 385 #define DMODE_FC2 0x20 386 #define BW16 32 387 #define MODE_286 16 388 #define IO_XFER 8 389 #define FIXED_ADDR 4 390 391 #define DSP_REG 0x2C 392 #define DSPS_REG 0x30 393 394 /* Parameters to begin SDTR negotiations. Empirically, I find that 395 * the 53c700-66 cannot handle an offset >8, so don't change this */ 396 #define NCR_700_MAX_OFFSET 8 397 /* Was hoping the max offset would be greater for the 710, but 398 * empirically it seems to be 8 also */ 399 #define NCR_710_MAX_OFFSET 8 400 #define NCR_700_MIN_XFERP 1 401 #define NCR_710_MIN_XFERP 0 402 #define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */ 403 404 #define script_patch_32(script, symbol, value) \ 405 { \ 406 int i; \ 407 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 408 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + value; \ 409 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 410 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 411 DEBUG((" script, patching %s at %d to 0x%lx\n", \ 412 #symbol, A_##symbol##_used[i], (value))); \ 413 } \ 414 } 415 416 #define script_patch_32_abs(script, symbol, value) \ 417 { \ 418 int i; \ 419 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 420 (script)[A_##symbol##_used[i]] = bS_to_host(value); \ 421 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 422 DEBUG((" script, patching %s at %d to 0x%lx\n", \ 423 #symbol, A_##symbol##_used[i], (value))); \ 424 } \ 425 } 426 427 /* Used for patching the SCSI ID in the SELECT instruction */ 428 #define script_patch_ID(script, symbol, value) \ 429 { \ 430 int i; \ 431 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 432 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ 433 val &= 0xff00ffff; \ 434 val |= ((value) & 0xff) << 16; \ 435 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 436 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 437 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \ 438 #symbol, A_##symbol##_used[i], val)); \ 439 } \ 440 } 441 442 #define script_patch_16(script, symbol, value) \ 443 { \ 444 int i; \ 445 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 446 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ 447 val &= 0xffff0000; \ 448 val |= ((value) & 0xffff); \ 449 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 450 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 451 DEBUG((" script, patching short field %s at %d to 0x%x\n", \ 452 #symbol, A_##symbol##_used[i], val)); \ 453 } \ 454 } 455 456 457 static inline __u8 458 NCR_700_mem_readb(struct Scsi_Host *host, __u32 reg) 459 { 460 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 461 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 462 463 return readb(host->base + (reg^bE)); 464 } 465 466 static inline __u32 467 NCR_700_mem_readl(struct Scsi_Host *host, __u32 reg) 468 { 469 __u32 value = __raw_readl(host->base + reg); 470 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 471 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 472 #if 1 473 /* sanity check the register */ 474 if((reg & 0x3) != 0) 475 BUG(); 476 #endif 477 478 return bS_to_cpu(value); 479 } 480 481 static inline void 482 NCR_700_mem_writeb(__u8 value, struct Scsi_Host *host, __u32 reg) 483 { 484 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 485 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 486 487 writeb(value, host->base + (reg^bE)); 488 } 489 490 static inline void 491 NCR_700_mem_writel(__u32 value, struct Scsi_Host *host, __u32 reg) 492 { 493 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 494 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 495 496 #if 1 497 /* sanity check the register */ 498 if((reg & 0x3) != 0) 499 BUG(); 500 #endif 501 502 __raw_writel(bS_to_host(value), host->base + reg); 503 } 504 505 static inline __u8 506 NCR_700_io_readb(struct Scsi_Host *host, __u32 reg) 507 { 508 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 509 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 510 511 return inb(host->base + (reg^bE)); 512 } 513 514 static inline __u32 515 NCR_700_io_readl(struct Scsi_Host *host, __u32 reg) 516 { 517 __u32 value = inl(host->base + reg); 518 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 519 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 520 521 #if 1 522 /* sanity check the register */ 523 if((reg & 0x3) != 0) 524 BUG(); 525 #endif 526 527 return bS_to_cpu(value); 528 } 529 530 static inline void 531 NCR_700_io_writeb(__u8 value, struct Scsi_Host *host, __u32 reg) 532 { 533 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 534 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 535 536 outb(value, host->base + (reg^bE)); 537 } 538 539 static inline void 540 NCR_700_io_writel(__u32 value, struct Scsi_Host *host, __u32 reg) 541 { 542 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 543 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 544 545 #if 1 546 /* sanity check the register */ 547 if((reg & 0x3) != 0) 548 BUG(); 549 #endif 550 551 outl(bS_to_host(value), host->base + reg); 552 } 553 554 #ifdef CONFIG_53C700_BOTH_MAPPED 555 556 static inline __u8 557 NCR_700_readb(struct Scsi_Host *host, __u32 reg) 558 { 559 __u8 val; 560 561 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 562 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 563 564 if(hostdata->mem_mapped) 565 val = NCR_700_mem_readb(host, reg); 566 else 567 val = NCR_700_io_readb(host, reg); 568 569 return val; 570 } 571 572 static inline __u32 573 NCR_700_readl(struct Scsi_Host *host, __u32 reg) 574 { 575 __u32 val; 576 577 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 578 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 579 580 if(hostdata->mem_mapped) 581 val = NCR_700_mem_readl(host, reg); 582 else 583 val = NCR_700_io_readl(host, reg); 584 585 return val; 586 } 587 588 static inline void 589 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg) 590 { 591 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 592 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 593 594 if(hostdata->mem_mapped) 595 NCR_700_mem_writeb(value, host, reg); 596 else 597 NCR_700_io_writeb(value, host, reg); 598 } 599 600 static inline void 601 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg) 602 { 603 const struct NCR_700_Host_Parameters *hostdata __attribute__((unused)) 604 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 605 606 if(hostdata->mem_mapped) 607 NCR_700_mem_writel(value, host, reg); 608 else 609 NCR_700_io_writel(value, host, reg); 610 } 611 612 static inline void 613 NCR_700_set_mem_mapped(struct NCR_700_Host_Parameters *hostdata) 614 { 615 hostdata->mem_mapped = 1; 616 } 617 618 static inline void 619 NCR_700_set_io_mapped(struct NCR_700_Host_Parameters *hostdata) 620 { 621 hostdata->mem_mapped = 0; 622 } 623 624 625 #elif defined(CONFIG_53C700_IO_MAPPED) 626 627 #define NCR_700_readb NCR_700_io_readb 628 #define NCR_700_readl NCR_700_io_readl 629 #define NCR_700_writeb NCR_700_io_writeb 630 #define NCR_700_writel NCR_700_io_writel 631 632 #define NCR_700_set_io_mapped(x) 633 #define NCR_700_set_mem_mapped(x) error I/O mapped only 634 635 #elif defined(CONFIG_53C700_MEM_MAPPED) 636 637 #define NCR_700_readb NCR_700_mem_readb 638 #define NCR_700_readl NCR_700_mem_readl 639 #define NCR_700_writeb NCR_700_mem_writeb 640 #define NCR_700_writel NCR_700_mem_writel 641 642 #define NCR_700_set_io_mapped(x) error MEM mapped only 643 #define NCR_700_set_mem_mapped(x) 644 645 #else 646 #error neither CONFIG_53C700_MEM_MAPPED nor CONFIG_53C700_IO_MAPPED is set 647 #endif 648 649 #endif 650