1 /* 2 3w-9xxx.h -- 3ware 9000 Storage Controller device driver for Linux. 3 4 Written By: Adam Radford <linuxraid@amcc.com> 5 Modifications By: Tom Couch <linuxraid@amcc.com> 6 7 Copyright (C) 2004-2008 Applied Micro Circuits Corporation. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; version 2 of the License. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 NO WARRANTY 19 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 20 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 21 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 22 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 23 solely responsible for determining the appropriateness of using and 24 distributing the Program and assumes all risks associated with its 25 exercise of rights under this Agreement, including but not limited to 26 the risks and costs of program errors, damage to or loss of data, 27 programs or equipment, and unavailability or interruption of operations. 28 29 DISCLAIMER OF LIABILITY 30 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 31 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 33 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 34 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 35 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 36 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 37 38 You should have received a copy of the GNU General Public License 39 along with this program; if not, write to the Free Software 40 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 41 42 Bugs/Comments/Suggestions should be mailed to: 43 linuxraid@amcc.com 44 45 For more information, goto: 46 http://www.amcc.com 47 */ 48 49 #ifndef _3W_9XXX_H 50 #define _3W_9XXX_H 51 52 /* AEN string type */ 53 typedef struct TAG_twa_message_type { 54 unsigned int code; 55 char* text; 56 } twa_message_type; 57 58 /* AEN strings */ 59 static twa_message_type twa_aen_table[] = { 60 {0x0000, "AEN queue empty"}, 61 {0x0001, "Controller reset occurred"}, 62 {0x0002, "Degraded unit detected"}, 63 {0x0003, "Controller error occured"}, 64 {0x0004, "Background rebuild failed"}, 65 {0x0005, "Background rebuild done"}, 66 {0x0006, "Incomplete unit detected"}, 67 {0x0007, "Background initialize done"}, 68 {0x0008, "Unclean shutdown detected"}, 69 {0x0009, "Drive timeout detected"}, 70 {0x000A, "Drive error detected"}, 71 {0x000B, "Rebuild started"}, 72 {0x000C, "Background initialize started"}, 73 {0x000D, "Entire logical unit was deleted"}, 74 {0x000E, "Background initialize failed"}, 75 {0x000F, "SMART attribute exceeded threshold"}, 76 {0x0010, "Power supply reported AC under range"}, 77 {0x0011, "Power supply reported DC out of range"}, 78 {0x0012, "Power supply reported a malfunction"}, 79 {0x0013, "Power supply predicted malfunction"}, 80 {0x0014, "Battery charge is below threshold"}, 81 {0x0015, "Fan speed is below threshold"}, 82 {0x0016, "Temperature sensor is above threshold"}, 83 {0x0017, "Power supply was removed"}, 84 {0x0018, "Power supply was inserted"}, 85 {0x0019, "Drive was removed from a bay"}, 86 {0x001A, "Drive was inserted into a bay"}, 87 {0x001B, "Drive bay cover door was opened"}, 88 {0x001C, "Drive bay cover door was closed"}, 89 {0x001D, "Product case was opened"}, 90 {0x0020, "Prepare for shutdown (power-off)"}, 91 {0x0021, "Downgrade UDMA mode to lower speed"}, 92 {0x0022, "Upgrade UDMA mode to higher speed"}, 93 {0x0023, "Sector repair completed"}, 94 {0x0024, "Sbuf memory test failed"}, 95 {0x0025, "Error flushing cached write data to array"}, 96 {0x0026, "Drive reported data ECC error"}, 97 {0x0027, "DCB has checksum error"}, 98 {0x0028, "DCB version is unsupported"}, 99 {0x0029, "Background verify started"}, 100 {0x002A, "Background verify failed"}, 101 {0x002B, "Background verify done"}, 102 {0x002C, "Bad sector overwritten during rebuild"}, 103 {0x002D, "Background rebuild error on source drive"}, 104 {0x002E, "Replace failed because replacement drive too small"}, 105 {0x002F, "Verify failed because array was never initialized"}, 106 {0x0030, "Unsupported ATA drive"}, 107 {0x0031, "Synchronize host/controller time"}, 108 {0x0032, "Spare capacity is inadequate for some units"}, 109 {0x0033, "Background migration started"}, 110 {0x0034, "Background migration failed"}, 111 {0x0035, "Background migration done"}, 112 {0x0036, "Verify detected and fixed data/parity mismatch"}, 113 {0x0037, "SO-DIMM incompatible"}, 114 {0x0038, "SO-DIMM not detected"}, 115 {0x0039, "Corrected Sbuf ECC error"}, 116 {0x003A, "Drive power on reset detected"}, 117 {0x003B, "Background rebuild paused"}, 118 {0x003C, "Background initialize paused"}, 119 {0x003D, "Background verify paused"}, 120 {0x003E, "Background migration paused"}, 121 {0x003F, "Corrupt flash file system detected"}, 122 {0x0040, "Flash file system repaired"}, 123 {0x0041, "Unit number assignments were lost"}, 124 {0x0042, "Error during read of primary DCB"}, 125 {0x0043, "Latent error found in backup DCB"}, 126 {0x00FC, "Recovered/finished array membership update"}, 127 {0x00FD, "Handler lockup"}, 128 {0x00FE, "Retrying PCI transfer"}, 129 {0x00FF, "AEN queue is full"}, 130 {0xFFFFFFFF, (char*) 0} 131 }; 132 133 /* AEN severity table */ 134 static char *twa_aen_severity_table[] = 135 { 136 "None", "ERROR", "WARNING", "INFO", "DEBUG", (char*) 0 137 }; 138 139 /* Error strings */ 140 static twa_message_type twa_error_table[] = { 141 {0x0100, "SGL entry contains zero data"}, 142 {0x0101, "Invalid command opcode"}, 143 {0x0102, "SGL entry has unaligned address"}, 144 {0x0103, "SGL size does not match command"}, 145 {0x0104, "SGL entry has illegal length"}, 146 {0x0105, "Command packet is not aligned"}, 147 {0x0106, "Invalid request ID"}, 148 {0x0107, "Duplicate request ID"}, 149 {0x0108, "ID not locked"}, 150 {0x0109, "LBA out of range"}, 151 {0x010A, "Logical unit not supported"}, 152 {0x010B, "Parameter table does not exist"}, 153 {0x010C, "Parameter index does not exist"}, 154 {0x010D, "Invalid field in CDB"}, 155 {0x010E, "Specified port has invalid drive"}, 156 {0x010F, "Parameter item size mismatch"}, 157 {0x0110, "Failed memory allocation"}, 158 {0x0111, "Memory request too large"}, 159 {0x0112, "Out of memory segments"}, 160 {0x0113, "Invalid address to deallocate"}, 161 {0x0114, "Out of memory"}, 162 {0x0115, "Out of heap"}, 163 {0x0120, "Double degrade"}, 164 {0x0121, "Drive not degraded"}, 165 {0x0122, "Reconstruct error"}, 166 {0x0123, "Replace not accepted"}, 167 {0x0124, "Replace drive capacity too small"}, 168 {0x0125, "Sector count not allowed"}, 169 {0x0126, "No spares left"}, 170 {0x0127, "Reconstruct error"}, 171 {0x0128, "Unit is offline"}, 172 {0x0129, "Cannot update status to DCB"}, 173 {0x0130, "Invalid stripe handle"}, 174 {0x0131, "Handle that was not locked"}, 175 {0x0132, "Handle that was not empty"}, 176 {0x0133, "Handle has different owner"}, 177 {0x0140, "IPR has parent"}, 178 {0x0150, "Illegal Pbuf address alignment"}, 179 {0x0151, "Illegal Pbuf transfer length"}, 180 {0x0152, "Illegal Sbuf address alignment"}, 181 {0x0153, "Illegal Sbuf transfer length"}, 182 {0x0160, "Command packet too large"}, 183 {0x0161, "SGL exceeds maximum length"}, 184 {0x0162, "SGL has too many entries"}, 185 {0x0170, "Insufficient resources for rebuilder"}, 186 {0x0171, "Verify error (data != parity)"}, 187 {0x0180, "Requested segment not in directory of this DCB"}, 188 {0x0181, "DCB segment has unsupported version"}, 189 {0x0182, "DCB segment has checksum error"}, 190 {0x0183, "DCB support (settings) segment invalid"}, 191 {0x0184, "DCB UDB (unit descriptor block) segment invalid"}, 192 {0x0185, "DCB GUID (globally unique identifier) segment invalid"}, 193 {0x01A0, "Could not clear Sbuf"}, 194 {0x01C0, "Flash identify failed"}, 195 {0x01C1, "Flash out of bounds"}, 196 {0x01C2, "Flash verify error"}, 197 {0x01C3, "Flash file object not found"}, 198 {0x01C4, "Flash file already present"}, 199 {0x01C5, "Flash file system full"}, 200 {0x01C6, "Flash file not present"}, 201 {0x01C7, "Flash file size error"}, 202 {0x01C8, "Bad flash file checksum"}, 203 {0x01CA, "Corrupt flash file system detected"}, 204 {0x01D0, "Invalid field in parameter list"}, 205 {0x01D1, "Parameter list length error"}, 206 {0x01D2, "Parameter item is not changeable"}, 207 {0x01D3, "Parameter item is not saveable"}, 208 {0x0200, "UDMA CRC error"}, 209 {0x0201, "Internal CRC error"}, 210 {0x0202, "Data ECC error"}, 211 {0x0203, "ADP level 1 error"}, 212 {0x0204, "Port timeout"}, 213 {0x0205, "Drive power on reset"}, 214 {0x0206, "ADP level 2 error"}, 215 {0x0207, "Soft reset failed"}, 216 {0x0208, "Drive not ready"}, 217 {0x0209, "Unclassified port error"}, 218 {0x020A, "Drive aborted command"}, 219 {0x0210, "Internal CRC error"}, 220 {0x0211, "PCI abort error"}, 221 {0x0212, "PCI parity error"}, 222 {0x0213, "Port handler error"}, 223 {0x0214, "Token interrupt count error"}, 224 {0x0215, "Timeout waiting for PCI transfer"}, 225 {0x0216, "Corrected buffer ECC"}, 226 {0x0217, "Uncorrected buffer ECC"}, 227 {0x0230, "Unsupported command during flash recovery"}, 228 {0x0231, "Next image buffer expected"}, 229 {0x0232, "Binary image architecture incompatible"}, 230 {0x0233, "Binary image has no signature"}, 231 {0x0234, "Binary image has bad checksum"}, 232 {0x0235, "Image downloaded overflowed buffer"}, 233 {0x0240, "I2C device not found"}, 234 {0x0241, "I2C transaction aborted"}, 235 {0x0242, "SO-DIMM parameter(s) incompatible using defaults"}, 236 {0x0243, "SO-DIMM unsupported"}, 237 {0x0248, "SPI transfer status error"}, 238 {0x0249, "SPI transfer timeout error"}, 239 {0x0250, "Invalid unit descriptor size in CreateUnit"}, 240 {0x0251, "Unit descriptor size exceeds data buffer in CreateUnit"}, 241 {0x0252, "Invalid value in CreateUnit descriptor"}, 242 {0x0253, "Inadequate disk space to support descriptor in CreateUnit"}, 243 {0x0254, "Unable to create data channel for this unit descriptor"}, 244 {0x0255, "CreateUnit descriptor specifies a drive already in use"}, 245 {0x0256, "Unable to write configuration to all disks during CreateUnit"}, 246 {0x0257, "CreateUnit does not support this descriptor version"}, 247 {0x0258, "Invalid subunit for RAID 0 or 5 in CreateUnit"}, 248 {0x0259, "Too many descriptors in CreateUnit"}, 249 {0x025A, "Invalid configuration specified in CreateUnit descriptor"}, 250 {0x025B, "Invalid LBA offset specified in CreateUnit descriptor"}, 251 {0x025C, "Invalid stripelet size specified in CreateUnit descriptor"}, 252 {0x0260, "SMART attribute exceeded threshold"}, 253 {0xFFFFFFFF, (char*) 0} 254 }; 255 256 /* Control register bit definitions */ 257 #define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 258 #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 259 #define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 260 #define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 261 #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 262 #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 263 #define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200 264 #define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100 265 #define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080 266 #define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040 267 #define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 268 #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000 269 #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 270 #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000 271 272 /* Status register bit definitions */ 273 #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000 274 #define TW_STATUS_MINOR_VERSION_MASK 0x0F000000 275 #define TW_STATUS_PCI_PARITY_ERROR 0x00800000 276 #define TW_STATUS_QUEUE_ERROR 0x00400000 277 #define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000 278 #define TW_STATUS_PCI_ABORT 0x00100000 279 #define TW_STATUS_HOST_INTERRUPT 0x00080000 280 #define TW_STATUS_ATTENTION_INTERRUPT 0x00040000 281 #define TW_STATUS_COMMAND_INTERRUPT 0x00020000 282 #define TW_STATUS_RESPONSE_INTERRUPT 0x00010000 283 #define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000 284 #define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 285 #define TW_STATUS_MICROCONTROLLER_READY 0x00002000 286 #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 287 #define TW_STATUS_EXPECTED_BITS 0x00002000 288 #define TW_STATUS_UNEXPECTED_BITS 0x00F00000 289 #define TW_STATUS_VALID_INTERRUPT 0x00DF0000 290 291 /* PCI related defines */ 292 #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100 293 #define TW_PCI_CLEAR_PCI_ABORT 0x2000 294 295 /* Command packet opcodes used by the driver */ 296 #define TW_OP_INIT_CONNECTION 0x1 297 #define TW_OP_GET_PARAM 0x12 298 #define TW_OP_SET_PARAM 0x13 299 #define TW_OP_EXECUTE_SCSI 0x10 300 #define TW_OP_DOWNLOAD_FIRMWARE 0x16 301 #define TW_OP_RESET 0x1C 302 303 /* Asynchronous Event Notification (AEN) codes used by the driver */ 304 #define TW_AEN_QUEUE_EMPTY 0x0000 305 #define TW_AEN_SOFT_RESET 0x0001 306 #define TW_AEN_SYNC_TIME_WITH_HOST 0x031 307 #define TW_AEN_SEVERITY_ERROR 0x1 308 #define TW_AEN_SEVERITY_DEBUG 0x4 309 #define TW_AEN_NOT_RETRIEVED 0x1 310 #define TW_AEN_RETRIEVED 0x2 311 312 /* Command state defines */ 313 #define TW_S_INITIAL 0x1 /* Initial state */ 314 #define TW_S_STARTED 0x2 /* Id in use */ 315 #define TW_S_POSTED 0x4 /* Posted to the controller */ 316 #define TW_S_PENDING 0x8 /* Waiting to be posted in isr */ 317 #define TW_S_COMPLETED 0x10 /* Completed by isr */ 318 #define TW_S_FINISHED 0x20 /* I/O completely done */ 319 320 /* Compatibility defines */ 321 #define TW_9000_ARCH_ID 0x5 322 #define TW_CURRENT_DRIVER_SRL 35 323 #define TW_CURRENT_DRIVER_BUILD 0 324 #define TW_CURRENT_DRIVER_BRANCH 0 325 326 /* Phase defines */ 327 #define TW_PHASE_INITIAL 0 328 #define TW_PHASE_SINGLE 1 329 #define TW_PHASE_SGLIST 2 330 331 /* Misc defines */ 332 #define TW_9550SX_DRAIN_COMPLETED 0xFFFF 333 #define TW_SECTOR_SIZE 512 334 #define TW_ALIGNMENT_9000 4 /* 4 bytes */ 335 #define TW_ALIGNMENT_9000_SGL 0x3 336 #define TW_MAX_UNITS 16 337 #define TW_MAX_UNITS_9650SE 32 338 #define TW_INIT_MESSAGE_CREDITS 0x100 339 #define TW_INIT_COMMAND_PACKET_SIZE 0x3 340 #define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED 0x6 341 #define TW_EXTENDED_INIT_CONNECT 0x2 342 #define TW_BUNDLED_FW_SAFE_TO_FLASH 0x4 343 #define TW_CTLR_FW_RECOMMENDS_FLASH 0x8 344 #define TW_CTLR_FW_COMPATIBLE 0x2 345 #define TW_BASE_FW_SRL 24 346 #define TW_BASE_FW_BRANCH 0 347 #define TW_BASE_FW_BUILD 1 348 #define TW_FW_SRL_LUNS_SUPPORTED 28 349 #define TW_Q_LENGTH 256 350 #define TW_Q_START 0 351 #define TW_MAX_SLOT 32 352 #define TW_MAX_RESET_TRIES 2 353 #define TW_MAX_CMDS_PER_LUN 254 354 #define TW_MAX_RESPONSE_DRAIN 256 355 #define TW_MAX_AEN_DRAIN 255 356 #define TW_IN_RESET 2 357 #define TW_USING_MSI 3 358 #define TW_IN_ATTENTION_LOOP 4 359 #define TW_MAX_SECTORS 256 360 #define TW_AEN_WAIT_TIME 1000 361 #define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */ 362 #define TW_MAX_CDB_LEN 16 363 #define TW_ISR_DONT_COMPLETE 2 364 #define TW_ISR_DONT_RESULT 3 365 #define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */ 366 #define TW_IOCTL_CHRDEV_FREE -1 367 #define TW_COMMAND_OFFSET 128 /* 128 bytes */ 368 #define TW_VERSION_TABLE 0x0402 369 #define TW_TIMEKEEP_TABLE 0x040A 370 #define TW_INFORMATION_TABLE 0x0403 371 #define TW_PARAM_FWVER 3 372 #define TW_PARAM_FWVER_LENGTH 16 373 #define TW_PARAM_BIOSVER 4 374 #define TW_PARAM_BIOSVER_LENGTH 16 375 #define TW_PARAM_PORTCOUNT 3 376 #define TW_PARAM_PORTCOUNT_LENGTH 1 377 #define TW_MIN_SGL_LENGTH 0x200 /* 512 bytes */ 378 #define TW_MAX_SENSE_LENGTH 256 379 #define TW_EVENT_SOURCE_AEN 0x1000 380 #define TW_EVENT_SOURCE_COMMAND 0x1001 381 #define TW_EVENT_SOURCE_PCHIP 0x1002 382 #define TW_EVENT_SOURCE_DRIVER 0x1003 383 #define TW_IOCTL_GET_COMPATIBILITY_INFO 0x101 384 #define TW_IOCTL_GET_LAST_EVENT 0x102 385 #define TW_IOCTL_GET_FIRST_EVENT 0x103 386 #define TW_IOCTL_GET_NEXT_EVENT 0x104 387 #define TW_IOCTL_GET_PREVIOUS_EVENT 0x105 388 #define TW_IOCTL_GET_LOCK 0x106 389 #define TW_IOCTL_RELEASE_LOCK 0x107 390 #define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108 391 #define TW_IOCTL_ERROR_STATUS_NOT_LOCKED 0x1001 // Not locked 392 #define TW_IOCTL_ERROR_STATUS_LOCKED 0x1002 // Already locked 393 #define TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS 0x1003 // No more events 394 #define TW_IOCTL_ERROR_STATUS_AEN_CLOBBER 0x1004 // AEN clobber occurred 395 #define TW_IOCTL_ERROR_OS_EFAULT -EFAULT // Bad address 396 #define TW_IOCTL_ERROR_OS_EINTR -EINTR // Interrupted system call 397 #define TW_IOCTL_ERROR_OS_EINVAL -EINVAL // Invalid argument 398 #define TW_IOCTL_ERROR_OS_ENOMEM -ENOMEM // Out of memory 399 #define TW_IOCTL_ERROR_OS_ERESTARTSYS -ERESTARTSYS // Restart system call 400 #define TW_IOCTL_ERROR_OS_EIO -EIO // I/O error 401 #define TW_IOCTL_ERROR_OS_ENOTTY -ENOTTY // Not a typewriter 402 #define TW_IOCTL_ERROR_OS_ENODEV -ENODEV // No such device 403 #define TW_ALLOCATION_LENGTH 128 404 #define TW_SENSE_DATA_LENGTH 18 405 #define TW_STATUS_CHECK_CONDITION 2 406 #define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a 407 #define TW_ERROR_UNIT_OFFLINE 0x128 408 #define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3 409 #define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4 410 #define TW_MESSAGE_SOURCE_LINUX_DRIVER 6 411 #define TW_DRIVER TW_MESSAGE_SOURCE_LINUX_DRIVER 412 #define TW_MESSAGE_SOURCE_LINUX_OS 9 413 #define TW_OS TW_MESSAGE_SOURCE_LINUX_OS 414 #ifndef PCI_DEVICE_ID_3WARE_9000 415 #define PCI_DEVICE_ID_3WARE_9000 0x1002 416 #endif 417 #ifndef PCI_DEVICE_ID_3WARE_9550SX 418 #define PCI_DEVICE_ID_3WARE_9550SX 0x1003 419 #endif 420 #ifndef PCI_DEVICE_ID_3WARE_9650SE 421 #define PCI_DEVICE_ID_3WARE_9650SE 0x1004 422 #endif 423 #ifndef PCI_DEVICE_ID_3WARE_9690SA 424 #define PCI_DEVICE_ID_3WARE_9690SA 0x1005 425 #endif 426 427 /* Bitmask macros to eliminate bitfields */ 428 429 /* opcode: 5, reserved: 3 */ 430 #define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f)) 431 #define TW_OP_OUT(x) (x & 0x1f) 432 433 /* opcode: 5, sgloffset: 3 */ 434 #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f)) 435 #define TW_SGL_OUT(x) ((x >> 5) & 0x7) 436 437 /* severity: 3, reserved: 5 */ 438 #define TW_SEV_OUT(x) (x & 0x7) 439 440 /* reserved_1: 4, response_id: 8, reserved_2: 20 */ 441 #define TW_RESID_OUT(x) ((x >> 4) & 0xff) 442 443 /* request_id: 12, lun: 4 */ 444 #define TW_REQ_LUN_IN(lun, request_id) (((lun << 12) & 0xf000) | (request_id & 0xfff)) 445 #define TW_LUN_OUT(lun) ((lun >> 12) & 0xf) 446 447 /* Macros */ 448 #define TW_CONTROL_REG_ADDR(x) (x->base_addr) 449 #define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4) 450 #define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8)) 451 #define TW_COMMAND_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x20) 452 #define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC) 453 #define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30) 454 #define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 455 #define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 456 #define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 457 #define TW_DISABLE_INTERRUPTS(x) (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) 458 #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) 459 #define TW_MASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 460 #define TW_UNMASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 461 #define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \ 462 TW_CONTROL_CLEAR_HOST_INTERRUPT | \ 463 TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ 464 TW_CONTROL_MASK_COMMAND_INTERRUPT | \ 465 TW_CONTROL_MASK_RESPONSE_INTERRUPT | \ 466 TW_CONTROL_CLEAR_ERROR_STATUS | \ 467 TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) 468 #define TW_PRINTK(h,a,b,c) { \ 469 if (h) \ 470 printk(KERN_WARNING "3w-9xxx: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \ 471 else \ 472 printk(KERN_WARNING "3w-9xxx: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \ 473 } 474 #define TW_MAX_LUNS(srl) (srl < TW_FW_SRL_LUNS_SUPPORTED ? 1 : 16) 475 #define TW_COMMAND_SIZE (sizeof(dma_addr_t) > 4 ? 5 : 4) 476 #define TW_APACHE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 72 : 109) 477 #define TW_ESCALADE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 41 : 62) 478 #define TW_PADDING_LENGTH (sizeof(dma_addr_t) > 4 ? 8 : 0) 479 #define TW_CPU_TO_SGL(x) (sizeof(dma_addr_t) > 4 ? cpu_to_le64(x) : cpu_to_le32(x)) 480 481 #pragma pack(1) 482 483 /* Scatter Gather List Entry */ 484 typedef struct TAG_TW_SG_Entry { 485 dma_addr_t address; 486 u32 length; 487 } TW_SG_Entry; 488 489 /* Command Packet */ 490 typedef struct TW_Command { 491 unsigned char opcode__sgloffset; 492 unsigned char size; 493 unsigned char request_id; 494 unsigned char unit__hostid; 495 /* Second DWORD */ 496 unsigned char status; 497 unsigned char flags; 498 union { 499 unsigned short block_count; 500 unsigned short parameter_count; 501 } byte6_offset; 502 union { 503 struct { 504 u32 lba; 505 TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; 506 dma_addr_t padding; 507 } io; 508 struct { 509 TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; 510 u32 padding; 511 dma_addr_t padding2; 512 } param; 513 } byte8_offset; 514 } TW_Command; 515 516 /* Command Packet for 9000+ controllers */ 517 typedef struct TAG_TW_Command_Apache { 518 unsigned char opcode__reserved; 519 unsigned char unit; 520 unsigned short request_id__lunl; 521 unsigned char status; 522 unsigned char sgl_offset; 523 unsigned short sgl_entries__lunh; 524 unsigned char cdb[16]; 525 TW_SG_Entry sg_list[TW_APACHE_MAX_SGL_LENGTH]; 526 unsigned char padding[TW_PADDING_LENGTH]; 527 } TW_Command_Apache; 528 529 /* New command packet header */ 530 typedef struct TAG_TW_Command_Apache_Header { 531 unsigned char sense_data[TW_SENSE_DATA_LENGTH]; 532 struct { 533 char reserved[4]; 534 unsigned short error; 535 unsigned char padding; 536 unsigned char severity__reserved; 537 } status_block; 538 unsigned char err_specific_desc[98]; 539 struct { 540 unsigned char size_header; 541 unsigned short reserved; 542 unsigned char size_sense; 543 } header_desc; 544 } TW_Command_Apache_Header; 545 546 /* This struct is a union of the 2 command packets */ 547 typedef struct TAG_TW_Command_Full { 548 TW_Command_Apache_Header header; 549 union { 550 TW_Command oldcommand; 551 TW_Command_Apache newcommand; 552 } command; 553 } TW_Command_Full; 554 555 /* Initconnection structure */ 556 typedef struct TAG_TW_Initconnect { 557 unsigned char opcode__reserved; 558 unsigned char size; 559 unsigned char request_id; 560 unsigned char res2; 561 unsigned char status; 562 unsigned char flags; 563 unsigned short message_credits; 564 u32 features; 565 unsigned short fw_srl; 566 unsigned short fw_arch_id; 567 unsigned short fw_branch; 568 unsigned short fw_build; 569 u32 result; 570 } TW_Initconnect; 571 572 /* Event info structure */ 573 typedef struct TAG_TW_Event 574 { 575 unsigned int sequence_id; 576 unsigned int time_stamp_sec; 577 unsigned short aen_code; 578 unsigned char severity; 579 unsigned char retrieved; 580 unsigned char repeat_count; 581 unsigned char parameter_len; 582 unsigned char parameter_data[98]; 583 } TW_Event; 584 585 typedef struct TAG_TW_Ioctl_Driver_Command { 586 unsigned int control_code; 587 unsigned int status; 588 unsigned int unique_id; 589 unsigned int sequence_id; 590 unsigned int os_specific; 591 unsigned int buffer_length; 592 } TW_Ioctl_Driver_Command; 593 594 typedef struct TAG_TW_Ioctl_Apache { 595 TW_Ioctl_Driver_Command driver_command; 596 char padding[488]; 597 TW_Command_Full firmware_command; 598 char data_buffer[1]; 599 } TW_Ioctl_Buf_Apache; 600 601 /* Lock structure for ioctl get/release lock */ 602 typedef struct TAG_TW_Lock { 603 unsigned long timeout_msec; 604 unsigned long time_remaining_msec; 605 unsigned long force_flag; 606 } TW_Lock; 607 608 /* GetParam descriptor */ 609 typedef struct { 610 unsigned short table_id; 611 unsigned short parameter_id; 612 unsigned short parameter_size_bytes; 613 unsigned short actual_parameter_size_bytes; 614 unsigned char data[1]; 615 } TW_Param_Apache, *PTW_Param_Apache; 616 617 /* Response queue */ 618 typedef union TAG_TW_Response_Queue { 619 u32 response_id; 620 u32 value; 621 } TW_Response_Queue; 622 623 /* Compatibility information structure */ 624 typedef struct TAG_TW_Compatibility_Info 625 { 626 char driver_version[32]; 627 unsigned short working_srl; 628 unsigned short working_branch; 629 unsigned short working_build; 630 unsigned short driver_srl_high; 631 unsigned short driver_branch_high; 632 unsigned short driver_build_high; 633 unsigned short driver_srl_low; 634 unsigned short driver_branch_low; 635 unsigned short driver_build_low; 636 unsigned short fw_on_ctlr_srl; 637 unsigned short fw_on_ctlr_branch; 638 unsigned short fw_on_ctlr_build; 639 } TW_Compatibility_Info; 640 641 #pragma pack() 642 643 typedef struct TAG_TW_Device_Extension { 644 u32 __iomem *base_addr; 645 unsigned long *generic_buffer_virt[TW_Q_LENGTH]; 646 dma_addr_t generic_buffer_phys[TW_Q_LENGTH]; 647 TW_Command_Full *command_packet_virt[TW_Q_LENGTH]; 648 dma_addr_t command_packet_phys[TW_Q_LENGTH]; 649 struct pci_dev *tw_pci_dev; 650 struct scsi_cmnd *srb[TW_Q_LENGTH]; 651 unsigned char free_queue[TW_Q_LENGTH]; 652 unsigned char free_head; 653 unsigned char free_tail; 654 unsigned char pending_queue[TW_Q_LENGTH]; 655 unsigned char pending_head; 656 unsigned char pending_tail; 657 int state[TW_Q_LENGTH]; 658 unsigned int posted_request_count; 659 unsigned int max_posted_request_count; 660 unsigned int pending_request_count; 661 unsigned int max_pending_request_count; 662 unsigned int max_sgl_entries; 663 unsigned int sgl_entries; 664 unsigned int num_resets; 665 unsigned int sector_count; 666 unsigned int max_sector_count; 667 unsigned int aen_count; 668 struct Scsi_Host *host; 669 long flags; 670 int reset_print; 671 TW_Event *event_queue[TW_Q_LENGTH]; 672 unsigned char error_index; 673 unsigned char event_queue_wrapped; 674 unsigned int error_sequence_id; 675 int ioctl_sem_lock; 676 u32 ioctl_msec; 677 int chrdev_request_id; 678 wait_queue_head_t ioctl_wqueue; 679 struct mutex ioctl_lock; 680 char aen_clobber; 681 TW_Compatibility_Info tw_compat_info; 682 } TW_Device_Extension; 683 684 #endif /* _3W_9XXX_H */ 685 686