1 /* 2 3w-9xxx.h -- 3ware 9000 Storage Controller device driver for Linux. 3 4 Written By: Adam Radford <linuxraid@amcc.com> 5 6 Copyright (C) 2004-2005 Applied Micro Circuits Corporation. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; version 2 of the License. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 NO WARRANTY 18 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 19 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 20 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 21 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 22 solely responsible for determining the appropriateness of using and 23 distributing the Program and assumes all risks associated with its 24 exercise of rights under this Agreement, including but not limited to 25 the risks and costs of program errors, damage to or loss of data, 26 programs or equipment, and unavailability or interruption of operations. 27 28 DISCLAIMER OF LIABILITY 29 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 30 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 32 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 33 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 34 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 35 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 36 37 You should have received a copy of the GNU General Public License 38 along with this program; if not, write to the Free Software 39 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 40 41 Bugs/Comments/Suggestions should be mailed to: 42 linuxraid@amcc.com 43 44 For more information, goto: 45 http://www.amcc.com 46 */ 47 48 #ifndef _3W_9XXX_H 49 #define _3W_9XXX_H 50 51 /* AEN string type */ 52 typedef struct TAG_twa_message_type { 53 unsigned int code; 54 char* text; 55 } twa_message_type; 56 57 /* AEN strings */ 58 static twa_message_type twa_aen_table[] = { 59 {0x0000, "AEN queue empty"}, 60 {0x0001, "Controller reset occurred"}, 61 {0x0002, "Degraded unit detected"}, 62 {0x0003, "Controller error occured"}, 63 {0x0004, "Background rebuild failed"}, 64 {0x0005, "Background rebuild done"}, 65 {0x0006, "Incomplete unit detected"}, 66 {0x0007, "Background initialize done"}, 67 {0x0008, "Unclean shutdown detected"}, 68 {0x0009, "Drive timeout detected"}, 69 {0x000A, "Drive error detected"}, 70 {0x000B, "Rebuild started"}, 71 {0x000C, "Background initialize started"}, 72 {0x000D, "Entire logical unit was deleted"}, 73 {0x000E, "Background initialize failed"}, 74 {0x000F, "SMART attribute exceeded threshold"}, 75 {0x0010, "Power supply reported AC under range"}, 76 {0x0011, "Power supply reported DC out of range"}, 77 {0x0012, "Power supply reported a malfunction"}, 78 {0x0013, "Power supply predicted malfunction"}, 79 {0x0014, "Battery charge is below threshold"}, 80 {0x0015, "Fan speed is below threshold"}, 81 {0x0016, "Temperature sensor is above threshold"}, 82 {0x0017, "Power supply was removed"}, 83 {0x0018, "Power supply was inserted"}, 84 {0x0019, "Drive was removed from a bay"}, 85 {0x001A, "Drive was inserted into a bay"}, 86 {0x001B, "Drive bay cover door was opened"}, 87 {0x001C, "Drive bay cover door was closed"}, 88 {0x001D, "Product case was opened"}, 89 {0x0020, "Prepare for shutdown (power-off)"}, 90 {0x0021, "Downgrade UDMA mode to lower speed"}, 91 {0x0022, "Upgrade UDMA mode to higher speed"}, 92 {0x0023, "Sector repair completed"}, 93 {0x0024, "Sbuf memory test failed"}, 94 {0x0025, "Error flushing cached write data to array"}, 95 {0x0026, "Drive reported data ECC error"}, 96 {0x0027, "DCB has checksum error"}, 97 {0x0028, "DCB version is unsupported"}, 98 {0x0029, "Background verify started"}, 99 {0x002A, "Background verify failed"}, 100 {0x002B, "Background verify done"}, 101 {0x002C, "Bad sector overwritten during rebuild"}, 102 {0x002D, "Background rebuild error on source drive"}, 103 {0x002E, "Replace failed because replacement drive too small"}, 104 {0x002F, "Verify failed because array was never initialized"}, 105 {0x0030, "Unsupported ATA drive"}, 106 {0x0031, "Synchronize host/controller time"}, 107 {0x0032, "Spare capacity is inadequate for some units"}, 108 {0x0033, "Background migration started"}, 109 {0x0034, "Background migration failed"}, 110 {0x0035, "Background migration done"}, 111 {0x0036, "Verify detected and fixed data/parity mismatch"}, 112 {0x0037, "SO-DIMM incompatible"}, 113 {0x0038, "SO-DIMM not detected"}, 114 {0x0039, "Corrected Sbuf ECC error"}, 115 {0x003A, "Drive power on reset detected"}, 116 {0x003B, "Background rebuild paused"}, 117 {0x003C, "Background initialize paused"}, 118 {0x003D, "Background verify paused"}, 119 {0x003E, "Background migration paused"}, 120 {0x003F, "Corrupt flash file system detected"}, 121 {0x0040, "Flash file system repaired"}, 122 {0x0041, "Unit number assignments were lost"}, 123 {0x0042, "Error during read of primary DCB"}, 124 {0x0043, "Latent error found in backup DCB"}, 125 {0x00FC, "Recovered/finished array membership update"}, 126 {0x00FD, "Handler lockup"}, 127 {0x00FE, "Retrying PCI transfer"}, 128 {0x00FF, "AEN queue is full"}, 129 {0xFFFFFFFF, (char*) 0} 130 }; 131 132 /* AEN severity table */ 133 static char *twa_aen_severity_table[] = 134 { 135 "None", "ERROR", "WARNING", "INFO", "DEBUG", (char*) 0 136 }; 137 138 /* Error strings */ 139 static twa_message_type twa_error_table[] = { 140 {0x0100, "SGL entry contains zero data"}, 141 {0x0101, "Invalid command opcode"}, 142 {0x0102, "SGL entry has unaligned address"}, 143 {0x0103, "SGL size does not match command"}, 144 {0x0104, "SGL entry has illegal length"}, 145 {0x0105, "Command packet is not aligned"}, 146 {0x0106, "Invalid request ID"}, 147 {0x0107, "Duplicate request ID"}, 148 {0x0108, "ID not locked"}, 149 {0x0109, "LBA out of range"}, 150 {0x010A, "Logical unit not supported"}, 151 {0x010B, "Parameter table does not exist"}, 152 {0x010C, "Parameter index does not exist"}, 153 {0x010D, "Invalid field in CDB"}, 154 {0x010E, "Specified port has invalid drive"}, 155 {0x010F, "Parameter item size mismatch"}, 156 {0x0110, "Failed memory allocation"}, 157 {0x0111, "Memory request too large"}, 158 {0x0112, "Out of memory segments"}, 159 {0x0113, "Invalid address to deallocate"}, 160 {0x0114, "Out of memory"}, 161 {0x0115, "Out of heap"}, 162 {0x0120, "Double degrade"}, 163 {0x0121, "Drive not degraded"}, 164 {0x0122, "Reconstruct error"}, 165 {0x0123, "Replace not accepted"}, 166 {0x0124, "Replace drive capacity too small"}, 167 {0x0125, "Sector count not allowed"}, 168 {0x0126, "No spares left"}, 169 {0x0127, "Reconstruct error"}, 170 {0x0128, "Unit is offline"}, 171 {0x0129, "Cannot update status to DCB"}, 172 {0x0130, "Invalid stripe handle"}, 173 {0x0131, "Handle that was not locked"}, 174 {0x0132, "Handle that was not empty"}, 175 {0x0133, "Handle has different owner"}, 176 {0x0140, "IPR has parent"}, 177 {0x0150, "Illegal Pbuf address alignment"}, 178 {0x0151, "Illegal Pbuf transfer length"}, 179 {0x0152, "Illegal Sbuf address alignment"}, 180 {0x0153, "Illegal Sbuf transfer length"}, 181 {0x0160, "Command packet too large"}, 182 {0x0161, "SGL exceeds maximum length"}, 183 {0x0162, "SGL has too many entries"}, 184 {0x0170, "Insufficient resources for rebuilder"}, 185 {0x0171, "Verify error (data != parity)"}, 186 {0x0180, "Requested segment not in directory of this DCB"}, 187 {0x0181, "DCB segment has unsupported version"}, 188 {0x0182, "DCB segment has checksum error"}, 189 {0x0183, "DCB support (settings) segment invalid"}, 190 {0x0184, "DCB UDB (unit descriptor block) segment invalid"}, 191 {0x0185, "DCB GUID (globally unique identifier) segment invalid"}, 192 {0x01A0, "Could not clear Sbuf"}, 193 {0x01C0, "Flash identify failed"}, 194 {0x01C1, "Flash out of bounds"}, 195 {0x01C2, "Flash verify error"}, 196 {0x01C3, "Flash file object not found"}, 197 {0x01C4, "Flash file already present"}, 198 {0x01C5, "Flash file system full"}, 199 {0x01C6, "Flash file not present"}, 200 {0x01C7, "Flash file size error"}, 201 {0x01C8, "Bad flash file checksum"}, 202 {0x01CA, "Corrupt flash file system detected"}, 203 {0x01D0, "Invalid field in parameter list"}, 204 {0x01D1, "Parameter list length error"}, 205 {0x01D2, "Parameter item is not changeable"}, 206 {0x01D3, "Parameter item is not saveable"}, 207 {0x0200, "UDMA CRC error"}, 208 {0x0201, "Internal CRC error"}, 209 {0x0202, "Data ECC error"}, 210 {0x0203, "ADP level 1 error"}, 211 {0x0204, "Port timeout"}, 212 {0x0205, "Drive power on reset"}, 213 {0x0206, "ADP level 2 error"}, 214 {0x0207, "Soft reset failed"}, 215 {0x0208, "Drive not ready"}, 216 {0x0209, "Unclassified port error"}, 217 {0x020A, "Drive aborted command"}, 218 {0x0210, "Internal CRC error"}, 219 {0x0211, "PCI abort error"}, 220 {0x0212, "PCI parity error"}, 221 {0x0213, "Port handler error"}, 222 {0x0214, "Token interrupt count error"}, 223 {0x0215, "Timeout waiting for PCI transfer"}, 224 {0x0216, "Corrected buffer ECC"}, 225 {0x0217, "Uncorrected buffer ECC"}, 226 {0x0230, "Unsupported command during flash recovery"}, 227 {0x0231, "Next image buffer expected"}, 228 {0x0232, "Binary image architecture incompatible"}, 229 {0x0233, "Binary image has no signature"}, 230 {0x0234, "Binary image has bad checksum"}, 231 {0x0235, "Image downloaded overflowed buffer"}, 232 {0x0240, "I2C device not found"}, 233 {0x0241, "I2C transaction aborted"}, 234 {0x0242, "SO-DIMM parameter(s) incompatible using defaults"}, 235 {0x0243, "SO-DIMM unsupported"}, 236 {0x0248, "SPI transfer status error"}, 237 {0x0249, "SPI transfer timeout error"}, 238 {0x0250, "Invalid unit descriptor size in CreateUnit"}, 239 {0x0251, "Unit descriptor size exceeds data buffer in CreateUnit"}, 240 {0x0252, "Invalid value in CreateUnit descriptor"}, 241 {0x0253, "Inadequate disk space to support descriptor in CreateUnit"}, 242 {0x0254, "Unable to create data channel for this unit descriptor"}, 243 {0x0255, "CreateUnit descriptor specifies a drive already in use"}, 244 {0x0256, "Unable to write configuration to all disks during CreateUnit"}, 245 {0x0257, "CreateUnit does not support this descriptor version"}, 246 {0x0258, "Invalid subunit for RAID 0 or 5 in CreateUnit"}, 247 {0x0259, "Too many descriptors in CreateUnit"}, 248 {0x025A, "Invalid configuration specified in CreateUnit descriptor"}, 249 {0x025B, "Invalid LBA offset specified in CreateUnit descriptor"}, 250 {0x025C, "Invalid stripelet size specified in CreateUnit descriptor"}, 251 {0x0260, "SMART attribute exceeded threshold"}, 252 {0xFFFFFFFF, (char*) 0} 253 }; 254 255 /* Control register bit definitions */ 256 #define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 257 #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 258 #define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 259 #define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 260 #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 261 #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 262 #define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200 263 #define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100 264 #define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080 265 #define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040 266 #define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 267 #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000 268 #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 269 #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000 270 271 /* Status register bit definitions */ 272 #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000 273 #define TW_STATUS_MINOR_VERSION_MASK 0x0F000000 274 #define TW_STATUS_PCI_PARITY_ERROR 0x00800000 275 #define TW_STATUS_QUEUE_ERROR 0x00400000 276 #define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000 277 #define TW_STATUS_PCI_ABORT 0x00100000 278 #define TW_STATUS_HOST_INTERRUPT 0x00080000 279 #define TW_STATUS_ATTENTION_INTERRUPT 0x00040000 280 #define TW_STATUS_COMMAND_INTERRUPT 0x00020000 281 #define TW_STATUS_RESPONSE_INTERRUPT 0x00010000 282 #define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000 283 #define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 284 #define TW_STATUS_MICROCONTROLLER_READY 0x00002000 285 #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 286 #define TW_STATUS_EXPECTED_BITS 0x00002000 287 #define TW_STATUS_UNEXPECTED_BITS 0x00F00000 288 #define TW_STATUS_VALID_INTERRUPT 0x00DF0000 289 290 /* RESPONSE QUEUE BIT DEFINITIONS */ 291 #define TW_RESPONSE_ID_MASK 0x00000FF0 292 293 /* PCI related defines */ 294 #define TW_NUMDEVICES 1 295 #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100 296 #define TW_PCI_CLEAR_PCI_ABORT 0x2000 297 298 /* Command packet opcodes used by the driver */ 299 #define TW_OP_INIT_CONNECTION 0x1 300 #define TW_OP_GET_PARAM 0x12 301 #define TW_OP_SET_PARAM 0x13 302 #define TW_OP_EXECUTE_SCSI 0x10 303 #define TW_OP_DOWNLOAD_FIRMWARE 0x16 304 #define TW_OP_RESET 0x1C 305 306 /* Asynchronous Event Notification (AEN) codes used by the driver */ 307 #define TW_AEN_QUEUE_EMPTY 0x0000 308 #define TW_AEN_SOFT_RESET 0x0001 309 #define TW_AEN_SYNC_TIME_WITH_HOST 0x031 310 #define TW_AEN_SEVERITY_ERROR 0x1 311 #define TW_AEN_SEVERITY_DEBUG 0x4 312 #define TW_AEN_NOT_RETRIEVED 0x1 313 #define TW_AEN_RETRIEVED 0x2 314 315 /* Command state defines */ 316 #define TW_S_INITIAL 0x1 /* Initial state */ 317 #define TW_S_STARTED 0x2 /* Id in use */ 318 #define TW_S_POSTED 0x4 /* Posted to the controller */ 319 #define TW_S_PENDING 0x8 /* Waiting to be posted in isr */ 320 #define TW_S_COMPLETED 0x10 /* Completed by isr */ 321 #define TW_S_FINISHED 0x20 /* I/O completely done */ 322 323 /* Compatibility defines */ 324 #define TW_9000_ARCH_ID 0x5 325 #define TW_CURRENT_DRIVER_SRL 30 326 #define TW_CURRENT_DRIVER_BUILD 80 327 #define TW_CURRENT_DRIVER_BRANCH 0 328 329 /* Phase defines */ 330 #define TW_PHASE_INITIAL 0 331 #define TW_PHASE_SINGLE 1 332 #define TW_PHASE_SGLIST 2 333 334 /* Misc defines */ 335 #define TW_9550SX_DRAIN_COMPLETED 0xFFFF 336 #define TW_SECTOR_SIZE 512 337 #define TW_ALIGNMENT_9000 4 /* 4 bytes */ 338 #define TW_ALIGNMENT_9000_SGL 0x3 339 #define TW_MAX_UNITS 16 340 #define TW_INIT_MESSAGE_CREDITS 0x100 341 #define TW_INIT_COMMAND_PACKET_SIZE 0x3 342 #define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED 0x6 343 #define TW_EXTENDED_INIT_CONNECT 0x2 344 #define TW_BUNDLED_FW_SAFE_TO_FLASH 0x4 345 #define TW_CTLR_FW_RECOMMENDS_FLASH 0x8 346 #define TW_CTLR_FW_COMPATIBLE 0x2 347 #define TW_BASE_FW_SRL 24 348 #define TW_BASE_FW_BRANCH 0 349 #define TW_BASE_FW_BUILD 1 350 #define TW_FW_SRL_LUNS_SUPPORTED 28 351 #define TW_Q_LENGTH 256 352 #define TW_Q_START 0 353 #define TW_MAX_SLOT 32 354 #define TW_MAX_RESET_TRIES 2 355 #define TW_MAX_CMDS_PER_LUN 254 356 #define TW_MAX_RESPONSE_DRAIN 256 357 #define TW_MAX_AEN_DRAIN 40 358 #define TW_IN_RESET 2 359 #define TW_IN_CHRDEV_IOCTL 3 360 #define TW_IN_ATTENTION_LOOP 4 361 #define TW_MAX_SECTORS 256 362 #define TW_AEN_WAIT_TIME 1000 363 #define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */ 364 #define TW_MAX_CDB_LEN 16 365 #define TW_ISR_DONT_COMPLETE 2 366 #define TW_ISR_DONT_RESULT 3 367 #define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */ 368 #define TW_IOCTL_CHRDEV_FREE -1 369 #define TW_COMMAND_OFFSET 128 /* 128 bytes */ 370 #define TW_VERSION_TABLE 0x0402 371 #define TW_TIMEKEEP_TABLE 0x040A 372 #define TW_INFORMATION_TABLE 0x0403 373 #define TW_PARAM_FWVER 3 374 #define TW_PARAM_FWVER_LENGTH 16 375 #define TW_PARAM_BIOSVER 4 376 #define TW_PARAM_BIOSVER_LENGTH 16 377 #define TW_PARAM_PORTCOUNT 3 378 #define TW_PARAM_PORTCOUNT_LENGTH 1 379 #define TW_MIN_SGL_LENGTH 0x200 /* 512 bytes */ 380 #define TW_MAX_SENSE_LENGTH 256 381 #define TW_EVENT_SOURCE_AEN 0x1000 382 #define TW_EVENT_SOURCE_COMMAND 0x1001 383 #define TW_EVENT_SOURCE_PCHIP 0x1002 384 #define TW_EVENT_SOURCE_DRIVER 0x1003 385 #define TW_IOCTL_GET_COMPATIBILITY_INFO 0x101 386 #define TW_IOCTL_GET_LAST_EVENT 0x102 387 #define TW_IOCTL_GET_FIRST_EVENT 0x103 388 #define TW_IOCTL_GET_NEXT_EVENT 0x104 389 #define TW_IOCTL_GET_PREVIOUS_EVENT 0x105 390 #define TW_IOCTL_GET_LOCK 0x106 391 #define TW_IOCTL_RELEASE_LOCK 0x107 392 #define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108 393 #define TW_IOCTL_ERROR_STATUS_NOT_LOCKED 0x1001 // Not locked 394 #define TW_IOCTL_ERROR_STATUS_LOCKED 0x1002 // Already locked 395 #define TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS 0x1003 // No more events 396 #define TW_IOCTL_ERROR_STATUS_AEN_CLOBBER 0x1004 // AEN clobber occurred 397 #define TW_IOCTL_ERROR_OS_EFAULT -EFAULT // Bad address 398 #define TW_IOCTL_ERROR_OS_EINTR -EINTR // Interrupted system call 399 #define TW_IOCTL_ERROR_OS_EINVAL -EINVAL // Invalid argument 400 #define TW_IOCTL_ERROR_OS_ENOMEM -ENOMEM // Out of memory 401 #define TW_IOCTL_ERROR_OS_ERESTARTSYS -ERESTARTSYS // Restart system call 402 #define TW_IOCTL_ERROR_OS_EIO -EIO // I/O error 403 #define TW_IOCTL_ERROR_OS_ENOTTY -ENOTTY // Not a typewriter 404 #define TW_IOCTL_ERROR_OS_ENODEV -ENODEV // No such device 405 #define TW_ALLOCATION_LENGTH 128 406 #define TW_SENSE_DATA_LENGTH 18 407 #define TW_STATUS_CHECK_CONDITION 2 408 #define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a 409 #define TW_ERROR_UNIT_OFFLINE 0x128 410 #define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3 411 #define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4 412 #define TW_MESSAGE_SOURCE_LINUX_DRIVER 6 413 #define TW_DRIVER TW_MESSAGE_SOURCE_LINUX_DRIVER 414 #define TW_MESSAGE_SOURCE_LINUX_OS 9 415 #define TW_OS TW_MESSAGE_SOURCE_LINUX_OS 416 #ifndef PCI_DEVICE_ID_3WARE_9000 417 #define PCI_DEVICE_ID_3WARE_9000 0x1002 418 #endif 419 #ifndef PCI_DEVICE_ID_3WARE_9550SX 420 #define PCI_DEVICE_ID_3WARE_9550SX 0x1003 421 #endif 422 423 /* Bitmask macros to eliminate bitfields */ 424 425 /* opcode: 5, reserved: 3 */ 426 #define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f)) 427 #define TW_OP_OUT(x) (x & 0x1f) 428 429 /* opcode: 5, sgloffset: 3 */ 430 #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f)) 431 #define TW_SGL_OUT(x) ((x >> 5) & 0x7) 432 433 /* severity: 3, reserved: 5 */ 434 #define TW_SEV_OUT(x) (x & 0x7) 435 436 /* reserved_1: 4, response_id: 8, reserved_2: 20 */ 437 #define TW_RESID_OUT(x) ((x >> 4) & 0xff) 438 439 /* request_id: 12, lun: 4 */ 440 #define TW_REQ_LUN_IN(lun, request_id) (((lun << 12) & 0xf000) | (request_id & 0xfff)) 441 #define TW_LUN_OUT(lun) ((lun >> 12) & 0xf) 442 443 /* Macros */ 444 #define TW_CONTROL_REG_ADDR(x) (x->base_addr) 445 #define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4) 446 #define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8)) 447 #define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC) 448 #define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30) 449 #define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 450 #define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 451 #define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 452 #define TW_DISABLE_INTERRUPTS(x) (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) 453 #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) 454 #define TW_MASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 455 #define TW_UNMASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) 456 #define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \ 457 TW_CONTROL_CLEAR_HOST_INTERRUPT | \ 458 TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ 459 TW_CONTROL_MASK_COMMAND_INTERRUPT | \ 460 TW_CONTROL_MASK_RESPONSE_INTERRUPT | \ 461 TW_CONTROL_CLEAR_ERROR_STATUS | \ 462 TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) 463 #define TW_PRINTK(h,a,b,c) { \ 464 if (h) \ 465 printk(KERN_WARNING "3w-9xxx: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \ 466 else \ 467 printk(KERN_WARNING "3w-9xxx: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \ 468 } 469 #define TW_MAX_LUNS(srl) (srl < TW_FW_SRL_LUNS_SUPPORTED ? 1 : 16) 470 #define TW_COMMAND_SIZE (sizeof(dma_addr_t) > 4 ? 5 : 4) 471 #define TW_APACHE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 72 : 109) 472 #define TW_ESCALADE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 41 : 62) 473 #define TW_PADDING_LENGTH (sizeof(dma_addr_t) > 4 ? 8 : 0) 474 475 #pragma pack(1) 476 477 /* Scatter Gather List Entry */ 478 typedef struct TAG_TW_SG_Entry { 479 dma_addr_t address; 480 u32 length; 481 } TW_SG_Entry; 482 483 /* Command Packet */ 484 typedef struct TW_Command { 485 unsigned char opcode__sgloffset; 486 unsigned char size; 487 unsigned char request_id; 488 unsigned char unit__hostid; 489 /* Second DWORD */ 490 unsigned char status; 491 unsigned char flags; 492 union { 493 unsigned short block_count; 494 unsigned short parameter_count; 495 } byte6_offset; 496 union { 497 struct { 498 u32 lba; 499 TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; 500 dma_addr_t padding; 501 } io; 502 struct { 503 TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH]; 504 u32 padding; 505 dma_addr_t padding2; 506 } param; 507 } byte8_offset; 508 } TW_Command; 509 510 /* Command Packet for 9000+ controllers */ 511 typedef struct TAG_TW_Command_Apache { 512 unsigned char opcode__reserved; 513 unsigned char unit; 514 unsigned short request_id__lunl; 515 unsigned char status; 516 unsigned char sgl_offset; 517 unsigned short sgl_entries__lunh; 518 unsigned char cdb[16]; 519 TW_SG_Entry sg_list[TW_APACHE_MAX_SGL_LENGTH]; 520 unsigned char padding[TW_PADDING_LENGTH]; 521 } TW_Command_Apache; 522 523 /* New command packet header */ 524 typedef struct TAG_TW_Command_Apache_Header { 525 unsigned char sense_data[TW_SENSE_DATA_LENGTH]; 526 struct { 527 char reserved[4]; 528 unsigned short error; 529 unsigned char padding; 530 unsigned char severity__reserved; 531 } status_block; 532 unsigned char err_specific_desc[98]; 533 struct { 534 unsigned char size_header; 535 unsigned short reserved; 536 unsigned char size_sense; 537 } header_desc; 538 } TW_Command_Apache_Header; 539 540 /* This struct is a union of the 2 command packets */ 541 typedef struct TAG_TW_Command_Full { 542 TW_Command_Apache_Header header; 543 union { 544 TW_Command oldcommand; 545 TW_Command_Apache newcommand; 546 } command; 547 } TW_Command_Full; 548 549 /* Initconnection structure */ 550 typedef struct TAG_TW_Initconnect { 551 unsigned char opcode__reserved; 552 unsigned char size; 553 unsigned char request_id; 554 unsigned char res2; 555 unsigned char status; 556 unsigned char flags; 557 unsigned short message_credits; 558 u32 features; 559 unsigned short fw_srl; 560 unsigned short fw_arch_id; 561 unsigned short fw_branch; 562 unsigned short fw_build; 563 u32 result; 564 } TW_Initconnect; 565 566 /* Event info structure */ 567 typedef struct TAG_TW_Event 568 { 569 unsigned int sequence_id; 570 unsigned int time_stamp_sec; 571 unsigned short aen_code; 572 unsigned char severity; 573 unsigned char retrieved; 574 unsigned char repeat_count; 575 unsigned char parameter_len; 576 unsigned char parameter_data[98]; 577 } TW_Event; 578 579 typedef struct TAG_TW_Ioctl_Driver_Command { 580 unsigned int control_code; 581 unsigned int status; 582 unsigned int unique_id; 583 unsigned int sequence_id; 584 unsigned int os_specific; 585 unsigned int buffer_length; 586 } TW_Ioctl_Driver_Command; 587 588 typedef struct TAG_TW_Ioctl_Apache { 589 TW_Ioctl_Driver_Command driver_command; 590 char padding[488]; 591 TW_Command_Full firmware_command; 592 char data_buffer[1]; 593 } TW_Ioctl_Buf_Apache; 594 595 /* Lock structure for ioctl get/release lock */ 596 typedef struct TAG_TW_Lock { 597 unsigned long timeout_msec; 598 unsigned long time_remaining_msec; 599 unsigned long force_flag; 600 } TW_Lock; 601 602 /* GetParam descriptor */ 603 typedef struct { 604 unsigned short table_id; 605 unsigned short parameter_id; 606 unsigned short parameter_size_bytes; 607 unsigned short actual_parameter_size_bytes; 608 unsigned char data[1]; 609 } TW_Param_Apache, *PTW_Param_Apache; 610 611 /* Response queue */ 612 typedef union TAG_TW_Response_Queue { 613 u32 response_id; 614 u32 value; 615 } TW_Response_Queue; 616 617 typedef struct TAG_TW_Info { 618 char *buffer; 619 int length; 620 int offset; 621 int position; 622 } TW_Info; 623 624 /* Compatibility information structure */ 625 typedef struct TAG_TW_Compatibility_Info 626 { 627 char driver_version[32]; 628 unsigned short working_srl; 629 unsigned short working_branch; 630 unsigned short working_build; 631 unsigned short driver_srl_high; 632 unsigned short driver_branch_high; 633 unsigned short driver_build_high; 634 unsigned short driver_srl_low; 635 unsigned short driver_branch_low; 636 unsigned short driver_build_low; 637 } TW_Compatibility_Info; 638 639 typedef struct TAG_TW_Device_Extension { 640 u32 __iomem *base_addr; 641 unsigned long *generic_buffer_virt[TW_Q_LENGTH]; 642 dma_addr_t generic_buffer_phys[TW_Q_LENGTH]; 643 TW_Command_Full *command_packet_virt[TW_Q_LENGTH]; 644 dma_addr_t command_packet_phys[TW_Q_LENGTH]; 645 struct pci_dev *tw_pci_dev; 646 struct scsi_cmnd *srb[TW_Q_LENGTH]; 647 unsigned char free_queue[TW_Q_LENGTH]; 648 unsigned char free_head; 649 unsigned char free_tail; 650 unsigned char pending_queue[TW_Q_LENGTH]; 651 unsigned char pending_head; 652 unsigned char pending_tail; 653 int state[TW_Q_LENGTH]; 654 unsigned int posted_request_count; 655 unsigned int max_posted_request_count; 656 unsigned int pending_request_count; 657 unsigned int max_pending_request_count; 658 unsigned int max_sgl_entries; 659 unsigned int sgl_entries; 660 unsigned int num_resets; 661 unsigned int sector_count; 662 unsigned int max_sector_count; 663 unsigned int aen_count; 664 struct Scsi_Host *host; 665 long flags; 666 int reset_print; 667 TW_Event *event_queue[TW_Q_LENGTH]; 668 unsigned char error_index; 669 unsigned char event_queue_wrapped; 670 unsigned int error_sequence_id; 671 int ioctl_sem_lock; 672 u32 ioctl_msec; 673 int chrdev_request_id; 674 wait_queue_head_t ioctl_wqueue; 675 struct semaphore ioctl_sem; 676 char aen_clobber; 677 unsigned short working_srl; 678 unsigned short working_branch; 679 unsigned short working_build; 680 } TW_Device_Extension; 681 682 #pragma pack() 683 684 #endif /* _3W_9XXX_H */ 685 686