1 /* 2 * drivers/s390/net/qeth_core_main.c 3 * 4 * Copyright IBM Corp. 2007 5 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>, 6 * Frank Pavlic <fpavlic@de.ibm.com>, 7 * Thomas Spatzier <tspat@de.ibm.com>, 8 * Frank Blaschka <frank.blaschka@de.ibm.com> 9 */ 10 11 #define KMSG_COMPONENT "qeth" 12 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/string.h> 17 #include <linux/errno.h> 18 #include <linux/kernel.h> 19 #include <linux/ip.h> 20 #include <linux/tcp.h> 21 #include <linux/mii.h> 22 #include <linux/kthread.h> 23 24 #include <asm/ebcdic.h> 25 #include <asm/io.h> 26 27 #include "qeth_core.h" 28 29 struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = { 30 /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */ 31 /* N P A M L V H */ 32 [QETH_DBF_SETUP] = {"qeth_setup", 33 8, 1, 8, 5, &debug_hex_ascii_view, NULL}, 34 [QETH_DBF_QERR] = {"qeth_qerr", 35 2, 1, 8, 2, &debug_hex_ascii_view, NULL}, 36 [QETH_DBF_TRACE] = {"qeth_trace", 37 4, 1, 8, 3, &debug_hex_ascii_view, NULL}, 38 [QETH_DBF_MSG] = {"qeth_msg", 39 8, 1, 128, 3, &debug_sprintf_view, NULL}, 40 [QETH_DBF_SENSE] = {"qeth_sense", 41 2, 1, 64, 2, &debug_hex_ascii_view, NULL}, 42 [QETH_DBF_MISC] = {"qeth_misc", 43 2, 1, 256, 2, &debug_hex_ascii_view, NULL}, 44 [QETH_DBF_CTRL] = {"qeth_control", 45 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL}, 46 }; 47 EXPORT_SYMBOL_GPL(qeth_dbf); 48 49 struct qeth_card_list_struct qeth_core_card_list; 50 EXPORT_SYMBOL_GPL(qeth_core_card_list); 51 struct kmem_cache *qeth_core_header_cache; 52 EXPORT_SYMBOL_GPL(qeth_core_header_cache); 53 54 static struct device *qeth_core_root_dev; 55 static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY; 56 static struct lock_class_key qdio_out_skb_queue_key; 57 58 static void qeth_send_control_data_cb(struct qeth_channel *, 59 struct qeth_cmd_buffer *); 60 static int qeth_issue_next_read(struct qeth_card *); 61 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *); 62 static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32); 63 static void qeth_free_buffer_pool(struct qeth_card *); 64 static int qeth_qdio_establish(struct qeth_card *); 65 66 67 static inline void __qeth_fill_buffer_frag(struct sk_buff *skb, 68 struct qdio_buffer *buffer, int is_tso, 69 int *next_element_to_fill) 70 { 71 struct skb_frag_struct *frag; 72 int fragno; 73 unsigned long addr; 74 int element, cnt, dlen; 75 76 fragno = skb_shinfo(skb)->nr_frags; 77 element = *next_element_to_fill; 78 dlen = 0; 79 80 if (is_tso) 81 buffer->element[element].flags = 82 SBAL_FLAGS_MIDDLE_FRAG; 83 else 84 buffer->element[element].flags = 85 SBAL_FLAGS_FIRST_FRAG; 86 dlen = skb->len - skb->data_len; 87 if (dlen) { 88 buffer->element[element].addr = skb->data; 89 buffer->element[element].length = dlen; 90 element++; 91 } 92 for (cnt = 0; cnt < fragno; cnt++) { 93 frag = &skb_shinfo(skb)->frags[cnt]; 94 addr = (page_to_pfn(frag->page) << PAGE_SHIFT) + 95 frag->page_offset; 96 buffer->element[element].addr = (char *)addr; 97 buffer->element[element].length = frag->size; 98 if (cnt < (fragno - 1)) 99 buffer->element[element].flags = 100 SBAL_FLAGS_MIDDLE_FRAG; 101 else 102 buffer->element[element].flags = 103 SBAL_FLAGS_LAST_FRAG; 104 element++; 105 } 106 *next_element_to_fill = element; 107 } 108 109 static inline const char *qeth_get_cardname(struct qeth_card *card) 110 { 111 if (card->info.guestlan) { 112 switch (card->info.type) { 113 case QETH_CARD_TYPE_OSAE: 114 return " Guest LAN QDIO"; 115 case QETH_CARD_TYPE_IQD: 116 return " Guest LAN Hiper"; 117 default: 118 return " unknown"; 119 } 120 } else { 121 switch (card->info.type) { 122 case QETH_CARD_TYPE_OSAE: 123 return " OSD Express"; 124 case QETH_CARD_TYPE_IQD: 125 return " HiperSockets"; 126 case QETH_CARD_TYPE_OSN: 127 return " OSN QDIO"; 128 default: 129 return " unknown"; 130 } 131 } 132 return " n/a"; 133 } 134 135 /* max length to be returned: 14 */ 136 const char *qeth_get_cardname_short(struct qeth_card *card) 137 { 138 if (card->info.guestlan) { 139 switch (card->info.type) { 140 case QETH_CARD_TYPE_OSAE: 141 return "GuestLAN QDIO"; 142 case QETH_CARD_TYPE_IQD: 143 return "GuestLAN Hiper"; 144 default: 145 return "unknown"; 146 } 147 } else { 148 switch (card->info.type) { 149 case QETH_CARD_TYPE_OSAE: 150 switch (card->info.link_type) { 151 case QETH_LINK_TYPE_FAST_ETH: 152 return "OSD_100"; 153 case QETH_LINK_TYPE_HSTR: 154 return "HSTR"; 155 case QETH_LINK_TYPE_GBIT_ETH: 156 return "OSD_1000"; 157 case QETH_LINK_TYPE_10GBIT_ETH: 158 return "OSD_10GIG"; 159 case QETH_LINK_TYPE_LANE_ETH100: 160 return "OSD_FE_LANE"; 161 case QETH_LINK_TYPE_LANE_TR: 162 return "OSD_TR_LANE"; 163 case QETH_LINK_TYPE_LANE_ETH1000: 164 return "OSD_GbE_LANE"; 165 case QETH_LINK_TYPE_LANE: 166 return "OSD_ATM_LANE"; 167 default: 168 return "OSD_Express"; 169 } 170 case QETH_CARD_TYPE_IQD: 171 return "HiperSockets"; 172 case QETH_CARD_TYPE_OSN: 173 return "OSN"; 174 default: 175 return "unknown"; 176 } 177 } 178 return "n/a"; 179 } 180 181 void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads, 182 int clear_start_mask) 183 { 184 unsigned long flags; 185 186 spin_lock_irqsave(&card->thread_mask_lock, flags); 187 card->thread_allowed_mask = threads; 188 if (clear_start_mask) 189 card->thread_start_mask &= threads; 190 spin_unlock_irqrestore(&card->thread_mask_lock, flags); 191 wake_up(&card->wait_q); 192 } 193 EXPORT_SYMBOL_GPL(qeth_set_allowed_threads); 194 195 int qeth_threads_running(struct qeth_card *card, unsigned long threads) 196 { 197 unsigned long flags; 198 int rc = 0; 199 200 spin_lock_irqsave(&card->thread_mask_lock, flags); 201 rc = (card->thread_running_mask & threads); 202 spin_unlock_irqrestore(&card->thread_mask_lock, flags); 203 return rc; 204 } 205 EXPORT_SYMBOL_GPL(qeth_threads_running); 206 207 int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads) 208 { 209 return wait_event_interruptible(card->wait_q, 210 qeth_threads_running(card, threads) == 0); 211 } 212 EXPORT_SYMBOL_GPL(qeth_wait_for_threads); 213 214 void qeth_clear_working_pool_list(struct qeth_card *card) 215 { 216 struct qeth_buffer_pool_entry *pool_entry, *tmp; 217 218 QETH_DBF_TEXT(TRACE, 5, "clwrklst"); 219 list_for_each_entry_safe(pool_entry, tmp, 220 &card->qdio.in_buf_pool.entry_list, list){ 221 list_del(&pool_entry->list); 222 } 223 } 224 EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list); 225 226 static int qeth_alloc_buffer_pool(struct qeth_card *card) 227 { 228 struct qeth_buffer_pool_entry *pool_entry; 229 void *ptr; 230 int i, j; 231 232 QETH_DBF_TEXT(TRACE, 5, "alocpool"); 233 for (i = 0; i < card->qdio.init_pool.buf_count; ++i) { 234 pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL); 235 if (!pool_entry) { 236 qeth_free_buffer_pool(card); 237 return -ENOMEM; 238 } 239 for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) { 240 ptr = (void *) __get_free_page(GFP_KERNEL); 241 if (!ptr) { 242 while (j > 0) 243 free_page((unsigned long) 244 pool_entry->elements[--j]); 245 kfree(pool_entry); 246 qeth_free_buffer_pool(card); 247 return -ENOMEM; 248 } 249 pool_entry->elements[j] = ptr; 250 } 251 list_add(&pool_entry->init_list, 252 &card->qdio.init_pool.entry_list); 253 } 254 return 0; 255 } 256 257 int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt) 258 { 259 QETH_DBF_TEXT(TRACE, 2, "realcbp"); 260 261 if ((card->state != CARD_STATE_DOWN) && 262 (card->state != CARD_STATE_RECOVER)) 263 return -EPERM; 264 265 /* TODO: steel/add buffers from/to a running card's buffer pool (?) */ 266 qeth_clear_working_pool_list(card); 267 qeth_free_buffer_pool(card); 268 card->qdio.in_buf_pool.buf_count = bufcnt; 269 card->qdio.init_pool.buf_count = bufcnt; 270 return qeth_alloc_buffer_pool(card); 271 } 272 273 int qeth_set_large_send(struct qeth_card *card, 274 enum qeth_large_send_types type) 275 { 276 int rc = 0; 277 278 if (card->dev == NULL) { 279 card->options.large_send = type; 280 return 0; 281 } 282 if (card->state == CARD_STATE_UP) 283 netif_tx_disable(card->dev); 284 card->options.large_send = type; 285 switch (card->options.large_send) { 286 case QETH_LARGE_SEND_TSO: 287 if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) { 288 card->dev->features |= NETIF_F_TSO | NETIF_F_SG | 289 NETIF_F_HW_CSUM; 290 } else { 291 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | 292 NETIF_F_HW_CSUM); 293 card->options.large_send = QETH_LARGE_SEND_NO; 294 rc = -EOPNOTSUPP; 295 } 296 break; 297 default: /* includes QETH_LARGE_SEND_NO */ 298 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | 299 NETIF_F_HW_CSUM); 300 break; 301 } 302 if (card->state == CARD_STATE_UP) 303 netif_wake_queue(card->dev); 304 return rc; 305 } 306 EXPORT_SYMBOL_GPL(qeth_set_large_send); 307 308 static int qeth_issue_next_read(struct qeth_card *card) 309 { 310 int rc; 311 struct qeth_cmd_buffer *iob; 312 313 QETH_DBF_TEXT(TRACE, 5, "issnxrd"); 314 if (card->read.state != CH_STATE_UP) 315 return -EIO; 316 iob = qeth_get_buffer(&card->read); 317 if (!iob) { 318 dev_warn(&card->gdev->dev, "The qeth device driver " 319 "failed to recover an error on the device\n"); 320 QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob " 321 "available\n", dev_name(&card->gdev->dev)); 322 return -ENOMEM; 323 } 324 qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE); 325 QETH_DBF_TEXT(TRACE, 6, "noirqpnd"); 326 rc = ccw_device_start(card->read.ccwdev, &card->read.ccw, 327 (addr_t) iob, 0, 0); 328 if (rc) { 329 QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! " 330 "rc=%i\n", dev_name(&card->gdev->dev), rc); 331 atomic_set(&card->read.irq_pending, 0); 332 qeth_schedule_recovery(card); 333 wake_up(&card->wait_q); 334 } 335 return rc; 336 } 337 338 static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card) 339 { 340 struct qeth_reply *reply; 341 342 reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC); 343 if (reply) { 344 atomic_set(&reply->refcnt, 1); 345 atomic_set(&reply->received, 0); 346 reply->card = card; 347 }; 348 return reply; 349 } 350 351 static void qeth_get_reply(struct qeth_reply *reply) 352 { 353 WARN_ON(atomic_read(&reply->refcnt) <= 0); 354 atomic_inc(&reply->refcnt); 355 } 356 357 static void qeth_put_reply(struct qeth_reply *reply) 358 { 359 WARN_ON(atomic_read(&reply->refcnt) <= 0); 360 if (atomic_dec_and_test(&reply->refcnt)) 361 kfree(reply); 362 } 363 364 static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc, 365 struct qeth_card *card) 366 { 367 char *ipa_name; 368 int com = cmd->hdr.command; 369 ipa_name = qeth_get_ipa_cmd_name(com); 370 if (rc) 371 QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n", 372 ipa_name, com, QETH_CARD_IFNAME(card), 373 rc, qeth_get_ipa_msg(rc)); 374 else 375 QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n", 376 ipa_name, com, QETH_CARD_IFNAME(card)); 377 } 378 379 static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card, 380 struct qeth_cmd_buffer *iob) 381 { 382 struct qeth_ipa_cmd *cmd = NULL; 383 384 QETH_DBF_TEXT(TRACE, 5, "chkipad"); 385 if (IS_IPA(iob->data)) { 386 cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data); 387 if (IS_IPA_REPLY(cmd)) { 388 if (cmd->hdr.command < IPA_CMD_SETCCID || 389 cmd->hdr.command > IPA_CMD_MODCCID) 390 qeth_issue_ipa_msg(cmd, 391 cmd->hdr.return_code, card); 392 return cmd; 393 } else { 394 switch (cmd->hdr.command) { 395 case IPA_CMD_STOPLAN: 396 dev_warn(&card->gdev->dev, 397 "The link for interface %s on CHPID" 398 " 0x%X failed\n", 399 QETH_CARD_IFNAME(card), 400 card->info.chpid); 401 card->lan_online = 0; 402 if (card->dev && netif_carrier_ok(card->dev)) 403 netif_carrier_off(card->dev); 404 return NULL; 405 case IPA_CMD_STARTLAN: 406 dev_info(&card->gdev->dev, 407 "The link for %s on CHPID 0x%X has" 408 " been restored\n", 409 QETH_CARD_IFNAME(card), 410 card->info.chpid); 411 netif_carrier_on(card->dev); 412 card->lan_online = 1; 413 qeth_schedule_recovery(card); 414 return NULL; 415 case IPA_CMD_MODCCID: 416 return cmd; 417 case IPA_CMD_REGISTER_LOCAL_ADDR: 418 QETH_DBF_TEXT(TRACE, 3, "irla"); 419 break; 420 case IPA_CMD_UNREGISTER_LOCAL_ADDR: 421 QETH_DBF_TEXT(TRACE, 3, "urla"); 422 break; 423 default: 424 QETH_DBF_MESSAGE(2, "Received data is IPA " 425 "but not a reply!\n"); 426 break; 427 } 428 } 429 } 430 return cmd; 431 } 432 433 void qeth_clear_ipacmd_list(struct qeth_card *card) 434 { 435 struct qeth_reply *reply, *r; 436 unsigned long flags; 437 438 QETH_DBF_TEXT(TRACE, 4, "clipalst"); 439 440 spin_lock_irqsave(&card->lock, flags); 441 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) { 442 qeth_get_reply(reply); 443 reply->rc = -EIO; 444 atomic_inc(&reply->received); 445 list_del_init(&reply->list); 446 wake_up(&reply->wait_q); 447 qeth_put_reply(reply); 448 } 449 spin_unlock_irqrestore(&card->lock, flags); 450 } 451 EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list); 452 453 static int qeth_check_idx_response(unsigned char *buffer) 454 { 455 if (!buffer) 456 return 0; 457 458 QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN); 459 if ((buffer[2] & 0xc0) == 0xc0) { 460 QETH_DBF_MESSAGE(2, "received an IDX TERMINATE " 461 "with cause code 0x%02x%s\n", 462 buffer[4], 463 ((buffer[4] == 0x22) ? 464 " -- try another portname" : "")); 465 QETH_DBF_TEXT(TRACE, 2, "ckidxres"); 466 QETH_DBF_TEXT(TRACE, 2, " idxterm"); 467 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO); 468 return -EIO; 469 } 470 return 0; 471 } 472 473 static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob, 474 __u32 len) 475 { 476 struct qeth_card *card; 477 478 QETH_DBF_TEXT(TRACE, 4, "setupccw"); 479 card = CARD_FROM_CDEV(channel->ccwdev); 480 if (channel == &card->read) 481 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1)); 482 else 483 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1)); 484 channel->ccw.count = len; 485 channel->ccw.cda = (__u32) __pa(iob); 486 } 487 488 static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel) 489 { 490 __u8 index; 491 492 QETH_DBF_TEXT(TRACE, 6, "getbuff"); 493 index = channel->io_buf_no; 494 do { 495 if (channel->iob[index].state == BUF_STATE_FREE) { 496 channel->iob[index].state = BUF_STATE_LOCKED; 497 channel->io_buf_no = (channel->io_buf_no + 1) % 498 QETH_CMD_BUFFER_NO; 499 memset(channel->iob[index].data, 0, QETH_BUFSIZE); 500 return channel->iob + index; 501 } 502 index = (index + 1) % QETH_CMD_BUFFER_NO; 503 } while (index != channel->io_buf_no); 504 505 return NULL; 506 } 507 508 void qeth_release_buffer(struct qeth_channel *channel, 509 struct qeth_cmd_buffer *iob) 510 { 511 unsigned long flags; 512 513 QETH_DBF_TEXT(TRACE, 6, "relbuff"); 514 spin_lock_irqsave(&channel->iob_lock, flags); 515 memset(iob->data, 0, QETH_BUFSIZE); 516 iob->state = BUF_STATE_FREE; 517 iob->callback = qeth_send_control_data_cb; 518 iob->rc = 0; 519 spin_unlock_irqrestore(&channel->iob_lock, flags); 520 } 521 EXPORT_SYMBOL_GPL(qeth_release_buffer); 522 523 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel) 524 { 525 struct qeth_cmd_buffer *buffer = NULL; 526 unsigned long flags; 527 528 spin_lock_irqsave(&channel->iob_lock, flags); 529 buffer = __qeth_get_buffer(channel); 530 spin_unlock_irqrestore(&channel->iob_lock, flags); 531 return buffer; 532 } 533 534 struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel) 535 { 536 struct qeth_cmd_buffer *buffer; 537 wait_event(channel->wait_q, 538 ((buffer = qeth_get_buffer(channel)) != NULL)); 539 return buffer; 540 } 541 EXPORT_SYMBOL_GPL(qeth_wait_for_buffer); 542 543 void qeth_clear_cmd_buffers(struct qeth_channel *channel) 544 { 545 int cnt; 546 547 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) 548 qeth_release_buffer(channel, &channel->iob[cnt]); 549 channel->buf_no = 0; 550 channel->io_buf_no = 0; 551 } 552 EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers); 553 554 static void qeth_send_control_data_cb(struct qeth_channel *channel, 555 struct qeth_cmd_buffer *iob) 556 { 557 struct qeth_card *card; 558 struct qeth_reply *reply, *r; 559 struct qeth_ipa_cmd *cmd; 560 unsigned long flags; 561 int keep_reply; 562 563 QETH_DBF_TEXT(TRACE, 4, "sndctlcb"); 564 565 card = CARD_FROM_CDEV(channel->ccwdev); 566 if (qeth_check_idx_response(iob->data)) { 567 qeth_clear_ipacmd_list(card); 568 if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6) 569 dev_err(&card->gdev->dev, 570 "The qeth device is not configured " 571 "for the OSI layer required by z/VM\n"); 572 qeth_schedule_recovery(card); 573 goto out; 574 } 575 576 cmd = qeth_check_ipa_data(card, iob); 577 if ((cmd == NULL) && (card->state != CARD_STATE_DOWN)) 578 goto out; 579 /*in case of OSN : check if cmd is set */ 580 if (card->info.type == QETH_CARD_TYPE_OSN && 581 cmd && 582 cmd->hdr.command != IPA_CMD_STARTLAN && 583 card->osn_info.assist_cb != NULL) { 584 card->osn_info.assist_cb(card->dev, cmd); 585 goto out; 586 } 587 588 spin_lock_irqsave(&card->lock, flags); 589 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) { 590 if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) || 591 ((cmd) && (reply->seqno == cmd->hdr.seqno))) { 592 qeth_get_reply(reply); 593 list_del_init(&reply->list); 594 spin_unlock_irqrestore(&card->lock, flags); 595 keep_reply = 0; 596 if (reply->callback != NULL) { 597 if (cmd) { 598 reply->offset = (__u16)((char *)cmd - 599 (char *)iob->data); 600 keep_reply = reply->callback(card, 601 reply, 602 (unsigned long)cmd); 603 } else 604 keep_reply = reply->callback(card, 605 reply, 606 (unsigned long)iob); 607 } 608 if (cmd) 609 reply->rc = (u16) cmd->hdr.return_code; 610 else if (iob->rc) 611 reply->rc = iob->rc; 612 if (keep_reply) { 613 spin_lock_irqsave(&card->lock, flags); 614 list_add_tail(&reply->list, 615 &card->cmd_waiter_list); 616 spin_unlock_irqrestore(&card->lock, flags); 617 } else { 618 atomic_inc(&reply->received); 619 wake_up(&reply->wait_q); 620 } 621 qeth_put_reply(reply); 622 goto out; 623 } 624 } 625 spin_unlock_irqrestore(&card->lock, flags); 626 out: 627 memcpy(&card->seqno.pdu_hdr_ack, 628 QETH_PDU_HEADER_SEQ_NO(iob->data), 629 QETH_SEQ_NO_LENGTH); 630 qeth_release_buffer(channel, iob); 631 } 632 633 static int qeth_setup_channel(struct qeth_channel *channel) 634 { 635 int cnt; 636 637 QETH_DBF_TEXT(SETUP, 2, "setupch"); 638 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) { 639 channel->iob[cnt].data = (char *) 640 kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL); 641 if (channel->iob[cnt].data == NULL) 642 break; 643 channel->iob[cnt].state = BUF_STATE_FREE; 644 channel->iob[cnt].channel = channel; 645 channel->iob[cnt].callback = qeth_send_control_data_cb; 646 channel->iob[cnt].rc = 0; 647 } 648 if (cnt < QETH_CMD_BUFFER_NO) { 649 while (cnt-- > 0) 650 kfree(channel->iob[cnt].data); 651 return -ENOMEM; 652 } 653 channel->buf_no = 0; 654 channel->io_buf_no = 0; 655 atomic_set(&channel->irq_pending, 0); 656 spin_lock_init(&channel->iob_lock); 657 658 init_waitqueue_head(&channel->wait_q); 659 return 0; 660 } 661 662 static int qeth_set_thread_start_bit(struct qeth_card *card, 663 unsigned long thread) 664 { 665 unsigned long flags; 666 667 spin_lock_irqsave(&card->thread_mask_lock, flags); 668 if (!(card->thread_allowed_mask & thread) || 669 (card->thread_start_mask & thread)) { 670 spin_unlock_irqrestore(&card->thread_mask_lock, flags); 671 return -EPERM; 672 } 673 card->thread_start_mask |= thread; 674 spin_unlock_irqrestore(&card->thread_mask_lock, flags); 675 return 0; 676 } 677 678 void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread) 679 { 680 unsigned long flags; 681 682 spin_lock_irqsave(&card->thread_mask_lock, flags); 683 card->thread_start_mask &= ~thread; 684 spin_unlock_irqrestore(&card->thread_mask_lock, flags); 685 wake_up(&card->wait_q); 686 } 687 EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit); 688 689 void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread) 690 { 691 unsigned long flags; 692 693 spin_lock_irqsave(&card->thread_mask_lock, flags); 694 card->thread_running_mask &= ~thread; 695 spin_unlock_irqrestore(&card->thread_mask_lock, flags); 696 wake_up(&card->wait_q); 697 } 698 EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit); 699 700 static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread) 701 { 702 unsigned long flags; 703 int rc = 0; 704 705 spin_lock_irqsave(&card->thread_mask_lock, flags); 706 if (card->thread_start_mask & thread) { 707 if ((card->thread_allowed_mask & thread) && 708 !(card->thread_running_mask & thread)) { 709 rc = 1; 710 card->thread_start_mask &= ~thread; 711 card->thread_running_mask |= thread; 712 } else 713 rc = -EPERM; 714 } 715 spin_unlock_irqrestore(&card->thread_mask_lock, flags); 716 return rc; 717 } 718 719 int qeth_do_run_thread(struct qeth_card *card, unsigned long thread) 720 { 721 int rc = 0; 722 723 wait_event(card->wait_q, 724 (rc = __qeth_do_run_thread(card, thread)) >= 0); 725 return rc; 726 } 727 EXPORT_SYMBOL_GPL(qeth_do_run_thread); 728 729 void qeth_schedule_recovery(struct qeth_card *card) 730 { 731 QETH_DBF_TEXT(TRACE, 2, "startrec"); 732 if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0) 733 schedule_work(&card->kernel_thread_starter); 734 } 735 EXPORT_SYMBOL_GPL(qeth_schedule_recovery); 736 737 static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb) 738 { 739 int dstat, cstat; 740 char *sense; 741 742 sense = (char *) irb->ecw; 743 cstat = irb->scsw.cmd.cstat; 744 dstat = irb->scsw.cmd.dstat; 745 746 if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK | 747 SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK | 748 SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) { 749 QETH_DBF_TEXT(TRACE, 2, "CGENCHK"); 750 dev_warn(&cdev->dev, "The qeth device driver " 751 "failed to recover an error on the device\n"); 752 QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ", 753 dev_name(&cdev->dev), dstat, cstat); 754 print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET, 755 16, 1, irb, 64, 1); 756 return 1; 757 } 758 759 if (dstat & DEV_STAT_UNIT_CHECK) { 760 if (sense[SENSE_RESETTING_EVENT_BYTE] & 761 SENSE_RESETTING_EVENT_FLAG) { 762 QETH_DBF_TEXT(TRACE, 2, "REVIND"); 763 return 1; 764 } 765 if (sense[SENSE_COMMAND_REJECT_BYTE] & 766 SENSE_COMMAND_REJECT_FLAG) { 767 QETH_DBF_TEXT(TRACE, 2, "CMDREJi"); 768 return 1; 769 } 770 if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) { 771 QETH_DBF_TEXT(TRACE, 2, "AFFE"); 772 return 1; 773 } 774 if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) { 775 QETH_DBF_TEXT(TRACE, 2, "ZEROSEN"); 776 return 0; 777 } 778 QETH_DBF_TEXT(TRACE, 2, "DGENCHK"); 779 return 1; 780 } 781 return 0; 782 } 783 784 static long __qeth_check_irb_error(struct ccw_device *cdev, 785 unsigned long intparm, struct irb *irb) 786 { 787 if (!IS_ERR(irb)) 788 return 0; 789 790 switch (PTR_ERR(irb)) { 791 case -EIO: 792 QETH_DBF_MESSAGE(2, "%s i/o-error on device\n", 793 dev_name(&cdev->dev)); 794 QETH_DBF_TEXT(TRACE, 2, "ckirberr"); 795 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO); 796 break; 797 case -ETIMEDOUT: 798 dev_warn(&cdev->dev, "A hardware operation timed out" 799 " on the device\n"); 800 QETH_DBF_TEXT(TRACE, 2, "ckirberr"); 801 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT); 802 if (intparm == QETH_RCD_PARM) { 803 struct qeth_card *card = CARD_FROM_CDEV(cdev); 804 805 if (card && (card->data.ccwdev == cdev)) { 806 card->data.state = CH_STATE_DOWN; 807 wake_up(&card->wait_q); 808 } 809 } 810 break; 811 default: 812 QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n", 813 dev_name(&cdev->dev), PTR_ERR(irb)); 814 QETH_DBF_TEXT(TRACE, 2, "ckirberr"); 815 QETH_DBF_TEXT(TRACE, 2, " rc???"); 816 } 817 return PTR_ERR(irb); 818 } 819 820 static void qeth_irq(struct ccw_device *cdev, unsigned long intparm, 821 struct irb *irb) 822 { 823 int rc; 824 int cstat, dstat; 825 struct qeth_cmd_buffer *buffer; 826 struct qeth_channel *channel; 827 struct qeth_card *card; 828 struct qeth_cmd_buffer *iob; 829 __u8 index; 830 831 QETH_DBF_TEXT(TRACE, 5, "irq"); 832 833 if (__qeth_check_irb_error(cdev, intparm, irb)) 834 return; 835 cstat = irb->scsw.cmd.cstat; 836 dstat = irb->scsw.cmd.dstat; 837 838 card = CARD_FROM_CDEV(cdev); 839 if (!card) 840 return; 841 842 if (card->read.ccwdev == cdev) { 843 channel = &card->read; 844 QETH_DBF_TEXT(TRACE, 5, "read"); 845 } else if (card->write.ccwdev == cdev) { 846 channel = &card->write; 847 QETH_DBF_TEXT(TRACE, 5, "write"); 848 } else { 849 channel = &card->data; 850 QETH_DBF_TEXT(TRACE, 5, "data"); 851 } 852 atomic_set(&channel->irq_pending, 0); 853 854 if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC)) 855 channel->state = CH_STATE_STOPPED; 856 857 if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC)) 858 channel->state = CH_STATE_HALTED; 859 860 /*let's wake up immediately on data channel*/ 861 if ((channel == &card->data) && (intparm != 0) && 862 (intparm != QETH_RCD_PARM)) 863 goto out; 864 865 if (intparm == QETH_CLEAR_CHANNEL_PARM) { 866 QETH_DBF_TEXT(TRACE, 6, "clrchpar"); 867 /* we don't have to handle this further */ 868 intparm = 0; 869 } 870 if (intparm == QETH_HALT_CHANNEL_PARM) { 871 QETH_DBF_TEXT(TRACE, 6, "hltchpar"); 872 /* we don't have to handle this further */ 873 intparm = 0; 874 } 875 if ((dstat & DEV_STAT_UNIT_EXCEP) || 876 (dstat & DEV_STAT_UNIT_CHECK) || 877 (cstat)) { 878 if (irb->esw.esw0.erw.cons) { 879 dev_warn(&channel->ccwdev->dev, 880 "The qeth device driver failed to recover " 881 "an error on the device\n"); 882 QETH_DBF_MESSAGE(2, "%s sense data available. cstat " 883 "0x%X dstat 0x%X\n", 884 dev_name(&channel->ccwdev->dev), cstat, dstat); 885 print_hex_dump(KERN_WARNING, "qeth: irb ", 886 DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1); 887 print_hex_dump(KERN_WARNING, "qeth: sense data ", 888 DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1); 889 } 890 if (intparm == QETH_RCD_PARM) { 891 channel->state = CH_STATE_DOWN; 892 goto out; 893 } 894 rc = qeth_get_problem(cdev, irb); 895 if (rc) { 896 qeth_clear_ipacmd_list(card); 897 qeth_schedule_recovery(card); 898 goto out; 899 } 900 } 901 902 if (intparm == QETH_RCD_PARM) { 903 channel->state = CH_STATE_RCD_DONE; 904 goto out; 905 } 906 if (intparm) { 907 buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm); 908 buffer->state = BUF_STATE_PROCESSED; 909 } 910 if (channel == &card->data) 911 return; 912 if (channel == &card->read && 913 channel->state == CH_STATE_UP) 914 qeth_issue_next_read(card); 915 916 iob = channel->iob; 917 index = channel->buf_no; 918 while (iob[index].state == BUF_STATE_PROCESSED) { 919 if (iob[index].callback != NULL) 920 iob[index].callback(channel, iob + index); 921 922 index = (index + 1) % QETH_CMD_BUFFER_NO; 923 } 924 channel->buf_no = index; 925 out: 926 wake_up(&card->wait_q); 927 return; 928 } 929 930 static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue, 931 struct qeth_qdio_out_buffer *buf) 932 { 933 int i; 934 struct sk_buff *skb; 935 936 /* is PCI flag set on buffer? */ 937 if (buf->buffer->element[0].flags & 0x40) 938 atomic_dec(&queue->set_pci_flags_count); 939 940 skb = skb_dequeue(&buf->skb_list); 941 while (skb) { 942 atomic_dec(&skb->users); 943 dev_kfree_skb_any(skb); 944 skb = skb_dequeue(&buf->skb_list); 945 } 946 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) { 947 if (buf->buffer->element[i].addr && buf->is_header[i]) 948 kmem_cache_free(qeth_core_header_cache, 949 buf->buffer->element[i].addr); 950 buf->is_header[i] = 0; 951 buf->buffer->element[i].length = 0; 952 buf->buffer->element[i].addr = NULL; 953 buf->buffer->element[i].flags = 0; 954 } 955 buf->next_element_to_fill = 0; 956 atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY); 957 } 958 959 void qeth_clear_qdio_buffers(struct qeth_card *card) 960 { 961 int i, j; 962 963 QETH_DBF_TEXT(TRACE, 2, "clearqdbf"); 964 /* clear outbound buffers to free skbs */ 965 for (i = 0; i < card->qdio.no_out_queues; ++i) 966 if (card->qdio.out_qs[i]) { 967 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) 968 qeth_clear_output_buffer(card->qdio.out_qs[i], 969 &card->qdio.out_qs[i]->bufs[j]); 970 } 971 } 972 EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers); 973 974 static void qeth_free_buffer_pool(struct qeth_card *card) 975 { 976 struct qeth_buffer_pool_entry *pool_entry, *tmp; 977 int i = 0; 978 QETH_DBF_TEXT(TRACE, 5, "freepool"); 979 list_for_each_entry_safe(pool_entry, tmp, 980 &card->qdio.init_pool.entry_list, init_list){ 981 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) 982 free_page((unsigned long)pool_entry->elements[i]); 983 list_del(&pool_entry->init_list); 984 kfree(pool_entry); 985 } 986 } 987 988 static void qeth_free_qdio_buffers(struct qeth_card *card) 989 { 990 int i, j; 991 992 QETH_DBF_TEXT(TRACE, 2, "freeqdbf"); 993 if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) == 994 QETH_QDIO_UNINITIALIZED) 995 return; 996 kfree(card->qdio.in_q); 997 card->qdio.in_q = NULL; 998 /* inbound buffer pool */ 999 qeth_free_buffer_pool(card); 1000 /* free outbound qdio_qs */ 1001 if (card->qdio.out_qs) { 1002 for (i = 0; i < card->qdio.no_out_queues; ++i) { 1003 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) 1004 qeth_clear_output_buffer(card->qdio.out_qs[i], 1005 &card->qdio.out_qs[i]->bufs[j]); 1006 kfree(card->qdio.out_qs[i]); 1007 } 1008 kfree(card->qdio.out_qs); 1009 card->qdio.out_qs = NULL; 1010 } 1011 } 1012 1013 static void qeth_clean_channel(struct qeth_channel *channel) 1014 { 1015 int cnt; 1016 1017 QETH_DBF_TEXT(SETUP, 2, "freech"); 1018 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) 1019 kfree(channel->iob[cnt].data); 1020 } 1021 1022 static int qeth_is_1920_device(struct qeth_card *card) 1023 { 1024 int single_queue = 0; 1025 struct ccw_device *ccwdev; 1026 struct channelPath_dsc { 1027 u8 flags; 1028 u8 lsn; 1029 u8 desc; 1030 u8 chpid; 1031 u8 swla; 1032 u8 zeroes; 1033 u8 chla; 1034 u8 chpp; 1035 } *chp_dsc; 1036 1037 QETH_DBF_TEXT(SETUP, 2, "chk_1920"); 1038 1039 ccwdev = card->data.ccwdev; 1040 chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0); 1041 if (chp_dsc != NULL) { 1042 /* CHPP field bit 6 == 1 -> single queue */ 1043 single_queue = ((chp_dsc->chpp & 0x02) == 0x02); 1044 kfree(chp_dsc); 1045 } 1046 QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue); 1047 return single_queue; 1048 } 1049 1050 static void qeth_init_qdio_info(struct qeth_card *card) 1051 { 1052 QETH_DBF_TEXT(SETUP, 4, "intqdinf"); 1053 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED); 1054 /* inbound */ 1055 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT; 1056 card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT; 1057 card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count; 1058 INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list); 1059 INIT_LIST_HEAD(&card->qdio.init_pool.entry_list); 1060 } 1061 1062 static void qeth_set_intial_options(struct qeth_card *card) 1063 { 1064 card->options.route4.type = NO_ROUTER; 1065 card->options.route6.type = NO_ROUTER; 1066 card->options.checksum_type = QETH_CHECKSUM_DEFAULT; 1067 card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS; 1068 card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL; 1069 card->options.fake_broadcast = 0; 1070 card->options.add_hhlen = DEFAULT_ADD_HHLEN; 1071 card->options.performance_stats = 0; 1072 card->options.rx_sg_cb = QETH_RX_SG_CB; 1073 } 1074 1075 static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread) 1076 { 1077 unsigned long flags; 1078 int rc = 0; 1079 1080 spin_lock_irqsave(&card->thread_mask_lock, flags); 1081 QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x", 1082 (u8) card->thread_start_mask, 1083 (u8) card->thread_allowed_mask, 1084 (u8) card->thread_running_mask); 1085 rc = (card->thread_start_mask & thread); 1086 spin_unlock_irqrestore(&card->thread_mask_lock, flags); 1087 return rc; 1088 } 1089 1090 static void qeth_start_kernel_thread(struct work_struct *work) 1091 { 1092 struct qeth_card *card = container_of(work, struct qeth_card, 1093 kernel_thread_starter); 1094 QETH_DBF_TEXT(TRACE , 2, "strthrd"); 1095 1096 if (card->read.state != CH_STATE_UP && 1097 card->write.state != CH_STATE_UP) 1098 return; 1099 if (qeth_do_start_thread(card, QETH_RECOVER_THREAD)) 1100 kthread_run(card->discipline.recover, (void *) card, 1101 "qeth_recover"); 1102 } 1103 1104 static int qeth_setup_card(struct qeth_card *card) 1105 { 1106 1107 QETH_DBF_TEXT(SETUP, 2, "setupcrd"); 1108 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *)); 1109 1110 card->read.state = CH_STATE_DOWN; 1111 card->write.state = CH_STATE_DOWN; 1112 card->data.state = CH_STATE_DOWN; 1113 card->state = CARD_STATE_DOWN; 1114 card->lan_online = 0; 1115 card->use_hard_stop = 0; 1116 card->dev = NULL; 1117 spin_lock_init(&card->vlanlock); 1118 spin_lock_init(&card->mclock); 1119 card->vlangrp = NULL; 1120 spin_lock_init(&card->lock); 1121 spin_lock_init(&card->ip_lock); 1122 spin_lock_init(&card->thread_mask_lock); 1123 card->thread_start_mask = 0; 1124 card->thread_allowed_mask = 0; 1125 card->thread_running_mask = 0; 1126 INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread); 1127 INIT_LIST_HEAD(&card->ip_list); 1128 card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL); 1129 if (!card->ip_tbd_list) { 1130 QETH_DBF_TEXT(SETUP, 0, "iptbdnom"); 1131 return -ENOMEM; 1132 } 1133 INIT_LIST_HEAD(card->ip_tbd_list); 1134 INIT_LIST_HEAD(&card->cmd_waiter_list); 1135 init_waitqueue_head(&card->wait_q); 1136 /* intial options */ 1137 qeth_set_intial_options(card); 1138 /* IP address takeover */ 1139 INIT_LIST_HEAD(&card->ipato.entries); 1140 card->ipato.enabled = 0; 1141 card->ipato.invert4 = 0; 1142 card->ipato.invert6 = 0; 1143 /* init QDIO stuff */ 1144 qeth_init_qdio_info(card); 1145 return 0; 1146 } 1147 1148 static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr) 1149 { 1150 struct qeth_card *card = container_of(slr, struct qeth_card, 1151 qeth_service_level); 1152 seq_printf(m, "qeth: %s firmware level %s\n", CARD_BUS_ID(card), 1153 card->info.mcl_level); 1154 } 1155 1156 static struct qeth_card *qeth_alloc_card(void) 1157 { 1158 struct qeth_card *card; 1159 1160 QETH_DBF_TEXT(SETUP, 2, "alloccrd"); 1161 card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL); 1162 if (!card) 1163 return NULL; 1164 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *)); 1165 if (qeth_setup_channel(&card->read)) { 1166 kfree(card); 1167 return NULL; 1168 } 1169 if (qeth_setup_channel(&card->write)) { 1170 qeth_clean_channel(&card->read); 1171 kfree(card); 1172 return NULL; 1173 } 1174 card->options.layer2 = -1; 1175 card->qeth_service_level.seq_print = qeth_core_sl_print; 1176 register_service_level(&card->qeth_service_level); 1177 return card; 1178 } 1179 1180 static int qeth_determine_card_type(struct qeth_card *card) 1181 { 1182 int i = 0; 1183 1184 QETH_DBF_TEXT(SETUP, 2, "detcdtyp"); 1185 1186 card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT; 1187 card->qdio.default_out_queue = QETH_DEFAULT_QUEUE; 1188 while (known_devices[i][4]) { 1189 if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) && 1190 (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) { 1191 card->info.type = known_devices[i][4]; 1192 card->qdio.no_out_queues = known_devices[i][8]; 1193 card->info.is_multicast_different = known_devices[i][9]; 1194 if (qeth_is_1920_device(card)) { 1195 dev_info(&card->gdev->dev, 1196 "Priority Queueing not supported\n"); 1197 card->qdio.no_out_queues = 1; 1198 card->qdio.default_out_queue = 0; 1199 } 1200 return 0; 1201 } 1202 i++; 1203 } 1204 card->info.type = QETH_CARD_TYPE_UNKNOWN; 1205 dev_err(&card->gdev->dev, "The adapter hardware is of an " 1206 "unknown type\n"); 1207 return -ENOENT; 1208 } 1209 1210 static int qeth_clear_channel(struct qeth_channel *channel) 1211 { 1212 unsigned long flags; 1213 struct qeth_card *card; 1214 int rc; 1215 1216 QETH_DBF_TEXT(TRACE, 3, "clearch"); 1217 card = CARD_FROM_CDEV(channel->ccwdev); 1218 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags); 1219 rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM); 1220 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags); 1221 1222 if (rc) 1223 return rc; 1224 rc = wait_event_interruptible_timeout(card->wait_q, 1225 channel->state == CH_STATE_STOPPED, QETH_TIMEOUT); 1226 if (rc == -ERESTARTSYS) 1227 return rc; 1228 if (channel->state != CH_STATE_STOPPED) 1229 return -ETIME; 1230 channel->state = CH_STATE_DOWN; 1231 return 0; 1232 } 1233 1234 static int qeth_halt_channel(struct qeth_channel *channel) 1235 { 1236 unsigned long flags; 1237 struct qeth_card *card; 1238 int rc; 1239 1240 QETH_DBF_TEXT(TRACE, 3, "haltch"); 1241 card = CARD_FROM_CDEV(channel->ccwdev); 1242 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags); 1243 rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM); 1244 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags); 1245 1246 if (rc) 1247 return rc; 1248 rc = wait_event_interruptible_timeout(card->wait_q, 1249 channel->state == CH_STATE_HALTED, QETH_TIMEOUT); 1250 if (rc == -ERESTARTSYS) 1251 return rc; 1252 if (channel->state != CH_STATE_HALTED) 1253 return -ETIME; 1254 return 0; 1255 } 1256 1257 static int qeth_halt_channels(struct qeth_card *card) 1258 { 1259 int rc1 = 0, rc2 = 0, rc3 = 0; 1260 1261 QETH_DBF_TEXT(TRACE, 3, "haltchs"); 1262 rc1 = qeth_halt_channel(&card->read); 1263 rc2 = qeth_halt_channel(&card->write); 1264 rc3 = qeth_halt_channel(&card->data); 1265 if (rc1) 1266 return rc1; 1267 if (rc2) 1268 return rc2; 1269 return rc3; 1270 } 1271 1272 static int qeth_clear_channels(struct qeth_card *card) 1273 { 1274 int rc1 = 0, rc2 = 0, rc3 = 0; 1275 1276 QETH_DBF_TEXT(TRACE, 3, "clearchs"); 1277 rc1 = qeth_clear_channel(&card->read); 1278 rc2 = qeth_clear_channel(&card->write); 1279 rc3 = qeth_clear_channel(&card->data); 1280 if (rc1) 1281 return rc1; 1282 if (rc2) 1283 return rc2; 1284 return rc3; 1285 } 1286 1287 static int qeth_clear_halt_card(struct qeth_card *card, int halt) 1288 { 1289 int rc = 0; 1290 1291 QETH_DBF_TEXT(TRACE, 3, "clhacrd"); 1292 QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *)); 1293 1294 if (halt) 1295 rc = qeth_halt_channels(card); 1296 if (rc) 1297 return rc; 1298 return qeth_clear_channels(card); 1299 } 1300 1301 int qeth_qdio_clear_card(struct qeth_card *card, int use_halt) 1302 { 1303 int rc = 0; 1304 1305 QETH_DBF_TEXT(TRACE, 3, "qdioclr"); 1306 switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED, 1307 QETH_QDIO_CLEANING)) { 1308 case QETH_QDIO_ESTABLISHED: 1309 if (card->info.type == QETH_CARD_TYPE_IQD) 1310 rc = qdio_cleanup(CARD_DDEV(card), 1311 QDIO_FLAG_CLEANUP_USING_HALT); 1312 else 1313 rc = qdio_cleanup(CARD_DDEV(card), 1314 QDIO_FLAG_CLEANUP_USING_CLEAR); 1315 if (rc) 1316 QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc); 1317 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED); 1318 break; 1319 case QETH_QDIO_CLEANING: 1320 return rc; 1321 default: 1322 break; 1323 } 1324 rc = qeth_clear_halt_card(card, use_halt); 1325 if (rc) 1326 QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc); 1327 card->state = CARD_STATE_DOWN; 1328 return rc; 1329 } 1330 EXPORT_SYMBOL_GPL(qeth_qdio_clear_card); 1331 1332 static int qeth_read_conf_data(struct qeth_card *card, void **buffer, 1333 int *length) 1334 { 1335 struct ciw *ciw; 1336 char *rcd_buf; 1337 int ret; 1338 struct qeth_channel *channel = &card->data; 1339 unsigned long flags; 1340 1341 /* 1342 * scan for RCD command in extended SenseID data 1343 */ 1344 ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD); 1345 if (!ciw || ciw->cmd == 0) 1346 return -EOPNOTSUPP; 1347 rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA); 1348 if (!rcd_buf) 1349 return -ENOMEM; 1350 1351 channel->ccw.cmd_code = ciw->cmd; 1352 channel->ccw.cda = (__u32) __pa(rcd_buf); 1353 channel->ccw.count = ciw->count; 1354 channel->ccw.flags = CCW_FLAG_SLI; 1355 channel->state = CH_STATE_RCD; 1356 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags); 1357 ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw, 1358 QETH_RCD_PARM, LPM_ANYPATH, 0, 1359 QETH_RCD_TIMEOUT); 1360 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags); 1361 if (!ret) 1362 wait_event(card->wait_q, 1363 (channel->state == CH_STATE_RCD_DONE || 1364 channel->state == CH_STATE_DOWN)); 1365 if (channel->state == CH_STATE_DOWN) 1366 ret = -EIO; 1367 else 1368 channel->state = CH_STATE_DOWN; 1369 if (ret) { 1370 kfree(rcd_buf); 1371 *buffer = NULL; 1372 *length = 0; 1373 } else { 1374 *length = ciw->count; 1375 *buffer = rcd_buf; 1376 } 1377 return ret; 1378 } 1379 1380 static int qeth_get_unitaddr(struct qeth_card *card) 1381 { 1382 int length; 1383 char *prcd; 1384 int rc; 1385 1386 QETH_DBF_TEXT(SETUP, 2, "getunit"); 1387 rc = qeth_read_conf_data(card, (void **) &prcd, &length); 1388 if (rc) { 1389 QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n", 1390 dev_name(&card->gdev->dev), rc); 1391 return rc; 1392 } 1393 card->info.chpid = prcd[30]; 1394 card->info.unit_addr2 = prcd[31]; 1395 card->info.cula = prcd[63]; 1396 card->info.guestlan = ((prcd[0x10] == _ascebc['V']) && 1397 (prcd[0x11] == _ascebc['M'])); 1398 kfree(prcd); 1399 return 0; 1400 } 1401 1402 static void qeth_init_tokens(struct qeth_card *card) 1403 { 1404 card->token.issuer_rm_w = 0x00010103UL; 1405 card->token.cm_filter_w = 0x00010108UL; 1406 card->token.cm_connection_w = 0x0001010aUL; 1407 card->token.ulp_filter_w = 0x0001010bUL; 1408 card->token.ulp_connection_w = 0x0001010dUL; 1409 } 1410 1411 static void qeth_init_func_level(struct qeth_card *card) 1412 { 1413 if (card->ipato.enabled) { 1414 if (card->info.type == QETH_CARD_TYPE_IQD) 1415 card->info.func_level = 1416 QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT; 1417 else 1418 card->info.func_level = 1419 QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT; 1420 } else { 1421 if (card->info.type == QETH_CARD_TYPE_IQD) 1422 /*FIXME:why do we have same values for dis and ena for 1423 osae??? */ 1424 card->info.func_level = 1425 QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT; 1426 else 1427 card->info.func_level = 1428 QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT; 1429 } 1430 } 1431 1432 static int qeth_idx_activate_get_answer(struct qeth_channel *channel, 1433 void (*idx_reply_cb)(struct qeth_channel *, 1434 struct qeth_cmd_buffer *)) 1435 { 1436 struct qeth_cmd_buffer *iob; 1437 unsigned long flags; 1438 int rc; 1439 struct qeth_card *card; 1440 1441 QETH_DBF_TEXT(SETUP, 2, "idxanswr"); 1442 card = CARD_FROM_CDEV(channel->ccwdev); 1443 iob = qeth_get_buffer(channel); 1444 iob->callback = idx_reply_cb; 1445 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1)); 1446 channel->ccw.count = QETH_BUFSIZE; 1447 channel->ccw.cda = (__u32) __pa(iob->data); 1448 1449 wait_event(card->wait_q, 1450 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0); 1451 QETH_DBF_TEXT(SETUP, 6, "noirqpnd"); 1452 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags); 1453 rc = ccw_device_start(channel->ccwdev, 1454 &channel->ccw, (addr_t) iob, 0, 0); 1455 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags); 1456 1457 if (rc) { 1458 QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc); 1459 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc); 1460 atomic_set(&channel->irq_pending, 0); 1461 wake_up(&card->wait_q); 1462 return rc; 1463 } 1464 rc = wait_event_interruptible_timeout(card->wait_q, 1465 channel->state == CH_STATE_UP, QETH_TIMEOUT); 1466 if (rc == -ERESTARTSYS) 1467 return rc; 1468 if (channel->state != CH_STATE_UP) { 1469 rc = -ETIME; 1470 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc); 1471 qeth_clear_cmd_buffers(channel); 1472 } else 1473 rc = 0; 1474 return rc; 1475 } 1476 1477 static int qeth_idx_activate_channel(struct qeth_channel *channel, 1478 void (*idx_reply_cb)(struct qeth_channel *, 1479 struct qeth_cmd_buffer *)) 1480 { 1481 struct qeth_card *card; 1482 struct qeth_cmd_buffer *iob; 1483 unsigned long flags; 1484 __u16 temp; 1485 __u8 tmp; 1486 int rc; 1487 struct ccw_dev_id temp_devid; 1488 1489 card = CARD_FROM_CDEV(channel->ccwdev); 1490 1491 QETH_DBF_TEXT(SETUP, 2, "idxactch"); 1492 1493 iob = qeth_get_buffer(channel); 1494 iob->callback = idx_reply_cb; 1495 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1)); 1496 channel->ccw.count = IDX_ACTIVATE_SIZE; 1497 channel->ccw.cda = (__u32) __pa(iob->data); 1498 if (channel == &card->write) { 1499 memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE); 1500 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data), 1501 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH); 1502 card->seqno.trans_hdr++; 1503 } else { 1504 memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE); 1505 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data), 1506 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH); 1507 } 1508 tmp = ((__u8)card->info.portno) | 0x80; 1509 memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1); 1510 memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data), 1511 &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH); 1512 memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data), 1513 &card->info.func_level, sizeof(__u16)); 1514 ccw_device_get_id(CARD_DDEV(card), &temp_devid); 1515 memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2); 1516 temp = (card->info.cula << 8) + card->info.unit_addr2; 1517 memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2); 1518 1519 wait_event(card->wait_q, 1520 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0); 1521 QETH_DBF_TEXT(SETUP, 6, "noirqpnd"); 1522 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags); 1523 rc = ccw_device_start(channel->ccwdev, 1524 &channel->ccw, (addr_t) iob, 0, 0); 1525 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags); 1526 1527 if (rc) { 1528 QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n", 1529 rc); 1530 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc); 1531 atomic_set(&channel->irq_pending, 0); 1532 wake_up(&card->wait_q); 1533 return rc; 1534 } 1535 rc = wait_event_interruptible_timeout(card->wait_q, 1536 channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT); 1537 if (rc == -ERESTARTSYS) 1538 return rc; 1539 if (channel->state != CH_STATE_ACTIVATING) { 1540 dev_warn(&channel->ccwdev->dev, "The qeth device driver" 1541 " failed to recover an error on the device\n"); 1542 QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n", 1543 dev_name(&channel->ccwdev->dev)); 1544 QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME); 1545 qeth_clear_cmd_buffers(channel); 1546 return -ETIME; 1547 } 1548 return qeth_idx_activate_get_answer(channel, idx_reply_cb); 1549 } 1550 1551 static int qeth_peer_func_level(int level) 1552 { 1553 if ((level & 0xff) == 8) 1554 return (level & 0xff) + 0x400; 1555 if (((level >> 8) & 3) == 1) 1556 return (level & 0xff) + 0x200; 1557 return level; 1558 } 1559 1560 static void qeth_idx_write_cb(struct qeth_channel *channel, 1561 struct qeth_cmd_buffer *iob) 1562 { 1563 struct qeth_card *card; 1564 __u16 temp; 1565 1566 QETH_DBF_TEXT(SETUP , 2, "idxwrcb"); 1567 1568 if (channel->state == CH_STATE_DOWN) { 1569 channel->state = CH_STATE_ACTIVATING; 1570 goto out; 1571 } 1572 card = CARD_FROM_CDEV(channel->ccwdev); 1573 1574 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) { 1575 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19) 1576 dev_err(&card->write.ccwdev->dev, 1577 "The adapter is used exclusively by another " 1578 "host\n"); 1579 else 1580 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:" 1581 " negative reply\n", 1582 dev_name(&card->write.ccwdev->dev)); 1583 goto out; 1584 } 1585 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2); 1586 if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) { 1587 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: " 1588 "function level mismatch (sent: 0x%x, received: " 1589 "0x%x)\n", dev_name(&card->write.ccwdev->dev), 1590 card->info.func_level, temp); 1591 goto out; 1592 } 1593 channel->state = CH_STATE_UP; 1594 out: 1595 qeth_release_buffer(channel, iob); 1596 } 1597 1598 static void qeth_idx_read_cb(struct qeth_channel *channel, 1599 struct qeth_cmd_buffer *iob) 1600 { 1601 struct qeth_card *card; 1602 __u16 temp; 1603 1604 QETH_DBF_TEXT(SETUP , 2, "idxrdcb"); 1605 if (channel->state == CH_STATE_DOWN) { 1606 channel->state = CH_STATE_ACTIVATING; 1607 goto out; 1608 } 1609 1610 card = CARD_FROM_CDEV(channel->ccwdev); 1611 if (qeth_check_idx_response(iob->data)) 1612 goto out; 1613 1614 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) { 1615 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19) 1616 dev_err(&card->write.ccwdev->dev, 1617 "The adapter is used exclusively by another " 1618 "host\n"); 1619 else 1620 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:" 1621 " negative reply\n", 1622 dev_name(&card->read.ccwdev->dev)); 1623 goto out; 1624 } 1625 1626 /** 1627 * temporary fix for microcode bug 1628 * to revert it,replace OR by AND 1629 */ 1630 if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) || 1631 (card->info.type == QETH_CARD_TYPE_OSAE)) 1632 card->info.portname_required = 1; 1633 1634 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2); 1635 if (temp != qeth_peer_func_level(card->info.func_level)) { 1636 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function " 1637 "level mismatch (sent: 0x%x, received: 0x%x)\n", 1638 dev_name(&card->read.ccwdev->dev), 1639 card->info.func_level, temp); 1640 goto out; 1641 } 1642 memcpy(&card->token.issuer_rm_r, 1643 QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data), 1644 QETH_MPC_TOKEN_LENGTH); 1645 memcpy(&card->info.mcl_level[0], 1646 QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH); 1647 channel->state = CH_STATE_UP; 1648 out: 1649 qeth_release_buffer(channel, iob); 1650 } 1651 1652 void qeth_prepare_control_data(struct qeth_card *card, int len, 1653 struct qeth_cmd_buffer *iob) 1654 { 1655 qeth_setup_ccw(&card->write, iob->data, len); 1656 iob->callback = qeth_release_buffer; 1657 1658 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data), 1659 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH); 1660 card->seqno.trans_hdr++; 1661 memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data), 1662 &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH); 1663 card->seqno.pdu_hdr++; 1664 memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data), 1665 &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH); 1666 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN); 1667 } 1668 EXPORT_SYMBOL_GPL(qeth_prepare_control_data); 1669 1670 int qeth_send_control_data(struct qeth_card *card, int len, 1671 struct qeth_cmd_buffer *iob, 1672 int (*reply_cb)(struct qeth_card *, struct qeth_reply *, 1673 unsigned long), 1674 void *reply_param) 1675 { 1676 int rc; 1677 unsigned long flags; 1678 struct qeth_reply *reply = NULL; 1679 unsigned long timeout, event_timeout; 1680 struct qeth_ipa_cmd *cmd; 1681 1682 QETH_DBF_TEXT(TRACE, 2, "sendctl"); 1683 1684 reply = qeth_alloc_reply(card); 1685 if (!reply) { 1686 return -ENOMEM; 1687 } 1688 reply->callback = reply_cb; 1689 reply->param = reply_param; 1690 if (card->state == CARD_STATE_DOWN) 1691 reply->seqno = QETH_IDX_COMMAND_SEQNO; 1692 else 1693 reply->seqno = card->seqno.ipa++; 1694 init_waitqueue_head(&reply->wait_q); 1695 spin_lock_irqsave(&card->lock, flags); 1696 list_add_tail(&reply->list, &card->cmd_waiter_list); 1697 spin_unlock_irqrestore(&card->lock, flags); 1698 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN); 1699 1700 while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ; 1701 qeth_prepare_control_data(card, len, iob); 1702 1703 if (IS_IPA(iob->data)) 1704 event_timeout = QETH_IPA_TIMEOUT; 1705 else 1706 event_timeout = QETH_TIMEOUT; 1707 timeout = jiffies + event_timeout; 1708 1709 QETH_DBF_TEXT(TRACE, 6, "noirqpnd"); 1710 spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags); 1711 rc = ccw_device_start(card->write.ccwdev, &card->write.ccw, 1712 (addr_t) iob, 0, 0); 1713 spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags); 1714 if (rc) { 1715 QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: " 1716 "ccw_device_start rc = %i\n", 1717 dev_name(&card->write.ccwdev->dev), rc); 1718 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc); 1719 spin_lock_irqsave(&card->lock, flags); 1720 list_del_init(&reply->list); 1721 qeth_put_reply(reply); 1722 spin_unlock_irqrestore(&card->lock, flags); 1723 qeth_release_buffer(iob->channel, iob); 1724 atomic_set(&card->write.irq_pending, 0); 1725 wake_up(&card->wait_q); 1726 return rc; 1727 } 1728 1729 /* we have only one long running ipassist, since we can ensure 1730 process context of this command we can sleep */ 1731 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE); 1732 if ((cmd->hdr.command == IPA_CMD_SETIP) && 1733 (cmd->hdr.prot_version == QETH_PROT_IPV4)) { 1734 if (!wait_event_timeout(reply->wait_q, 1735 atomic_read(&reply->received), event_timeout)) 1736 goto time_err; 1737 } else { 1738 while (!atomic_read(&reply->received)) { 1739 if (time_after(jiffies, timeout)) 1740 goto time_err; 1741 cpu_relax(); 1742 }; 1743 } 1744 1745 rc = reply->rc; 1746 qeth_put_reply(reply); 1747 return rc; 1748 1749 time_err: 1750 spin_lock_irqsave(&reply->card->lock, flags); 1751 list_del_init(&reply->list); 1752 spin_unlock_irqrestore(&reply->card->lock, flags); 1753 reply->rc = -ETIME; 1754 atomic_inc(&reply->received); 1755 wake_up(&reply->wait_q); 1756 rc = reply->rc; 1757 qeth_put_reply(reply); 1758 return rc; 1759 } 1760 EXPORT_SYMBOL_GPL(qeth_send_control_data); 1761 1762 static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply, 1763 unsigned long data) 1764 { 1765 struct qeth_cmd_buffer *iob; 1766 1767 QETH_DBF_TEXT(SETUP, 2, "cmenblcb"); 1768 1769 iob = (struct qeth_cmd_buffer *) data; 1770 memcpy(&card->token.cm_filter_r, 1771 QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data), 1772 QETH_MPC_TOKEN_LENGTH); 1773 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc); 1774 return 0; 1775 } 1776 1777 static int qeth_cm_enable(struct qeth_card *card) 1778 { 1779 int rc; 1780 struct qeth_cmd_buffer *iob; 1781 1782 QETH_DBF_TEXT(SETUP, 2, "cmenable"); 1783 1784 iob = qeth_wait_for_buffer(&card->write); 1785 memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE); 1786 memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data), 1787 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH); 1788 memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data), 1789 &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH); 1790 1791 rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob, 1792 qeth_cm_enable_cb, NULL); 1793 return rc; 1794 } 1795 1796 static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply, 1797 unsigned long data) 1798 { 1799 1800 struct qeth_cmd_buffer *iob; 1801 1802 QETH_DBF_TEXT(SETUP, 2, "cmsetpcb"); 1803 1804 iob = (struct qeth_cmd_buffer *) data; 1805 memcpy(&card->token.cm_connection_r, 1806 QETH_CM_SETUP_RESP_DEST_ADDR(iob->data), 1807 QETH_MPC_TOKEN_LENGTH); 1808 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc); 1809 return 0; 1810 } 1811 1812 static int qeth_cm_setup(struct qeth_card *card) 1813 { 1814 int rc; 1815 struct qeth_cmd_buffer *iob; 1816 1817 QETH_DBF_TEXT(SETUP, 2, "cmsetup"); 1818 1819 iob = qeth_wait_for_buffer(&card->write); 1820 memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE); 1821 memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data), 1822 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH); 1823 memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data), 1824 &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH); 1825 memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data), 1826 &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH); 1827 rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob, 1828 qeth_cm_setup_cb, NULL); 1829 return rc; 1830 1831 } 1832 1833 static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card) 1834 { 1835 switch (card->info.type) { 1836 case QETH_CARD_TYPE_UNKNOWN: 1837 return 1500; 1838 case QETH_CARD_TYPE_IQD: 1839 return card->info.max_mtu; 1840 case QETH_CARD_TYPE_OSAE: 1841 switch (card->info.link_type) { 1842 case QETH_LINK_TYPE_HSTR: 1843 case QETH_LINK_TYPE_LANE_TR: 1844 return 2000; 1845 default: 1846 return 1492; 1847 } 1848 default: 1849 return 1500; 1850 } 1851 } 1852 1853 static inline int qeth_get_max_mtu_for_card(int cardtype) 1854 { 1855 switch (cardtype) { 1856 1857 case QETH_CARD_TYPE_UNKNOWN: 1858 case QETH_CARD_TYPE_OSAE: 1859 case QETH_CARD_TYPE_OSN: 1860 return 61440; 1861 case QETH_CARD_TYPE_IQD: 1862 return 57344; 1863 default: 1864 return 1500; 1865 } 1866 } 1867 1868 static inline int qeth_get_mtu_out_of_mpc(int cardtype) 1869 { 1870 switch (cardtype) { 1871 case QETH_CARD_TYPE_IQD: 1872 return 1; 1873 default: 1874 return 0; 1875 } 1876 } 1877 1878 static inline int qeth_get_mtu_outof_framesize(int framesize) 1879 { 1880 switch (framesize) { 1881 case 0x4000: 1882 return 8192; 1883 case 0x6000: 1884 return 16384; 1885 case 0xa000: 1886 return 32768; 1887 case 0xffff: 1888 return 57344; 1889 default: 1890 return 0; 1891 } 1892 } 1893 1894 static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu) 1895 { 1896 switch (card->info.type) { 1897 case QETH_CARD_TYPE_OSAE: 1898 return ((mtu >= 576) && (mtu <= 61440)); 1899 case QETH_CARD_TYPE_IQD: 1900 return ((mtu >= 576) && 1901 (mtu <= card->info.max_mtu + 4096 - 32)); 1902 case QETH_CARD_TYPE_OSN: 1903 case QETH_CARD_TYPE_UNKNOWN: 1904 default: 1905 return 1; 1906 } 1907 } 1908 1909 static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply, 1910 unsigned long data) 1911 { 1912 1913 __u16 mtu, framesize; 1914 __u16 len; 1915 __u8 link_type; 1916 struct qeth_cmd_buffer *iob; 1917 1918 QETH_DBF_TEXT(SETUP, 2, "ulpenacb"); 1919 1920 iob = (struct qeth_cmd_buffer *) data; 1921 memcpy(&card->token.ulp_filter_r, 1922 QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data), 1923 QETH_MPC_TOKEN_LENGTH); 1924 if (qeth_get_mtu_out_of_mpc(card->info.type)) { 1925 memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2); 1926 mtu = qeth_get_mtu_outof_framesize(framesize); 1927 if (!mtu) { 1928 iob->rc = -EINVAL; 1929 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc); 1930 return 0; 1931 } 1932 card->info.max_mtu = mtu; 1933 card->info.initial_mtu = mtu; 1934 card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE; 1935 } else { 1936 card->info.initial_mtu = qeth_get_initial_mtu_for_card(card); 1937 card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type); 1938 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT; 1939 } 1940 1941 memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2); 1942 if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) { 1943 memcpy(&link_type, 1944 QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1); 1945 card->info.link_type = link_type; 1946 } else 1947 card->info.link_type = 0; 1948 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc); 1949 return 0; 1950 } 1951 1952 static int qeth_ulp_enable(struct qeth_card *card) 1953 { 1954 int rc; 1955 char prot_type; 1956 struct qeth_cmd_buffer *iob; 1957 1958 /*FIXME: trace view callbacks*/ 1959 QETH_DBF_TEXT(SETUP, 2, "ulpenabl"); 1960 1961 iob = qeth_wait_for_buffer(&card->write); 1962 memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE); 1963 1964 *(QETH_ULP_ENABLE_LINKNUM(iob->data)) = 1965 (__u8) card->info.portno; 1966 if (card->options.layer2) 1967 if (card->info.type == QETH_CARD_TYPE_OSN) 1968 prot_type = QETH_PROT_OSN2; 1969 else 1970 prot_type = QETH_PROT_LAYER2; 1971 else 1972 prot_type = QETH_PROT_TCPIP; 1973 1974 memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1); 1975 memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data), 1976 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH); 1977 memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data), 1978 &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH); 1979 memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data), 1980 card->info.portname, 9); 1981 rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob, 1982 qeth_ulp_enable_cb, NULL); 1983 return rc; 1984 1985 } 1986 1987 static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply, 1988 unsigned long data) 1989 { 1990 struct qeth_cmd_buffer *iob; 1991 1992 QETH_DBF_TEXT(SETUP, 2, "ulpstpcb"); 1993 1994 iob = (struct qeth_cmd_buffer *) data; 1995 memcpy(&card->token.ulp_connection_r, 1996 QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data), 1997 QETH_MPC_TOKEN_LENGTH); 1998 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc); 1999 return 0; 2000 } 2001 2002 static int qeth_ulp_setup(struct qeth_card *card) 2003 { 2004 int rc; 2005 __u16 temp; 2006 struct qeth_cmd_buffer *iob; 2007 struct ccw_dev_id dev_id; 2008 2009 QETH_DBF_TEXT(SETUP, 2, "ulpsetup"); 2010 2011 iob = qeth_wait_for_buffer(&card->write); 2012 memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE); 2013 2014 memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data), 2015 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH); 2016 memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data), 2017 &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH); 2018 memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data), 2019 &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH); 2020 2021 ccw_device_get_id(CARD_DDEV(card), &dev_id); 2022 memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2); 2023 temp = (card->info.cula << 8) + card->info.unit_addr2; 2024 memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2); 2025 rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob, 2026 qeth_ulp_setup_cb, NULL); 2027 return rc; 2028 } 2029 2030 static int qeth_alloc_qdio_buffers(struct qeth_card *card) 2031 { 2032 int i, j; 2033 2034 QETH_DBF_TEXT(SETUP, 2, "allcqdbf"); 2035 2036 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED, 2037 QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED) 2038 return 0; 2039 2040 card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q), 2041 GFP_KERNEL); 2042 if (!card->qdio.in_q) 2043 goto out_nomem; 2044 QETH_DBF_TEXT(SETUP, 2, "inq"); 2045 QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *)); 2046 memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q)); 2047 /* give inbound qeth_qdio_buffers their qdio_buffers */ 2048 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) 2049 card->qdio.in_q->bufs[i].buffer = 2050 &card->qdio.in_q->qdio_bufs[i]; 2051 /* inbound buffer pool */ 2052 if (qeth_alloc_buffer_pool(card)) 2053 goto out_freeinq; 2054 /* outbound */ 2055 card->qdio.out_qs = 2056 kmalloc(card->qdio.no_out_queues * 2057 sizeof(struct qeth_qdio_out_q *), GFP_KERNEL); 2058 if (!card->qdio.out_qs) 2059 goto out_freepool; 2060 for (i = 0; i < card->qdio.no_out_queues; ++i) { 2061 card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q), 2062 GFP_KERNEL); 2063 if (!card->qdio.out_qs[i]) 2064 goto out_freeoutq; 2065 QETH_DBF_TEXT_(SETUP, 2, "outq %i", i); 2066 QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *)); 2067 memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q)); 2068 card->qdio.out_qs[i]->queue_no = i; 2069 /* give outbound qeth_qdio_buffers their qdio_buffers */ 2070 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) { 2071 card->qdio.out_qs[i]->bufs[j].buffer = 2072 &card->qdio.out_qs[i]->qdio_bufs[j]; 2073 skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j]. 2074 skb_list); 2075 lockdep_set_class( 2076 &card->qdio.out_qs[i]->bufs[j].skb_list.lock, 2077 &qdio_out_skb_queue_key); 2078 INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list); 2079 } 2080 } 2081 return 0; 2082 2083 out_freeoutq: 2084 while (i > 0) 2085 kfree(card->qdio.out_qs[--i]); 2086 kfree(card->qdio.out_qs); 2087 card->qdio.out_qs = NULL; 2088 out_freepool: 2089 qeth_free_buffer_pool(card); 2090 out_freeinq: 2091 kfree(card->qdio.in_q); 2092 card->qdio.in_q = NULL; 2093 out_nomem: 2094 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED); 2095 return -ENOMEM; 2096 } 2097 2098 static void qeth_create_qib_param_field(struct qeth_card *card, 2099 char *param_field) 2100 { 2101 2102 param_field[0] = _ascebc['P']; 2103 param_field[1] = _ascebc['C']; 2104 param_field[2] = _ascebc['I']; 2105 param_field[3] = _ascebc['T']; 2106 *((unsigned int *) (¶m_field[4])) = QETH_PCI_THRESHOLD_A(card); 2107 *((unsigned int *) (¶m_field[8])) = QETH_PCI_THRESHOLD_B(card); 2108 *((unsigned int *) (¶m_field[12])) = QETH_PCI_TIMER_VALUE(card); 2109 } 2110 2111 static void qeth_create_qib_param_field_blkt(struct qeth_card *card, 2112 char *param_field) 2113 { 2114 param_field[16] = _ascebc['B']; 2115 param_field[17] = _ascebc['L']; 2116 param_field[18] = _ascebc['K']; 2117 param_field[19] = _ascebc['T']; 2118 *((unsigned int *) (¶m_field[20])) = card->info.blkt.time_total; 2119 *((unsigned int *) (¶m_field[24])) = card->info.blkt.inter_packet; 2120 *((unsigned int *) (¶m_field[28])) = 2121 card->info.blkt.inter_packet_jumbo; 2122 } 2123 2124 static int qeth_qdio_activate(struct qeth_card *card) 2125 { 2126 QETH_DBF_TEXT(SETUP, 3, "qdioact"); 2127 return qdio_activate(CARD_DDEV(card)); 2128 } 2129 2130 static int qeth_dm_act(struct qeth_card *card) 2131 { 2132 int rc; 2133 struct qeth_cmd_buffer *iob; 2134 2135 QETH_DBF_TEXT(SETUP, 2, "dmact"); 2136 2137 iob = qeth_wait_for_buffer(&card->write); 2138 memcpy(iob->data, DM_ACT, DM_ACT_SIZE); 2139 2140 memcpy(QETH_DM_ACT_DEST_ADDR(iob->data), 2141 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH); 2142 memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data), 2143 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH); 2144 rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL); 2145 return rc; 2146 } 2147 2148 static int qeth_mpc_initialize(struct qeth_card *card) 2149 { 2150 int rc; 2151 2152 QETH_DBF_TEXT(SETUP, 2, "mpcinit"); 2153 2154 rc = qeth_issue_next_read(card); 2155 if (rc) { 2156 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc); 2157 return rc; 2158 } 2159 rc = qeth_cm_enable(card); 2160 if (rc) { 2161 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc); 2162 goto out_qdio; 2163 } 2164 rc = qeth_cm_setup(card); 2165 if (rc) { 2166 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc); 2167 goto out_qdio; 2168 } 2169 rc = qeth_ulp_enable(card); 2170 if (rc) { 2171 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc); 2172 goto out_qdio; 2173 } 2174 rc = qeth_ulp_setup(card); 2175 if (rc) { 2176 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc); 2177 goto out_qdio; 2178 } 2179 rc = qeth_alloc_qdio_buffers(card); 2180 if (rc) { 2181 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc); 2182 goto out_qdio; 2183 } 2184 rc = qeth_qdio_establish(card); 2185 if (rc) { 2186 QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc); 2187 qeth_free_qdio_buffers(card); 2188 goto out_qdio; 2189 } 2190 rc = qeth_qdio_activate(card); 2191 if (rc) { 2192 QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc); 2193 goto out_qdio; 2194 } 2195 rc = qeth_dm_act(card); 2196 if (rc) { 2197 QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc); 2198 goto out_qdio; 2199 } 2200 2201 return 0; 2202 out_qdio: 2203 qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD); 2204 return rc; 2205 } 2206 2207 static void qeth_print_status_with_portname(struct qeth_card *card) 2208 { 2209 char dbf_text[15]; 2210 int i; 2211 2212 sprintf(dbf_text, "%s", card->info.portname + 1); 2213 for (i = 0; i < 8; i++) 2214 dbf_text[i] = 2215 (char) _ebcasc[(__u8) dbf_text[i]]; 2216 dbf_text[8] = 0; 2217 dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n" 2218 "with link type %s (portname: %s)\n", 2219 qeth_get_cardname(card), 2220 (card->info.mcl_level[0]) ? " (level: " : "", 2221 (card->info.mcl_level[0]) ? card->info.mcl_level : "", 2222 (card->info.mcl_level[0]) ? ")" : "", 2223 qeth_get_cardname_short(card), 2224 dbf_text); 2225 2226 } 2227 2228 static void qeth_print_status_no_portname(struct qeth_card *card) 2229 { 2230 if (card->info.portname[0]) 2231 dev_info(&card->gdev->dev, "Device is a%s " 2232 "card%s%s%s\nwith link type %s " 2233 "(no portname needed by interface).\n", 2234 qeth_get_cardname(card), 2235 (card->info.mcl_level[0]) ? " (level: " : "", 2236 (card->info.mcl_level[0]) ? card->info.mcl_level : "", 2237 (card->info.mcl_level[0]) ? ")" : "", 2238 qeth_get_cardname_short(card)); 2239 else 2240 dev_info(&card->gdev->dev, "Device is a%s " 2241 "card%s%s%s\nwith link type %s.\n", 2242 qeth_get_cardname(card), 2243 (card->info.mcl_level[0]) ? " (level: " : "", 2244 (card->info.mcl_level[0]) ? card->info.mcl_level : "", 2245 (card->info.mcl_level[0]) ? ")" : "", 2246 qeth_get_cardname_short(card)); 2247 } 2248 2249 void qeth_print_status_message(struct qeth_card *card) 2250 { 2251 switch (card->info.type) { 2252 case QETH_CARD_TYPE_OSAE: 2253 /* VM will use a non-zero first character 2254 * to indicate a HiperSockets like reporting 2255 * of the level OSA sets the first character to zero 2256 * */ 2257 if (!card->info.mcl_level[0]) { 2258 sprintf(card->info.mcl_level, "%02x%02x", 2259 card->info.mcl_level[2], 2260 card->info.mcl_level[3]); 2261 2262 card->info.mcl_level[QETH_MCL_LENGTH] = 0; 2263 break; 2264 } 2265 /* fallthrough */ 2266 case QETH_CARD_TYPE_IQD: 2267 if ((card->info.guestlan) || 2268 (card->info.mcl_level[0] & 0x80)) { 2269 card->info.mcl_level[0] = (char) _ebcasc[(__u8) 2270 card->info.mcl_level[0]]; 2271 card->info.mcl_level[1] = (char) _ebcasc[(__u8) 2272 card->info.mcl_level[1]]; 2273 card->info.mcl_level[2] = (char) _ebcasc[(__u8) 2274 card->info.mcl_level[2]]; 2275 card->info.mcl_level[3] = (char) _ebcasc[(__u8) 2276 card->info.mcl_level[3]]; 2277 card->info.mcl_level[QETH_MCL_LENGTH] = 0; 2278 } 2279 break; 2280 default: 2281 memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1); 2282 } 2283 if (card->info.portname_required) 2284 qeth_print_status_with_portname(card); 2285 else 2286 qeth_print_status_no_portname(card); 2287 } 2288 EXPORT_SYMBOL_GPL(qeth_print_status_message); 2289 2290 static void qeth_initialize_working_pool_list(struct qeth_card *card) 2291 { 2292 struct qeth_buffer_pool_entry *entry; 2293 2294 QETH_DBF_TEXT(TRACE, 5, "inwrklst"); 2295 2296 list_for_each_entry(entry, 2297 &card->qdio.init_pool.entry_list, init_list) { 2298 qeth_put_buffer_pool_entry(card, entry); 2299 } 2300 } 2301 2302 static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry( 2303 struct qeth_card *card) 2304 { 2305 struct list_head *plh; 2306 struct qeth_buffer_pool_entry *entry; 2307 int i, free; 2308 struct page *page; 2309 2310 if (list_empty(&card->qdio.in_buf_pool.entry_list)) 2311 return NULL; 2312 2313 list_for_each(plh, &card->qdio.in_buf_pool.entry_list) { 2314 entry = list_entry(plh, struct qeth_buffer_pool_entry, list); 2315 free = 1; 2316 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) { 2317 if (page_count(virt_to_page(entry->elements[i])) > 1) { 2318 free = 0; 2319 break; 2320 } 2321 } 2322 if (free) { 2323 list_del_init(&entry->list); 2324 return entry; 2325 } 2326 } 2327 2328 /* no free buffer in pool so take first one and swap pages */ 2329 entry = list_entry(card->qdio.in_buf_pool.entry_list.next, 2330 struct qeth_buffer_pool_entry, list); 2331 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) { 2332 if (page_count(virt_to_page(entry->elements[i])) > 1) { 2333 page = alloc_page(GFP_ATOMIC); 2334 if (!page) { 2335 return NULL; 2336 } else { 2337 free_page((unsigned long)entry->elements[i]); 2338 entry->elements[i] = page_address(page); 2339 if (card->options.performance_stats) 2340 card->perf_stats.sg_alloc_page_rx++; 2341 } 2342 } 2343 } 2344 list_del_init(&entry->list); 2345 return entry; 2346 } 2347 2348 static int qeth_init_input_buffer(struct qeth_card *card, 2349 struct qeth_qdio_buffer *buf) 2350 { 2351 struct qeth_buffer_pool_entry *pool_entry; 2352 int i; 2353 2354 pool_entry = qeth_find_free_buffer_pool_entry(card); 2355 if (!pool_entry) 2356 return 1; 2357 2358 /* 2359 * since the buffer is accessed only from the input_tasklet 2360 * there shouldn't be a need to synchronize; also, since we use 2361 * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off 2362 * buffers 2363 */ 2364 2365 buf->pool_entry = pool_entry; 2366 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) { 2367 buf->buffer->element[i].length = PAGE_SIZE; 2368 buf->buffer->element[i].addr = pool_entry->elements[i]; 2369 if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1) 2370 buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY; 2371 else 2372 buf->buffer->element[i].flags = 0; 2373 } 2374 return 0; 2375 } 2376 2377 int qeth_init_qdio_queues(struct qeth_card *card) 2378 { 2379 int i, j; 2380 int rc; 2381 2382 QETH_DBF_TEXT(SETUP, 2, "initqdqs"); 2383 2384 /* inbound queue */ 2385 memset(card->qdio.in_q->qdio_bufs, 0, 2386 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer)); 2387 qeth_initialize_working_pool_list(card); 2388 /*give only as many buffers to hardware as we have buffer pool entries*/ 2389 for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i) 2390 qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]); 2391 card->qdio.in_q->next_buf_to_init = 2392 card->qdio.in_buf_pool.buf_count - 1; 2393 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0, 2394 card->qdio.in_buf_pool.buf_count - 1); 2395 if (rc) { 2396 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc); 2397 return rc; 2398 } 2399 /* outbound queue */ 2400 for (i = 0; i < card->qdio.no_out_queues; ++i) { 2401 memset(card->qdio.out_qs[i]->qdio_bufs, 0, 2402 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer)); 2403 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) { 2404 qeth_clear_output_buffer(card->qdio.out_qs[i], 2405 &card->qdio.out_qs[i]->bufs[j]); 2406 } 2407 card->qdio.out_qs[i]->card = card; 2408 card->qdio.out_qs[i]->next_buf_to_fill = 0; 2409 card->qdio.out_qs[i]->do_pack = 0; 2410 atomic_set(&card->qdio.out_qs[i]->used_buffers, 0); 2411 atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0); 2412 atomic_set(&card->qdio.out_qs[i]->state, 2413 QETH_OUT_Q_UNLOCKED); 2414 } 2415 return 0; 2416 } 2417 EXPORT_SYMBOL_GPL(qeth_init_qdio_queues); 2418 2419 static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type) 2420 { 2421 switch (link_type) { 2422 case QETH_LINK_TYPE_HSTR: 2423 return 2; 2424 default: 2425 return 1; 2426 } 2427 } 2428 2429 static void qeth_fill_ipacmd_header(struct qeth_card *card, 2430 struct qeth_ipa_cmd *cmd, __u8 command, 2431 enum qeth_prot_versions prot) 2432 { 2433 memset(cmd, 0, sizeof(struct qeth_ipa_cmd)); 2434 cmd->hdr.command = command; 2435 cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST; 2436 cmd->hdr.seqno = card->seqno.ipa; 2437 cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type); 2438 cmd->hdr.rel_adapter_no = (__u8) card->info.portno; 2439 if (card->options.layer2) 2440 cmd->hdr.prim_version_no = 2; 2441 else 2442 cmd->hdr.prim_version_no = 1; 2443 cmd->hdr.param_count = 1; 2444 cmd->hdr.prot_version = prot; 2445 cmd->hdr.ipa_supported = 0; 2446 cmd->hdr.ipa_enabled = 0; 2447 } 2448 2449 struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card, 2450 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot) 2451 { 2452 struct qeth_cmd_buffer *iob; 2453 struct qeth_ipa_cmd *cmd; 2454 2455 iob = qeth_wait_for_buffer(&card->write); 2456 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE); 2457 qeth_fill_ipacmd_header(card, cmd, ipacmd, prot); 2458 2459 return iob; 2460 } 2461 EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer); 2462 2463 void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob, 2464 char prot_type) 2465 { 2466 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE); 2467 memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1); 2468 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data), 2469 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH); 2470 } 2471 EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd); 2472 2473 int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob, 2474 int (*reply_cb)(struct qeth_card *, struct qeth_reply*, 2475 unsigned long), 2476 void *reply_param) 2477 { 2478 int rc; 2479 char prot_type; 2480 2481 QETH_DBF_TEXT(TRACE, 4, "sendipa"); 2482 2483 if (card->options.layer2) 2484 if (card->info.type == QETH_CARD_TYPE_OSN) 2485 prot_type = QETH_PROT_OSN2; 2486 else 2487 prot_type = QETH_PROT_LAYER2; 2488 else 2489 prot_type = QETH_PROT_TCPIP; 2490 qeth_prepare_ipa_cmd(card, iob, prot_type); 2491 rc = qeth_send_control_data(card, IPA_CMD_LENGTH, 2492 iob, reply_cb, reply_param); 2493 return rc; 2494 } 2495 EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd); 2496 2497 static int qeth_send_startstoplan(struct qeth_card *card, 2498 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot) 2499 { 2500 int rc; 2501 struct qeth_cmd_buffer *iob; 2502 2503 iob = qeth_get_ipacmd_buffer(card, ipacmd, prot); 2504 rc = qeth_send_ipa_cmd(card, iob, NULL, NULL); 2505 2506 return rc; 2507 } 2508 2509 int qeth_send_startlan(struct qeth_card *card) 2510 { 2511 int rc; 2512 2513 QETH_DBF_TEXT(SETUP, 2, "strtlan"); 2514 2515 rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0); 2516 return rc; 2517 } 2518 EXPORT_SYMBOL_GPL(qeth_send_startlan); 2519 2520 int qeth_send_stoplan(struct qeth_card *card) 2521 { 2522 int rc = 0; 2523 2524 /* 2525 * TODO: according to the IPA format document page 14, 2526 * TCP/IP (we!) never issue a STOPLAN 2527 * is this right ?!? 2528 */ 2529 QETH_DBF_TEXT(SETUP, 2, "stoplan"); 2530 2531 rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0); 2532 return rc; 2533 } 2534 EXPORT_SYMBOL_GPL(qeth_send_stoplan); 2535 2536 int qeth_default_setadapterparms_cb(struct qeth_card *card, 2537 struct qeth_reply *reply, unsigned long data) 2538 { 2539 struct qeth_ipa_cmd *cmd; 2540 2541 QETH_DBF_TEXT(TRACE, 4, "defadpcb"); 2542 2543 cmd = (struct qeth_ipa_cmd *) data; 2544 if (cmd->hdr.return_code == 0) 2545 cmd->hdr.return_code = 2546 cmd->data.setadapterparms.hdr.return_code; 2547 return 0; 2548 } 2549 EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb); 2550 2551 static int qeth_query_setadapterparms_cb(struct qeth_card *card, 2552 struct qeth_reply *reply, unsigned long data) 2553 { 2554 struct qeth_ipa_cmd *cmd; 2555 2556 QETH_DBF_TEXT(TRACE, 3, "quyadpcb"); 2557 2558 cmd = (struct qeth_ipa_cmd *) data; 2559 if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) 2560 card->info.link_type = 2561 cmd->data.setadapterparms.data.query_cmds_supp.lan_type; 2562 card->options.adp.supported_funcs = 2563 cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds; 2564 return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd); 2565 } 2566 2567 struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card, 2568 __u32 command, __u32 cmdlen) 2569 { 2570 struct qeth_cmd_buffer *iob; 2571 struct qeth_ipa_cmd *cmd; 2572 2573 iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS, 2574 QETH_PROT_IPV4); 2575 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE); 2576 cmd->data.setadapterparms.hdr.cmdlength = cmdlen; 2577 cmd->data.setadapterparms.hdr.command_code = command; 2578 cmd->data.setadapterparms.hdr.used_total = 1; 2579 cmd->data.setadapterparms.hdr.seq_no = 1; 2580 2581 return iob; 2582 } 2583 EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd); 2584 2585 int qeth_query_setadapterparms(struct qeth_card *card) 2586 { 2587 int rc; 2588 struct qeth_cmd_buffer *iob; 2589 2590 QETH_DBF_TEXT(TRACE, 3, "queryadp"); 2591 iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED, 2592 sizeof(struct qeth_ipacmd_setadpparms)); 2593 rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL); 2594 return rc; 2595 } 2596 EXPORT_SYMBOL_GPL(qeth_query_setadapterparms); 2597 2598 int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error, 2599 const char *dbftext) 2600 { 2601 if (qdio_error) { 2602 QETH_DBF_TEXT(TRACE, 2, dbftext); 2603 QETH_DBF_TEXT(QERR, 2, dbftext); 2604 QETH_DBF_TEXT_(QERR, 2, " F15=%02X", 2605 buf->element[15].flags & 0xff); 2606 QETH_DBF_TEXT_(QERR, 2, " F14=%02X", 2607 buf->element[14].flags & 0xff); 2608 QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error); 2609 return 1; 2610 } 2611 return 0; 2612 } 2613 EXPORT_SYMBOL_GPL(qeth_check_qdio_errors); 2614 2615 void qeth_queue_input_buffer(struct qeth_card *card, int index) 2616 { 2617 struct qeth_qdio_q *queue = card->qdio.in_q; 2618 int count; 2619 int i; 2620 int rc; 2621 int newcount = 0; 2622 2623 count = (index < queue->next_buf_to_init)? 2624 card->qdio.in_buf_pool.buf_count - 2625 (queue->next_buf_to_init - index) : 2626 card->qdio.in_buf_pool.buf_count - 2627 (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index); 2628 /* only requeue at a certain threshold to avoid SIGAs */ 2629 if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) { 2630 for (i = queue->next_buf_to_init; 2631 i < queue->next_buf_to_init + count; ++i) { 2632 if (qeth_init_input_buffer(card, 2633 &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) { 2634 break; 2635 } else { 2636 newcount++; 2637 } 2638 } 2639 2640 if (newcount < count) { 2641 /* we are in memory shortage so we switch back to 2642 traditional skb allocation and drop packages */ 2643 atomic_set(&card->force_alloc_skb, 3); 2644 count = newcount; 2645 } else { 2646 atomic_add_unless(&card->force_alloc_skb, -1, 0); 2647 } 2648 2649 /* 2650 * according to old code it should be avoided to requeue all 2651 * 128 buffers in order to benefit from PCI avoidance. 2652 * this function keeps at least one buffer (the buffer at 2653 * 'index') un-requeued -> this buffer is the first buffer that 2654 * will be requeued the next time 2655 */ 2656 if (card->options.performance_stats) { 2657 card->perf_stats.inbound_do_qdio_cnt++; 2658 card->perf_stats.inbound_do_qdio_start_time = 2659 qeth_get_micros(); 2660 } 2661 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 2662 queue->next_buf_to_init, count); 2663 if (card->options.performance_stats) 2664 card->perf_stats.inbound_do_qdio_time += 2665 qeth_get_micros() - 2666 card->perf_stats.inbound_do_qdio_start_time; 2667 if (rc) { 2668 dev_warn(&card->gdev->dev, 2669 "QDIO reported an error, rc=%i\n", rc); 2670 QETH_DBF_TEXT(TRACE, 2, "qinberr"); 2671 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card)); 2672 } 2673 queue->next_buf_to_init = (queue->next_buf_to_init + count) % 2674 QDIO_MAX_BUFFERS_PER_Q; 2675 } 2676 } 2677 EXPORT_SYMBOL_GPL(qeth_queue_input_buffer); 2678 2679 static int qeth_handle_send_error(struct qeth_card *card, 2680 struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err) 2681 { 2682 int sbalf15 = buffer->buffer->element[15].flags & 0xff; 2683 2684 QETH_DBF_TEXT(TRACE, 6, "hdsnderr"); 2685 qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr"); 2686 2687 if (!qdio_err) 2688 return QETH_SEND_ERROR_NONE; 2689 2690 if ((sbalf15 >= 15) && (sbalf15 <= 31)) 2691 return QETH_SEND_ERROR_RETRY; 2692 2693 QETH_DBF_TEXT(TRACE, 1, "lnkfail"); 2694 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card)); 2695 QETH_DBF_TEXT_(TRACE, 1, "%04x %02x", 2696 (u16)qdio_err, (u8)sbalf15); 2697 return QETH_SEND_ERROR_LINK_FAILURE; 2698 } 2699 2700 /* 2701 * Switched to packing state if the number of used buffers on a queue 2702 * reaches a certain limit. 2703 */ 2704 static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue) 2705 { 2706 if (!queue->do_pack) { 2707 if (atomic_read(&queue->used_buffers) 2708 >= QETH_HIGH_WATERMARK_PACK){ 2709 /* switch non-PACKING -> PACKING */ 2710 QETH_DBF_TEXT(TRACE, 6, "np->pack"); 2711 if (queue->card->options.performance_stats) 2712 queue->card->perf_stats.sc_dp_p++; 2713 queue->do_pack = 1; 2714 } 2715 } 2716 } 2717 2718 /* 2719 * Switches from packing to non-packing mode. If there is a packing 2720 * buffer on the queue this buffer will be prepared to be flushed. 2721 * In that case 1 is returned to inform the caller. If no buffer 2722 * has to be flushed, zero is returned. 2723 */ 2724 static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue) 2725 { 2726 struct qeth_qdio_out_buffer *buffer; 2727 int flush_count = 0; 2728 2729 if (queue->do_pack) { 2730 if (atomic_read(&queue->used_buffers) 2731 <= QETH_LOW_WATERMARK_PACK) { 2732 /* switch PACKING -> non-PACKING */ 2733 QETH_DBF_TEXT(TRACE, 6, "pack->np"); 2734 if (queue->card->options.performance_stats) 2735 queue->card->perf_stats.sc_p_dp++; 2736 queue->do_pack = 0; 2737 /* flush packing buffers */ 2738 buffer = &queue->bufs[queue->next_buf_to_fill]; 2739 if ((atomic_read(&buffer->state) == 2740 QETH_QDIO_BUF_EMPTY) && 2741 (buffer->next_element_to_fill > 0)) { 2742 atomic_set(&buffer->state, 2743 QETH_QDIO_BUF_PRIMED); 2744 flush_count++; 2745 queue->next_buf_to_fill = 2746 (queue->next_buf_to_fill + 1) % 2747 QDIO_MAX_BUFFERS_PER_Q; 2748 } 2749 } 2750 } 2751 return flush_count; 2752 } 2753 2754 /* 2755 * Called to flush a packing buffer if no more pci flags are on the queue. 2756 * Checks if there is a packing buffer and prepares it to be flushed. 2757 * In that case returns 1, otherwise zero. 2758 */ 2759 static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue) 2760 { 2761 struct qeth_qdio_out_buffer *buffer; 2762 2763 buffer = &queue->bufs[queue->next_buf_to_fill]; 2764 if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) && 2765 (buffer->next_element_to_fill > 0)) { 2766 /* it's a packing buffer */ 2767 atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED); 2768 queue->next_buf_to_fill = 2769 (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q; 2770 return 1; 2771 } 2772 return 0; 2773 } 2774 2775 static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index, 2776 int count) 2777 { 2778 struct qeth_qdio_out_buffer *buf; 2779 int rc; 2780 int i; 2781 unsigned int qdio_flags; 2782 2783 for (i = index; i < index + count; ++i) { 2784 buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q]; 2785 buf->buffer->element[buf->next_element_to_fill - 1].flags |= 2786 SBAL_FLAGS_LAST_ENTRY; 2787 2788 if (queue->card->info.type == QETH_CARD_TYPE_IQD) 2789 continue; 2790 2791 if (!queue->do_pack) { 2792 if ((atomic_read(&queue->used_buffers) >= 2793 (QETH_HIGH_WATERMARK_PACK - 2794 QETH_WATERMARK_PACK_FUZZ)) && 2795 !atomic_read(&queue->set_pci_flags_count)) { 2796 /* it's likely that we'll go to packing 2797 * mode soon */ 2798 atomic_inc(&queue->set_pci_flags_count); 2799 buf->buffer->element[0].flags |= 0x40; 2800 } 2801 } else { 2802 if (!atomic_read(&queue->set_pci_flags_count)) { 2803 /* 2804 * there's no outstanding PCI any more, so we 2805 * have to request a PCI to be sure the the PCI 2806 * will wake at some time in the future then we 2807 * can flush packed buffers that might still be 2808 * hanging around, which can happen if no 2809 * further send was requested by the stack 2810 */ 2811 atomic_inc(&queue->set_pci_flags_count); 2812 buf->buffer->element[0].flags |= 0x40; 2813 } 2814 } 2815 } 2816 2817 queue->card->dev->trans_start = jiffies; 2818 if (queue->card->options.performance_stats) { 2819 queue->card->perf_stats.outbound_do_qdio_cnt++; 2820 queue->card->perf_stats.outbound_do_qdio_start_time = 2821 qeth_get_micros(); 2822 } 2823 qdio_flags = QDIO_FLAG_SYNC_OUTPUT; 2824 if (atomic_read(&queue->set_pci_flags_count)) 2825 qdio_flags |= QDIO_FLAG_PCI_OUT; 2826 rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags, 2827 queue->queue_no, index, count); 2828 if (queue->card->options.performance_stats) 2829 queue->card->perf_stats.outbound_do_qdio_time += 2830 qeth_get_micros() - 2831 queue->card->perf_stats.outbound_do_qdio_start_time; 2832 if (rc) { 2833 queue->card->stats.tx_errors += count; 2834 /* ignore temporary SIGA errors without busy condition */ 2835 if (rc == QDIO_ERROR_SIGA_TARGET) 2836 return; 2837 QETH_DBF_TEXT(TRACE, 2, "flushbuf"); 2838 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc); 2839 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card)); 2840 2841 /* this must not happen under normal circumstances. if it 2842 * happens something is really wrong -> recover */ 2843 qeth_schedule_recovery(queue->card); 2844 return; 2845 } 2846 atomic_add(count, &queue->used_buffers); 2847 if (queue->card->options.performance_stats) 2848 queue->card->perf_stats.bufs_sent += count; 2849 } 2850 2851 static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue) 2852 { 2853 int index; 2854 int flush_cnt = 0; 2855 int q_was_packing = 0; 2856 2857 /* 2858 * check if weed have to switch to non-packing mode or if 2859 * we have to get a pci flag out on the queue 2860 */ 2861 if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) || 2862 !atomic_read(&queue->set_pci_flags_count)) { 2863 if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) == 2864 QETH_OUT_Q_UNLOCKED) { 2865 /* 2866 * If we get in here, there was no action in 2867 * do_send_packet. So, we check if there is a 2868 * packing buffer to be flushed here. 2869 */ 2870 netif_stop_queue(queue->card->dev); 2871 index = queue->next_buf_to_fill; 2872 q_was_packing = queue->do_pack; 2873 /* queue->do_pack may change */ 2874 barrier(); 2875 flush_cnt += qeth_switch_to_nonpacking_if_needed(queue); 2876 if (!flush_cnt && 2877 !atomic_read(&queue->set_pci_flags_count)) 2878 flush_cnt += 2879 qeth_flush_buffers_on_no_pci(queue); 2880 if (queue->card->options.performance_stats && 2881 q_was_packing) 2882 queue->card->perf_stats.bufs_sent_pack += 2883 flush_cnt; 2884 if (flush_cnt) 2885 qeth_flush_buffers(queue, index, flush_cnt); 2886 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED); 2887 } 2888 } 2889 } 2890 2891 void qeth_qdio_output_handler(struct ccw_device *ccwdev, 2892 unsigned int qdio_error, int __queue, int first_element, 2893 int count, unsigned long card_ptr) 2894 { 2895 struct qeth_card *card = (struct qeth_card *) card_ptr; 2896 struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue]; 2897 struct qeth_qdio_out_buffer *buffer; 2898 int i; 2899 2900 QETH_DBF_TEXT(TRACE, 6, "qdouhdl"); 2901 if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) { 2902 QETH_DBF_TEXT(TRACE, 2, "achkcond"); 2903 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card)); 2904 netif_stop_queue(card->dev); 2905 qeth_schedule_recovery(card); 2906 return; 2907 } 2908 if (card->options.performance_stats) { 2909 card->perf_stats.outbound_handler_cnt++; 2910 card->perf_stats.outbound_handler_start_time = 2911 qeth_get_micros(); 2912 } 2913 for (i = first_element; i < (first_element + count); ++i) { 2914 buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q]; 2915 qeth_handle_send_error(card, buffer, qdio_error); 2916 qeth_clear_output_buffer(queue, buffer); 2917 } 2918 atomic_sub(count, &queue->used_buffers); 2919 /* check if we need to do something on this outbound queue */ 2920 if (card->info.type != QETH_CARD_TYPE_IQD) 2921 qeth_check_outbound_queue(queue); 2922 2923 netif_wake_queue(queue->card->dev); 2924 if (card->options.performance_stats) 2925 card->perf_stats.outbound_handler_time += qeth_get_micros() - 2926 card->perf_stats.outbound_handler_start_time; 2927 } 2928 EXPORT_SYMBOL_GPL(qeth_qdio_output_handler); 2929 2930 int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb) 2931 { 2932 int cast_type = RTN_UNSPEC; 2933 2934 if (card->info.type == QETH_CARD_TYPE_OSN) 2935 return cast_type; 2936 2937 if (skb->dst && skb->dst->neighbour) { 2938 cast_type = skb->dst->neighbour->type; 2939 if ((cast_type == RTN_BROADCAST) || 2940 (cast_type == RTN_MULTICAST) || 2941 (cast_type == RTN_ANYCAST)) 2942 return cast_type; 2943 else 2944 return RTN_UNSPEC; 2945 } 2946 /* try something else */ 2947 if (skb->protocol == ETH_P_IPV6) 2948 return (skb_network_header(skb)[24] == 0xff) ? 2949 RTN_MULTICAST : 0; 2950 else if (skb->protocol == ETH_P_IP) 2951 return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ? 2952 RTN_MULTICAST : 0; 2953 /* ... */ 2954 if (!memcmp(skb->data, skb->dev->broadcast, 6)) 2955 return RTN_BROADCAST; 2956 else { 2957 u16 hdr_mac; 2958 2959 hdr_mac = *((u16 *)skb->data); 2960 /* tr multicast? */ 2961 switch (card->info.link_type) { 2962 case QETH_LINK_TYPE_HSTR: 2963 case QETH_LINK_TYPE_LANE_TR: 2964 if ((hdr_mac == QETH_TR_MAC_NC) || 2965 (hdr_mac == QETH_TR_MAC_C)) 2966 return RTN_MULTICAST; 2967 break; 2968 /* eth or so multicast? */ 2969 default: 2970 if ((hdr_mac == QETH_ETH_MAC_V4) || 2971 (hdr_mac == QETH_ETH_MAC_V6)) 2972 return RTN_MULTICAST; 2973 } 2974 } 2975 return cast_type; 2976 } 2977 EXPORT_SYMBOL_GPL(qeth_get_cast_type); 2978 2979 int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb, 2980 int ipv, int cast_type) 2981 { 2982 if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE)) 2983 return card->qdio.default_out_queue; 2984 switch (card->qdio.no_out_queues) { 2985 case 4: 2986 if (cast_type && card->info.is_multicast_different) 2987 return card->info.is_multicast_different & 2988 (card->qdio.no_out_queues - 1); 2989 if (card->qdio.do_prio_queueing && (ipv == 4)) { 2990 const u8 tos = ip_hdr(skb)->tos; 2991 2992 if (card->qdio.do_prio_queueing == 2993 QETH_PRIO_Q_ING_TOS) { 2994 if (tos & IP_TOS_NOTIMPORTANT) 2995 return 3; 2996 if (tos & IP_TOS_HIGHRELIABILITY) 2997 return 2; 2998 if (tos & IP_TOS_HIGHTHROUGHPUT) 2999 return 1; 3000 if (tos & IP_TOS_LOWDELAY) 3001 return 0; 3002 } 3003 if (card->qdio.do_prio_queueing == 3004 QETH_PRIO_Q_ING_PREC) 3005 return 3 - (tos >> 6); 3006 } else if (card->qdio.do_prio_queueing && (ipv == 6)) { 3007 /* TODO: IPv6!!! */ 3008 } 3009 return card->qdio.default_out_queue; 3010 case 1: /* fallthrough for single-out-queue 1920-device */ 3011 default: 3012 return card->qdio.default_out_queue; 3013 } 3014 } 3015 EXPORT_SYMBOL_GPL(qeth_get_priority_queue); 3016 3017 int qeth_get_elements_no(struct qeth_card *card, void *hdr, 3018 struct sk_buff *skb, int elems) 3019 { 3020 int elements_needed = 0; 3021 3022 if (skb_shinfo(skb)->nr_frags > 0) 3023 elements_needed = (skb_shinfo(skb)->nr_frags + 1); 3024 if (elements_needed == 0) 3025 elements_needed = 1 + (((((unsigned long) skb->data) % 3026 PAGE_SIZE) + skb->len) >> PAGE_SHIFT); 3027 if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) { 3028 QETH_DBF_MESSAGE(2, "Invalid size of IP packet " 3029 "(Number=%d / Length=%d). Discarded.\n", 3030 (elements_needed+elems), skb->len); 3031 return 0; 3032 } 3033 return elements_needed; 3034 } 3035 EXPORT_SYMBOL_GPL(qeth_get_elements_no); 3036 3037 static inline void __qeth_fill_buffer(struct sk_buff *skb, 3038 struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill, 3039 int offset) 3040 { 3041 int length = skb->len; 3042 int length_here; 3043 int element; 3044 char *data; 3045 int first_lap ; 3046 3047 element = *next_element_to_fill; 3048 data = skb->data; 3049 first_lap = (is_tso == 0 ? 1 : 0); 3050 3051 if (offset >= 0) { 3052 data = skb->data + offset; 3053 length -= offset; 3054 first_lap = 0; 3055 } 3056 3057 while (length > 0) { 3058 /* length_here is the remaining amount of data in this page */ 3059 length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE); 3060 if (length < length_here) 3061 length_here = length; 3062 3063 buffer->element[element].addr = data; 3064 buffer->element[element].length = length_here; 3065 length -= length_here; 3066 if (!length) { 3067 if (first_lap) 3068 buffer->element[element].flags = 0; 3069 else 3070 buffer->element[element].flags = 3071 SBAL_FLAGS_LAST_FRAG; 3072 } else { 3073 if (first_lap) 3074 buffer->element[element].flags = 3075 SBAL_FLAGS_FIRST_FRAG; 3076 else 3077 buffer->element[element].flags = 3078 SBAL_FLAGS_MIDDLE_FRAG; 3079 } 3080 data += length_here; 3081 element++; 3082 first_lap = 0; 3083 } 3084 *next_element_to_fill = element; 3085 } 3086 3087 static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue, 3088 struct qeth_qdio_out_buffer *buf, struct sk_buff *skb, 3089 struct qeth_hdr *hdr, int offset, int hd_len) 3090 { 3091 struct qdio_buffer *buffer; 3092 int flush_cnt = 0, hdr_len, large_send = 0; 3093 3094 buffer = buf->buffer; 3095 atomic_inc(&skb->users); 3096 skb_queue_tail(&buf->skb_list, skb); 3097 3098 /*check first on TSO ....*/ 3099 if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) { 3100 int element = buf->next_element_to_fill; 3101 3102 hdr_len = sizeof(struct qeth_hdr_tso) + 3103 ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len; 3104 /*fill first buffer entry only with header information */ 3105 buffer->element[element].addr = skb->data; 3106 buffer->element[element].length = hdr_len; 3107 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG; 3108 buf->next_element_to_fill++; 3109 skb->data += hdr_len; 3110 skb->len -= hdr_len; 3111 large_send = 1; 3112 } 3113 3114 if (offset >= 0) { 3115 int element = buf->next_element_to_fill; 3116 buffer->element[element].addr = hdr; 3117 buffer->element[element].length = sizeof(struct qeth_hdr) + 3118 hd_len; 3119 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG; 3120 buf->is_header[element] = 1; 3121 buf->next_element_to_fill++; 3122 } 3123 3124 if (skb_shinfo(skb)->nr_frags == 0) 3125 __qeth_fill_buffer(skb, buffer, large_send, 3126 (int *)&buf->next_element_to_fill, offset); 3127 else 3128 __qeth_fill_buffer_frag(skb, buffer, large_send, 3129 (int *)&buf->next_element_to_fill); 3130 3131 if (!queue->do_pack) { 3132 QETH_DBF_TEXT(TRACE, 6, "fillbfnp"); 3133 /* set state to PRIMED -> will be flushed */ 3134 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED); 3135 flush_cnt = 1; 3136 } else { 3137 QETH_DBF_TEXT(TRACE, 6, "fillbfpa"); 3138 if (queue->card->options.performance_stats) 3139 queue->card->perf_stats.skbs_sent_pack++; 3140 if (buf->next_element_to_fill >= 3141 QETH_MAX_BUFFER_ELEMENTS(queue->card)) { 3142 /* 3143 * packed buffer if full -> set state PRIMED 3144 * -> will be flushed 3145 */ 3146 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED); 3147 flush_cnt = 1; 3148 } 3149 } 3150 return flush_cnt; 3151 } 3152 3153 int qeth_do_send_packet_fast(struct qeth_card *card, 3154 struct qeth_qdio_out_q *queue, struct sk_buff *skb, 3155 struct qeth_hdr *hdr, int elements_needed, 3156 int offset, int hd_len) 3157 { 3158 struct qeth_qdio_out_buffer *buffer; 3159 int index; 3160 3161 /* spin until we get the queue ... */ 3162 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED, 3163 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED); 3164 /* ... now we've got the queue */ 3165 index = queue->next_buf_to_fill; 3166 buffer = &queue->bufs[queue->next_buf_to_fill]; 3167 /* 3168 * check if buffer is empty to make sure that we do not 'overtake' 3169 * ourselves and try to fill a buffer that is already primed 3170 */ 3171 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) 3172 goto out; 3173 queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) % 3174 QDIO_MAX_BUFFERS_PER_Q; 3175 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED); 3176 qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len); 3177 qeth_flush_buffers(queue, index, 1); 3178 return 0; 3179 out: 3180 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED); 3181 return -EBUSY; 3182 } 3183 EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast); 3184 3185 int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue, 3186 struct sk_buff *skb, struct qeth_hdr *hdr, 3187 int elements_needed) 3188 { 3189 struct qeth_qdio_out_buffer *buffer; 3190 int start_index; 3191 int flush_count = 0; 3192 int do_pack = 0; 3193 int tmp; 3194 int rc = 0; 3195 3196 /* spin until we get the queue ... */ 3197 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED, 3198 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED); 3199 start_index = queue->next_buf_to_fill; 3200 buffer = &queue->bufs[queue->next_buf_to_fill]; 3201 /* 3202 * check if buffer is empty to make sure that we do not 'overtake' 3203 * ourselves and try to fill a buffer that is already primed 3204 */ 3205 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) { 3206 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED); 3207 return -EBUSY; 3208 } 3209 /* check if we need to switch packing state of this queue */ 3210 qeth_switch_to_packing_if_needed(queue); 3211 if (queue->do_pack) { 3212 do_pack = 1; 3213 /* does packet fit in current buffer? */ 3214 if ((QETH_MAX_BUFFER_ELEMENTS(card) - 3215 buffer->next_element_to_fill) < elements_needed) { 3216 /* ... no -> set state PRIMED */ 3217 atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED); 3218 flush_count++; 3219 queue->next_buf_to_fill = 3220 (queue->next_buf_to_fill + 1) % 3221 QDIO_MAX_BUFFERS_PER_Q; 3222 buffer = &queue->bufs[queue->next_buf_to_fill]; 3223 /* we did a step forward, so check buffer state 3224 * again */ 3225 if (atomic_read(&buffer->state) != 3226 QETH_QDIO_BUF_EMPTY) { 3227 qeth_flush_buffers(queue, start_index, 3228 flush_count); 3229 atomic_set(&queue->state, 3230 QETH_OUT_Q_UNLOCKED); 3231 return -EBUSY; 3232 } 3233 } 3234 } 3235 tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0); 3236 queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) % 3237 QDIO_MAX_BUFFERS_PER_Q; 3238 flush_count += tmp; 3239 if (flush_count) 3240 qeth_flush_buffers(queue, start_index, flush_count); 3241 else if (!atomic_read(&queue->set_pci_flags_count)) 3242 atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH); 3243 /* 3244 * queue->state will go from LOCKED -> UNLOCKED or from 3245 * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us 3246 * (switch packing state or flush buffer to get another pci flag out). 3247 * In that case we will enter this loop 3248 */ 3249 while (atomic_dec_return(&queue->state)) { 3250 flush_count = 0; 3251 start_index = queue->next_buf_to_fill; 3252 /* check if we can go back to non-packing state */ 3253 flush_count += qeth_switch_to_nonpacking_if_needed(queue); 3254 /* 3255 * check if we need to flush a packing buffer to get a pci 3256 * flag out on the queue 3257 */ 3258 if (!flush_count && !atomic_read(&queue->set_pci_flags_count)) 3259 flush_count += qeth_flush_buffers_on_no_pci(queue); 3260 if (flush_count) 3261 qeth_flush_buffers(queue, start_index, flush_count); 3262 } 3263 /* at this point the queue is UNLOCKED again */ 3264 if (queue->card->options.performance_stats && do_pack) 3265 queue->card->perf_stats.bufs_sent_pack += flush_count; 3266 3267 return rc; 3268 } 3269 EXPORT_SYMBOL_GPL(qeth_do_send_packet); 3270 3271 static int qeth_setadp_promisc_mode_cb(struct qeth_card *card, 3272 struct qeth_reply *reply, unsigned long data) 3273 { 3274 struct qeth_ipa_cmd *cmd; 3275 struct qeth_ipacmd_setadpparms *setparms; 3276 3277 QETH_DBF_TEXT(TRACE, 4, "prmadpcb"); 3278 3279 cmd = (struct qeth_ipa_cmd *) data; 3280 setparms = &(cmd->data.setadapterparms); 3281 3282 qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd); 3283 if (cmd->hdr.return_code) { 3284 QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code); 3285 setparms->data.mode = SET_PROMISC_MODE_OFF; 3286 } 3287 card->info.promisc_mode = setparms->data.mode; 3288 return 0; 3289 } 3290 3291 void qeth_setadp_promisc_mode(struct qeth_card *card) 3292 { 3293 enum qeth_ipa_promisc_modes mode; 3294 struct net_device *dev = card->dev; 3295 struct qeth_cmd_buffer *iob; 3296 struct qeth_ipa_cmd *cmd; 3297 3298 QETH_DBF_TEXT(TRACE, 4, "setprom"); 3299 3300 if (((dev->flags & IFF_PROMISC) && 3301 (card->info.promisc_mode == SET_PROMISC_MODE_ON)) || 3302 (!(dev->flags & IFF_PROMISC) && 3303 (card->info.promisc_mode == SET_PROMISC_MODE_OFF))) 3304 return; 3305 mode = SET_PROMISC_MODE_OFF; 3306 if (dev->flags & IFF_PROMISC) 3307 mode = SET_PROMISC_MODE_ON; 3308 QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode); 3309 3310 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE, 3311 sizeof(struct qeth_ipacmd_setadpparms)); 3312 cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE); 3313 cmd->data.setadapterparms.data.mode = mode; 3314 qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL); 3315 } 3316 EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode); 3317 3318 int qeth_change_mtu(struct net_device *dev, int new_mtu) 3319 { 3320 struct qeth_card *card; 3321 char dbf_text[15]; 3322 3323 card = dev->ml_priv; 3324 3325 QETH_DBF_TEXT(TRACE, 4, "chgmtu"); 3326 sprintf(dbf_text, "%8x", new_mtu); 3327 QETH_DBF_TEXT(TRACE, 4, dbf_text); 3328 3329 if (new_mtu < 64) 3330 return -EINVAL; 3331 if (new_mtu > 65535) 3332 return -EINVAL; 3333 if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) && 3334 (!qeth_mtu_is_valid(card, new_mtu))) 3335 return -EINVAL; 3336 dev->mtu = new_mtu; 3337 return 0; 3338 } 3339 EXPORT_SYMBOL_GPL(qeth_change_mtu); 3340 3341 struct net_device_stats *qeth_get_stats(struct net_device *dev) 3342 { 3343 struct qeth_card *card; 3344 3345 card = dev->ml_priv; 3346 3347 QETH_DBF_TEXT(TRACE, 5, "getstat"); 3348 3349 return &card->stats; 3350 } 3351 EXPORT_SYMBOL_GPL(qeth_get_stats); 3352 3353 static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card, 3354 struct qeth_reply *reply, unsigned long data) 3355 { 3356 struct qeth_ipa_cmd *cmd; 3357 3358 QETH_DBF_TEXT(TRACE, 4, "chgmaccb"); 3359 3360 cmd = (struct qeth_ipa_cmd *) data; 3361 if (!card->options.layer2 || 3362 !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) { 3363 memcpy(card->dev->dev_addr, 3364 &cmd->data.setadapterparms.data.change_addr.addr, 3365 OSA_ADDR_LEN); 3366 card->info.mac_bits |= QETH_LAYER2_MAC_READ; 3367 } 3368 qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd); 3369 return 0; 3370 } 3371 3372 int qeth_setadpparms_change_macaddr(struct qeth_card *card) 3373 { 3374 int rc; 3375 struct qeth_cmd_buffer *iob; 3376 struct qeth_ipa_cmd *cmd; 3377 3378 QETH_DBF_TEXT(TRACE, 4, "chgmac"); 3379 3380 iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS, 3381 sizeof(struct qeth_ipacmd_setadpparms)); 3382 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE); 3383 cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC; 3384 cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN; 3385 memcpy(&cmd->data.setadapterparms.data.change_addr.addr, 3386 card->dev->dev_addr, OSA_ADDR_LEN); 3387 rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb, 3388 NULL); 3389 return rc; 3390 } 3391 EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr); 3392 3393 void qeth_tx_timeout(struct net_device *dev) 3394 { 3395 struct qeth_card *card; 3396 3397 card = dev->ml_priv; 3398 card->stats.tx_errors++; 3399 qeth_schedule_recovery(card); 3400 } 3401 EXPORT_SYMBOL_GPL(qeth_tx_timeout); 3402 3403 int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum) 3404 { 3405 struct qeth_card *card = dev->ml_priv; 3406 int rc = 0; 3407 3408 switch (regnum) { 3409 case MII_BMCR: /* Basic mode control register */ 3410 rc = BMCR_FULLDPLX; 3411 if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) && 3412 (card->info.link_type != QETH_LINK_TYPE_OSN) && 3413 (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH)) 3414 rc |= BMCR_SPEED100; 3415 break; 3416 case MII_BMSR: /* Basic mode status register */ 3417 rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS | 3418 BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL | 3419 BMSR_100BASE4; 3420 break; 3421 case MII_PHYSID1: /* PHYS ID 1 */ 3422 rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) | 3423 dev->dev_addr[2]; 3424 rc = (rc >> 5) & 0xFFFF; 3425 break; 3426 case MII_PHYSID2: /* PHYS ID 2 */ 3427 rc = (dev->dev_addr[2] << 10) & 0xFFFF; 3428 break; 3429 case MII_ADVERTISE: /* Advertisement control reg */ 3430 rc = ADVERTISE_ALL; 3431 break; 3432 case MII_LPA: /* Link partner ability reg */ 3433 rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL | 3434 LPA_100BASE4 | LPA_LPACK; 3435 break; 3436 case MII_EXPANSION: /* Expansion register */ 3437 break; 3438 case MII_DCOUNTER: /* disconnect counter */ 3439 break; 3440 case MII_FCSCOUNTER: /* false carrier counter */ 3441 break; 3442 case MII_NWAYTEST: /* N-way auto-neg test register */ 3443 break; 3444 case MII_RERRCOUNTER: /* rx error counter */ 3445 rc = card->stats.rx_errors; 3446 break; 3447 case MII_SREVISION: /* silicon revision */ 3448 break; 3449 case MII_RESV1: /* reserved 1 */ 3450 break; 3451 case MII_LBRERROR: /* loopback, rx, bypass error */ 3452 break; 3453 case MII_PHYADDR: /* physical address */ 3454 break; 3455 case MII_RESV2: /* reserved 2 */ 3456 break; 3457 case MII_TPISTATUS: /* TPI status for 10mbps */ 3458 break; 3459 case MII_NCONFIG: /* network interface config */ 3460 break; 3461 default: 3462 break; 3463 } 3464 return rc; 3465 } 3466 EXPORT_SYMBOL_GPL(qeth_mdio_read); 3467 3468 static int qeth_send_ipa_snmp_cmd(struct qeth_card *card, 3469 struct qeth_cmd_buffer *iob, int len, 3470 int (*reply_cb)(struct qeth_card *, struct qeth_reply *, 3471 unsigned long), 3472 void *reply_param) 3473 { 3474 u16 s1, s2; 3475 3476 QETH_DBF_TEXT(TRACE, 4, "sendsnmp"); 3477 3478 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE); 3479 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data), 3480 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH); 3481 /* adjust PDU length fields in IPA_PDU_HEADER */ 3482 s1 = (u32) IPA_PDU_HEADER_SIZE + len; 3483 s2 = (u32) len; 3484 memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2); 3485 memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2); 3486 memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2); 3487 memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2); 3488 return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob, 3489 reply_cb, reply_param); 3490 } 3491 3492 static int qeth_snmp_command_cb(struct qeth_card *card, 3493 struct qeth_reply *reply, unsigned long sdata) 3494 { 3495 struct qeth_ipa_cmd *cmd; 3496 struct qeth_arp_query_info *qinfo; 3497 struct qeth_snmp_cmd *snmp; 3498 unsigned char *data; 3499 __u16 data_len; 3500 3501 QETH_DBF_TEXT(TRACE, 3, "snpcmdcb"); 3502 3503 cmd = (struct qeth_ipa_cmd *) sdata; 3504 data = (unsigned char *)((char *)cmd - reply->offset); 3505 qinfo = (struct qeth_arp_query_info *) reply->param; 3506 snmp = &cmd->data.setadapterparms.data.snmp; 3507 3508 if (cmd->hdr.return_code) { 3509 QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code); 3510 return 0; 3511 } 3512 if (cmd->data.setadapterparms.hdr.return_code) { 3513 cmd->hdr.return_code = 3514 cmd->data.setadapterparms.hdr.return_code; 3515 QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code); 3516 return 0; 3517 } 3518 data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data)); 3519 if (cmd->data.setadapterparms.hdr.seq_no == 1) 3520 data_len -= (__u16)((char *)&snmp->data - (char *)cmd); 3521 else 3522 data_len -= (__u16)((char *)&snmp->request - (char *)cmd); 3523 3524 /* check if there is enough room in userspace */ 3525 if ((qinfo->udata_len - qinfo->udata_offset) < data_len) { 3526 QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM); 3527 cmd->hdr.return_code = -ENOMEM; 3528 return 0; 3529 } 3530 QETH_DBF_TEXT_(TRACE, 4, "snore%i", 3531 cmd->data.setadapterparms.hdr.used_total); 3532 QETH_DBF_TEXT_(TRACE, 4, "sseqn%i", 3533 cmd->data.setadapterparms.hdr.seq_no); 3534 /*copy entries to user buffer*/ 3535 if (cmd->data.setadapterparms.hdr.seq_no == 1) { 3536 memcpy(qinfo->udata + qinfo->udata_offset, 3537 (char *)snmp, 3538 data_len + offsetof(struct qeth_snmp_cmd, data)); 3539 qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data); 3540 } else { 3541 memcpy(qinfo->udata + qinfo->udata_offset, 3542 (char *)&snmp->request, data_len); 3543 } 3544 qinfo->udata_offset += data_len; 3545 /* check if all replies received ... */ 3546 QETH_DBF_TEXT_(TRACE, 4, "srtot%i", 3547 cmd->data.setadapterparms.hdr.used_total); 3548 QETH_DBF_TEXT_(TRACE, 4, "srseq%i", 3549 cmd->data.setadapterparms.hdr.seq_no); 3550 if (cmd->data.setadapterparms.hdr.seq_no < 3551 cmd->data.setadapterparms.hdr.used_total) 3552 return 1; 3553 return 0; 3554 } 3555 3556 int qeth_snmp_command(struct qeth_card *card, char __user *udata) 3557 { 3558 struct qeth_cmd_buffer *iob; 3559 struct qeth_ipa_cmd *cmd; 3560 struct qeth_snmp_ureq *ureq; 3561 int req_len; 3562 struct qeth_arp_query_info qinfo = {0, }; 3563 int rc = 0; 3564 3565 QETH_DBF_TEXT(TRACE, 3, "snmpcmd"); 3566 3567 if (card->info.guestlan) 3568 return -EOPNOTSUPP; 3569 3570 if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) && 3571 (!card->options.layer2)) { 3572 return -EOPNOTSUPP; 3573 } 3574 /* skip 4 bytes (data_len struct member) to get req_len */ 3575 if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int))) 3576 return -EFAULT; 3577 ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL); 3578 if (!ureq) { 3579 QETH_DBF_TEXT(TRACE, 2, "snmpnome"); 3580 return -ENOMEM; 3581 } 3582 if (copy_from_user(ureq, udata, 3583 req_len + sizeof(struct qeth_snmp_ureq_hdr))) { 3584 kfree(ureq); 3585 return -EFAULT; 3586 } 3587 qinfo.udata_len = ureq->hdr.data_len; 3588 qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL); 3589 if (!qinfo.udata) { 3590 kfree(ureq); 3591 return -ENOMEM; 3592 } 3593 qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr); 3594 3595 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL, 3596 QETH_SNMP_SETADP_CMDLENGTH + req_len); 3597 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE); 3598 memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len); 3599 rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len, 3600 qeth_snmp_command_cb, (void *)&qinfo); 3601 if (rc) 3602 QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n", 3603 QETH_CARD_IFNAME(card), rc); 3604 else { 3605 if (copy_to_user(udata, qinfo.udata, qinfo.udata_len)) 3606 rc = -EFAULT; 3607 } 3608 3609 kfree(ureq); 3610 kfree(qinfo.udata); 3611 return rc; 3612 } 3613 EXPORT_SYMBOL_GPL(qeth_snmp_command); 3614 3615 static inline int qeth_get_qdio_q_format(struct qeth_card *card) 3616 { 3617 switch (card->info.type) { 3618 case QETH_CARD_TYPE_IQD: 3619 return 2; 3620 default: 3621 return 0; 3622 } 3623 } 3624 3625 static int qeth_qdio_establish(struct qeth_card *card) 3626 { 3627 struct qdio_initialize init_data; 3628 char *qib_param_field; 3629 struct qdio_buffer **in_sbal_ptrs; 3630 struct qdio_buffer **out_sbal_ptrs; 3631 int i, j, k; 3632 int rc = 0; 3633 3634 QETH_DBF_TEXT(SETUP, 2, "qdioest"); 3635 3636 qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char), 3637 GFP_KERNEL); 3638 if (!qib_param_field) 3639 return -ENOMEM; 3640 3641 qeth_create_qib_param_field(card, qib_param_field); 3642 qeth_create_qib_param_field_blkt(card, qib_param_field); 3643 3644 in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *), 3645 GFP_KERNEL); 3646 if (!in_sbal_ptrs) { 3647 kfree(qib_param_field); 3648 return -ENOMEM; 3649 } 3650 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) 3651 in_sbal_ptrs[i] = (struct qdio_buffer *) 3652 virt_to_phys(card->qdio.in_q->bufs[i].buffer); 3653 3654 out_sbal_ptrs = 3655 kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q * 3656 sizeof(void *), GFP_KERNEL); 3657 if (!out_sbal_ptrs) { 3658 kfree(in_sbal_ptrs); 3659 kfree(qib_param_field); 3660 return -ENOMEM; 3661 } 3662 for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i) 3663 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) { 3664 out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys( 3665 card->qdio.out_qs[i]->bufs[j].buffer); 3666 } 3667 3668 memset(&init_data, 0, sizeof(struct qdio_initialize)); 3669 init_data.cdev = CARD_DDEV(card); 3670 init_data.q_format = qeth_get_qdio_q_format(card); 3671 init_data.qib_param_field_format = 0; 3672 init_data.qib_param_field = qib_param_field; 3673 init_data.no_input_qs = 1; 3674 init_data.no_output_qs = card->qdio.no_out_queues; 3675 init_data.input_handler = card->discipline.input_handler; 3676 init_data.output_handler = card->discipline.output_handler; 3677 init_data.int_parm = (unsigned long) card; 3678 init_data.flags = QDIO_INBOUND_0COPY_SBALS | 3679 QDIO_OUTBOUND_0COPY_SBALS | 3680 QDIO_USE_OUTBOUND_PCIS; 3681 init_data.input_sbal_addr_array = (void **) in_sbal_ptrs; 3682 init_data.output_sbal_addr_array = (void **) out_sbal_ptrs; 3683 3684 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED, 3685 QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) { 3686 rc = qdio_initialize(&init_data); 3687 if (rc) 3688 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED); 3689 } 3690 kfree(out_sbal_ptrs); 3691 kfree(in_sbal_ptrs); 3692 kfree(qib_param_field); 3693 return rc; 3694 } 3695 3696 static void qeth_core_free_card(struct qeth_card *card) 3697 { 3698 3699 QETH_DBF_TEXT(SETUP, 2, "freecrd"); 3700 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *)); 3701 qeth_clean_channel(&card->read); 3702 qeth_clean_channel(&card->write); 3703 if (card->dev) 3704 free_netdev(card->dev); 3705 kfree(card->ip_tbd_list); 3706 qeth_free_qdio_buffers(card); 3707 unregister_service_level(&card->qeth_service_level); 3708 kfree(card); 3709 } 3710 3711 static struct ccw_device_id qeth_ids[] = { 3712 {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE}, 3713 {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD}, 3714 {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN}, 3715 {}, 3716 }; 3717 MODULE_DEVICE_TABLE(ccw, qeth_ids); 3718 3719 static struct ccw_driver qeth_ccw_driver = { 3720 .name = "qeth", 3721 .ids = qeth_ids, 3722 .probe = ccwgroup_probe_ccwdev, 3723 .remove = ccwgroup_remove_ccwdev, 3724 }; 3725 3726 static int qeth_core_driver_group(const char *buf, struct device *root_dev, 3727 unsigned long driver_id) 3728 { 3729 return ccwgroup_create_from_string(root_dev, driver_id, 3730 &qeth_ccw_driver, 3, buf); 3731 } 3732 3733 int qeth_core_hardsetup_card(struct qeth_card *card) 3734 { 3735 struct qdio_ssqd_desc *ssqd; 3736 int retries = 3; 3737 int mpno = 0; 3738 int rc; 3739 3740 QETH_DBF_TEXT(SETUP, 2, "hrdsetup"); 3741 atomic_set(&card->force_alloc_skb, 0); 3742 retry: 3743 if (retries < 3) { 3744 QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n", 3745 dev_name(&card->gdev->dev)); 3746 ccw_device_set_offline(CARD_DDEV(card)); 3747 ccw_device_set_offline(CARD_WDEV(card)); 3748 ccw_device_set_offline(CARD_RDEV(card)); 3749 ccw_device_set_online(CARD_RDEV(card)); 3750 ccw_device_set_online(CARD_WDEV(card)); 3751 ccw_device_set_online(CARD_DDEV(card)); 3752 } 3753 rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD); 3754 if (rc == -ERESTARTSYS) { 3755 QETH_DBF_TEXT(SETUP, 2, "break1"); 3756 return rc; 3757 } else if (rc) { 3758 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc); 3759 if (--retries < 0) 3760 goto out; 3761 else 3762 goto retry; 3763 } 3764 3765 rc = qeth_get_unitaddr(card); 3766 if (rc) { 3767 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc); 3768 return rc; 3769 } 3770 3771 ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL); 3772 if (!ssqd) { 3773 rc = -ENOMEM; 3774 goto out; 3775 } 3776 rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd); 3777 if (rc == 0) 3778 mpno = ssqd->pcnt; 3779 kfree(ssqd); 3780 3781 if (mpno) 3782 mpno = min(mpno - 1, QETH_MAX_PORTNO); 3783 if (card->info.portno > mpno) { 3784 QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d" 3785 "\n.", CARD_BUS_ID(card), card->info.portno); 3786 rc = -ENODEV; 3787 goto out; 3788 } 3789 qeth_init_tokens(card); 3790 qeth_init_func_level(card); 3791 rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb); 3792 if (rc == -ERESTARTSYS) { 3793 QETH_DBF_TEXT(SETUP, 2, "break2"); 3794 return rc; 3795 } else if (rc) { 3796 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc); 3797 if (--retries < 0) 3798 goto out; 3799 else 3800 goto retry; 3801 } 3802 rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb); 3803 if (rc == -ERESTARTSYS) { 3804 QETH_DBF_TEXT(SETUP, 2, "break3"); 3805 return rc; 3806 } else if (rc) { 3807 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc); 3808 if (--retries < 0) 3809 goto out; 3810 else 3811 goto retry; 3812 } 3813 rc = qeth_mpc_initialize(card); 3814 if (rc) { 3815 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc); 3816 goto out; 3817 } 3818 return 0; 3819 out: 3820 dev_warn(&card->gdev->dev, "The qeth device driver failed to recover " 3821 "an error on the device\n"); 3822 QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n", 3823 dev_name(&card->gdev->dev), rc); 3824 return rc; 3825 } 3826 EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card); 3827 3828 static inline int qeth_create_skb_frag(struct qdio_buffer_element *element, 3829 struct sk_buff **pskb, int offset, int *pfrag, int data_len) 3830 { 3831 struct page *page = virt_to_page(element->addr); 3832 if (*pskb == NULL) { 3833 /* the upper protocol layers assume that there is data in the 3834 * skb itself. Copy a small amount (64 bytes) to make them 3835 * happy. */ 3836 *pskb = dev_alloc_skb(64 + ETH_HLEN); 3837 if (!(*pskb)) 3838 return -ENOMEM; 3839 skb_reserve(*pskb, ETH_HLEN); 3840 if (data_len <= 64) { 3841 memcpy(skb_put(*pskb, data_len), element->addr + offset, 3842 data_len); 3843 } else { 3844 get_page(page); 3845 memcpy(skb_put(*pskb, 64), element->addr + offset, 64); 3846 skb_fill_page_desc(*pskb, *pfrag, page, offset + 64, 3847 data_len - 64); 3848 (*pskb)->data_len += data_len - 64; 3849 (*pskb)->len += data_len - 64; 3850 (*pskb)->truesize += data_len - 64; 3851 (*pfrag)++; 3852 } 3853 } else { 3854 get_page(page); 3855 skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len); 3856 (*pskb)->data_len += data_len; 3857 (*pskb)->len += data_len; 3858 (*pskb)->truesize += data_len; 3859 (*pfrag)++; 3860 } 3861 return 0; 3862 } 3863 3864 struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card, 3865 struct qdio_buffer *buffer, 3866 struct qdio_buffer_element **__element, int *__offset, 3867 struct qeth_hdr **hdr) 3868 { 3869 struct qdio_buffer_element *element = *__element; 3870 int offset = *__offset; 3871 struct sk_buff *skb = NULL; 3872 int skb_len; 3873 void *data_ptr; 3874 int data_len; 3875 int headroom = 0; 3876 int use_rx_sg = 0; 3877 int frag = 0; 3878 3879 /* qeth_hdr must not cross element boundaries */ 3880 if (element->length < offset + sizeof(struct qeth_hdr)) { 3881 if (qeth_is_last_sbale(element)) 3882 return NULL; 3883 element++; 3884 offset = 0; 3885 if (element->length < sizeof(struct qeth_hdr)) 3886 return NULL; 3887 } 3888 *hdr = element->addr + offset; 3889 3890 offset += sizeof(struct qeth_hdr); 3891 if (card->options.layer2) { 3892 if (card->info.type == QETH_CARD_TYPE_OSN) { 3893 skb_len = (*hdr)->hdr.osn.pdu_length; 3894 headroom = sizeof(struct qeth_hdr); 3895 } else { 3896 skb_len = (*hdr)->hdr.l2.pkt_length; 3897 } 3898 } else { 3899 skb_len = (*hdr)->hdr.l3.length; 3900 if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) || 3901 (card->info.link_type == QETH_LINK_TYPE_HSTR)) 3902 headroom = TR_HLEN; 3903 else 3904 headroom = ETH_HLEN; 3905 } 3906 3907 if (!skb_len) 3908 return NULL; 3909 3910 if ((skb_len >= card->options.rx_sg_cb) && 3911 (!(card->info.type == QETH_CARD_TYPE_OSN)) && 3912 (!atomic_read(&card->force_alloc_skb))) { 3913 use_rx_sg = 1; 3914 } else { 3915 skb = dev_alloc_skb(skb_len + headroom); 3916 if (!skb) 3917 goto no_mem; 3918 if (headroom) 3919 skb_reserve(skb, headroom); 3920 } 3921 3922 data_ptr = element->addr + offset; 3923 while (skb_len) { 3924 data_len = min(skb_len, (int)(element->length - offset)); 3925 if (data_len) { 3926 if (use_rx_sg) { 3927 if (qeth_create_skb_frag(element, &skb, offset, 3928 &frag, data_len)) 3929 goto no_mem; 3930 } else { 3931 memcpy(skb_put(skb, data_len), data_ptr, 3932 data_len); 3933 } 3934 } 3935 skb_len -= data_len; 3936 if (skb_len) { 3937 if (qeth_is_last_sbale(element)) { 3938 QETH_DBF_TEXT(TRACE, 4, "unexeob"); 3939 QETH_DBF_TEXT_(TRACE, 4, "%s", 3940 CARD_BUS_ID(card)); 3941 QETH_DBF_TEXT(QERR, 2, "unexeob"); 3942 QETH_DBF_TEXT_(QERR, 2, "%s", 3943 CARD_BUS_ID(card)); 3944 QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer)); 3945 dev_kfree_skb_any(skb); 3946 card->stats.rx_errors++; 3947 return NULL; 3948 } 3949 element++; 3950 offset = 0; 3951 data_ptr = element->addr; 3952 } else { 3953 offset += data_len; 3954 } 3955 } 3956 *__element = element; 3957 *__offset = offset; 3958 if (use_rx_sg && card->options.performance_stats) { 3959 card->perf_stats.sg_skbs_rx++; 3960 card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags; 3961 } 3962 return skb; 3963 no_mem: 3964 if (net_ratelimit()) { 3965 QETH_DBF_TEXT(TRACE, 2, "noskbmem"); 3966 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card)); 3967 } 3968 card->stats.rx_dropped++; 3969 return NULL; 3970 } 3971 EXPORT_SYMBOL_GPL(qeth_core_get_next_skb); 3972 3973 static void qeth_unregister_dbf_views(void) 3974 { 3975 int x; 3976 for (x = 0; x < QETH_DBF_INFOS; x++) { 3977 debug_unregister(qeth_dbf[x].id); 3978 qeth_dbf[x].id = NULL; 3979 } 3980 } 3981 3982 void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...) 3983 { 3984 char dbf_txt_buf[32]; 3985 va_list args; 3986 3987 if (level > (qeth_dbf[dbf_nix].id)->level) 3988 return; 3989 va_start(args, fmt); 3990 vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args); 3991 va_end(args); 3992 debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf); 3993 } 3994 EXPORT_SYMBOL_GPL(qeth_dbf_longtext); 3995 3996 static int qeth_register_dbf_views(void) 3997 { 3998 int ret; 3999 int x; 4000 4001 for (x = 0; x < QETH_DBF_INFOS; x++) { 4002 /* register the areas */ 4003 qeth_dbf[x].id = debug_register(qeth_dbf[x].name, 4004 qeth_dbf[x].pages, 4005 qeth_dbf[x].areas, 4006 qeth_dbf[x].len); 4007 if (qeth_dbf[x].id == NULL) { 4008 qeth_unregister_dbf_views(); 4009 return -ENOMEM; 4010 } 4011 4012 /* register a view */ 4013 ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view); 4014 if (ret) { 4015 qeth_unregister_dbf_views(); 4016 return ret; 4017 } 4018 4019 /* set a passing level */ 4020 debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level); 4021 } 4022 4023 return 0; 4024 } 4025 4026 int qeth_core_load_discipline(struct qeth_card *card, 4027 enum qeth_discipline_id discipline) 4028 { 4029 int rc = 0; 4030 switch (discipline) { 4031 case QETH_DISCIPLINE_LAYER3: 4032 card->discipline.ccwgdriver = try_then_request_module( 4033 symbol_get(qeth_l3_ccwgroup_driver), 4034 "qeth_l3"); 4035 break; 4036 case QETH_DISCIPLINE_LAYER2: 4037 card->discipline.ccwgdriver = try_then_request_module( 4038 symbol_get(qeth_l2_ccwgroup_driver), 4039 "qeth_l2"); 4040 break; 4041 } 4042 if (!card->discipline.ccwgdriver) { 4043 dev_err(&card->gdev->dev, "There is no kernel module to " 4044 "support discipline %d\n", discipline); 4045 rc = -EINVAL; 4046 } 4047 return rc; 4048 } 4049 4050 void qeth_core_free_discipline(struct qeth_card *card) 4051 { 4052 if (card->options.layer2) 4053 symbol_put(qeth_l2_ccwgroup_driver); 4054 else 4055 symbol_put(qeth_l3_ccwgroup_driver); 4056 card->discipline.ccwgdriver = NULL; 4057 } 4058 4059 static int qeth_core_probe_device(struct ccwgroup_device *gdev) 4060 { 4061 struct qeth_card *card; 4062 struct device *dev; 4063 int rc; 4064 unsigned long flags; 4065 4066 QETH_DBF_TEXT(SETUP, 2, "probedev"); 4067 4068 dev = &gdev->dev; 4069 if (!get_device(dev)) 4070 return -ENODEV; 4071 4072 QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev)); 4073 4074 card = qeth_alloc_card(); 4075 if (!card) { 4076 QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM); 4077 rc = -ENOMEM; 4078 goto err_dev; 4079 } 4080 card->read.ccwdev = gdev->cdev[0]; 4081 card->write.ccwdev = gdev->cdev[1]; 4082 card->data.ccwdev = gdev->cdev[2]; 4083 dev_set_drvdata(&gdev->dev, card); 4084 card->gdev = gdev; 4085 gdev->cdev[0]->handler = qeth_irq; 4086 gdev->cdev[1]->handler = qeth_irq; 4087 gdev->cdev[2]->handler = qeth_irq; 4088 4089 rc = qeth_determine_card_type(card); 4090 if (rc) { 4091 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc); 4092 goto err_card; 4093 } 4094 rc = qeth_setup_card(card); 4095 if (rc) { 4096 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc); 4097 goto err_card; 4098 } 4099 4100 if (card->info.type == QETH_CARD_TYPE_OSN) { 4101 rc = qeth_core_create_osn_attributes(dev); 4102 if (rc) 4103 goto err_card; 4104 rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2); 4105 if (rc) { 4106 qeth_core_remove_osn_attributes(dev); 4107 goto err_card; 4108 } 4109 rc = card->discipline.ccwgdriver->probe(card->gdev); 4110 if (rc) { 4111 qeth_core_free_discipline(card); 4112 qeth_core_remove_osn_attributes(dev); 4113 goto err_card; 4114 } 4115 } else { 4116 rc = qeth_core_create_device_attributes(dev); 4117 if (rc) 4118 goto err_card; 4119 } 4120 4121 write_lock_irqsave(&qeth_core_card_list.rwlock, flags); 4122 list_add_tail(&card->list, &qeth_core_card_list.list); 4123 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags); 4124 return 0; 4125 4126 err_card: 4127 qeth_core_free_card(card); 4128 err_dev: 4129 put_device(dev); 4130 return rc; 4131 } 4132 4133 static void qeth_core_remove_device(struct ccwgroup_device *gdev) 4134 { 4135 unsigned long flags; 4136 struct qeth_card *card = dev_get_drvdata(&gdev->dev); 4137 4138 QETH_DBF_TEXT(SETUP, 2, "removedv"); 4139 if (card->discipline.ccwgdriver) { 4140 card->discipline.ccwgdriver->remove(gdev); 4141 qeth_core_free_discipline(card); 4142 } 4143 4144 if (card->info.type == QETH_CARD_TYPE_OSN) { 4145 qeth_core_remove_osn_attributes(&gdev->dev); 4146 } else { 4147 qeth_core_remove_device_attributes(&gdev->dev); 4148 } 4149 write_lock_irqsave(&qeth_core_card_list.rwlock, flags); 4150 list_del(&card->list); 4151 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags); 4152 qeth_core_free_card(card); 4153 dev_set_drvdata(&gdev->dev, NULL); 4154 put_device(&gdev->dev); 4155 return; 4156 } 4157 4158 static int qeth_core_set_online(struct ccwgroup_device *gdev) 4159 { 4160 struct qeth_card *card = dev_get_drvdata(&gdev->dev); 4161 int rc = 0; 4162 int def_discipline; 4163 4164 if (!card->discipline.ccwgdriver) { 4165 if (card->info.type == QETH_CARD_TYPE_IQD) 4166 def_discipline = QETH_DISCIPLINE_LAYER3; 4167 else 4168 def_discipline = QETH_DISCIPLINE_LAYER2; 4169 rc = qeth_core_load_discipline(card, def_discipline); 4170 if (rc) 4171 goto err; 4172 rc = card->discipline.ccwgdriver->probe(card->gdev); 4173 if (rc) 4174 goto err; 4175 } 4176 rc = card->discipline.ccwgdriver->set_online(gdev); 4177 err: 4178 return rc; 4179 } 4180 4181 static int qeth_core_set_offline(struct ccwgroup_device *gdev) 4182 { 4183 struct qeth_card *card = dev_get_drvdata(&gdev->dev); 4184 return card->discipline.ccwgdriver->set_offline(gdev); 4185 } 4186 4187 static void qeth_core_shutdown(struct ccwgroup_device *gdev) 4188 { 4189 struct qeth_card *card = dev_get_drvdata(&gdev->dev); 4190 if (card->discipline.ccwgdriver && 4191 card->discipline.ccwgdriver->shutdown) 4192 card->discipline.ccwgdriver->shutdown(gdev); 4193 } 4194 4195 static struct ccwgroup_driver qeth_core_ccwgroup_driver = { 4196 .owner = THIS_MODULE, 4197 .name = "qeth", 4198 .driver_id = 0xD8C5E3C8, 4199 .probe = qeth_core_probe_device, 4200 .remove = qeth_core_remove_device, 4201 .set_online = qeth_core_set_online, 4202 .set_offline = qeth_core_set_offline, 4203 .shutdown = qeth_core_shutdown, 4204 }; 4205 4206 static ssize_t 4207 qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf, 4208 size_t count) 4209 { 4210 int err; 4211 err = qeth_core_driver_group(buf, qeth_core_root_dev, 4212 qeth_core_ccwgroup_driver.driver_id); 4213 if (err) 4214 return err; 4215 else 4216 return count; 4217 } 4218 4219 static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store); 4220 4221 static struct { 4222 const char str[ETH_GSTRING_LEN]; 4223 } qeth_ethtool_stats_keys[] = { 4224 /* 0 */{"rx skbs"}, 4225 {"rx buffers"}, 4226 {"tx skbs"}, 4227 {"tx buffers"}, 4228 {"tx skbs no packing"}, 4229 {"tx buffers no packing"}, 4230 {"tx skbs packing"}, 4231 {"tx buffers packing"}, 4232 {"tx sg skbs"}, 4233 {"tx sg frags"}, 4234 /* 10 */{"rx sg skbs"}, 4235 {"rx sg frags"}, 4236 {"rx sg page allocs"}, 4237 {"tx large kbytes"}, 4238 {"tx large count"}, 4239 {"tx pk state ch n->p"}, 4240 {"tx pk state ch p->n"}, 4241 {"tx pk watermark low"}, 4242 {"tx pk watermark high"}, 4243 {"queue 0 buffer usage"}, 4244 /* 20 */{"queue 1 buffer usage"}, 4245 {"queue 2 buffer usage"}, 4246 {"queue 3 buffer usage"}, 4247 {"rx handler time"}, 4248 {"rx handler count"}, 4249 {"rx do_QDIO time"}, 4250 {"rx do_QDIO count"}, 4251 {"tx handler time"}, 4252 {"tx handler count"}, 4253 {"tx time"}, 4254 /* 30 */{"tx count"}, 4255 {"tx do_QDIO time"}, 4256 {"tx do_QDIO count"}, 4257 {"tx csum"}, 4258 }; 4259 4260 int qeth_core_get_stats_count(struct net_device *dev) 4261 { 4262 return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN); 4263 } 4264 EXPORT_SYMBOL_GPL(qeth_core_get_stats_count); 4265 4266 void qeth_core_get_ethtool_stats(struct net_device *dev, 4267 struct ethtool_stats *stats, u64 *data) 4268 { 4269 struct qeth_card *card = dev->ml_priv; 4270 data[0] = card->stats.rx_packets - 4271 card->perf_stats.initial_rx_packets; 4272 data[1] = card->perf_stats.bufs_rec; 4273 data[2] = card->stats.tx_packets - 4274 card->perf_stats.initial_tx_packets; 4275 data[3] = card->perf_stats.bufs_sent; 4276 data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets 4277 - card->perf_stats.skbs_sent_pack; 4278 data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack; 4279 data[6] = card->perf_stats.skbs_sent_pack; 4280 data[7] = card->perf_stats.bufs_sent_pack; 4281 data[8] = card->perf_stats.sg_skbs_sent; 4282 data[9] = card->perf_stats.sg_frags_sent; 4283 data[10] = card->perf_stats.sg_skbs_rx; 4284 data[11] = card->perf_stats.sg_frags_rx; 4285 data[12] = card->perf_stats.sg_alloc_page_rx; 4286 data[13] = (card->perf_stats.large_send_bytes >> 10); 4287 data[14] = card->perf_stats.large_send_cnt; 4288 data[15] = card->perf_stats.sc_dp_p; 4289 data[16] = card->perf_stats.sc_p_dp; 4290 data[17] = QETH_LOW_WATERMARK_PACK; 4291 data[18] = QETH_HIGH_WATERMARK_PACK; 4292 data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers); 4293 data[20] = (card->qdio.no_out_queues > 1) ? 4294 atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0; 4295 data[21] = (card->qdio.no_out_queues > 2) ? 4296 atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0; 4297 data[22] = (card->qdio.no_out_queues > 3) ? 4298 atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0; 4299 data[23] = card->perf_stats.inbound_time; 4300 data[24] = card->perf_stats.inbound_cnt; 4301 data[25] = card->perf_stats.inbound_do_qdio_time; 4302 data[26] = card->perf_stats.inbound_do_qdio_cnt; 4303 data[27] = card->perf_stats.outbound_handler_time; 4304 data[28] = card->perf_stats.outbound_handler_cnt; 4305 data[29] = card->perf_stats.outbound_time; 4306 data[30] = card->perf_stats.outbound_cnt; 4307 data[31] = card->perf_stats.outbound_do_qdio_time; 4308 data[32] = card->perf_stats.outbound_do_qdio_cnt; 4309 data[33] = card->perf_stats.tx_csum; 4310 } 4311 EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats); 4312 4313 void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4314 { 4315 switch (stringset) { 4316 case ETH_SS_STATS: 4317 memcpy(data, &qeth_ethtool_stats_keys, 4318 sizeof(qeth_ethtool_stats_keys)); 4319 break; 4320 default: 4321 WARN_ON(1); 4322 break; 4323 } 4324 } 4325 EXPORT_SYMBOL_GPL(qeth_core_get_strings); 4326 4327 void qeth_core_get_drvinfo(struct net_device *dev, 4328 struct ethtool_drvinfo *info) 4329 { 4330 struct qeth_card *card = dev->ml_priv; 4331 if (card->options.layer2) 4332 strcpy(info->driver, "qeth_l2"); 4333 else 4334 strcpy(info->driver, "qeth_l3"); 4335 4336 strcpy(info->version, "1.0"); 4337 strcpy(info->fw_version, card->info.mcl_level); 4338 sprintf(info->bus_info, "%s/%s/%s", 4339 CARD_RDEV_ID(card), 4340 CARD_WDEV_ID(card), 4341 CARD_DDEV_ID(card)); 4342 } 4343 EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo); 4344 4345 int qeth_core_ethtool_get_settings(struct net_device *netdev, 4346 struct ethtool_cmd *ecmd) 4347 { 4348 struct qeth_card *card = netdev->ml_priv; 4349 enum qeth_link_types link_type; 4350 4351 if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan)) 4352 link_type = QETH_LINK_TYPE_10GBIT_ETH; 4353 else 4354 link_type = card->info.link_type; 4355 4356 ecmd->transceiver = XCVR_INTERNAL; 4357 ecmd->supported = SUPPORTED_Autoneg; 4358 ecmd->advertising = ADVERTISED_Autoneg; 4359 ecmd->duplex = DUPLEX_FULL; 4360 ecmd->autoneg = AUTONEG_ENABLE; 4361 4362 switch (link_type) { 4363 case QETH_LINK_TYPE_FAST_ETH: 4364 case QETH_LINK_TYPE_LANE_ETH100: 4365 ecmd->supported |= SUPPORTED_10baseT_Half | 4366 SUPPORTED_10baseT_Full | 4367 SUPPORTED_100baseT_Half | 4368 SUPPORTED_100baseT_Full | 4369 SUPPORTED_TP; 4370 ecmd->advertising |= ADVERTISED_10baseT_Half | 4371 ADVERTISED_10baseT_Full | 4372 ADVERTISED_100baseT_Half | 4373 ADVERTISED_100baseT_Full | 4374 ADVERTISED_TP; 4375 ecmd->speed = SPEED_100; 4376 ecmd->port = PORT_TP; 4377 break; 4378 4379 case QETH_LINK_TYPE_GBIT_ETH: 4380 case QETH_LINK_TYPE_LANE_ETH1000: 4381 ecmd->supported |= SUPPORTED_10baseT_Half | 4382 SUPPORTED_10baseT_Full | 4383 SUPPORTED_100baseT_Half | 4384 SUPPORTED_100baseT_Full | 4385 SUPPORTED_1000baseT_Half | 4386 SUPPORTED_1000baseT_Full | 4387 SUPPORTED_FIBRE; 4388 ecmd->advertising |= ADVERTISED_10baseT_Half | 4389 ADVERTISED_10baseT_Full | 4390 ADVERTISED_100baseT_Half | 4391 ADVERTISED_100baseT_Full | 4392 ADVERTISED_1000baseT_Half | 4393 ADVERTISED_1000baseT_Full | 4394 ADVERTISED_FIBRE; 4395 ecmd->speed = SPEED_1000; 4396 ecmd->port = PORT_FIBRE; 4397 break; 4398 4399 case QETH_LINK_TYPE_10GBIT_ETH: 4400 ecmd->supported |= SUPPORTED_10baseT_Half | 4401 SUPPORTED_10baseT_Full | 4402 SUPPORTED_100baseT_Half | 4403 SUPPORTED_100baseT_Full | 4404 SUPPORTED_1000baseT_Half | 4405 SUPPORTED_1000baseT_Full | 4406 SUPPORTED_10000baseT_Full | 4407 SUPPORTED_FIBRE; 4408 ecmd->advertising |= ADVERTISED_10baseT_Half | 4409 ADVERTISED_10baseT_Full | 4410 ADVERTISED_100baseT_Half | 4411 ADVERTISED_100baseT_Full | 4412 ADVERTISED_1000baseT_Half | 4413 ADVERTISED_1000baseT_Full | 4414 ADVERTISED_10000baseT_Full | 4415 ADVERTISED_FIBRE; 4416 ecmd->speed = SPEED_10000; 4417 ecmd->port = PORT_FIBRE; 4418 break; 4419 4420 default: 4421 ecmd->supported |= SUPPORTED_10baseT_Half | 4422 SUPPORTED_10baseT_Full | 4423 SUPPORTED_TP; 4424 ecmd->advertising |= ADVERTISED_10baseT_Half | 4425 ADVERTISED_10baseT_Full | 4426 ADVERTISED_TP; 4427 ecmd->speed = SPEED_10; 4428 ecmd->port = PORT_TP; 4429 } 4430 4431 return 0; 4432 } 4433 EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings); 4434 4435 static int __init qeth_core_init(void) 4436 { 4437 int rc; 4438 4439 pr_info("loading core functions\n"); 4440 INIT_LIST_HEAD(&qeth_core_card_list.list); 4441 rwlock_init(&qeth_core_card_list.rwlock); 4442 4443 rc = qeth_register_dbf_views(); 4444 if (rc) 4445 goto out_err; 4446 rc = ccw_driver_register(&qeth_ccw_driver); 4447 if (rc) 4448 goto ccw_err; 4449 rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver); 4450 if (rc) 4451 goto ccwgroup_err; 4452 rc = driver_create_file(&qeth_core_ccwgroup_driver.driver, 4453 &driver_attr_group); 4454 if (rc) 4455 goto driver_err; 4456 qeth_core_root_dev = root_device_register("qeth"); 4457 rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0; 4458 if (rc) 4459 goto register_err; 4460 4461 qeth_core_header_cache = kmem_cache_create("qeth_hdr", 4462 sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL); 4463 if (!qeth_core_header_cache) { 4464 rc = -ENOMEM; 4465 goto slab_err; 4466 } 4467 4468 return 0; 4469 slab_err: 4470 root_device_unregister(qeth_core_root_dev); 4471 register_err: 4472 driver_remove_file(&qeth_core_ccwgroup_driver.driver, 4473 &driver_attr_group); 4474 driver_err: 4475 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver); 4476 ccwgroup_err: 4477 ccw_driver_unregister(&qeth_ccw_driver); 4478 ccw_err: 4479 QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc); 4480 qeth_unregister_dbf_views(); 4481 out_err: 4482 pr_err("Initializing the qeth device driver failed\n"); 4483 return rc; 4484 } 4485 4486 static void __exit qeth_core_exit(void) 4487 { 4488 root_device_unregister(qeth_core_root_dev); 4489 driver_remove_file(&qeth_core_ccwgroup_driver.driver, 4490 &driver_attr_group); 4491 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver); 4492 ccw_driver_unregister(&qeth_ccw_driver); 4493 kmem_cache_destroy(qeth_core_header_cache); 4494 qeth_unregister_dbf_views(); 4495 pr_info("core functions removed\n"); 4496 } 4497 4498 module_init(qeth_core_init); 4499 module_exit(qeth_core_exit); 4500 MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>"); 4501 MODULE_DESCRIPTION("qeth core functions"); 4502 MODULE_LICENSE("GPL"); 4503