1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright IBM Corp. 2000, 2009 4 * Author(s): Utz Bacher <utz.bacher@de.ibm.com> 5 * Jan Glauber <jang@linux.vnet.ibm.com> 6 */ 7 #ifndef _CIO_QDIO_H 8 #define _CIO_QDIO_H 9 10 #include <asm/page.h> 11 #include <asm/schid.h> 12 #include <asm/debug.h> 13 #include "chsc.h" 14 15 #define QDIO_BUSY_BIT_PATIENCE (100 << 12) /* 100 microseconds */ 16 #define QDIO_BUSY_BIT_RETRY_DELAY 10 /* 10 milliseconds */ 17 #define QDIO_BUSY_BIT_RETRIES 1000 /* = 10s retry time */ 18 19 enum qdio_irq_states { 20 QDIO_IRQ_STATE_INACTIVE, 21 QDIO_IRQ_STATE_ESTABLISHED, 22 QDIO_IRQ_STATE_ACTIVE, 23 QDIO_IRQ_STATE_STOPPED, 24 QDIO_IRQ_STATE_CLEANUP, 25 QDIO_IRQ_STATE_ERR, 26 NR_QDIO_IRQ_STATES, 27 }; 28 29 /* used as intparm in do_IO */ 30 #define QDIO_DOING_ESTABLISH 1 31 #define QDIO_DOING_ACTIVATE 2 32 #define QDIO_DOING_CLEANUP 3 33 34 #define SLSB_STATE_NOT_INIT 0x0 35 #define SLSB_STATE_EMPTY 0x1 36 #define SLSB_STATE_PRIMED 0x2 37 #define SLSB_STATE_PENDING 0x3 38 #define SLSB_STATE_HALTED 0xe 39 #define SLSB_STATE_ERROR 0xf 40 #define SLSB_TYPE_INPUT 0x0 41 #define SLSB_TYPE_OUTPUT 0x20 42 #define SLSB_OWNER_PROG 0x80 43 #define SLSB_OWNER_CU 0x40 44 45 #define SLSB_P_INPUT_NOT_INIT \ 46 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT) /* 0x80 */ 47 #define SLSB_P_INPUT_ACK \ 48 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x81 */ 49 #define SLSB_CU_INPUT_EMPTY \ 50 (SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x41 */ 51 #define SLSB_P_INPUT_PRIMED \ 52 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED) /* 0x82 */ 53 #define SLSB_P_INPUT_HALTED \ 54 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED) /* 0x8e */ 55 #define SLSB_P_INPUT_ERROR \ 56 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR) /* 0x8f */ 57 #define SLSB_P_OUTPUT_NOT_INIT \ 58 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */ 59 #define SLSB_P_OUTPUT_EMPTY \ 60 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY) /* 0xa1 */ 61 #define SLSB_P_OUTPUT_PENDING \ 62 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_PENDING) /* 0xa3 */ 63 #define SLSB_CU_OUTPUT_PRIMED \ 64 (SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED) /* 0x62 */ 65 #define SLSB_P_OUTPUT_HALTED \ 66 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED) /* 0xae */ 67 #define SLSB_P_OUTPUT_ERROR \ 68 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR) /* 0xaf */ 69 70 #define SLSB_ERROR_DURING_LOOKUP 0xff 71 72 /* additional CIWs returned by extended Sense-ID */ 73 #define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */ 74 #define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */ 75 76 /* flags for st qdio sch data */ 77 #define CHSC_FLAG_QDIO_CAPABILITY 0x80 78 #define CHSC_FLAG_VALIDITY 0x40 79 80 /* SIGA flags */ 81 #define QDIO_SIGA_WRITE 0x00 82 #define QDIO_SIGA_READ 0x01 83 #define QDIO_SIGA_SYNC 0x02 84 #define QDIO_SIGA_WRITEM 0x03 85 #define QDIO_SIGA_WRITEQ 0x04 86 #define QDIO_SIGA_QEBSM_FLAG 0x80 87 88 static inline int do_sqbs(u64 token, unsigned char state, int queue, 89 int *start, int *count) 90 { 91 unsigned long _queuestart = ((unsigned long)queue << 32) | *start; 92 unsigned long _ccq = *count; 93 94 asm volatile( 95 " lgr 1,%[token]\n" 96 " .insn rsy,0xeb000000008a,%[qs],%[ccq],0(%[state])" 97 : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart) 98 : [state] "d" ((unsigned long)state), [token] "d" (token) 99 : "memory", "cc", "1"); 100 *count = _ccq & 0xff; 101 *start = _queuestart & 0xff; 102 103 return (_ccq >> 32) & 0xff; 104 } 105 106 static inline int do_eqbs(u64 token, unsigned char *state, int queue, 107 int *start, int *count, int ack) 108 { 109 unsigned long _queuestart = ((unsigned long)queue << 32) | *start; 110 unsigned long _state = (unsigned long)ack << 63; 111 unsigned long _ccq = *count; 112 113 asm volatile( 114 " lgr 1,%[token]\n" 115 " .insn rrf,0xb99c0000,%[qs],%[state],%[ccq],0" 116 : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart), 117 [state] "+&d" (_state) 118 : [token] "d" (token) 119 : "memory", "cc", "1"); 120 *count = _ccq & 0xff; 121 *start = _queuestart & 0xff; 122 *state = _state & 0xff; 123 124 return (_ccq >> 32) & 0xff; 125 } 126 127 struct qdio_irq; 128 129 struct siga_flag { 130 u8 input:1; 131 u8 output:1; 132 u8 sync:1; 133 u8 sync_after_ai:1; 134 u8 sync_out_after_pci:1; 135 u8:3; 136 } __attribute__ ((packed)); 137 138 struct qdio_dev_perf_stat { 139 unsigned int adapter_int; 140 unsigned int qdio_int; 141 unsigned int pci_request_int; 142 143 unsigned int tasklet_outbound; 144 145 unsigned int siga_read; 146 unsigned int siga_write; 147 unsigned int siga_sync; 148 149 unsigned int inbound_call; 150 unsigned int stop_polling; 151 unsigned int inbound_queue_full; 152 unsigned int outbound_call; 153 unsigned int outbound_handler; 154 unsigned int outbound_queue_full; 155 unsigned int fast_requeue; 156 unsigned int target_full; 157 unsigned int eqbs; 158 unsigned int eqbs_partial; 159 unsigned int sqbs; 160 unsigned int sqbs_partial; 161 unsigned int int_discarded; 162 } ____cacheline_aligned; 163 164 struct qdio_queue_perf_stat { 165 /* Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128. */ 166 unsigned int nr_sbals[8]; 167 unsigned int nr_sbal_error; 168 unsigned int nr_sbal_nop; 169 unsigned int nr_sbal_total; 170 }; 171 172 enum qdio_irq_poll_states { 173 QDIO_IRQ_DISABLED, 174 }; 175 176 struct qdio_input_q { 177 /* Batch of SBALs that we processed while polling the queue: */ 178 unsigned int batch_start; 179 unsigned int batch_count; 180 }; 181 182 struct qdio_output_q { 183 /* PCIs are enabled for the queue */ 184 int pci_out_enabled; 185 /* timer to check for more outbound work */ 186 struct timer_list timer; 187 /* tasklet to check for completions */ 188 struct tasklet_struct tasklet; 189 }; 190 191 /* 192 * Note on cache alignment: grouped slsb and write mostly data at the beginning 193 * sbal[] is read-only and starts on a new cacheline followed by read mostly. 194 */ 195 struct qdio_q { 196 struct slsb slsb; 197 198 union { 199 struct qdio_input_q in; 200 struct qdio_output_q out; 201 } u; 202 203 /* 204 * inbound: next buffer the program should check for 205 * outbound: next buffer to check if adapter processed it 206 */ 207 int first_to_check; 208 209 /* number of buffers in use by the adapter */ 210 atomic_t nr_buf_used; 211 212 /* last scan of the queue */ 213 u64 timestamp; 214 215 struct qdio_queue_perf_stat q_stats; 216 217 struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned; 218 219 /* queue number */ 220 int nr; 221 222 /* bitmask of queue number */ 223 int mask; 224 225 /* input or output queue */ 226 int is_input_q; 227 228 /* upper-layer program handler */ 229 qdio_handler_t (*handler); 230 231 struct qdio_irq *irq_ptr; 232 struct sl *sl; 233 /* 234 * A page is allocated under this pointer and used for slib and sl. 235 * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2. 236 */ 237 struct slib *slib; 238 } __attribute__ ((aligned(256))); 239 240 struct qdio_irq { 241 struct qib qib; 242 u32 *dsci; /* address of device state change indicator */ 243 struct ccw_device *cdev; 244 struct list_head entry; /* list of thinint devices */ 245 struct dentry *debugfs_dev; 246 u64 last_data_irq_time; 247 248 unsigned long int_parm; 249 struct subchannel_id schid; 250 unsigned long sch_token; /* QEBSM facility */ 251 252 enum qdio_irq_states state; 253 254 struct siga_flag siga_flag; /* siga sync information from qdioac */ 255 256 int nr_input_qs; 257 int nr_output_qs; 258 259 struct ccw1 ccw; 260 struct ciw equeue; 261 struct ciw aqueue; 262 263 struct qdio_ssqd_desc ssqd_desc; 264 void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *); 265 266 unsigned int scan_threshold; /* used SBALs before tasklet schedule */ 267 int perf_stat_enabled; 268 269 struct qdr *qdr; 270 unsigned long chsc_page; 271 272 struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ]; 273 struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ]; 274 unsigned int max_input_qs; 275 unsigned int max_output_qs; 276 277 void (*irq_poll)(struct ccw_device *cdev, unsigned long data); 278 unsigned long poll_state; 279 280 debug_info_t *debug_area; 281 struct mutex setup_mutex; 282 struct qdio_dev_perf_stat perf_stat; 283 }; 284 285 /* helper functions */ 286 #define queue_type(q) q->irq_ptr->qib.qfmt 287 #define SCH_NO(q) (q->irq_ptr->schid.sch_no) 288 289 #define is_thinint_irq(irq) \ 290 (irq->qib.qfmt == QDIO_IQDIO_QFMT || \ 291 css_general_characteristics.aif_osa) 292 293 #define qperf(__qdev, __attr) ((__qdev)->perf_stat.(__attr)) 294 295 #define QDIO_PERF_STAT_INC(__irq, __attr) \ 296 ({ \ 297 struct qdio_irq *qdev = __irq; \ 298 if (qdev->perf_stat_enabled) \ 299 (qdev->perf_stat.__attr)++; \ 300 }) 301 302 #define qperf_inc(__q, __attr) QDIO_PERF_STAT_INC((__q)->irq_ptr, __attr) 303 304 static inline void account_sbals_error(struct qdio_q *q, int count) 305 { 306 q->q_stats.nr_sbal_error += count; 307 q->q_stats.nr_sbal_total += count; 308 } 309 310 /* the highest iqdio queue is used for multicast */ 311 static inline int multicast_outbound(struct qdio_q *q) 312 { 313 return (q->irq_ptr->nr_output_qs > 1) && 314 (q->nr == q->irq_ptr->nr_output_qs - 1); 315 } 316 317 static inline void qdio_deliver_irq(struct qdio_irq *irq) 318 { 319 if (!test_and_set_bit(QDIO_IRQ_DISABLED, &irq->poll_state)) 320 irq->irq_poll(irq->cdev, irq->int_parm); 321 else 322 QDIO_PERF_STAT_INC(irq, int_discarded); 323 } 324 325 #define pci_out_supported(irq) ((irq)->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED) 326 #define is_qebsm(q) (q->irq_ptr->sch_token != 0) 327 328 #define need_siga_in(q) (q->irq_ptr->siga_flag.input) 329 #define need_siga_out(q) (q->irq_ptr->siga_flag.output) 330 #define need_siga_sync(q) (unlikely(q->irq_ptr->siga_flag.sync)) 331 #define need_siga_sync_after_ai(q) \ 332 (unlikely(q->irq_ptr->siga_flag.sync_after_ai)) 333 #define need_siga_sync_out_after_pci(q) \ 334 (unlikely(q->irq_ptr->siga_flag.sync_out_after_pci)) 335 336 #define for_each_input_queue(irq_ptr, q, i) \ 337 for (i = 0; i < irq_ptr->nr_input_qs && \ 338 ({ q = irq_ptr->input_qs[i]; 1; }); i++) 339 #define for_each_output_queue(irq_ptr, q, i) \ 340 for (i = 0; i < irq_ptr->nr_output_qs && \ 341 ({ q = irq_ptr->output_qs[i]; 1; }); i++) 342 343 #define add_buf(bufnr, inc) QDIO_BUFNR((bufnr) + (inc)) 344 #define next_buf(bufnr) add_buf(bufnr, 1) 345 #define sub_buf(bufnr, dec) QDIO_BUFNR((bufnr) - (dec)) 346 #define prev_buf(bufnr) sub_buf(bufnr, 1) 347 348 #define queue_irqs_enabled(q) \ 349 (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0) 350 #define queue_irqs_disabled(q) \ 351 (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0) 352 353 extern u64 last_ai_time; 354 355 /* prototypes for thin interrupt */ 356 int qdio_establish_thinint(struct qdio_irq *irq_ptr); 357 void qdio_shutdown_thinint(struct qdio_irq *irq_ptr); 358 int qdio_thinint_init(void); 359 void qdio_thinint_exit(void); 360 int test_nonshared_ind(struct qdio_irq *); 361 362 /* prototypes for setup */ 363 void qdio_outbound_tasklet(struct tasklet_struct *t); 364 void qdio_outbound_timer(struct timer_list *t); 365 void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm, 366 struct irb *irb); 367 int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs, 368 int nr_output_qs); 369 void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr); 370 int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr, 371 struct subchannel_id *schid, 372 struct qdio_ssqd_desc *data); 373 int qdio_setup_irq(struct qdio_irq *irq_ptr, struct qdio_initialize *init_data); 374 void qdio_shutdown_irq(struct qdio_irq *irq); 375 void qdio_print_subchannel_info(struct qdio_irq *irq_ptr); 376 void qdio_free_queues(struct qdio_irq *irq_ptr); 377 int qdio_setup_init(void); 378 void qdio_setup_exit(void); 379 380 int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr, 381 unsigned char *state); 382 #endif /* _CIO_QDIO_H */ 383