xref: /openbmc/linux/drivers/s390/cio/qdio.h (revision baa7eb025ab14f3cba2e35c0a8648f9c9f01d24f)
1 /*
2  * linux/drivers/s390/cio/qdio.h
3  *
4  * Copyright 2000,2009 IBM Corp.
5  * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
6  *	      Jan Glauber <jang@linux.vnet.ibm.com>
7  */
8 #ifndef _CIO_QDIO_H
9 #define _CIO_QDIO_H
10 
11 #include <asm/page.h>
12 #include <asm/schid.h>
13 #include <asm/debug.h>
14 #include "chsc.h"
15 
16 #define QDIO_BUSY_BIT_PATIENCE		(100 << 12)	/* 100 microseconds */
17 #define QDIO_INPUT_THRESHOLD		(500 << 12)	/* 500 microseconds */
18 
19 /*
20  * if an asynchronous HiperSockets queue runs full, the 10 seconds timer wait
21  * till next initiative to give transmitted skbs back to the stack is too long.
22  * Therefore polling is started in case of multicast queue is filled more
23  * than 50 percent.
24  */
25 #define QDIO_IQDIO_POLL_LVL		65	/* HS multicast queue */
26 
27 enum qdio_irq_states {
28 	QDIO_IRQ_STATE_INACTIVE,
29 	QDIO_IRQ_STATE_ESTABLISHED,
30 	QDIO_IRQ_STATE_ACTIVE,
31 	QDIO_IRQ_STATE_STOPPED,
32 	QDIO_IRQ_STATE_CLEANUP,
33 	QDIO_IRQ_STATE_ERR,
34 	NR_QDIO_IRQ_STATES,
35 };
36 
37 /* used as intparm in do_IO */
38 #define QDIO_DOING_ESTABLISH	1
39 #define QDIO_DOING_ACTIVATE	2
40 #define QDIO_DOING_CLEANUP	3
41 
42 #define SLSB_STATE_NOT_INIT	0x0
43 #define SLSB_STATE_EMPTY	0x1
44 #define SLSB_STATE_PRIMED	0x2
45 #define SLSB_STATE_HALTED	0xe
46 #define SLSB_STATE_ERROR	0xf
47 #define SLSB_TYPE_INPUT		0x0
48 #define SLSB_TYPE_OUTPUT	0x20
49 #define SLSB_OWNER_PROG		0x80
50 #define SLSB_OWNER_CU		0x40
51 
52 #define SLSB_P_INPUT_NOT_INIT	\
53 	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT)  /* 0x80 */
54 #define SLSB_P_INPUT_ACK	\
55 	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY)	   /* 0x81 */
56 #define SLSB_CU_INPUT_EMPTY	\
57 	(SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY)	   /* 0x41 */
58 #define SLSB_P_INPUT_PRIMED	\
59 	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED)	   /* 0x82 */
60 #define SLSB_P_INPUT_HALTED	\
61 	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED)	   /* 0x8e */
62 #define SLSB_P_INPUT_ERROR	\
63 	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR)	   /* 0x8f */
64 #define SLSB_P_OUTPUT_NOT_INIT	\
65 	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */
66 #define SLSB_P_OUTPUT_EMPTY	\
67 	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY)	   /* 0xa1 */
68 #define SLSB_CU_OUTPUT_PRIMED	\
69 	(SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED)	   /* 0x62 */
70 #define SLSB_P_OUTPUT_HALTED	\
71 	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED)   /* 0xae */
72 #define SLSB_P_OUTPUT_ERROR	\
73 	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR)	   /* 0xaf */
74 
75 #define SLSB_ERROR_DURING_LOOKUP  0xff
76 
77 /* additional CIWs returned by extended Sense-ID */
78 #define CIW_TYPE_EQUEUE			0x3 /* establish QDIO queues */
79 #define CIW_TYPE_AQUEUE			0x4 /* activate QDIO queues */
80 
81 /* flags for st qdio sch data */
82 #define CHSC_FLAG_QDIO_CAPABILITY	0x80
83 #define CHSC_FLAG_VALIDITY		0x40
84 
85 /* qdio adapter-characteristics-1 flag */
86 #define AC1_SIGA_INPUT_NEEDED		0x40	/* process input queues */
87 #define AC1_SIGA_OUTPUT_NEEDED		0x20	/* process output queues */
88 #define AC1_SIGA_SYNC_NEEDED		0x10	/* ask hypervisor to sync */
89 #define AC1_AUTOMATIC_SYNC_ON_THININT	0x08	/* set by hypervisor */
90 #define AC1_AUTOMATIC_SYNC_ON_OUT_PCI	0x04	/* set by hypervisor */
91 #define AC1_SC_QEBSM_AVAILABLE		0x02	/* available for subchannel */
92 #define AC1_SC_QEBSM_ENABLED		0x01	/* enabled for subchannel */
93 
94 #ifdef CONFIG_64BIT
95 static inline int do_sqbs(u64 token, unsigned char state, int queue,
96 			  int *start, int *count)
97 {
98 	register unsigned long _ccq asm ("0") = *count;
99 	register unsigned long _token asm ("1") = token;
100 	unsigned long _queuestart = ((unsigned long)queue << 32) | *start;
101 
102 	asm volatile(
103 		"	.insn	rsy,0xeb000000008A,%1,0,0(%2)"
104 		: "+d" (_ccq), "+d" (_queuestart)
105 		: "d" ((unsigned long)state), "d" (_token)
106 		: "memory", "cc");
107 	*count = _ccq & 0xff;
108 	*start = _queuestart & 0xff;
109 
110 	return (_ccq >> 32) & 0xff;
111 }
112 
113 static inline int do_eqbs(u64 token, unsigned char *state, int queue,
114 			  int *start, int *count, int ack)
115 {
116 	register unsigned long _ccq asm ("0") = *count;
117 	register unsigned long _token asm ("1") = token;
118 	unsigned long _queuestart = ((unsigned long)queue << 32) | *start;
119 	unsigned long _state = (unsigned long)ack << 63;
120 
121 	asm volatile(
122 		"	.insn	rrf,0xB99c0000,%1,%2,0,0"
123 		: "+d" (_ccq), "+d" (_queuestart), "+d" (_state)
124 		: "d" (_token)
125 		: "memory", "cc");
126 	*count = _ccq & 0xff;
127 	*start = _queuestart & 0xff;
128 	*state = _state & 0xff;
129 
130 	return (_ccq >> 32) & 0xff;
131 }
132 #else
133 static inline int do_sqbs(u64 token, unsigned char state, int queue,
134 			  int *start, int *count) { return 0; }
135 static inline int do_eqbs(u64 token, unsigned char *state, int queue,
136 			  int *start, int *count, int ack) { return 0; }
137 #endif /* CONFIG_64BIT */
138 
139 struct qdio_irq;
140 
141 struct siga_flag {
142 	u8 input:1;
143 	u8 output:1;
144 	u8 sync:1;
145 	u8 no_sync_ti:1;
146 	u8 no_sync_out_ti:1;
147 	u8 no_sync_out_pci:1;
148 	u8:2;
149 } __attribute__ ((packed));
150 
151 struct chsc_ssqd_area {
152 	struct chsc_header request;
153 	u16:10;
154 	u8 ssid:2;
155 	u8 fmt:4;
156 	u16 first_sch;
157 	u16:16;
158 	u16 last_sch;
159 	u32:32;
160 	struct chsc_header response;
161 	u32:32;
162 	struct qdio_ssqd_desc qdio_ssqd;
163 } __attribute__ ((packed));
164 
165 struct scssc_area {
166 	struct chsc_header request;
167 	u16 operation_code;
168 	u16:16;
169 	u32:32;
170 	u32:32;
171 	u64 summary_indicator_addr;
172 	u64 subchannel_indicator_addr;
173 	u32 ks:4;
174 	u32 kc:4;
175 	u32:21;
176 	u32 isc:3;
177 	u32 word_with_d_bit;
178 	u32:32;
179 	struct subchannel_id schid;
180 	u32 reserved[1004];
181 	struct chsc_header response;
182 	u32:32;
183 } __attribute__ ((packed));
184 
185 struct qdio_dev_perf_stat {
186 	unsigned int adapter_int;
187 	unsigned int qdio_int;
188 	unsigned int pci_request_int;
189 
190 	unsigned int tasklet_inbound;
191 	unsigned int tasklet_inbound_resched;
192 	unsigned int tasklet_inbound_resched2;
193 	unsigned int tasklet_outbound;
194 
195 	unsigned int siga_read;
196 	unsigned int siga_write;
197 	unsigned int siga_sync;
198 
199 	unsigned int inbound_call;
200 	unsigned int inbound_handler;
201 	unsigned int stop_polling;
202 	unsigned int inbound_queue_full;
203 	unsigned int outbound_call;
204 	unsigned int outbound_handler;
205 	unsigned int fast_requeue;
206 	unsigned int target_full;
207 	unsigned int eqbs;
208 	unsigned int eqbs_partial;
209 	unsigned int sqbs;
210 	unsigned int sqbs_partial;
211 	unsigned int int_discarded;
212 } ____cacheline_aligned;
213 
214 struct qdio_queue_perf_stat {
215 	/*
216 	 * Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128.
217 	 * Since max. 127 SBALs are scanned reuse entry for 128 as queue full
218 	 * aka 127 SBALs found.
219 	 */
220 	unsigned int nr_sbals[8];
221 	unsigned int nr_sbal_error;
222 	unsigned int nr_sbal_nop;
223 	unsigned int nr_sbal_total;
224 };
225 
226 enum qdio_queue_irq_states {
227 	QDIO_QUEUE_IRQS_DISABLED,
228 };
229 
230 struct qdio_input_q {
231 	/* input buffer acknowledgement flag */
232 	int polling;
233 	/* first ACK'ed buffer */
234 	int ack_start;
235 	/* how much sbals are acknowledged with qebsm */
236 	int ack_count;
237 	/* last time of noticing incoming data */
238 	u64 timestamp;
239 	/* upper-layer polling flag */
240 	unsigned long queue_irq_state;
241 	/* callback to start upper-layer polling */
242 	void (*queue_start_poll) (struct ccw_device *, int, unsigned long);
243 };
244 
245 struct qdio_output_q {
246 	/* PCIs are enabled for the queue */
247 	int pci_out_enabled;
248 	/* IQDIO: output multiple buffers (enhanced SIGA) */
249 	int use_enh_siga;
250 	/* timer to check for more outbound work */
251 	struct timer_list timer;
252 };
253 
254 /*
255  * Note on cache alignment: grouped slsb and write mostly data at the beginning
256  * sbal[] is read-only and starts on a new cacheline followed by read mostly.
257  */
258 struct qdio_q {
259 	struct slsb slsb;
260 
261 	union {
262 		struct qdio_input_q in;
263 		struct qdio_output_q out;
264 	} u;
265 
266 	/*
267 	 * inbound: next buffer the program should check for
268 	 * outbound: next buffer to check if adapter processed it
269 	 */
270 	int first_to_check;
271 
272 	/* first_to_check of the last time */
273 	int last_move;
274 
275 	/* beginning position for calling the program */
276 	int first_to_kick;
277 
278 	/* number of buffers in use by the adapter */
279 	atomic_t nr_buf_used;
280 
281 	/* error condition during a data transfer */
282 	unsigned int qdio_error;
283 
284 	struct tasklet_struct tasklet;
285 	struct qdio_queue_perf_stat q_stats;
286 
287 	struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned;
288 
289 	/* queue number */
290 	int nr;
291 
292 	/* bitmask of queue number */
293 	int mask;
294 
295 	/* input or output queue */
296 	int is_input_q;
297 
298 	/* list of thinint input queues */
299 	struct list_head entry;
300 
301 	/* upper-layer program handler */
302 	qdio_handler_t (*handler);
303 
304 	struct dentry *debugfs_q;
305 	struct qdio_irq *irq_ptr;
306 	struct sl *sl;
307 	/*
308 	 * A page is allocated under this pointer and used for slib and sl.
309 	 * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2.
310 	 */
311 	struct slib *slib;
312 } __attribute__ ((aligned(256)));
313 
314 struct qdio_irq {
315 	struct qib qib;
316 	u32 *dsci;		/* address of device state change indicator */
317 	struct ccw_device *cdev;
318 	struct dentry *debugfs_dev;
319 	struct dentry *debugfs_perf;
320 
321 	unsigned long int_parm;
322 	struct subchannel_id schid;
323 	unsigned long sch_token;	/* QEBSM facility */
324 
325 	enum qdio_irq_states state;
326 
327 	struct siga_flag siga_flag;	/* siga sync information from qdioac */
328 
329 	int nr_input_qs;
330 	int nr_output_qs;
331 
332 	struct ccw1 ccw;
333 	struct ciw equeue;
334 	struct ciw aqueue;
335 
336 	struct qdio_ssqd_desc ssqd_desc;
337 	void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *);
338 
339 	int perf_stat_enabled;
340 
341 	struct qdr *qdr;
342 	unsigned long chsc_page;
343 
344 	struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ];
345 	struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ];
346 
347 	debug_info_t *debug_area;
348 	struct mutex setup_mutex;
349 	struct qdio_dev_perf_stat perf_stat;
350 };
351 
352 /* helper functions */
353 #define queue_type(q)	q->irq_ptr->qib.qfmt
354 #define SCH_NO(q)	(q->irq_ptr->schid.sch_no)
355 
356 #define is_thinint_irq(irq) \
357 	(irq->qib.qfmt == QDIO_IQDIO_QFMT || \
358 	 css_general_characteristics.aif_osa)
359 
360 #define qperf(__qdev, __attr)	((__qdev)->perf_stat.(__attr))
361 
362 #define qperf_inc(__q, __attr)						\
363 ({									\
364 	struct qdio_irq *qdev = (__q)->irq_ptr;				\
365 	if (qdev->perf_stat_enabled)					\
366 		(qdev->perf_stat.__attr)++;				\
367 })
368 
369 static inline void account_sbals_error(struct qdio_q *q, int count)
370 {
371 	q->q_stats.nr_sbal_error += count;
372 	q->q_stats.nr_sbal_total += count;
373 }
374 
375 /* the highest iqdio queue is used for multicast */
376 static inline int multicast_outbound(struct qdio_q *q)
377 {
378 	return (q->irq_ptr->nr_output_qs > 1) &&
379 	       (q->nr == q->irq_ptr->nr_output_qs - 1);
380 }
381 
382 #define pci_out_supported(q) \
383 	(q->irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)
384 #define is_qebsm(q)			(q->irq_ptr->sch_token != 0)
385 
386 #define need_siga_sync_thinint(q)	(!q->irq_ptr->siga_flag.no_sync_ti)
387 #define need_siga_sync_out_thinint(q)	(!q->irq_ptr->siga_flag.no_sync_out_ti)
388 #define need_siga_in(q)			(q->irq_ptr->siga_flag.input)
389 #define need_siga_out(q)		(q->irq_ptr->siga_flag.output)
390 #define need_siga_sync(q)		(q->irq_ptr->siga_flag.sync)
391 #define siga_syncs_out_pci(q)		(q->irq_ptr->siga_flag.no_sync_out_pci)
392 
393 #define for_each_input_queue(irq_ptr, q, i)	\
394 	for (i = 0, q = irq_ptr->input_qs[0];	\
395 		i < irq_ptr->nr_input_qs;	\
396 		q = irq_ptr->input_qs[++i])
397 #define for_each_output_queue(irq_ptr, q, i)	\
398 	for (i = 0, q = irq_ptr->output_qs[0];	\
399 		i < irq_ptr->nr_output_qs;	\
400 		q = irq_ptr->output_qs[++i])
401 
402 #define prev_buf(bufnr)	\
403 	((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK)
404 #define next_buf(bufnr)	\
405 	((bufnr + 1) & QDIO_MAX_BUFFERS_MASK)
406 #define add_buf(bufnr, inc) \
407 	((bufnr + inc) & QDIO_MAX_BUFFERS_MASK)
408 #define sub_buf(bufnr, dec) \
409 	((bufnr - dec) & QDIO_MAX_BUFFERS_MASK)
410 
411 #define queue_irqs_enabled(q)			\
412 	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0)
413 #define queue_irqs_disabled(q)			\
414 	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0)
415 
416 #define TIQDIO_SHARED_IND		63
417 
418 /* device state change indicators */
419 struct indicator_t {
420 	u32 ind;	/* u32 because of compare-and-swap performance */
421 	atomic_t count; /* use count, 0 or 1 for non-shared indicators */
422 };
423 
424 extern struct indicator_t *q_indicators;
425 
426 static inline int shared_ind(struct qdio_irq *irq_ptr)
427 {
428 	return irq_ptr->dsci == &q_indicators[TIQDIO_SHARED_IND].ind;
429 }
430 
431 /* prototypes for thin interrupt */
432 void qdio_setup_thinint(struct qdio_irq *irq_ptr);
433 int qdio_establish_thinint(struct qdio_irq *irq_ptr);
434 void qdio_shutdown_thinint(struct qdio_irq *irq_ptr);
435 void tiqdio_add_input_queues(struct qdio_irq *irq_ptr);
436 void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr);
437 void tiqdio_inbound_processing(unsigned long q);
438 int tiqdio_allocate_memory(void);
439 void tiqdio_free_memory(void);
440 int tiqdio_register_thinints(void);
441 void tiqdio_unregister_thinints(void);
442 
443 /* prototypes for setup */
444 void qdio_inbound_processing(unsigned long data);
445 void qdio_outbound_processing(unsigned long data);
446 void qdio_outbound_timer(unsigned long data);
447 void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm,
448 		      struct irb *irb);
449 int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs,
450 		     int nr_output_qs);
451 void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr);
452 int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr,
453 			struct subchannel_id *schid,
454 			struct qdio_ssqd_desc *data);
455 int qdio_setup_irq(struct qdio_initialize *init_data);
456 void qdio_print_subchannel_info(struct qdio_irq *irq_ptr,
457 				struct ccw_device *cdev);
458 void qdio_release_memory(struct qdio_irq *irq_ptr);
459 int qdio_setup_create_sysfs(struct ccw_device *cdev);
460 void qdio_setup_destroy_sysfs(struct ccw_device *cdev);
461 int qdio_setup_init(void);
462 void qdio_setup_exit(void);
463 
464 int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr,
465 			unsigned char *state);
466 #endif /* _CIO_QDIO_H */
467