1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright IBM Corp. 2000, 2009 4 * Author(s): Utz Bacher <utz.bacher@de.ibm.com> 5 * Jan Glauber <jang@linux.vnet.ibm.com> 6 */ 7 #ifndef _CIO_QDIO_H 8 #define _CIO_QDIO_H 9 10 #include <asm/page.h> 11 #include <asm/schid.h> 12 #include <asm/debug.h> 13 #include "chsc.h" 14 15 #define QDIO_BUSY_BIT_PATIENCE (100 << 12) /* 100 microseconds */ 16 #define QDIO_BUSY_BIT_RETRY_DELAY 10 /* 10 milliseconds */ 17 #define QDIO_BUSY_BIT_RETRIES 1000 /* = 10s retry time */ 18 #define QDIO_INPUT_THRESHOLD (500 << 12) /* 500 microseconds */ 19 20 enum qdio_irq_states { 21 QDIO_IRQ_STATE_INACTIVE, 22 QDIO_IRQ_STATE_ESTABLISHED, 23 QDIO_IRQ_STATE_ACTIVE, 24 QDIO_IRQ_STATE_STOPPED, 25 QDIO_IRQ_STATE_CLEANUP, 26 QDIO_IRQ_STATE_ERR, 27 NR_QDIO_IRQ_STATES, 28 }; 29 30 /* used as intparm in do_IO */ 31 #define QDIO_DOING_ESTABLISH 1 32 #define QDIO_DOING_ACTIVATE 2 33 #define QDIO_DOING_CLEANUP 3 34 35 #define SLSB_STATE_NOT_INIT 0x0 36 #define SLSB_STATE_EMPTY 0x1 37 #define SLSB_STATE_PRIMED 0x2 38 #define SLSB_STATE_PENDING 0x3 39 #define SLSB_STATE_HALTED 0xe 40 #define SLSB_STATE_ERROR 0xf 41 #define SLSB_TYPE_INPUT 0x0 42 #define SLSB_TYPE_OUTPUT 0x20 43 #define SLSB_OWNER_PROG 0x80 44 #define SLSB_OWNER_CU 0x40 45 46 #define SLSB_P_INPUT_NOT_INIT \ 47 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT) /* 0x80 */ 48 #define SLSB_P_INPUT_ACK \ 49 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x81 */ 50 #define SLSB_CU_INPUT_EMPTY \ 51 (SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x41 */ 52 #define SLSB_P_INPUT_PRIMED \ 53 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED) /* 0x82 */ 54 #define SLSB_P_INPUT_HALTED \ 55 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED) /* 0x8e */ 56 #define SLSB_P_INPUT_ERROR \ 57 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR) /* 0x8f */ 58 #define SLSB_P_OUTPUT_NOT_INIT \ 59 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */ 60 #define SLSB_P_OUTPUT_EMPTY \ 61 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY) /* 0xa1 */ 62 #define SLSB_P_OUTPUT_PENDING \ 63 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_PENDING) /* 0xa3 */ 64 #define SLSB_CU_OUTPUT_PRIMED \ 65 (SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED) /* 0x62 */ 66 #define SLSB_P_OUTPUT_HALTED \ 67 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED) /* 0xae */ 68 #define SLSB_P_OUTPUT_ERROR \ 69 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR) /* 0xaf */ 70 71 #define SLSB_ERROR_DURING_LOOKUP 0xff 72 73 /* additional CIWs returned by extended Sense-ID */ 74 #define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */ 75 #define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */ 76 77 /* flags for st qdio sch data */ 78 #define CHSC_FLAG_QDIO_CAPABILITY 0x80 79 #define CHSC_FLAG_VALIDITY 0x40 80 81 /* SIGA flags */ 82 #define QDIO_SIGA_WRITE 0x00 83 #define QDIO_SIGA_READ 0x01 84 #define QDIO_SIGA_SYNC 0x02 85 #define QDIO_SIGA_WRITEQ 0x04 86 #define QDIO_SIGA_QEBSM_FLAG 0x80 87 88 static inline int do_sqbs(u64 token, unsigned char state, int queue, 89 int *start, int *count) 90 { 91 register unsigned long _ccq asm ("0") = *count; 92 register unsigned long _token asm ("1") = token; 93 unsigned long _queuestart = ((unsigned long)queue << 32) | *start; 94 95 asm volatile( 96 " .insn rsy,0xeb000000008A,%1,0,0(%2)" 97 : "+d" (_ccq), "+d" (_queuestart) 98 : "d" ((unsigned long)state), "d" (_token) 99 : "memory", "cc"); 100 *count = _ccq & 0xff; 101 *start = _queuestart & 0xff; 102 103 return (_ccq >> 32) & 0xff; 104 } 105 106 static inline int do_eqbs(u64 token, unsigned char *state, int queue, 107 int *start, int *count, int ack) 108 { 109 register unsigned long _ccq asm ("0") = *count; 110 register unsigned long _token asm ("1") = token; 111 unsigned long _queuestart = ((unsigned long)queue << 32) | *start; 112 unsigned long _state = (unsigned long)ack << 63; 113 114 asm volatile( 115 " .insn rrf,0xB99c0000,%1,%2,0,0" 116 : "+d" (_ccq), "+d" (_queuestart), "+d" (_state) 117 : "d" (_token) 118 : "memory", "cc"); 119 *count = _ccq & 0xff; 120 *start = _queuestart & 0xff; 121 *state = _state & 0xff; 122 123 return (_ccq >> 32) & 0xff; 124 } 125 126 struct qdio_irq; 127 128 struct siga_flag { 129 u8 input:1; 130 u8 output:1; 131 u8 sync:1; 132 u8 sync_after_ai:1; 133 u8 sync_out_after_pci:1; 134 u8:3; 135 } __attribute__ ((packed)); 136 137 struct qdio_dev_perf_stat { 138 unsigned int adapter_int; 139 unsigned int qdio_int; 140 unsigned int pci_request_int; 141 142 unsigned int tasklet_inbound; 143 unsigned int tasklet_inbound_resched; 144 unsigned int tasklet_inbound_resched2; 145 unsigned int tasklet_outbound; 146 147 unsigned int siga_read; 148 unsigned int siga_write; 149 unsigned int siga_sync; 150 151 unsigned int inbound_call; 152 unsigned int inbound_handler; 153 unsigned int stop_polling; 154 unsigned int inbound_queue_full; 155 unsigned int outbound_call; 156 unsigned int outbound_handler; 157 unsigned int outbound_queue_full; 158 unsigned int fast_requeue; 159 unsigned int target_full; 160 unsigned int eqbs; 161 unsigned int eqbs_partial; 162 unsigned int sqbs; 163 unsigned int sqbs_partial; 164 unsigned int int_discarded; 165 } ____cacheline_aligned; 166 167 struct qdio_queue_perf_stat { 168 /* 169 * Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128. 170 * Since max. 127 SBALs are scanned reuse entry for 128 as queue full 171 * aka 127 SBALs found. 172 */ 173 unsigned int nr_sbals[8]; 174 unsigned int nr_sbal_error; 175 unsigned int nr_sbal_nop; 176 unsigned int nr_sbal_total; 177 }; 178 179 enum qdio_queue_irq_states { 180 QDIO_QUEUE_IRQS_DISABLED, 181 }; 182 183 struct qdio_input_q { 184 /* input buffer acknowledgement flag */ 185 int polling; 186 /* first ACK'ed buffer */ 187 int ack_start; 188 /* how much sbals are acknowledged with qebsm */ 189 int ack_count; 190 /* last time of noticing incoming data */ 191 u64 timestamp; 192 /* upper-layer polling flag */ 193 unsigned long queue_irq_state; 194 /* callback to start upper-layer polling */ 195 void (*queue_start_poll) (struct ccw_device *, int, unsigned long); 196 }; 197 198 struct qdio_output_q { 199 /* PCIs are enabled for the queue */ 200 int pci_out_enabled; 201 /* cq: use asynchronous output buffers */ 202 int use_cq; 203 /* cq: aobs used for particual SBAL */ 204 struct qaob **aobs; 205 /* cq: sbal state related to asynchronous operation */ 206 struct qdio_outbuf_state *sbal_state; 207 /* timer to check for more outbound work */ 208 struct timer_list timer; 209 }; 210 211 /* 212 * Note on cache alignment: grouped slsb and write mostly data at the beginning 213 * sbal[] is read-only and starts on a new cacheline followed by read mostly. 214 */ 215 struct qdio_q { 216 struct slsb slsb; 217 218 union { 219 struct qdio_input_q in; 220 struct qdio_output_q out; 221 } u; 222 223 /* 224 * inbound: next buffer the program should check for 225 * outbound: next buffer to check if adapter processed it 226 */ 227 int first_to_check; 228 229 /* beginning position for calling the program */ 230 int first_to_kick; 231 232 /* number of buffers in use by the adapter */ 233 atomic_t nr_buf_used; 234 235 /* error condition during a data transfer */ 236 unsigned int qdio_error; 237 238 /* last scan of the queue */ 239 u64 timestamp; 240 241 struct tasklet_struct tasklet; 242 struct qdio_queue_perf_stat q_stats; 243 244 struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned; 245 246 /* queue number */ 247 int nr; 248 249 /* bitmask of queue number */ 250 int mask; 251 252 /* input or output queue */ 253 int is_input_q; 254 255 /* list of thinint input queues */ 256 struct list_head entry; 257 258 /* upper-layer program handler */ 259 qdio_handler_t (*handler); 260 261 struct dentry *debugfs_q; 262 struct qdio_irq *irq_ptr; 263 struct sl *sl; 264 /* 265 * A page is allocated under this pointer and used for slib and sl. 266 * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2. 267 */ 268 struct slib *slib; 269 } __attribute__ ((aligned(256))); 270 271 struct qdio_irq { 272 struct qib qib; 273 u32 *dsci; /* address of device state change indicator */ 274 struct ccw_device *cdev; 275 struct dentry *debugfs_dev; 276 struct dentry *debugfs_perf; 277 278 unsigned long int_parm; 279 struct subchannel_id schid; 280 unsigned long sch_token; /* QEBSM facility */ 281 282 enum qdio_irq_states state; 283 284 struct siga_flag siga_flag; /* siga sync information from qdioac */ 285 286 int nr_input_qs; 287 int nr_output_qs; 288 289 struct ccw1 ccw; 290 struct ciw equeue; 291 struct ciw aqueue; 292 293 struct qdio_ssqd_desc ssqd_desc; 294 void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *); 295 296 unsigned int scan_threshold; /* used SBALs before tasklet schedule */ 297 int perf_stat_enabled; 298 299 struct qdr *qdr; 300 unsigned long chsc_page; 301 302 struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ]; 303 struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ]; 304 305 debug_info_t *debug_area; 306 struct mutex setup_mutex; 307 struct qdio_dev_perf_stat perf_stat; 308 }; 309 310 /* helper functions */ 311 #define queue_type(q) q->irq_ptr->qib.qfmt 312 #define SCH_NO(q) (q->irq_ptr->schid.sch_no) 313 314 #define is_thinint_irq(irq) \ 315 (irq->qib.qfmt == QDIO_IQDIO_QFMT || \ 316 css_general_characteristics.aif_osa) 317 318 #define qperf(__qdev, __attr) ((__qdev)->perf_stat.(__attr)) 319 320 #define qperf_inc(__q, __attr) \ 321 ({ \ 322 struct qdio_irq *qdev = (__q)->irq_ptr; \ 323 if (qdev->perf_stat_enabled) \ 324 (qdev->perf_stat.__attr)++; \ 325 }) 326 327 static inline void account_sbals_error(struct qdio_q *q, int count) 328 { 329 q->q_stats.nr_sbal_error += count; 330 q->q_stats.nr_sbal_total += count; 331 } 332 333 /* the highest iqdio queue is used for multicast */ 334 static inline int multicast_outbound(struct qdio_q *q) 335 { 336 return (q->irq_ptr->nr_output_qs > 1) && 337 (q->nr == q->irq_ptr->nr_output_qs - 1); 338 } 339 340 #define pci_out_supported(irq) ((irq)->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED) 341 #define is_qebsm(q) (q->irq_ptr->sch_token != 0) 342 343 #define need_siga_in(q) (q->irq_ptr->siga_flag.input) 344 #define need_siga_out(q) (q->irq_ptr->siga_flag.output) 345 #define need_siga_sync(q) (unlikely(q->irq_ptr->siga_flag.sync)) 346 #define need_siga_sync_after_ai(q) \ 347 (unlikely(q->irq_ptr->siga_flag.sync_after_ai)) 348 #define need_siga_sync_out_after_pci(q) \ 349 (unlikely(q->irq_ptr->siga_flag.sync_out_after_pci)) 350 351 #define for_each_input_queue(irq_ptr, q, i) \ 352 for (i = 0; i < irq_ptr->nr_input_qs && \ 353 ({ q = irq_ptr->input_qs[i]; 1; }); i++) 354 #define for_each_output_queue(irq_ptr, q, i) \ 355 for (i = 0; i < irq_ptr->nr_output_qs && \ 356 ({ q = irq_ptr->output_qs[i]; 1; }); i++) 357 358 #define prev_buf(bufnr) \ 359 ((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK) 360 #define next_buf(bufnr) \ 361 ((bufnr + 1) & QDIO_MAX_BUFFERS_MASK) 362 #define add_buf(bufnr, inc) \ 363 ((bufnr + inc) & QDIO_MAX_BUFFERS_MASK) 364 #define sub_buf(bufnr, dec) \ 365 ((bufnr - dec) & QDIO_MAX_BUFFERS_MASK) 366 367 #define queue_irqs_enabled(q) \ 368 (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0) 369 #define queue_irqs_disabled(q) \ 370 (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0) 371 372 extern u64 last_ai_time; 373 374 /* prototypes for thin interrupt */ 375 void qdio_setup_thinint(struct qdio_irq *irq_ptr); 376 int qdio_establish_thinint(struct qdio_irq *irq_ptr); 377 void qdio_shutdown_thinint(struct qdio_irq *irq_ptr); 378 void tiqdio_add_input_queues(struct qdio_irq *irq_ptr); 379 void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr); 380 void tiqdio_inbound_processing(unsigned long q); 381 int tiqdio_allocate_memory(void); 382 void tiqdio_free_memory(void); 383 int tiqdio_register_thinints(void); 384 void tiqdio_unregister_thinints(void); 385 void clear_nonshared_ind(struct qdio_irq *); 386 int test_nonshared_ind(struct qdio_irq *); 387 388 /* prototypes for setup */ 389 void qdio_inbound_processing(unsigned long data); 390 void qdio_outbound_processing(unsigned long data); 391 void qdio_outbound_timer(struct timer_list *t); 392 void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm, 393 struct irb *irb); 394 int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs, 395 int nr_output_qs); 396 void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr); 397 int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr, 398 struct subchannel_id *schid, 399 struct qdio_ssqd_desc *data); 400 int qdio_setup_irq(struct qdio_initialize *init_data); 401 void qdio_print_subchannel_info(struct qdio_irq *irq_ptr, 402 struct ccw_device *cdev); 403 void qdio_release_memory(struct qdio_irq *irq_ptr); 404 int qdio_setup_create_sysfs(struct ccw_device *cdev); 405 void qdio_setup_destroy_sysfs(struct ccw_device *cdev); 406 int qdio_setup_init(void); 407 void qdio_setup_exit(void); 408 int qdio_enable_async_operation(struct qdio_output_q *q); 409 void qdio_disable_async_operation(struct qdio_output_q *q); 410 struct qaob *qdio_allocate_aob(void); 411 412 int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr, 413 unsigned char *state); 414 #endif /* _CIO_QDIO_H */ 415