xref: /openbmc/linux/drivers/rtc/rtc-zynqmp.c (revision f89d416a)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
4  *
5  * Copyright (C) 2015 Xilinx, Inc.
6  *
7  */
8 
9 #include <linux/delay.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/rtc.h>
16 
17 /* RTC Registers */
18 #define RTC_SET_TM_WR		0x00
19 #define RTC_SET_TM_RD		0x04
20 #define RTC_CALIB_WR		0x08
21 #define RTC_CALIB_RD		0x0C
22 #define RTC_CUR_TM		0x10
23 #define RTC_CUR_TICK		0x14
24 #define RTC_ALRM		0x18
25 #define RTC_INT_STS		0x20
26 #define RTC_INT_MASK		0x24
27 #define RTC_INT_EN		0x28
28 #define RTC_INT_DIS		0x2C
29 #define RTC_CTRL		0x40
30 
31 #define RTC_FR_EN		BIT(20)
32 #define RTC_FR_DATSHIFT		16
33 #define RTC_TICK_MASK		0xFFFF
34 #define RTC_INT_SEC		BIT(0)
35 #define RTC_INT_ALRM		BIT(1)
36 #define RTC_OSC_EN		BIT(24)
37 #define RTC_BATT_EN		BIT(31)
38 
39 #define RTC_CALIB_DEF		0x198233
40 #define RTC_CALIB_MASK		0x1FFFFF
41 
42 struct xlnx_rtc_dev {
43 	struct rtc_device	*rtc;
44 	void __iomem		*reg_base;
45 	int			alarm_irq;
46 	int			sec_irq;
47 	unsigned int		calibval;
48 };
49 
50 static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
51 {
52 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
53 	unsigned long new_time;
54 
55 	/*
56 	 * The value written will be updated after 1 sec into the
57 	 * seconds read register, so we need to program time +1 sec
58 	 * to get the correct time on read.
59 	 */
60 	new_time = rtc_tm_to_time64(tm) + 1;
61 
62 	/*
63 	 * Writing into calibration register will clear the Tick Counter and
64 	 * force the next second to be signaled exactly in 1 second period
65 	 */
66 	xrtcdev->calibval &= RTC_CALIB_MASK;
67 	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
68 
69 	writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
70 
71 	/*
72 	 * Clear the rtc interrupt status register after setting the
73 	 * time. During a read_time function, the code should read the
74 	 * RTC_INT_STATUS register and if bit 0 is still 0, it means
75 	 * that one second has not elapsed yet since RTC was set and
76 	 * the current time should be read from SET_TIME_READ register;
77 	 * otherwise, CURRENT_TIME register is read to report the time
78 	 */
79 	writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS);
80 
81 	return 0;
82 }
83 
84 static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
85 {
86 	u32 status;
87 	unsigned long read_time;
88 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
89 
90 	status = readl(xrtcdev->reg_base + RTC_INT_STS);
91 
92 	if (status & RTC_INT_SEC) {
93 		/*
94 		 * RTC has updated the CURRENT_TIME with the time written into
95 		 * SET_TIME_WRITE register.
96 		 */
97 		rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);
98 	} else {
99 		/*
100 		 * Time written in SET_TIME_WRITE has not yet updated into
101 		 * the seconds read register, so read the time from the
102 		 * SET_TIME_WRITE instead of CURRENT_TIME register.
103 		 * Since we add +1 sec while writing, we need to -1 sec while
104 		 * reading.
105 		 */
106 		read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
107 		rtc_time64_to_tm(read_time, tm);
108 	}
109 
110 	return 0;
111 }
112 
113 static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
114 {
115 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
116 
117 	rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
118 	alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
119 
120 	return 0;
121 }
122 
123 static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
124 {
125 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
126 
127 	if (enabled)
128 		writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
129 	else
130 		writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
131 
132 	return 0;
133 }
134 
135 static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
136 {
137 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
138 	unsigned long alarm_time;
139 
140 	alarm_time = rtc_tm_to_time64(&alrm->time);
141 
142 	writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
143 
144 	xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
145 
146 	return 0;
147 }
148 
149 static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
150 {
151 	u32 rtc_ctrl;
152 
153 	/* Enable RTC switch to battery when VCC_PSAUX is not available */
154 	rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
155 	rtc_ctrl |= RTC_BATT_EN;
156 	writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
157 
158 	/*
159 	 * Based on crystal freq of 33.330 KHz
160 	 * set the seconds counter and enable, set fractions counter
161 	 * to default value suggested as per design spec
162 	 * to correct RTC delay in frequency over period of time.
163 	 */
164 	xrtcdev->calibval &= RTC_CALIB_MASK;
165 	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
166 }
167 
168 static const struct rtc_class_ops xlnx_rtc_ops = {
169 	.set_time	  = xlnx_rtc_set_time,
170 	.read_time	  = xlnx_rtc_read_time,
171 	.read_alarm	  = xlnx_rtc_read_alarm,
172 	.set_alarm	  = xlnx_rtc_set_alarm,
173 	.alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
174 };
175 
176 static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
177 {
178 	struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
179 	unsigned int status;
180 
181 	status = readl(xrtcdev->reg_base + RTC_INT_STS);
182 	/* Check if interrupt asserted */
183 	if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
184 		return IRQ_NONE;
185 
186 	/* Clear RTC_INT_ALRM interrupt only */
187 	writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
188 
189 	if (status & RTC_INT_ALRM)
190 		rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
191 
192 	return IRQ_HANDLED;
193 }
194 
195 static int xlnx_rtc_probe(struct platform_device *pdev)
196 {
197 	struct xlnx_rtc_dev *xrtcdev;
198 	int ret;
199 
200 	xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
201 	if (!xrtcdev)
202 		return -ENOMEM;
203 
204 	platform_set_drvdata(pdev, xrtcdev);
205 
206 	xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
207 	if (IS_ERR(xrtcdev->rtc))
208 		return PTR_ERR(xrtcdev->rtc);
209 
210 	xrtcdev->rtc->ops = &xlnx_rtc_ops;
211 	xrtcdev->rtc->range_max = U32_MAX;
212 
213 	xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
214 	if (IS_ERR(xrtcdev->reg_base))
215 		return PTR_ERR(xrtcdev->reg_base);
216 
217 	xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
218 	if (xrtcdev->alarm_irq < 0)
219 		return xrtcdev->alarm_irq;
220 	ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
221 			       xlnx_rtc_interrupt, 0,
222 			       dev_name(&pdev->dev), xrtcdev);
223 	if (ret) {
224 		dev_err(&pdev->dev, "request irq failed\n");
225 		return ret;
226 	}
227 
228 	xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
229 	if (xrtcdev->sec_irq < 0)
230 		return xrtcdev->sec_irq;
231 	ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
232 			       xlnx_rtc_interrupt, 0,
233 			       dev_name(&pdev->dev), xrtcdev);
234 	if (ret) {
235 		dev_err(&pdev->dev, "request irq failed\n");
236 		return ret;
237 	}
238 
239 	ret = of_property_read_u32(pdev->dev.of_node, "calibration",
240 				   &xrtcdev->calibval);
241 	if (ret)
242 		xrtcdev->calibval = RTC_CALIB_DEF;
243 
244 	xlnx_init_rtc(xrtcdev);
245 
246 	device_init_wakeup(&pdev->dev, 1);
247 
248 	return rtc_register_device(xrtcdev->rtc);
249 }
250 
251 static int xlnx_rtc_remove(struct platform_device *pdev)
252 {
253 	xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
254 	device_init_wakeup(&pdev->dev, 0);
255 
256 	return 0;
257 }
258 
259 static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
260 {
261 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
262 
263 	if (device_may_wakeup(dev))
264 		enable_irq_wake(xrtcdev->alarm_irq);
265 	else
266 		xlnx_rtc_alarm_irq_enable(dev, 0);
267 
268 	return 0;
269 }
270 
271 static int __maybe_unused xlnx_rtc_resume(struct device *dev)
272 {
273 	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
274 
275 	if (device_may_wakeup(dev))
276 		disable_irq_wake(xrtcdev->alarm_irq);
277 	else
278 		xlnx_rtc_alarm_irq_enable(dev, 1);
279 
280 	return 0;
281 }
282 
283 static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
284 
285 static const struct of_device_id xlnx_rtc_of_match[] = {
286 	{.compatible = "xlnx,zynqmp-rtc" },
287 	{ }
288 };
289 MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
290 
291 static struct platform_driver xlnx_rtc_driver = {
292 	.probe		= xlnx_rtc_probe,
293 	.remove		= xlnx_rtc_remove,
294 	.driver		= {
295 		.name	= KBUILD_MODNAME,
296 		.pm	= &xlnx_rtc_pm_ops,
297 		.of_match_table	= xlnx_rtc_of_match,
298 	},
299 };
300 
301 module_platform_driver(xlnx_rtc_driver);
302 
303 MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
304 MODULE_AUTHOR("Xilinx Inc.");
305 MODULE_LICENSE("GPL v2");
306