1 /* 2 * An RTC driver for the NVIDIA Tegra 200 series internal RTC. 3 * 4 * Copyright (c) 2010, NVIDIA Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/init.h> 24 #include <linux/io.h> 25 #include <linux/irq.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/mod_devicetable.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm.h> 31 #include <linux/rtc.h> 32 #include <linux/slab.h> 33 34 /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */ 35 #define TEGRA_RTC_REG_BUSY 0x004 36 #define TEGRA_RTC_REG_SECONDS 0x008 37 /* when msec is read, the seconds are buffered into shadow seconds. */ 38 #define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c 39 #define TEGRA_RTC_REG_MILLI_SECONDS 0x010 40 #define TEGRA_RTC_REG_SECONDS_ALARM0 0x014 41 #define TEGRA_RTC_REG_SECONDS_ALARM1 0x018 42 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c 43 #define TEGRA_RTC_REG_INTR_MASK 0x028 44 /* write 1 bits to clear status bits */ 45 #define TEGRA_RTC_REG_INTR_STATUS 0x02c 46 47 /* bits in INTR_MASK */ 48 #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4) 49 #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3) 50 #define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2) 51 #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1) 52 #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0) 53 54 /* bits in INTR_STATUS */ 55 #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4) 56 #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3) 57 #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2) 58 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1) 59 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0) 60 61 struct tegra_rtc_info { 62 struct platform_device *pdev; 63 struct rtc_device *rtc_dev; 64 void __iomem *rtc_base; /* NULL if not initialized. */ 65 struct clk *clk; 66 int tegra_rtc_irq; /* alarm and periodic irq */ 67 spinlock_t tegra_rtc_lock; 68 }; 69 70 /* RTC hardware is busy when it is updating its values over AHB once 71 * every eight 32kHz clocks (~250uS). 72 * outside of these updates the CPU is free to write. 73 * CPU is always free to read. 74 */ 75 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info) 76 { 77 return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1; 78 } 79 80 /* Wait for hardware to be ready for writing. 81 * This function tries to maximize the amount of time before the next update. 82 * It does this by waiting for the RTC to become busy with its periodic update, 83 * then returning once the RTC first becomes not busy. 84 * This periodic update (where the seconds and milliseconds are copied to the 85 * AHB side) occurs every eight 32kHz clocks (~250uS). 86 * The behavior of this function allows us to make some assumptions without 87 * introducing a race, because 250uS is plenty of time to read/write a value. 88 */ 89 static int tegra_rtc_wait_while_busy(struct device *dev) 90 { 91 struct tegra_rtc_info *info = dev_get_drvdata(dev); 92 93 int retries = 500; /* ~490 us is the worst case, ~250 us is best. */ 94 95 /* first wait for the RTC to become busy. this is when it 96 * posts its updated seconds+msec registers to AHB side. */ 97 while (tegra_rtc_check_busy(info)) { 98 if (!retries--) 99 goto retry_failed; 100 udelay(1); 101 } 102 103 /* now we have about 250 us to manipulate registers */ 104 return 0; 105 106 retry_failed: 107 dev_err(dev, "write failed:retry count exceeded.\n"); 108 return -ETIMEDOUT; 109 } 110 111 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm) 112 { 113 struct tegra_rtc_info *info = dev_get_drvdata(dev); 114 unsigned long sec, msec; 115 unsigned long sl_irq_flags; 116 117 /* RTC hardware copies seconds to shadow seconds when a read 118 * of milliseconds occurs. use a lock to keep other threads out. */ 119 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); 120 121 msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS); 122 sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS); 123 124 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); 125 126 rtc_time_to_tm(sec, tm); 127 128 dev_vdbg(dev, "time read as %lu. %ptR\n", sec, tm); 129 130 return 0; 131 } 132 133 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm) 134 { 135 struct tegra_rtc_info *info = dev_get_drvdata(dev); 136 unsigned long sec; 137 int ret; 138 139 /* convert tm to seconds. */ 140 rtc_tm_to_time(tm, &sec); 141 142 dev_vdbg(dev, "time set to %lu. %ptR\n", sec, tm); 143 144 /* seconds only written if wait succeeded. */ 145 ret = tegra_rtc_wait_while_busy(dev); 146 if (!ret) 147 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS); 148 149 dev_vdbg(dev, "time read back as %d\n", 150 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS)); 151 152 return ret; 153 } 154 155 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 156 { 157 struct tegra_rtc_info *info = dev_get_drvdata(dev); 158 unsigned long sec; 159 unsigned tmp; 160 161 sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); 162 163 if (sec == 0) { 164 /* alarm is disabled. */ 165 alarm->enabled = 0; 166 } else { 167 /* alarm is enabled. */ 168 alarm->enabled = 1; 169 rtc_time_to_tm(sec, &alarm->time); 170 } 171 172 tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 173 alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0; 174 175 return 0; 176 } 177 178 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 179 { 180 struct tegra_rtc_info *info = dev_get_drvdata(dev); 181 unsigned status; 182 unsigned long sl_irq_flags; 183 184 tegra_rtc_wait_while_busy(dev); 185 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); 186 187 /* read the original value, and OR in the flag. */ 188 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 189 if (enabled) 190 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */ 191 else 192 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */ 193 194 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 195 196 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); 197 198 return 0; 199 } 200 201 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 202 { 203 struct tegra_rtc_info *info = dev_get_drvdata(dev); 204 unsigned long sec; 205 206 if (alarm->enabled) 207 rtc_tm_to_time(&alarm->time, &sec); 208 else 209 sec = 0; 210 211 tegra_rtc_wait_while_busy(dev); 212 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); 213 dev_vdbg(dev, "alarm read back as %d\n", 214 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); 215 216 /* if successfully written and alarm is enabled ... */ 217 if (sec) { 218 tegra_rtc_alarm_irq_enable(dev, 1); 219 dev_vdbg(dev, "alarm set as %lu. %ptR\n", sec, &alarm->time); 220 } else { 221 /* disable alarm if 0 or write error. */ 222 dev_vdbg(dev, "alarm disabled\n"); 223 tegra_rtc_alarm_irq_enable(dev, 0); 224 } 225 226 return 0; 227 } 228 229 static int tegra_rtc_proc(struct device *dev, struct seq_file *seq) 230 { 231 if (!dev || !dev->driver) 232 return 0; 233 234 seq_printf(seq, "name\t\t: %s\n", dev_name(dev)); 235 236 return 0; 237 } 238 239 static irqreturn_t tegra_rtc_irq_handler(int irq, void *data) 240 { 241 struct device *dev = data; 242 struct tegra_rtc_info *info = dev_get_drvdata(dev); 243 unsigned long events = 0; 244 unsigned status; 245 unsigned long sl_irq_flags; 246 247 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 248 if (status) { 249 /* clear the interrupt masks and status on any irq. */ 250 tegra_rtc_wait_while_busy(dev); 251 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags); 252 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 253 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 254 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags); 255 } 256 257 /* check if Alarm */ 258 if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)) 259 events |= RTC_IRQF | RTC_AF; 260 261 /* check if Periodic */ 262 if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)) 263 events |= RTC_IRQF | RTC_PF; 264 265 rtc_update_irq(info->rtc_dev, 1, events); 266 267 return IRQ_HANDLED; 268 } 269 270 static const struct rtc_class_ops tegra_rtc_ops = { 271 .read_time = tegra_rtc_read_time, 272 .set_time = tegra_rtc_set_time, 273 .read_alarm = tegra_rtc_read_alarm, 274 .set_alarm = tegra_rtc_set_alarm, 275 .proc = tegra_rtc_proc, 276 .alarm_irq_enable = tegra_rtc_alarm_irq_enable, 277 }; 278 279 static const struct of_device_id tegra_rtc_dt_match[] = { 280 { .compatible = "nvidia,tegra20-rtc", }, 281 {} 282 }; 283 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match); 284 285 static int __init tegra_rtc_probe(struct platform_device *pdev) 286 { 287 struct tegra_rtc_info *info; 288 struct resource *res; 289 int ret; 290 291 info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info), 292 GFP_KERNEL); 293 if (!info) 294 return -ENOMEM; 295 296 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 297 info->rtc_base = devm_ioremap_resource(&pdev->dev, res); 298 if (IS_ERR(info->rtc_base)) 299 return PTR_ERR(info->rtc_base); 300 301 ret = platform_get_irq(pdev, 0); 302 if (ret <= 0) { 303 dev_err(&pdev->dev, "failed to get platform IRQ: %d\n", ret); 304 return ret; 305 } 306 307 info->tegra_rtc_irq = ret; 308 309 info->clk = devm_clk_get(&pdev->dev, NULL); 310 if (IS_ERR(info->clk)) 311 return PTR_ERR(info->clk); 312 313 ret = clk_prepare_enable(info->clk); 314 if (ret < 0) 315 return ret; 316 317 /* set context info. */ 318 info->pdev = pdev; 319 spin_lock_init(&info->tegra_rtc_lock); 320 321 platform_set_drvdata(pdev, info); 322 323 /* clear out the hardware. */ 324 writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0); 325 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 326 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 327 328 device_init_wakeup(&pdev->dev, 1); 329 330 info->rtc_dev = devm_rtc_device_register(&pdev->dev, 331 dev_name(&pdev->dev), &tegra_rtc_ops, 332 THIS_MODULE); 333 if (IS_ERR(info->rtc_dev)) { 334 ret = PTR_ERR(info->rtc_dev); 335 dev_err(&pdev->dev, "Unable to register device (err=%d).\n", 336 ret); 337 goto disable_clk; 338 } 339 340 ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq, 341 tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH, 342 dev_name(&pdev->dev), &pdev->dev); 343 if (ret) { 344 dev_err(&pdev->dev, 345 "Unable to request interrupt for device (err=%d).\n", 346 ret); 347 goto disable_clk; 348 } 349 350 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n"); 351 352 return 0; 353 354 disable_clk: 355 clk_disable_unprepare(info->clk); 356 return ret; 357 } 358 359 static int tegra_rtc_remove(struct platform_device *pdev) 360 { 361 struct tegra_rtc_info *info = platform_get_drvdata(pdev); 362 363 clk_disable_unprepare(info->clk); 364 365 return 0; 366 } 367 368 #ifdef CONFIG_PM_SLEEP 369 static int tegra_rtc_suspend(struct device *dev) 370 { 371 struct tegra_rtc_info *info = dev_get_drvdata(dev); 372 373 tegra_rtc_wait_while_busy(dev); 374 375 /* only use ALARM0 as a wake source. */ 376 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS); 377 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0, 378 info->rtc_base + TEGRA_RTC_REG_INTR_MASK); 379 380 dev_vdbg(dev, "alarm sec = %d\n", 381 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0)); 382 383 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n", 384 device_may_wakeup(dev), info->tegra_rtc_irq); 385 386 /* leave the alarms on as a wake source. */ 387 if (device_may_wakeup(dev)) 388 enable_irq_wake(info->tegra_rtc_irq); 389 390 return 0; 391 } 392 393 static int tegra_rtc_resume(struct device *dev) 394 { 395 struct tegra_rtc_info *info = dev_get_drvdata(dev); 396 397 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n", 398 device_may_wakeup(dev)); 399 /* alarms were left on as a wake source, turn them off. */ 400 if (device_may_wakeup(dev)) 401 disable_irq_wake(info->tegra_rtc_irq); 402 403 return 0; 404 } 405 #endif 406 407 static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume); 408 409 static void tegra_rtc_shutdown(struct platform_device *pdev) 410 { 411 dev_vdbg(&pdev->dev, "disabling interrupts.\n"); 412 tegra_rtc_alarm_irq_enable(&pdev->dev, 0); 413 } 414 415 MODULE_ALIAS("platform:tegra_rtc"); 416 static struct platform_driver tegra_rtc_driver = { 417 .remove = tegra_rtc_remove, 418 .shutdown = tegra_rtc_shutdown, 419 .driver = { 420 .name = "tegra_rtc", 421 .of_match_table = tegra_rtc_dt_match, 422 .pm = &tegra_rtc_pm_ops, 423 }, 424 }; 425 426 module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe); 427 428 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>"); 429 MODULE_DESCRIPTION("driver for Tegra internal RTC"); 430 MODULE_LICENSE("GPL"); 431