1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * An RTC driver for Allwinner A31/A23 4 * 5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> 6 * 7 * based on rtc-sunxi.c 8 * 9 * An RTC driver for Allwinner A10/A20 10 * 11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/clk/sunxi-ng.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/fs.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/rtc.h> 30 #include <linux/slab.h> 31 #include <linux/types.h> 32 33 /* Control register */ 34 #define SUN6I_LOSC_CTRL 0x0000 35 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) 36 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) 37 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) 38 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) 39 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) 40 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) 41 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) 42 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) 43 44 #define SUN6I_LOSC_CLK_PRESCAL 0x0008 45 46 /* RTC */ 47 #define SUN6I_RTC_YMD 0x0010 48 #define SUN6I_RTC_HMS 0x0014 49 50 /* Alarm 0 (counter) */ 51 #define SUN6I_ALRM_COUNTER 0x0020 52 /* This holds the remaining alarm seconds on older SoCs (current value) */ 53 #define SUN6I_ALRM_COUNTER_HMS 0x0024 54 #define SUN6I_ALRM_EN 0x0028 55 #define SUN6I_ALRM_EN_CNT_EN BIT(0) 56 #define SUN6I_ALRM_IRQ_EN 0x002c 57 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) 58 #define SUN6I_ALRM_IRQ_STA 0x0030 59 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) 60 61 /* Alarm 1 (wall clock) */ 62 #define SUN6I_ALRM1_EN 0x0044 63 #define SUN6I_ALRM1_IRQ_EN 0x0048 64 #define SUN6I_ALRM1_IRQ_STA 0x004c 65 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) 66 67 /* Alarm config */ 68 #define SUN6I_ALARM_CONFIG 0x0050 69 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) 70 71 #define SUN6I_LOSC_OUT_GATING 0x0060 72 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 73 74 /* 75 * Get date values 76 */ 77 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) 78 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) 79 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) 80 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) 81 82 /* 83 * Get time values 84 */ 85 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) 86 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) 87 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) 88 89 /* 90 * Set date values 91 */ 92 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) 93 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) 94 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) 95 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) 96 97 /* 98 * Set time values 99 */ 100 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) 101 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) 102 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) 103 104 /* 105 * The year parameter passed to the driver is usually an offset relative to 106 * the year 1900. This macro is used to convert this offset to another one 107 * relative to the minimum year allowed by the hardware. 108 * 109 * The year range is 1970 - 2033. This range is selected to match Allwinner's 110 * driver, even though it is somewhat limited. 111 */ 112 #define SUN6I_YEAR_MIN 1970 113 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) 114 115 #define SECS_PER_DAY (24 * 3600ULL) 116 117 /* 118 * There are other differences between models, including: 119 * 120 * - number of GPIO pins that can be configured to hold a certain level 121 * - crypto-key related registers (H5, H6) 122 * - boot process related (super standby, secondary processor entry address) 123 * registers (R40, H6) 124 * - SYS power domain controls (R40) 125 * - DCXO controls (H6) 126 * - RC oscillator calibration (H6) 127 * 128 * These functions are not covered by this driver. 129 */ 130 struct sun6i_rtc_clk_data { 131 unsigned long rc_osc_rate; 132 unsigned int fixed_prescaler : 16; 133 unsigned int has_prescaler : 1; 134 unsigned int has_out_clk : 1; 135 unsigned int export_iosc : 1; 136 unsigned int has_losc_en : 1; 137 unsigned int has_auto_swt : 1; 138 }; 139 140 #define RTC_LINEAR_DAY BIT(0) 141 142 struct sun6i_rtc_dev { 143 struct rtc_device *rtc; 144 const struct sun6i_rtc_clk_data *data; 145 void __iomem *base; 146 int irq; 147 time64_t alarm; 148 unsigned long flags; 149 150 struct clk_hw hw; 151 struct clk_hw *int_osc; 152 struct clk *losc; 153 struct clk *ext_losc; 154 155 spinlock_t lock; 156 }; 157 158 static struct sun6i_rtc_dev *sun6i_rtc; 159 160 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, 161 unsigned long parent_rate) 162 { 163 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 164 u32 val = 0; 165 166 val = readl(rtc->base + SUN6I_LOSC_CTRL); 167 if (val & SUN6I_LOSC_CTRL_EXT_OSC) 168 return parent_rate; 169 170 if (rtc->data->fixed_prescaler) 171 parent_rate /= rtc->data->fixed_prescaler; 172 173 if (rtc->data->has_prescaler) { 174 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); 175 val &= GENMASK(4, 0); 176 } 177 178 return parent_rate / (val + 1); 179 } 180 181 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) 182 { 183 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 184 185 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; 186 } 187 188 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) 189 { 190 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 191 unsigned long flags; 192 u32 val; 193 194 if (index > 1) 195 return -EINVAL; 196 197 spin_lock_irqsave(&rtc->lock, flags); 198 val = readl(rtc->base + SUN6I_LOSC_CTRL); 199 val &= ~SUN6I_LOSC_CTRL_EXT_OSC; 200 val |= SUN6I_LOSC_CTRL_KEY; 201 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; 202 if (rtc->data->has_losc_en) { 203 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; 204 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; 205 } 206 writel(val, rtc->base + SUN6I_LOSC_CTRL); 207 spin_unlock_irqrestore(&rtc->lock, flags); 208 209 return 0; 210 } 211 212 static const struct clk_ops sun6i_rtc_osc_ops = { 213 .recalc_rate = sun6i_rtc_osc_recalc_rate, 214 215 .get_parent = sun6i_rtc_osc_get_parent, 216 .set_parent = sun6i_rtc_osc_set_parent, 217 }; 218 219 static void __init sun6i_rtc_clk_init(struct device_node *node, 220 const struct sun6i_rtc_clk_data *data) 221 { 222 struct clk_hw_onecell_data *clk_data; 223 struct sun6i_rtc_dev *rtc; 224 struct clk_init_data init = { 225 .ops = &sun6i_rtc_osc_ops, 226 .name = "losc", 227 }; 228 const char *iosc_name = "rtc-int-osc"; 229 const char *clkout_name = "osc32k-out"; 230 const char *parents[2]; 231 u32 reg; 232 233 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); 234 if (!rtc) 235 return; 236 237 rtc->data = data; 238 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); 239 if (!clk_data) { 240 kfree(rtc); 241 return; 242 } 243 244 spin_lock_init(&rtc->lock); 245 246 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); 247 if (IS_ERR(rtc->base)) { 248 pr_crit("Can't map RTC registers"); 249 goto err; 250 } 251 252 reg = SUN6I_LOSC_CTRL_KEY; 253 if (rtc->data->has_auto_swt) { 254 /* Bypass auto-switch to int osc, on ext losc failure */ 255 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; 256 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 257 } 258 259 /* Switch to the external, more precise, oscillator, if present */ 260 if (of_get_property(node, "clocks", NULL)) { 261 reg |= SUN6I_LOSC_CTRL_EXT_OSC; 262 if (rtc->data->has_losc_en) 263 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; 264 } 265 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 266 267 /* Yes, I know, this is ugly. */ 268 sun6i_rtc = rtc; 269 270 /* Only read IOSC name from device tree if it is exported */ 271 if (rtc->data->export_iosc) 272 of_property_read_string_index(node, "clock-output-names", 2, 273 &iosc_name); 274 275 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, 276 iosc_name, 277 NULL, 0, 278 rtc->data->rc_osc_rate, 279 300000000); 280 if (IS_ERR(rtc->int_osc)) { 281 pr_crit("Couldn't register the internal oscillator\n"); 282 goto err; 283 } 284 285 parents[0] = clk_hw_get_name(rtc->int_osc); 286 /* If there is no external oscillator, this will be NULL and ... */ 287 parents[1] = of_clk_get_parent_name(node, 0); 288 289 rtc->hw.init = &init; 290 291 init.parent_names = parents; 292 /* ... number of clock parents will be 1. */ 293 init.num_parents = of_clk_get_parent_count(node) + 1; 294 of_property_read_string_index(node, "clock-output-names", 0, 295 &init.name); 296 297 rtc->losc = clk_register(NULL, &rtc->hw); 298 if (IS_ERR(rtc->losc)) { 299 pr_crit("Couldn't register the LOSC clock\n"); 300 goto err_register; 301 } 302 303 of_property_read_string_index(node, "clock-output-names", 1, 304 &clkout_name); 305 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, 306 0, rtc->base + SUN6I_LOSC_OUT_GATING, 307 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, 308 &rtc->lock); 309 if (IS_ERR(rtc->ext_losc)) { 310 pr_crit("Couldn't register the LOSC external gate\n"); 311 goto err_register; 312 } 313 314 clk_data->num = 2; 315 clk_data->hws[0] = &rtc->hw; 316 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); 317 if (rtc->data->export_iosc) { 318 clk_data->hws[2] = rtc->int_osc; 319 clk_data->num = 3; 320 } 321 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 322 return; 323 324 err_register: 325 clk_hw_unregister_fixed_rate(rtc->int_osc); 326 err: 327 kfree(clk_data); 328 } 329 330 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { 331 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 332 .has_prescaler = 1, 333 }; 334 335 static void __init sun6i_a31_rtc_clk_init(struct device_node *node) 336 { 337 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); 338 } 339 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", 340 sun6i_a31_rtc_clk_init); 341 342 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { 343 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 344 .has_prescaler = 1, 345 .has_out_clk = 1, 346 }; 347 348 static void __init sun8i_a23_rtc_clk_init(struct device_node *node) 349 { 350 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); 351 } 352 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", 353 sun8i_a23_rtc_clk_init); 354 355 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { 356 .rc_osc_rate = 16000000, 357 .fixed_prescaler = 32, 358 .has_prescaler = 1, 359 .has_out_clk = 1, 360 .export_iosc = 1, 361 }; 362 363 static void __init sun8i_h3_rtc_clk_init(struct device_node *node) 364 { 365 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); 366 } 367 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", 368 sun8i_h3_rtc_clk_init); 369 /* As far as we are concerned, clocks for H5 are the same as H3 */ 370 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", 371 sun8i_h3_rtc_clk_init); 372 373 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { 374 .rc_osc_rate = 16000000, 375 .fixed_prescaler = 32, 376 .has_prescaler = 1, 377 .has_out_clk = 1, 378 .export_iosc = 1, 379 .has_losc_en = 1, 380 .has_auto_swt = 1, 381 }; 382 383 static void __init sun50i_h6_rtc_clk_init(struct device_node *node) 384 { 385 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); 386 } 387 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", 388 sun50i_h6_rtc_clk_init); 389 390 /* 391 * The R40 user manual is self-conflicting on whether the prescaler is 392 * fixed or configurable. The clock diagram shows it as fixed, but there 393 * is also a configurable divider in the RTC block. 394 */ 395 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = { 396 .rc_osc_rate = 16000000, 397 .fixed_prescaler = 512, 398 }; 399 static void __init sun8i_r40_rtc_clk_init(struct device_node *node) 400 { 401 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data); 402 } 403 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", 404 sun8i_r40_rtc_clk_init); 405 406 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { 407 .rc_osc_rate = 32000, 408 .has_out_clk = 1, 409 }; 410 411 static void __init sun8i_v3_rtc_clk_init(struct device_node *node) 412 { 413 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); 414 } 415 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", 416 sun8i_v3_rtc_clk_init); 417 418 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) 419 { 420 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; 421 irqreturn_t ret = IRQ_NONE; 422 u32 val; 423 424 spin_lock(&chip->lock); 425 val = readl(chip->base + SUN6I_ALRM_IRQ_STA); 426 427 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { 428 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; 429 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); 430 431 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); 432 433 ret = IRQ_HANDLED; 434 } 435 spin_unlock(&chip->lock); 436 437 return ret; 438 } 439 440 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) 441 { 442 u32 alrm_val = 0; 443 u32 alrm_irq_val = 0; 444 u32 alrm_wake_val = 0; 445 unsigned long flags; 446 447 if (to) { 448 alrm_val = SUN6I_ALRM_EN_CNT_EN; 449 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; 450 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; 451 } else { 452 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 453 chip->base + SUN6I_ALRM_IRQ_STA); 454 } 455 456 spin_lock_irqsave(&chip->lock, flags); 457 writel(alrm_val, chip->base + SUN6I_ALRM_EN); 458 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); 459 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); 460 spin_unlock_irqrestore(&chip->lock, flags); 461 } 462 463 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 464 { 465 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 466 u32 date, time; 467 468 /* 469 * read again in case it changes 470 */ 471 do { 472 date = readl(chip->base + SUN6I_RTC_YMD); 473 time = readl(chip->base + SUN6I_RTC_HMS); 474 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || 475 (time != readl(chip->base + SUN6I_RTC_HMS))); 476 477 if (chip->flags & RTC_LINEAR_DAY) { 478 /* 479 * Newer chips store a linear day number, the manual 480 * does not mandate any epoch base. The BSP driver uses 481 * the UNIX epoch, let's just copy that, as it's the 482 * easiest anyway. 483 */ 484 rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm); 485 } else { 486 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); 487 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1; 488 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); 489 490 /* 491 * switch from (data_year->min)-relative offset to 492 * a (1900)-relative one 493 */ 494 rtc_tm->tm_year += SUN6I_YEAR_OFF; 495 } 496 497 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); 498 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); 499 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); 500 501 return 0; 502 } 503 504 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 505 { 506 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 507 unsigned long flags; 508 u32 alrm_st; 509 u32 alrm_en; 510 511 spin_lock_irqsave(&chip->lock, flags); 512 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); 513 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); 514 spin_unlock_irqrestore(&chip->lock, flags); 515 516 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); 517 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); 518 rtc_time64_to_tm(chip->alarm, &wkalrm->time); 519 520 return 0; 521 } 522 523 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 524 { 525 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 526 struct rtc_time *alrm_tm = &wkalrm->time; 527 struct rtc_time tm_now; 528 time64_t time_set; 529 u32 counter_val, counter_val_hms; 530 int ret; 531 532 time_set = rtc_tm_to_time64(alrm_tm); 533 534 if (chip->flags & RTC_LINEAR_DAY) { 535 /* 536 * The alarm registers hold the actual alarm time, encoded 537 * in the same way (linear day + HMS) as the current time. 538 */ 539 counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) | 540 SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) | 541 SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour); 542 /* The division will cut off the H:M:S part of alrm_tm. */ 543 counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY); 544 } else { 545 /* The alarm register holds the number of seconds left. */ 546 time64_t time_now; 547 548 ret = sun6i_rtc_gettime(dev, &tm_now); 549 if (ret < 0) { 550 dev_err(dev, "Error in getting time\n"); 551 return -EINVAL; 552 } 553 554 time_now = rtc_tm_to_time64(&tm_now); 555 if (time_set <= time_now) { 556 dev_err(dev, "Date to set in the past\n"); 557 return -EINVAL; 558 } 559 if ((time_set - time_now) > U32_MAX) { 560 dev_err(dev, "Date too far in the future\n"); 561 return -EINVAL; 562 } 563 564 counter_val = time_set - time_now; 565 } 566 567 sun6i_rtc_setaie(0, chip); 568 writel(0, chip->base + SUN6I_ALRM_COUNTER); 569 if (chip->flags & RTC_LINEAR_DAY) 570 writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS); 571 usleep_range(100, 300); 572 573 writel(counter_val, chip->base + SUN6I_ALRM_COUNTER); 574 if (chip->flags & RTC_LINEAR_DAY) 575 writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS); 576 chip->alarm = time_set; 577 578 sun6i_rtc_setaie(wkalrm->enabled, chip); 579 580 return 0; 581 } 582 583 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, 584 unsigned int mask, unsigned int ms_timeout) 585 { 586 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); 587 u32 reg; 588 589 do { 590 reg = readl(chip->base + offset); 591 reg &= mask; 592 593 if (!reg) 594 return 0; 595 596 } while (time_before(jiffies, timeout)); 597 598 return -ETIMEDOUT; 599 } 600 601 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) 602 { 603 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 604 u32 date = 0; 605 u32 time = 0; 606 607 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | 608 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | 609 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); 610 611 if (chip->flags & RTC_LINEAR_DAY) { 612 /* The division will cut off the H:M:S part of rtc_tm. */ 613 date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY); 614 } else { 615 rtc_tm->tm_year -= SUN6I_YEAR_OFF; 616 rtc_tm->tm_mon += 1; 617 618 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | 619 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | 620 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); 621 622 if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) 623 date |= SUN6I_LEAP_SET_VALUE(1); 624 } 625 626 /* Check whether registers are writable */ 627 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 628 SUN6I_LOSC_CTRL_ACC_MASK, 50)) { 629 dev_err(dev, "rtc is still busy.\n"); 630 return -EBUSY; 631 } 632 633 writel(time, chip->base + SUN6I_RTC_HMS); 634 635 /* 636 * After writing the RTC HH-MM-SS register, the 637 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not 638 * be cleared until the real writing operation is finished 639 */ 640 641 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 642 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { 643 dev_err(dev, "Failed to set rtc time.\n"); 644 return -ETIMEDOUT; 645 } 646 647 writel(date, chip->base + SUN6I_RTC_YMD); 648 649 /* 650 * After writing the RTC YY-MM-DD register, the 651 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not 652 * be cleared until the real writing operation is finished 653 */ 654 655 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 656 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { 657 dev_err(dev, "Failed to set rtc time.\n"); 658 return -ETIMEDOUT; 659 } 660 661 return 0; 662 } 663 664 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 665 { 666 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 667 668 if (!enabled) 669 sun6i_rtc_setaie(enabled, chip); 670 671 return 0; 672 } 673 674 static const struct rtc_class_ops sun6i_rtc_ops = { 675 .read_time = sun6i_rtc_gettime, 676 .set_time = sun6i_rtc_settime, 677 .read_alarm = sun6i_rtc_getalarm, 678 .set_alarm = sun6i_rtc_setalarm, 679 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable 680 }; 681 682 #ifdef CONFIG_PM_SLEEP 683 /* Enable IRQ wake on suspend, to wake up from RTC. */ 684 static int sun6i_rtc_suspend(struct device *dev) 685 { 686 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 687 688 if (device_may_wakeup(dev)) 689 enable_irq_wake(chip->irq); 690 691 return 0; 692 } 693 694 /* Disable IRQ wake on resume. */ 695 static int sun6i_rtc_resume(struct device *dev) 696 { 697 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 698 699 if (device_may_wakeup(dev)) 700 disable_irq_wake(chip->irq); 701 702 return 0; 703 } 704 #endif 705 706 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, 707 sun6i_rtc_suspend, sun6i_rtc_resume); 708 709 static void sun6i_rtc_bus_clk_cleanup(void *data) 710 { 711 struct clk *bus_clk = data; 712 713 clk_disable_unprepare(bus_clk); 714 } 715 716 static int sun6i_rtc_probe(struct platform_device *pdev) 717 { 718 struct sun6i_rtc_dev *chip = sun6i_rtc; 719 struct device *dev = &pdev->dev; 720 struct clk *bus_clk; 721 int ret; 722 723 bus_clk = devm_clk_get_optional(dev, "bus"); 724 if (IS_ERR(bus_clk)) 725 return PTR_ERR(bus_clk); 726 727 if (bus_clk) { 728 ret = clk_prepare_enable(bus_clk); 729 if (ret) 730 return ret; 731 732 ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup, 733 bus_clk); 734 if (ret) 735 return ret; 736 } 737 738 if (!chip) { 739 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 740 if (!chip) 741 return -ENOMEM; 742 743 spin_lock_init(&chip->lock); 744 745 chip->base = devm_platform_ioremap_resource(pdev, 0); 746 if (IS_ERR(chip->base)) 747 return PTR_ERR(chip->base); 748 749 if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) { 750 ret = sun6i_rtc_ccu_probe(dev, chip->base); 751 if (ret) 752 return ret; 753 } 754 } 755 756 platform_set_drvdata(pdev, chip); 757 758 chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev); 759 760 chip->irq = platform_get_irq(pdev, 0); 761 if (chip->irq < 0) 762 return chip->irq; 763 764 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, 765 0, dev_name(&pdev->dev), chip); 766 if (ret) { 767 dev_err(&pdev->dev, "Could not request IRQ\n"); 768 return ret; 769 } 770 771 /* clear the alarm counter value */ 772 writel(0, chip->base + SUN6I_ALRM_COUNTER); 773 774 /* disable counter alarm */ 775 writel(0, chip->base + SUN6I_ALRM_EN); 776 777 /* disable counter alarm interrupt */ 778 writel(0, chip->base + SUN6I_ALRM_IRQ_EN); 779 780 /* disable week alarm */ 781 writel(0, chip->base + SUN6I_ALRM1_EN); 782 783 /* disable week alarm interrupt */ 784 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); 785 786 /* clear counter alarm pending interrupts */ 787 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 788 chip->base + SUN6I_ALRM_IRQ_STA); 789 790 /* clear week alarm pending interrupts */ 791 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, 792 chip->base + SUN6I_ALRM1_IRQ_STA); 793 794 /* disable alarm wakeup */ 795 writel(0, chip->base + SUN6I_ALARM_CONFIG); 796 797 clk_prepare_enable(chip->losc); 798 799 device_init_wakeup(&pdev->dev, 1); 800 801 chip->rtc = devm_rtc_allocate_device(&pdev->dev); 802 if (IS_ERR(chip->rtc)) 803 return PTR_ERR(chip->rtc); 804 805 chip->rtc->ops = &sun6i_rtc_ops; 806 if (chip->flags & RTC_LINEAR_DAY) 807 chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1; 808 else 809 chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ 810 811 ret = devm_rtc_register_device(chip->rtc); 812 if (ret) 813 return ret; 814 815 dev_info(&pdev->dev, "RTC enabled\n"); 816 817 return 0; 818 } 819 820 /* 821 * As far as RTC functionality goes, all models are the same. The 822 * datasheets claim that different models have different number of 823 * registers available for non-volatile storage, but experiments show 824 * that all SoCs have 16 registers available for this purpose. 825 */ 826 static const struct of_device_id sun6i_rtc_dt_ids[] = { 827 { .compatible = "allwinner,sun6i-a31-rtc" }, 828 { .compatible = "allwinner,sun8i-a23-rtc" }, 829 { .compatible = "allwinner,sun8i-h3-rtc" }, 830 { .compatible = "allwinner,sun8i-r40-rtc" }, 831 { .compatible = "allwinner,sun8i-v3-rtc" }, 832 { .compatible = "allwinner,sun50i-h5-rtc" }, 833 { .compatible = "allwinner,sun50i-h6-rtc" }, 834 { .compatible = "allwinner,sun50i-h616-rtc", 835 .data = (void *)RTC_LINEAR_DAY }, 836 { /* sentinel */ }, 837 }; 838 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); 839 840 static struct platform_driver sun6i_rtc_driver = { 841 .probe = sun6i_rtc_probe, 842 .driver = { 843 .name = "sun6i-rtc", 844 .of_match_table = sun6i_rtc_dt_ids, 845 .pm = &sun6i_rtc_pm_ops, 846 }, 847 }; 848 builtin_platform_driver(sun6i_rtc_driver); 849