1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * An RTC driver for Allwinner A31/A23 4 * 5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> 6 * 7 * based on rtc-sunxi.c 8 * 9 * An RTC driver for Allwinner A10/A20 10 * 11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/fs.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/rtc.h> 29 #include <linux/slab.h> 30 #include <linux/types.h> 31 32 /* Control register */ 33 #define SUN6I_LOSC_CTRL 0x0000 34 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) 35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) 36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) 37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) 38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) 39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) 40 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) 41 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) 42 43 #define SUN6I_LOSC_CLK_PRESCAL 0x0008 44 45 /* RTC */ 46 #define SUN6I_RTC_YMD 0x0010 47 #define SUN6I_RTC_HMS 0x0014 48 49 /* Alarm 0 (counter) */ 50 #define SUN6I_ALRM_COUNTER 0x0020 51 #define SUN6I_ALRM_CUR_VAL 0x0024 52 #define SUN6I_ALRM_EN 0x0028 53 #define SUN6I_ALRM_EN_CNT_EN BIT(0) 54 #define SUN6I_ALRM_IRQ_EN 0x002c 55 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) 56 #define SUN6I_ALRM_IRQ_STA 0x0030 57 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) 58 59 /* Alarm 1 (wall clock) */ 60 #define SUN6I_ALRM1_EN 0x0044 61 #define SUN6I_ALRM1_IRQ_EN 0x0048 62 #define SUN6I_ALRM1_IRQ_STA 0x004c 63 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) 64 65 /* Alarm config */ 66 #define SUN6I_ALARM_CONFIG 0x0050 67 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) 68 69 #define SUN6I_LOSC_OUT_GATING 0x0060 70 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 71 72 /* 73 * Get date values 74 */ 75 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) 76 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) 77 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) 78 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) 79 80 /* 81 * Get time values 82 */ 83 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) 84 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) 85 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) 86 87 /* 88 * Set date values 89 */ 90 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) 91 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) 92 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) 93 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) 94 95 /* 96 * Set time values 97 */ 98 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) 99 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) 100 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) 101 102 /* 103 * The year parameter passed to the driver is usually an offset relative to 104 * the year 1900. This macro is used to convert this offset to another one 105 * relative to the minimum year allowed by the hardware. 106 * 107 * The year range is 1970 - 2033. This range is selected to match Allwinner's 108 * driver, even though it is somewhat limited. 109 */ 110 #define SUN6I_YEAR_MIN 1970 111 #define SUN6I_YEAR_MAX 2033 112 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) 113 114 /* 115 * There are other differences between models, including: 116 * 117 * - number of GPIO pins that can be configured to hold a certain level 118 * - crypto-key related registers (H5, H6) 119 * - boot process related (super standby, secondary processor entry address) 120 * registers (R40, H6) 121 * - SYS power domain controls (R40) 122 * - DCXO controls (H6) 123 * - RC oscillator calibration (H6) 124 * 125 * These functions are not covered by this driver. 126 */ 127 struct sun6i_rtc_clk_data { 128 unsigned long rc_osc_rate; 129 unsigned int fixed_prescaler : 16; 130 unsigned int has_prescaler : 1; 131 unsigned int has_out_clk : 1; 132 unsigned int export_iosc : 1; 133 unsigned int has_losc_en : 1; 134 unsigned int has_auto_swt : 1; 135 }; 136 137 struct sun6i_rtc_dev { 138 struct rtc_device *rtc; 139 struct device *dev; 140 const struct sun6i_rtc_clk_data *data; 141 void __iomem *base; 142 int irq; 143 unsigned long alarm; 144 145 struct clk_hw hw; 146 struct clk_hw *int_osc; 147 struct clk *losc; 148 struct clk *ext_losc; 149 150 spinlock_t lock; 151 }; 152 153 static struct sun6i_rtc_dev *sun6i_rtc; 154 155 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, 156 unsigned long parent_rate) 157 { 158 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 159 u32 val = 0; 160 161 val = readl(rtc->base + SUN6I_LOSC_CTRL); 162 if (val & SUN6I_LOSC_CTRL_EXT_OSC) 163 return parent_rate; 164 165 if (rtc->data->fixed_prescaler) 166 parent_rate /= rtc->data->fixed_prescaler; 167 168 if (rtc->data->has_prescaler) { 169 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); 170 val &= GENMASK(4, 0); 171 } 172 173 return parent_rate / (val + 1); 174 } 175 176 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) 177 { 178 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 179 180 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; 181 } 182 183 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) 184 { 185 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 186 unsigned long flags; 187 u32 val; 188 189 if (index > 1) 190 return -EINVAL; 191 192 spin_lock_irqsave(&rtc->lock, flags); 193 val = readl(rtc->base + SUN6I_LOSC_CTRL); 194 val &= ~SUN6I_LOSC_CTRL_EXT_OSC; 195 val |= SUN6I_LOSC_CTRL_KEY; 196 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; 197 if (rtc->data->has_losc_en) { 198 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; 199 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; 200 } 201 writel(val, rtc->base + SUN6I_LOSC_CTRL); 202 spin_unlock_irqrestore(&rtc->lock, flags); 203 204 return 0; 205 } 206 207 static const struct clk_ops sun6i_rtc_osc_ops = { 208 .recalc_rate = sun6i_rtc_osc_recalc_rate, 209 210 .get_parent = sun6i_rtc_osc_get_parent, 211 .set_parent = sun6i_rtc_osc_set_parent, 212 }; 213 214 static void __init sun6i_rtc_clk_init(struct device_node *node, 215 const struct sun6i_rtc_clk_data *data) 216 { 217 struct clk_hw_onecell_data *clk_data; 218 struct sun6i_rtc_dev *rtc; 219 struct clk_init_data init = { 220 .ops = &sun6i_rtc_osc_ops, 221 .name = "losc", 222 }; 223 const char *iosc_name = "rtc-int-osc"; 224 const char *clkout_name = "osc32k-out"; 225 const char *parents[2]; 226 u32 reg; 227 228 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); 229 if (!rtc) 230 return; 231 232 rtc->data = data; 233 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); 234 if (!clk_data) { 235 kfree(rtc); 236 return; 237 } 238 239 spin_lock_init(&rtc->lock); 240 241 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); 242 if (IS_ERR(rtc->base)) { 243 pr_crit("Can't map RTC registers"); 244 goto err; 245 } 246 247 reg = SUN6I_LOSC_CTRL_KEY; 248 if (rtc->data->has_auto_swt) { 249 /* Bypass auto-switch to int osc, on ext losc failure */ 250 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; 251 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 252 } 253 254 /* Switch to the external, more precise, oscillator */ 255 reg |= SUN6I_LOSC_CTRL_EXT_OSC; 256 if (rtc->data->has_losc_en) 257 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; 258 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 259 260 /* Yes, I know, this is ugly. */ 261 sun6i_rtc = rtc; 262 263 /* Deal with old DTs */ 264 if (!of_get_property(node, "clocks", NULL)) 265 goto err; 266 267 /* Only read IOSC name from device tree if it is exported */ 268 if (rtc->data->export_iosc) 269 of_property_read_string_index(node, "clock-output-names", 2, 270 &iosc_name); 271 272 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, 273 iosc_name, 274 NULL, 0, 275 rtc->data->rc_osc_rate, 276 300000000); 277 if (IS_ERR(rtc->int_osc)) { 278 pr_crit("Couldn't register the internal oscillator\n"); 279 return; 280 } 281 282 parents[0] = clk_hw_get_name(rtc->int_osc); 283 parents[1] = of_clk_get_parent_name(node, 0); 284 285 rtc->hw.init = &init; 286 287 init.parent_names = parents; 288 init.num_parents = of_clk_get_parent_count(node) + 1; 289 of_property_read_string_index(node, "clock-output-names", 0, 290 &init.name); 291 292 rtc->losc = clk_register(NULL, &rtc->hw); 293 if (IS_ERR(rtc->losc)) { 294 pr_crit("Couldn't register the LOSC clock\n"); 295 return; 296 } 297 298 of_property_read_string_index(node, "clock-output-names", 1, 299 &clkout_name); 300 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, 301 0, rtc->base + SUN6I_LOSC_OUT_GATING, 302 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, 303 &rtc->lock); 304 if (IS_ERR(rtc->ext_losc)) { 305 pr_crit("Couldn't register the LOSC external gate\n"); 306 return; 307 } 308 309 clk_data->num = 2; 310 clk_data->hws[0] = &rtc->hw; 311 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); 312 if (rtc->data->export_iosc) { 313 clk_data->hws[2] = rtc->int_osc; 314 clk_data->num = 3; 315 } 316 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 317 return; 318 319 err: 320 kfree(clk_data); 321 } 322 323 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { 324 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 325 .has_prescaler = 1, 326 }; 327 328 static void __init sun6i_a31_rtc_clk_init(struct device_node *node) 329 { 330 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); 331 } 332 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", 333 sun6i_a31_rtc_clk_init); 334 335 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { 336 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 337 .has_prescaler = 1, 338 .has_out_clk = 1, 339 }; 340 341 static void __init sun8i_a23_rtc_clk_init(struct device_node *node) 342 { 343 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); 344 } 345 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", 346 sun8i_a23_rtc_clk_init); 347 348 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { 349 .rc_osc_rate = 16000000, 350 .fixed_prescaler = 32, 351 .has_prescaler = 1, 352 .has_out_clk = 1, 353 .export_iosc = 1, 354 }; 355 356 static void __init sun8i_h3_rtc_clk_init(struct device_node *node) 357 { 358 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); 359 } 360 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", 361 sun8i_h3_rtc_clk_init); 362 /* As far as we are concerned, clocks for H5 are the same as H3 */ 363 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", 364 sun8i_h3_rtc_clk_init); 365 366 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { 367 .rc_osc_rate = 16000000, 368 .fixed_prescaler = 32, 369 .has_prescaler = 1, 370 .has_out_clk = 1, 371 .export_iosc = 1, 372 .has_losc_en = 1, 373 .has_auto_swt = 1, 374 }; 375 376 static void __init sun50i_h6_rtc_clk_init(struct device_node *node) 377 { 378 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); 379 } 380 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", 381 sun50i_h6_rtc_clk_init); 382 383 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { 384 .rc_osc_rate = 32000, 385 .has_out_clk = 1, 386 }; 387 388 static void __init sun8i_v3_rtc_clk_init(struct device_node *node) 389 { 390 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); 391 } 392 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", 393 sun8i_v3_rtc_clk_init); 394 395 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) 396 { 397 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; 398 irqreturn_t ret = IRQ_NONE; 399 u32 val; 400 401 spin_lock(&chip->lock); 402 val = readl(chip->base + SUN6I_ALRM_IRQ_STA); 403 404 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { 405 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; 406 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); 407 408 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); 409 410 ret = IRQ_HANDLED; 411 } 412 spin_unlock(&chip->lock); 413 414 return ret; 415 } 416 417 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) 418 { 419 u32 alrm_val = 0; 420 u32 alrm_irq_val = 0; 421 u32 alrm_wake_val = 0; 422 unsigned long flags; 423 424 if (to) { 425 alrm_val = SUN6I_ALRM_EN_CNT_EN; 426 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; 427 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; 428 } else { 429 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 430 chip->base + SUN6I_ALRM_IRQ_STA); 431 } 432 433 spin_lock_irqsave(&chip->lock, flags); 434 writel(alrm_val, chip->base + SUN6I_ALRM_EN); 435 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); 436 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); 437 spin_unlock_irqrestore(&chip->lock, flags); 438 } 439 440 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 441 { 442 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 443 u32 date, time; 444 445 /* 446 * read again in case it changes 447 */ 448 do { 449 date = readl(chip->base + SUN6I_RTC_YMD); 450 time = readl(chip->base + SUN6I_RTC_HMS); 451 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || 452 (time != readl(chip->base + SUN6I_RTC_HMS))); 453 454 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); 455 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); 456 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); 457 458 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); 459 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date); 460 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); 461 462 rtc_tm->tm_mon -= 1; 463 464 /* 465 * switch from (data_year->min)-relative offset to 466 * a (1900)-relative one 467 */ 468 rtc_tm->tm_year += SUN6I_YEAR_OFF; 469 470 return 0; 471 } 472 473 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 474 { 475 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 476 unsigned long flags; 477 u32 alrm_st; 478 u32 alrm_en; 479 480 spin_lock_irqsave(&chip->lock, flags); 481 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); 482 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); 483 spin_unlock_irqrestore(&chip->lock, flags); 484 485 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); 486 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); 487 rtc_time_to_tm(chip->alarm, &wkalrm->time); 488 489 return 0; 490 } 491 492 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 493 { 494 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 495 struct rtc_time *alrm_tm = &wkalrm->time; 496 struct rtc_time tm_now; 497 unsigned long time_now = 0; 498 unsigned long time_set = 0; 499 unsigned long time_gap = 0; 500 int ret = 0; 501 502 ret = sun6i_rtc_gettime(dev, &tm_now); 503 if (ret < 0) { 504 dev_err(dev, "Error in getting time\n"); 505 return -EINVAL; 506 } 507 508 rtc_tm_to_time(alrm_tm, &time_set); 509 rtc_tm_to_time(&tm_now, &time_now); 510 if (time_set <= time_now) { 511 dev_err(dev, "Date to set in the past\n"); 512 return -EINVAL; 513 } 514 515 time_gap = time_set - time_now; 516 517 if (time_gap > U32_MAX) { 518 dev_err(dev, "Date too far in the future\n"); 519 return -EINVAL; 520 } 521 522 sun6i_rtc_setaie(0, chip); 523 writel(0, chip->base + SUN6I_ALRM_COUNTER); 524 usleep_range(100, 300); 525 526 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); 527 chip->alarm = time_set; 528 529 sun6i_rtc_setaie(wkalrm->enabled, chip); 530 531 return 0; 532 } 533 534 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, 535 unsigned int mask, unsigned int ms_timeout) 536 { 537 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); 538 u32 reg; 539 540 do { 541 reg = readl(chip->base + offset); 542 reg &= mask; 543 544 if (!reg) 545 return 0; 546 547 } while (time_before(jiffies, timeout)); 548 549 return -ETIMEDOUT; 550 } 551 552 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) 553 { 554 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 555 u32 date = 0; 556 u32 time = 0; 557 int year; 558 559 year = rtc_tm->tm_year + 1900; 560 if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) { 561 dev_err(dev, "rtc only supports year in range %d - %d\n", 562 SUN6I_YEAR_MIN, SUN6I_YEAR_MAX); 563 return -EINVAL; 564 } 565 566 rtc_tm->tm_year -= SUN6I_YEAR_OFF; 567 rtc_tm->tm_mon += 1; 568 569 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | 570 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | 571 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); 572 573 if (is_leap_year(year)) 574 date |= SUN6I_LEAP_SET_VALUE(1); 575 576 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | 577 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | 578 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); 579 580 /* Check whether registers are writable */ 581 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 582 SUN6I_LOSC_CTRL_ACC_MASK, 50)) { 583 dev_err(dev, "rtc is still busy.\n"); 584 return -EBUSY; 585 } 586 587 writel(time, chip->base + SUN6I_RTC_HMS); 588 589 /* 590 * After writing the RTC HH-MM-SS register, the 591 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not 592 * be cleared until the real writing operation is finished 593 */ 594 595 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 596 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { 597 dev_err(dev, "Failed to set rtc time.\n"); 598 return -ETIMEDOUT; 599 } 600 601 writel(date, chip->base + SUN6I_RTC_YMD); 602 603 /* 604 * After writing the RTC YY-MM-DD register, the 605 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not 606 * be cleared until the real writing operation is finished 607 */ 608 609 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 610 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { 611 dev_err(dev, "Failed to set rtc time.\n"); 612 return -ETIMEDOUT; 613 } 614 615 return 0; 616 } 617 618 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 619 { 620 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 621 622 if (!enabled) 623 sun6i_rtc_setaie(enabled, chip); 624 625 return 0; 626 } 627 628 static const struct rtc_class_ops sun6i_rtc_ops = { 629 .read_time = sun6i_rtc_gettime, 630 .set_time = sun6i_rtc_settime, 631 .read_alarm = sun6i_rtc_getalarm, 632 .set_alarm = sun6i_rtc_setalarm, 633 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable 634 }; 635 636 #ifdef CONFIG_PM_SLEEP 637 /* Enable IRQ wake on suspend, to wake up from RTC. */ 638 static int sun6i_rtc_suspend(struct device *dev) 639 { 640 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 641 642 if (device_may_wakeup(dev)) 643 enable_irq_wake(chip->irq); 644 645 return 0; 646 } 647 648 /* Disable IRQ wake on resume. */ 649 static int sun6i_rtc_resume(struct device *dev) 650 { 651 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 652 653 if (device_may_wakeup(dev)) 654 disable_irq_wake(chip->irq); 655 656 return 0; 657 } 658 #endif 659 660 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, 661 sun6i_rtc_suspend, sun6i_rtc_resume); 662 663 static int sun6i_rtc_probe(struct platform_device *pdev) 664 { 665 struct sun6i_rtc_dev *chip = sun6i_rtc; 666 int ret; 667 668 if (!chip) 669 return -ENODEV; 670 671 platform_set_drvdata(pdev, chip); 672 chip->dev = &pdev->dev; 673 674 chip->irq = platform_get_irq(pdev, 0); 675 if (chip->irq < 0) 676 return chip->irq; 677 678 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, 679 0, dev_name(&pdev->dev), chip); 680 if (ret) { 681 dev_err(&pdev->dev, "Could not request IRQ\n"); 682 return ret; 683 } 684 685 /* clear the alarm counter value */ 686 writel(0, chip->base + SUN6I_ALRM_COUNTER); 687 688 /* disable counter alarm */ 689 writel(0, chip->base + SUN6I_ALRM_EN); 690 691 /* disable counter alarm interrupt */ 692 writel(0, chip->base + SUN6I_ALRM_IRQ_EN); 693 694 /* disable week alarm */ 695 writel(0, chip->base + SUN6I_ALRM1_EN); 696 697 /* disable week alarm interrupt */ 698 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); 699 700 /* clear counter alarm pending interrupts */ 701 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 702 chip->base + SUN6I_ALRM_IRQ_STA); 703 704 /* clear week alarm pending interrupts */ 705 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, 706 chip->base + SUN6I_ALRM1_IRQ_STA); 707 708 /* disable alarm wakeup */ 709 writel(0, chip->base + SUN6I_ALARM_CONFIG); 710 711 clk_prepare_enable(chip->losc); 712 713 device_init_wakeup(&pdev->dev, 1); 714 715 chip->rtc = devm_rtc_device_register(&pdev->dev, "rtc-sun6i", 716 &sun6i_rtc_ops, THIS_MODULE); 717 if (IS_ERR(chip->rtc)) { 718 dev_err(&pdev->dev, "unable to register device\n"); 719 return PTR_ERR(chip->rtc); 720 } 721 722 dev_info(&pdev->dev, "RTC enabled\n"); 723 724 return 0; 725 } 726 727 /* 728 * As far as RTC functionality goes, all models are the same. The 729 * datasheets claim that different models have different number of 730 * registers available for non-volatile storage, but experiments show 731 * that all SoCs have 16 registers available for this purpose. 732 */ 733 static const struct of_device_id sun6i_rtc_dt_ids[] = { 734 { .compatible = "allwinner,sun6i-a31-rtc" }, 735 { .compatible = "allwinner,sun8i-a23-rtc" }, 736 { .compatible = "allwinner,sun8i-h3-rtc" }, 737 { .compatible = "allwinner,sun8i-r40-rtc" }, 738 { .compatible = "allwinner,sun8i-v3-rtc" }, 739 { .compatible = "allwinner,sun50i-h5-rtc" }, 740 { .compatible = "allwinner,sun50i-h6-rtc" }, 741 { /* sentinel */ }, 742 }; 743 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); 744 745 static struct platform_driver sun6i_rtc_driver = { 746 .probe = sun6i_rtc_probe, 747 .driver = { 748 .name = "sun6i-rtc", 749 .of_match_table = sun6i_rtc_dt_ids, 750 .pm = &sun6i_rtc_pm_ops, 751 }, 752 }; 753 builtin_platform_driver(sun6i_rtc_driver); 754