1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * An RTC driver for Allwinner A31/A23 4 * 5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> 6 * 7 * based on rtc-sunxi.c 8 * 9 * An RTC driver for Allwinner A10/A20 10 * 11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/clk/sunxi-ng.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/fs.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/rtc.h> 30 #include <linux/slab.h> 31 #include <linux/types.h> 32 33 /* Control register */ 34 #define SUN6I_LOSC_CTRL 0x0000 35 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) 36 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) 37 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) 38 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) 39 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) 40 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) 41 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) 42 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) 43 44 #define SUN6I_LOSC_CLK_PRESCAL 0x0008 45 46 /* RTC */ 47 #define SUN6I_RTC_YMD 0x0010 48 #define SUN6I_RTC_HMS 0x0014 49 50 /* Alarm 0 (counter) */ 51 #define SUN6I_ALRM_COUNTER 0x0020 52 /* This holds the remaining alarm seconds on older SoCs (current value) */ 53 #define SUN6I_ALRM_COUNTER_HMS 0x0024 54 #define SUN6I_ALRM_EN 0x0028 55 #define SUN6I_ALRM_EN_CNT_EN BIT(0) 56 #define SUN6I_ALRM_IRQ_EN 0x002c 57 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) 58 #define SUN6I_ALRM_IRQ_STA 0x0030 59 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) 60 61 /* Alarm 1 (wall clock) */ 62 #define SUN6I_ALRM1_EN 0x0044 63 #define SUN6I_ALRM1_IRQ_EN 0x0048 64 #define SUN6I_ALRM1_IRQ_STA 0x004c 65 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) 66 67 /* Alarm config */ 68 #define SUN6I_ALARM_CONFIG 0x0050 69 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) 70 71 #define SUN6I_LOSC_OUT_GATING 0x0060 72 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 73 74 /* 75 * Get date values 76 */ 77 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) 78 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) 79 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) 80 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) 81 82 /* 83 * Get time values 84 */ 85 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) 86 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) 87 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) 88 89 /* 90 * Set date values 91 */ 92 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) 93 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) 94 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) 95 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) 96 97 /* 98 * Set time values 99 */ 100 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) 101 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) 102 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) 103 104 /* 105 * The year parameter passed to the driver is usually an offset relative to 106 * the year 1900. This macro is used to convert this offset to another one 107 * relative to the minimum year allowed by the hardware. 108 * 109 * The year range is 1970 - 2033. This range is selected to match Allwinner's 110 * driver, even though it is somewhat limited. 111 */ 112 #define SUN6I_YEAR_MIN 1970 113 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) 114 115 #define SECS_PER_DAY (24 * 3600ULL) 116 117 /* 118 * There are other differences between models, including: 119 * 120 * - number of GPIO pins that can be configured to hold a certain level 121 * - crypto-key related registers (H5, H6) 122 * - boot process related (super standby, secondary processor entry address) 123 * registers (R40, H6) 124 * - SYS power domain controls (R40) 125 * - DCXO controls (H6) 126 * - RC oscillator calibration (H6) 127 * 128 * These functions are not covered by this driver. 129 */ 130 struct sun6i_rtc_clk_data { 131 unsigned long rc_osc_rate; 132 unsigned int fixed_prescaler : 16; 133 unsigned int has_prescaler : 1; 134 unsigned int has_out_clk : 1; 135 unsigned int export_iosc : 1; 136 unsigned int has_losc_en : 1; 137 unsigned int has_auto_swt : 1; 138 }; 139 140 #define RTC_LINEAR_DAY BIT(0) 141 142 struct sun6i_rtc_dev { 143 struct rtc_device *rtc; 144 const struct sun6i_rtc_clk_data *data; 145 void __iomem *base; 146 int irq; 147 time64_t alarm; 148 unsigned long flags; 149 150 struct clk_hw hw; 151 struct clk_hw *int_osc; 152 struct clk *losc; 153 struct clk *ext_losc; 154 155 spinlock_t lock; 156 }; 157 158 static struct sun6i_rtc_dev *sun6i_rtc; 159 160 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, 161 unsigned long parent_rate) 162 { 163 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 164 u32 val = 0; 165 166 val = readl(rtc->base + SUN6I_LOSC_CTRL); 167 if (val & SUN6I_LOSC_CTRL_EXT_OSC) 168 return parent_rate; 169 170 if (rtc->data->fixed_prescaler) 171 parent_rate /= rtc->data->fixed_prescaler; 172 173 if (rtc->data->has_prescaler) { 174 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); 175 val &= GENMASK(4, 0); 176 } 177 178 return parent_rate / (val + 1); 179 } 180 181 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) 182 { 183 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 184 185 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; 186 } 187 188 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) 189 { 190 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 191 unsigned long flags; 192 u32 val; 193 194 if (index > 1) 195 return -EINVAL; 196 197 spin_lock_irqsave(&rtc->lock, flags); 198 val = readl(rtc->base + SUN6I_LOSC_CTRL); 199 val &= ~SUN6I_LOSC_CTRL_EXT_OSC; 200 val |= SUN6I_LOSC_CTRL_KEY; 201 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; 202 if (rtc->data->has_losc_en) { 203 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; 204 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; 205 } 206 writel(val, rtc->base + SUN6I_LOSC_CTRL); 207 spin_unlock_irqrestore(&rtc->lock, flags); 208 209 return 0; 210 } 211 212 static const struct clk_ops sun6i_rtc_osc_ops = { 213 .recalc_rate = sun6i_rtc_osc_recalc_rate, 214 215 .get_parent = sun6i_rtc_osc_get_parent, 216 .set_parent = sun6i_rtc_osc_set_parent, 217 }; 218 219 static void __init sun6i_rtc_clk_init(struct device_node *node, 220 const struct sun6i_rtc_clk_data *data) 221 { 222 struct clk_hw_onecell_data *clk_data; 223 struct sun6i_rtc_dev *rtc; 224 struct clk_init_data init = { 225 .ops = &sun6i_rtc_osc_ops, 226 .name = "losc", 227 }; 228 const char *iosc_name = "rtc-int-osc"; 229 const char *clkout_name = "osc32k-out"; 230 const char *parents[2]; 231 u32 reg; 232 233 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); 234 if (!rtc) 235 return; 236 237 rtc->data = data; 238 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); 239 if (!clk_data) { 240 kfree(rtc); 241 return; 242 } 243 244 spin_lock_init(&rtc->lock); 245 246 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); 247 if (IS_ERR(rtc->base)) { 248 pr_crit("Can't map RTC registers"); 249 goto err; 250 } 251 252 reg = SUN6I_LOSC_CTRL_KEY; 253 if (rtc->data->has_auto_swt) { 254 /* Bypass auto-switch to int osc, on ext losc failure */ 255 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; 256 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 257 } 258 259 /* Switch to the external, more precise, oscillator, if present */ 260 if (of_get_property(node, "clocks", NULL)) { 261 reg |= SUN6I_LOSC_CTRL_EXT_OSC; 262 if (rtc->data->has_losc_en) 263 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; 264 } 265 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 266 267 /* Yes, I know, this is ugly. */ 268 sun6i_rtc = rtc; 269 270 /* Only read IOSC name from device tree if it is exported */ 271 if (rtc->data->export_iosc) 272 of_property_read_string_index(node, "clock-output-names", 2, 273 &iosc_name); 274 275 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, 276 iosc_name, 277 NULL, 0, 278 rtc->data->rc_osc_rate, 279 300000000); 280 if (IS_ERR(rtc->int_osc)) { 281 pr_crit("Couldn't register the internal oscillator\n"); 282 goto err; 283 } 284 285 parents[0] = clk_hw_get_name(rtc->int_osc); 286 /* If there is no external oscillator, this will be NULL and ... */ 287 parents[1] = of_clk_get_parent_name(node, 0); 288 289 rtc->hw.init = &init; 290 291 init.parent_names = parents; 292 /* ... number of clock parents will be 1. */ 293 init.num_parents = of_clk_get_parent_count(node) + 1; 294 of_property_read_string_index(node, "clock-output-names", 0, 295 &init.name); 296 297 rtc->losc = clk_register(NULL, &rtc->hw); 298 if (IS_ERR(rtc->losc)) { 299 pr_crit("Couldn't register the LOSC clock\n"); 300 goto err_register; 301 } 302 303 of_property_read_string_index(node, "clock-output-names", 1, 304 &clkout_name); 305 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, 306 0, rtc->base + SUN6I_LOSC_OUT_GATING, 307 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, 308 &rtc->lock); 309 if (IS_ERR(rtc->ext_losc)) { 310 pr_crit("Couldn't register the LOSC external gate\n"); 311 goto err_register; 312 } 313 314 clk_data->num = 2; 315 clk_data->hws[0] = &rtc->hw; 316 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); 317 if (rtc->data->export_iosc) { 318 clk_data->hws[2] = rtc->int_osc; 319 clk_data->num = 3; 320 } 321 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 322 return; 323 324 err_register: 325 clk_hw_unregister_fixed_rate(rtc->int_osc); 326 err: 327 kfree(clk_data); 328 } 329 330 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { 331 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 332 .has_prescaler = 1, 333 }; 334 335 static void __init sun6i_a31_rtc_clk_init(struct device_node *node) 336 { 337 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); 338 } 339 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", 340 sun6i_a31_rtc_clk_init); 341 342 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { 343 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 344 .has_prescaler = 1, 345 .has_out_clk = 1, 346 }; 347 348 static void __init sun8i_a23_rtc_clk_init(struct device_node *node) 349 { 350 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); 351 } 352 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", 353 sun8i_a23_rtc_clk_init); 354 355 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { 356 .rc_osc_rate = 16000000, 357 .fixed_prescaler = 32, 358 .has_prescaler = 1, 359 .has_out_clk = 1, 360 .export_iosc = 1, 361 }; 362 363 static void __init sun8i_h3_rtc_clk_init(struct device_node *node) 364 { 365 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); 366 } 367 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", 368 sun8i_h3_rtc_clk_init); 369 /* As far as we are concerned, clocks for H5 are the same as H3 */ 370 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", 371 sun8i_h3_rtc_clk_init); 372 373 /* 374 * The R40 user manual is self-conflicting on whether the prescaler is 375 * fixed or configurable. The clock diagram shows it as fixed, but there 376 * is also a configurable divider in the RTC block. 377 */ 378 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = { 379 .rc_osc_rate = 16000000, 380 .fixed_prescaler = 512, 381 }; 382 static void __init sun8i_r40_rtc_clk_init(struct device_node *node) 383 { 384 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data); 385 } 386 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", 387 sun8i_r40_rtc_clk_init); 388 389 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { 390 .rc_osc_rate = 32000, 391 .has_out_clk = 1, 392 }; 393 394 static void __init sun8i_v3_rtc_clk_init(struct device_node *node) 395 { 396 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); 397 } 398 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", 399 sun8i_v3_rtc_clk_init); 400 401 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) 402 { 403 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; 404 irqreturn_t ret = IRQ_NONE; 405 u32 val; 406 407 spin_lock(&chip->lock); 408 val = readl(chip->base + SUN6I_ALRM_IRQ_STA); 409 410 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { 411 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; 412 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); 413 414 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); 415 416 ret = IRQ_HANDLED; 417 } 418 spin_unlock(&chip->lock); 419 420 return ret; 421 } 422 423 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) 424 { 425 u32 alrm_val = 0; 426 u32 alrm_irq_val = 0; 427 u32 alrm_wake_val = 0; 428 unsigned long flags; 429 430 if (to) { 431 alrm_val = SUN6I_ALRM_EN_CNT_EN; 432 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; 433 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; 434 } else { 435 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 436 chip->base + SUN6I_ALRM_IRQ_STA); 437 } 438 439 spin_lock_irqsave(&chip->lock, flags); 440 writel(alrm_val, chip->base + SUN6I_ALRM_EN); 441 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); 442 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); 443 spin_unlock_irqrestore(&chip->lock, flags); 444 } 445 446 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 447 { 448 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 449 u32 date, time; 450 451 /* 452 * read again in case it changes 453 */ 454 do { 455 date = readl(chip->base + SUN6I_RTC_YMD); 456 time = readl(chip->base + SUN6I_RTC_HMS); 457 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || 458 (time != readl(chip->base + SUN6I_RTC_HMS))); 459 460 if (chip->flags & RTC_LINEAR_DAY) { 461 /* 462 * Newer chips store a linear day number, the manual 463 * does not mandate any epoch base. The BSP driver uses 464 * the UNIX epoch, let's just copy that, as it's the 465 * easiest anyway. 466 */ 467 rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm); 468 } else { 469 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); 470 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1; 471 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); 472 473 /* 474 * switch from (data_year->min)-relative offset to 475 * a (1900)-relative one 476 */ 477 rtc_tm->tm_year += SUN6I_YEAR_OFF; 478 } 479 480 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); 481 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); 482 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); 483 484 return 0; 485 } 486 487 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 488 { 489 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 490 unsigned long flags; 491 u32 alrm_st; 492 u32 alrm_en; 493 494 spin_lock_irqsave(&chip->lock, flags); 495 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); 496 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); 497 spin_unlock_irqrestore(&chip->lock, flags); 498 499 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); 500 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); 501 rtc_time64_to_tm(chip->alarm, &wkalrm->time); 502 503 return 0; 504 } 505 506 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 507 { 508 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 509 struct rtc_time *alrm_tm = &wkalrm->time; 510 struct rtc_time tm_now; 511 time64_t time_set; 512 u32 counter_val, counter_val_hms; 513 int ret; 514 515 time_set = rtc_tm_to_time64(alrm_tm); 516 517 if (chip->flags & RTC_LINEAR_DAY) { 518 /* 519 * The alarm registers hold the actual alarm time, encoded 520 * in the same way (linear day + HMS) as the current time. 521 */ 522 counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) | 523 SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) | 524 SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour); 525 /* The division will cut off the H:M:S part of alrm_tm. */ 526 counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY); 527 } else { 528 /* The alarm register holds the number of seconds left. */ 529 time64_t time_now; 530 531 ret = sun6i_rtc_gettime(dev, &tm_now); 532 if (ret < 0) { 533 dev_err(dev, "Error in getting time\n"); 534 return -EINVAL; 535 } 536 537 time_now = rtc_tm_to_time64(&tm_now); 538 if (time_set <= time_now) { 539 dev_err(dev, "Date to set in the past\n"); 540 return -EINVAL; 541 } 542 if ((time_set - time_now) > U32_MAX) { 543 dev_err(dev, "Date too far in the future\n"); 544 return -EINVAL; 545 } 546 547 counter_val = time_set - time_now; 548 } 549 550 sun6i_rtc_setaie(0, chip); 551 writel(0, chip->base + SUN6I_ALRM_COUNTER); 552 if (chip->flags & RTC_LINEAR_DAY) 553 writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS); 554 usleep_range(100, 300); 555 556 writel(counter_val, chip->base + SUN6I_ALRM_COUNTER); 557 if (chip->flags & RTC_LINEAR_DAY) 558 writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS); 559 chip->alarm = time_set; 560 561 sun6i_rtc_setaie(wkalrm->enabled, chip); 562 563 return 0; 564 } 565 566 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, 567 unsigned int mask, unsigned int ms_timeout) 568 { 569 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); 570 u32 reg; 571 572 do { 573 reg = readl(chip->base + offset); 574 reg &= mask; 575 576 if (!reg) 577 return 0; 578 579 } while (time_before(jiffies, timeout)); 580 581 return -ETIMEDOUT; 582 } 583 584 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) 585 { 586 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 587 u32 date = 0; 588 u32 time = 0; 589 590 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | 591 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | 592 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); 593 594 if (chip->flags & RTC_LINEAR_DAY) { 595 /* The division will cut off the H:M:S part of rtc_tm. */ 596 date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY); 597 } else { 598 rtc_tm->tm_year -= SUN6I_YEAR_OFF; 599 rtc_tm->tm_mon += 1; 600 601 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | 602 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | 603 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); 604 605 if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) 606 date |= SUN6I_LEAP_SET_VALUE(1); 607 } 608 609 /* Check whether registers are writable */ 610 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 611 SUN6I_LOSC_CTRL_ACC_MASK, 50)) { 612 dev_err(dev, "rtc is still busy.\n"); 613 return -EBUSY; 614 } 615 616 writel(time, chip->base + SUN6I_RTC_HMS); 617 618 /* 619 * After writing the RTC HH-MM-SS register, the 620 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not 621 * be cleared until the real writing operation is finished 622 */ 623 624 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 625 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { 626 dev_err(dev, "Failed to set rtc time.\n"); 627 return -ETIMEDOUT; 628 } 629 630 writel(date, chip->base + SUN6I_RTC_YMD); 631 632 /* 633 * After writing the RTC YY-MM-DD register, the 634 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not 635 * be cleared until the real writing operation is finished 636 */ 637 638 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 639 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { 640 dev_err(dev, "Failed to set rtc time.\n"); 641 return -ETIMEDOUT; 642 } 643 644 return 0; 645 } 646 647 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 648 { 649 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 650 651 if (!enabled) 652 sun6i_rtc_setaie(enabled, chip); 653 654 return 0; 655 } 656 657 static const struct rtc_class_ops sun6i_rtc_ops = { 658 .read_time = sun6i_rtc_gettime, 659 .set_time = sun6i_rtc_settime, 660 .read_alarm = sun6i_rtc_getalarm, 661 .set_alarm = sun6i_rtc_setalarm, 662 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable 663 }; 664 665 #ifdef CONFIG_PM_SLEEP 666 /* Enable IRQ wake on suspend, to wake up from RTC. */ 667 static int sun6i_rtc_suspend(struct device *dev) 668 { 669 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 670 671 if (device_may_wakeup(dev)) 672 enable_irq_wake(chip->irq); 673 674 return 0; 675 } 676 677 /* Disable IRQ wake on resume. */ 678 static int sun6i_rtc_resume(struct device *dev) 679 { 680 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 681 682 if (device_may_wakeup(dev)) 683 disable_irq_wake(chip->irq); 684 685 return 0; 686 } 687 #endif 688 689 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, 690 sun6i_rtc_suspend, sun6i_rtc_resume); 691 692 static void sun6i_rtc_bus_clk_cleanup(void *data) 693 { 694 struct clk *bus_clk = data; 695 696 clk_disable_unprepare(bus_clk); 697 } 698 699 static int sun6i_rtc_probe(struct platform_device *pdev) 700 { 701 struct sun6i_rtc_dev *chip = sun6i_rtc; 702 struct device *dev = &pdev->dev; 703 struct clk *bus_clk; 704 int ret; 705 706 bus_clk = devm_clk_get_optional(dev, "bus"); 707 if (IS_ERR(bus_clk)) 708 return PTR_ERR(bus_clk); 709 710 if (bus_clk) { 711 ret = clk_prepare_enable(bus_clk); 712 if (ret) 713 return ret; 714 715 ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup, 716 bus_clk); 717 if (ret) 718 return ret; 719 } 720 721 if (!chip) { 722 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 723 if (!chip) 724 return -ENOMEM; 725 726 spin_lock_init(&chip->lock); 727 728 chip->base = devm_platform_ioremap_resource(pdev, 0); 729 if (IS_ERR(chip->base)) 730 return PTR_ERR(chip->base); 731 732 if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) { 733 ret = sun6i_rtc_ccu_probe(dev, chip->base); 734 if (ret) 735 return ret; 736 } 737 } 738 739 platform_set_drvdata(pdev, chip); 740 741 chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev); 742 743 chip->irq = platform_get_irq(pdev, 0); 744 if (chip->irq < 0) 745 return chip->irq; 746 747 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, 748 0, dev_name(&pdev->dev), chip); 749 if (ret) { 750 dev_err(&pdev->dev, "Could not request IRQ\n"); 751 return ret; 752 } 753 754 /* clear the alarm counter value */ 755 writel(0, chip->base + SUN6I_ALRM_COUNTER); 756 757 /* disable counter alarm */ 758 writel(0, chip->base + SUN6I_ALRM_EN); 759 760 /* disable counter alarm interrupt */ 761 writel(0, chip->base + SUN6I_ALRM_IRQ_EN); 762 763 /* disable week alarm */ 764 writel(0, chip->base + SUN6I_ALRM1_EN); 765 766 /* disable week alarm interrupt */ 767 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); 768 769 /* clear counter alarm pending interrupts */ 770 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 771 chip->base + SUN6I_ALRM_IRQ_STA); 772 773 /* clear week alarm pending interrupts */ 774 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, 775 chip->base + SUN6I_ALRM1_IRQ_STA); 776 777 /* disable alarm wakeup */ 778 writel(0, chip->base + SUN6I_ALARM_CONFIG); 779 780 clk_prepare_enable(chip->losc); 781 782 device_init_wakeup(&pdev->dev, 1); 783 784 chip->rtc = devm_rtc_allocate_device(&pdev->dev); 785 if (IS_ERR(chip->rtc)) 786 return PTR_ERR(chip->rtc); 787 788 chip->rtc->ops = &sun6i_rtc_ops; 789 if (chip->flags & RTC_LINEAR_DAY) 790 chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1; 791 else 792 chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ 793 794 ret = devm_rtc_register_device(chip->rtc); 795 if (ret) 796 return ret; 797 798 dev_info(&pdev->dev, "RTC enabled\n"); 799 800 return 0; 801 } 802 803 /* 804 * As far as RTC functionality goes, all models are the same. The 805 * datasheets claim that different models have different number of 806 * registers available for non-volatile storage, but experiments show 807 * that all SoCs have 16 registers available for this purpose. 808 */ 809 static const struct of_device_id sun6i_rtc_dt_ids[] = { 810 { .compatible = "allwinner,sun6i-a31-rtc" }, 811 { .compatible = "allwinner,sun8i-a23-rtc" }, 812 { .compatible = "allwinner,sun8i-h3-rtc" }, 813 { .compatible = "allwinner,sun8i-r40-rtc" }, 814 { .compatible = "allwinner,sun8i-v3-rtc" }, 815 { .compatible = "allwinner,sun50i-h5-rtc" }, 816 { .compatible = "allwinner,sun50i-h6-rtc" }, 817 { .compatible = "allwinner,sun50i-h616-rtc", 818 .data = (void *)RTC_LINEAR_DAY }, 819 { /* sentinel */ }, 820 }; 821 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); 822 823 static struct platform_driver sun6i_rtc_driver = { 824 .probe = sun6i_rtc_probe, 825 .driver = { 826 .name = "sun6i-rtc", 827 .of_match_table = sun6i_rtc_dt_ids, 828 .pm = &sun6i_rtc_pm_ops, 829 }, 830 }; 831 builtin_platform_driver(sun6i_rtc_driver); 832