1 /* 2 * Freescale STMP37XX/STMP378X Real Time Clock driver 3 * 4 * Copyright (c) 2007 Sigmatel, Inc. 5 * Peter Hartley, <peter.hartley@sigmatel.com> 6 * 7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. 8 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 9 * Copyright 2011 Wolfram Sang, Pengutronix e.K. 10 */ 11 12 /* 13 * The code contained herein is licensed under the GNU General Public 14 * License. You may obtain a copy of the GNU General Public License 15 * Version 2 or later at the following locations: 16 * 17 * http://www.opensource.org/licenses/gpl-license.html 18 * http://www.gnu.org/copyleft/gpl.html 19 */ 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/io.h> 23 #include <linux/init.h> 24 #include <linux/platform_device.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/rtc.h> 28 #include <linux/slab.h> 29 #include <linux/of_device.h> 30 #include <linux/of.h> 31 #include <linux/stmp_device.h> 32 #include <linux/stmp3xxx_rtc_wdt.h> 33 34 #define STMP3XXX_RTC_CTRL 0x0 35 #define STMP3XXX_RTC_CTRL_SET 0x4 36 #define STMP3XXX_RTC_CTRL_CLR 0x8 37 #define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001 38 #define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 39 #define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004 40 #define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010 41 42 #define STMP3XXX_RTC_STAT 0x10 43 #define STMP3XXX_RTC_STAT_STALE_SHIFT 16 44 #define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000 45 #define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000 46 #define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000 47 48 #define STMP3XXX_RTC_SECONDS 0x30 49 50 #define STMP3XXX_RTC_ALARM 0x40 51 52 #define STMP3XXX_RTC_WATCHDOG 0x50 53 54 #define STMP3XXX_RTC_PERSISTENT0 0x60 55 #define STMP3XXX_RTC_PERSISTENT0_SET 0x64 56 #define STMP3XXX_RTC_PERSISTENT0_CLR 0x68 57 #define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) 58 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) 59 #define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2) 60 #define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4) 61 #define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) 62 #define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) 63 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7) 64 65 #define STMP3XXX_RTC_PERSISTENT1 0x70 66 /* missing bitmask in headers */ 67 #define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000 68 69 struct stmp3xxx_rtc_data { 70 struct rtc_device *rtc; 71 void __iomem *io; 72 int irq_alarm; 73 }; 74 75 #if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG) 76 /** 77 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC 78 * @dev: the parent device of the watchdog (= the RTC) 79 * @timeout: the desired value for the timeout register of the watchdog. 80 * 0 disables the watchdog 81 * 82 * The watchdog needs one register and two bits which are in the RTC domain. 83 * To handle the resource conflict, the RTC driver will create another 84 * platform_device for the watchdog driver as a child of the RTC device. 85 * The watchdog driver is passed the below accessor function via platform_data 86 * to configure the watchdog. Locking is not needed because accessing SET/CLR 87 * registers is atomic. 88 */ 89 90 static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout) 91 { 92 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 93 94 if (timeout) { 95 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG); 96 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, 97 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET); 98 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, 99 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET); 100 } else { 101 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, 102 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); 103 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, 104 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR); 105 } 106 } 107 108 static struct stmp3xxx_wdt_pdata wdt_pdata = { 109 .wdt_set_timeout = stmp3xxx_wdt_set_timeout, 110 }; 111 112 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev) 113 { 114 struct platform_device *wdt_pdev = 115 platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id); 116 117 if (wdt_pdev) { 118 wdt_pdev->dev.parent = &rtc_pdev->dev; 119 wdt_pdev->dev.platform_data = &wdt_pdata; 120 platform_device_add(wdt_pdev); 121 } 122 } 123 #else 124 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev) 125 { 126 } 127 #endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */ 128 129 static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data) 130 { 131 int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */ 132 /* 133 * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 134 * states: 135 * | The order in which registers are updated is 136 * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds. 137 * | (This list is in bitfield order, from LSB to MSB, as they would 138 * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT 139 * | register. For example, the Seconds register corresponds to 140 * | STALE_REGS or NEW_REGS containing 0x80.) 141 */ 142 do { 143 if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) & 144 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT))) 145 return 0; 146 udelay(1); 147 } while (--timeout > 0); 148 return (readl(rtc_data->io + STMP3XXX_RTC_STAT) & 149 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0; 150 } 151 152 /* Time read/write */ 153 static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 154 { 155 int ret; 156 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 157 158 ret = stmp3xxx_wait_time(rtc_data); 159 if (ret) 160 return ret; 161 162 rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm); 163 return 0; 164 } 165 166 static int stmp3xxx_rtc_set_mmss(struct device *dev, unsigned long t) 167 { 168 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 169 170 writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS); 171 return stmp3xxx_wait_time(rtc_data); 172 } 173 174 /* interrupt(s) handler */ 175 static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id) 176 { 177 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id); 178 u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL); 179 180 if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) { 181 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ, 182 rtc_data->io + STMP3XXX_RTC_CTRL_CLR); 183 rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF); 184 return IRQ_HANDLED; 185 } 186 187 return IRQ_NONE; 188 } 189 190 static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled) 191 { 192 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 193 194 if (enabled) { 195 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 196 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN, 197 rtc_data->io + STMP3XXX_RTC_PERSISTENT0_SET); 198 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, 199 rtc_data->io + STMP3XXX_RTC_CTRL_SET); 200 } else { 201 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 202 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN, 203 rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR); 204 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, 205 rtc_data->io + STMP3XXX_RTC_CTRL_CLR); 206 } 207 return 0; 208 } 209 210 static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) 211 { 212 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 213 214 rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time); 215 return 0; 216 } 217 218 static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) 219 { 220 unsigned long t; 221 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 222 223 rtc_tm_to_time(&alm->time, &t); 224 writel(t, rtc_data->io + STMP3XXX_RTC_ALARM); 225 226 stmp3xxx_alarm_irq_enable(dev, alm->enabled); 227 228 return 0; 229 } 230 231 static struct rtc_class_ops stmp3xxx_rtc_ops = { 232 .alarm_irq_enable = 233 stmp3xxx_alarm_irq_enable, 234 .read_time = stmp3xxx_rtc_gettime, 235 .set_mmss = stmp3xxx_rtc_set_mmss, 236 .read_alarm = stmp3xxx_rtc_read_alarm, 237 .set_alarm = stmp3xxx_rtc_set_alarm, 238 }; 239 240 static int stmp3xxx_rtc_remove(struct platform_device *pdev) 241 { 242 struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev); 243 244 if (!rtc_data) 245 return 0; 246 247 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, 248 rtc_data->io + STMP3XXX_RTC_CTRL_CLR); 249 250 return 0; 251 } 252 253 static int stmp3xxx_rtc_probe(struct platform_device *pdev) 254 { 255 struct stmp3xxx_rtc_data *rtc_data; 256 struct resource *r; 257 u32 rtc_stat; 258 u32 pers0_set, pers0_clr; 259 u32 crystalfreq = 0; 260 int err; 261 262 rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL); 263 if (!rtc_data) 264 return -ENOMEM; 265 266 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 267 if (!r) { 268 dev_err(&pdev->dev, "failed to get resource\n"); 269 return -ENXIO; 270 } 271 272 rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 273 if (!rtc_data->io) { 274 dev_err(&pdev->dev, "ioremap failed\n"); 275 return -EIO; 276 } 277 278 rtc_data->irq_alarm = platform_get_irq(pdev, 0); 279 280 rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT); 281 if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) { 282 dev_err(&pdev->dev, "no device onboard\n"); 283 return -ENODEV; 284 } 285 286 platform_set_drvdata(pdev, rtc_data); 287 288 err = stmp_reset_block(rtc_data->io); 289 if (err) { 290 dev_err(&pdev->dev, "stmp_reset_block failed: %d\n", err); 291 return err; 292 } 293 294 /* 295 * Obviously the rtc needs a clock input to be able to run. 296 * This clock can be provided by an external 32k crystal. If that one is 297 * missing XTAL must not be disabled in suspend which consumes a 298 * lot of power. Normally the presence and exact frequency (supported 299 * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality 300 * proves these fuses are not blown correctly on all machines, so the 301 * frequency can be overridden in the device tree. 302 */ 303 if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT) 304 crystalfreq = 32000; 305 else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT) 306 crystalfreq = 32768; 307 308 of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq", 309 &crystalfreq); 310 311 switch (crystalfreq) { 312 case 32000: 313 /* keep 32kHz crystal running in low-power mode */ 314 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ | 315 STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP | 316 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE; 317 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP; 318 break; 319 case 32768: 320 /* keep 32.768kHz crystal running in low-power mode */ 321 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP | 322 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE; 323 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP | 324 STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ; 325 break; 326 default: 327 dev_warn(&pdev->dev, 328 "invalid crystal-freq specified in device-tree. Assuming no crystal\n"); 329 /* fall-through */ 330 case 0: 331 /* keep XTAL on in low-power mode */ 332 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP; 333 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP | 334 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE; 335 } 336 337 writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0_SET); 338 339 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 340 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | 341 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr, 342 rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR); 343 344 writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN | 345 STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, 346 rtc_data->io + STMP3XXX_RTC_CTRL_CLR); 347 348 rtc_data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, 349 &stmp3xxx_rtc_ops, THIS_MODULE); 350 if (IS_ERR(rtc_data->rtc)) 351 return PTR_ERR(rtc_data->rtc); 352 353 err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm, 354 stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev); 355 if (err) { 356 dev_err(&pdev->dev, "Cannot claim IRQ%d\n", 357 rtc_data->irq_alarm); 358 return err; 359 } 360 361 stmp3xxx_wdt_register(pdev); 362 return 0; 363 } 364 365 #ifdef CONFIG_PM_SLEEP 366 static int stmp3xxx_rtc_suspend(struct device *dev) 367 { 368 return 0; 369 } 370 371 static int stmp3xxx_rtc_resume(struct device *dev) 372 { 373 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 374 375 stmp_reset_block(rtc_data->io); 376 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 377 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | 378 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE, 379 rtc_data->io + STMP3XXX_RTC_PERSISTENT0_CLR); 380 return 0; 381 } 382 #endif 383 384 static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend, 385 stmp3xxx_rtc_resume); 386 387 static const struct of_device_id rtc_dt_ids[] = { 388 { .compatible = "fsl,stmp3xxx-rtc", }, 389 { /* sentinel */ } 390 }; 391 MODULE_DEVICE_TABLE(of, rtc_dt_ids); 392 393 static struct platform_driver stmp3xxx_rtcdrv = { 394 .probe = stmp3xxx_rtc_probe, 395 .remove = stmp3xxx_rtc_remove, 396 .driver = { 397 .name = "stmp3xxx-rtc", 398 .pm = &stmp3xxx_rtc_pm_ops, 399 .of_match_table = rtc_dt_ids, 400 }, 401 }; 402 403 module_platform_driver(stmp3xxx_rtcdrv); 404 405 MODULE_DESCRIPTION("STMP3xxx RTC Driver"); 406 MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and " 407 "Wolfram Sang <w.sang@pengutronix.de>"); 408 MODULE_LICENSE("GPL"); 409