1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2017 4 * Author: Amelie Delaunay <amelie.delaunay@st.com> 5 */ 6 7 #include <linux/bcd.h> 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/ioport.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_wakeirq.h> 15 #include <linux/regmap.h> 16 #include <linux/rtc.h> 17 18 #define DRIVER_NAME "stm32_rtc" 19 20 /* STM32_RTC_TR bit fields */ 21 #define STM32_RTC_TR_SEC_SHIFT 0 22 #define STM32_RTC_TR_SEC GENMASK(6, 0) 23 #define STM32_RTC_TR_MIN_SHIFT 8 24 #define STM32_RTC_TR_MIN GENMASK(14, 8) 25 #define STM32_RTC_TR_HOUR_SHIFT 16 26 #define STM32_RTC_TR_HOUR GENMASK(21, 16) 27 28 /* STM32_RTC_DR bit fields */ 29 #define STM32_RTC_DR_DATE_SHIFT 0 30 #define STM32_RTC_DR_DATE GENMASK(5, 0) 31 #define STM32_RTC_DR_MONTH_SHIFT 8 32 #define STM32_RTC_DR_MONTH GENMASK(12, 8) 33 #define STM32_RTC_DR_WDAY_SHIFT 13 34 #define STM32_RTC_DR_WDAY GENMASK(15, 13) 35 #define STM32_RTC_DR_YEAR_SHIFT 16 36 #define STM32_RTC_DR_YEAR GENMASK(23, 16) 37 38 /* STM32_RTC_CR bit fields */ 39 #define STM32_RTC_CR_FMT BIT(6) 40 #define STM32_RTC_CR_ALRAE BIT(8) 41 #define STM32_RTC_CR_ALRAIE BIT(12) 42 43 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ 44 #define STM32_RTC_ISR_ALRAWF BIT(0) 45 #define STM32_RTC_ISR_INITS BIT(4) 46 #define STM32_RTC_ISR_RSF BIT(5) 47 #define STM32_RTC_ISR_INITF BIT(6) 48 #define STM32_RTC_ISR_INIT BIT(7) 49 #define STM32_RTC_ISR_ALRAF BIT(8) 50 51 /* STM32_RTC_PRER bit fields */ 52 #define STM32_RTC_PRER_PRED_S_SHIFT 0 53 #define STM32_RTC_PRER_PRED_S GENMASK(14, 0) 54 #define STM32_RTC_PRER_PRED_A_SHIFT 16 55 #define STM32_RTC_PRER_PRED_A GENMASK(22, 16) 56 57 /* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */ 58 #define STM32_RTC_ALRMXR_SEC_SHIFT 0 59 #define STM32_RTC_ALRMXR_SEC GENMASK(6, 0) 60 #define STM32_RTC_ALRMXR_SEC_MASK BIT(7) 61 #define STM32_RTC_ALRMXR_MIN_SHIFT 8 62 #define STM32_RTC_ALRMXR_MIN GENMASK(14, 8) 63 #define STM32_RTC_ALRMXR_MIN_MASK BIT(15) 64 #define STM32_RTC_ALRMXR_HOUR_SHIFT 16 65 #define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16) 66 #define STM32_RTC_ALRMXR_PM BIT(22) 67 #define STM32_RTC_ALRMXR_HOUR_MASK BIT(23) 68 #define STM32_RTC_ALRMXR_DATE_SHIFT 24 69 #define STM32_RTC_ALRMXR_DATE GENMASK(29, 24) 70 #define STM32_RTC_ALRMXR_WDSEL BIT(30) 71 #define STM32_RTC_ALRMXR_WDAY_SHIFT 24 72 #define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24) 73 #define STM32_RTC_ALRMXR_DATE_MASK BIT(31) 74 75 /* STM32_RTC_SR/_SCR bit fields */ 76 #define STM32_RTC_SR_ALRA BIT(0) 77 78 /* STM32_RTC_VERR bit fields */ 79 #define STM32_RTC_VERR_MINREV_SHIFT 0 80 #define STM32_RTC_VERR_MINREV GENMASK(3, 0) 81 #define STM32_RTC_VERR_MAJREV_SHIFT 4 82 #define STM32_RTC_VERR_MAJREV GENMASK(7, 4) 83 84 /* STM32_RTC_WPR key constants */ 85 #define RTC_WPR_1ST_KEY 0xCA 86 #define RTC_WPR_2ND_KEY 0x53 87 #define RTC_WPR_WRONG_KEY 0xFF 88 89 /* Max STM32 RTC register offset is 0x3FC */ 90 #define UNDEF_REG 0xFFFF 91 92 struct stm32_rtc; 93 94 struct stm32_rtc_registers { 95 u16 tr; 96 u16 dr; 97 u16 cr; 98 u16 isr; 99 u16 prer; 100 u16 alrmar; 101 u16 wpr; 102 u16 sr; 103 u16 scr; 104 u16 verr; 105 }; 106 107 struct stm32_rtc_events { 108 u32 alra; 109 }; 110 111 struct stm32_rtc_data { 112 const struct stm32_rtc_registers regs; 113 const struct stm32_rtc_events events; 114 void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags); 115 bool has_pclk; 116 bool need_dbp; 117 }; 118 119 struct stm32_rtc { 120 struct rtc_device *rtc_dev; 121 void __iomem *base; 122 struct regmap *dbp; 123 unsigned int dbp_reg; 124 unsigned int dbp_mask; 125 struct clk *pclk; 126 struct clk *rtc_ck; 127 const struct stm32_rtc_data *data; 128 int irq_alarm; 129 }; 130 131 static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc) 132 { 133 const struct stm32_rtc_registers *regs = &rtc->data->regs; 134 135 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); 136 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr); 137 } 138 139 static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc) 140 { 141 const struct stm32_rtc_registers *regs = &rtc->data->regs; 142 143 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); 144 } 145 146 static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) 147 { 148 const struct stm32_rtc_registers *regs = &rtc->data->regs; 149 unsigned int isr = readl_relaxed(rtc->base + regs->isr); 150 151 if (!(isr & STM32_RTC_ISR_INITF)) { 152 isr |= STM32_RTC_ISR_INIT; 153 writel_relaxed(isr, rtc->base + regs->isr); 154 155 /* 156 * It takes around 2 rtc_ck clock cycles to enter in 157 * initialization phase mode (and have INITF flag set). As 158 * slowest rtc_ck frequency may be 32kHz and highest should be 159 * 1MHz, we poll every 10 us with a timeout of 100ms. 160 */ 161 return readl_relaxed_poll_timeout_atomic( 162 rtc->base + regs->isr, 163 isr, (isr & STM32_RTC_ISR_INITF), 164 10, 100000); 165 } 166 167 return 0; 168 } 169 170 static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc) 171 { 172 const struct stm32_rtc_registers *regs = &rtc->data->regs; 173 unsigned int isr = readl_relaxed(rtc->base + regs->isr); 174 175 isr &= ~STM32_RTC_ISR_INIT; 176 writel_relaxed(isr, rtc->base + regs->isr); 177 } 178 179 static int stm32_rtc_wait_sync(struct stm32_rtc *rtc) 180 { 181 const struct stm32_rtc_registers *regs = &rtc->data->regs; 182 unsigned int isr = readl_relaxed(rtc->base + regs->isr); 183 184 isr &= ~STM32_RTC_ISR_RSF; 185 writel_relaxed(isr, rtc->base + regs->isr); 186 187 /* 188 * Wait for RSF to be set to ensure the calendar registers are 189 * synchronised, it takes around 2 rtc_ck clock cycles 190 */ 191 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, 192 isr, 193 (isr & STM32_RTC_ISR_RSF), 194 10, 100000); 195 } 196 197 static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc, 198 unsigned int flags) 199 { 200 rtc->data->clear_events(rtc, flags); 201 } 202 203 static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id) 204 { 205 struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id; 206 const struct stm32_rtc_registers *regs = &rtc->data->regs; 207 const struct stm32_rtc_events *evts = &rtc->data->events; 208 unsigned int status, cr; 209 210 rtc_lock(rtc->rtc_dev); 211 212 status = readl_relaxed(rtc->base + regs->sr); 213 cr = readl_relaxed(rtc->base + regs->cr); 214 215 if ((status & evts->alra) && 216 (cr & STM32_RTC_CR_ALRAIE)) { 217 /* Alarm A flag - Alarm interrupt */ 218 dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n"); 219 220 /* Pass event to the kernel */ 221 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF); 222 223 /* Clear event flags, otherwise new events won't be received */ 224 stm32_rtc_clear_event_flags(rtc, evts->alra); 225 } 226 227 rtc_unlock(rtc->rtc_dev); 228 229 return IRQ_HANDLED; 230 } 231 232 /* Convert rtc_time structure from bin to bcd format */ 233 static void tm2bcd(struct rtc_time *tm) 234 { 235 tm->tm_sec = bin2bcd(tm->tm_sec); 236 tm->tm_min = bin2bcd(tm->tm_min); 237 tm->tm_hour = bin2bcd(tm->tm_hour); 238 239 tm->tm_mday = bin2bcd(tm->tm_mday); 240 tm->tm_mon = bin2bcd(tm->tm_mon + 1); 241 tm->tm_year = bin2bcd(tm->tm_year - 100); 242 /* 243 * Number of days since Sunday 244 * - on kernel side, 0=Sunday...6=Saturday 245 * - on rtc side, 0=invalid,1=Monday...7=Sunday 246 */ 247 tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday; 248 } 249 250 /* Convert rtc_time structure from bcd to bin format */ 251 static void bcd2tm(struct rtc_time *tm) 252 { 253 tm->tm_sec = bcd2bin(tm->tm_sec); 254 tm->tm_min = bcd2bin(tm->tm_min); 255 tm->tm_hour = bcd2bin(tm->tm_hour); 256 257 tm->tm_mday = bcd2bin(tm->tm_mday); 258 tm->tm_mon = bcd2bin(tm->tm_mon) - 1; 259 tm->tm_year = bcd2bin(tm->tm_year) + 100; 260 /* 261 * Number of days since Sunday 262 * - on kernel side, 0=Sunday...6=Saturday 263 * - on rtc side, 0=invalid,1=Monday...7=Sunday 264 */ 265 tm->tm_wday %= 7; 266 } 267 268 static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm) 269 { 270 struct stm32_rtc *rtc = dev_get_drvdata(dev); 271 const struct stm32_rtc_registers *regs = &rtc->data->regs; 272 unsigned int tr, dr; 273 274 /* Time and Date in BCD format */ 275 tr = readl_relaxed(rtc->base + regs->tr); 276 dr = readl_relaxed(rtc->base + regs->dr); 277 278 tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT; 279 tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT; 280 tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT; 281 282 tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT; 283 tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT; 284 tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT; 285 tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT; 286 287 /* We don't report tm_yday and tm_isdst */ 288 289 bcd2tm(tm); 290 291 return 0; 292 } 293 294 static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm) 295 { 296 struct stm32_rtc *rtc = dev_get_drvdata(dev); 297 const struct stm32_rtc_registers *regs = &rtc->data->regs; 298 unsigned int tr, dr; 299 int ret = 0; 300 301 tm2bcd(tm); 302 303 /* Time in BCD format */ 304 tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) | 305 ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) | 306 ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR); 307 308 /* Date in BCD format */ 309 dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) | 310 ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) | 311 ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) | 312 ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY); 313 314 stm32_rtc_wpr_unlock(rtc); 315 316 ret = stm32_rtc_enter_init_mode(rtc); 317 if (ret) { 318 dev_err(dev, "Can't enter in init mode. Set time aborted.\n"); 319 goto end; 320 } 321 322 writel_relaxed(tr, rtc->base + regs->tr); 323 writel_relaxed(dr, rtc->base + regs->dr); 324 325 stm32_rtc_exit_init_mode(rtc); 326 327 ret = stm32_rtc_wait_sync(rtc); 328 end: 329 stm32_rtc_wpr_lock(rtc); 330 331 return ret; 332 } 333 334 static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 335 { 336 struct stm32_rtc *rtc = dev_get_drvdata(dev); 337 const struct stm32_rtc_registers *regs = &rtc->data->regs; 338 const struct stm32_rtc_events *evts = &rtc->data->events; 339 struct rtc_time *tm = &alrm->time; 340 unsigned int alrmar, cr, status; 341 342 alrmar = readl_relaxed(rtc->base + regs->alrmar); 343 cr = readl_relaxed(rtc->base + regs->cr); 344 status = readl_relaxed(rtc->base + regs->sr); 345 346 if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) { 347 /* 348 * Date/day doesn't matter in Alarm comparison so alarm 349 * triggers every day 350 */ 351 tm->tm_mday = -1; 352 tm->tm_wday = -1; 353 } else { 354 if (alrmar & STM32_RTC_ALRMXR_WDSEL) { 355 /* Alarm is set to a day of week */ 356 tm->tm_mday = -1; 357 tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >> 358 STM32_RTC_ALRMXR_WDAY_SHIFT; 359 tm->tm_wday %= 7; 360 } else { 361 /* Alarm is set to a day of month */ 362 tm->tm_wday = -1; 363 tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >> 364 STM32_RTC_ALRMXR_DATE_SHIFT; 365 } 366 } 367 368 if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) { 369 /* Hours don't matter in Alarm comparison */ 370 tm->tm_hour = -1; 371 } else { 372 tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >> 373 STM32_RTC_ALRMXR_HOUR_SHIFT; 374 if (alrmar & STM32_RTC_ALRMXR_PM) 375 tm->tm_hour += 12; 376 } 377 378 if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) { 379 /* Minutes don't matter in Alarm comparison */ 380 tm->tm_min = -1; 381 } else { 382 tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >> 383 STM32_RTC_ALRMXR_MIN_SHIFT; 384 } 385 386 if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) { 387 /* Seconds don't matter in Alarm comparison */ 388 tm->tm_sec = -1; 389 } else { 390 tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >> 391 STM32_RTC_ALRMXR_SEC_SHIFT; 392 } 393 394 bcd2tm(tm); 395 396 alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0; 397 alrm->pending = (status & evts->alra) ? 1 : 0; 398 399 return 0; 400 } 401 402 static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 403 { 404 struct stm32_rtc *rtc = dev_get_drvdata(dev); 405 const struct stm32_rtc_registers *regs = &rtc->data->regs; 406 const struct stm32_rtc_events *evts = &rtc->data->events; 407 unsigned int cr; 408 409 cr = readl_relaxed(rtc->base + regs->cr); 410 411 stm32_rtc_wpr_unlock(rtc); 412 413 /* We expose Alarm A to the kernel */ 414 if (enabled) 415 cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); 416 else 417 cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); 418 writel_relaxed(cr, rtc->base + regs->cr); 419 420 /* Clear event flags, otherwise new events won't be received */ 421 stm32_rtc_clear_event_flags(rtc, evts->alra); 422 423 stm32_rtc_wpr_lock(rtc); 424 425 return 0; 426 } 427 428 static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm) 429 { 430 const struct stm32_rtc_registers *regs = &rtc->data->regs; 431 int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec; 432 unsigned int dr = readl_relaxed(rtc->base + regs->dr); 433 unsigned int tr = readl_relaxed(rtc->base + regs->tr); 434 435 cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT; 436 cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT; 437 cur_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT; 438 cur_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT; 439 cur_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT; 440 cur_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT; 441 442 /* 443 * Assuming current date is M-D-Y H:M:S. 444 * RTC alarm can't be set on a specific month and year. 445 * So the valid alarm range is: 446 * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S 447 * with a specific case for December... 448 */ 449 if ((((tm->tm_year > cur_year) && 450 (tm->tm_mon == 0x1) && (cur_mon == 0x12)) || 451 ((tm->tm_year == cur_year) && 452 (tm->tm_mon <= cur_mon + 1))) && 453 ((tm->tm_mday > cur_day) || 454 ((tm->tm_mday == cur_day) && 455 ((tm->tm_hour > cur_hour) || 456 ((tm->tm_hour == cur_hour) && (tm->tm_min > cur_min)) || 457 ((tm->tm_hour == cur_hour) && (tm->tm_min == cur_min) && 458 (tm->tm_sec >= cur_sec)))))) 459 return 0; 460 461 return -EINVAL; 462 } 463 464 static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 465 { 466 struct stm32_rtc *rtc = dev_get_drvdata(dev); 467 const struct stm32_rtc_registers *regs = &rtc->data->regs; 468 struct rtc_time *tm = &alrm->time; 469 unsigned int cr, isr, alrmar; 470 int ret = 0; 471 472 tm2bcd(tm); 473 474 /* 475 * RTC alarm can't be set on a specific date, unless this date is 476 * up to the same day of month next month. 477 */ 478 if (stm32_rtc_valid_alrm(rtc, tm) < 0) { 479 dev_err(dev, "Alarm can be set only on upcoming month.\n"); 480 return -EINVAL; 481 } 482 483 alrmar = 0; 484 /* tm_year and tm_mon are not used because not supported by RTC */ 485 alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) & 486 STM32_RTC_ALRMXR_DATE; 487 /* 24-hour format */ 488 alrmar &= ~STM32_RTC_ALRMXR_PM; 489 alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) & 490 STM32_RTC_ALRMXR_HOUR; 491 alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) & 492 STM32_RTC_ALRMXR_MIN; 493 alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) & 494 STM32_RTC_ALRMXR_SEC; 495 496 stm32_rtc_wpr_unlock(rtc); 497 498 /* Disable Alarm */ 499 cr = readl_relaxed(rtc->base + regs->cr); 500 cr &= ~STM32_RTC_CR_ALRAE; 501 writel_relaxed(cr, rtc->base + regs->cr); 502 503 /* 504 * Poll Alarm write flag to be sure that Alarm update is allowed: it 505 * takes around 2 rtc_ck clock cycles 506 */ 507 ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, 508 isr, 509 (isr & STM32_RTC_ISR_ALRAWF), 510 10, 100000); 511 512 if (ret) { 513 dev_err(dev, "Alarm update not allowed\n"); 514 goto end; 515 } 516 517 /* Write to Alarm register */ 518 writel_relaxed(alrmar, rtc->base + regs->alrmar); 519 520 stm32_rtc_alarm_irq_enable(dev, alrm->enabled); 521 end: 522 stm32_rtc_wpr_lock(rtc); 523 524 return ret; 525 } 526 527 static const struct rtc_class_ops stm32_rtc_ops = { 528 .read_time = stm32_rtc_read_time, 529 .set_time = stm32_rtc_set_time, 530 .read_alarm = stm32_rtc_read_alarm, 531 .set_alarm = stm32_rtc_set_alarm, 532 .alarm_irq_enable = stm32_rtc_alarm_irq_enable, 533 }; 534 535 static void stm32_rtc_clear_events(struct stm32_rtc *rtc, 536 unsigned int flags) 537 { 538 const struct stm32_rtc_registers *regs = &rtc->data->regs; 539 540 /* Flags are cleared by writing 0 in RTC_ISR */ 541 writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags, 542 rtc->base + regs->isr); 543 } 544 545 static const struct stm32_rtc_data stm32_rtc_data = { 546 .has_pclk = false, 547 .need_dbp = true, 548 .regs = { 549 .tr = 0x00, 550 .dr = 0x04, 551 .cr = 0x08, 552 .isr = 0x0C, 553 .prer = 0x10, 554 .alrmar = 0x1C, 555 .wpr = 0x24, 556 .sr = 0x0C, /* set to ISR offset to ease alarm management */ 557 .scr = UNDEF_REG, 558 .verr = UNDEF_REG, 559 }, 560 .events = { 561 .alra = STM32_RTC_ISR_ALRAF, 562 }, 563 .clear_events = stm32_rtc_clear_events, 564 }; 565 566 static const struct stm32_rtc_data stm32h7_rtc_data = { 567 .has_pclk = true, 568 .need_dbp = true, 569 .regs = { 570 .tr = 0x00, 571 .dr = 0x04, 572 .cr = 0x08, 573 .isr = 0x0C, 574 .prer = 0x10, 575 .alrmar = 0x1C, 576 .wpr = 0x24, 577 .sr = 0x0C, /* set to ISR offset to ease alarm management */ 578 .scr = UNDEF_REG, 579 .verr = UNDEF_REG, 580 }, 581 .events = { 582 .alra = STM32_RTC_ISR_ALRAF, 583 }, 584 .clear_events = stm32_rtc_clear_events, 585 }; 586 587 static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc, 588 unsigned int flags) 589 { 590 struct stm32_rtc_registers regs = rtc->data->regs; 591 592 /* Flags are cleared by writing 1 in RTC_SCR */ 593 writel_relaxed(flags, rtc->base + regs.scr); 594 } 595 596 static const struct stm32_rtc_data stm32mp1_data = { 597 .has_pclk = true, 598 .need_dbp = false, 599 .regs = { 600 .tr = 0x00, 601 .dr = 0x04, 602 .cr = 0x18, 603 .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */ 604 .prer = 0x10, 605 .alrmar = 0x40, 606 .wpr = 0x24, 607 .sr = 0x50, 608 .scr = 0x5C, 609 .verr = 0x3F4, 610 }, 611 .events = { 612 .alra = STM32_RTC_SR_ALRA, 613 }, 614 .clear_events = stm32mp1_rtc_clear_events, 615 }; 616 617 static const struct of_device_id stm32_rtc_of_match[] = { 618 { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data }, 619 { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data }, 620 { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data }, 621 {} 622 }; 623 MODULE_DEVICE_TABLE(of, stm32_rtc_of_match); 624 625 static int stm32_rtc_init(struct platform_device *pdev, 626 struct stm32_rtc *rtc) 627 { 628 const struct stm32_rtc_registers *regs = &rtc->data->regs; 629 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr; 630 unsigned int rate; 631 int ret = 0; 632 633 rate = clk_get_rate(rtc->rtc_ck); 634 635 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */ 636 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT; 637 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT; 638 639 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) { 640 pred_s = (rate / (pred_a + 1)) - 1; 641 642 if (((pred_s + 1) * (pred_a + 1)) == rate) 643 break; 644 } 645 646 /* 647 * Can't find a 1Hz, so give priority to RTC power consumption 648 * by choosing the higher possible value for prediv_a 649 */ 650 if ((pred_s > pred_s_max) || (pred_a > pred_a_max)) { 651 pred_a = pred_a_max; 652 pred_s = (rate / (pred_a + 1)) - 1; 653 654 dev_warn(&pdev->dev, "rtc_ck is %s\n", 655 (rate < ((pred_a + 1) * (pred_s + 1))) ? 656 "fast" : "slow"); 657 } 658 659 stm32_rtc_wpr_unlock(rtc); 660 661 ret = stm32_rtc_enter_init_mode(rtc); 662 if (ret) { 663 dev_err(&pdev->dev, 664 "Can't enter in init mode. Prescaler config failed.\n"); 665 goto end; 666 } 667 668 prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S; 669 writel_relaxed(prer, rtc->base + regs->prer); 670 prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A; 671 writel_relaxed(prer, rtc->base + regs->prer); 672 673 /* Force 24h time format */ 674 cr = readl_relaxed(rtc->base + regs->cr); 675 cr &= ~STM32_RTC_CR_FMT; 676 writel_relaxed(cr, rtc->base + regs->cr); 677 678 stm32_rtc_exit_init_mode(rtc); 679 680 ret = stm32_rtc_wait_sync(rtc); 681 end: 682 stm32_rtc_wpr_lock(rtc); 683 684 return ret; 685 } 686 687 static int stm32_rtc_probe(struct platform_device *pdev) 688 { 689 struct stm32_rtc *rtc; 690 const struct stm32_rtc_registers *regs; 691 int ret; 692 693 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 694 if (!rtc) 695 return -ENOMEM; 696 697 rtc->base = devm_platform_ioremap_resource(pdev, 0); 698 if (IS_ERR(rtc->base)) 699 return PTR_ERR(rtc->base); 700 701 rtc->data = (struct stm32_rtc_data *) 702 of_device_get_match_data(&pdev->dev); 703 regs = &rtc->data->regs; 704 705 if (rtc->data->need_dbp) { 706 rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 707 "st,syscfg"); 708 if (IS_ERR(rtc->dbp)) { 709 dev_err(&pdev->dev, "no st,syscfg\n"); 710 return PTR_ERR(rtc->dbp); 711 } 712 713 ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg", 714 1, &rtc->dbp_reg); 715 if (ret) { 716 dev_err(&pdev->dev, "can't read DBP register offset\n"); 717 return ret; 718 } 719 720 ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg", 721 2, &rtc->dbp_mask); 722 if (ret) { 723 dev_err(&pdev->dev, "can't read DBP register mask\n"); 724 return ret; 725 } 726 } 727 728 if (!rtc->data->has_pclk) { 729 rtc->pclk = NULL; 730 rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL); 731 } else { 732 rtc->pclk = devm_clk_get(&pdev->dev, "pclk"); 733 if (IS_ERR(rtc->pclk)) { 734 dev_err(&pdev->dev, "no pclk clock"); 735 return PTR_ERR(rtc->pclk); 736 } 737 rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck"); 738 } 739 if (IS_ERR(rtc->rtc_ck)) { 740 dev_err(&pdev->dev, "no rtc_ck clock"); 741 return PTR_ERR(rtc->rtc_ck); 742 } 743 744 if (rtc->data->has_pclk) { 745 ret = clk_prepare_enable(rtc->pclk); 746 if (ret) 747 return ret; 748 } 749 750 ret = clk_prepare_enable(rtc->rtc_ck); 751 if (ret) 752 goto err_no_rtc_ck; 753 754 if (rtc->data->need_dbp) 755 regmap_update_bits(rtc->dbp, rtc->dbp_reg, 756 rtc->dbp_mask, rtc->dbp_mask); 757 758 /* 759 * After a system reset, RTC_ISR.INITS flag can be read to check if 760 * the calendar has been initialized or not. INITS flag is reset by a 761 * power-on reset (no vbat, no power-supply). It is not reset if 762 * rtc_ck parent clock has changed (so RTC prescalers need to be 763 * changed). That's why we cannot rely on this flag to know if RTC 764 * init has to be done. 765 */ 766 ret = stm32_rtc_init(pdev, rtc); 767 if (ret) 768 goto err; 769 770 rtc->irq_alarm = platform_get_irq(pdev, 0); 771 if (rtc->irq_alarm <= 0) { 772 ret = rtc->irq_alarm; 773 goto err; 774 } 775 776 ret = device_init_wakeup(&pdev->dev, true); 777 if (ret) 778 goto err; 779 780 ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq_alarm); 781 if (ret) 782 goto err; 783 784 platform_set_drvdata(pdev, rtc); 785 786 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name, 787 &stm32_rtc_ops, THIS_MODULE); 788 if (IS_ERR(rtc->rtc_dev)) { 789 ret = PTR_ERR(rtc->rtc_dev); 790 dev_err(&pdev->dev, "rtc device registration failed, err=%d\n", 791 ret); 792 goto err; 793 } 794 795 /* Handle RTC alarm interrupts */ 796 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL, 797 stm32_rtc_alarm_irq, IRQF_ONESHOT, 798 pdev->name, rtc); 799 if (ret) { 800 dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n", 801 rtc->irq_alarm); 802 goto err; 803 } 804 805 /* 806 * If INITS flag is reset (calendar year field set to 0x00), calendar 807 * must be initialized 808 */ 809 if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS)) 810 dev_warn(&pdev->dev, "Date/Time must be initialized\n"); 811 812 if (regs->verr != UNDEF_REG) { 813 u32 ver = readl_relaxed(rtc->base + regs->verr); 814 815 dev_info(&pdev->dev, "registered rev:%d.%d\n", 816 (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF, 817 (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF); 818 } 819 820 return 0; 821 822 err: 823 clk_disable_unprepare(rtc->rtc_ck); 824 err_no_rtc_ck: 825 if (rtc->data->has_pclk) 826 clk_disable_unprepare(rtc->pclk); 827 828 if (rtc->data->need_dbp) 829 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); 830 831 dev_pm_clear_wake_irq(&pdev->dev); 832 device_init_wakeup(&pdev->dev, false); 833 834 return ret; 835 } 836 837 static void stm32_rtc_remove(struct platform_device *pdev) 838 { 839 struct stm32_rtc *rtc = platform_get_drvdata(pdev); 840 const struct stm32_rtc_registers *regs = &rtc->data->regs; 841 unsigned int cr; 842 843 /* Disable interrupts */ 844 stm32_rtc_wpr_unlock(rtc); 845 cr = readl_relaxed(rtc->base + regs->cr); 846 cr &= ~STM32_RTC_CR_ALRAIE; 847 writel_relaxed(cr, rtc->base + regs->cr); 848 stm32_rtc_wpr_lock(rtc); 849 850 clk_disable_unprepare(rtc->rtc_ck); 851 if (rtc->data->has_pclk) 852 clk_disable_unprepare(rtc->pclk); 853 854 /* Enable backup domain write protection if needed */ 855 if (rtc->data->need_dbp) 856 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); 857 858 dev_pm_clear_wake_irq(&pdev->dev); 859 device_init_wakeup(&pdev->dev, false); 860 } 861 862 #ifdef CONFIG_PM_SLEEP 863 static int stm32_rtc_suspend(struct device *dev) 864 { 865 struct stm32_rtc *rtc = dev_get_drvdata(dev); 866 867 if (rtc->data->has_pclk) 868 clk_disable_unprepare(rtc->pclk); 869 870 return 0; 871 } 872 873 static int stm32_rtc_resume(struct device *dev) 874 { 875 struct stm32_rtc *rtc = dev_get_drvdata(dev); 876 int ret = 0; 877 878 if (rtc->data->has_pclk) { 879 ret = clk_prepare_enable(rtc->pclk); 880 if (ret) 881 return ret; 882 } 883 884 ret = stm32_rtc_wait_sync(rtc); 885 if (ret < 0) { 886 if (rtc->data->has_pclk) 887 clk_disable_unprepare(rtc->pclk); 888 return ret; 889 } 890 891 return ret; 892 } 893 #endif 894 895 static SIMPLE_DEV_PM_OPS(stm32_rtc_pm_ops, 896 stm32_rtc_suspend, stm32_rtc_resume); 897 898 static struct platform_driver stm32_rtc_driver = { 899 .probe = stm32_rtc_probe, 900 .remove_new = stm32_rtc_remove, 901 .driver = { 902 .name = DRIVER_NAME, 903 .pm = &stm32_rtc_pm_ops, 904 .of_match_table = stm32_rtc_of_match, 905 }, 906 }; 907 908 module_platform_driver(stm32_rtc_driver); 909 910 MODULE_ALIAS("platform:" DRIVER_NAME); 911 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 912 MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver"); 913 MODULE_LICENSE("GPL v2"); 914