1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc. 4 5 #include <linux/init.h> 6 #include <linux/io.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_wakeirq.h> 12 #include <linux/rtc.h> 13 #include <linux/clk.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/regmap.h> 16 17 #define SNVS_LPREGISTER_OFFSET 0x34 18 19 /* These register offsets are relative to LP (Low Power) range */ 20 #define SNVS_LPCR 0x04 21 #define SNVS_LPSR 0x18 22 #define SNVS_LPSRTCMR 0x1c 23 #define SNVS_LPSRTCLR 0x20 24 #define SNVS_LPTAR 0x24 25 #define SNVS_LPPGDR 0x30 26 27 #define SNVS_LPCR_SRTC_ENV (1 << 0) 28 #define SNVS_LPCR_LPTA_EN (1 << 1) 29 #define SNVS_LPCR_LPWUI_EN (1 << 3) 30 #define SNVS_LPSR_LPTA (1 << 0) 31 32 #define SNVS_LPPGDR_INIT 0x41736166 33 #define CNTR_TO_SECS_SH 15 34 35 struct snvs_rtc_data { 36 struct rtc_device *rtc; 37 struct regmap *regmap; 38 int offset; 39 int irq; 40 struct clk *clk; 41 }; 42 43 /* Read 64 bit timer register, which could be in inconsistent state */ 44 static u64 rtc_read_lpsrt(struct snvs_rtc_data *data) 45 { 46 u32 msb, lsb; 47 48 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb); 49 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb); 50 return (u64)msb << 32 | lsb; 51 } 52 53 /* Read the secure real time counter, taking care to deal with the cases of the 54 * counter updating while being read. 55 */ 56 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data) 57 { 58 u64 read1, read2; 59 unsigned int timeout = 100; 60 61 /* As expected, the registers might update between the read of the LSB 62 * reg and the MSB reg. It's also possible that one register might be 63 * in partially modified state as well. 64 */ 65 read1 = rtc_read_lpsrt(data); 66 do { 67 read2 = read1; 68 read1 = rtc_read_lpsrt(data); 69 } while (read1 != read2 && --timeout); 70 if (!timeout) 71 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n"); 72 73 /* Convert 47-bit counter to 32-bit raw second count */ 74 return (u32) (read1 >> CNTR_TO_SECS_SH); 75 } 76 77 /* Just read the lsb from the counter, dealing with inconsistent state */ 78 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb) 79 { 80 u32 count1, count2; 81 unsigned int timeout = 100; 82 83 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); 84 do { 85 count2 = count1; 86 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); 87 } while (count1 != count2 && --timeout); 88 if (!timeout) { 89 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n"); 90 return -ETIMEDOUT; 91 } 92 93 *lsb = count1; 94 return 0; 95 } 96 97 static int rtc_write_sync_lp(struct snvs_rtc_data *data) 98 { 99 u32 count1, count2; 100 u32 elapsed; 101 unsigned int timeout = 1000; 102 int ret; 103 104 ret = rtc_read_lp_counter_lsb(data, &count1); 105 if (ret) 106 return ret; 107 108 /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */ 109 do { 110 ret = rtc_read_lp_counter_lsb(data, &count2); 111 if (ret) 112 return ret; 113 elapsed = count2 - count1; /* wrap around _is_ handled! */ 114 } while (elapsed < 3 && --timeout); 115 if (!timeout) { 116 dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n"); 117 return -ETIMEDOUT; 118 } 119 return 0; 120 } 121 122 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable) 123 { 124 int timeout = 1000; 125 u32 lpcr; 126 127 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV, 128 enable ? SNVS_LPCR_SRTC_ENV : 0); 129 130 while (--timeout) { 131 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr); 132 133 if (enable) { 134 if (lpcr & SNVS_LPCR_SRTC_ENV) 135 break; 136 } else { 137 if (!(lpcr & SNVS_LPCR_SRTC_ENV)) 138 break; 139 } 140 } 141 142 if (!timeout) 143 return -ETIMEDOUT; 144 145 return 0; 146 } 147 148 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm) 149 { 150 struct snvs_rtc_data *data = dev_get_drvdata(dev); 151 unsigned long time; 152 int ret; 153 154 ret = clk_enable(data->clk); 155 if (ret) 156 return ret; 157 158 time = rtc_read_lp_counter(data); 159 rtc_time64_to_tm(time, tm); 160 161 clk_disable(data->clk); 162 163 return 0; 164 } 165 166 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm) 167 { 168 struct snvs_rtc_data *data = dev_get_drvdata(dev); 169 unsigned long time = rtc_tm_to_time64(tm); 170 int ret; 171 172 ret = clk_enable(data->clk); 173 if (ret) 174 return ret; 175 176 /* Disable RTC first */ 177 ret = snvs_rtc_enable(data, false); 178 if (ret) 179 return ret; 180 181 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */ 182 regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH); 183 regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH)); 184 185 /* Enable RTC again */ 186 ret = snvs_rtc_enable(data, true); 187 188 clk_disable(data->clk); 189 190 return ret; 191 } 192 193 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 194 { 195 struct snvs_rtc_data *data = dev_get_drvdata(dev); 196 u32 lptar, lpsr; 197 int ret; 198 199 ret = clk_enable(data->clk); 200 if (ret) 201 return ret; 202 203 regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar); 204 rtc_time64_to_tm(lptar, &alrm->time); 205 206 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); 207 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0; 208 209 clk_disable(data->clk); 210 211 return 0; 212 } 213 214 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) 215 { 216 struct snvs_rtc_data *data = dev_get_drvdata(dev); 217 int ret; 218 219 ret = clk_enable(data->clk); 220 if (ret) 221 return ret; 222 223 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, 224 (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN), 225 enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0); 226 227 ret = rtc_write_sync_lp(data); 228 229 clk_disable(data->clk); 230 231 return ret; 232 } 233 234 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 235 { 236 struct snvs_rtc_data *data = dev_get_drvdata(dev); 237 unsigned long time = rtc_tm_to_time64(&alrm->time); 238 int ret; 239 240 ret = clk_enable(data->clk); 241 if (ret) 242 return ret; 243 244 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0); 245 ret = rtc_write_sync_lp(data); 246 if (ret) 247 return ret; 248 regmap_write(data->regmap, data->offset + SNVS_LPTAR, time); 249 250 /* Clear alarm interrupt status bit */ 251 regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA); 252 253 clk_disable(data->clk); 254 255 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled); 256 } 257 258 static const struct rtc_class_ops snvs_rtc_ops = { 259 .read_time = snvs_rtc_read_time, 260 .set_time = snvs_rtc_set_time, 261 .read_alarm = snvs_rtc_read_alarm, 262 .set_alarm = snvs_rtc_set_alarm, 263 .alarm_irq_enable = snvs_rtc_alarm_irq_enable, 264 }; 265 266 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id) 267 { 268 struct device *dev = dev_id; 269 struct snvs_rtc_data *data = dev_get_drvdata(dev); 270 u32 lpsr; 271 u32 events = 0; 272 273 clk_enable(data->clk); 274 275 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); 276 277 if (lpsr & SNVS_LPSR_LPTA) { 278 events |= (RTC_AF | RTC_IRQF); 279 280 /* RTC alarm should be one-shot */ 281 snvs_rtc_alarm_irq_enable(dev, 0); 282 283 rtc_update_irq(data->rtc, 1, events); 284 } 285 286 /* clear interrupt status */ 287 regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr); 288 289 clk_disable(data->clk); 290 291 return events ? IRQ_HANDLED : IRQ_NONE; 292 } 293 294 static const struct regmap_config snvs_rtc_config = { 295 .reg_bits = 32, 296 .val_bits = 32, 297 .reg_stride = 4, 298 }; 299 300 static void snvs_rtc_action(void *data) 301 { 302 clk_disable_unprepare(data); 303 } 304 305 static int snvs_rtc_probe(struct platform_device *pdev) 306 { 307 struct snvs_rtc_data *data; 308 int ret; 309 void __iomem *mmio; 310 311 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 312 if (!data) 313 return -ENOMEM; 314 315 data->rtc = devm_rtc_allocate_device(&pdev->dev); 316 if (IS_ERR(data->rtc)) 317 return PTR_ERR(data->rtc); 318 319 data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap"); 320 321 if (IS_ERR(data->regmap)) { 322 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n"); 323 324 mmio = devm_platform_ioremap_resource(pdev, 0); 325 if (IS_ERR(mmio)) 326 return PTR_ERR(mmio); 327 328 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config); 329 } else { 330 data->offset = SNVS_LPREGISTER_OFFSET; 331 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset); 332 } 333 334 if (IS_ERR(data->regmap)) { 335 dev_err(&pdev->dev, "Can't find snvs syscon\n"); 336 return -ENODEV; 337 } 338 339 data->irq = platform_get_irq(pdev, 0); 340 if (data->irq < 0) 341 return data->irq; 342 343 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc"); 344 if (IS_ERR(data->clk)) { 345 data->clk = NULL; 346 } else { 347 ret = clk_prepare_enable(data->clk); 348 if (ret) { 349 dev_err(&pdev->dev, 350 "Could not prepare or enable the snvs clock\n"); 351 return ret; 352 } 353 } 354 355 ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk); 356 if (ret) 357 return ret; 358 359 platform_set_drvdata(pdev, data); 360 361 /* Initialize glitch detect */ 362 regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT); 363 364 /* Clear interrupt status */ 365 regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff); 366 367 /* Enable RTC */ 368 ret = snvs_rtc_enable(data, true); 369 if (ret) { 370 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret); 371 return ret; 372 } 373 374 device_init_wakeup(&pdev->dev, true); 375 ret = dev_pm_set_wake_irq(&pdev->dev, data->irq); 376 if (ret) 377 dev_err(&pdev->dev, "failed to enable irq wake\n"); 378 379 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler, 380 IRQF_SHARED, "rtc alarm", &pdev->dev); 381 if (ret) { 382 dev_err(&pdev->dev, "failed to request irq %d: %d\n", 383 data->irq, ret); 384 return ret; 385 } 386 387 data->rtc->ops = &snvs_rtc_ops; 388 data->rtc->range_max = U32_MAX; 389 390 return devm_rtc_register_device(data->rtc); 391 } 392 393 static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev) 394 { 395 struct snvs_rtc_data *data = dev_get_drvdata(dev); 396 397 clk_disable(data->clk); 398 399 return 0; 400 } 401 402 static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev) 403 { 404 struct snvs_rtc_data *data = dev_get_drvdata(dev); 405 406 if (data->clk) 407 return clk_enable(data->clk); 408 409 return 0; 410 } 411 412 static const struct dev_pm_ops snvs_rtc_pm_ops = { 413 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq) 414 }; 415 416 static const struct of_device_id snvs_dt_ids[] = { 417 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", }, 418 { /* sentinel */ } 419 }; 420 MODULE_DEVICE_TABLE(of, snvs_dt_ids); 421 422 static struct platform_driver snvs_rtc_driver = { 423 .driver = { 424 .name = "snvs_rtc", 425 .pm = &snvs_rtc_pm_ops, 426 .of_match_table = snvs_dt_ids, 427 }, 428 .probe = snvs_rtc_probe, 429 }; 430 module_platform_driver(snvs_rtc_driver); 431 432 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 433 MODULE_DESCRIPTION("Freescale SNVS RTC Driver"); 434 MODULE_LICENSE("GPL"); 435