1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc. 4 5 #include <linux/init.h> 6 #include <linux/io.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_wakeirq.h> 12 #include <linux/rtc.h> 13 #include <linux/clk.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/regmap.h> 16 17 #define SNVS_LPREGISTER_OFFSET 0x34 18 19 /* These register offsets are relative to LP (Low Power) range */ 20 #define SNVS_LPCR 0x04 21 #define SNVS_LPSR 0x18 22 #define SNVS_LPSRTCMR 0x1c 23 #define SNVS_LPSRTCLR 0x20 24 #define SNVS_LPTAR 0x24 25 #define SNVS_LPPGDR 0x30 26 27 #define SNVS_LPCR_SRTC_ENV (1 << 0) 28 #define SNVS_LPCR_LPTA_EN (1 << 1) 29 #define SNVS_LPCR_LPWUI_EN (1 << 3) 30 #define SNVS_LPSR_LPTA (1 << 0) 31 32 #define SNVS_LPPGDR_INIT 0x41736166 33 #define CNTR_TO_SECS_SH 15 34 35 struct snvs_rtc_data { 36 struct rtc_device *rtc; 37 struct regmap *regmap; 38 int offset; 39 int irq; 40 struct clk *clk; 41 }; 42 43 /* Read 64 bit timer register, which could be in inconsistent state */ 44 static u64 rtc_read_lpsrt(struct snvs_rtc_data *data) 45 { 46 u32 msb, lsb; 47 48 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb); 49 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb); 50 return (u64)msb << 32 | lsb; 51 } 52 53 /* Read the secure real time counter, taking care to deal with the cases of the 54 * counter updating while being read. 55 */ 56 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data) 57 { 58 u64 read1, read2; 59 unsigned int timeout = 100; 60 61 /* As expected, the registers might update between the read of the LSB 62 * reg and the MSB reg. It's also possible that one register might be 63 * in partially modified state as well. 64 */ 65 read1 = rtc_read_lpsrt(data); 66 do { 67 read2 = read1; 68 read1 = rtc_read_lpsrt(data); 69 } while (read1 != read2 && --timeout); 70 if (!timeout) 71 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n"); 72 73 /* Convert 47-bit counter to 32-bit raw second count */ 74 return (u32) (read1 >> CNTR_TO_SECS_SH); 75 } 76 77 /* Just read the lsb from the counter, dealing with inconsistent state */ 78 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb) 79 { 80 u32 count1, count2; 81 unsigned int timeout = 100; 82 83 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); 84 do { 85 count2 = count1; 86 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); 87 } while (count1 != count2 && --timeout); 88 if (!timeout) { 89 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n"); 90 return -ETIMEDOUT; 91 } 92 93 *lsb = count1; 94 return 0; 95 } 96 97 static int rtc_write_sync_lp(struct snvs_rtc_data *data) 98 { 99 u32 count1, count2; 100 u32 elapsed; 101 unsigned int timeout = 1000; 102 int ret; 103 104 ret = rtc_read_lp_counter_lsb(data, &count1); 105 if (ret) 106 return ret; 107 108 /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */ 109 do { 110 ret = rtc_read_lp_counter_lsb(data, &count2); 111 if (ret) 112 return ret; 113 elapsed = count2 - count1; /* wrap around _is_ handled! */ 114 } while (elapsed < 3 && --timeout); 115 if (!timeout) { 116 dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n"); 117 return -ETIMEDOUT; 118 } 119 return 0; 120 } 121 122 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable) 123 { 124 int timeout = 1000; 125 u32 lpcr; 126 127 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV, 128 enable ? SNVS_LPCR_SRTC_ENV : 0); 129 130 while (--timeout) { 131 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr); 132 133 if (enable) { 134 if (lpcr & SNVS_LPCR_SRTC_ENV) 135 break; 136 } else { 137 if (!(lpcr & SNVS_LPCR_SRTC_ENV)) 138 break; 139 } 140 } 141 142 if (!timeout) 143 return -ETIMEDOUT; 144 145 return 0; 146 } 147 148 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm) 149 { 150 struct snvs_rtc_data *data = dev_get_drvdata(dev); 151 unsigned long time; 152 int ret; 153 154 if (data->clk) { 155 ret = clk_enable(data->clk); 156 if (ret) 157 return ret; 158 } 159 160 time = rtc_read_lp_counter(data); 161 rtc_time64_to_tm(time, tm); 162 163 if (data->clk) 164 clk_disable(data->clk); 165 166 return 0; 167 } 168 169 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm) 170 { 171 struct snvs_rtc_data *data = dev_get_drvdata(dev); 172 unsigned long time = rtc_tm_to_time64(tm); 173 int ret; 174 175 if (data->clk) { 176 ret = clk_enable(data->clk); 177 if (ret) 178 return ret; 179 } 180 181 /* Disable RTC first */ 182 ret = snvs_rtc_enable(data, false); 183 if (ret) 184 return ret; 185 186 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */ 187 regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH); 188 regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH)); 189 190 /* Enable RTC again */ 191 ret = snvs_rtc_enable(data, true); 192 193 if (data->clk) 194 clk_disable(data->clk); 195 196 return ret; 197 } 198 199 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 200 { 201 struct snvs_rtc_data *data = dev_get_drvdata(dev); 202 u32 lptar, lpsr; 203 int ret; 204 205 if (data->clk) { 206 ret = clk_enable(data->clk); 207 if (ret) 208 return ret; 209 } 210 211 regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar); 212 rtc_time64_to_tm(lptar, &alrm->time); 213 214 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); 215 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0; 216 217 if (data->clk) 218 clk_disable(data->clk); 219 220 return 0; 221 } 222 223 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) 224 { 225 struct snvs_rtc_data *data = dev_get_drvdata(dev); 226 int ret; 227 228 if (data->clk) { 229 ret = clk_enable(data->clk); 230 if (ret) 231 return ret; 232 } 233 234 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, 235 (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN), 236 enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0); 237 238 ret = rtc_write_sync_lp(data); 239 240 if (data->clk) 241 clk_disable(data->clk); 242 243 return ret; 244 } 245 246 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 247 { 248 struct snvs_rtc_data *data = dev_get_drvdata(dev); 249 unsigned long time = rtc_tm_to_time64(&alrm->time); 250 int ret; 251 252 if (data->clk) { 253 ret = clk_enable(data->clk); 254 if (ret) 255 return ret; 256 } 257 258 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0); 259 ret = rtc_write_sync_lp(data); 260 if (ret) 261 return ret; 262 regmap_write(data->regmap, data->offset + SNVS_LPTAR, time); 263 264 /* Clear alarm interrupt status bit */ 265 regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA); 266 267 if (data->clk) 268 clk_disable(data->clk); 269 270 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled); 271 } 272 273 static const struct rtc_class_ops snvs_rtc_ops = { 274 .read_time = snvs_rtc_read_time, 275 .set_time = snvs_rtc_set_time, 276 .read_alarm = snvs_rtc_read_alarm, 277 .set_alarm = snvs_rtc_set_alarm, 278 .alarm_irq_enable = snvs_rtc_alarm_irq_enable, 279 }; 280 281 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id) 282 { 283 struct device *dev = dev_id; 284 struct snvs_rtc_data *data = dev_get_drvdata(dev); 285 u32 lpsr; 286 u32 events = 0; 287 288 if (data->clk) 289 clk_enable(data->clk); 290 291 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); 292 293 if (lpsr & SNVS_LPSR_LPTA) { 294 events |= (RTC_AF | RTC_IRQF); 295 296 /* RTC alarm should be one-shot */ 297 snvs_rtc_alarm_irq_enable(dev, 0); 298 299 rtc_update_irq(data->rtc, 1, events); 300 } 301 302 /* clear interrupt status */ 303 regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr); 304 305 if (data->clk) 306 clk_disable(data->clk); 307 308 return events ? IRQ_HANDLED : IRQ_NONE; 309 } 310 311 static const struct regmap_config snvs_rtc_config = { 312 .reg_bits = 32, 313 .val_bits = 32, 314 .reg_stride = 4, 315 }; 316 317 static void snvs_rtc_action(void *data) 318 { 319 if (data) 320 clk_disable_unprepare(data); 321 } 322 323 static int snvs_rtc_probe(struct platform_device *pdev) 324 { 325 struct snvs_rtc_data *data; 326 int ret; 327 void __iomem *mmio; 328 329 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 330 if (!data) 331 return -ENOMEM; 332 333 data->rtc = devm_rtc_allocate_device(&pdev->dev); 334 if (IS_ERR(data->rtc)) 335 return PTR_ERR(data->rtc); 336 337 data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap"); 338 339 if (IS_ERR(data->regmap)) { 340 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n"); 341 342 mmio = devm_platform_ioremap_resource(pdev, 0); 343 if (IS_ERR(mmio)) 344 return PTR_ERR(mmio); 345 346 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config); 347 } else { 348 data->offset = SNVS_LPREGISTER_OFFSET; 349 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset); 350 } 351 352 if (IS_ERR(data->regmap)) { 353 dev_err(&pdev->dev, "Can't find snvs syscon\n"); 354 return -ENODEV; 355 } 356 357 data->irq = platform_get_irq(pdev, 0); 358 if (data->irq < 0) 359 return data->irq; 360 361 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc"); 362 if (IS_ERR(data->clk)) { 363 data->clk = NULL; 364 } else { 365 ret = clk_prepare_enable(data->clk); 366 if (ret) { 367 dev_err(&pdev->dev, 368 "Could not prepare or enable the snvs clock\n"); 369 return ret; 370 } 371 } 372 373 ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk); 374 if (ret) 375 return ret; 376 377 platform_set_drvdata(pdev, data); 378 379 /* Initialize glitch detect */ 380 regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT); 381 382 /* Clear interrupt status */ 383 regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff); 384 385 /* Enable RTC */ 386 ret = snvs_rtc_enable(data, true); 387 if (ret) { 388 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret); 389 return ret; 390 } 391 392 device_init_wakeup(&pdev->dev, true); 393 ret = dev_pm_set_wake_irq(&pdev->dev, data->irq); 394 if (ret) 395 dev_err(&pdev->dev, "failed to enable irq wake\n"); 396 397 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler, 398 IRQF_SHARED, "rtc alarm", &pdev->dev); 399 if (ret) { 400 dev_err(&pdev->dev, "failed to request irq %d: %d\n", 401 data->irq, ret); 402 return ret; 403 } 404 405 data->rtc->ops = &snvs_rtc_ops; 406 data->rtc->range_max = U32_MAX; 407 408 return rtc_register_device(data->rtc); 409 } 410 411 static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev) 412 { 413 struct snvs_rtc_data *data = dev_get_drvdata(dev); 414 415 if (data->clk) 416 clk_disable(data->clk); 417 418 return 0; 419 } 420 421 static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev) 422 { 423 struct snvs_rtc_data *data = dev_get_drvdata(dev); 424 425 if (data->clk) 426 return clk_enable(data->clk); 427 428 return 0; 429 } 430 431 static const struct dev_pm_ops snvs_rtc_pm_ops = { 432 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq) 433 }; 434 435 static const struct of_device_id snvs_dt_ids[] = { 436 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", }, 437 { /* sentinel */ } 438 }; 439 MODULE_DEVICE_TABLE(of, snvs_dt_ids); 440 441 static struct platform_driver snvs_rtc_driver = { 442 .driver = { 443 .name = "snvs_rtc", 444 .pm = &snvs_rtc_pm_ops, 445 .of_match_table = snvs_dt_ids, 446 }, 447 .probe = snvs_rtc_probe, 448 }; 449 module_platform_driver(snvs_rtc_driver); 450 451 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 452 MODULE_DESCRIPTION("Freescale SNVS RTC Driver"); 453 MODULE_LICENSE("GPL"); 454