1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc. 4 5 #include <linux/init.h> 6 #include <linux/io.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_wakeirq.h> 12 #include <linux/rtc.h> 13 #include <linux/clk.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/regmap.h> 16 17 #define SNVS_LPREGISTER_OFFSET 0x34 18 19 /* These register offsets are relative to LP (Low Power) range */ 20 #define SNVS_LPCR 0x04 21 #define SNVS_LPSR 0x18 22 #define SNVS_LPSRTCMR 0x1c 23 #define SNVS_LPSRTCLR 0x20 24 #define SNVS_LPTAR 0x24 25 #define SNVS_LPPGDR 0x30 26 27 #define SNVS_LPCR_SRTC_ENV (1 << 0) 28 #define SNVS_LPCR_LPTA_EN (1 << 1) 29 #define SNVS_LPCR_LPWUI_EN (1 << 3) 30 #define SNVS_LPSR_LPTA (1 << 0) 31 32 #define SNVS_LPPGDR_INIT 0x41736166 33 #define CNTR_TO_SECS_SH 15 34 35 struct snvs_rtc_data { 36 struct rtc_device *rtc; 37 struct regmap *regmap; 38 int offset; 39 int irq; 40 struct clk *clk; 41 }; 42 43 /* Read 64 bit timer register, which could be in inconsistent state */ 44 static u64 rtc_read_lpsrt(struct snvs_rtc_data *data) 45 { 46 u32 msb, lsb; 47 48 regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb); 49 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb); 50 return (u64)msb << 32 | lsb; 51 } 52 53 /* Read the secure real time counter, taking care to deal with the cases of the 54 * counter updating while being read. 55 */ 56 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data) 57 { 58 u64 read1, read2; 59 unsigned int timeout = 100; 60 61 /* As expected, the registers might update between the read of the LSB 62 * reg and the MSB reg. It's also possible that one register might be 63 * in partially modified state as well. 64 */ 65 read1 = rtc_read_lpsrt(data); 66 do { 67 read2 = read1; 68 read1 = rtc_read_lpsrt(data); 69 } while (read1 != read2 && --timeout); 70 if (!timeout) 71 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n"); 72 73 /* Convert 47-bit counter to 32-bit raw second count */ 74 return (u32) (read1 >> CNTR_TO_SECS_SH); 75 } 76 77 /* Just read the lsb from the counter, dealing with inconsistent state */ 78 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb) 79 { 80 u32 count1, count2; 81 unsigned int timeout = 100; 82 83 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); 84 do { 85 count2 = count1; 86 regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1); 87 } while (count1 != count2 && --timeout); 88 if (!timeout) { 89 dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n"); 90 return -ETIMEDOUT; 91 } 92 93 *lsb = count1; 94 return 0; 95 } 96 97 static int rtc_write_sync_lp(struct snvs_rtc_data *data) 98 { 99 u32 count1, count2; 100 u32 elapsed; 101 unsigned int timeout = 1000; 102 int ret; 103 104 ret = rtc_read_lp_counter_lsb(data, &count1); 105 if (ret) 106 return ret; 107 108 /* Wait for 3 CKIL cycles, about 61.0-91.5 µs */ 109 do { 110 ret = rtc_read_lp_counter_lsb(data, &count2); 111 if (ret) 112 return ret; 113 elapsed = count2 - count1; /* wrap around _is_ handled! */ 114 } while (elapsed < 3 && --timeout); 115 if (!timeout) { 116 dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n"); 117 return -ETIMEDOUT; 118 } 119 return 0; 120 } 121 122 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable) 123 { 124 int timeout = 1000; 125 u32 lpcr; 126 127 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV, 128 enable ? SNVS_LPCR_SRTC_ENV : 0); 129 130 while (--timeout) { 131 regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr); 132 133 if (enable) { 134 if (lpcr & SNVS_LPCR_SRTC_ENV) 135 break; 136 } else { 137 if (!(lpcr & SNVS_LPCR_SRTC_ENV)) 138 break; 139 } 140 } 141 142 if (!timeout) 143 return -ETIMEDOUT; 144 145 return 0; 146 } 147 148 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm) 149 { 150 struct snvs_rtc_data *data = dev_get_drvdata(dev); 151 unsigned long time = rtc_read_lp_counter(data); 152 153 rtc_time64_to_tm(time, tm); 154 155 return 0; 156 } 157 158 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm) 159 { 160 struct snvs_rtc_data *data = dev_get_drvdata(dev); 161 unsigned long time = rtc_tm_to_time64(tm); 162 int ret; 163 164 /* Disable RTC first */ 165 ret = snvs_rtc_enable(data, false); 166 if (ret) 167 return ret; 168 169 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */ 170 regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH); 171 regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH)); 172 173 /* Enable RTC again */ 174 ret = snvs_rtc_enable(data, true); 175 176 return ret; 177 } 178 179 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 180 { 181 struct snvs_rtc_data *data = dev_get_drvdata(dev); 182 u32 lptar, lpsr; 183 184 regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar); 185 rtc_time64_to_tm(lptar, &alrm->time); 186 187 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); 188 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0; 189 190 return 0; 191 } 192 193 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) 194 { 195 struct snvs_rtc_data *data = dev_get_drvdata(dev); 196 197 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, 198 (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN), 199 enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0); 200 201 return rtc_write_sync_lp(data); 202 } 203 204 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 205 { 206 struct snvs_rtc_data *data = dev_get_drvdata(dev); 207 unsigned long time = rtc_tm_to_time64(&alrm->time); 208 int ret; 209 210 regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0); 211 ret = rtc_write_sync_lp(data); 212 if (ret) 213 return ret; 214 regmap_write(data->regmap, data->offset + SNVS_LPTAR, time); 215 216 /* Clear alarm interrupt status bit */ 217 regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA); 218 219 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled); 220 } 221 222 static const struct rtc_class_ops snvs_rtc_ops = { 223 .read_time = snvs_rtc_read_time, 224 .set_time = snvs_rtc_set_time, 225 .read_alarm = snvs_rtc_read_alarm, 226 .set_alarm = snvs_rtc_set_alarm, 227 .alarm_irq_enable = snvs_rtc_alarm_irq_enable, 228 }; 229 230 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id) 231 { 232 struct device *dev = dev_id; 233 struct snvs_rtc_data *data = dev_get_drvdata(dev); 234 u32 lpsr; 235 u32 events = 0; 236 237 if (data->clk) 238 clk_enable(data->clk); 239 240 regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr); 241 242 if (lpsr & SNVS_LPSR_LPTA) { 243 events |= (RTC_AF | RTC_IRQF); 244 245 /* RTC alarm should be one-shot */ 246 snvs_rtc_alarm_irq_enable(dev, 0); 247 248 rtc_update_irq(data->rtc, 1, events); 249 } 250 251 /* clear interrupt status */ 252 regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr); 253 254 if (data->clk) 255 clk_disable(data->clk); 256 257 return events ? IRQ_HANDLED : IRQ_NONE; 258 } 259 260 static const struct regmap_config snvs_rtc_config = { 261 .reg_bits = 32, 262 .val_bits = 32, 263 .reg_stride = 4, 264 }; 265 266 static void snvs_rtc_action(void *data) 267 { 268 if (data) 269 clk_disable_unprepare(data); 270 } 271 272 static int snvs_rtc_probe(struct platform_device *pdev) 273 { 274 struct snvs_rtc_data *data; 275 int ret; 276 void __iomem *mmio; 277 278 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 279 if (!data) 280 return -ENOMEM; 281 282 data->rtc = devm_rtc_allocate_device(&pdev->dev); 283 if (IS_ERR(data->rtc)) 284 return PTR_ERR(data->rtc); 285 286 data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap"); 287 288 if (IS_ERR(data->regmap)) { 289 dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n"); 290 291 mmio = devm_platform_ioremap_resource(pdev, 0); 292 if (IS_ERR(mmio)) 293 return PTR_ERR(mmio); 294 295 data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config); 296 } else { 297 data->offset = SNVS_LPREGISTER_OFFSET; 298 of_property_read_u32(pdev->dev.of_node, "offset", &data->offset); 299 } 300 301 if (IS_ERR(data->regmap)) { 302 dev_err(&pdev->dev, "Can't find snvs syscon\n"); 303 return -ENODEV; 304 } 305 306 data->irq = platform_get_irq(pdev, 0); 307 if (data->irq < 0) 308 return data->irq; 309 310 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc"); 311 if (IS_ERR(data->clk)) { 312 data->clk = NULL; 313 } else { 314 ret = clk_prepare_enable(data->clk); 315 if (ret) { 316 dev_err(&pdev->dev, 317 "Could not prepare or enable the snvs clock\n"); 318 return ret; 319 } 320 } 321 322 ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk); 323 if (ret) 324 return ret; 325 326 platform_set_drvdata(pdev, data); 327 328 /* Initialize glitch detect */ 329 regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT); 330 331 /* Clear interrupt status */ 332 regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff); 333 334 /* Enable RTC */ 335 ret = snvs_rtc_enable(data, true); 336 if (ret) { 337 dev_err(&pdev->dev, "failed to enable rtc %d\n", ret); 338 return ret; 339 } 340 341 device_init_wakeup(&pdev->dev, true); 342 ret = dev_pm_set_wake_irq(&pdev->dev, data->irq); 343 if (ret) 344 dev_err(&pdev->dev, "failed to enable irq wake\n"); 345 346 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler, 347 IRQF_SHARED, "rtc alarm", &pdev->dev); 348 if (ret) { 349 dev_err(&pdev->dev, "failed to request irq %d: %d\n", 350 data->irq, ret); 351 return ret; 352 } 353 354 data->rtc->ops = &snvs_rtc_ops; 355 data->rtc->range_max = U32_MAX; 356 357 return rtc_register_device(data->rtc); 358 } 359 360 static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev) 361 { 362 struct snvs_rtc_data *data = dev_get_drvdata(dev); 363 364 if (data->clk) 365 clk_disable_unprepare(data->clk); 366 367 return 0; 368 } 369 370 static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev) 371 { 372 struct snvs_rtc_data *data = dev_get_drvdata(dev); 373 374 if (data->clk) 375 return clk_prepare_enable(data->clk); 376 377 return 0; 378 } 379 380 static const struct dev_pm_ops snvs_rtc_pm_ops = { 381 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq) 382 }; 383 384 static const struct of_device_id snvs_dt_ids[] = { 385 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", }, 386 { /* sentinel */ } 387 }; 388 MODULE_DEVICE_TABLE(of, snvs_dt_ids); 389 390 static struct platform_driver snvs_rtc_driver = { 391 .driver = { 392 .name = "snvs_rtc", 393 .pm = &snvs_rtc_pm_ops, 394 .of_match_table = snvs_dt_ids, 395 }, 396 .probe = snvs_rtc_probe, 397 }; 398 module_platform_driver(snvs_rtc_driver); 399 400 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 401 MODULE_DESCRIPTION("Freescale SNVS RTC Driver"); 402 MODULE_LICENSE("GPL"); 403