1 /* 2 * SuperH On-Chip RTC Support 3 * 4 * Copyright (C) 2006 - 2009 Paul Mundt 5 * Copyright (C) 2006 Jamie Lenehan 6 * Copyright (C) 2008 Angelo Castello 7 * 8 * Based on the old arch/sh/kernel/cpu/rtc.c by: 9 * 10 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> 11 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka 12 * 13 * This file is subject to the terms and conditions of the GNU General Public 14 * License. See the file "COPYING" in the main directory of this archive 15 * for more details. 16 */ 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/bcd.h> 20 #include <linux/rtc.h> 21 #include <linux/init.h> 22 #include <linux/platform_device.h> 23 #include <linux/seq_file.h> 24 #include <linux/interrupt.h> 25 #include <linux/spinlock.h> 26 #include <linux/io.h> 27 #include <linux/log2.h> 28 #include <linux/clk.h> 29 #include <linux/slab.h> 30 #include <asm/rtc.h> 31 32 #define DRV_NAME "sh-rtc" 33 34 #define RTC_REG(r) ((r) * rtc_reg_size) 35 36 #define R64CNT RTC_REG(0) 37 38 #define RSECCNT RTC_REG(1) /* RTC sec */ 39 #define RMINCNT RTC_REG(2) /* RTC min */ 40 #define RHRCNT RTC_REG(3) /* RTC hour */ 41 #define RWKCNT RTC_REG(4) /* RTC week */ 42 #define RDAYCNT RTC_REG(5) /* RTC day */ 43 #define RMONCNT RTC_REG(6) /* RTC month */ 44 #define RYRCNT RTC_REG(7) /* RTC year */ 45 #define RSECAR RTC_REG(8) /* ALARM sec */ 46 #define RMINAR RTC_REG(9) /* ALARM min */ 47 #define RHRAR RTC_REG(10) /* ALARM hour */ 48 #define RWKAR RTC_REG(11) /* ALARM week */ 49 #define RDAYAR RTC_REG(12) /* ALARM day */ 50 #define RMONAR RTC_REG(13) /* ALARM month */ 51 #define RCR1 RTC_REG(14) /* Control */ 52 #define RCR2 RTC_REG(15) /* Control */ 53 54 /* 55 * Note on RYRAR and RCR3: Up until this point most of the register 56 * definitions are consistent across all of the available parts. However, 57 * the placement of the optional RYRAR and RCR3 (the RYRAR control 58 * register used to control RYRCNT/RYRAR compare) varies considerably 59 * across various parts, occasionally being mapped in to a completely 60 * unrelated address space. For proper RYRAR support a separate resource 61 * would have to be handed off, but as this is purely optional in 62 * practice, we simply opt not to support it, thereby keeping the code 63 * quite a bit more simplified. 64 */ 65 66 /* ALARM Bits - or with BCD encoded value */ 67 #define AR_ENB 0x80 /* Enable for alarm cmp */ 68 69 /* Period Bits */ 70 #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */ 71 #define PF_COUNT 0x200 /* Half periodic counter */ 72 #define PF_OXS 0x400 /* Periodic One x Second */ 73 #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */ 74 #define PF_MASK 0xf00 75 76 /* RCR1 Bits */ 77 #define RCR1_CF 0x80 /* Carry Flag */ 78 #define RCR1_CIE 0x10 /* Carry Interrupt Enable */ 79 #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ 80 #define RCR1_AF 0x01 /* Alarm Flag */ 81 82 /* RCR2 Bits */ 83 #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ 84 #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ 85 #define RCR2_RTCEN 0x08 /* ENable RTC */ 86 #define RCR2_ADJ 0x04 /* ADJustment (30-second) */ 87 #define RCR2_RESET 0x02 /* Reset bit */ 88 #define RCR2_START 0x01 /* Start bit */ 89 90 struct sh_rtc { 91 void __iomem *regbase; 92 unsigned long regsize; 93 struct resource *res; 94 int alarm_irq; 95 int periodic_irq; 96 int carry_irq; 97 struct clk *clk; 98 struct rtc_device *rtc_dev; 99 spinlock_t lock; 100 unsigned long capabilities; /* See asm/rtc.h for cap bits */ 101 unsigned short periodic_freq; 102 }; 103 104 static int __sh_rtc_interrupt(struct sh_rtc *rtc) 105 { 106 unsigned int tmp, pending; 107 108 tmp = readb(rtc->regbase + RCR1); 109 pending = tmp & RCR1_CF; 110 tmp &= ~RCR1_CF; 111 writeb(tmp, rtc->regbase + RCR1); 112 113 /* Users have requested One x Second IRQ */ 114 if (pending && rtc->periodic_freq & PF_OXS) 115 rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF); 116 117 return pending; 118 } 119 120 static int __sh_rtc_alarm(struct sh_rtc *rtc) 121 { 122 unsigned int tmp, pending; 123 124 tmp = readb(rtc->regbase + RCR1); 125 pending = tmp & RCR1_AF; 126 tmp &= ~(RCR1_AF | RCR1_AIE); 127 writeb(tmp, rtc->regbase + RCR1); 128 129 if (pending) 130 rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF); 131 132 return pending; 133 } 134 135 static int __sh_rtc_periodic(struct sh_rtc *rtc) 136 { 137 struct rtc_device *rtc_dev = rtc->rtc_dev; 138 struct rtc_task *irq_task; 139 unsigned int tmp, pending; 140 141 tmp = readb(rtc->regbase + RCR2); 142 pending = tmp & RCR2_PEF; 143 tmp &= ~RCR2_PEF; 144 writeb(tmp, rtc->regbase + RCR2); 145 146 if (!pending) 147 return 0; 148 149 /* Half period enabled than one skipped and the next notified */ 150 if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT)) 151 rtc->periodic_freq &= ~PF_COUNT; 152 else { 153 if (rtc->periodic_freq & PF_HP) 154 rtc->periodic_freq |= PF_COUNT; 155 if (rtc->periodic_freq & PF_KOU) { 156 spin_lock(&rtc_dev->irq_task_lock); 157 irq_task = rtc_dev->irq_task; 158 if (irq_task) 159 irq_task->func(irq_task->private_data); 160 spin_unlock(&rtc_dev->irq_task_lock); 161 } else 162 rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF); 163 } 164 165 return pending; 166 } 167 168 static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id) 169 { 170 struct sh_rtc *rtc = dev_id; 171 int ret; 172 173 spin_lock(&rtc->lock); 174 ret = __sh_rtc_interrupt(rtc); 175 spin_unlock(&rtc->lock); 176 177 return IRQ_RETVAL(ret); 178 } 179 180 static irqreturn_t sh_rtc_alarm(int irq, void *dev_id) 181 { 182 struct sh_rtc *rtc = dev_id; 183 int ret; 184 185 spin_lock(&rtc->lock); 186 ret = __sh_rtc_alarm(rtc); 187 spin_unlock(&rtc->lock); 188 189 return IRQ_RETVAL(ret); 190 } 191 192 static irqreturn_t sh_rtc_periodic(int irq, void *dev_id) 193 { 194 struct sh_rtc *rtc = dev_id; 195 int ret; 196 197 spin_lock(&rtc->lock); 198 ret = __sh_rtc_periodic(rtc); 199 spin_unlock(&rtc->lock); 200 201 return IRQ_RETVAL(ret); 202 } 203 204 static irqreturn_t sh_rtc_shared(int irq, void *dev_id) 205 { 206 struct sh_rtc *rtc = dev_id; 207 int ret; 208 209 spin_lock(&rtc->lock); 210 ret = __sh_rtc_interrupt(rtc); 211 ret |= __sh_rtc_alarm(rtc); 212 ret |= __sh_rtc_periodic(rtc); 213 spin_unlock(&rtc->lock); 214 215 return IRQ_RETVAL(ret); 216 } 217 218 static int sh_rtc_irq_set_state(struct device *dev, int enable) 219 { 220 struct sh_rtc *rtc = dev_get_drvdata(dev); 221 unsigned int tmp; 222 223 spin_lock_irq(&rtc->lock); 224 225 tmp = readb(rtc->regbase + RCR2); 226 227 if (enable) { 228 rtc->periodic_freq |= PF_KOU; 229 tmp &= ~RCR2_PEF; /* Clear PES bit */ 230 tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */ 231 } else { 232 rtc->periodic_freq &= ~PF_KOU; 233 tmp &= ~(RCR2_PESMASK | RCR2_PEF); 234 } 235 236 writeb(tmp, rtc->regbase + RCR2); 237 238 spin_unlock_irq(&rtc->lock); 239 240 return 0; 241 } 242 243 static int sh_rtc_irq_set_freq(struct device *dev, int freq) 244 { 245 struct sh_rtc *rtc = dev_get_drvdata(dev); 246 int tmp, ret = 0; 247 248 spin_lock_irq(&rtc->lock); 249 tmp = rtc->periodic_freq & PF_MASK; 250 251 switch (freq) { 252 case 0: 253 rtc->periodic_freq = 0x00; 254 break; 255 case 1: 256 rtc->periodic_freq = 0x60; 257 break; 258 case 2: 259 rtc->periodic_freq = 0x50; 260 break; 261 case 4: 262 rtc->periodic_freq = 0x40; 263 break; 264 case 8: 265 rtc->periodic_freq = 0x30 | PF_HP; 266 break; 267 case 16: 268 rtc->periodic_freq = 0x30; 269 break; 270 case 32: 271 rtc->periodic_freq = 0x20 | PF_HP; 272 break; 273 case 64: 274 rtc->periodic_freq = 0x20; 275 break; 276 case 128: 277 rtc->periodic_freq = 0x10 | PF_HP; 278 break; 279 case 256: 280 rtc->periodic_freq = 0x10; 281 break; 282 default: 283 ret = -ENOTSUPP; 284 } 285 286 if (ret == 0) 287 rtc->periodic_freq |= tmp; 288 289 spin_unlock_irq(&rtc->lock); 290 return ret; 291 } 292 293 static inline void sh_rtc_setaie(struct device *dev, unsigned int enable) 294 { 295 struct sh_rtc *rtc = dev_get_drvdata(dev); 296 unsigned int tmp; 297 298 spin_lock_irq(&rtc->lock); 299 300 tmp = readb(rtc->regbase + RCR1); 301 302 if (enable) 303 tmp |= RCR1_AIE; 304 else 305 tmp &= ~RCR1_AIE; 306 307 writeb(tmp, rtc->regbase + RCR1); 308 309 spin_unlock_irq(&rtc->lock); 310 } 311 312 static int sh_rtc_proc(struct device *dev, struct seq_file *seq) 313 { 314 struct sh_rtc *rtc = dev_get_drvdata(dev); 315 unsigned int tmp; 316 317 tmp = readb(rtc->regbase + RCR1); 318 seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no"); 319 320 tmp = readb(rtc->regbase + RCR2); 321 seq_printf(seq, "periodic_IRQ\t: %s\n", 322 (tmp & RCR2_PESMASK) ? "yes" : "no"); 323 324 return 0; 325 } 326 327 static inline void sh_rtc_setcie(struct device *dev, unsigned int enable) 328 { 329 struct sh_rtc *rtc = dev_get_drvdata(dev); 330 unsigned int tmp; 331 332 spin_lock_irq(&rtc->lock); 333 334 tmp = readb(rtc->regbase + RCR1); 335 336 if (!enable) 337 tmp &= ~RCR1_CIE; 338 else 339 tmp |= RCR1_CIE; 340 341 writeb(tmp, rtc->regbase + RCR1); 342 343 spin_unlock_irq(&rtc->lock); 344 } 345 346 static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 347 { 348 sh_rtc_setaie(dev, enabled); 349 return 0; 350 } 351 352 static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm) 353 { 354 struct platform_device *pdev = to_platform_device(dev); 355 struct sh_rtc *rtc = platform_get_drvdata(pdev); 356 unsigned int sec128, sec2, yr, yr100, cf_bit; 357 358 do { 359 unsigned int tmp; 360 361 spin_lock_irq(&rtc->lock); 362 363 tmp = readb(rtc->regbase + RCR1); 364 tmp &= ~RCR1_CF; /* Clear CF-bit */ 365 tmp |= RCR1_CIE; 366 writeb(tmp, rtc->regbase + RCR1); 367 368 sec128 = readb(rtc->regbase + R64CNT); 369 370 tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT)); 371 tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT)); 372 tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT)); 373 tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT)); 374 tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT)); 375 tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1; 376 377 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { 378 yr = readw(rtc->regbase + RYRCNT); 379 yr100 = bcd2bin(yr >> 8); 380 yr &= 0xff; 381 } else { 382 yr = readb(rtc->regbase + RYRCNT); 383 yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20); 384 } 385 386 tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900; 387 388 sec2 = readb(rtc->regbase + R64CNT); 389 cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF; 390 391 spin_unlock_irq(&rtc->lock); 392 } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0); 393 394 #if RTC_BIT_INVERTED != 0 395 if ((sec128 & RTC_BIT_INVERTED)) 396 tm->tm_sec--; 397 #endif 398 399 /* only keep the carry interrupt enabled if UIE is on */ 400 if (!(rtc->periodic_freq & PF_OXS)) 401 sh_rtc_setcie(dev, 0); 402 403 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 404 "mday=%d, mon=%d, year=%d, wday=%d\n", 405 __func__, 406 tm->tm_sec, tm->tm_min, tm->tm_hour, 407 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); 408 409 return rtc_valid_tm(tm); 410 } 411 412 static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm) 413 { 414 struct platform_device *pdev = to_platform_device(dev); 415 struct sh_rtc *rtc = platform_get_drvdata(pdev); 416 unsigned int tmp; 417 int year; 418 419 spin_lock_irq(&rtc->lock); 420 421 /* Reset pre-scaler & stop RTC */ 422 tmp = readb(rtc->regbase + RCR2); 423 tmp |= RCR2_RESET; 424 tmp &= ~RCR2_START; 425 writeb(tmp, rtc->regbase + RCR2); 426 427 writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT); 428 writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT); 429 writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT); 430 writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT); 431 writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT); 432 writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT); 433 434 if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) { 435 year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) | 436 bin2bcd(tm->tm_year % 100); 437 writew(year, rtc->regbase + RYRCNT); 438 } else { 439 year = tm->tm_year % 100; 440 writeb(bin2bcd(year), rtc->regbase + RYRCNT); 441 } 442 443 /* Start RTC */ 444 tmp = readb(rtc->regbase + RCR2); 445 tmp &= ~RCR2_RESET; 446 tmp |= RCR2_RTCEN | RCR2_START; 447 writeb(tmp, rtc->regbase + RCR2); 448 449 spin_unlock_irq(&rtc->lock); 450 451 return 0; 452 } 453 454 static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) 455 { 456 unsigned int byte; 457 int value = 0xff; /* return 0xff for ignored values */ 458 459 byte = readb(rtc->regbase + reg_off); 460 if (byte & AR_ENB) { 461 byte &= ~AR_ENB; /* strip the enable bit */ 462 value = bcd2bin(byte); 463 } 464 465 return value; 466 } 467 468 static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) 469 { 470 struct platform_device *pdev = to_platform_device(dev); 471 struct sh_rtc *rtc = platform_get_drvdata(pdev); 472 struct rtc_time *tm = &wkalrm->time; 473 474 spin_lock_irq(&rtc->lock); 475 476 tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR); 477 tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR); 478 tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR); 479 tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR); 480 tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR); 481 tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR); 482 if (tm->tm_mon > 0) 483 tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */ 484 485 wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0; 486 487 spin_unlock_irq(&rtc->lock); 488 489 return 0; 490 } 491 492 static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc, 493 int value, int reg_off) 494 { 495 /* < 0 for a value that is ignored */ 496 if (value < 0) 497 writeb(0, rtc->regbase + reg_off); 498 else 499 writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); 500 } 501 502 static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) 503 { 504 struct platform_device *pdev = to_platform_device(dev); 505 struct sh_rtc *rtc = platform_get_drvdata(pdev); 506 unsigned int rcr1; 507 struct rtc_time *tm = &wkalrm->time; 508 int mon; 509 510 spin_lock_irq(&rtc->lock); 511 512 /* disable alarm interrupt and clear the alarm flag */ 513 rcr1 = readb(rtc->regbase + RCR1); 514 rcr1 &= ~(RCR1_AF | RCR1_AIE); 515 writeb(rcr1, rtc->regbase + RCR1); 516 517 /* set alarm time */ 518 sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR); 519 sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR); 520 sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR); 521 sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR); 522 sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR); 523 mon = tm->tm_mon; 524 if (mon >= 0) 525 mon += 1; 526 sh_rtc_write_alarm_value(rtc, mon, RMONAR); 527 528 if (wkalrm->enabled) { 529 rcr1 |= RCR1_AIE; 530 writeb(rcr1, rtc->regbase + RCR1); 531 } 532 533 spin_unlock_irq(&rtc->lock); 534 535 return 0; 536 } 537 538 static struct rtc_class_ops sh_rtc_ops = { 539 .read_time = sh_rtc_read_time, 540 .set_time = sh_rtc_set_time, 541 .read_alarm = sh_rtc_read_alarm, 542 .set_alarm = sh_rtc_set_alarm, 543 .proc = sh_rtc_proc, 544 .alarm_irq_enable = sh_rtc_alarm_irq_enable, 545 }; 546 547 static int __init sh_rtc_probe(struct platform_device *pdev) 548 { 549 struct sh_rtc *rtc; 550 struct resource *res; 551 struct rtc_time r; 552 char clk_name[6]; 553 int clk_id, ret; 554 555 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 556 if (unlikely(!rtc)) 557 return -ENOMEM; 558 559 spin_lock_init(&rtc->lock); 560 561 /* get periodic/carry/alarm irqs */ 562 ret = platform_get_irq(pdev, 0); 563 if (unlikely(ret <= 0)) { 564 dev_err(&pdev->dev, "No IRQ resource\n"); 565 return -ENOENT; 566 } 567 568 rtc->periodic_irq = ret; 569 rtc->carry_irq = platform_get_irq(pdev, 1); 570 rtc->alarm_irq = platform_get_irq(pdev, 2); 571 572 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 573 if (unlikely(res == NULL)) { 574 dev_err(&pdev->dev, "No IO resource\n"); 575 return -ENOENT; 576 } 577 578 rtc->regsize = resource_size(res); 579 580 rtc->res = devm_request_mem_region(&pdev->dev, res->start, 581 rtc->regsize, pdev->name); 582 if (unlikely(!rtc->res)) 583 return -EBUSY; 584 585 rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start, 586 rtc->regsize); 587 if (unlikely(!rtc->regbase)) 588 return -EINVAL; 589 590 clk_id = pdev->id; 591 /* With a single device, the clock id is still "rtc0" */ 592 if (clk_id < 0) 593 clk_id = 0; 594 595 snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); 596 597 rtc->clk = devm_clk_get(&pdev->dev, clk_name); 598 if (IS_ERR(rtc->clk)) { 599 /* 600 * No error handling for rtc->clk intentionally, not all 601 * platforms will have a unique clock for the RTC, and 602 * the clk API can handle the struct clk pointer being 603 * NULL. 604 */ 605 rtc->clk = NULL; 606 } 607 608 clk_enable(rtc->clk); 609 610 rtc->capabilities = RTC_DEF_CAPABILITIES; 611 if (dev_get_platdata(&pdev->dev)) { 612 struct sh_rtc_platform_info *pinfo = 613 dev_get_platdata(&pdev->dev); 614 615 /* 616 * Some CPUs have special capabilities in addition to the 617 * default set. Add those in here. 618 */ 619 rtc->capabilities |= pinfo->capabilities; 620 } 621 622 if (rtc->carry_irq <= 0) { 623 /* register shared periodic/carry/alarm irq */ 624 ret = devm_request_irq(&pdev->dev, rtc->periodic_irq, 625 sh_rtc_shared, 0, "sh-rtc", rtc); 626 if (unlikely(ret)) { 627 dev_err(&pdev->dev, 628 "request IRQ failed with %d, IRQ %d\n", ret, 629 rtc->periodic_irq); 630 goto err_unmap; 631 } 632 } else { 633 /* register periodic/carry/alarm irqs */ 634 ret = devm_request_irq(&pdev->dev, rtc->periodic_irq, 635 sh_rtc_periodic, 0, "sh-rtc period", rtc); 636 if (unlikely(ret)) { 637 dev_err(&pdev->dev, 638 "request period IRQ failed with %d, IRQ %d\n", 639 ret, rtc->periodic_irq); 640 goto err_unmap; 641 } 642 643 ret = devm_request_irq(&pdev->dev, rtc->carry_irq, 644 sh_rtc_interrupt, 0, "sh-rtc carry", rtc); 645 if (unlikely(ret)) { 646 dev_err(&pdev->dev, 647 "request carry IRQ failed with %d, IRQ %d\n", 648 ret, rtc->carry_irq); 649 goto err_unmap; 650 } 651 652 ret = devm_request_irq(&pdev->dev, rtc->alarm_irq, 653 sh_rtc_alarm, 0, "sh-rtc alarm", rtc); 654 if (unlikely(ret)) { 655 dev_err(&pdev->dev, 656 "request alarm IRQ failed with %d, IRQ %d\n", 657 ret, rtc->alarm_irq); 658 goto err_unmap; 659 } 660 } 661 662 platform_set_drvdata(pdev, rtc); 663 664 /* everything disabled by default */ 665 sh_rtc_irq_set_freq(&pdev->dev, 0); 666 sh_rtc_irq_set_state(&pdev->dev, 0); 667 sh_rtc_setaie(&pdev->dev, 0); 668 sh_rtc_setcie(&pdev->dev, 0); 669 670 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "sh", 671 &sh_rtc_ops, THIS_MODULE); 672 if (IS_ERR(rtc->rtc_dev)) { 673 ret = PTR_ERR(rtc->rtc_dev); 674 goto err_unmap; 675 } 676 677 rtc->rtc_dev->max_user_freq = 256; 678 679 /* reset rtc to epoch 0 if time is invalid */ 680 if (rtc_read_time(rtc->rtc_dev, &r) < 0) { 681 rtc_time_to_tm(0, &r); 682 rtc_set_time(rtc->rtc_dev, &r); 683 } 684 685 device_init_wakeup(&pdev->dev, 1); 686 return 0; 687 688 err_unmap: 689 clk_disable(rtc->clk); 690 691 return ret; 692 } 693 694 static int __exit sh_rtc_remove(struct platform_device *pdev) 695 { 696 struct sh_rtc *rtc = platform_get_drvdata(pdev); 697 698 sh_rtc_irq_set_state(&pdev->dev, 0); 699 700 sh_rtc_setaie(&pdev->dev, 0); 701 sh_rtc_setcie(&pdev->dev, 0); 702 703 clk_disable(rtc->clk); 704 705 return 0; 706 } 707 708 static void sh_rtc_set_irq_wake(struct device *dev, int enabled) 709 { 710 struct platform_device *pdev = to_platform_device(dev); 711 struct sh_rtc *rtc = platform_get_drvdata(pdev); 712 713 irq_set_irq_wake(rtc->periodic_irq, enabled); 714 715 if (rtc->carry_irq > 0) { 716 irq_set_irq_wake(rtc->carry_irq, enabled); 717 irq_set_irq_wake(rtc->alarm_irq, enabled); 718 } 719 } 720 721 #ifdef CONFIG_PM_SLEEP 722 static int sh_rtc_suspend(struct device *dev) 723 { 724 if (device_may_wakeup(dev)) 725 sh_rtc_set_irq_wake(dev, 1); 726 727 return 0; 728 } 729 730 static int sh_rtc_resume(struct device *dev) 731 { 732 if (device_may_wakeup(dev)) 733 sh_rtc_set_irq_wake(dev, 0); 734 735 return 0; 736 } 737 #endif 738 739 static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume); 740 741 static struct platform_driver sh_rtc_platform_driver = { 742 .driver = { 743 .name = DRV_NAME, 744 .pm = &sh_rtc_pm_ops, 745 }, 746 .remove = __exit_p(sh_rtc_remove), 747 }; 748 749 module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe); 750 751 MODULE_DESCRIPTION("SuperH on-chip RTC driver"); 752 MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, " 753 "Jamie Lenehan <lenehan@twibble.org>, " 754 "Angelo Castello <angelo.castello@st.com>"); 755 MODULE_LICENSE("GPL"); 756 MODULE_ALIAS("platform:" DRV_NAME); 757