1 /* 2 * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd 3 * http://www.samsung.com 4 * 5 * Copyright (C) 2013 Google, Inc 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20 #include <linux/module.h> 21 #include <linux/i2c.h> 22 #include <linux/bcd.h> 23 #include <linux/regmap.h> 24 #include <linux/rtc.h> 25 #include <linux/platform_device.h> 26 #include <linux/mfd/samsung/core.h> 27 #include <linux/mfd/samsung/irq.h> 28 #include <linux/mfd/samsung/rtc.h> 29 #include <linux/mfd/samsung/s2mps14.h> 30 31 /* 32 * Maximum number of retries for checking changes in UDR field 33 * of S5M_RTC_UDR_CON register (to limit possible endless loop). 34 * 35 * After writing to RTC registers (setting time or alarm) read the UDR field 36 * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have 37 * been transferred. 38 */ 39 #define UDR_READ_RETRY_CNT 5 40 41 enum { 42 RTC_SEC = 0, 43 RTC_MIN, 44 RTC_HOUR, 45 RTC_WEEKDAY, 46 RTC_DATE, 47 RTC_MONTH, 48 RTC_YEAR1, 49 RTC_YEAR2, 50 /* Make sure this is always the last enum name. */ 51 RTC_MAX_NUM_TIME_REGS 52 }; 53 54 /* 55 * Registers used by the driver which are different between chipsets. 56 * 57 * Operations like read time and write alarm/time require updating 58 * specific fields in UDR register. These fields usually are auto-cleared 59 * (with some exceptions). 60 * 61 * Table of operations per device: 62 * 63 * Device | Write time | Read time | Write alarm 64 * ================================================= 65 * S5M8767 | UDR + TIME | | UDR 66 * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR 67 * S2MPS13 | WUDR | RUDR | WUDR + AUDR 68 * S2MPS15 | WUDR | RUDR | AUDR 69 */ 70 struct s5m_rtc_reg_config { 71 /* Number of registers used for setting time/alarm0/alarm1 */ 72 unsigned int regs_count; 73 /* First register for time, seconds */ 74 unsigned int time; 75 /* RTC control register */ 76 unsigned int ctrl; 77 /* First register for alarm 0, seconds */ 78 unsigned int alarm0; 79 /* First register for alarm 1, seconds */ 80 unsigned int alarm1; 81 /* 82 * Register for update flag (UDR). Typically setting UDR field to 1 83 * will enable update of time or alarm register. Then it will be 84 * auto-cleared after successful update. 85 */ 86 unsigned int udr_update; 87 /* Auto-cleared mask in UDR field for writing time and alarm */ 88 unsigned int autoclear_udr_mask; 89 /* 90 * Masks in UDR field for time and alarm operations. 91 * The read time mask can be 0. Rest should not. 92 */ 93 unsigned int read_time_udr_mask; 94 unsigned int write_time_udr_mask; 95 unsigned int write_alarm_udr_mask; 96 }; 97 98 /* Register map for S5M8763 and S5M8767 */ 99 static const struct s5m_rtc_reg_config s5m_rtc_regs = { 100 .regs_count = 8, 101 .time = S5M_RTC_SEC, 102 .ctrl = S5M_ALARM1_CONF, 103 .alarm0 = S5M_ALARM0_SEC, 104 .alarm1 = S5M_ALARM1_SEC, 105 .udr_update = S5M_RTC_UDR_CON, 106 .autoclear_udr_mask = S5M_RTC_UDR_MASK, 107 .read_time_udr_mask = 0, /* Not needed */ 108 .write_time_udr_mask = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK, 109 .write_alarm_udr_mask = S5M_RTC_UDR_MASK, 110 }; 111 112 /* Register map for S2MPS13 */ 113 static const struct s5m_rtc_reg_config s2mps13_rtc_regs = { 114 .regs_count = 7, 115 .time = S2MPS_RTC_SEC, 116 .ctrl = S2MPS_RTC_CTRL, 117 .alarm0 = S2MPS_ALARM0_SEC, 118 .alarm1 = S2MPS_ALARM1_SEC, 119 .udr_update = S2MPS_RTC_UDR_CON, 120 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, 121 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, 122 .write_time_udr_mask = S2MPS_RTC_WUDR_MASK, 123 .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK, 124 }; 125 126 /* Register map for S2MPS11/14 */ 127 static const struct s5m_rtc_reg_config s2mps14_rtc_regs = { 128 .regs_count = 7, 129 .time = S2MPS_RTC_SEC, 130 .ctrl = S2MPS_RTC_CTRL, 131 .alarm0 = S2MPS_ALARM0_SEC, 132 .alarm1 = S2MPS_ALARM1_SEC, 133 .udr_update = S2MPS_RTC_UDR_CON, 134 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, 135 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, 136 .write_time_udr_mask = S2MPS_RTC_WUDR_MASK, 137 .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK, 138 }; 139 140 /* 141 * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits 142 * are swapped. 143 */ 144 static const struct s5m_rtc_reg_config s2mps15_rtc_regs = { 145 .regs_count = 7, 146 .time = S2MPS_RTC_SEC, 147 .ctrl = S2MPS_RTC_CTRL, 148 .alarm0 = S2MPS_ALARM0_SEC, 149 .alarm1 = S2MPS_ALARM1_SEC, 150 .udr_update = S2MPS_RTC_UDR_CON, 151 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, 152 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, 153 .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK, 154 .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK, 155 }; 156 157 struct s5m_rtc_info { 158 struct device *dev; 159 struct i2c_client *i2c; 160 struct sec_pmic_dev *s5m87xx; 161 struct regmap *regmap; 162 struct rtc_device *rtc_dev; 163 int irq; 164 enum sec_device_type device_type; 165 int rtc_24hr_mode; 166 const struct s5m_rtc_reg_config *regs; 167 }; 168 169 static const struct regmap_config s5m_rtc_regmap_config = { 170 .reg_bits = 8, 171 .val_bits = 8, 172 173 .max_register = S5M_RTC_REG_MAX, 174 }; 175 176 static const struct regmap_config s2mps14_rtc_regmap_config = { 177 .reg_bits = 8, 178 .val_bits = 8, 179 180 .max_register = S2MPS_RTC_REG_MAX, 181 }; 182 183 static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm, 184 int rtc_24hr_mode) 185 { 186 tm->tm_sec = data[RTC_SEC] & 0x7f; 187 tm->tm_min = data[RTC_MIN] & 0x7f; 188 if (rtc_24hr_mode) { 189 tm->tm_hour = data[RTC_HOUR] & 0x1f; 190 } else { 191 tm->tm_hour = data[RTC_HOUR] & 0x0f; 192 if (data[RTC_HOUR] & HOUR_PM_MASK) 193 tm->tm_hour += 12; 194 } 195 196 tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f); 197 tm->tm_mday = data[RTC_DATE] & 0x1f; 198 tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1; 199 tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100; 200 tm->tm_yday = 0; 201 tm->tm_isdst = 0; 202 } 203 204 static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data) 205 { 206 data[RTC_SEC] = tm->tm_sec; 207 data[RTC_MIN] = tm->tm_min; 208 209 if (tm->tm_hour >= 12) 210 data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK; 211 else 212 data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK; 213 214 data[RTC_WEEKDAY] = 1 << tm->tm_wday; 215 data[RTC_DATE] = tm->tm_mday; 216 data[RTC_MONTH] = tm->tm_mon + 1; 217 data[RTC_YEAR1] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0; 218 219 if (tm->tm_year < 100) { 220 pr_err("RTC cannot handle the year %d\n", 221 1900 + tm->tm_year); 222 return -EINVAL; 223 } else { 224 return 0; 225 } 226 } 227 228 /* 229 * Read RTC_UDR_CON register and wait till UDR field is cleared. 230 * This indicates that time/alarm update ended. 231 */ 232 static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info) 233 { 234 int ret, retry = UDR_READ_RETRY_CNT; 235 unsigned int data; 236 237 do { 238 ret = regmap_read(info->regmap, info->regs->udr_update, &data); 239 } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret); 240 241 if (!retry) 242 dev_err(info->dev, "waiting for UDR update, reached max number of retries\n"); 243 244 return ret; 245 } 246 247 static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info, 248 struct rtc_wkalrm *alarm) 249 { 250 int ret; 251 unsigned int val; 252 253 switch (info->device_type) { 254 case S5M8767X: 255 case S5M8763X: 256 ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val); 257 val &= S5M_ALARM0_STATUS; 258 break; 259 case S2MPS15X: 260 case S2MPS14X: 261 case S2MPS13X: 262 ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2, 263 &val); 264 val &= S2MPS_ALARM0_STATUS; 265 break; 266 default: 267 return -EINVAL; 268 } 269 if (ret < 0) 270 return ret; 271 272 if (val) 273 alarm->pending = 1; 274 else 275 alarm->pending = 0; 276 277 return 0; 278 } 279 280 static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info) 281 { 282 int ret; 283 unsigned int data; 284 285 ret = regmap_read(info->regmap, info->regs->udr_update, &data); 286 if (ret < 0) { 287 dev_err(info->dev, "failed to read update reg(%d)\n", ret); 288 return ret; 289 } 290 291 data |= info->regs->write_time_udr_mask; 292 293 ret = regmap_write(info->regmap, info->regs->udr_update, data); 294 if (ret < 0) { 295 dev_err(info->dev, "failed to write update reg(%d)\n", ret); 296 return ret; 297 } 298 299 ret = s5m8767_wait_for_udr_update(info); 300 301 return ret; 302 } 303 304 static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info) 305 { 306 int ret; 307 unsigned int data; 308 309 ret = regmap_read(info->regmap, info->regs->udr_update, &data); 310 if (ret < 0) { 311 dev_err(info->dev, "%s: fail to read update reg(%d)\n", 312 __func__, ret); 313 return ret; 314 } 315 316 data |= info->regs->write_alarm_udr_mask; 317 switch (info->device_type) { 318 case S5M8763X: 319 case S5M8767X: 320 data &= ~S5M_RTC_TIME_EN_MASK; 321 break; 322 case S2MPS15X: 323 case S2MPS14X: 324 case S2MPS13X: 325 /* No exceptions needed */ 326 break; 327 default: 328 return -EINVAL; 329 } 330 331 ret = regmap_write(info->regmap, info->regs->udr_update, data); 332 if (ret < 0) { 333 dev_err(info->dev, "%s: fail to write update reg(%d)\n", 334 __func__, ret); 335 return ret; 336 } 337 338 ret = s5m8767_wait_for_udr_update(info); 339 340 /* On S2MPS13 the AUDR is not auto-cleared */ 341 if (info->device_type == S2MPS13X) 342 regmap_update_bits(info->regmap, info->regs->udr_update, 343 S2MPS13_RTC_AUDR_MASK, 0); 344 345 return ret; 346 } 347 348 static void s5m8763_data_to_tm(u8 *data, struct rtc_time *tm) 349 { 350 tm->tm_sec = bcd2bin(data[RTC_SEC]); 351 tm->tm_min = bcd2bin(data[RTC_MIN]); 352 353 if (data[RTC_HOUR] & HOUR_12) { 354 tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x1f); 355 if (data[RTC_HOUR] & HOUR_PM) 356 tm->tm_hour += 12; 357 } else { 358 tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f); 359 } 360 361 tm->tm_wday = data[RTC_WEEKDAY] & 0x07; 362 tm->tm_mday = bcd2bin(data[RTC_DATE]); 363 tm->tm_mon = bcd2bin(data[RTC_MONTH]); 364 tm->tm_year = bcd2bin(data[RTC_YEAR1]) + bcd2bin(data[RTC_YEAR2]) * 100; 365 tm->tm_year -= 1900; 366 } 367 368 static void s5m8763_tm_to_data(struct rtc_time *tm, u8 *data) 369 { 370 data[RTC_SEC] = bin2bcd(tm->tm_sec); 371 data[RTC_MIN] = bin2bcd(tm->tm_min); 372 data[RTC_HOUR] = bin2bcd(tm->tm_hour); 373 data[RTC_WEEKDAY] = tm->tm_wday; 374 data[RTC_DATE] = bin2bcd(tm->tm_mday); 375 data[RTC_MONTH] = bin2bcd(tm->tm_mon); 376 data[RTC_YEAR1] = bin2bcd(tm->tm_year % 100); 377 data[RTC_YEAR2] = bin2bcd((tm->tm_year + 1900) / 100); 378 } 379 380 static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm) 381 { 382 struct s5m_rtc_info *info = dev_get_drvdata(dev); 383 u8 data[RTC_MAX_NUM_TIME_REGS]; 384 int ret; 385 386 if (info->regs->read_time_udr_mask) { 387 ret = regmap_update_bits(info->regmap, 388 info->regs->udr_update, 389 info->regs->read_time_udr_mask, 390 info->regs->read_time_udr_mask); 391 if (ret) { 392 dev_err(dev, 393 "Failed to prepare registers for time reading: %d\n", 394 ret); 395 return ret; 396 } 397 } 398 ret = regmap_bulk_read(info->regmap, info->regs->time, data, 399 info->regs->regs_count); 400 if (ret < 0) 401 return ret; 402 403 switch (info->device_type) { 404 case S5M8763X: 405 s5m8763_data_to_tm(data, tm); 406 break; 407 408 case S5M8767X: 409 case S2MPS15X: 410 case S2MPS14X: 411 case S2MPS13X: 412 s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode); 413 break; 414 415 default: 416 return -EINVAL; 417 } 418 419 dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, 420 1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday, 421 tm->tm_hour, tm->tm_min, tm->tm_sec, tm->tm_wday); 422 423 return 0; 424 } 425 426 static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) 427 { 428 struct s5m_rtc_info *info = dev_get_drvdata(dev); 429 u8 data[RTC_MAX_NUM_TIME_REGS]; 430 int ret = 0; 431 432 switch (info->device_type) { 433 case S5M8763X: 434 s5m8763_tm_to_data(tm, data); 435 break; 436 case S5M8767X: 437 case S2MPS15X: 438 case S2MPS14X: 439 case S2MPS13X: 440 ret = s5m8767_tm_to_data(tm, data); 441 break; 442 default: 443 return -EINVAL; 444 } 445 446 if (ret < 0) 447 return ret; 448 449 dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, 450 1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday, 451 tm->tm_hour, tm->tm_min, tm->tm_sec, tm->tm_wday); 452 453 ret = regmap_raw_write(info->regmap, info->regs->time, data, 454 info->regs->regs_count); 455 if (ret < 0) 456 return ret; 457 458 ret = s5m8767_rtc_set_time_reg(info); 459 460 return ret; 461 } 462 463 static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 464 { 465 struct s5m_rtc_info *info = dev_get_drvdata(dev); 466 u8 data[RTC_MAX_NUM_TIME_REGS]; 467 unsigned int val; 468 int ret, i; 469 470 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, 471 info->regs->regs_count); 472 if (ret < 0) 473 return ret; 474 475 switch (info->device_type) { 476 case S5M8763X: 477 s5m8763_data_to_tm(data, &alrm->time); 478 ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val); 479 if (ret < 0) 480 return ret; 481 482 alrm->enabled = !!val; 483 break; 484 485 case S5M8767X: 486 case S2MPS15X: 487 case S2MPS14X: 488 case S2MPS13X: 489 s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode); 490 alrm->enabled = 0; 491 for (i = 0; i < info->regs->regs_count; i++) { 492 if (data[i] & ALARM_ENABLE_MASK) { 493 alrm->enabled = 1; 494 break; 495 } 496 } 497 break; 498 499 default: 500 return -EINVAL; 501 } 502 503 dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, 504 1900 + alrm->time.tm_year, 1 + alrm->time.tm_mon, 505 alrm->time.tm_mday, alrm->time.tm_hour, 506 alrm->time.tm_min, alrm->time.tm_sec, 507 alrm->time.tm_wday); 508 509 ret = s5m_check_peding_alarm_interrupt(info, alrm); 510 511 return 0; 512 } 513 514 static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info) 515 { 516 u8 data[RTC_MAX_NUM_TIME_REGS]; 517 int ret, i; 518 struct rtc_time tm; 519 520 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, 521 info->regs->regs_count); 522 if (ret < 0) 523 return ret; 524 525 s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode); 526 dev_dbg(info->dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, 527 1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday, 528 tm.tm_hour, tm.tm_min, tm.tm_sec, tm.tm_wday); 529 530 switch (info->device_type) { 531 case S5M8763X: 532 ret = regmap_write(info->regmap, S5M_ALARM0_CONF, 0); 533 break; 534 535 case S5M8767X: 536 case S2MPS15X: 537 case S2MPS14X: 538 case S2MPS13X: 539 for (i = 0; i < info->regs->regs_count; i++) 540 data[i] &= ~ALARM_ENABLE_MASK; 541 542 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, 543 info->regs->regs_count); 544 if (ret < 0) 545 return ret; 546 547 ret = s5m8767_rtc_set_alarm_reg(info); 548 549 break; 550 551 default: 552 return -EINVAL; 553 } 554 555 return ret; 556 } 557 558 static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) 559 { 560 int ret; 561 u8 data[RTC_MAX_NUM_TIME_REGS]; 562 u8 alarm0_conf; 563 struct rtc_time tm; 564 565 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, 566 info->regs->regs_count); 567 if (ret < 0) 568 return ret; 569 570 s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode); 571 dev_dbg(info->dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, 572 1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday, 573 tm.tm_hour, tm.tm_min, tm.tm_sec, tm.tm_wday); 574 575 switch (info->device_type) { 576 case S5M8763X: 577 alarm0_conf = 0x77; 578 ret = regmap_write(info->regmap, S5M_ALARM0_CONF, alarm0_conf); 579 break; 580 581 case S5M8767X: 582 case S2MPS15X: 583 case S2MPS14X: 584 case S2MPS13X: 585 data[RTC_SEC] |= ALARM_ENABLE_MASK; 586 data[RTC_MIN] |= ALARM_ENABLE_MASK; 587 data[RTC_HOUR] |= ALARM_ENABLE_MASK; 588 data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK; 589 if (data[RTC_DATE] & 0x1f) 590 data[RTC_DATE] |= ALARM_ENABLE_MASK; 591 if (data[RTC_MONTH] & 0xf) 592 data[RTC_MONTH] |= ALARM_ENABLE_MASK; 593 if (data[RTC_YEAR1] & 0x7f) 594 data[RTC_YEAR1] |= ALARM_ENABLE_MASK; 595 596 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, 597 info->regs->regs_count); 598 if (ret < 0) 599 return ret; 600 ret = s5m8767_rtc_set_alarm_reg(info); 601 602 break; 603 604 default: 605 return -EINVAL; 606 } 607 608 return ret; 609 } 610 611 static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 612 { 613 struct s5m_rtc_info *info = dev_get_drvdata(dev); 614 u8 data[RTC_MAX_NUM_TIME_REGS]; 615 int ret; 616 617 switch (info->device_type) { 618 case S5M8763X: 619 s5m8763_tm_to_data(&alrm->time, data); 620 break; 621 622 case S5M8767X: 623 case S2MPS15X: 624 case S2MPS14X: 625 case S2MPS13X: 626 s5m8767_tm_to_data(&alrm->time, data); 627 break; 628 629 default: 630 return -EINVAL; 631 } 632 633 dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, 634 1900 + alrm->time.tm_year, 1 + alrm->time.tm_mon, 635 alrm->time.tm_mday, alrm->time.tm_hour, alrm->time.tm_min, 636 alrm->time.tm_sec, alrm->time.tm_wday); 637 638 ret = s5m_rtc_stop_alarm(info); 639 if (ret < 0) 640 return ret; 641 642 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, 643 info->regs->regs_count); 644 if (ret < 0) 645 return ret; 646 647 ret = s5m8767_rtc_set_alarm_reg(info); 648 if (ret < 0) 649 return ret; 650 651 if (alrm->enabled) 652 ret = s5m_rtc_start_alarm(info); 653 654 return ret; 655 } 656 657 static int s5m_rtc_alarm_irq_enable(struct device *dev, 658 unsigned int enabled) 659 { 660 struct s5m_rtc_info *info = dev_get_drvdata(dev); 661 662 if (enabled) 663 return s5m_rtc_start_alarm(info); 664 else 665 return s5m_rtc_stop_alarm(info); 666 } 667 668 static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data) 669 { 670 struct s5m_rtc_info *info = data; 671 672 rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); 673 674 return IRQ_HANDLED; 675 } 676 677 static const struct rtc_class_ops s5m_rtc_ops = { 678 .read_time = s5m_rtc_read_time, 679 .set_time = s5m_rtc_set_time, 680 .read_alarm = s5m_rtc_read_alarm, 681 .set_alarm = s5m_rtc_set_alarm, 682 .alarm_irq_enable = s5m_rtc_alarm_irq_enable, 683 }; 684 685 static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info) 686 { 687 u8 data[2]; 688 int ret; 689 690 switch (info->device_type) { 691 case S5M8763X: 692 case S5M8767X: 693 /* UDR update time. Default of 7.32 ms is too long. */ 694 ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON, 695 S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US); 696 if (ret < 0) 697 dev_err(info->dev, "%s: fail to change UDR time: %d\n", 698 __func__, ret); 699 700 /* Set RTC control register : Binary mode, 24hour mode */ 701 data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); 702 data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); 703 704 ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2); 705 break; 706 707 case S2MPS15X: 708 case S2MPS14X: 709 case S2MPS13X: 710 data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); 711 ret = regmap_write(info->regmap, info->regs->ctrl, data[0]); 712 if (ret < 0) 713 break; 714 715 /* 716 * Should set WUDR & (RUDR or AUDR) bits to high after writing 717 * RTC_CTRL register like writing Alarm registers. We can't find 718 * the description from datasheet but vendor code does that 719 * really. 720 */ 721 ret = s5m8767_rtc_set_alarm_reg(info); 722 break; 723 724 default: 725 return -EINVAL; 726 } 727 728 info->rtc_24hr_mode = 1; 729 if (ret < 0) { 730 dev_err(info->dev, "%s: fail to write controlm reg(%d)\n", 731 __func__, ret); 732 return ret; 733 } 734 735 return ret; 736 } 737 738 static int s5m_rtc_probe(struct platform_device *pdev) 739 { 740 struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent); 741 struct sec_platform_data *pdata = s5m87xx->pdata; 742 struct s5m_rtc_info *info; 743 const struct regmap_config *regmap_cfg; 744 int ret, alarm_irq; 745 746 if (!pdata) { 747 dev_err(pdev->dev.parent, "Platform data not supplied\n"); 748 return -ENODEV; 749 } 750 751 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 752 if (!info) 753 return -ENOMEM; 754 755 switch (platform_get_device_id(pdev)->driver_data) { 756 case S2MPS15X: 757 regmap_cfg = &s2mps14_rtc_regmap_config; 758 info->regs = &s2mps15_rtc_regs; 759 alarm_irq = S2MPS14_IRQ_RTCA0; 760 break; 761 case S2MPS14X: 762 regmap_cfg = &s2mps14_rtc_regmap_config; 763 info->regs = &s2mps14_rtc_regs; 764 alarm_irq = S2MPS14_IRQ_RTCA0; 765 break; 766 case S2MPS13X: 767 regmap_cfg = &s2mps14_rtc_regmap_config; 768 info->regs = &s2mps13_rtc_regs; 769 alarm_irq = S2MPS14_IRQ_RTCA0; 770 break; 771 case S5M8763X: 772 regmap_cfg = &s5m_rtc_regmap_config; 773 info->regs = &s5m_rtc_regs; 774 alarm_irq = S5M8763_IRQ_ALARM0; 775 break; 776 case S5M8767X: 777 regmap_cfg = &s5m_rtc_regmap_config; 778 info->regs = &s5m_rtc_regs; 779 alarm_irq = S5M8767_IRQ_RTCA1; 780 break; 781 default: 782 dev_err(&pdev->dev, 783 "Device type %lu is not supported by RTC driver\n", 784 platform_get_device_id(pdev)->driver_data); 785 return -ENODEV; 786 } 787 788 info->i2c = i2c_new_dummy(s5m87xx->i2c->adapter, RTC_I2C_ADDR); 789 if (!info->i2c) { 790 dev_err(&pdev->dev, "Failed to allocate I2C for RTC\n"); 791 return -ENODEV; 792 } 793 794 info->regmap = devm_regmap_init_i2c(info->i2c, regmap_cfg); 795 if (IS_ERR(info->regmap)) { 796 ret = PTR_ERR(info->regmap); 797 dev_err(&pdev->dev, "Failed to allocate RTC register map: %d\n", 798 ret); 799 goto err; 800 } 801 802 info->dev = &pdev->dev; 803 info->s5m87xx = s5m87xx; 804 info->device_type = platform_get_device_id(pdev)->driver_data; 805 806 if (s5m87xx->irq_data) { 807 info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq); 808 if (info->irq <= 0) { 809 ret = -EINVAL; 810 dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n", 811 alarm_irq); 812 goto err; 813 } 814 } 815 816 platform_set_drvdata(pdev, info); 817 818 ret = s5m8767_rtc_init_reg(info); 819 820 device_init_wakeup(&pdev->dev, 1); 821 822 info->rtc_dev = devm_rtc_device_register(&pdev->dev, "s5m-rtc", 823 &s5m_rtc_ops, THIS_MODULE); 824 825 if (IS_ERR(info->rtc_dev)) { 826 ret = PTR_ERR(info->rtc_dev); 827 goto err; 828 } 829 830 if (!info->irq) { 831 dev_info(&pdev->dev, "Alarm IRQ not available\n"); 832 return 0; 833 } 834 835 ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL, 836 s5m_rtc_alarm_irq, 0, "rtc-alarm0", 837 info); 838 if (ret < 0) { 839 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", 840 info->irq, ret); 841 goto err; 842 } 843 844 return 0; 845 846 err: 847 i2c_unregister_device(info->i2c); 848 849 return ret; 850 } 851 852 static int s5m_rtc_remove(struct platform_device *pdev) 853 { 854 struct s5m_rtc_info *info = platform_get_drvdata(pdev); 855 856 i2c_unregister_device(info->i2c); 857 858 return 0; 859 } 860 861 #ifdef CONFIG_PM_SLEEP 862 static int s5m_rtc_resume(struct device *dev) 863 { 864 struct s5m_rtc_info *info = dev_get_drvdata(dev); 865 int ret = 0; 866 867 if (info->irq && device_may_wakeup(dev)) 868 ret = disable_irq_wake(info->irq); 869 870 return ret; 871 } 872 873 static int s5m_rtc_suspend(struct device *dev) 874 { 875 struct s5m_rtc_info *info = dev_get_drvdata(dev); 876 int ret = 0; 877 878 if (info->irq && device_may_wakeup(dev)) 879 ret = enable_irq_wake(info->irq); 880 881 return ret; 882 } 883 #endif /* CONFIG_PM_SLEEP */ 884 885 static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume); 886 887 static const struct platform_device_id s5m_rtc_id[] = { 888 { "s5m-rtc", S5M8767X }, 889 { "s2mps13-rtc", S2MPS13X }, 890 { "s2mps14-rtc", S2MPS14X }, 891 { "s2mps15-rtc", S2MPS15X }, 892 { }, 893 }; 894 MODULE_DEVICE_TABLE(platform, s5m_rtc_id); 895 896 static struct platform_driver s5m_rtc_driver = { 897 .driver = { 898 .name = "s5m-rtc", 899 .pm = &s5m_rtc_pm_ops, 900 }, 901 .probe = s5m_rtc_probe, 902 .remove = s5m_rtc_remove, 903 .id_table = s5m_rtc_id, 904 }; 905 906 module_platform_driver(s5m_rtc_driver); 907 908 /* Module information */ 909 MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); 910 MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver"); 911 MODULE_LICENSE("GPL"); 912 MODULE_ALIAS("platform:s5m-rtc"); 913