1 /* 2 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 3 * http://www.simtec.co.uk/products/SWLINUX/ 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * S3C2410 Internal RTC register definition 10 */ 11 12 #ifndef __ASM_ARCH_REGS_RTC_H 13 #define __ASM_ARCH_REGS_RTC_H __FILE__ 14 15 #define S3C2410_RTCREG(x) (x) 16 #define S3C2410_INTP S3C2410_RTCREG(0x30) 17 #define S3C2410_INTP_ALM (1 << 1) 18 #define S3C2410_INTP_TIC (1 << 0) 19 20 #define S3C2410_RTCCON S3C2410_RTCREG(0x40) 21 #define S3C2410_RTCCON_RTCEN (1 << 0) 22 #define S3C2410_RTCCON_CNTSEL (1 << 2) 23 #define S3C2410_RTCCON_CLKRST (1 << 3) 24 #define S3C2443_RTCCON_TICSEL (1 << 4) 25 #define S3C64XX_RTCCON_TICEN (1 << 8) 26 27 #define S3C2410_TICNT S3C2410_RTCREG(0x44) 28 #define S3C2410_TICNT_ENABLE (1 << 7) 29 30 /* S3C2443: tick count is 15 bit wide 31 * TICNT[6:0] contains upper 7 bits 32 * TICNT1[7:0] contains lower 8 bits 33 */ 34 #define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8) 35 #define S3C2443_TICNT1 S3C2410_RTCREG(0x4C) 36 #define S3C2443_TICNT1_PART(x) (x & 0xff) 37 38 /* S3C2416: tick count is 32 bit wide 39 * TICNT[6:0] contains bits [14:8] 40 * TICNT1[7:0] contains lower 8 bits 41 * TICNT2[16:0] contains upper 17 bits 42 */ 43 #define S3C2416_TICNT2 S3C2410_RTCREG(0x48) 44 #define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15) 45 46 #define S3C2410_RTCALM S3C2410_RTCREG(0x50) 47 #define S3C2410_RTCALM_ALMEN (1 << 6) 48 #define S3C2410_RTCALM_YEAREN (1 << 5) 49 #define S3C2410_RTCALM_MONEN (1 << 4) 50 #define S3C2410_RTCALM_DAYEN (1 << 3) 51 #define S3C2410_RTCALM_HOUREN (1 << 2) 52 #define S3C2410_RTCALM_MINEN (1 << 1) 53 #define S3C2410_RTCALM_SECEN (1 << 0) 54 55 #define S3C2410_ALMSEC S3C2410_RTCREG(0x54) 56 #define S3C2410_ALMMIN S3C2410_RTCREG(0x58) 57 #define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) 58 59 #define S3C2410_ALMDATE S3C2410_RTCREG(0x60) 60 #define S3C2410_ALMMON S3C2410_RTCREG(0x64) 61 #define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) 62 63 #define S3C2410_RTCSEC S3C2410_RTCREG(0x70) 64 #define S3C2410_RTCMIN S3C2410_RTCREG(0x74) 65 #define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) 66 #define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) 67 #define S3C2410_RTCMON S3C2410_RTCREG(0x84) 68 #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) 69 70 #endif /* __ASM_ARCH_REGS_RTC_H */ 71