1 /* 2 * Real Time Clock interface for XScale PXA27x and PXA3xx 3 * 4 * Copyright (C) 2008 Robert Jarzmik 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 #include <linux/init.h> 23 #include <linux/platform_device.h> 24 #include <linux/module.h> 25 #include <linux/rtc.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 31 #include <mach/hardware.h> 32 33 #define TIMER_FREQ CLOCK_TICK_RATE 34 #define RTC_DEF_DIVIDER (32768 - 1) 35 #define RTC_DEF_TRIM 0 36 #define MAXFREQ_PERIODIC 1000 37 38 /* 39 * PXA Registers and bits definitions 40 */ 41 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ 42 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ 43 #define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */ 44 #define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */ 45 #define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */ 46 #define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */ 47 #define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */ 48 #define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */ 49 #define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */ 50 #define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */ 51 #define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */ 52 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ 53 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ 54 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ 55 #define RTSR_AL (1 << 0) /* RTC alarm detected */ 56 #define RTSR_TRIG_MASK (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\ 57 | RTSR_SWAL1 | RTSR_SWAL2) 58 #define RYxR_YEAR_S 9 59 #define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S) 60 #define RYxR_MONTH_S 5 61 #define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S) 62 #define RYxR_DAY_MASK 0x1f 63 #define RDxR_HOUR_S 12 64 #define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S) 65 #define RDxR_MIN_S 6 66 #define RDxR_MIN_MASK (0x3f << RDxR_MIN_S) 67 #define RDxR_SEC_MASK 0x3f 68 69 #define RTSR 0x08 70 #define RTTR 0x0c 71 #define RDCR 0x10 72 #define RYCR 0x14 73 #define RDAR1 0x18 74 #define RYAR1 0x1c 75 #define RTCPICR 0x34 76 #define PIAR 0x38 77 78 #define rtc_readl(pxa_rtc, reg) \ 79 __raw_readl((pxa_rtc)->base + (reg)) 80 #define rtc_writel(pxa_rtc, reg, value) \ 81 __raw_writel((value), (pxa_rtc)->base + (reg)) 82 83 struct pxa_rtc { 84 struct resource *ress; 85 void __iomem *base; 86 int irq_1Hz; 87 int irq_Alrm; 88 struct rtc_device *rtc; 89 spinlock_t lock; /* Protects this structure */ 90 struct rtc_time rtc_alarm; 91 }; 92 93 static u32 ryxr_calc(struct rtc_time *tm) 94 { 95 return ((tm->tm_year + 1900) << RYxR_YEAR_S) 96 | ((tm->tm_mon + 1) << RYxR_MONTH_S) 97 | tm->tm_mday; 98 } 99 100 static u32 rdxr_calc(struct rtc_time *tm) 101 { 102 return (tm->tm_hour << RDxR_HOUR_S) | (tm->tm_min << RDxR_MIN_S) 103 | tm->tm_sec; 104 } 105 106 static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm) 107 { 108 tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900; 109 tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1; 110 tm->tm_mday = (rycr & RYxR_DAY_MASK); 111 tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S; 112 tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S; 113 tm->tm_sec = rdcr & RDxR_SEC_MASK; 114 } 115 116 static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask) 117 { 118 u32 rtsr; 119 120 rtsr = rtc_readl(pxa_rtc, RTSR); 121 rtsr &= ~RTSR_TRIG_MASK; 122 rtsr &= ~mask; 123 rtc_writel(pxa_rtc, RTSR, rtsr); 124 } 125 126 static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask) 127 { 128 u32 rtsr; 129 130 rtsr = rtc_readl(pxa_rtc, RTSR); 131 rtsr &= ~RTSR_TRIG_MASK; 132 rtsr |= mask; 133 rtc_writel(pxa_rtc, RTSR, rtsr); 134 } 135 136 static irqreturn_t pxa_rtc_irq(int irq, void *dev_id) 137 { 138 struct platform_device *pdev = to_platform_device(dev_id); 139 struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev); 140 u32 rtsr; 141 unsigned long events = 0; 142 143 spin_lock(&pxa_rtc->lock); 144 145 /* clear interrupt sources */ 146 rtsr = rtc_readl(pxa_rtc, RTSR); 147 rtc_writel(pxa_rtc, RTSR, rtsr); 148 149 /* temporary disable rtc interrupts */ 150 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE); 151 152 /* clear alarm interrupt if it has occurred */ 153 if (rtsr & RTSR_RDAL1) 154 rtsr &= ~RTSR_RDALE1; 155 156 /* update irq data & counter */ 157 if (rtsr & RTSR_RDAL1) 158 events |= RTC_AF | RTC_IRQF; 159 if (rtsr & RTSR_HZ) 160 events |= RTC_UF | RTC_IRQF; 161 if (rtsr & RTSR_PIAL) 162 events |= RTC_PF | RTC_IRQF; 163 164 rtc_update_irq(pxa_rtc->rtc, 1, events); 165 166 /* enable back rtc interrupts */ 167 rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK); 168 169 spin_unlock(&pxa_rtc->lock); 170 return IRQ_HANDLED; 171 } 172 173 static int pxa_rtc_open(struct device *dev) 174 { 175 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 176 int ret; 177 178 ret = request_irq(pxa_rtc->irq_1Hz, pxa_rtc_irq, IRQF_DISABLED, 179 "rtc 1Hz", dev); 180 if (ret < 0) { 181 dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_1Hz, 182 ret); 183 goto err_irq_1Hz; 184 } 185 ret = request_irq(pxa_rtc->irq_Alrm, pxa_rtc_irq, IRQF_DISABLED, 186 "rtc Alrm", dev); 187 if (ret < 0) { 188 dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_Alrm, 189 ret); 190 goto err_irq_Alrm; 191 } 192 193 return 0; 194 195 err_irq_Alrm: 196 free_irq(pxa_rtc->irq_1Hz, dev); 197 err_irq_1Hz: 198 return ret; 199 } 200 201 static void pxa_rtc_release(struct device *dev) 202 { 203 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 204 205 spin_lock_irq(&pxa_rtc->lock); 206 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE); 207 spin_unlock_irq(&pxa_rtc->lock); 208 209 free_irq(pxa_rtc->irq_Alrm, dev); 210 free_irq(pxa_rtc->irq_1Hz, dev); 211 } 212 213 static int pxa_periodic_irq_set_freq(struct device *dev, int freq) 214 { 215 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 216 int period_ms; 217 218 if (freq < 1 || freq > MAXFREQ_PERIODIC) 219 return -EINVAL; 220 221 period_ms = 1000 / freq; 222 rtc_writel(pxa_rtc, PIAR, period_ms); 223 224 return 0; 225 } 226 227 static int pxa_periodic_irq_set_state(struct device *dev, int enabled) 228 { 229 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 230 231 if (enabled) 232 rtsr_set_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE); 233 else 234 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE); 235 236 return 0; 237 } 238 239 static int pxa_rtc_ioctl(struct device *dev, unsigned int cmd, 240 unsigned long arg) 241 { 242 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 243 int ret = 0; 244 245 spin_lock_irq(&pxa_rtc->lock); 246 switch (cmd) { 247 case RTC_AIE_OFF: 248 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1); 249 break; 250 case RTC_AIE_ON: 251 rtsr_set_bits(pxa_rtc, RTSR_RDALE1); 252 break; 253 case RTC_UIE_OFF: 254 rtsr_clear_bits(pxa_rtc, RTSR_HZE); 255 break; 256 case RTC_UIE_ON: 257 rtsr_set_bits(pxa_rtc, RTSR_HZE); 258 break; 259 default: 260 ret = -ENOIOCTLCMD; 261 } 262 263 spin_unlock_irq(&pxa_rtc->lock); 264 return ret; 265 } 266 267 static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm) 268 { 269 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 270 u32 rycr, rdcr; 271 272 rycr = rtc_readl(pxa_rtc, RYCR); 273 rdcr = rtc_readl(pxa_rtc, RDCR); 274 275 tm_calc(rycr, rdcr, tm); 276 return 0; 277 } 278 279 static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm) 280 { 281 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 282 283 rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm)); 284 rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm)); 285 286 return 0; 287 } 288 289 static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 290 { 291 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 292 u32 rtsr, ryar, rdar; 293 294 ryar = rtc_readl(pxa_rtc, RYAR1); 295 rdar = rtc_readl(pxa_rtc, RDAR1); 296 tm_calc(ryar, rdar, &alrm->time); 297 298 rtsr = rtc_readl(pxa_rtc, RTSR); 299 alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0; 300 alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0; 301 return 0; 302 } 303 304 static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 305 { 306 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 307 u32 rtsr; 308 309 spin_lock_irq(&pxa_rtc->lock); 310 311 rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time)); 312 rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time)); 313 314 rtsr = rtc_readl(pxa_rtc, RTSR); 315 if (alrm->enabled) 316 rtsr |= RTSR_RDALE1; 317 else 318 rtsr &= ~RTSR_RDALE1; 319 rtc_writel(pxa_rtc, RTSR, rtsr); 320 321 spin_unlock_irq(&pxa_rtc->lock); 322 323 return 0; 324 } 325 326 static int pxa_rtc_proc(struct device *dev, struct seq_file *seq) 327 { 328 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 329 330 seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR)); 331 seq_printf(seq, "update_IRQ\t: %s\n", 332 (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no"); 333 seq_printf(seq, "periodic_IRQ\t: %s\n", 334 (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no"); 335 seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR)); 336 337 return 0; 338 } 339 340 static const struct rtc_class_ops pxa_rtc_ops = { 341 .open = pxa_rtc_open, 342 .release = pxa_rtc_release, 343 .ioctl = pxa_rtc_ioctl, 344 .read_time = pxa_rtc_read_time, 345 .set_time = pxa_rtc_set_time, 346 .read_alarm = pxa_rtc_read_alarm, 347 .set_alarm = pxa_rtc_set_alarm, 348 .proc = pxa_rtc_proc, 349 .irq_set_state = pxa_periodic_irq_set_state, 350 .irq_set_freq = pxa_periodic_irq_set_freq, 351 }; 352 353 static int __init pxa_rtc_probe(struct platform_device *pdev) 354 { 355 struct device *dev = &pdev->dev; 356 struct pxa_rtc *pxa_rtc; 357 int ret; 358 u32 rttr; 359 360 pxa_rtc = kzalloc(sizeof(struct pxa_rtc), GFP_KERNEL); 361 if (!pxa_rtc) 362 return -ENOMEM; 363 364 spin_lock_init(&pxa_rtc->lock); 365 platform_set_drvdata(pdev, pxa_rtc); 366 367 ret = -ENXIO; 368 pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0); 369 if (!pxa_rtc->ress) { 370 dev_err(dev, "No I/O memory resource defined\n"); 371 goto err_ress; 372 } 373 374 pxa_rtc->irq_1Hz = platform_get_irq(pdev, 0); 375 if (pxa_rtc->irq_1Hz < 0) { 376 dev_err(dev, "No 1Hz IRQ resource defined\n"); 377 goto err_ress; 378 } 379 pxa_rtc->irq_Alrm = platform_get_irq(pdev, 1); 380 if (pxa_rtc->irq_Alrm < 0) { 381 dev_err(dev, "No alarm IRQ resource defined\n"); 382 goto err_ress; 383 } 384 385 ret = -ENOMEM; 386 pxa_rtc->base = ioremap(pxa_rtc->ress->start, 387 resource_size(pxa_rtc->ress)); 388 if (!pxa_rtc->base) { 389 dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n"); 390 goto err_map; 391 } 392 393 /* 394 * If the clock divider is uninitialized then reset it to the 395 * default value to get the 1Hz clock. 396 */ 397 if (rtc_readl(pxa_rtc, RTTR) == 0) { 398 rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); 399 rtc_writel(pxa_rtc, RTTR, rttr); 400 dev_warn(dev, "warning: initializing default clock" 401 " divider/trim value\n"); 402 } 403 404 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE); 405 406 pxa_rtc->rtc = rtc_device_register("pxa-rtc", &pdev->dev, &pxa_rtc_ops, 407 THIS_MODULE); 408 ret = PTR_ERR(pxa_rtc->rtc); 409 if (IS_ERR(pxa_rtc->rtc)) { 410 dev_err(dev, "Failed to register RTC device -> %d\n", ret); 411 goto err_rtc_reg; 412 } 413 414 device_init_wakeup(dev, 1); 415 416 return 0; 417 418 err_rtc_reg: 419 iounmap(pxa_rtc->base); 420 err_ress: 421 err_map: 422 kfree(pxa_rtc); 423 return ret; 424 } 425 426 static int __exit pxa_rtc_remove(struct platform_device *pdev) 427 { 428 struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev); 429 430 rtc_device_unregister(pxa_rtc->rtc); 431 432 spin_lock_irq(&pxa_rtc->lock); 433 iounmap(pxa_rtc->base); 434 spin_unlock_irq(&pxa_rtc->lock); 435 436 kfree(pxa_rtc); 437 438 return 0; 439 } 440 441 #ifdef CONFIG_PM 442 static int pxa_rtc_suspend(struct device *dev) 443 { 444 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 445 446 if (device_may_wakeup(dev)) 447 enable_irq_wake(pxa_rtc->irq_Alrm); 448 return 0; 449 } 450 451 static int pxa_rtc_resume(struct device *dev) 452 { 453 struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); 454 455 if (device_may_wakeup(dev)) 456 disable_irq_wake(pxa_rtc->irq_Alrm); 457 return 0; 458 } 459 460 static const struct dev_pm_ops pxa_rtc_pm_ops = { 461 .suspend = pxa_rtc_suspend, 462 .resume = pxa_rtc_resume, 463 }; 464 #endif 465 466 static struct platform_driver pxa_rtc_driver = { 467 .remove = __exit_p(pxa_rtc_remove), 468 .driver = { 469 .name = "pxa-rtc", 470 #ifdef CONFIG_PM 471 .pm = &pxa_rtc_pm_ops, 472 #endif 473 }, 474 }; 475 476 static int __init pxa_rtc_init(void) 477 { 478 if (cpu_is_pxa27x() || cpu_is_pxa3xx()) 479 return platform_driver_probe(&pxa_rtc_driver, pxa_rtc_probe); 480 481 return -ENODEV; 482 } 483 484 static void __exit pxa_rtc_exit(void) 485 { 486 platform_driver_unregister(&pxa_rtc_driver); 487 } 488 489 module_init(pxa_rtc_init); 490 module_exit(pxa_rtc_exit); 491 492 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>"); 493 MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)"); 494 MODULE_LICENSE("GPL"); 495 MODULE_ALIAS("platform:pxa-rtc"); 496