1 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 #include <linux/of.h> 13 #include <linux/module.h> 14 #include <linux/init.h> 15 #include <linux/rtc.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <linux/spinlock.h> 21 22 /* RTC Register offsets from RTC CTRL REG */ 23 #define PM8XXX_ALARM_CTRL_OFFSET 0x01 24 #define PM8XXX_RTC_WRITE_OFFSET 0x02 25 #define PM8XXX_RTC_READ_OFFSET 0x06 26 #define PM8XXX_ALARM_RW_OFFSET 0x0A 27 28 /* RTC_CTRL register bit fields */ 29 #define PM8xxx_RTC_ENABLE BIT(7) 30 #define PM8xxx_RTC_ALARM_CLEAR BIT(0) 31 32 #define NUM_8_BIT_RTC_REGS 0x4 33 34 /** 35 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions 36 * @ctrl: base address of control register 37 * @write: base address of write register 38 * @read: base address of read register 39 * @alarm_ctrl: base address of alarm control register 40 * @alarm_ctrl2: base address of alarm control2 register 41 * @alarm_rw: base address of alarm read-write register 42 * @alarm_en: alarm enable mask 43 */ 44 struct pm8xxx_rtc_regs { 45 unsigned int ctrl; 46 unsigned int write; 47 unsigned int read; 48 unsigned int alarm_ctrl; 49 unsigned int alarm_ctrl2; 50 unsigned int alarm_rw; 51 unsigned int alarm_en; 52 }; 53 54 /** 55 * struct pm8xxx_rtc - rtc driver internal structure 56 * @rtc: rtc device for this driver. 57 * @regmap: regmap used to access RTC registers 58 * @allow_set_time: indicates whether writing to the RTC is allowed 59 * @rtc_alarm_irq: rtc alarm irq number. 60 * @ctrl_reg: rtc control register. 61 * @rtc_dev: device structure. 62 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg. 63 */ 64 struct pm8xxx_rtc { 65 struct rtc_device *rtc; 66 struct regmap *regmap; 67 bool allow_set_time; 68 int rtc_alarm_irq; 69 const struct pm8xxx_rtc_regs *regs; 70 struct device *rtc_dev; 71 spinlock_t ctrl_reg_lock; 72 }; 73 74 /* 75 * Steps to write the RTC registers. 76 * 1. Disable alarm if enabled. 77 * 2. Disable rtc if enabled. 78 * 3. Write 0x00 to LSB. 79 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0]. 80 * 5. Enable rtc if disabled in step 2. 81 * 6. Enable alarm if disabled in step 1. 82 */ 83 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm) 84 { 85 int rc, i; 86 unsigned long secs, irq_flags; 87 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0; 88 unsigned int ctrl_reg, rtc_ctrl_reg; 89 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 90 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; 91 92 if (!rtc_dd->allow_set_time) 93 return -EACCES; 94 95 rtc_tm_to_time(tm, &secs); 96 97 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs); 98 99 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { 100 value[i] = secs & 0xFF; 101 secs >>= 8; 102 } 103 104 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); 105 106 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); 107 if (rc) 108 goto rtc_rw_fail; 109 110 if (ctrl_reg & regs->alarm_en) { 111 alarm_enabled = 1; 112 ctrl_reg &= ~regs->alarm_en; 113 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); 114 if (rc) { 115 dev_err(dev, "Write to RTC Alarm control register failed\n"); 116 goto rtc_rw_fail; 117 } 118 } 119 120 /* Disable RTC H/w before writing on RTC register */ 121 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg); 122 if (rc) 123 goto rtc_rw_fail; 124 125 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) { 126 rtc_disabled = 1; 127 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE; 128 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg); 129 if (rc) { 130 dev_err(dev, "Write to RTC control register failed\n"); 131 goto rtc_rw_fail; 132 } 133 } 134 135 /* Write 0 to Byte[0] */ 136 rc = regmap_write(rtc_dd->regmap, regs->write, 0); 137 if (rc) { 138 dev_err(dev, "Write to RTC write data register failed\n"); 139 goto rtc_rw_fail; 140 } 141 142 /* Write Byte[1], Byte[2], Byte[3] */ 143 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1, 144 &value[1], sizeof(value) - 1); 145 if (rc) { 146 dev_err(dev, "Write to RTC write data register failed\n"); 147 goto rtc_rw_fail; 148 } 149 150 /* Write Byte[0] */ 151 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]); 152 if (rc) { 153 dev_err(dev, "Write to RTC write data register failed\n"); 154 goto rtc_rw_fail; 155 } 156 157 /* Enable RTC H/w after writing on RTC register */ 158 if (rtc_disabled) { 159 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE; 160 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg); 161 if (rc) { 162 dev_err(dev, "Write to RTC control register failed\n"); 163 goto rtc_rw_fail; 164 } 165 } 166 167 if (alarm_enabled) { 168 ctrl_reg |= regs->alarm_en; 169 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); 170 if (rc) { 171 dev_err(dev, "Write to RTC Alarm control register failed\n"); 172 goto rtc_rw_fail; 173 } 174 } 175 176 rtc_rw_fail: 177 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 178 179 return rc; 180 } 181 182 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm) 183 { 184 int rc; 185 u8 value[NUM_8_BIT_RTC_REGS]; 186 unsigned long secs; 187 unsigned int reg; 188 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 189 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; 190 191 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value)); 192 if (rc) { 193 dev_err(dev, "RTC read data register failed\n"); 194 return rc; 195 } 196 197 /* 198 * Read the LSB again and check if there has been a carry over. 199 * If there is, redo the read operation. 200 */ 201 rc = regmap_read(rtc_dd->regmap, regs->read, ®); 202 if (rc < 0) { 203 dev_err(dev, "RTC read data register failed\n"); 204 return rc; 205 } 206 207 if (unlikely(reg < value[0])) { 208 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, 209 value, sizeof(value)); 210 if (rc) { 211 dev_err(dev, "RTC read data register failed\n"); 212 return rc; 213 } 214 } 215 216 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24); 217 218 rtc_time_to_tm(secs, tm); 219 220 dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n", 221 secs, tm->tm_hour, tm->tm_min, tm->tm_sec, 222 tm->tm_mday, tm->tm_mon, tm->tm_year); 223 224 return 0; 225 } 226 227 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 228 { 229 int rc, i; 230 u8 value[NUM_8_BIT_RTC_REGS]; 231 unsigned int ctrl_reg; 232 unsigned long secs, irq_flags; 233 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 234 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; 235 236 rtc_tm_to_time(&alarm->time, &secs); 237 238 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { 239 value[i] = secs & 0xFF; 240 secs >>= 8; 241 } 242 243 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); 244 245 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value, 246 sizeof(value)); 247 if (rc) { 248 dev_err(dev, "Write to RTC ALARM register failed\n"); 249 goto rtc_rw_fail; 250 } 251 252 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); 253 if (rc) 254 goto rtc_rw_fail; 255 256 if (alarm->enabled) 257 ctrl_reg |= regs->alarm_en; 258 else 259 ctrl_reg &= ~regs->alarm_en; 260 261 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); 262 if (rc) { 263 dev_err(dev, "Write to RTC alarm control register failed\n"); 264 goto rtc_rw_fail; 265 } 266 267 dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", 268 alarm->time.tm_hour, alarm->time.tm_min, 269 alarm->time.tm_sec, alarm->time.tm_mday, 270 alarm->time.tm_mon, alarm->time.tm_year); 271 rtc_rw_fail: 272 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 273 return rc; 274 } 275 276 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 277 { 278 int rc; 279 u8 value[NUM_8_BIT_RTC_REGS]; 280 unsigned long secs; 281 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 282 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; 283 284 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value, 285 sizeof(value)); 286 if (rc) { 287 dev_err(dev, "RTC alarm time read failed\n"); 288 return rc; 289 } 290 291 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24); 292 293 rtc_time_to_tm(secs, &alarm->time); 294 295 rc = rtc_valid_tm(&alarm->time); 296 if (rc < 0) { 297 dev_err(dev, "Invalid alarm time read from RTC\n"); 298 return rc; 299 } 300 301 dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", 302 alarm->time.tm_hour, alarm->time.tm_min, 303 alarm->time.tm_sec, alarm->time.tm_mday, 304 alarm->time.tm_mon, alarm->time.tm_year); 305 306 return 0; 307 } 308 309 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) 310 { 311 int rc; 312 unsigned long irq_flags; 313 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 314 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; 315 unsigned int ctrl_reg; 316 317 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); 318 319 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); 320 if (rc) 321 goto rtc_rw_fail; 322 323 if (enable) 324 ctrl_reg |= regs->alarm_en; 325 else 326 ctrl_reg &= ~regs->alarm_en; 327 328 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); 329 if (rc) { 330 dev_err(dev, "Write to RTC control register failed\n"); 331 goto rtc_rw_fail; 332 } 333 334 rtc_rw_fail: 335 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 336 return rc; 337 } 338 339 static const struct rtc_class_ops pm8xxx_rtc_ops = { 340 .read_time = pm8xxx_rtc_read_time, 341 .set_time = pm8xxx_rtc_set_time, 342 .set_alarm = pm8xxx_rtc_set_alarm, 343 .read_alarm = pm8xxx_rtc_read_alarm, 344 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable, 345 }; 346 347 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) 348 { 349 struct pm8xxx_rtc *rtc_dd = dev_id; 350 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; 351 unsigned int ctrl_reg; 352 int rc; 353 unsigned long irq_flags; 354 355 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF); 356 357 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); 358 359 /* Clear the alarm enable bit */ 360 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); 361 if (rc) { 362 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 363 goto rtc_alarm_handled; 364 } 365 366 ctrl_reg &= ~regs->alarm_en; 367 368 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); 369 if (rc) { 370 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 371 dev_err(rtc_dd->rtc_dev, 372 "Write to alarm control register failed\n"); 373 goto rtc_alarm_handled; 374 } 375 376 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); 377 378 /* Clear RTC alarm register */ 379 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg); 380 if (rc) { 381 dev_err(rtc_dd->rtc_dev, 382 "RTC Alarm control2 register read failed\n"); 383 goto rtc_alarm_handled; 384 } 385 386 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR; 387 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg); 388 if (rc) 389 dev_err(rtc_dd->rtc_dev, 390 "Write to RTC Alarm control2 register failed\n"); 391 392 rtc_alarm_handled: 393 return IRQ_HANDLED; 394 } 395 396 static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd) 397 { 398 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; 399 unsigned int ctrl_reg; 400 int rc; 401 402 /* Check if the RTC is on, else turn it on */ 403 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg); 404 if (rc) 405 return rc; 406 407 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) { 408 ctrl_reg |= PM8xxx_RTC_ENABLE; 409 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg); 410 if (rc) 411 return rc; 412 } 413 414 return 0; 415 } 416 417 static const struct pm8xxx_rtc_regs pm8921_regs = { 418 .ctrl = 0x11d, 419 .write = 0x11f, 420 .read = 0x123, 421 .alarm_rw = 0x127, 422 .alarm_ctrl = 0x11d, 423 .alarm_ctrl2 = 0x11e, 424 .alarm_en = BIT(1), 425 }; 426 427 static const struct pm8xxx_rtc_regs pm8058_regs = { 428 .ctrl = 0x1e8, 429 .write = 0x1ea, 430 .read = 0x1ee, 431 .alarm_rw = 0x1f2, 432 .alarm_ctrl = 0x1e8, 433 .alarm_ctrl2 = 0x1e9, 434 .alarm_en = BIT(1), 435 }; 436 437 static const struct pm8xxx_rtc_regs pm8941_regs = { 438 .ctrl = 0x6046, 439 .write = 0x6040, 440 .read = 0x6048, 441 .alarm_rw = 0x6140, 442 .alarm_ctrl = 0x6146, 443 .alarm_ctrl2 = 0x6148, 444 .alarm_en = BIT(7), 445 }; 446 447 /* 448 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out 449 */ 450 static const struct of_device_id pm8xxx_id_table[] = { 451 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs }, 452 { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs }, 453 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs }, 454 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs }, 455 { }, 456 }; 457 MODULE_DEVICE_TABLE(of, pm8xxx_id_table); 458 459 static int pm8xxx_rtc_probe(struct platform_device *pdev) 460 { 461 int rc; 462 struct pm8xxx_rtc *rtc_dd; 463 const struct of_device_id *match; 464 465 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node); 466 if (!match) 467 return -ENXIO; 468 469 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL); 470 if (rtc_dd == NULL) 471 return -ENOMEM; 472 473 /* Initialise spinlock to protect RTC control register */ 474 spin_lock_init(&rtc_dd->ctrl_reg_lock); 475 476 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL); 477 if (!rtc_dd->regmap) { 478 dev_err(&pdev->dev, "Parent regmap unavailable.\n"); 479 return -ENXIO; 480 } 481 482 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0); 483 if (rtc_dd->rtc_alarm_irq < 0) { 484 dev_err(&pdev->dev, "Alarm IRQ resource absent!\n"); 485 return -ENXIO; 486 } 487 488 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node, 489 "allow-set-time"); 490 491 rtc_dd->regs = match->data; 492 rtc_dd->rtc_dev = &pdev->dev; 493 494 rc = pm8xxx_rtc_enable(rtc_dd); 495 if (rc) 496 return rc; 497 498 platform_set_drvdata(pdev, rtc_dd); 499 500 device_init_wakeup(&pdev->dev, 1); 501 502 /* Register the RTC device */ 503 rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc", 504 &pm8xxx_rtc_ops, THIS_MODULE); 505 if (IS_ERR(rtc_dd->rtc)) { 506 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n", 507 __func__, PTR_ERR(rtc_dd->rtc)); 508 return PTR_ERR(rtc_dd->rtc); 509 } 510 511 /* Request the alarm IRQ */ 512 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq, 513 pm8xxx_alarm_trigger, 514 IRQF_TRIGGER_RISING, 515 "pm8xxx_rtc_alarm", rtc_dd); 516 if (rc < 0) { 517 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc); 518 return rc; 519 } 520 521 dev_dbg(&pdev->dev, "Probe success !!\n"); 522 523 return 0; 524 } 525 526 #ifdef CONFIG_PM_SLEEP 527 static int pm8xxx_rtc_resume(struct device *dev) 528 { 529 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 530 531 if (device_may_wakeup(dev)) 532 disable_irq_wake(rtc_dd->rtc_alarm_irq); 533 534 return 0; 535 } 536 537 static int pm8xxx_rtc_suspend(struct device *dev) 538 { 539 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); 540 541 if (device_may_wakeup(dev)) 542 enable_irq_wake(rtc_dd->rtc_alarm_irq); 543 544 return 0; 545 } 546 #endif 547 548 static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops, 549 pm8xxx_rtc_suspend, 550 pm8xxx_rtc_resume); 551 552 static struct platform_driver pm8xxx_rtc_driver = { 553 .probe = pm8xxx_rtc_probe, 554 .driver = { 555 .name = "rtc-pm8xxx", 556 .pm = &pm8xxx_rtc_pm_ops, 557 .of_match_table = pm8xxx_id_table, 558 }, 559 }; 560 561 module_platform_driver(pm8xxx_rtc_driver); 562 563 MODULE_ALIAS("platform:rtc-pm8xxx"); 564 MODULE_DESCRIPTION("PMIC8xxx RTC driver"); 565 MODULE_LICENSE("GPL v2"); 566 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>"); 567