1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com> 10 * 11 * based on the other drivers in this same directory. 12 * 13 * Datasheet: http://cache.nxp.com/documents/data_sheet/PCF2127.pdf 14 */ 15 16 #include <linux/i2c.h> 17 #include <linux/spi/spi.h> 18 #include <linux/bcd.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/regmap.h> 25 #include <linux/watchdog.h> 26 27 /* Control register 1 */ 28 #define PCF2127_REG_CTRL1 0x00 29 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 30 /* Control register 2 */ 31 #define PCF2127_REG_CTRL2 0x01 32 #define PCF2127_BIT_CTRL2_AIE BIT(1) 33 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 34 #define PCF2127_BIT_CTRL2_AF BIT(4) 35 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 36 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 37 /* Control register 3 */ 38 #define PCF2127_REG_CTRL3 0x02 39 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 40 #define PCF2127_BIT_CTRL3_BIE BIT(1) 41 #define PCF2127_BIT_CTRL3_BLF BIT(2) 42 #define PCF2127_BIT_CTRL3_BF BIT(3) 43 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 44 /* Time and date registers */ 45 #define PCF2127_REG_SC 0x03 46 #define PCF2127_BIT_SC_OSF BIT(7) 47 #define PCF2127_REG_MN 0x04 48 #define PCF2127_REG_HR 0x05 49 #define PCF2127_REG_DM 0x06 50 #define PCF2127_REG_DW 0x07 51 #define PCF2127_REG_MO 0x08 52 #define PCF2127_REG_YR 0x09 53 /* Alarm registers */ 54 #define PCF2127_REG_ALARM_SC 0x0A 55 #define PCF2127_REG_ALARM_MN 0x0B 56 #define PCF2127_REG_ALARM_HR 0x0C 57 #define PCF2127_REG_ALARM_DM 0x0D 58 #define PCF2127_REG_ALARM_DW 0x0E 59 #define PCF2127_BIT_ALARM_AE BIT(7) 60 /* Watchdog registers */ 61 #define PCF2127_REG_WD_CTL 0x10 62 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 63 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 64 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 65 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 66 #define PCF2127_REG_WD_VAL 0x11 67 /* Tamper timestamp registers */ 68 #define PCF2127_REG_TS_CTRL 0x12 69 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 70 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 71 #define PCF2127_REG_TS_SC 0x13 72 #define PCF2127_REG_TS_MN 0x14 73 #define PCF2127_REG_TS_HR 0x15 74 #define PCF2127_REG_TS_DM 0x16 75 #define PCF2127_REG_TS_MO 0x17 76 #define PCF2127_REG_TS_YR 0x18 77 /* 78 * RAM registers 79 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 80 * battery backed and can survive a power outage. 81 * PCF2129 doesn't have this feature. 82 */ 83 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 84 #define PCF2127_REG_RAM_WRT_CMD 0x1C 85 #define PCF2127_REG_RAM_RD_CMD 0x1D 86 87 /* Watchdog timer value constants */ 88 #define PCF2127_WD_VAL_STOP 0 89 #define PCF2127_WD_VAL_MIN 2 90 #define PCF2127_WD_VAL_MAX 255 91 #define PCF2127_WD_VAL_DEFAULT 60 92 93 struct pcf2127 { 94 struct rtc_device *rtc; 95 struct watchdog_device wdd; 96 struct regmap *regmap; 97 }; 98 99 /* 100 * In the routines that deal directly with the pcf2127 hardware, we use 101 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 102 */ 103 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 104 { 105 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 106 unsigned char buf[10]; 107 int ret; 108 109 /* 110 * Avoid reading CTRL2 register as it causes WD_VAL register 111 * value to reset to 0 which means watchdog is stopped. 112 */ 113 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL3, 114 (buf + PCF2127_REG_CTRL3), 115 ARRAY_SIZE(buf) - PCF2127_REG_CTRL3); 116 if (ret) { 117 dev_err(dev, "%s: read error\n", __func__); 118 return ret; 119 } 120 121 if (buf[PCF2127_REG_CTRL3] & PCF2127_BIT_CTRL3_BLF) 122 dev_info(dev, 123 "low voltage detected, check/replace RTC battery.\n"); 124 125 /* Clock integrity is not guaranteed when OSF flag is set. */ 126 if (buf[PCF2127_REG_SC] & PCF2127_BIT_SC_OSF) { 127 /* 128 * no need clear the flag here, 129 * it will be cleared once the new date is saved 130 */ 131 dev_warn(dev, 132 "oscillator stop detected, date/time is not reliable\n"); 133 return -EINVAL; 134 } 135 136 dev_dbg(dev, 137 "%s: raw data is cr3=%02x, sec=%02x, min=%02x, hr=%02x, " 138 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 139 __func__, buf[PCF2127_REG_CTRL3], buf[PCF2127_REG_SC], 140 buf[PCF2127_REG_MN], buf[PCF2127_REG_HR], 141 buf[PCF2127_REG_DM], buf[PCF2127_REG_DW], 142 buf[PCF2127_REG_MO], buf[PCF2127_REG_YR]); 143 144 tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F); 145 tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F); 146 tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F); /* rtc hr 0-23 */ 147 tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F); 148 tm->tm_wday = buf[PCF2127_REG_DW] & 0x07; 149 tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */ 150 tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]); 151 tm->tm_year += 100; 152 153 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 154 "mday=%d, mon=%d, year=%d, wday=%d\n", 155 __func__, 156 tm->tm_sec, tm->tm_min, tm->tm_hour, 157 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 158 159 return 0; 160 } 161 162 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 163 { 164 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 165 unsigned char buf[7]; 166 int i = 0, err; 167 168 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 169 "mday=%d, mon=%d, year=%d, wday=%d\n", 170 __func__, 171 tm->tm_sec, tm->tm_min, tm->tm_hour, 172 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 173 174 /* hours, minutes and seconds */ 175 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 176 buf[i++] = bin2bcd(tm->tm_min); 177 buf[i++] = bin2bcd(tm->tm_hour); 178 buf[i++] = bin2bcd(tm->tm_mday); 179 buf[i++] = tm->tm_wday & 0x07; 180 181 /* month, 1 - 12 */ 182 buf[i++] = bin2bcd(tm->tm_mon + 1); 183 184 /* year */ 185 buf[i++] = bin2bcd(tm->tm_year - 100); 186 187 /* write register's data */ 188 err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i); 189 if (err) { 190 dev_err(dev, 191 "%s: err=%d", __func__, err); 192 return err; 193 } 194 195 return 0; 196 } 197 198 static int pcf2127_rtc_ioctl(struct device *dev, 199 unsigned int cmd, unsigned long arg) 200 { 201 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 202 int val, touser = 0; 203 int ret; 204 205 switch (cmd) { 206 case RTC_VL_READ: 207 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 208 if (ret) 209 return ret; 210 211 if (val & PCF2127_BIT_CTRL3_BLF) 212 touser |= RTC_VL_BACKUP_LOW; 213 214 if (val & PCF2127_BIT_CTRL3_BF) 215 touser |= RTC_VL_BACKUP_SWITCH; 216 217 return put_user(touser, (unsigned int __user *)arg); 218 219 case RTC_VL_CLR: 220 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 221 PCF2127_BIT_CTRL3_BF, 0); 222 223 default: 224 return -ENOIOCTLCMD; 225 } 226 } 227 228 static const struct rtc_class_ops pcf2127_rtc_ops = { 229 .ioctl = pcf2127_rtc_ioctl, 230 .read_time = pcf2127_rtc_read_time, 231 .set_time = pcf2127_rtc_set_time, 232 }; 233 234 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 235 void *val, size_t bytes) 236 { 237 struct pcf2127 *pcf2127 = priv; 238 int ret; 239 unsigned char offsetbuf[] = { offset >> 8, offset }; 240 241 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 242 offsetbuf, 2); 243 if (ret) 244 return ret; 245 246 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 247 val, bytes); 248 249 return ret ?: bytes; 250 } 251 252 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 253 void *val, size_t bytes) 254 { 255 struct pcf2127 *pcf2127 = priv; 256 int ret; 257 unsigned char offsetbuf[] = { offset >> 8, offset }; 258 259 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 260 offsetbuf, 2); 261 if (ret) 262 return ret; 263 264 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 265 val, bytes); 266 267 return ret ?: bytes; 268 } 269 270 /* watchdog driver */ 271 272 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 273 { 274 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 275 276 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout); 277 } 278 279 /* 280 * Restart watchdog timer if feature is active. 281 * 282 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 283 * since register also contain control/status flags for other features. 284 * Always call this function after reading CTRL2 register. 285 */ 286 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 287 { 288 int ret = 0; 289 290 if (watchdog_active(wdd)) { 291 ret = pcf2127_wdt_ping(wdd); 292 if (ret) 293 dev_err(wdd->parent, 294 "%s: watchdog restart failed, ret=%d\n", 295 __func__, ret); 296 } 297 298 return ret; 299 } 300 301 static int pcf2127_wdt_start(struct watchdog_device *wdd) 302 { 303 return pcf2127_wdt_ping(wdd); 304 } 305 306 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 307 { 308 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 309 310 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, 311 PCF2127_WD_VAL_STOP); 312 } 313 314 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 315 unsigned int new_timeout) 316 { 317 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 318 new_timeout, wdd->timeout); 319 320 wdd->timeout = new_timeout; 321 322 return pcf2127_wdt_active_ping(wdd); 323 } 324 325 static const struct watchdog_info pcf2127_wdt_info = { 326 .identity = "NXP PCF2127/PCF2129 Watchdog", 327 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 328 }; 329 330 static const struct watchdog_ops pcf2127_watchdog_ops = { 331 .owner = THIS_MODULE, 332 .start = pcf2127_wdt_start, 333 .stop = pcf2127_wdt_stop, 334 .ping = pcf2127_wdt_ping, 335 .set_timeout = pcf2127_wdt_set_timeout, 336 }; 337 338 /* Alarm */ 339 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 340 { 341 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 342 unsigned int buf[5], ctrl2; 343 int ret; 344 345 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 346 if (ret) 347 return ret; 348 349 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 350 if (ret) 351 return ret; 352 353 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 354 sizeof(buf)); 355 if (ret) 356 return ret; 357 358 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 359 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 360 361 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 362 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 363 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 364 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 365 366 return 0; 367 } 368 369 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 370 { 371 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 372 int ret; 373 374 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 375 PCF2127_BIT_CTRL2_AIE, 376 enable ? PCF2127_BIT_CTRL2_AIE : 0); 377 if (ret) 378 return ret; 379 380 return pcf2127_wdt_active_ping(&pcf2127->wdd); 381 } 382 383 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 384 { 385 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 386 uint8_t buf[5]; 387 int ret; 388 389 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 390 PCF2127_BIT_CTRL2_AF, 0); 391 if (ret) 392 return ret; 393 394 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 395 if (ret) 396 return ret; 397 398 buf[0] = bin2bcd(alrm->time.tm_sec); 399 buf[1] = bin2bcd(alrm->time.tm_min); 400 buf[2] = bin2bcd(alrm->time.tm_hour); 401 buf[3] = bin2bcd(alrm->time.tm_mday); 402 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 403 404 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 405 sizeof(buf)); 406 if (ret) 407 return ret; 408 409 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 410 } 411 412 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 413 { 414 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 415 unsigned int ctrl2 = 0; 416 int ret = 0; 417 418 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 419 if (ret) 420 return IRQ_NONE; 421 422 if (!(ctrl2 & PCF2127_BIT_CTRL2_AF)) 423 return IRQ_NONE; 424 425 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 426 ctrl2 & ~(PCF2127_BIT_CTRL2_AF | PCF2127_BIT_CTRL2_WDTF)); 427 428 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 429 430 pcf2127_wdt_active_ping(&pcf2127->wdd); 431 432 return IRQ_HANDLED; 433 } 434 435 static const struct rtc_class_ops pcf2127_rtc_alrm_ops = { 436 .ioctl = pcf2127_rtc_ioctl, 437 .read_time = pcf2127_rtc_read_time, 438 .set_time = pcf2127_rtc_set_time, 439 .read_alarm = pcf2127_rtc_read_alarm, 440 .set_alarm = pcf2127_rtc_set_alarm, 441 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 442 }; 443 444 /* sysfs interface */ 445 446 static ssize_t timestamp0_store(struct device *dev, 447 struct device_attribute *attr, 448 const char *buf, size_t count) 449 { 450 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 451 int ret; 452 453 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 454 PCF2127_BIT_CTRL1_TSF1, 0); 455 if (ret) { 456 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret); 457 return ret; 458 } 459 460 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 461 PCF2127_BIT_CTRL2_TSF2, 0); 462 if (ret) { 463 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret); 464 return ret; 465 } 466 467 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 468 if (ret) 469 return ret; 470 471 return count; 472 }; 473 474 static ssize_t timestamp0_show(struct device *dev, 475 struct device_attribute *attr, char *buf) 476 { 477 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 478 struct rtc_time tm; 479 int ret; 480 unsigned char data[25]; 481 482 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL1, data, 483 sizeof(data)); 484 if (ret) { 485 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 486 return ret; 487 } 488 489 dev_dbg(dev, 490 "%s: raw data is cr1=%02x, cr2=%02x, cr3=%02x, ts_sc=%02x, " 491 "ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 492 __func__, data[PCF2127_REG_CTRL1], data[PCF2127_REG_CTRL2], 493 data[PCF2127_REG_CTRL3], data[PCF2127_REG_TS_SC], 494 data[PCF2127_REG_TS_MN], data[PCF2127_REG_TS_HR], 495 data[PCF2127_REG_TS_DM], data[PCF2127_REG_TS_MO], 496 data[PCF2127_REG_TS_YR]); 497 498 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 499 if (ret) 500 return ret; 501 502 if (!(data[PCF2127_REG_CTRL1] & PCF2127_BIT_CTRL1_TSF1) && 503 !(data[PCF2127_REG_CTRL2] & PCF2127_BIT_CTRL2_TSF2)) 504 return 0; 505 506 tm.tm_sec = bcd2bin(data[PCF2127_REG_TS_SC] & 0x7F); 507 tm.tm_min = bcd2bin(data[PCF2127_REG_TS_MN] & 0x7F); 508 tm.tm_hour = bcd2bin(data[PCF2127_REG_TS_HR] & 0x3F); 509 tm.tm_mday = bcd2bin(data[PCF2127_REG_TS_DM] & 0x3F); 510 /* TS_MO register (month) value range: 1-12 */ 511 tm.tm_mon = bcd2bin(data[PCF2127_REG_TS_MO] & 0x1F) - 1; 512 tm.tm_year = bcd2bin(data[PCF2127_REG_TS_YR]); 513 if (tm.tm_year < 70) 514 tm.tm_year += 100; /* assume we are in 1970...2069 */ 515 516 ret = rtc_valid_tm(&tm); 517 if (ret) 518 return ret; 519 520 return sprintf(buf, "%llu\n", 521 (unsigned long long)rtc_tm_to_time64(&tm)); 522 }; 523 524 static DEVICE_ATTR_RW(timestamp0); 525 526 static struct attribute *pcf2127_attrs[] = { 527 &dev_attr_timestamp0.attr, 528 NULL 529 }; 530 531 static const struct attribute_group pcf2127_attr_group = { 532 .attrs = pcf2127_attrs, 533 }; 534 535 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 536 int alarm_irq, const char *name, bool has_nvmem) 537 { 538 struct pcf2127 *pcf2127; 539 u32 wdd_timeout; 540 int ret = 0; 541 542 dev_dbg(dev, "%s\n", __func__); 543 544 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 545 if (!pcf2127) 546 return -ENOMEM; 547 548 pcf2127->regmap = regmap; 549 550 dev_set_drvdata(dev, pcf2127); 551 552 pcf2127->rtc = devm_rtc_allocate_device(dev); 553 if (IS_ERR(pcf2127->rtc)) 554 return PTR_ERR(pcf2127->rtc); 555 556 pcf2127->rtc->ops = &pcf2127_rtc_ops; 557 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 558 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 559 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 560 pcf2127->rtc->uie_unsupported = 1; 561 562 if (alarm_irq >= 0) { 563 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 564 pcf2127_rtc_irq, 565 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 566 dev_name(dev), dev); 567 if (ret) { 568 dev_err(dev, "failed to request alarm irq\n"); 569 return ret; 570 } 571 } 572 573 if (alarm_irq >= 0 || device_property_read_bool(dev, "wakeup-source")) { 574 device_init_wakeup(dev, true); 575 pcf2127->rtc->ops = &pcf2127_rtc_alrm_ops; 576 } 577 578 pcf2127->wdd.parent = dev; 579 pcf2127->wdd.info = &pcf2127_wdt_info; 580 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 581 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 582 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 583 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 584 pcf2127->wdd.min_hw_heartbeat_ms = 500; 585 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 586 587 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 588 589 if (has_nvmem) { 590 struct nvmem_config nvmem_cfg = { 591 .priv = pcf2127, 592 .reg_read = pcf2127_nvmem_read, 593 .reg_write = pcf2127_nvmem_write, 594 .size = 512, 595 }; 596 597 ret = rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 598 } 599 600 /* 601 * Watchdog timer enabled and reset pin /RST activated when timed out. 602 * Select 1Hz clock source for watchdog timer. 603 * Note: Countdown timer disabled and not available. 604 */ 605 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL, 606 PCF2127_BIT_WD_CTL_CD1 | 607 PCF2127_BIT_WD_CTL_CD0 | 608 PCF2127_BIT_WD_CTL_TF1 | 609 PCF2127_BIT_WD_CTL_TF0, 610 PCF2127_BIT_WD_CTL_CD1 | 611 PCF2127_BIT_WD_CTL_CD0 | 612 PCF2127_BIT_WD_CTL_TF1); 613 if (ret) { 614 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 615 return ret; 616 } 617 618 /* Test if watchdog timer is started by bootloader */ 619 ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout); 620 if (ret) 621 return ret; 622 623 if (wdd_timeout) 624 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 625 626 #ifdef CONFIG_WATCHDOG 627 ret = devm_watchdog_register_device(dev, &pcf2127->wdd); 628 if (ret) 629 return ret; 630 #endif /* CONFIG_WATCHDOG */ 631 632 /* 633 * Disable battery low/switch-over timestamp and interrupts. 634 * Clear battery interrupt flags which can block new trigger events. 635 * Note: This is the default chip behaviour but added to ensure 636 * correct tamper timestamp and interrupt function. 637 */ 638 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 639 PCF2127_BIT_CTRL3_BTSE | 640 PCF2127_BIT_CTRL3_BIE | 641 PCF2127_BIT_CTRL3_BLIE, 0); 642 if (ret) { 643 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 644 __func__); 645 return ret; 646 } 647 648 /* 649 * Enable timestamp function and store timestamp of first trigger 650 * event until TSF1 and TFS2 interrupt flags are cleared. 651 */ 652 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL, 653 PCF2127_BIT_TS_CTRL_TSOFF | 654 PCF2127_BIT_TS_CTRL_TSM, 655 PCF2127_BIT_TS_CTRL_TSM); 656 if (ret) { 657 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n", 658 __func__); 659 return ret; 660 } 661 662 /* 663 * Enable interrupt generation when TSF1 or TSF2 timestamp flags 664 * are set. Interrupt signal is an open-drain output and can be 665 * left floating if unused. 666 */ 667 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 668 PCF2127_BIT_CTRL2_TSIE, 669 PCF2127_BIT_CTRL2_TSIE); 670 if (ret) { 671 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n", 672 __func__); 673 return ret; 674 } 675 676 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group); 677 if (ret) { 678 dev_err(dev, "%s: tamper sysfs registering failed\n", 679 __func__); 680 return ret; 681 } 682 683 return rtc_register_device(pcf2127->rtc); 684 } 685 686 #ifdef CONFIG_OF 687 static const struct of_device_id pcf2127_of_match[] = { 688 { .compatible = "nxp,pcf2127" }, 689 { .compatible = "nxp,pcf2129" }, 690 { .compatible = "nxp,pca2129" }, 691 {} 692 }; 693 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 694 #endif 695 696 #if IS_ENABLED(CONFIG_I2C) 697 698 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 699 { 700 struct device *dev = context; 701 struct i2c_client *client = to_i2c_client(dev); 702 int ret; 703 704 ret = i2c_master_send(client, data, count); 705 if (ret != count) 706 return ret < 0 ? ret : -EIO; 707 708 return 0; 709 } 710 711 static int pcf2127_i2c_gather_write(void *context, 712 const void *reg, size_t reg_size, 713 const void *val, size_t val_size) 714 { 715 struct device *dev = context; 716 struct i2c_client *client = to_i2c_client(dev); 717 int ret; 718 void *buf; 719 720 if (WARN_ON(reg_size != 1)) 721 return -EINVAL; 722 723 buf = kmalloc(val_size + 1, GFP_KERNEL); 724 if (!buf) 725 return -ENOMEM; 726 727 memcpy(buf, reg, 1); 728 memcpy(buf + 1, val, val_size); 729 730 ret = i2c_master_send(client, buf, val_size + 1); 731 732 kfree(buf); 733 734 if (ret != val_size + 1) 735 return ret < 0 ? ret : -EIO; 736 737 return 0; 738 } 739 740 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 741 void *val, size_t val_size) 742 { 743 struct device *dev = context; 744 struct i2c_client *client = to_i2c_client(dev); 745 int ret; 746 747 if (WARN_ON(reg_size != 1)) 748 return -EINVAL; 749 750 ret = i2c_master_send(client, reg, 1); 751 if (ret != 1) 752 return ret < 0 ? ret : -EIO; 753 754 ret = i2c_master_recv(client, val, val_size); 755 if (ret != val_size) 756 return ret < 0 ? ret : -EIO; 757 758 return 0; 759 } 760 761 /* 762 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 763 * is that the STOP condition is required between set register address and 764 * read register data when reading from registers. 765 */ 766 static const struct regmap_bus pcf2127_i2c_regmap = { 767 .write = pcf2127_i2c_write, 768 .gather_write = pcf2127_i2c_gather_write, 769 .read = pcf2127_i2c_read, 770 }; 771 772 static struct i2c_driver pcf2127_i2c_driver; 773 774 static int pcf2127_i2c_probe(struct i2c_client *client, 775 const struct i2c_device_id *id) 776 { 777 struct regmap *regmap; 778 static const struct regmap_config config = { 779 .reg_bits = 8, 780 .val_bits = 8, 781 .max_register = 0x1d, 782 }; 783 784 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 785 return -ENODEV; 786 787 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 788 &client->dev, &config); 789 if (IS_ERR(regmap)) { 790 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 791 __func__, PTR_ERR(regmap)); 792 return PTR_ERR(regmap); 793 } 794 795 return pcf2127_probe(&client->dev, regmap, client->irq, 796 pcf2127_i2c_driver.driver.name, id->driver_data); 797 } 798 799 static const struct i2c_device_id pcf2127_i2c_id[] = { 800 { "pcf2127", 1 }, 801 { "pcf2129", 0 }, 802 { "pca2129", 0 }, 803 { } 804 }; 805 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 806 807 static struct i2c_driver pcf2127_i2c_driver = { 808 .driver = { 809 .name = "rtc-pcf2127-i2c", 810 .of_match_table = of_match_ptr(pcf2127_of_match), 811 }, 812 .probe = pcf2127_i2c_probe, 813 .id_table = pcf2127_i2c_id, 814 }; 815 816 static int pcf2127_i2c_register_driver(void) 817 { 818 return i2c_add_driver(&pcf2127_i2c_driver); 819 } 820 821 static void pcf2127_i2c_unregister_driver(void) 822 { 823 i2c_del_driver(&pcf2127_i2c_driver); 824 } 825 826 #else 827 828 static int pcf2127_i2c_register_driver(void) 829 { 830 return 0; 831 } 832 833 static void pcf2127_i2c_unregister_driver(void) 834 { 835 } 836 837 #endif 838 839 #if IS_ENABLED(CONFIG_SPI_MASTER) 840 841 static struct spi_driver pcf2127_spi_driver; 842 843 static int pcf2127_spi_probe(struct spi_device *spi) 844 { 845 static const struct regmap_config config = { 846 .reg_bits = 8, 847 .val_bits = 8, 848 .read_flag_mask = 0xa0, 849 .write_flag_mask = 0x20, 850 .max_register = 0x1d, 851 }; 852 struct regmap *regmap; 853 854 regmap = devm_regmap_init_spi(spi, &config); 855 if (IS_ERR(regmap)) { 856 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 857 __func__, PTR_ERR(regmap)); 858 return PTR_ERR(regmap); 859 } 860 861 return pcf2127_probe(&spi->dev, regmap, spi->irq, 862 pcf2127_spi_driver.driver.name, 863 spi_get_device_id(spi)->driver_data); 864 } 865 866 static const struct spi_device_id pcf2127_spi_id[] = { 867 { "pcf2127", 1 }, 868 { "pcf2129", 0 }, 869 { "pca2129", 0 }, 870 { } 871 }; 872 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 873 874 static struct spi_driver pcf2127_spi_driver = { 875 .driver = { 876 .name = "rtc-pcf2127-spi", 877 .of_match_table = of_match_ptr(pcf2127_of_match), 878 }, 879 .probe = pcf2127_spi_probe, 880 .id_table = pcf2127_spi_id, 881 }; 882 883 static int pcf2127_spi_register_driver(void) 884 { 885 return spi_register_driver(&pcf2127_spi_driver); 886 } 887 888 static void pcf2127_spi_unregister_driver(void) 889 { 890 spi_unregister_driver(&pcf2127_spi_driver); 891 } 892 893 #else 894 895 static int pcf2127_spi_register_driver(void) 896 { 897 return 0; 898 } 899 900 static void pcf2127_spi_unregister_driver(void) 901 { 902 } 903 904 #endif 905 906 static int __init pcf2127_init(void) 907 { 908 int ret; 909 910 ret = pcf2127_i2c_register_driver(); 911 if (ret) { 912 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 913 return ret; 914 } 915 916 ret = pcf2127_spi_register_driver(); 917 if (ret) { 918 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 919 pcf2127_i2c_unregister_driver(); 920 } 921 922 return ret; 923 } 924 module_init(pcf2127_init) 925 926 static void __exit pcf2127_exit(void) 927 { 928 pcf2127_spi_unregister_driver(); 929 pcf2127_i2c_unregister_driver(); 930 } 931 module_exit(pcf2127_exit) 932 933 MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>"); 934 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 935 MODULE_LICENSE("GPL v2"); 936