1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com> 10 * 11 * based on the other drivers in this same directory. 12 * 13 * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 14 */ 15 16 #include <linux/i2c.h> 17 #include <linux/spi/spi.h> 18 #include <linux/bcd.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_device.h> 25 #include <linux/regmap.h> 26 #include <linux/watchdog.h> 27 28 /* Control register 1 */ 29 #define PCF2127_REG_CTRL1 0x00 30 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 31 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 32 /* Control register 2 */ 33 #define PCF2127_REG_CTRL2 0x01 34 #define PCF2127_BIT_CTRL2_AIE BIT(1) 35 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 36 #define PCF2127_BIT_CTRL2_AF BIT(4) 37 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 38 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 39 /* Control register 3 */ 40 #define PCF2127_REG_CTRL3 0x02 41 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 42 #define PCF2127_BIT_CTRL3_BIE BIT(1) 43 #define PCF2127_BIT_CTRL3_BLF BIT(2) 44 #define PCF2127_BIT_CTRL3_BF BIT(3) 45 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 46 /* Time and date registers */ 47 #define PCF2127_REG_TIME_BASE 0x03 48 #define PCF2127_BIT_SC_OSF BIT(7) 49 /* Alarm registers */ 50 #define PCF2127_REG_ALARM_BASE 0x0A 51 #define PCF2127_BIT_ALARM_AE BIT(7) 52 /* CLKOUT control register */ 53 #define PCF2127_REG_CLKOUT 0x0f 54 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 55 /* Watchdog registers */ 56 #define PCF2127_REG_WD_CTL 0x10 57 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 58 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 59 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 60 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 61 #define PCF2127_REG_WD_VAL 0x11 62 /* Tamper timestamp registers */ 63 #define PCF2127_REG_TS_CTRL 0x12 64 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 65 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 66 /* 67 * RAM registers 68 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 69 * battery backed and can survive a power outage. 70 * PCF2129 doesn't have this feature. 71 */ 72 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 73 #define PCF2127_REG_RAM_WRT_CMD 0x1C 74 #define PCF2127_REG_RAM_RD_CMD 0x1D 75 76 /* Watchdog timer value constants */ 77 #define PCF2127_WD_VAL_STOP 0 78 #define PCF2127_WD_VAL_MIN 2 79 #define PCF2127_WD_VAL_MAX 255 80 #define PCF2127_WD_VAL_DEFAULT 60 81 82 /* Mask for currently enabled interrupts */ 83 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 84 #define PCF2127_CTRL2_IRQ_MASK ( \ 85 PCF2127_BIT_CTRL2_AF | \ 86 PCF2127_BIT_CTRL2_WDTF | \ 87 PCF2127_BIT_CTRL2_TSF2) 88 89 enum pcf21xx_type { 90 PCF2127, 91 PCF2129, 92 PCF21XX_LAST_ID 93 }; 94 95 struct pcf21xx_config { 96 int type; /* IC variant */ 97 int max_register; 98 unsigned int has_nvmem:1; 99 unsigned int has_bit_wd_ctl_cd0:1; 100 u8 reg_time_base; /* Time/date base register. */ 101 u8 regs_alarm_base; /* Alarm function base registers. */ 102 }; 103 104 struct pcf2127 { 105 struct rtc_device *rtc; 106 struct watchdog_device wdd; 107 struct regmap *regmap; 108 const struct pcf21xx_config *cfg; 109 time64_t ts; 110 bool ts_valid; 111 bool irq_enabled; 112 }; 113 114 /* 115 * In the routines that deal directly with the pcf2127 hardware, we use 116 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 117 */ 118 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 119 { 120 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 121 unsigned char buf[7]; 122 int ret; 123 124 /* 125 * Avoid reading CTRL2 register as it causes WD_VAL register 126 * value to reset to 0 which means watchdog is stopped. 127 */ 128 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base, 129 buf, sizeof(buf)); 130 if (ret) { 131 dev_err(dev, "%s: read error\n", __func__); 132 return ret; 133 } 134 135 /* Clock integrity is not guaranteed when OSF flag is set. */ 136 if (buf[0] & PCF2127_BIT_SC_OSF) { 137 /* 138 * no need clear the flag here, 139 * it will be cleared once the new date is saved 140 */ 141 dev_warn(dev, 142 "oscillator stop detected, date/time is not reliable\n"); 143 return -EINVAL; 144 } 145 146 dev_dbg(dev, 147 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 148 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 149 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 150 151 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 152 tm->tm_min = bcd2bin(buf[1] & 0x7F); 153 tm->tm_hour = bcd2bin(buf[2] & 0x3F); 154 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 155 tm->tm_wday = buf[4] & 0x07; 156 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 157 tm->tm_year = bcd2bin(buf[6]); 158 tm->tm_year += 100; 159 160 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 161 "mday=%d, mon=%d, year=%d, wday=%d\n", 162 __func__, 163 tm->tm_sec, tm->tm_min, tm->tm_hour, 164 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 165 166 return 0; 167 } 168 169 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 170 { 171 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 172 unsigned char buf[7]; 173 int i = 0, err; 174 175 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 176 "mday=%d, mon=%d, year=%d, wday=%d\n", 177 __func__, 178 tm->tm_sec, tm->tm_min, tm->tm_hour, 179 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 180 181 /* hours, minutes and seconds */ 182 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 183 buf[i++] = bin2bcd(tm->tm_min); 184 buf[i++] = bin2bcd(tm->tm_hour); 185 buf[i++] = bin2bcd(tm->tm_mday); 186 buf[i++] = tm->tm_wday & 0x07; 187 188 /* month, 1 - 12 */ 189 buf[i++] = bin2bcd(tm->tm_mon + 1); 190 191 /* year */ 192 buf[i++] = bin2bcd(tm->tm_year - 100); 193 194 /* write register's data */ 195 err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); 196 if (err) { 197 dev_dbg(dev, "%s: err=%d", __func__, err); 198 return err; 199 } 200 201 return 0; 202 } 203 204 static int pcf2127_rtc_ioctl(struct device *dev, 205 unsigned int cmd, unsigned long arg) 206 { 207 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 208 int val, touser = 0; 209 int ret; 210 211 switch (cmd) { 212 case RTC_VL_READ: 213 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 214 if (ret) 215 return ret; 216 217 if (val & PCF2127_BIT_CTRL3_BLF) 218 touser |= RTC_VL_BACKUP_LOW; 219 220 if (val & PCF2127_BIT_CTRL3_BF) 221 touser |= RTC_VL_BACKUP_SWITCH; 222 223 return put_user(touser, (unsigned int __user *)arg); 224 225 case RTC_VL_CLR: 226 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 227 PCF2127_BIT_CTRL3_BF, 0); 228 229 default: 230 return -ENOIOCTLCMD; 231 } 232 } 233 234 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 235 void *val, size_t bytes) 236 { 237 struct pcf2127 *pcf2127 = priv; 238 int ret; 239 unsigned char offsetbuf[] = { offset >> 8, offset }; 240 241 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 242 offsetbuf, 2); 243 if (ret) 244 return ret; 245 246 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 247 val, bytes); 248 } 249 250 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 251 void *val, size_t bytes) 252 { 253 struct pcf2127 *pcf2127 = priv; 254 int ret; 255 unsigned char offsetbuf[] = { offset >> 8, offset }; 256 257 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 258 offsetbuf, 2); 259 if (ret) 260 return ret; 261 262 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 263 val, bytes); 264 } 265 266 /* watchdog driver */ 267 268 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 269 { 270 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 271 272 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout); 273 } 274 275 /* 276 * Restart watchdog timer if feature is active. 277 * 278 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 279 * since register also contain control/status flags for other features. 280 * Always call this function after reading CTRL2 register. 281 */ 282 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 283 { 284 int ret = 0; 285 286 if (watchdog_active(wdd)) { 287 ret = pcf2127_wdt_ping(wdd); 288 if (ret) 289 dev_err(wdd->parent, 290 "%s: watchdog restart failed, ret=%d\n", 291 __func__, ret); 292 } 293 294 return ret; 295 } 296 297 static int pcf2127_wdt_start(struct watchdog_device *wdd) 298 { 299 return pcf2127_wdt_ping(wdd); 300 } 301 302 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 303 { 304 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 305 306 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, 307 PCF2127_WD_VAL_STOP); 308 } 309 310 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 311 unsigned int new_timeout) 312 { 313 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 314 new_timeout, wdd->timeout); 315 316 wdd->timeout = new_timeout; 317 318 return pcf2127_wdt_active_ping(wdd); 319 } 320 321 static const struct watchdog_info pcf2127_wdt_info = { 322 .identity = "NXP PCF2127/PCF2129 Watchdog", 323 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 324 }; 325 326 static const struct watchdog_ops pcf2127_watchdog_ops = { 327 .owner = THIS_MODULE, 328 .start = pcf2127_wdt_start, 329 .stop = pcf2127_wdt_stop, 330 .ping = pcf2127_wdt_ping, 331 .set_timeout = pcf2127_wdt_set_timeout, 332 }; 333 334 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 335 { 336 u32 wdd_timeout; 337 int ret; 338 339 if (!IS_ENABLED(CONFIG_WATCHDOG) || 340 !device_property_read_bool(dev, "reset-source")) 341 return 0; 342 343 pcf2127->wdd.parent = dev; 344 pcf2127->wdd.info = &pcf2127_wdt_info; 345 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 346 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 347 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 348 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 349 pcf2127->wdd.min_hw_heartbeat_ms = 500; 350 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 351 352 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 353 354 /* Test if watchdog timer is started by bootloader */ 355 ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout); 356 if (ret) 357 return ret; 358 359 if (wdd_timeout) 360 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 361 362 return devm_watchdog_register_device(dev, &pcf2127->wdd); 363 } 364 365 /* Alarm */ 366 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 367 { 368 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 369 u8 buf[5]; 370 unsigned int ctrl2; 371 int ret; 372 373 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 374 if (ret) 375 return ret; 376 377 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 378 if (ret) 379 return ret; 380 381 ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 382 buf, sizeof(buf)); 383 if (ret) 384 return ret; 385 386 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 387 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 388 389 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 390 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 391 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 392 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 393 394 return 0; 395 } 396 397 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 398 { 399 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 400 int ret; 401 402 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 403 PCF2127_BIT_CTRL2_AIE, 404 enable ? PCF2127_BIT_CTRL2_AIE : 0); 405 if (ret) 406 return ret; 407 408 return pcf2127_wdt_active_ping(&pcf2127->wdd); 409 } 410 411 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 412 { 413 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 414 uint8_t buf[5]; 415 int ret; 416 417 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 418 PCF2127_BIT_CTRL2_AF, 0); 419 if (ret) 420 return ret; 421 422 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 423 if (ret) 424 return ret; 425 426 buf[0] = bin2bcd(alrm->time.tm_sec); 427 buf[1] = bin2bcd(alrm->time.tm_min); 428 buf[2] = bin2bcd(alrm->time.tm_hour); 429 buf[3] = bin2bcd(alrm->time.tm_mday); 430 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 431 432 ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 433 buf, sizeof(buf)); 434 if (ret) 435 return ret; 436 437 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 438 } 439 440 /* 441 * This function reads ctrl2 register, caller is responsible for calling 442 * pcf2127_wdt_active_ping() 443 */ 444 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts) 445 { 446 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 447 struct rtc_time tm; 448 int ret; 449 unsigned char data[7]; 450 451 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_TS_CTRL, data, 452 sizeof(data)); 453 if (ret) { 454 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 455 return ret; 456 } 457 458 dev_dbg(dev, 459 "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 460 __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 461 462 tm.tm_sec = bcd2bin(data[1] & 0x7F); 463 tm.tm_min = bcd2bin(data[2] & 0x7F); 464 tm.tm_hour = bcd2bin(data[3] & 0x3F); 465 tm.tm_mday = bcd2bin(data[4] & 0x3F); 466 /* TS_MO register (month) value range: 1-12 */ 467 tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 468 tm.tm_year = bcd2bin(data[6]); 469 if (tm.tm_year < 70) 470 tm.tm_year += 100; /* assume we are in 1970...2069 */ 471 472 ret = rtc_valid_tm(&tm); 473 if (ret) { 474 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 475 return ret; 476 } 477 478 *ts = rtc_tm_to_time64(&tm); 479 return 0; 480 }; 481 482 static void pcf2127_rtc_ts_snapshot(struct device *dev) 483 { 484 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 485 int ret; 486 487 /* Let userspace read the first timestamp */ 488 if (pcf2127->ts_valid) 489 return; 490 491 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts); 492 if (!ret) 493 pcf2127->ts_valid = true; 494 } 495 496 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 497 { 498 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 499 unsigned int ctrl1, ctrl2; 500 int ret = 0; 501 502 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 503 if (ret) 504 return IRQ_NONE; 505 506 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 507 if (ret) 508 return IRQ_NONE; 509 510 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 511 return IRQ_NONE; 512 513 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 514 pcf2127_rtc_ts_snapshot(dev); 515 516 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 517 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 518 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 519 520 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 521 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 522 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 523 524 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 525 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 526 527 pcf2127_wdt_active_ping(&pcf2127->wdd); 528 529 return IRQ_HANDLED; 530 } 531 532 static const struct rtc_class_ops pcf2127_rtc_ops = { 533 .ioctl = pcf2127_rtc_ioctl, 534 .read_time = pcf2127_rtc_read_time, 535 .set_time = pcf2127_rtc_set_time, 536 .read_alarm = pcf2127_rtc_read_alarm, 537 .set_alarm = pcf2127_rtc_set_alarm, 538 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 539 }; 540 541 /* sysfs interface */ 542 543 static ssize_t timestamp0_store(struct device *dev, 544 struct device_attribute *attr, 545 const char *buf, size_t count) 546 { 547 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 548 int ret; 549 550 if (pcf2127->irq_enabled) { 551 pcf2127->ts_valid = false; 552 } else { 553 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 554 PCF2127_BIT_CTRL1_TSF1, 0); 555 if (ret) { 556 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret); 557 return ret; 558 } 559 560 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 561 PCF2127_BIT_CTRL2_TSF2, 0); 562 if (ret) { 563 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret); 564 return ret; 565 } 566 567 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 568 if (ret) 569 return ret; 570 } 571 572 return count; 573 }; 574 575 static ssize_t timestamp0_show(struct device *dev, 576 struct device_attribute *attr, char *buf) 577 { 578 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 579 unsigned int ctrl1, ctrl2; 580 int ret; 581 time64_t ts; 582 583 if (pcf2127->irq_enabled) { 584 if (!pcf2127->ts_valid) 585 return 0; 586 ts = pcf2127->ts; 587 } else { 588 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 589 if (ret) 590 return 0; 591 592 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 593 if (ret) 594 return 0; 595 596 if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) && 597 !(ctrl2 & PCF2127_BIT_CTRL2_TSF2)) 598 return 0; 599 600 ret = pcf2127_rtc_ts_read(dev->parent, &ts); 601 if (ret) 602 return 0; 603 604 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 605 if (ret) 606 return ret; 607 } 608 return sprintf(buf, "%llu\n", (unsigned long long)ts); 609 }; 610 611 static DEVICE_ATTR_RW(timestamp0); 612 613 static struct attribute *pcf2127_attrs[] = { 614 &dev_attr_timestamp0.attr, 615 NULL 616 }; 617 618 static const struct attribute_group pcf2127_attr_group = { 619 .attrs = pcf2127_attrs, 620 }; 621 622 static struct pcf21xx_config pcf21xx_cfg[] = { 623 [PCF2127] = { 624 .type = PCF2127, 625 .max_register = 0x1d, 626 .has_nvmem = 1, 627 .has_bit_wd_ctl_cd0 = 1, 628 .reg_time_base = PCF2127_REG_TIME_BASE, 629 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 630 }, 631 [PCF2129] = { 632 .type = PCF2129, 633 .max_register = 0x19, 634 .has_nvmem = 0, 635 .has_bit_wd_ctl_cd0 = 0, 636 .reg_time_base = PCF2127_REG_TIME_BASE, 637 .regs_alarm_base = PCF2127_REG_ALARM_BASE, 638 }, 639 }; 640 641 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 642 int alarm_irq, const char *name, const struct pcf21xx_config *config) 643 { 644 struct pcf2127 *pcf2127; 645 int ret = 0; 646 unsigned int val; 647 648 dev_dbg(dev, "%s\n", __func__); 649 650 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 651 if (!pcf2127) 652 return -ENOMEM; 653 654 pcf2127->regmap = regmap; 655 pcf2127->cfg = config; 656 657 dev_set_drvdata(dev, pcf2127); 658 659 pcf2127->rtc = devm_rtc_allocate_device(dev); 660 if (IS_ERR(pcf2127->rtc)) 661 return PTR_ERR(pcf2127->rtc); 662 663 pcf2127->rtc->ops = &pcf2127_rtc_ops; 664 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 665 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 666 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 667 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 668 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 669 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 670 671 if (alarm_irq > 0) { 672 unsigned long flags; 673 674 /* 675 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 676 * obtained from device tree. 677 */ 678 if (dev_fwnode(dev)) 679 flags = 0; 680 else 681 flags = IRQF_TRIGGER_LOW; 682 683 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 684 pcf2127_rtc_irq, 685 flags | IRQF_ONESHOT, 686 dev_name(dev), dev); 687 if (ret) { 688 dev_err(dev, "failed to request alarm irq\n"); 689 return ret; 690 } 691 pcf2127->irq_enabled = true; 692 } 693 694 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 695 device_init_wakeup(dev, true); 696 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 697 } 698 699 if (pcf2127->cfg->has_nvmem) { 700 struct nvmem_config nvmem_cfg = { 701 .priv = pcf2127, 702 .reg_read = pcf2127_nvmem_read, 703 .reg_write = pcf2127_nvmem_write, 704 .size = 512, 705 }; 706 707 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 708 } 709 710 /* 711 * The "Power-On Reset Override" facility prevents the RTC to do a reset 712 * after power on. For normal operation the PORO must be disabled. 713 */ 714 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 715 PCF2127_BIT_CTRL1_POR_OVRD); 716 717 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val); 718 if (ret < 0) 719 return ret; 720 721 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 722 ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT, 723 PCF2127_BIT_CLKOUT_OTPR); 724 if (ret < 0) 725 return ret; 726 727 msleep(100); 728 } 729 730 /* 731 * Watchdog timer enabled and reset pin /RST activated when timed out. 732 * Select 1Hz clock source for watchdog timer. 733 * Note: Countdown timer disabled and not available. 734 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 735 * of register watchdg_tim_ctl. The bit[6] is labeled 736 * as T. Bits labeled as T must always be written with 737 * logic 0. 738 */ 739 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL, 740 PCF2127_BIT_WD_CTL_CD1 | 741 PCF2127_BIT_WD_CTL_CD0 | 742 PCF2127_BIT_WD_CTL_TF1 | 743 PCF2127_BIT_WD_CTL_TF0, 744 PCF2127_BIT_WD_CTL_CD1 | 745 (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 746 PCF2127_BIT_WD_CTL_TF1); 747 if (ret) { 748 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 749 return ret; 750 } 751 752 pcf2127_watchdog_init(dev, pcf2127); 753 754 /* 755 * Disable battery low/switch-over timestamp and interrupts. 756 * Clear battery interrupt flags which can block new trigger events. 757 * Note: This is the default chip behaviour but added to ensure 758 * correct tamper timestamp and interrupt function. 759 */ 760 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 761 PCF2127_BIT_CTRL3_BTSE | 762 PCF2127_BIT_CTRL3_BIE | 763 PCF2127_BIT_CTRL3_BLIE, 0); 764 if (ret) { 765 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 766 __func__); 767 return ret; 768 } 769 770 /* 771 * Enable timestamp function and store timestamp of first trigger 772 * event until TSF1 and TSF2 interrupt flags are cleared. 773 */ 774 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL, 775 PCF2127_BIT_TS_CTRL_TSOFF | 776 PCF2127_BIT_TS_CTRL_TSM, 777 PCF2127_BIT_TS_CTRL_TSM); 778 if (ret) { 779 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n", 780 __func__); 781 return ret; 782 } 783 784 /* 785 * Enable interrupt generation when TSF1 or TSF2 timestamp flags 786 * are set. Interrupt signal is an open-drain output and can be 787 * left floating if unused. 788 */ 789 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 790 PCF2127_BIT_CTRL2_TSIE, 791 PCF2127_BIT_CTRL2_TSIE); 792 if (ret) { 793 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n", 794 __func__); 795 return ret; 796 } 797 798 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group); 799 if (ret) { 800 dev_err(dev, "%s: tamper sysfs registering failed\n", 801 __func__); 802 return ret; 803 } 804 805 return devm_rtc_register_device(pcf2127->rtc); 806 } 807 808 #ifdef CONFIG_OF 809 static const struct of_device_id pcf2127_of_match[] = { 810 { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 811 { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 812 { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 813 {} 814 }; 815 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 816 #endif 817 818 #if IS_ENABLED(CONFIG_I2C) 819 820 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 821 { 822 struct device *dev = context; 823 struct i2c_client *client = to_i2c_client(dev); 824 int ret; 825 826 ret = i2c_master_send(client, data, count); 827 if (ret != count) 828 return ret < 0 ? ret : -EIO; 829 830 return 0; 831 } 832 833 static int pcf2127_i2c_gather_write(void *context, 834 const void *reg, size_t reg_size, 835 const void *val, size_t val_size) 836 { 837 struct device *dev = context; 838 struct i2c_client *client = to_i2c_client(dev); 839 int ret; 840 void *buf; 841 842 if (WARN_ON(reg_size != 1)) 843 return -EINVAL; 844 845 buf = kmalloc(val_size + 1, GFP_KERNEL); 846 if (!buf) 847 return -ENOMEM; 848 849 memcpy(buf, reg, 1); 850 memcpy(buf + 1, val, val_size); 851 852 ret = i2c_master_send(client, buf, val_size + 1); 853 854 kfree(buf); 855 856 if (ret != val_size + 1) 857 return ret < 0 ? ret : -EIO; 858 859 return 0; 860 } 861 862 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 863 void *val, size_t val_size) 864 { 865 struct device *dev = context; 866 struct i2c_client *client = to_i2c_client(dev); 867 int ret; 868 869 if (WARN_ON(reg_size != 1)) 870 return -EINVAL; 871 872 ret = i2c_master_send(client, reg, 1); 873 if (ret != 1) 874 return ret < 0 ? ret : -EIO; 875 876 ret = i2c_master_recv(client, val, val_size); 877 if (ret != val_size) 878 return ret < 0 ? ret : -EIO; 879 880 return 0; 881 } 882 883 /* 884 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 885 * is that the STOP condition is required between set register address and 886 * read register data when reading from registers. 887 */ 888 static const struct regmap_bus pcf2127_i2c_regmap = { 889 .write = pcf2127_i2c_write, 890 .gather_write = pcf2127_i2c_gather_write, 891 .read = pcf2127_i2c_read, 892 }; 893 894 static struct i2c_driver pcf2127_i2c_driver; 895 896 static const struct i2c_device_id pcf2127_i2c_id[] = { 897 { "pcf2127", PCF2127 }, 898 { "pcf2129", PCF2129 }, 899 { "pca2129", PCF2129 }, 900 { } 901 }; 902 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 903 904 static int pcf2127_i2c_probe(struct i2c_client *client) 905 { 906 struct regmap *regmap; 907 static struct regmap_config config = { 908 .reg_bits = 8, 909 .val_bits = 8, 910 }; 911 const struct pcf21xx_config *variant; 912 913 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 914 return -ENODEV; 915 916 if (client->dev.of_node) { 917 variant = of_device_get_match_data(&client->dev); 918 if (!variant) 919 return -ENODEV; 920 } else { 921 enum pcf21xx_type type = 922 i2c_match_id(pcf2127_i2c_id, client)->driver_data; 923 924 if (type >= PCF21XX_LAST_ID) 925 return -ENODEV; 926 variant = &pcf21xx_cfg[type]; 927 } 928 929 config.max_register = variant->max_register, 930 931 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 932 &client->dev, &config); 933 if (IS_ERR(regmap)) { 934 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 935 __func__, PTR_ERR(regmap)); 936 return PTR_ERR(regmap); 937 } 938 939 return pcf2127_probe(&client->dev, regmap, client->irq, 940 pcf2127_i2c_driver.driver.name, variant); 941 } 942 943 static struct i2c_driver pcf2127_i2c_driver = { 944 .driver = { 945 .name = "rtc-pcf2127-i2c", 946 .of_match_table = of_match_ptr(pcf2127_of_match), 947 }, 948 .probe = pcf2127_i2c_probe, 949 .id_table = pcf2127_i2c_id, 950 }; 951 952 static int pcf2127_i2c_register_driver(void) 953 { 954 return i2c_add_driver(&pcf2127_i2c_driver); 955 } 956 957 static void pcf2127_i2c_unregister_driver(void) 958 { 959 i2c_del_driver(&pcf2127_i2c_driver); 960 } 961 962 #else 963 964 static int pcf2127_i2c_register_driver(void) 965 { 966 return 0; 967 } 968 969 static void pcf2127_i2c_unregister_driver(void) 970 { 971 } 972 973 #endif 974 975 #if IS_ENABLED(CONFIG_SPI_MASTER) 976 977 static struct spi_driver pcf2127_spi_driver; 978 static const struct spi_device_id pcf2127_spi_id[]; 979 980 static int pcf2127_spi_probe(struct spi_device *spi) 981 { 982 static struct regmap_config config = { 983 .reg_bits = 8, 984 .val_bits = 8, 985 .read_flag_mask = 0xa0, 986 .write_flag_mask = 0x20, 987 }; 988 struct regmap *regmap; 989 const struct pcf21xx_config *variant; 990 991 if (spi->dev.of_node) { 992 variant = of_device_get_match_data(&spi->dev); 993 if (!variant) 994 return -ENODEV; 995 } else { 996 enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 997 998 if (type >= PCF21XX_LAST_ID) 999 return -ENODEV; 1000 variant = &pcf21xx_cfg[type]; 1001 } 1002 1003 config.max_register = variant->max_register, 1004 1005 regmap = devm_regmap_init_spi(spi, &config); 1006 if (IS_ERR(regmap)) { 1007 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 1008 __func__, PTR_ERR(regmap)); 1009 return PTR_ERR(regmap); 1010 } 1011 1012 return pcf2127_probe(&spi->dev, regmap, spi->irq, 1013 pcf2127_spi_driver.driver.name, 1014 variant); 1015 } 1016 1017 static const struct spi_device_id pcf2127_spi_id[] = { 1018 { "pcf2127", PCF2127 }, 1019 { "pcf2129", PCF2129 }, 1020 { "pca2129", PCF2129 }, 1021 { } 1022 }; 1023 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 1024 1025 static struct spi_driver pcf2127_spi_driver = { 1026 .driver = { 1027 .name = "rtc-pcf2127-spi", 1028 .of_match_table = of_match_ptr(pcf2127_of_match), 1029 }, 1030 .probe = pcf2127_spi_probe, 1031 .id_table = pcf2127_spi_id, 1032 }; 1033 1034 static int pcf2127_spi_register_driver(void) 1035 { 1036 return spi_register_driver(&pcf2127_spi_driver); 1037 } 1038 1039 static void pcf2127_spi_unregister_driver(void) 1040 { 1041 spi_unregister_driver(&pcf2127_spi_driver); 1042 } 1043 1044 #else 1045 1046 static int pcf2127_spi_register_driver(void) 1047 { 1048 return 0; 1049 } 1050 1051 static void pcf2127_spi_unregister_driver(void) 1052 { 1053 } 1054 1055 #endif 1056 1057 static int __init pcf2127_init(void) 1058 { 1059 int ret; 1060 1061 ret = pcf2127_i2c_register_driver(); 1062 if (ret) { 1063 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1064 return ret; 1065 } 1066 1067 ret = pcf2127_spi_register_driver(); 1068 if (ret) { 1069 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1070 pcf2127_i2c_unregister_driver(); 1071 } 1072 1073 return ret; 1074 } 1075 module_init(pcf2127_init) 1076 1077 static void __exit pcf2127_exit(void) 1078 { 1079 pcf2127_spi_unregister_driver(); 1080 pcf2127_i2c_unregister_driver(); 1081 } 1082 module_exit(pcf2127_exit) 1083 1084 MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>"); 1085 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 1086 MODULE_LICENSE("GPL v2"); 1087