1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * An I2C and SPI driver for the NXP PCF2127/29 RTC 4 * Copyright 2013 Til-Technologies 5 * 6 * Author: Renaud Cerrato <r.cerrato@til-technologies.fr> 7 * 8 * Watchdog and tamper functions 9 * Author: Bruno Thomsen <bruno.thomsen@gmail.com> 10 * 11 * based on the other drivers in this same directory. 12 * 13 * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 14 */ 15 16 #include <linux/i2c.h> 17 #include <linux/spi/spi.h> 18 #include <linux/bcd.h> 19 #include <linux/rtc.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/regmap.h> 25 #include <linux/watchdog.h> 26 27 /* Control register 1 */ 28 #define PCF2127_REG_CTRL1 0x00 29 #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 30 #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 31 /* Control register 2 */ 32 #define PCF2127_REG_CTRL2 0x01 33 #define PCF2127_BIT_CTRL2_AIE BIT(1) 34 #define PCF2127_BIT_CTRL2_TSIE BIT(2) 35 #define PCF2127_BIT_CTRL2_AF BIT(4) 36 #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 37 #define PCF2127_BIT_CTRL2_WDTF BIT(6) 38 /* Control register 3 */ 39 #define PCF2127_REG_CTRL3 0x02 40 #define PCF2127_BIT_CTRL3_BLIE BIT(0) 41 #define PCF2127_BIT_CTRL3_BIE BIT(1) 42 #define PCF2127_BIT_CTRL3_BLF BIT(2) 43 #define PCF2127_BIT_CTRL3_BF BIT(3) 44 #define PCF2127_BIT_CTRL3_BTSE BIT(4) 45 /* Time and date registers */ 46 #define PCF2127_REG_SC 0x03 47 #define PCF2127_BIT_SC_OSF BIT(7) 48 /* Alarm registers */ 49 #define PCF2127_REG_ALARM_SC 0x0A 50 #define PCF2127_REG_ALARM_MN 0x0B 51 #define PCF2127_REG_ALARM_HR 0x0C 52 #define PCF2127_REG_ALARM_DM 0x0D 53 #define PCF2127_REG_ALARM_DW 0x0E 54 #define PCF2127_BIT_ALARM_AE BIT(7) 55 /* CLKOUT control register */ 56 #define PCF2127_REG_CLKOUT 0x0f 57 #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 58 /* Watchdog registers */ 59 #define PCF2127_REG_WD_CTL 0x10 60 #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 61 #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 62 #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 63 #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 64 #define PCF2127_REG_WD_VAL 0x11 65 /* Tamper timestamp registers */ 66 #define PCF2127_REG_TS_CTRL 0x12 67 #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 68 #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 69 #define PCF2127_REG_TS_SC 0x13 70 #define PCF2127_REG_TS_MN 0x14 71 #define PCF2127_REG_TS_HR 0x15 72 #define PCF2127_REG_TS_DM 0x16 73 #define PCF2127_REG_TS_MO 0x17 74 #define PCF2127_REG_TS_YR 0x18 75 /* 76 * RAM registers 77 * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 78 * battery backed and can survive a power outage. 79 * PCF2129 doesn't have this feature. 80 */ 81 #define PCF2127_REG_RAM_ADDR_MSB 0x1A 82 #define PCF2127_REG_RAM_WRT_CMD 0x1C 83 #define PCF2127_REG_RAM_RD_CMD 0x1D 84 85 /* Watchdog timer value constants */ 86 #define PCF2127_WD_VAL_STOP 0 87 #define PCF2127_WD_VAL_MIN 2 88 #define PCF2127_WD_VAL_MAX 255 89 #define PCF2127_WD_VAL_DEFAULT 60 90 91 /* Mask for currently enabled interrupts */ 92 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 93 #define PCF2127_CTRL2_IRQ_MASK ( \ 94 PCF2127_BIT_CTRL2_AF | \ 95 PCF2127_BIT_CTRL2_WDTF | \ 96 PCF2127_BIT_CTRL2_TSF2) 97 98 struct pcf2127 { 99 struct rtc_device *rtc; 100 struct watchdog_device wdd; 101 struct regmap *regmap; 102 time64_t ts; 103 bool ts_valid; 104 bool irq_enabled; 105 }; 106 107 /* 108 * In the routines that deal directly with the pcf2127 hardware, we use 109 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 110 */ 111 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 112 { 113 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 114 unsigned char buf[7]; 115 int ret; 116 117 /* 118 * Avoid reading CTRL2 register as it causes WD_VAL register 119 * value to reset to 0 which means watchdog is stopped. 120 */ 121 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_SC, buf, 122 sizeof(buf)); 123 if (ret) { 124 dev_err(dev, "%s: read error\n", __func__); 125 return ret; 126 } 127 128 /* Clock integrity is not guaranteed when OSF flag is set. */ 129 if (buf[0] & PCF2127_BIT_SC_OSF) { 130 /* 131 * no need clear the flag here, 132 * it will be cleared once the new date is saved 133 */ 134 dev_warn(dev, 135 "oscillator stop detected, date/time is not reliable\n"); 136 return -EINVAL; 137 } 138 139 dev_dbg(dev, 140 "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 141 "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 142 __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 143 144 tm->tm_sec = bcd2bin(buf[0] & 0x7F); 145 tm->tm_min = bcd2bin(buf[1] & 0x7F); 146 tm->tm_hour = bcd2bin(buf[2] & 0x3F); /* rtc hr 0-23 */ 147 tm->tm_mday = bcd2bin(buf[3] & 0x3F); 148 tm->tm_wday = buf[4] & 0x07; 149 tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; /* rtc mn 1-12 */ 150 tm->tm_year = bcd2bin(buf[6]); 151 tm->tm_year += 100; 152 153 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 154 "mday=%d, mon=%d, year=%d, wday=%d\n", 155 __func__, 156 tm->tm_sec, tm->tm_min, tm->tm_hour, 157 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 158 159 return 0; 160 } 161 162 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 163 { 164 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 165 unsigned char buf[7]; 166 int i = 0, err; 167 168 dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 169 "mday=%d, mon=%d, year=%d, wday=%d\n", 170 __func__, 171 tm->tm_sec, tm->tm_min, tm->tm_hour, 172 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 173 174 /* hours, minutes and seconds */ 175 buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 176 buf[i++] = bin2bcd(tm->tm_min); 177 buf[i++] = bin2bcd(tm->tm_hour); 178 buf[i++] = bin2bcd(tm->tm_mday); 179 buf[i++] = tm->tm_wday & 0x07; 180 181 /* month, 1 - 12 */ 182 buf[i++] = bin2bcd(tm->tm_mon + 1); 183 184 /* year */ 185 buf[i++] = bin2bcd(tm->tm_year - 100); 186 187 /* write register's data */ 188 err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i); 189 if (err) { 190 dev_err(dev, 191 "%s: err=%d", __func__, err); 192 return err; 193 } 194 195 return 0; 196 } 197 198 static int pcf2127_rtc_ioctl(struct device *dev, 199 unsigned int cmd, unsigned long arg) 200 { 201 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 202 int val, touser = 0; 203 int ret; 204 205 switch (cmd) { 206 case RTC_VL_READ: 207 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 208 if (ret) 209 return ret; 210 211 if (val & PCF2127_BIT_CTRL3_BLF) 212 touser |= RTC_VL_BACKUP_LOW; 213 214 if (val & PCF2127_BIT_CTRL3_BF) 215 touser |= RTC_VL_BACKUP_SWITCH; 216 217 return put_user(touser, (unsigned int __user *)arg); 218 219 case RTC_VL_CLR: 220 return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 221 PCF2127_BIT_CTRL3_BF, 0); 222 223 default: 224 return -ENOIOCTLCMD; 225 } 226 } 227 228 static int pcf2127_nvmem_read(void *priv, unsigned int offset, 229 void *val, size_t bytes) 230 { 231 struct pcf2127 *pcf2127 = priv; 232 int ret; 233 unsigned char offsetbuf[] = { offset >> 8, offset }; 234 235 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 236 offsetbuf, 2); 237 if (ret) 238 return ret; 239 240 return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 241 val, bytes); 242 } 243 244 static int pcf2127_nvmem_write(void *priv, unsigned int offset, 245 void *val, size_t bytes) 246 { 247 struct pcf2127 *pcf2127 = priv; 248 int ret; 249 unsigned char offsetbuf[] = { offset >> 8, offset }; 250 251 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 252 offsetbuf, 2); 253 if (ret) 254 return ret; 255 256 return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 257 val, bytes); 258 } 259 260 /* watchdog driver */ 261 262 static int pcf2127_wdt_ping(struct watchdog_device *wdd) 263 { 264 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 265 266 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout); 267 } 268 269 /* 270 * Restart watchdog timer if feature is active. 271 * 272 * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 273 * since register also contain control/status flags for other features. 274 * Always call this function after reading CTRL2 register. 275 */ 276 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 277 { 278 int ret = 0; 279 280 if (watchdog_active(wdd)) { 281 ret = pcf2127_wdt_ping(wdd); 282 if (ret) 283 dev_err(wdd->parent, 284 "%s: watchdog restart failed, ret=%d\n", 285 __func__, ret); 286 } 287 288 return ret; 289 } 290 291 static int pcf2127_wdt_start(struct watchdog_device *wdd) 292 { 293 return pcf2127_wdt_ping(wdd); 294 } 295 296 static int pcf2127_wdt_stop(struct watchdog_device *wdd) 297 { 298 struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 299 300 return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, 301 PCF2127_WD_VAL_STOP); 302 } 303 304 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 305 unsigned int new_timeout) 306 { 307 dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 308 new_timeout, wdd->timeout); 309 310 wdd->timeout = new_timeout; 311 312 return pcf2127_wdt_active_ping(wdd); 313 } 314 315 static const struct watchdog_info pcf2127_wdt_info = { 316 .identity = "NXP PCF2127/PCF2129 Watchdog", 317 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 318 }; 319 320 static const struct watchdog_ops pcf2127_watchdog_ops = { 321 .owner = THIS_MODULE, 322 .start = pcf2127_wdt_start, 323 .stop = pcf2127_wdt_stop, 324 .ping = pcf2127_wdt_ping, 325 .set_timeout = pcf2127_wdt_set_timeout, 326 }; 327 328 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 329 { 330 u32 wdd_timeout; 331 int ret; 332 333 if (!IS_ENABLED(CONFIG_WATCHDOG) || 334 !device_property_read_bool(dev, "reset-source")) 335 return 0; 336 337 pcf2127->wdd.parent = dev; 338 pcf2127->wdd.info = &pcf2127_wdt_info; 339 pcf2127->wdd.ops = &pcf2127_watchdog_ops; 340 pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 341 pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 342 pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 343 pcf2127->wdd.min_hw_heartbeat_ms = 500; 344 pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 345 346 watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 347 348 /* Test if watchdog timer is started by bootloader */ 349 ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout); 350 if (ret) 351 return ret; 352 353 if (wdd_timeout) 354 set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 355 356 return devm_watchdog_register_device(dev, &pcf2127->wdd); 357 } 358 359 /* Alarm */ 360 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 361 { 362 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 363 u8 buf[5]; 364 unsigned int ctrl2; 365 int ret; 366 367 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 368 if (ret) 369 return ret; 370 371 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 372 if (ret) 373 return ret; 374 375 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 376 sizeof(buf)); 377 if (ret) 378 return ret; 379 380 alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 381 alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 382 383 alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 384 alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 385 alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 386 alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 387 388 return 0; 389 } 390 391 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 392 { 393 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 394 int ret; 395 396 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 397 PCF2127_BIT_CTRL2_AIE, 398 enable ? PCF2127_BIT_CTRL2_AIE : 0); 399 if (ret) 400 return ret; 401 402 return pcf2127_wdt_active_ping(&pcf2127->wdd); 403 } 404 405 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 406 { 407 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 408 uint8_t buf[5]; 409 int ret; 410 411 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 412 PCF2127_BIT_CTRL2_AF, 0); 413 if (ret) 414 return ret; 415 416 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 417 if (ret) 418 return ret; 419 420 buf[0] = bin2bcd(alrm->time.tm_sec); 421 buf[1] = bin2bcd(alrm->time.tm_min); 422 buf[2] = bin2bcd(alrm->time.tm_hour); 423 buf[3] = bin2bcd(alrm->time.tm_mday); 424 buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 425 426 ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 427 sizeof(buf)); 428 if (ret) 429 return ret; 430 431 return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 432 } 433 434 /* 435 * This function reads ctrl2 register, caller is responsible for calling 436 * pcf2127_wdt_active_ping() 437 */ 438 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts) 439 { 440 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 441 struct rtc_time tm; 442 int ret; 443 unsigned char data[25]; 444 445 ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL1, data, 446 sizeof(data)); 447 if (ret) { 448 dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 449 return ret; 450 } 451 452 dev_dbg(dev, 453 "%s: raw data is cr1=%02x, cr2=%02x, cr3=%02x, ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 454 __func__, data[PCF2127_REG_CTRL1], data[PCF2127_REG_CTRL2], 455 data[PCF2127_REG_CTRL3], data[PCF2127_REG_TS_SC], 456 data[PCF2127_REG_TS_MN], data[PCF2127_REG_TS_HR], 457 data[PCF2127_REG_TS_DM], data[PCF2127_REG_TS_MO], 458 data[PCF2127_REG_TS_YR]); 459 460 tm.tm_sec = bcd2bin(data[PCF2127_REG_TS_SC] & 0x7F); 461 tm.tm_min = bcd2bin(data[PCF2127_REG_TS_MN] & 0x7F); 462 tm.tm_hour = bcd2bin(data[PCF2127_REG_TS_HR] & 0x3F); 463 tm.tm_mday = bcd2bin(data[PCF2127_REG_TS_DM] & 0x3F); 464 /* TS_MO register (month) value range: 1-12 */ 465 tm.tm_mon = bcd2bin(data[PCF2127_REG_TS_MO] & 0x1F) - 1; 466 tm.tm_year = bcd2bin(data[PCF2127_REG_TS_YR]); 467 if (tm.tm_year < 70) 468 tm.tm_year += 100; /* assume we are in 1970...2069 */ 469 470 ret = rtc_valid_tm(&tm); 471 if (ret) { 472 dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 473 return ret; 474 } 475 476 *ts = rtc_tm_to_time64(&tm); 477 return 0; 478 }; 479 480 static void pcf2127_rtc_ts_snapshot(struct device *dev) 481 { 482 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 483 int ret; 484 485 /* Let userspace read the first timestamp */ 486 if (pcf2127->ts_valid) 487 return; 488 489 ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts); 490 if (!ret) 491 pcf2127->ts_valid = true; 492 } 493 494 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 495 { 496 struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 497 unsigned int ctrl1, ctrl2; 498 int ret = 0; 499 500 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 501 if (ret) 502 return IRQ_NONE; 503 504 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 505 if (ret) 506 return IRQ_NONE; 507 508 if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 509 return IRQ_NONE; 510 511 if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 512 pcf2127_rtc_ts_snapshot(dev); 513 514 if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 515 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 516 ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 517 518 if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 519 regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 520 ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 521 522 if (ctrl2 & PCF2127_BIT_CTRL2_AF) 523 rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 524 525 pcf2127_wdt_active_ping(&pcf2127->wdd); 526 527 return IRQ_HANDLED; 528 } 529 530 static const struct rtc_class_ops pcf2127_rtc_ops = { 531 .ioctl = pcf2127_rtc_ioctl, 532 .read_time = pcf2127_rtc_read_time, 533 .set_time = pcf2127_rtc_set_time, 534 .read_alarm = pcf2127_rtc_read_alarm, 535 .set_alarm = pcf2127_rtc_set_alarm, 536 .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 537 }; 538 539 /* sysfs interface */ 540 541 static ssize_t timestamp0_store(struct device *dev, 542 struct device_attribute *attr, 543 const char *buf, size_t count) 544 { 545 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 546 int ret; 547 548 if (pcf2127->irq_enabled) { 549 pcf2127->ts_valid = false; 550 } else { 551 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 552 PCF2127_BIT_CTRL1_TSF1, 0); 553 if (ret) { 554 dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret); 555 return ret; 556 } 557 558 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 559 PCF2127_BIT_CTRL2_TSF2, 0); 560 if (ret) { 561 dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret); 562 return ret; 563 } 564 565 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 566 if (ret) 567 return ret; 568 } 569 570 return count; 571 }; 572 573 static ssize_t timestamp0_show(struct device *dev, 574 struct device_attribute *attr, char *buf) 575 { 576 struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 577 unsigned int ctrl1, ctrl2; 578 int ret; 579 time64_t ts; 580 581 if (pcf2127->irq_enabled) { 582 if (!pcf2127->ts_valid) 583 return 0; 584 ts = pcf2127->ts; 585 } else { 586 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 587 if (ret) 588 return 0; 589 590 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 591 if (ret) 592 return 0; 593 594 if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) && 595 !(ctrl2 & PCF2127_BIT_CTRL2_TSF2)) 596 return 0; 597 598 ret = pcf2127_rtc_ts_read(dev->parent, &ts); 599 if (ret) 600 return 0; 601 602 ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 603 if (ret) 604 return ret; 605 } 606 return sprintf(buf, "%llu\n", (unsigned long long)ts); 607 }; 608 609 static DEVICE_ATTR_RW(timestamp0); 610 611 static struct attribute *pcf2127_attrs[] = { 612 &dev_attr_timestamp0.attr, 613 NULL 614 }; 615 616 static const struct attribute_group pcf2127_attr_group = { 617 .attrs = pcf2127_attrs, 618 }; 619 620 static int pcf2127_probe(struct device *dev, struct regmap *regmap, 621 int alarm_irq, const char *name, bool is_pcf2127) 622 { 623 struct pcf2127 *pcf2127; 624 int ret = 0; 625 unsigned int val; 626 627 dev_dbg(dev, "%s\n", __func__); 628 629 pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 630 if (!pcf2127) 631 return -ENOMEM; 632 633 pcf2127->regmap = regmap; 634 635 dev_set_drvdata(dev, pcf2127); 636 637 pcf2127->rtc = devm_rtc_allocate_device(dev); 638 if (IS_ERR(pcf2127->rtc)) 639 return PTR_ERR(pcf2127->rtc); 640 641 pcf2127->rtc->ops = &pcf2127_rtc_ops; 642 pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 643 pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 644 pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 645 set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 646 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 647 clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 648 649 if (alarm_irq > 0) { 650 unsigned long flags; 651 652 /* 653 * If flags = 0, devm_request_threaded_irq() will use IRQ flags 654 * obtained from device tree. 655 */ 656 if (dev_fwnode(dev)) 657 flags = 0; 658 else 659 flags = IRQF_TRIGGER_LOW; 660 661 ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 662 pcf2127_rtc_irq, 663 flags | IRQF_ONESHOT, 664 dev_name(dev), dev); 665 if (ret) { 666 dev_err(dev, "failed to request alarm irq\n"); 667 return ret; 668 } 669 pcf2127->irq_enabled = true; 670 } 671 672 if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 673 device_init_wakeup(dev, true); 674 set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 675 } 676 677 if (is_pcf2127) { 678 struct nvmem_config nvmem_cfg = { 679 .priv = pcf2127, 680 .reg_read = pcf2127_nvmem_read, 681 .reg_write = pcf2127_nvmem_write, 682 .size = 512, 683 }; 684 685 ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 686 } 687 688 /* 689 * The "Power-On Reset Override" facility prevents the RTC to do a reset 690 * after power on. For normal operation the PORO must be disabled. 691 */ 692 regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 693 PCF2127_BIT_CTRL1_POR_OVRD); 694 695 ret = regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val); 696 if (ret < 0) 697 return ret; 698 699 if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 700 ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT, 701 PCF2127_BIT_CLKOUT_OTPR); 702 if (ret < 0) 703 return ret; 704 705 msleep(100); 706 } 707 708 /* 709 * Watchdog timer enabled and reset pin /RST activated when timed out. 710 * Select 1Hz clock source for watchdog timer. 711 * Note: Countdown timer disabled and not available. 712 * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 713 * of register watchdg_tim_ctl. The bit[6] is labeled 714 * as T. Bits labeled as T must always be written with 715 * logic 0. 716 */ 717 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL, 718 PCF2127_BIT_WD_CTL_CD1 | 719 PCF2127_BIT_WD_CTL_CD0 | 720 PCF2127_BIT_WD_CTL_TF1 | 721 PCF2127_BIT_WD_CTL_TF0, 722 PCF2127_BIT_WD_CTL_CD1 | 723 (is_pcf2127 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 724 PCF2127_BIT_WD_CTL_TF1); 725 if (ret) { 726 dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 727 return ret; 728 } 729 730 pcf2127_watchdog_init(dev, pcf2127); 731 732 /* 733 * Disable battery low/switch-over timestamp and interrupts. 734 * Clear battery interrupt flags which can block new trigger events. 735 * Note: This is the default chip behaviour but added to ensure 736 * correct tamper timestamp and interrupt function. 737 */ 738 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 739 PCF2127_BIT_CTRL3_BTSE | 740 PCF2127_BIT_CTRL3_BIE | 741 PCF2127_BIT_CTRL3_BLIE, 0); 742 if (ret) { 743 dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 744 __func__); 745 return ret; 746 } 747 748 /* 749 * Enable timestamp function and store timestamp of first trigger 750 * event until TSF1 and TSF2 interrupt flags are cleared. 751 */ 752 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL, 753 PCF2127_BIT_TS_CTRL_TSOFF | 754 PCF2127_BIT_TS_CTRL_TSM, 755 PCF2127_BIT_TS_CTRL_TSM); 756 if (ret) { 757 dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n", 758 __func__); 759 return ret; 760 } 761 762 /* 763 * Enable interrupt generation when TSF1 or TSF2 timestamp flags 764 * are set. Interrupt signal is an open-drain output and can be 765 * left floating if unused. 766 */ 767 ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 768 PCF2127_BIT_CTRL2_TSIE, 769 PCF2127_BIT_CTRL2_TSIE); 770 if (ret) { 771 dev_err(dev, "%s: tamper detection config (ctrl2) failed\n", 772 __func__); 773 return ret; 774 } 775 776 ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group); 777 if (ret) { 778 dev_err(dev, "%s: tamper sysfs registering failed\n", 779 __func__); 780 return ret; 781 } 782 783 return devm_rtc_register_device(pcf2127->rtc); 784 } 785 786 #ifdef CONFIG_OF 787 static const struct of_device_id pcf2127_of_match[] = { 788 { .compatible = "nxp,pcf2127" }, 789 { .compatible = "nxp,pcf2129" }, 790 { .compatible = "nxp,pca2129" }, 791 {} 792 }; 793 MODULE_DEVICE_TABLE(of, pcf2127_of_match); 794 #endif 795 796 #if IS_ENABLED(CONFIG_I2C) 797 798 static int pcf2127_i2c_write(void *context, const void *data, size_t count) 799 { 800 struct device *dev = context; 801 struct i2c_client *client = to_i2c_client(dev); 802 int ret; 803 804 ret = i2c_master_send(client, data, count); 805 if (ret != count) 806 return ret < 0 ? ret : -EIO; 807 808 return 0; 809 } 810 811 static int pcf2127_i2c_gather_write(void *context, 812 const void *reg, size_t reg_size, 813 const void *val, size_t val_size) 814 { 815 struct device *dev = context; 816 struct i2c_client *client = to_i2c_client(dev); 817 int ret; 818 void *buf; 819 820 if (WARN_ON(reg_size != 1)) 821 return -EINVAL; 822 823 buf = kmalloc(val_size + 1, GFP_KERNEL); 824 if (!buf) 825 return -ENOMEM; 826 827 memcpy(buf, reg, 1); 828 memcpy(buf + 1, val, val_size); 829 830 ret = i2c_master_send(client, buf, val_size + 1); 831 832 kfree(buf); 833 834 if (ret != val_size + 1) 835 return ret < 0 ? ret : -EIO; 836 837 return 0; 838 } 839 840 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 841 void *val, size_t val_size) 842 { 843 struct device *dev = context; 844 struct i2c_client *client = to_i2c_client(dev); 845 int ret; 846 847 if (WARN_ON(reg_size != 1)) 848 return -EINVAL; 849 850 ret = i2c_master_send(client, reg, 1); 851 if (ret != 1) 852 return ret < 0 ? ret : -EIO; 853 854 ret = i2c_master_recv(client, val, val_size); 855 if (ret != val_size) 856 return ret < 0 ? ret : -EIO; 857 858 return 0; 859 } 860 861 /* 862 * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 863 * is that the STOP condition is required between set register address and 864 * read register data when reading from registers. 865 */ 866 static const struct regmap_bus pcf2127_i2c_regmap = { 867 .write = pcf2127_i2c_write, 868 .gather_write = pcf2127_i2c_gather_write, 869 .read = pcf2127_i2c_read, 870 }; 871 872 static struct i2c_driver pcf2127_i2c_driver; 873 874 static const struct i2c_device_id pcf2127_i2c_id[] = { 875 { "pcf2127", 1 }, 876 { "pcf2129", 0 }, 877 { "pca2129", 0 }, 878 { } 879 }; 880 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 881 882 static int pcf2127_i2c_probe(struct i2c_client *client) 883 { 884 const struct i2c_device_id *id = i2c_match_id(pcf2127_i2c_id, client); 885 struct regmap *regmap; 886 static const struct regmap_config config = { 887 .reg_bits = 8, 888 .val_bits = 8, 889 .max_register = 0x1d, 890 }; 891 892 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 893 return -ENODEV; 894 895 regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 896 &client->dev, &config); 897 if (IS_ERR(regmap)) { 898 dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 899 __func__, PTR_ERR(regmap)); 900 return PTR_ERR(regmap); 901 } 902 903 return pcf2127_probe(&client->dev, regmap, client->irq, 904 pcf2127_i2c_driver.driver.name, id->driver_data); 905 } 906 907 static struct i2c_driver pcf2127_i2c_driver = { 908 .driver = { 909 .name = "rtc-pcf2127-i2c", 910 .of_match_table = of_match_ptr(pcf2127_of_match), 911 }, 912 .probe = pcf2127_i2c_probe, 913 .id_table = pcf2127_i2c_id, 914 }; 915 916 static int pcf2127_i2c_register_driver(void) 917 { 918 return i2c_add_driver(&pcf2127_i2c_driver); 919 } 920 921 static void pcf2127_i2c_unregister_driver(void) 922 { 923 i2c_del_driver(&pcf2127_i2c_driver); 924 } 925 926 #else 927 928 static int pcf2127_i2c_register_driver(void) 929 { 930 return 0; 931 } 932 933 static void pcf2127_i2c_unregister_driver(void) 934 { 935 } 936 937 #endif 938 939 #if IS_ENABLED(CONFIG_SPI_MASTER) 940 941 static struct spi_driver pcf2127_spi_driver; 942 943 static int pcf2127_spi_probe(struct spi_device *spi) 944 { 945 static const struct regmap_config config = { 946 .reg_bits = 8, 947 .val_bits = 8, 948 .read_flag_mask = 0xa0, 949 .write_flag_mask = 0x20, 950 .max_register = 0x1d, 951 }; 952 struct regmap *regmap; 953 954 regmap = devm_regmap_init_spi(spi, &config); 955 if (IS_ERR(regmap)) { 956 dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 957 __func__, PTR_ERR(regmap)); 958 return PTR_ERR(regmap); 959 } 960 961 return pcf2127_probe(&spi->dev, regmap, spi->irq, 962 pcf2127_spi_driver.driver.name, 963 spi_get_device_id(spi)->driver_data); 964 } 965 966 static const struct spi_device_id pcf2127_spi_id[] = { 967 { "pcf2127", 1 }, 968 { "pcf2129", 0 }, 969 { "pca2129", 0 }, 970 { } 971 }; 972 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 973 974 static struct spi_driver pcf2127_spi_driver = { 975 .driver = { 976 .name = "rtc-pcf2127-spi", 977 .of_match_table = of_match_ptr(pcf2127_of_match), 978 }, 979 .probe = pcf2127_spi_probe, 980 .id_table = pcf2127_spi_id, 981 }; 982 983 static int pcf2127_spi_register_driver(void) 984 { 985 return spi_register_driver(&pcf2127_spi_driver); 986 } 987 988 static void pcf2127_spi_unregister_driver(void) 989 { 990 spi_unregister_driver(&pcf2127_spi_driver); 991 } 992 993 #else 994 995 static int pcf2127_spi_register_driver(void) 996 { 997 return 0; 998 } 999 1000 static void pcf2127_spi_unregister_driver(void) 1001 { 1002 } 1003 1004 #endif 1005 1006 static int __init pcf2127_init(void) 1007 { 1008 int ret; 1009 1010 ret = pcf2127_i2c_register_driver(); 1011 if (ret) { 1012 pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 1013 return ret; 1014 } 1015 1016 ret = pcf2127_spi_register_driver(); 1017 if (ret) { 1018 pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 1019 pcf2127_i2c_unregister_driver(); 1020 } 1021 1022 return ret; 1023 } 1024 module_init(pcf2127_init) 1025 1026 static void __exit pcf2127_exit(void) 1027 { 1028 pcf2127_spi_unregister_driver(); 1029 pcf2127_i2c_unregister_driver(); 1030 } 1031 module_exit(pcf2127_exit) 1032 1033 MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>"); 1034 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 1035 MODULE_LICENSE("GPL v2"); 1036