1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 218cb6368SRenaud Cerrato /* 3cee2cc21SAkinobu Mita * An I2C and SPI driver for the NXP PCF2127/29 RTC 418cb6368SRenaud Cerrato * Copyright 2013 Til-Technologies 518cb6368SRenaud Cerrato * 618cb6368SRenaud Cerrato * Author: Renaud Cerrato <r.cerrato@til-technologies.fr> 718cb6368SRenaud Cerrato * 80e735eaaSBruno Thomsen * Watchdog and tamper functions 90e735eaaSBruno Thomsen * Author: Bruno Thomsen <bruno.thomsen@gmail.com> 100e735eaaSBruno Thomsen * 1118cb6368SRenaud Cerrato * based on the other drivers in this same directory. 1218cb6368SRenaud Cerrato * 13836e9ea3SFabio Estevam * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 1418cb6368SRenaud Cerrato */ 1518cb6368SRenaud Cerrato 1618cb6368SRenaud Cerrato #include <linux/i2c.h> 179408ec1aSAkinobu Mita #include <linux/spi/spi.h> 1818cb6368SRenaud Cerrato #include <linux/bcd.h> 1918cb6368SRenaud Cerrato #include <linux/rtc.h> 2018cb6368SRenaud Cerrato #include <linux/slab.h> 2118cb6368SRenaud Cerrato #include <linux/module.h> 2218cb6368SRenaud Cerrato #include <linux/of.h> 238a914bacSLiam Beguin #include <linux/of_irq.h> 24*fd28ceb4SHugo Villeneuve #include <linux/of_device.h> 25907b3262SAkinobu Mita #include <linux/regmap.h> 260e735eaaSBruno Thomsen #include <linux/watchdog.h> 2718cb6368SRenaud Cerrato 28bbfe3a7aSBruno Thomsen /* Control register 1 */ 29bbfe3a7aSBruno Thomsen #define PCF2127_REG_CTRL1 0x00 30b9ac079aSPhilipp Rosenberger #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 3103623b4bSBruno Thomsen #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 32bbfe3a7aSBruno Thomsen /* Control register 2 */ 33bbfe3a7aSBruno Thomsen #define PCF2127_REG_CTRL2 0x01 348a914bacSLiam Beguin #define PCF2127_BIT_CTRL2_AIE BIT(1) 3503623b4bSBruno Thomsen #define PCF2127_BIT_CTRL2_TSIE BIT(2) 368a914bacSLiam Beguin #define PCF2127_BIT_CTRL2_AF BIT(4) 3703623b4bSBruno Thomsen #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 3827006416SAlexandre Belloni #define PCF2127_BIT_CTRL2_WDTF BIT(6) 39bbfe3a7aSBruno Thomsen /* Control register 3 */ 40bbfe3a7aSBruno Thomsen #define PCF2127_REG_CTRL3 0x02 4103623b4bSBruno Thomsen #define PCF2127_BIT_CTRL3_BLIE BIT(0) 4203623b4bSBruno Thomsen #define PCF2127_BIT_CTRL3_BIE BIT(1) 43bbfe3a7aSBruno Thomsen #define PCF2127_BIT_CTRL3_BLF BIT(2) 4403623b4bSBruno Thomsen #define PCF2127_BIT_CTRL3_BF BIT(3) 4503623b4bSBruno Thomsen #define PCF2127_BIT_CTRL3_BTSE BIT(4) 46bbfe3a7aSBruno Thomsen /* Time and date registers */ 47bbfe3a7aSBruno Thomsen #define PCF2127_REG_SC 0x03 48bbfe3a7aSBruno Thomsen #define PCF2127_BIT_SC_OSF BIT(7) 498a914bacSLiam Beguin /* Alarm registers */ 508a914bacSLiam Beguin #define PCF2127_REG_ALARM_SC 0x0A 518a914bacSLiam Beguin #define PCF2127_REG_ALARM_MN 0x0B 528a914bacSLiam Beguin #define PCF2127_REG_ALARM_HR 0x0C 538a914bacSLiam Beguin #define PCF2127_REG_ALARM_DM 0x0D 548a914bacSLiam Beguin #define PCF2127_REG_ALARM_DW 0x0E 5527006416SAlexandre Belloni #define PCF2127_BIT_ALARM_AE BIT(7) 5615f57b3eSPhilipp Rosenberger /* CLKOUT control register */ 5715f57b3eSPhilipp Rosenberger #define PCF2127_REG_CLKOUT 0x0f 5815f57b3eSPhilipp Rosenberger #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 590e735eaaSBruno Thomsen /* Watchdog registers */ 600e735eaaSBruno Thomsen #define PCF2127_REG_WD_CTL 0x10 610e735eaaSBruno Thomsen #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 620e735eaaSBruno Thomsen #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 630e735eaaSBruno Thomsen #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 640e735eaaSBruno Thomsen #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 650e735eaaSBruno Thomsen #define PCF2127_REG_WD_VAL 0x11 6603623b4bSBruno Thomsen /* Tamper timestamp registers */ 6703623b4bSBruno Thomsen #define PCF2127_REG_TS_CTRL 0x12 6803623b4bSBruno Thomsen #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 6903623b4bSBruno Thomsen #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 70bbfe3a7aSBruno Thomsen /* 71bbfe3a7aSBruno Thomsen * RAM registers 72bbfe3a7aSBruno Thomsen * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 73bbfe3a7aSBruno Thomsen * battery backed and can survive a power outage. 74bbfe3a7aSBruno Thomsen * PCF2129 doesn't have this feature. 75bbfe3a7aSBruno Thomsen */ 76bbfe3a7aSBruno Thomsen #define PCF2127_REG_RAM_ADDR_MSB 0x1A 77bbfe3a7aSBruno Thomsen #define PCF2127_REG_RAM_WRT_CMD 0x1C 78bbfe3a7aSBruno Thomsen #define PCF2127_REG_RAM_RD_CMD 0x1D 79f97cfddcSUwe Kleine-König 800e735eaaSBruno Thomsen /* Watchdog timer value constants */ 810e735eaaSBruno Thomsen #define PCF2127_WD_VAL_STOP 0 820e735eaaSBruno Thomsen #define PCF2127_WD_VAL_MIN 2 830e735eaaSBruno Thomsen #define PCF2127_WD_VAL_MAX 255 840e735eaaSBruno Thomsen #define PCF2127_WD_VAL_DEFAULT 60 85653ebd75SAndrea Scian 862f861984SMian Yousaf Kaukab /* Mask for currently enabled interrupts */ 872f861984SMian Yousaf Kaukab #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 882f861984SMian Yousaf Kaukab #define PCF2127_CTRL2_IRQ_MASK ( \ 892f861984SMian Yousaf Kaukab PCF2127_BIT_CTRL2_AF | \ 902f861984SMian Yousaf Kaukab PCF2127_BIT_CTRL2_WDTF | \ 912f861984SMian Yousaf Kaukab PCF2127_BIT_CTRL2_TSF2) 922f861984SMian Yousaf Kaukab 93*fd28ceb4SHugo Villeneuve enum pcf21xx_type { 94*fd28ceb4SHugo Villeneuve PCF2127, 95*fd28ceb4SHugo Villeneuve PCF2129, 96*fd28ceb4SHugo Villeneuve PCF21XX_LAST_ID 97*fd28ceb4SHugo Villeneuve }; 98*fd28ceb4SHugo Villeneuve 99*fd28ceb4SHugo Villeneuve struct pcf21xx_config { 100*fd28ceb4SHugo Villeneuve int type; /* IC variant */ 101*fd28ceb4SHugo Villeneuve int max_register; 102*fd28ceb4SHugo Villeneuve unsigned int has_nvmem:1; 103*fd28ceb4SHugo Villeneuve unsigned int has_bit_wd_ctl_cd0:1; 104*fd28ceb4SHugo Villeneuve }; 105*fd28ceb4SHugo Villeneuve 10618cb6368SRenaud Cerrato struct pcf2127 { 10718cb6368SRenaud Cerrato struct rtc_device *rtc; 1080e735eaaSBruno Thomsen struct watchdog_device wdd; 109907b3262SAkinobu Mita struct regmap *regmap; 110*fd28ceb4SHugo Villeneuve const struct pcf21xx_config *cfg; 1112f861984SMian Yousaf Kaukab time64_t ts; 1122f861984SMian Yousaf Kaukab bool ts_valid; 1132f861984SMian Yousaf Kaukab bool irq_enabled; 11418cb6368SRenaud Cerrato }; 11518cb6368SRenaud Cerrato 11618cb6368SRenaud Cerrato /* 11718cb6368SRenaud Cerrato * In the routines that deal directly with the pcf2127 hardware, we use 11818cb6368SRenaud Cerrato * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 11918cb6368SRenaud Cerrato */ 120907b3262SAkinobu Mita static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 12118cb6368SRenaud Cerrato { 122907b3262SAkinobu Mita struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 12331f077c3SHugo Villeneuve unsigned char buf[7]; 124907b3262SAkinobu Mita int ret; 12518cb6368SRenaud Cerrato 1267f43020eSBruno Thomsen /* 1277f43020eSBruno Thomsen * Avoid reading CTRL2 register as it causes WD_VAL register 1287f43020eSBruno Thomsen * value to reset to 0 which means watchdog is stopped. 1297f43020eSBruno Thomsen */ 13031f077c3SHugo Villeneuve ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_SC, buf, 13131f077c3SHugo Villeneuve sizeof(buf)); 132907b3262SAkinobu Mita if (ret) { 133907b3262SAkinobu Mita dev_err(dev, "%s: read error\n", __func__); 134907b3262SAkinobu Mita return ret; 13518cb6368SRenaud Cerrato } 13618cb6368SRenaud Cerrato 137bbfe3a7aSBruno Thomsen /* Clock integrity is not guaranteed when OSF flag is set. */ 13831f077c3SHugo Villeneuve if (buf[0] & PCF2127_BIT_SC_OSF) { 139653ebd75SAndrea Scian /* 140653ebd75SAndrea Scian * no need clear the flag here, 141653ebd75SAndrea Scian * it will be cleared once the new date is saved 142653ebd75SAndrea Scian */ 143907b3262SAkinobu Mita dev_warn(dev, 144653ebd75SAndrea Scian "oscillator stop detected, date/time is not reliable\n"); 145653ebd75SAndrea Scian return -EINVAL; 14618cb6368SRenaud Cerrato } 14718cb6368SRenaud Cerrato 148907b3262SAkinobu Mita dev_dbg(dev, 14931f077c3SHugo Villeneuve "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 15018cb6368SRenaud Cerrato "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 15131f077c3SHugo Villeneuve __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 15218cb6368SRenaud Cerrato 15331f077c3SHugo Villeneuve tm->tm_sec = bcd2bin(buf[0] & 0x7F); 15431f077c3SHugo Villeneuve tm->tm_min = bcd2bin(buf[1] & 0x7F); 1550476b6c8SHugo Villeneuve tm->tm_hour = bcd2bin(buf[2] & 0x3F); 15631f077c3SHugo Villeneuve tm->tm_mday = bcd2bin(buf[3] & 0x3F); 15731f077c3SHugo Villeneuve tm->tm_wday = buf[4] & 0x07; 1580476b6c8SHugo Villeneuve tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 15931f077c3SHugo Villeneuve tm->tm_year = bcd2bin(buf[6]); 160b139bb5cSAlexandre Belloni tm->tm_year += 100; 16118cb6368SRenaud Cerrato 162907b3262SAkinobu Mita dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 16318cb6368SRenaud Cerrato "mday=%d, mon=%d, year=%d, wday=%d\n", 16418cb6368SRenaud Cerrato __func__, 16518cb6368SRenaud Cerrato tm->tm_sec, tm->tm_min, tm->tm_hour, 16618cb6368SRenaud Cerrato tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 16718cb6368SRenaud Cerrato 16822652ba7SAlexandre Belloni return 0; 16918cb6368SRenaud Cerrato } 17018cb6368SRenaud Cerrato 171907b3262SAkinobu Mita static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 17218cb6368SRenaud Cerrato { 173907b3262SAkinobu Mita struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 174907b3262SAkinobu Mita unsigned char buf[7]; 17518cb6368SRenaud Cerrato int i = 0, err; 17618cb6368SRenaud Cerrato 177907b3262SAkinobu Mita dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 17818cb6368SRenaud Cerrato "mday=%d, mon=%d, year=%d, wday=%d\n", 17918cb6368SRenaud Cerrato __func__, 18018cb6368SRenaud Cerrato tm->tm_sec, tm->tm_min, tm->tm_hour, 18118cb6368SRenaud Cerrato tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 18218cb6368SRenaud Cerrato 18318cb6368SRenaud Cerrato /* hours, minutes and seconds */ 184653ebd75SAndrea Scian buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 18518cb6368SRenaud Cerrato buf[i++] = bin2bcd(tm->tm_min); 18618cb6368SRenaud Cerrato buf[i++] = bin2bcd(tm->tm_hour); 18718cb6368SRenaud Cerrato buf[i++] = bin2bcd(tm->tm_mday); 18818cb6368SRenaud Cerrato buf[i++] = tm->tm_wday & 0x07; 18918cb6368SRenaud Cerrato 19018cb6368SRenaud Cerrato /* month, 1 - 12 */ 19118cb6368SRenaud Cerrato buf[i++] = bin2bcd(tm->tm_mon + 1); 19218cb6368SRenaud Cerrato 19318cb6368SRenaud Cerrato /* year */ 194b139bb5cSAlexandre Belloni buf[i++] = bin2bcd(tm->tm_year - 100); 19518cb6368SRenaud Cerrato 19618cb6368SRenaud Cerrato /* write register's data */ 197907b3262SAkinobu Mita err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i); 198907b3262SAkinobu Mita if (err) { 1993d740c64SHugo Villeneuve dev_dbg(dev, "%s: err=%d", __func__, err); 200907b3262SAkinobu Mita return err; 20118cb6368SRenaud Cerrato } 20218cb6368SRenaud Cerrato 20318cb6368SRenaud Cerrato return 0; 20418cb6368SRenaud Cerrato } 20518cb6368SRenaud Cerrato 20618cb6368SRenaud Cerrato static int pcf2127_rtc_ioctl(struct device *dev, 20718cb6368SRenaud Cerrato unsigned int cmd, unsigned long arg) 20818cb6368SRenaud Cerrato { 209907b3262SAkinobu Mita struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 2107d65cf8cSAlexandre Belloni int val, touser = 0; 211f97cfddcSUwe Kleine-König int ret; 21218cb6368SRenaud Cerrato 21318cb6368SRenaud Cerrato switch (cmd) { 21418cb6368SRenaud Cerrato case RTC_VL_READ: 2157d65cf8cSAlexandre Belloni ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 216907b3262SAkinobu Mita if (ret) 217f97cfddcSUwe Kleine-König return ret; 21818cb6368SRenaud Cerrato 2197d65cf8cSAlexandre Belloni if (val & PCF2127_BIT_CTRL3_BLF) 2207d65cf8cSAlexandre Belloni touser |= RTC_VL_BACKUP_LOW; 2217d65cf8cSAlexandre Belloni 2227d65cf8cSAlexandre Belloni if (val & PCF2127_BIT_CTRL3_BF) 2237d65cf8cSAlexandre Belloni touser |= RTC_VL_BACKUP_SWITCH; 224f97cfddcSUwe Kleine-König 225af427311SAlexandre Belloni return put_user(touser, (unsigned int __user *)arg); 2267d65cf8cSAlexandre Belloni 2277d65cf8cSAlexandre Belloni case RTC_VL_CLR: 2287d65cf8cSAlexandre Belloni return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 2297d65cf8cSAlexandre Belloni PCF2127_BIT_CTRL3_BF, 0); 2307d65cf8cSAlexandre Belloni 23118cb6368SRenaud Cerrato default: 23218cb6368SRenaud Cerrato return -ENOIOCTLCMD; 23318cb6368SRenaud Cerrato } 23418cb6368SRenaud Cerrato } 23518cb6368SRenaud Cerrato 236d6c3029fSUwe Kleine-König static int pcf2127_nvmem_read(void *priv, unsigned int offset, 237d6c3029fSUwe Kleine-König void *val, size_t bytes) 238d6c3029fSUwe Kleine-König { 239d6c3029fSUwe Kleine-König struct pcf2127 *pcf2127 = priv; 240d6c3029fSUwe Kleine-König int ret; 241d6c3029fSUwe Kleine-König unsigned char offsetbuf[] = { offset >> 8, offset }; 242d6c3029fSUwe Kleine-König 243bbfe3a7aSBruno Thomsen ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 244d6c3029fSUwe Kleine-König offsetbuf, 2); 245d6c3029fSUwe Kleine-König if (ret) 246d6c3029fSUwe Kleine-König return ret; 247d6c3029fSUwe Kleine-König 248ba1c30bfSDan Carpenter return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 249d6c3029fSUwe Kleine-König val, bytes); 250d6c3029fSUwe Kleine-König } 251d6c3029fSUwe Kleine-König 252d6c3029fSUwe Kleine-König static int pcf2127_nvmem_write(void *priv, unsigned int offset, 253d6c3029fSUwe Kleine-König void *val, size_t bytes) 254d6c3029fSUwe Kleine-König { 255d6c3029fSUwe Kleine-König struct pcf2127 *pcf2127 = priv; 256d6c3029fSUwe Kleine-König int ret; 257d6c3029fSUwe Kleine-König unsigned char offsetbuf[] = { offset >> 8, offset }; 258d6c3029fSUwe Kleine-König 259bbfe3a7aSBruno Thomsen ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 260d6c3029fSUwe Kleine-König offsetbuf, 2); 261d6c3029fSUwe Kleine-König if (ret) 262d6c3029fSUwe Kleine-König return ret; 263d6c3029fSUwe Kleine-König 264ba1c30bfSDan Carpenter return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 265d6c3029fSUwe Kleine-König val, bytes); 266d6c3029fSUwe Kleine-König } 267d6c3029fSUwe Kleine-König 2680e735eaaSBruno Thomsen /* watchdog driver */ 2690e735eaaSBruno Thomsen 2700e735eaaSBruno Thomsen static int pcf2127_wdt_ping(struct watchdog_device *wdd) 2710e735eaaSBruno Thomsen { 2720e735eaaSBruno Thomsen struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 2730e735eaaSBruno Thomsen 2740e735eaaSBruno Thomsen return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout); 2750e735eaaSBruno Thomsen } 2760e735eaaSBruno Thomsen 2770e735eaaSBruno Thomsen /* 2780e735eaaSBruno Thomsen * Restart watchdog timer if feature is active. 2790e735eaaSBruno Thomsen * 2800e735eaaSBruno Thomsen * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 2810e735eaaSBruno Thomsen * since register also contain control/status flags for other features. 2820e735eaaSBruno Thomsen * Always call this function after reading CTRL2 register. 2830e735eaaSBruno Thomsen */ 2840e735eaaSBruno Thomsen static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 2850e735eaaSBruno Thomsen { 2860e735eaaSBruno Thomsen int ret = 0; 2870e735eaaSBruno Thomsen 2880e735eaaSBruno Thomsen if (watchdog_active(wdd)) { 2890e735eaaSBruno Thomsen ret = pcf2127_wdt_ping(wdd); 2900e735eaaSBruno Thomsen if (ret) 2910e735eaaSBruno Thomsen dev_err(wdd->parent, 2920e735eaaSBruno Thomsen "%s: watchdog restart failed, ret=%d\n", 2930e735eaaSBruno Thomsen __func__, ret); 2940e735eaaSBruno Thomsen } 2950e735eaaSBruno Thomsen 2960e735eaaSBruno Thomsen return ret; 2970e735eaaSBruno Thomsen } 2980e735eaaSBruno Thomsen 2990e735eaaSBruno Thomsen static int pcf2127_wdt_start(struct watchdog_device *wdd) 3000e735eaaSBruno Thomsen { 3010e735eaaSBruno Thomsen return pcf2127_wdt_ping(wdd); 3020e735eaaSBruno Thomsen } 3030e735eaaSBruno Thomsen 3040e735eaaSBruno Thomsen static int pcf2127_wdt_stop(struct watchdog_device *wdd) 3050e735eaaSBruno Thomsen { 3060e735eaaSBruno Thomsen struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 3070e735eaaSBruno Thomsen 3080e735eaaSBruno Thomsen return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, 3090e735eaaSBruno Thomsen PCF2127_WD_VAL_STOP); 3100e735eaaSBruno Thomsen } 3110e735eaaSBruno Thomsen 3120e735eaaSBruno Thomsen static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 3130e735eaaSBruno Thomsen unsigned int new_timeout) 3140e735eaaSBruno Thomsen { 3150e735eaaSBruno Thomsen dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 3160e735eaaSBruno Thomsen new_timeout, wdd->timeout); 3170e735eaaSBruno Thomsen 3180e735eaaSBruno Thomsen wdd->timeout = new_timeout; 3190e735eaaSBruno Thomsen 3200e735eaaSBruno Thomsen return pcf2127_wdt_active_ping(wdd); 3210e735eaaSBruno Thomsen } 3220e735eaaSBruno Thomsen 3230e735eaaSBruno Thomsen static const struct watchdog_info pcf2127_wdt_info = { 3240e735eaaSBruno Thomsen .identity = "NXP PCF2127/PCF2129 Watchdog", 3250e735eaaSBruno Thomsen .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 3260e735eaaSBruno Thomsen }; 3270e735eaaSBruno Thomsen 3280e735eaaSBruno Thomsen static const struct watchdog_ops pcf2127_watchdog_ops = { 3290e735eaaSBruno Thomsen .owner = THIS_MODULE, 3300e735eaaSBruno Thomsen .start = pcf2127_wdt_start, 3310e735eaaSBruno Thomsen .stop = pcf2127_wdt_stop, 3320e735eaaSBruno Thomsen .ping = pcf2127_wdt_ping, 3330e735eaaSBruno Thomsen .set_timeout = pcf2127_wdt_set_timeout, 3340e735eaaSBruno Thomsen }; 3350e735eaaSBruno Thomsen 3365d78533aSUwe Kleine-König static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 3375d78533aSUwe Kleine-König { 3385d78533aSUwe Kleine-König u32 wdd_timeout; 3395d78533aSUwe Kleine-König int ret; 3405d78533aSUwe Kleine-König 34171ac1345SUwe Kleine-König if (!IS_ENABLED(CONFIG_WATCHDOG) || 34271ac1345SUwe Kleine-König !device_property_read_bool(dev, "reset-source")) 3435d78533aSUwe Kleine-König return 0; 3445d78533aSUwe Kleine-König 3455d78533aSUwe Kleine-König pcf2127->wdd.parent = dev; 3465d78533aSUwe Kleine-König pcf2127->wdd.info = &pcf2127_wdt_info; 3475d78533aSUwe Kleine-König pcf2127->wdd.ops = &pcf2127_watchdog_ops; 3485d78533aSUwe Kleine-König pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 3495d78533aSUwe Kleine-König pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 3505d78533aSUwe Kleine-König pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 3515d78533aSUwe Kleine-König pcf2127->wdd.min_hw_heartbeat_ms = 500; 3525d78533aSUwe Kleine-König pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 3535d78533aSUwe Kleine-König 3545d78533aSUwe Kleine-König watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 3555d78533aSUwe Kleine-König 3565d78533aSUwe Kleine-König /* Test if watchdog timer is started by bootloader */ 3575d78533aSUwe Kleine-König ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout); 3585d78533aSUwe Kleine-König if (ret) 3595d78533aSUwe Kleine-König return ret; 3605d78533aSUwe Kleine-König 3615d78533aSUwe Kleine-König if (wdd_timeout) 3625d78533aSUwe Kleine-König set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 3635d78533aSUwe Kleine-König 3645d78533aSUwe Kleine-König return devm_watchdog_register_device(dev, &pcf2127->wdd); 3655d78533aSUwe Kleine-König } 3665d78533aSUwe Kleine-König 3678a914bacSLiam Beguin /* Alarm */ 3688a914bacSLiam Beguin static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 3698a914bacSLiam Beguin { 3708a914bacSLiam Beguin struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 37173ce0530SHugo Villeneuve u8 buf[5]; 37273ce0530SHugo Villeneuve unsigned int ctrl2; 3738a914bacSLiam Beguin int ret; 3748a914bacSLiam Beguin 3758a914bacSLiam Beguin ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 3768a914bacSLiam Beguin if (ret) 3778a914bacSLiam Beguin return ret; 3788a914bacSLiam Beguin 3798a914bacSLiam Beguin ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 3808a914bacSLiam Beguin if (ret) 3818a914bacSLiam Beguin return ret; 3828a914bacSLiam Beguin 3838a914bacSLiam Beguin ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 3848a914bacSLiam Beguin sizeof(buf)); 3858a914bacSLiam Beguin if (ret) 3868a914bacSLiam Beguin return ret; 3878a914bacSLiam Beguin 3888a914bacSLiam Beguin alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 3898a914bacSLiam Beguin alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 3908a914bacSLiam Beguin 3918a914bacSLiam Beguin alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 3928a914bacSLiam Beguin alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 3938a914bacSLiam Beguin alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 3948a914bacSLiam Beguin alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 3958a914bacSLiam Beguin 3968a914bacSLiam Beguin return 0; 3978a914bacSLiam Beguin } 3988a914bacSLiam Beguin 3998a914bacSLiam Beguin static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 4008a914bacSLiam Beguin { 4018a914bacSLiam Beguin struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 4028a914bacSLiam Beguin int ret; 4038a914bacSLiam Beguin 4048a914bacSLiam Beguin ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 4058a914bacSLiam Beguin PCF2127_BIT_CTRL2_AIE, 4068a914bacSLiam Beguin enable ? PCF2127_BIT_CTRL2_AIE : 0); 4078a914bacSLiam Beguin if (ret) 4088a914bacSLiam Beguin return ret; 4098a914bacSLiam Beguin 4108a914bacSLiam Beguin return pcf2127_wdt_active_ping(&pcf2127->wdd); 4118a914bacSLiam Beguin } 4128a914bacSLiam Beguin 4138a914bacSLiam Beguin static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 4148a914bacSLiam Beguin { 4158a914bacSLiam Beguin struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 4168a914bacSLiam Beguin uint8_t buf[5]; 4178a914bacSLiam Beguin int ret; 4188a914bacSLiam Beguin 4198a914bacSLiam Beguin ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 4208a914bacSLiam Beguin PCF2127_BIT_CTRL2_AF, 0); 4218a914bacSLiam Beguin if (ret) 4228a914bacSLiam Beguin return ret; 4238a914bacSLiam Beguin 4248a914bacSLiam Beguin ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 4258a914bacSLiam Beguin if (ret) 4268a914bacSLiam Beguin return ret; 4278a914bacSLiam Beguin 4288a914bacSLiam Beguin buf[0] = bin2bcd(alrm->time.tm_sec); 4298a914bacSLiam Beguin buf[1] = bin2bcd(alrm->time.tm_min); 4308a914bacSLiam Beguin buf[2] = bin2bcd(alrm->time.tm_hour); 4318a914bacSLiam Beguin buf[3] = bin2bcd(alrm->time.tm_mday); 43227006416SAlexandre Belloni buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 4338a914bacSLiam Beguin 4348a914bacSLiam Beguin ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf, 4358a914bacSLiam Beguin sizeof(buf)); 4368a914bacSLiam Beguin if (ret) 4378a914bacSLiam Beguin return ret; 4388a914bacSLiam Beguin 4398a914bacSLiam Beguin return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 4408a914bacSLiam Beguin } 4418a914bacSLiam Beguin 4422f861984SMian Yousaf Kaukab /* 4432f861984SMian Yousaf Kaukab * This function reads ctrl2 register, caller is responsible for calling 4442f861984SMian Yousaf Kaukab * pcf2127_wdt_active_ping() 4452f861984SMian Yousaf Kaukab */ 4462f861984SMian Yousaf Kaukab static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts) 4472f861984SMian Yousaf Kaukab { 4482f861984SMian Yousaf Kaukab struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 4492f861984SMian Yousaf Kaukab struct rtc_time tm; 4502f861984SMian Yousaf Kaukab int ret; 451720fb4b8SHugo Villeneuve unsigned char data[7]; 4522f861984SMian Yousaf Kaukab 453720fb4b8SHugo Villeneuve ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_TS_CTRL, data, 4542f861984SMian Yousaf Kaukab sizeof(data)); 4552f861984SMian Yousaf Kaukab if (ret) { 4562f861984SMian Yousaf Kaukab dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 4572f861984SMian Yousaf Kaukab return ret; 4582f861984SMian Yousaf Kaukab } 4592f861984SMian Yousaf Kaukab 4602f861984SMian Yousaf Kaukab dev_dbg(dev, 461720fb4b8SHugo Villeneuve "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 462720fb4b8SHugo Villeneuve __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 4632f861984SMian Yousaf Kaukab 464720fb4b8SHugo Villeneuve tm.tm_sec = bcd2bin(data[1] & 0x7F); 465720fb4b8SHugo Villeneuve tm.tm_min = bcd2bin(data[2] & 0x7F); 466720fb4b8SHugo Villeneuve tm.tm_hour = bcd2bin(data[3] & 0x3F); 467720fb4b8SHugo Villeneuve tm.tm_mday = bcd2bin(data[4] & 0x3F); 4682f861984SMian Yousaf Kaukab /* TS_MO register (month) value range: 1-12 */ 469720fb4b8SHugo Villeneuve tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 470720fb4b8SHugo Villeneuve tm.tm_year = bcd2bin(data[6]); 4712f861984SMian Yousaf Kaukab if (tm.tm_year < 70) 4722f861984SMian Yousaf Kaukab tm.tm_year += 100; /* assume we are in 1970...2069 */ 4732f861984SMian Yousaf Kaukab 4742f861984SMian Yousaf Kaukab ret = rtc_valid_tm(&tm); 4752f861984SMian Yousaf Kaukab if (ret) { 4762f861984SMian Yousaf Kaukab dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 4772f861984SMian Yousaf Kaukab return ret; 4782f861984SMian Yousaf Kaukab } 4792f861984SMian Yousaf Kaukab 4802f861984SMian Yousaf Kaukab *ts = rtc_tm_to_time64(&tm); 4812f861984SMian Yousaf Kaukab return 0; 4822f861984SMian Yousaf Kaukab }; 4832f861984SMian Yousaf Kaukab 4842f861984SMian Yousaf Kaukab static void pcf2127_rtc_ts_snapshot(struct device *dev) 4852f861984SMian Yousaf Kaukab { 4862f861984SMian Yousaf Kaukab struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 4872f861984SMian Yousaf Kaukab int ret; 4882f861984SMian Yousaf Kaukab 4892f861984SMian Yousaf Kaukab /* Let userspace read the first timestamp */ 4902f861984SMian Yousaf Kaukab if (pcf2127->ts_valid) 4912f861984SMian Yousaf Kaukab return; 4922f861984SMian Yousaf Kaukab 4932f861984SMian Yousaf Kaukab ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts); 4942f861984SMian Yousaf Kaukab if (!ret) 4952f861984SMian Yousaf Kaukab pcf2127->ts_valid = true; 4962f861984SMian Yousaf Kaukab } 4972f861984SMian Yousaf Kaukab 4988a914bacSLiam Beguin static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 4998a914bacSLiam Beguin { 5008a914bacSLiam Beguin struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 5012f861984SMian Yousaf Kaukab unsigned int ctrl1, ctrl2; 5028a914bacSLiam Beguin int ret = 0; 5038a914bacSLiam Beguin 5042f861984SMian Yousaf Kaukab ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 5052f861984SMian Yousaf Kaukab if (ret) 5062f861984SMian Yousaf Kaukab return IRQ_NONE; 5072f861984SMian Yousaf Kaukab 5088a914bacSLiam Beguin ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 5098a914bacSLiam Beguin if (ret) 5108a914bacSLiam Beguin return IRQ_NONE; 5118a914bacSLiam Beguin 5122f861984SMian Yousaf Kaukab if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 51327006416SAlexandre Belloni return IRQ_NONE; 51427006416SAlexandre Belloni 5152f861984SMian Yousaf Kaukab if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 5162f861984SMian Yousaf Kaukab pcf2127_rtc_ts_snapshot(dev); 5178a914bacSLiam Beguin 5182f861984SMian Yousaf Kaukab if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 5192f861984SMian Yousaf Kaukab regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 5202f861984SMian Yousaf Kaukab ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 5212f861984SMian Yousaf Kaukab 5222f861984SMian Yousaf Kaukab if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 5232f861984SMian Yousaf Kaukab regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 5242f861984SMian Yousaf Kaukab ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 5252f861984SMian Yousaf Kaukab 5262f861984SMian Yousaf Kaukab if (ctrl2 & PCF2127_BIT_CTRL2_AF) 5278a914bacSLiam Beguin rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 5288a914bacSLiam Beguin 52927006416SAlexandre Belloni pcf2127_wdt_active_ping(&pcf2127->wdd); 5308a914bacSLiam Beguin 5318a914bacSLiam Beguin return IRQ_HANDLED; 5328a914bacSLiam Beguin } 5338a914bacSLiam Beguin 53425cbe9c8SAlexandre Belloni static const struct rtc_class_ops pcf2127_rtc_ops = { 5358a914bacSLiam Beguin .ioctl = pcf2127_rtc_ioctl, 5368a914bacSLiam Beguin .read_time = pcf2127_rtc_read_time, 5378a914bacSLiam Beguin .set_time = pcf2127_rtc_set_time, 5388a914bacSLiam Beguin .read_alarm = pcf2127_rtc_read_alarm, 5398a914bacSLiam Beguin .set_alarm = pcf2127_rtc_set_alarm, 5408a914bacSLiam Beguin .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 5418a914bacSLiam Beguin }; 5428a914bacSLiam Beguin 54303623b4bSBruno Thomsen /* sysfs interface */ 54403623b4bSBruno Thomsen 54503623b4bSBruno Thomsen static ssize_t timestamp0_store(struct device *dev, 54603623b4bSBruno Thomsen struct device_attribute *attr, 54703623b4bSBruno Thomsen const char *buf, size_t count) 54803623b4bSBruno Thomsen { 54903623b4bSBruno Thomsen struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 55003623b4bSBruno Thomsen int ret; 55103623b4bSBruno Thomsen 5522f861984SMian Yousaf Kaukab if (pcf2127->irq_enabled) { 5532f861984SMian Yousaf Kaukab pcf2127->ts_valid = false; 5542f861984SMian Yousaf Kaukab } else { 55503623b4bSBruno Thomsen ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 55603623b4bSBruno Thomsen PCF2127_BIT_CTRL1_TSF1, 0); 55703623b4bSBruno Thomsen if (ret) { 55803623b4bSBruno Thomsen dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret); 55903623b4bSBruno Thomsen return ret; 56003623b4bSBruno Thomsen } 56103623b4bSBruno Thomsen 56203623b4bSBruno Thomsen ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 56303623b4bSBruno Thomsen PCF2127_BIT_CTRL2_TSF2, 0); 56403623b4bSBruno Thomsen if (ret) { 56503623b4bSBruno Thomsen dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret); 56603623b4bSBruno Thomsen return ret; 56703623b4bSBruno Thomsen } 56803623b4bSBruno Thomsen 56903623b4bSBruno Thomsen ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 57003623b4bSBruno Thomsen if (ret) 57103623b4bSBruno Thomsen return ret; 5722f861984SMian Yousaf Kaukab } 57303623b4bSBruno Thomsen 57403623b4bSBruno Thomsen return count; 57503623b4bSBruno Thomsen }; 57603623b4bSBruno Thomsen 57703623b4bSBruno Thomsen static ssize_t timestamp0_show(struct device *dev, 57803623b4bSBruno Thomsen struct device_attribute *attr, char *buf) 57903623b4bSBruno Thomsen { 58003623b4bSBruno Thomsen struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 5812f861984SMian Yousaf Kaukab unsigned int ctrl1, ctrl2; 58203623b4bSBruno Thomsen int ret; 5832f861984SMian Yousaf Kaukab time64_t ts; 58403623b4bSBruno Thomsen 5852f861984SMian Yousaf Kaukab if (pcf2127->irq_enabled) { 5862f861984SMian Yousaf Kaukab if (!pcf2127->ts_valid) 5872f861984SMian Yousaf Kaukab return 0; 5882f861984SMian Yousaf Kaukab ts = pcf2127->ts; 5892f861984SMian Yousaf Kaukab } else { 5902f861984SMian Yousaf Kaukab ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 5912f861984SMian Yousaf Kaukab if (ret) 5922f861984SMian Yousaf Kaukab return 0; 59303623b4bSBruno Thomsen 5942f861984SMian Yousaf Kaukab ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 5952f861984SMian Yousaf Kaukab if (ret) 5962f861984SMian Yousaf Kaukab return 0; 5972f861984SMian Yousaf Kaukab 5982f861984SMian Yousaf Kaukab if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) && 5992f861984SMian Yousaf Kaukab !(ctrl2 & PCF2127_BIT_CTRL2_TSF2)) 6002f861984SMian Yousaf Kaukab return 0; 6012f861984SMian Yousaf Kaukab 6022f861984SMian Yousaf Kaukab ret = pcf2127_rtc_ts_read(dev->parent, &ts); 6032f861984SMian Yousaf Kaukab if (ret) 6042f861984SMian Yousaf Kaukab return 0; 60503623b4bSBruno Thomsen 60603623b4bSBruno Thomsen ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 60703623b4bSBruno Thomsen if (ret) 60803623b4bSBruno Thomsen return ret; 6092f861984SMian Yousaf Kaukab } 6102f861984SMian Yousaf Kaukab return sprintf(buf, "%llu\n", (unsigned long long)ts); 61103623b4bSBruno Thomsen }; 61203623b4bSBruno Thomsen 61303623b4bSBruno Thomsen static DEVICE_ATTR_RW(timestamp0); 61403623b4bSBruno Thomsen 61503623b4bSBruno Thomsen static struct attribute *pcf2127_attrs[] = { 61603623b4bSBruno Thomsen &dev_attr_timestamp0.attr, 61703623b4bSBruno Thomsen NULL 61803623b4bSBruno Thomsen }; 61903623b4bSBruno Thomsen 62003623b4bSBruno Thomsen static const struct attribute_group pcf2127_attr_group = { 62103623b4bSBruno Thomsen .attrs = pcf2127_attrs, 62203623b4bSBruno Thomsen }; 62303623b4bSBruno Thomsen 624*fd28ceb4SHugo Villeneuve static struct pcf21xx_config pcf21xx_cfg[] = { 625*fd28ceb4SHugo Villeneuve [PCF2127] = { 626*fd28ceb4SHugo Villeneuve .type = PCF2127, 627*fd28ceb4SHugo Villeneuve .max_register = 0x1d, 628*fd28ceb4SHugo Villeneuve .has_nvmem = 1, 629*fd28ceb4SHugo Villeneuve .has_bit_wd_ctl_cd0 = 1, 630*fd28ceb4SHugo Villeneuve }, 631*fd28ceb4SHugo Villeneuve [PCF2129] = { 632*fd28ceb4SHugo Villeneuve .type = PCF2129, 633*fd28ceb4SHugo Villeneuve .max_register = 0x19, 634*fd28ceb4SHugo Villeneuve .has_nvmem = 0, 635*fd28ceb4SHugo Villeneuve .has_bit_wd_ctl_cd0 = 0, 636*fd28ceb4SHugo Villeneuve }, 637*fd28ceb4SHugo Villeneuve }; 638*fd28ceb4SHugo Villeneuve 639907b3262SAkinobu Mita static int pcf2127_probe(struct device *dev, struct regmap *regmap, 640*fd28ceb4SHugo Villeneuve int alarm_irq, const char *name, const struct pcf21xx_config *config) 64118cb6368SRenaud Cerrato { 64218cb6368SRenaud Cerrato struct pcf2127 *pcf2127; 643d6c3029fSUwe Kleine-König int ret = 0; 64415f57b3eSPhilipp Rosenberger unsigned int val; 64518cb6368SRenaud Cerrato 646907b3262SAkinobu Mita dev_dbg(dev, "%s\n", __func__); 64718cb6368SRenaud Cerrato 648907b3262SAkinobu Mita pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 64918cb6368SRenaud Cerrato if (!pcf2127) 65018cb6368SRenaud Cerrato return -ENOMEM; 65118cb6368SRenaud Cerrato 652907b3262SAkinobu Mita pcf2127->regmap = regmap; 653*fd28ceb4SHugo Villeneuve pcf2127->cfg = config; 65418cb6368SRenaud Cerrato 655907b3262SAkinobu Mita dev_set_drvdata(dev, pcf2127); 656907b3262SAkinobu Mita 657e788771cSBruno Thomsen pcf2127->rtc = devm_rtc_allocate_device(dev); 658d6c3029fSUwe Kleine-König if (IS_ERR(pcf2127->rtc)) 659d6c3029fSUwe Kleine-König return PTR_ERR(pcf2127->rtc); 66018cb6368SRenaud Cerrato 661e788771cSBruno Thomsen pcf2127->rtc->ops = &pcf2127_rtc_ops; 662b139bb5cSAlexandre Belloni pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 663b139bb5cSAlexandre Belloni pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 664b139bb5cSAlexandre Belloni pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 665bda10273SAlexandre Belloni set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 666689fafd5SAlexandre Belloni clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 66725cbe9c8SAlexandre Belloni clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 668e788771cSBruno Thomsen 66935425bafSBiwen Li if (alarm_irq > 0) { 670d4785b46SHugo Villeneuve unsigned long flags; 671d4785b46SHugo Villeneuve 672d4785b46SHugo Villeneuve /* 673d4785b46SHugo Villeneuve * If flags = 0, devm_request_threaded_irq() will use IRQ flags 674d4785b46SHugo Villeneuve * obtained from device tree. 675d4785b46SHugo Villeneuve */ 676d4785b46SHugo Villeneuve if (dev_fwnode(dev)) 677d4785b46SHugo Villeneuve flags = 0; 678d4785b46SHugo Villeneuve else 679d4785b46SHugo Villeneuve flags = IRQF_TRIGGER_LOW; 680d4785b46SHugo Villeneuve 68127006416SAlexandre Belloni ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 68227006416SAlexandre Belloni pcf2127_rtc_irq, 683d4785b46SHugo Villeneuve flags | IRQF_ONESHOT, 6848a914bacSLiam Beguin dev_name(dev), dev); 6858a914bacSLiam Beguin if (ret) { 6868a914bacSLiam Beguin dev_err(dev, "failed to request alarm irq\n"); 6878a914bacSLiam Beguin return ret; 6888a914bacSLiam Beguin } 6892f861984SMian Yousaf Kaukab pcf2127->irq_enabled = true; 6908a914bacSLiam Beguin } 6918a914bacSLiam Beguin 69235425bafSBiwen Li if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 6938a914bacSLiam Beguin device_init_wakeup(dev, true); 69425cbe9c8SAlexandre Belloni set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 6958a914bacSLiam Beguin } 6968a914bacSLiam Beguin 697*fd28ceb4SHugo Villeneuve if (pcf2127->cfg->has_nvmem) { 698d6c3029fSUwe Kleine-König struct nvmem_config nvmem_cfg = { 699d6c3029fSUwe Kleine-König .priv = pcf2127, 700d6c3029fSUwe Kleine-König .reg_read = pcf2127_nvmem_read, 701d6c3029fSUwe Kleine-König .reg_write = pcf2127_nvmem_write, 702d6c3029fSUwe Kleine-König .size = 512, 703d6c3029fSUwe Kleine-König }; 704d6c3029fSUwe Kleine-König 7053a905c2dSBartosz Golaszewski ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 706d6c3029fSUwe Kleine-König } 707d6c3029fSUwe Kleine-König 7080e735eaaSBruno Thomsen /* 709b9ac079aSPhilipp Rosenberger * The "Power-On Reset Override" facility prevents the RTC to do a reset 710b9ac079aSPhilipp Rosenberger * after power on. For normal operation the PORO must be disabled. 711b9ac079aSPhilipp Rosenberger */ 712b9ac079aSPhilipp Rosenberger regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 713b9ac079aSPhilipp Rosenberger PCF2127_BIT_CTRL1_POR_OVRD); 714b9ac079aSPhilipp Rosenberger 71515f57b3eSPhilipp Rosenberger ret = regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val); 71615f57b3eSPhilipp Rosenberger if (ret < 0) 71715f57b3eSPhilipp Rosenberger return ret; 71815f57b3eSPhilipp Rosenberger 71915f57b3eSPhilipp Rosenberger if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 72015f57b3eSPhilipp Rosenberger ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT, 72115f57b3eSPhilipp Rosenberger PCF2127_BIT_CLKOUT_OTPR); 72215f57b3eSPhilipp Rosenberger if (ret < 0) 72315f57b3eSPhilipp Rosenberger return ret; 72415f57b3eSPhilipp Rosenberger 72515f57b3eSPhilipp Rosenberger msleep(100); 72615f57b3eSPhilipp Rosenberger } 72715f57b3eSPhilipp Rosenberger 728b9ac079aSPhilipp Rosenberger /* 7290e735eaaSBruno Thomsen * Watchdog timer enabled and reset pin /RST activated when timed out. 7300e735eaaSBruno Thomsen * Select 1Hz clock source for watchdog timer. 7310e735eaaSBruno Thomsen * Note: Countdown timer disabled and not available. 7322843d565SBiwen Li * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 7332843d565SBiwen Li * of register watchdg_tim_ctl. The bit[6] is labeled 7342843d565SBiwen Li * as T. Bits labeled as T must always be written with 7352843d565SBiwen Li * logic 0. 7360e735eaaSBruno Thomsen */ 7370e735eaaSBruno Thomsen ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL, 7380e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_CD1 | 7390e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_CD0 | 7400e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_TF1 | 7410e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_TF0, 7420e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_CD1 | 743*fd28ceb4SHugo Villeneuve (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 7440e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_TF1); 7450e735eaaSBruno Thomsen if (ret) { 7460e735eaaSBruno Thomsen dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 7470e735eaaSBruno Thomsen return ret; 7480e735eaaSBruno Thomsen } 7490e735eaaSBruno Thomsen 7505d78533aSUwe Kleine-König pcf2127_watchdog_init(dev, pcf2127); 7510e735eaaSBruno Thomsen 75203623b4bSBruno Thomsen /* 75303623b4bSBruno Thomsen * Disable battery low/switch-over timestamp and interrupts. 75403623b4bSBruno Thomsen * Clear battery interrupt flags which can block new trigger events. 75503623b4bSBruno Thomsen * Note: This is the default chip behaviour but added to ensure 75603623b4bSBruno Thomsen * correct tamper timestamp and interrupt function. 75703623b4bSBruno Thomsen */ 75803623b4bSBruno Thomsen ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 75903623b4bSBruno Thomsen PCF2127_BIT_CTRL3_BTSE | 76003623b4bSBruno Thomsen PCF2127_BIT_CTRL3_BIE | 76103623b4bSBruno Thomsen PCF2127_BIT_CTRL3_BLIE, 0); 76203623b4bSBruno Thomsen if (ret) { 76303623b4bSBruno Thomsen dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 76403623b4bSBruno Thomsen __func__); 76503623b4bSBruno Thomsen return ret; 76603623b4bSBruno Thomsen } 76703623b4bSBruno Thomsen 76803623b4bSBruno Thomsen /* 76903623b4bSBruno Thomsen * Enable timestamp function and store timestamp of first trigger 7707b69b54aSHugo Villeneuve * event until TSF1 and TSF2 interrupt flags are cleared. 77103623b4bSBruno Thomsen */ 77203623b4bSBruno Thomsen ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL, 77303623b4bSBruno Thomsen PCF2127_BIT_TS_CTRL_TSOFF | 77403623b4bSBruno Thomsen PCF2127_BIT_TS_CTRL_TSM, 77503623b4bSBruno Thomsen PCF2127_BIT_TS_CTRL_TSM); 77603623b4bSBruno Thomsen if (ret) { 77703623b4bSBruno Thomsen dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n", 77803623b4bSBruno Thomsen __func__); 77903623b4bSBruno Thomsen return ret; 78003623b4bSBruno Thomsen } 78103623b4bSBruno Thomsen 78203623b4bSBruno Thomsen /* 78303623b4bSBruno Thomsen * Enable interrupt generation when TSF1 or TSF2 timestamp flags 78403623b4bSBruno Thomsen * are set. Interrupt signal is an open-drain output and can be 78503623b4bSBruno Thomsen * left floating if unused. 78603623b4bSBruno Thomsen */ 78703623b4bSBruno Thomsen ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 78803623b4bSBruno Thomsen PCF2127_BIT_CTRL2_TSIE, 78903623b4bSBruno Thomsen PCF2127_BIT_CTRL2_TSIE); 79003623b4bSBruno Thomsen if (ret) { 79103623b4bSBruno Thomsen dev_err(dev, "%s: tamper detection config (ctrl2) failed\n", 79203623b4bSBruno Thomsen __func__); 79303623b4bSBruno Thomsen return ret; 79403623b4bSBruno Thomsen } 79503623b4bSBruno Thomsen 79603623b4bSBruno Thomsen ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group); 79703623b4bSBruno Thomsen if (ret) { 79803623b4bSBruno Thomsen dev_err(dev, "%s: tamper sysfs registering failed\n", 79903623b4bSBruno Thomsen __func__); 80003623b4bSBruno Thomsen return ret; 80103623b4bSBruno Thomsen } 80203623b4bSBruno Thomsen 803fdcfd854SBartosz Golaszewski return devm_rtc_register_device(pcf2127->rtc); 80418cb6368SRenaud Cerrato } 80518cb6368SRenaud Cerrato 80618cb6368SRenaud Cerrato #ifdef CONFIG_OF 80718cb6368SRenaud Cerrato static const struct of_device_id pcf2127_of_match[] = { 808*fd28ceb4SHugo Villeneuve { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 809*fd28ceb4SHugo Villeneuve { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 810*fd28ceb4SHugo Villeneuve { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 81118cb6368SRenaud Cerrato {} 81218cb6368SRenaud Cerrato }; 81318cb6368SRenaud Cerrato MODULE_DEVICE_TABLE(of, pcf2127_of_match); 81418cb6368SRenaud Cerrato #endif 81518cb6368SRenaud Cerrato 8169408ec1aSAkinobu Mita #if IS_ENABLED(CONFIG_I2C) 8179408ec1aSAkinobu Mita 818907b3262SAkinobu Mita static int pcf2127_i2c_write(void *context, const void *data, size_t count) 819907b3262SAkinobu Mita { 820907b3262SAkinobu Mita struct device *dev = context; 821907b3262SAkinobu Mita struct i2c_client *client = to_i2c_client(dev); 822907b3262SAkinobu Mita int ret; 823907b3262SAkinobu Mita 824907b3262SAkinobu Mita ret = i2c_master_send(client, data, count); 825907b3262SAkinobu Mita if (ret != count) 826907b3262SAkinobu Mita return ret < 0 ? ret : -EIO; 827907b3262SAkinobu Mita 828907b3262SAkinobu Mita return 0; 829907b3262SAkinobu Mita } 830907b3262SAkinobu Mita 831907b3262SAkinobu Mita static int pcf2127_i2c_gather_write(void *context, 832907b3262SAkinobu Mita const void *reg, size_t reg_size, 833907b3262SAkinobu Mita const void *val, size_t val_size) 834907b3262SAkinobu Mita { 835907b3262SAkinobu Mita struct device *dev = context; 836907b3262SAkinobu Mita struct i2c_client *client = to_i2c_client(dev); 837907b3262SAkinobu Mita int ret; 838907b3262SAkinobu Mita void *buf; 839907b3262SAkinobu Mita 840907b3262SAkinobu Mita if (WARN_ON(reg_size != 1)) 841907b3262SAkinobu Mita return -EINVAL; 842907b3262SAkinobu Mita 843907b3262SAkinobu Mita buf = kmalloc(val_size + 1, GFP_KERNEL); 844907b3262SAkinobu Mita if (!buf) 845907b3262SAkinobu Mita return -ENOMEM; 846907b3262SAkinobu Mita 847907b3262SAkinobu Mita memcpy(buf, reg, 1); 848907b3262SAkinobu Mita memcpy(buf + 1, val, val_size); 849907b3262SAkinobu Mita 850907b3262SAkinobu Mita ret = i2c_master_send(client, buf, val_size + 1); 8519bde0afbSXulin Sun 8529bde0afbSXulin Sun kfree(buf); 8539bde0afbSXulin Sun 854907b3262SAkinobu Mita if (ret != val_size + 1) 855907b3262SAkinobu Mita return ret < 0 ? ret : -EIO; 856907b3262SAkinobu Mita 857907b3262SAkinobu Mita return 0; 858907b3262SAkinobu Mita } 859907b3262SAkinobu Mita 860907b3262SAkinobu Mita static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 861907b3262SAkinobu Mita void *val, size_t val_size) 862907b3262SAkinobu Mita { 863907b3262SAkinobu Mita struct device *dev = context; 864907b3262SAkinobu Mita struct i2c_client *client = to_i2c_client(dev); 865907b3262SAkinobu Mita int ret; 866907b3262SAkinobu Mita 867907b3262SAkinobu Mita if (WARN_ON(reg_size != 1)) 868907b3262SAkinobu Mita return -EINVAL; 869907b3262SAkinobu Mita 870907b3262SAkinobu Mita ret = i2c_master_send(client, reg, 1); 871907b3262SAkinobu Mita if (ret != 1) 872907b3262SAkinobu Mita return ret < 0 ? ret : -EIO; 873907b3262SAkinobu Mita 874907b3262SAkinobu Mita ret = i2c_master_recv(client, val, val_size); 875907b3262SAkinobu Mita if (ret != val_size) 876907b3262SAkinobu Mita return ret < 0 ? ret : -EIO; 877907b3262SAkinobu Mita 878907b3262SAkinobu Mita return 0; 879907b3262SAkinobu Mita } 880907b3262SAkinobu Mita 881907b3262SAkinobu Mita /* 882907b3262SAkinobu Mita * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 883907b3262SAkinobu Mita * is that the STOP condition is required between set register address and 884907b3262SAkinobu Mita * read register data when reading from registers. 885907b3262SAkinobu Mita */ 886907b3262SAkinobu Mita static const struct regmap_bus pcf2127_i2c_regmap = { 887907b3262SAkinobu Mita .write = pcf2127_i2c_write, 888907b3262SAkinobu Mita .gather_write = pcf2127_i2c_gather_write, 889907b3262SAkinobu Mita .read = pcf2127_i2c_read, 89018cb6368SRenaud Cerrato }; 89118cb6368SRenaud Cerrato 892907b3262SAkinobu Mita static struct i2c_driver pcf2127_i2c_driver; 893907b3262SAkinobu Mita 8945418e595SUwe Kleine-König static const struct i2c_device_id pcf2127_i2c_id[] = { 895*fd28ceb4SHugo Villeneuve { "pcf2127", PCF2127 }, 896*fd28ceb4SHugo Villeneuve { "pcf2129", PCF2129 }, 897*fd28ceb4SHugo Villeneuve { "pca2129", PCF2129 }, 8985418e595SUwe Kleine-König { } 8995418e595SUwe Kleine-König }; 9005418e595SUwe Kleine-König MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 9015418e595SUwe Kleine-König 9025418e595SUwe Kleine-König static int pcf2127_i2c_probe(struct i2c_client *client) 903907b3262SAkinobu Mita { 904907b3262SAkinobu Mita struct regmap *regmap; 905*fd28ceb4SHugo Villeneuve static struct regmap_config config = { 906907b3262SAkinobu Mita .reg_bits = 8, 907907b3262SAkinobu Mita .val_bits = 8, 908907b3262SAkinobu Mita }; 909*fd28ceb4SHugo Villeneuve const struct pcf21xx_config *variant; 910907b3262SAkinobu Mita 911907b3262SAkinobu Mita if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 912907b3262SAkinobu Mita return -ENODEV; 913907b3262SAkinobu Mita 914*fd28ceb4SHugo Villeneuve if (client->dev.of_node) { 915*fd28ceb4SHugo Villeneuve variant = of_device_get_match_data(&client->dev); 916*fd28ceb4SHugo Villeneuve if (!variant) 917*fd28ceb4SHugo Villeneuve return -ENODEV; 918*fd28ceb4SHugo Villeneuve } else { 919*fd28ceb4SHugo Villeneuve enum pcf21xx_type type = 920*fd28ceb4SHugo Villeneuve i2c_match_id(pcf2127_i2c_id, client)->driver_data; 921*fd28ceb4SHugo Villeneuve 922*fd28ceb4SHugo Villeneuve if (type >= PCF21XX_LAST_ID) 923*fd28ceb4SHugo Villeneuve return -ENODEV; 924*fd28ceb4SHugo Villeneuve variant = &pcf21xx_cfg[type]; 925*fd28ceb4SHugo Villeneuve } 926*fd28ceb4SHugo Villeneuve 927*fd28ceb4SHugo Villeneuve config.max_register = variant->max_register, 928*fd28ceb4SHugo Villeneuve 929907b3262SAkinobu Mita regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 930907b3262SAkinobu Mita &client->dev, &config); 931907b3262SAkinobu Mita if (IS_ERR(regmap)) { 932907b3262SAkinobu Mita dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 933907b3262SAkinobu Mita __func__, PTR_ERR(regmap)); 934907b3262SAkinobu Mita return PTR_ERR(regmap); 935907b3262SAkinobu Mita } 936907b3262SAkinobu Mita 93727006416SAlexandre Belloni return pcf2127_probe(&client->dev, regmap, client->irq, 938*fd28ceb4SHugo Villeneuve pcf2127_i2c_driver.driver.name, variant); 939907b3262SAkinobu Mita } 940907b3262SAkinobu Mita 941907b3262SAkinobu Mita static struct i2c_driver pcf2127_i2c_driver = { 942907b3262SAkinobu Mita .driver = { 943907b3262SAkinobu Mita .name = "rtc-pcf2127-i2c", 944907b3262SAkinobu Mita .of_match_table = of_match_ptr(pcf2127_of_match), 945907b3262SAkinobu Mita }, 94631b0cecbSUwe Kleine-König .probe = pcf2127_i2c_probe, 947907b3262SAkinobu Mita .id_table = pcf2127_i2c_id, 948907b3262SAkinobu Mita }; 9499408ec1aSAkinobu Mita 9509408ec1aSAkinobu Mita static int pcf2127_i2c_register_driver(void) 9519408ec1aSAkinobu Mita { 9529408ec1aSAkinobu Mita return i2c_add_driver(&pcf2127_i2c_driver); 9539408ec1aSAkinobu Mita } 9549408ec1aSAkinobu Mita 9559408ec1aSAkinobu Mita static void pcf2127_i2c_unregister_driver(void) 9569408ec1aSAkinobu Mita { 9579408ec1aSAkinobu Mita i2c_del_driver(&pcf2127_i2c_driver); 9589408ec1aSAkinobu Mita } 9599408ec1aSAkinobu Mita 9609408ec1aSAkinobu Mita #else 9619408ec1aSAkinobu Mita 9629408ec1aSAkinobu Mita static int pcf2127_i2c_register_driver(void) 9639408ec1aSAkinobu Mita { 9649408ec1aSAkinobu Mita return 0; 9659408ec1aSAkinobu Mita } 9669408ec1aSAkinobu Mita 9679408ec1aSAkinobu Mita static void pcf2127_i2c_unregister_driver(void) 9689408ec1aSAkinobu Mita { 9699408ec1aSAkinobu Mita } 9709408ec1aSAkinobu Mita 9719408ec1aSAkinobu Mita #endif 9729408ec1aSAkinobu Mita 9739408ec1aSAkinobu Mita #if IS_ENABLED(CONFIG_SPI_MASTER) 9749408ec1aSAkinobu Mita 9759408ec1aSAkinobu Mita static struct spi_driver pcf2127_spi_driver; 976*fd28ceb4SHugo Villeneuve static const struct spi_device_id pcf2127_spi_id[]; 9779408ec1aSAkinobu Mita 9789408ec1aSAkinobu Mita static int pcf2127_spi_probe(struct spi_device *spi) 9799408ec1aSAkinobu Mita { 980*fd28ceb4SHugo Villeneuve static struct regmap_config config = { 9819408ec1aSAkinobu Mita .reg_bits = 8, 9829408ec1aSAkinobu Mita .val_bits = 8, 9839408ec1aSAkinobu Mita .read_flag_mask = 0xa0, 9849408ec1aSAkinobu Mita .write_flag_mask = 0x20, 9859408ec1aSAkinobu Mita }; 9869408ec1aSAkinobu Mita struct regmap *regmap; 987*fd28ceb4SHugo Villeneuve const struct pcf21xx_config *variant; 988*fd28ceb4SHugo Villeneuve 989*fd28ceb4SHugo Villeneuve if (spi->dev.of_node) { 990*fd28ceb4SHugo Villeneuve variant = of_device_get_match_data(&spi->dev); 991*fd28ceb4SHugo Villeneuve if (!variant) 992*fd28ceb4SHugo Villeneuve return -ENODEV; 993*fd28ceb4SHugo Villeneuve } else { 994*fd28ceb4SHugo Villeneuve enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 995*fd28ceb4SHugo Villeneuve 996*fd28ceb4SHugo Villeneuve if (type >= PCF21XX_LAST_ID) 997*fd28ceb4SHugo Villeneuve return -ENODEV; 998*fd28ceb4SHugo Villeneuve variant = &pcf21xx_cfg[type]; 999*fd28ceb4SHugo Villeneuve } 1000*fd28ceb4SHugo Villeneuve 1001*fd28ceb4SHugo Villeneuve config.max_register = variant->max_register, 10029408ec1aSAkinobu Mita 10039408ec1aSAkinobu Mita regmap = devm_regmap_init_spi(spi, &config); 10049408ec1aSAkinobu Mita if (IS_ERR(regmap)) { 10059408ec1aSAkinobu Mita dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 10069408ec1aSAkinobu Mita __func__, PTR_ERR(regmap)); 10079408ec1aSAkinobu Mita return PTR_ERR(regmap); 10089408ec1aSAkinobu Mita } 10099408ec1aSAkinobu Mita 101027006416SAlexandre Belloni return pcf2127_probe(&spi->dev, regmap, spi->irq, 101127006416SAlexandre Belloni pcf2127_spi_driver.driver.name, 1012*fd28ceb4SHugo Villeneuve variant); 10139408ec1aSAkinobu Mita } 10149408ec1aSAkinobu Mita 10159408ec1aSAkinobu Mita static const struct spi_device_id pcf2127_spi_id[] = { 1016*fd28ceb4SHugo Villeneuve { "pcf2127", PCF2127 }, 1017*fd28ceb4SHugo Villeneuve { "pcf2129", PCF2129 }, 1018*fd28ceb4SHugo Villeneuve { "pca2129", PCF2129 }, 10199408ec1aSAkinobu Mita { } 10209408ec1aSAkinobu Mita }; 10219408ec1aSAkinobu Mita MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 10229408ec1aSAkinobu Mita 10239408ec1aSAkinobu Mita static struct spi_driver pcf2127_spi_driver = { 10249408ec1aSAkinobu Mita .driver = { 10259408ec1aSAkinobu Mita .name = "rtc-pcf2127-spi", 10269408ec1aSAkinobu Mita .of_match_table = of_match_ptr(pcf2127_of_match), 10279408ec1aSAkinobu Mita }, 10289408ec1aSAkinobu Mita .probe = pcf2127_spi_probe, 10299408ec1aSAkinobu Mita .id_table = pcf2127_spi_id, 10309408ec1aSAkinobu Mita }; 10319408ec1aSAkinobu Mita 10329408ec1aSAkinobu Mita static int pcf2127_spi_register_driver(void) 10339408ec1aSAkinobu Mita { 10349408ec1aSAkinobu Mita return spi_register_driver(&pcf2127_spi_driver); 10359408ec1aSAkinobu Mita } 10369408ec1aSAkinobu Mita 10379408ec1aSAkinobu Mita static void pcf2127_spi_unregister_driver(void) 10389408ec1aSAkinobu Mita { 10399408ec1aSAkinobu Mita spi_unregister_driver(&pcf2127_spi_driver); 10409408ec1aSAkinobu Mita } 10419408ec1aSAkinobu Mita 10429408ec1aSAkinobu Mita #else 10439408ec1aSAkinobu Mita 10449408ec1aSAkinobu Mita static int pcf2127_spi_register_driver(void) 10459408ec1aSAkinobu Mita { 10469408ec1aSAkinobu Mita return 0; 10479408ec1aSAkinobu Mita } 10489408ec1aSAkinobu Mita 10499408ec1aSAkinobu Mita static void pcf2127_spi_unregister_driver(void) 10509408ec1aSAkinobu Mita { 10519408ec1aSAkinobu Mita } 10529408ec1aSAkinobu Mita 10539408ec1aSAkinobu Mita #endif 10549408ec1aSAkinobu Mita 10559408ec1aSAkinobu Mita static int __init pcf2127_init(void) 10569408ec1aSAkinobu Mita { 10579408ec1aSAkinobu Mita int ret; 10589408ec1aSAkinobu Mita 10599408ec1aSAkinobu Mita ret = pcf2127_i2c_register_driver(); 10609408ec1aSAkinobu Mita if (ret) { 10619408ec1aSAkinobu Mita pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 10629408ec1aSAkinobu Mita return ret; 10639408ec1aSAkinobu Mita } 10649408ec1aSAkinobu Mita 10659408ec1aSAkinobu Mita ret = pcf2127_spi_register_driver(); 10669408ec1aSAkinobu Mita if (ret) { 10679408ec1aSAkinobu Mita pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 10689408ec1aSAkinobu Mita pcf2127_i2c_unregister_driver(); 10699408ec1aSAkinobu Mita } 10709408ec1aSAkinobu Mita 10719408ec1aSAkinobu Mita return ret; 10729408ec1aSAkinobu Mita } 10739408ec1aSAkinobu Mita module_init(pcf2127_init) 10749408ec1aSAkinobu Mita 10759408ec1aSAkinobu Mita static void __exit pcf2127_exit(void) 10769408ec1aSAkinobu Mita { 10779408ec1aSAkinobu Mita pcf2127_spi_unregister_driver(); 10789408ec1aSAkinobu Mita pcf2127_i2c_unregister_driver(); 10799408ec1aSAkinobu Mita } 10809408ec1aSAkinobu Mita module_exit(pcf2127_exit) 108118cb6368SRenaud Cerrato 108218cb6368SRenaud Cerrato MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>"); 1083cee2cc21SAkinobu Mita MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 10844d8318bcSUwe Kleine-König MODULE_LICENSE("GPL v2"); 1085