1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 218cb6368SRenaud Cerrato /* 3cee2cc21SAkinobu Mita * An I2C and SPI driver for the NXP PCF2127/29 RTC 418cb6368SRenaud Cerrato * Copyright 2013 Til-Technologies 518cb6368SRenaud Cerrato * 618cb6368SRenaud Cerrato * Author: Renaud Cerrato <r.cerrato@til-technologies.fr> 718cb6368SRenaud Cerrato * 80e735eaaSBruno Thomsen * Watchdog and tamper functions 90e735eaaSBruno Thomsen * Author: Bruno Thomsen <bruno.thomsen@gmail.com> 100e735eaaSBruno Thomsen * 1118cb6368SRenaud Cerrato * based on the other drivers in this same directory. 1218cb6368SRenaud Cerrato * 13836e9ea3SFabio Estevam * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf 1418cb6368SRenaud Cerrato */ 1518cb6368SRenaud Cerrato 1618cb6368SRenaud Cerrato #include <linux/i2c.h> 179408ec1aSAkinobu Mita #include <linux/spi/spi.h> 1818cb6368SRenaud Cerrato #include <linux/bcd.h> 1918cb6368SRenaud Cerrato #include <linux/rtc.h> 2018cb6368SRenaud Cerrato #include <linux/slab.h> 2118cb6368SRenaud Cerrato #include <linux/module.h> 2218cb6368SRenaud Cerrato #include <linux/of.h> 238a914bacSLiam Beguin #include <linux/of_irq.h> 24fd28ceb4SHugo Villeneuve #include <linux/of_device.h> 25907b3262SAkinobu Mita #include <linux/regmap.h> 260e735eaaSBruno Thomsen #include <linux/watchdog.h> 2718cb6368SRenaud Cerrato 28bbfe3a7aSBruno Thomsen /* Control register 1 */ 29bbfe3a7aSBruno Thomsen #define PCF2127_REG_CTRL1 0x00 30b9ac079aSPhilipp Rosenberger #define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) 3103623b4bSBruno Thomsen #define PCF2127_BIT_CTRL1_TSF1 BIT(4) 32bbfe3a7aSBruno Thomsen /* Control register 2 */ 33bbfe3a7aSBruno Thomsen #define PCF2127_REG_CTRL2 0x01 348a914bacSLiam Beguin #define PCF2127_BIT_CTRL2_AIE BIT(1) 3503623b4bSBruno Thomsen #define PCF2127_BIT_CTRL2_TSIE BIT(2) 368a914bacSLiam Beguin #define PCF2127_BIT_CTRL2_AF BIT(4) 3703623b4bSBruno Thomsen #define PCF2127_BIT_CTRL2_TSF2 BIT(5) 3827006416SAlexandre Belloni #define PCF2127_BIT_CTRL2_WDTF BIT(6) 39bbfe3a7aSBruno Thomsen /* Control register 3 */ 40bbfe3a7aSBruno Thomsen #define PCF2127_REG_CTRL3 0x02 4103623b4bSBruno Thomsen #define PCF2127_BIT_CTRL3_BLIE BIT(0) 4203623b4bSBruno Thomsen #define PCF2127_BIT_CTRL3_BIE BIT(1) 43bbfe3a7aSBruno Thomsen #define PCF2127_BIT_CTRL3_BLF BIT(2) 4403623b4bSBruno Thomsen #define PCF2127_BIT_CTRL3_BF BIT(3) 4503623b4bSBruno Thomsen #define PCF2127_BIT_CTRL3_BTSE BIT(4) 46bbfe3a7aSBruno Thomsen /* Time and date registers */ 476211aceeSHugo Villeneuve #define PCF2127_REG_TIME_BASE 0x03 48bbfe3a7aSBruno Thomsen #define PCF2127_BIT_SC_OSF BIT(7) 498a914bacSLiam Beguin /* Alarm registers */ 507c6f0db4SHugo Villeneuve #define PCF2127_REG_ALARM_BASE 0x0A 5127006416SAlexandre Belloni #define PCF2127_BIT_ALARM_AE BIT(7) 5215f57b3eSPhilipp Rosenberger /* CLKOUT control register */ 5315f57b3eSPhilipp Rosenberger #define PCF2127_REG_CLKOUT 0x0f 5415f57b3eSPhilipp Rosenberger #define PCF2127_BIT_CLKOUT_OTPR BIT(5) 550e735eaaSBruno Thomsen /* Watchdog registers */ 560e735eaaSBruno Thomsen #define PCF2127_REG_WD_CTL 0x10 570e735eaaSBruno Thomsen #define PCF2127_BIT_WD_CTL_TF0 BIT(0) 580e735eaaSBruno Thomsen #define PCF2127_BIT_WD_CTL_TF1 BIT(1) 590e735eaaSBruno Thomsen #define PCF2127_BIT_WD_CTL_CD0 BIT(6) 600e735eaaSBruno Thomsen #define PCF2127_BIT_WD_CTL_CD1 BIT(7) 610e735eaaSBruno Thomsen #define PCF2127_REG_WD_VAL 0x11 62*420cc9e8SHugo Villeneuve /* Tamper timestamp1 registers */ 63*420cc9e8SHugo Villeneuve #define PCF2127_REG_TS1_BASE 0x12 6403623b4bSBruno Thomsen #define PCF2127_BIT_TS_CTRL_TSOFF BIT(6) 6503623b4bSBruno Thomsen #define PCF2127_BIT_TS_CTRL_TSM BIT(7) 66bbfe3a7aSBruno Thomsen /* 67bbfe3a7aSBruno Thomsen * RAM registers 68bbfe3a7aSBruno Thomsen * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is 69bbfe3a7aSBruno Thomsen * battery backed and can survive a power outage. 70bbfe3a7aSBruno Thomsen * PCF2129 doesn't have this feature. 71bbfe3a7aSBruno Thomsen */ 72bbfe3a7aSBruno Thomsen #define PCF2127_REG_RAM_ADDR_MSB 0x1A 73bbfe3a7aSBruno Thomsen #define PCF2127_REG_RAM_WRT_CMD 0x1C 74bbfe3a7aSBruno Thomsen #define PCF2127_REG_RAM_RD_CMD 0x1D 75f97cfddcSUwe Kleine-König 760e735eaaSBruno Thomsen /* Watchdog timer value constants */ 770e735eaaSBruno Thomsen #define PCF2127_WD_VAL_STOP 0 780e735eaaSBruno Thomsen #define PCF2127_WD_VAL_MIN 2 790e735eaaSBruno Thomsen #define PCF2127_WD_VAL_MAX 255 800e735eaaSBruno Thomsen #define PCF2127_WD_VAL_DEFAULT 60 81653ebd75SAndrea Scian 822f861984SMian Yousaf Kaukab /* Mask for currently enabled interrupts */ 832f861984SMian Yousaf Kaukab #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1) 842f861984SMian Yousaf Kaukab #define PCF2127_CTRL2_IRQ_MASK ( \ 852f861984SMian Yousaf Kaukab PCF2127_BIT_CTRL2_AF | \ 862f861984SMian Yousaf Kaukab PCF2127_BIT_CTRL2_WDTF | \ 872f861984SMian Yousaf Kaukab PCF2127_BIT_CTRL2_TSF2) 882f861984SMian Yousaf Kaukab 89*420cc9e8SHugo Villeneuve #define PCF2127_MAX_TS_SUPPORTED 1 90*420cc9e8SHugo Villeneuve 91fd28ceb4SHugo Villeneuve enum pcf21xx_type { 92fd28ceb4SHugo Villeneuve PCF2127, 93fd28ceb4SHugo Villeneuve PCF2129, 94fd28ceb4SHugo Villeneuve PCF21XX_LAST_ID 95fd28ceb4SHugo Villeneuve }; 96fd28ceb4SHugo Villeneuve 97*420cc9e8SHugo Villeneuve struct pcf21xx_ts_config { 98*420cc9e8SHugo Villeneuve u8 reg_base; /* Base register to read timestamp values. */ 99*420cc9e8SHugo Villeneuve 100*420cc9e8SHugo Villeneuve /* 101*420cc9e8SHugo Villeneuve * If the TS input pin is driven to GND, an interrupt can be generated 102*420cc9e8SHugo Villeneuve * (supported by all variants). 103*420cc9e8SHugo Villeneuve */ 104*420cc9e8SHugo Villeneuve u8 gnd_detect_reg; /* Interrupt control register address. */ 105*420cc9e8SHugo Villeneuve u8 gnd_detect_bit; /* Interrupt bit. */ 106*420cc9e8SHugo Villeneuve 107*420cc9e8SHugo Villeneuve /* 108*420cc9e8SHugo Villeneuve * If the TS input pin is driven to an intermediate level between GND 109*420cc9e8SHugo Villeneuve * and supply, an interrupt can be generated (optional feature depending 110*420cc9e8SHugo Villeneuve * on variant). 111*420cc9e8SHugo Villeneuve */ 112*420cc9e8SHugo Villeneuve u8 inter_detect_reg; /* Interrupt control register address. */ 113*420cc9e8SHugo Villeneuve u8 inter_detect_bit; /* Interrupt bit. */ 114*420cc9e8SHugo Villeneuve 115*420cc9e8SHugo Villeneuve u8 ie_reg; /* Interrupt enable control register. */ 116*420cc9e8SHugo Villeneuve u8 ie_bit; /* Interrupt enable bit. */ 117*420cc9e8SHugo Villeneuve }; 118*420cc9e8SHugo Villeneuve 119fd28ceb4SHugo Villeneuve struct pcf21xx_config { 120fd28ceb4SHugo Villeneuve int type; /* IC variant */ 121fd28ceb4SHugo Villeneuve int max_register; 122fd28ceb4SHugo Villeneuve unsigned int has_nvmem:1; 123fd28ceb4SHugo Villeneuve unsigned int has_bit_wd_ctl_cd0:1; 1246211aceeSHugo Villeneuve u8 reg_time_base; /* Time/date base register. */ 1257c6f0db4SHugo Villeneuve u8 regs_alarm_base; /* Alarm function base registers. */ 1266b57ec29SHugo Villeneuve u8 reg_wd_ctl; /* Watchdog control register. */ 1276b57ec29SHugo Villeneuve u8 reg_wd_val; /* Watchdog value register. */ 128fc16599eSHugo Villeneuve u8 reg_clkout; /* Clkout register. */ 129*420cc9e8SHugo Villeneuve unsigned int ts_count; 130*420cc9e8SHugo Villeneuve struct pcf21xx_ts_config ts[PCF2127_MAX_TS_SUPPORTED]; 131*420cc9e8SHugo Villeneuve struct attribute_group attribute_group; 132fd28ceb4SHugo Villeneuve }; 133fd28ceb4SHugo Villeneuve 13418cb6368SRenaud Cerrato struct pcf2127 { 13518cb6368SRenaud Cerrato struct rtc_device *rtc; 1360e735eaaSBruno Thomsen struct watchdog_device wdd; 137907b3262SAkinobu Mita struct regmap *regmap; 138fd28ceb4SHugo Villeneuve const struct pcf21xx_config *cfg; 1392f861984SMian Yousaf Kaukab bool irq_enabled; 140*420cc9e8SHugo Villeneuve time64_t ts[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp values. */ 141*420cc9e8SHugo Villeneuve bool ts_valid[PCF2127_MAX_TS_SUPPORTED]; /* Timestamp valid indication. */ 14218cb6368SRenaud Cerrato }; 14318cb6368SRenaud Cerrato 14418cb6368SRenaud Cerrato /* 14518cb6368SRenaud Cerrato * In the routines that deal directly with the pcf2127 hardware, we use 14618cb6368SRenaud Cerrato * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch. 14718cb6368SRenaud Cerrato */ 148907b3262SAkinobu Mita static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm) 14918cb6368SRenaud Cerrato { 150907b3262SAkinobu Mita struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 15131f077c3SHugo Villeneuve unsigned char buf[7]; 152907b3262SAkinobu Mita int ret; 15318cb6368SRenaud Cerrato 1547f43020eSBruno Thomsen /* 1557f43020eSBruno Thomsen * Avoid reading CTRL2 register as it causes WD_VAL register 1567f43020eSBruno Thomsen * value to reset to 0 which means watchdog is stopped. 1577f43020eSBruno Thomsen */ 1586211aceeSHugo Villeneuve ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->reg_time_base, 1596211aceeSHugo Villeneuve buf, sizeof(buf)); 160907b3262SAkinobu Mita if (ret) { 161907b3262SAkinobu Mita dev_err(dev, "%s: read error\n", __func__); 162907b3262SAkinobu Mita return ret; 16318cb6368SRenaud Cerrato } 16418cb6368SRenaud Cerrato 165bbfe3a7aSBruno Thomsen /* Clock integrity is not guaranteed when OSF flag is set. */ 16631f077c3SHugo Villeneuve if (buf[0] & PCF2127_BIT_SC_OSF) { 167653ebd75SAndrea Scian /* 168653ebd75SAndrea Scian * no need clear the flag here, 169653ebd75SAndrea Scian * it will be cleared once the new date is saved 170653ebd75SAndrea Scian */ 171907b3262SAkinobu Mita dev_warn(dev, 172653ebd75SAndrea Scian "oscillator stop detected, date/time is not reliable\n"); 173653ebd75SAndrea Scian return -EINVAL; 17418cb6368SRenaud Cerrato } 17518cb6368SRenaud Cerrato 176907b3262SAkinobu Mita dev_dbg(dev, 17731f077c3SHugo Villeneuve "%s: raw data is sec=%02x, min=%02x, hr=%02x, " 17818cb6368SRenaud Cerrato "mday=%02x, wday=%02x, mon=%02x, year=%02x\n", 17931f077c3SHugo Villeneuve __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); 18018cb6368SRenaud Cerrato 18131f077c3SHugo Villeneuve tm->tm_sec = bcd2bin(buf[0] & 0x7F); 18231f077c3SHugo Villeneuve tm->tm_min = bcd2bin(buf[1] & 0x7F); 1830476b6c8SHugo Villeneuve tm->tm_hour = bcd2bin(buf[2] & 0x3F); 18431f077c3SHugo Villeneuve tm->tm_mday = bcd2bin(buf[3] & 0x3F); 18531f077c3SHugo Villeneuve tm->tm_wday = buf[4] & 0x07; 1860476b6c8SHugo Villeneuve tm->tm_mon = bcd2bin(buf[5] & 0x1F) - 1; 18731f077c3SHugo Villeneuve tm->tm_year = bcd2bin(buf[6]); 188b139bb5cSAlexandre Belloni tm->tm_year += 100; 18918cb6368SRenaud Cerrato 190907b3262SAkinobu Mita dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 19118cb6368SRenaud Cerrato "mday=%d, mon=%d, year=%d, wday=%d\n", 19218cb6368SRenaud Cerrato __func__, 19318cb6368SRenaud Cerrato tm->tm_sec, tm->tm_min, tm->tm_hour, 19418cb6368SRenaud Cerrato tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 19518cb6368SRenaud Cerrato 19622652ba7SAlexandre Belloni return 0; 19718cb6368SRenaud Cerrato } 19818cb6368SRenaud Cerrato 199907b3262SAkinobu Mita static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm) 20018cb6368SRenaud Cerrato { 201907b3262SAkinobu Mita struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 202907b3262SAkinobu Mita unsigned char buf[7]; 20318cb6368SRenaud Cerrato int i = 0, err; 20418cb6368SRenaud Cerrato 205907b3262SAkinobu Mita dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, " 20618cb6368SRenaud Cerrato "mday=%d, mon=%d, year=%d, wday=%d\n", 20718cb6368SRenaud Cerrato __func__, 20818cb6368SRenaud Cerrato tm->tm_sec, tm->tm_min, tm->tm_hour, 20918cb6368SRenaud Cerrato tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 21018cb6368SRenaud Cerrato 21118cb6368SRenaud Cerrato /* hours, minutes and seconds */ 212653ebd75SAndrea Scian buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */ 21318cb6368SRenaud Cerrato buf[i++] = bin2bcd(tm->tm_min); 21418cb6368SRenaud Cerrato buf[i++] = bin2bcd(tm->tm_hour); 21518cb6368SRenaud Cerrato buf[i++] = bin2bcd(tm->tm_mday); 21618cb6368SRenaud Cerrato buf[i++] = tm->tm_wday & 0x07; 21718cb6368SRenaud Cerrato 21818cb6368SRenaud Cerrato /* month, 1 - 12 */ 21918cb6368SRenaud Cerrato buf[i++] = bin2bcd(tm->tm_mon + 1); 22018cb6368SRenaud Cerrato 22118cb6368SRenaud Cerrato /* year */ 222b139bb5cSAlexandre Belloni buf[i++] = bin2bcd(tm->tm_year - 100); 22318cb6368SRenaud Cerrato 22418cb6368SRenaud Cerrato /* write register's data */ 2256211aceeSHugo Villeneuve err = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->reg_time_base, buf, i); 226907b3262SAkinobu Mita if (err) { 2273d740c64SHugo Villeneuve dev_dbg(dev, "%s: err=%d", __func__, err); 228907b3262SAkinobu Mita return err; 22918cb6368SRenaud Cerrato } 23018cb6368SRenaud Cerrato 23118cb6368SRenaud Cerrato return 0; 23218cb6368SRenaud Cerrato } 23318cb6368SRenaud Cerrato 23418cb6368SRenaud Cerrato static int pcf2127_rtc_ioctl(struct device *dev, 23518cb6368SRenaud Cerrato unsigned int cmd, unsigned long arg) 23618cb6368SRenaud Cerrato { 237907b3262SAkinobu Mita struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 2387d65cf8cSAlexandre Belloni int val, touser = 0; 239f97cfddcSUwe Kleine-König int ret; 24018cb6368SRenaud Cerrato 24118cb6368SRenaud Cerrato switch (cmd) { 24218cb6368SRenaud Cerrato case RTC_VL_READ: 2437d65cf8cSAlexandre Belloni ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val); 244907b3262SAkinobu Mita if (ret) 245f97cfddcSUwe Kleine-König return ret; 24618cb6368SRenaud Cerrato 2477d65cf8cSAlexandre Belloni if (val & PCF2127_BIT_CTRL3_BLF) 2487d65cf8cSAlexandre Belloni touser |= RTC_VL_BACKUP_LOW; 2497d65cf8cSAlexandre Belloni 2507d65cf8cSAlexandre Belloni if (val & PCF2127_BIT_CTRL3_BF) 2517d65cf8cSAlexandre Belloni touser |= RTC_VL_BACKUP_SWITCH; 252f97cfddcSUwe Kleine-König 253af427311SAlexandre Belloni return put_user(touser, (unsigned int __user *)arg); 2547d65cf8cSAlexandre Belloni 2557d65cf8cSAlexandre Belloni case RTC_VL_CLR: 2567d65cf8cSAlexandre Belloni return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 2577d65cf8cSAlexandre Belloni PCF2127_BIT_CTRL3_BF, 0); 2587d65cf8cSAlexandre Belloni 25918cb6368SRenaud Cerrato default: 26018cb6368SRenaud Cerrato return -ENOIOCTLCMD; 26118cb6368SRenaud Cerrato } 26218cb6368SRenaud Cerrato } 26318cb6368SRenaud Cerrato 264d6c3029fSUwe Kleine-König static int pcf2127_nvmem_read(void *priv, unsigned int offset, 265d6c3029fSUwe Kleine-König void *val, size_t bytes) 266d6c3029fSUwe Kleine-König { 267d6c3029fSUwe Kleine-König struct pcf2127 *pcf2127 = priv; 268d6c3029fSUwe Kleine-König int ret; 269d6c3029fSUwe Kleine-König unsigned char offsetbuf[] = { offset >> 8, offset }; 270d6c3029fSUwe Kleine-König 271bbfe3a7aSBruno Thomsen ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 272d6c3029fSUwe Kleine-König offsetbuf, 2); 273d6c3029fSUwe Kleine-König if (ret) 274d6c3029fSUwe Kleine-König return ret; 275d6c3029fSUwe Kleine-König 276ba1c30bfSDan Carpenter return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD, 277d6c3029fSUwe Kleine-König val, bytes); 278d6c3029fSUwe Kleine-König } 279d6c3029fSUwe Kleine-König 280d6c3029fSUwe Kleine-König static int pcf2127_nvmem_write(void *priv, unsigned int offset, 281d6c3029fSUwe Kleine-König void *val, size_t bytes) 282d6c3029fSUwe Kleine-König { 283d6c3029fSUwe Kleine-König struct pcf2127 *pcf2127 = priv; 284d6c3029fSUwe Kleine-König int ret; 285d6c3029fSUwe Kleine-König unsigned char offsetbuf[] = { offset >> 8, offset }; 286d6c3029fSUwe Kleine-König 287bbfe3a7aSBruno Thomsen ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB, 288d6c3029fSUwe Kleine-König offsetbuf, 2); 289d6c3029fSUwe Kleine-König if (ret) 290d6c3029fSUwe Kleine-König return ret; 291d6c3029fSUwe Kleine-König 292ba1c30bfSDan Carpenter return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD, 293d6c3029fSUwe Kleine-König val, bytes); 294d6c3029fSUwe Kleine-König } 295d6c3029fSUwe Kleine-König 2960e735eaaSBruno Thomsen /* watchdog driver */ 2970e735eaaSBruno Thomsen 2980e735eaaSBruno Thomsen static int pcf2127_wdt_ping(struct watchdog_device *wdd) 2990e735eaaSBruno Thomsen { 3000e735eaaSBruno Thomsen struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 3010e735eaaSBruno Thomsen 3026b57ec29SHugo Villeneuve return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, wdd->timeout); 3030e735eaaSBruno Thomsen } 3040e735eaaSBruno Thomsen 3050e735eaaSBruno Thomsen /* 3060e735eaaSBruno Thomsen * Restart watchdog timer if feature is active. 3070e735eaaSBruno Thomsen * 3080e735eaaSBruno Thomsen * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate, 3090e735eaaSBruno Thomsen * since register also contain control/status flags for other features. 3100e735eaaSBruno Thomsen * Always call this function after reading CTRL2 register. 3110e735eaaSBruno Thomsen */ 3120e735eaaSBruno Thomsen static int pcf2127_wdt_active_ping(struct watchdog_device *wdd) 3130e735eaaSBruno Thomsen { 3140e735eaaSBruno Thomsen int ret = 0; 3150e735eaaSBruno Thomsen 3160e735eaaSBruno Thomsen if (watchdog_active(wdd)) { 3170e735eaaSBruno Thomsen ret = pcf2127_wdt_ping(wdd); 3180e735eaaSBruno Thomsen if (ret) 3190e735eaaSBruno Thomsen dev_err(wdd->parent, 3200e735eaaSBruno Thomsen "%s: watchdog restart failed, ret=%d\n", 3210e735eaaSBruno Thomsen __func__, ret); 3220e735eaaSBruno Thomsen } 3230e735eaaSBruno Thomsen 3240e735eaaSBruno Thomsen return ret; 3250e735eaaSBruno Thomsen } 3260e735eaaSBruno Thomsen 3270e735eaaSBruno Thomsen static int pcf2127_wdt_start(struct watchdog_device *wdd) 3280e735eaaSBruno Thomsen { 3290e735eaaSBruno Thomsen return pcf2127_wdt_ping(wdd); 3300e735eaaSBruno Thomsen } 3310e735eaaSBruno Thomsen 3320e735eaaSBruno Thomsen static int pcf2127_wdt_stop(struct watchdog_device *wdd) 3330e735eaaSBruno Thomsen { 3340e735eaaSBruno Thomsen struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd); 3350e735eaaSBruno Thomsen 3366b57ec29SHugo Villeneuve return regmap_write(pcf2127->regmap, pcf2127->cfg->reg_wd_val, 3370e735eaaSBruno Thomsen PCF2127_WD_VAL_STOP); 3380e735eaaSBruno Thomsen } 3390e735eaaSBruno Thomsen 3400e735eaaSBruno Thomsen static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd, 3410e735eaaSBruno Thomsen unsigned int new_timeout) 3420e735eaaSBruno Thomsen { 3430e735eaaSBruno Thomsen dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n", 3440e735eaaSBruno Thomsen new_timeout, wdd->timeout); 3450e735eaaSBruno Thomsen 3460e735eaaSBruno Thomsen wdd->timeout = new_timeout; 3470e735eaaSBruno Thomsen 3480e735eaaSBruno Thomsen return pcf2127_wdt_active_ping(wdd); 3490e735eaaSBruno Thomsen } 3500e735eaaSBruno Thomsen 3510e735eaaSBruno Thomsen static const struct watchdog_info pcf2127_wdt_info = { 3520e735eaaSBruno Thomsen .identity = "NXP PCF2127/PCF2129 Watchdog", 3530e735eaaSBruno Thomsen .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, 3540e735eaaSBruno Thomsen }; 3550e735eaaSBruno Thomsen 3560e735eaaSBruno Thomsen static const struct watchdog_ops pcf2127_watchdog_ops = { 3570e735eaaSBruno Thomsen .owner = THIS_MODULE, 3580e735eaaSBruno Thomsen .start = pcf2127_wdt_start, 3590e735eaaSBruno Thomsen .stop = pcf2127_wdt_stop, 3600e735eaaSBruno Thomsen .ping = pcf2127_wdt_ping, 3610e735eaaSBruno Thomsen .set_timeout = pcf2127_wdt_set_timeout, 3620e735eaaSBruno Thomsen }; 3630e735eaaSBruno Thomsen 3645d78533aSUwe Kleine-König static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127) 3655d78533aSUwe Kleine-König { 3665d78533aSUwe Kleine-König u32 wdd_timeout; 3675d78533aSUwe Kleine-König int ret; 3685d78533aSUwe Kleine-König 36971ac1345SUwe Kleine-König if (!IS_ENABLED(CONFIG_WATCHDOG) || 37071ac1345SUwe Kleine-König !device_property_read_bool(dev, "reset-source")) 3715d78533aSUwe Kleine-König return 0; 3725d78533aSUwe Kleine-König 3735d78533aSUwe Kleine-König pcf2127->wdd.parent = dev; 3745d78533aSUwe Kleine-König pcf2127->wdd.info = &pcf2127_wdt_info; 3755d78533aSUwe Kleine-König pcf2127->wdd.ops = &pcf2127_watchdog_ops; 3765d78533aSUwe Kleine-König pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN; 3775d78533aSUwe Kleine-König pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX; 3785d78533aSUwe Kleine-König pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT; 3795d78533aSUwe Kleine-König pcf2127->wdd.min_hw_heartbeat_ms = 500; 3805d78533aSUwe Kleine-König pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS; 3815d78533aSUwe Kleine-König 3825d78533aSUwe Kleine-König watchdog_set_drvdata(&pcf2127->wdd, pcf2127); 3835d78533aSUwe Kleine-König 3845d78533aSUwe Kleine-König /* Test if watchdog timer is started by bootloader */ 3856b57ec29SHugo Villeneuve ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_wd_val, &wdd_timeout); 3865d78533aSUwe Kleine-König if (ret) 3875d78533aSUwe Kleine-König return ret; 3885d78533aSUwe Kleine-König 3895d78533aSUwe Kleine-König if (wdd_timeout) 3905d78533aSUwe Kleine-König set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status); 3915d78533aSUwe Kleine-König 3925d78533aSUwe Kleine-König return devm_watchdog_register_device(dev, &pcf2127->wdd); 3935d78533aSUwe Kleine-König } 3945d78533aSUwe Kleine-König 3958a914bacSLiam Beguin /* Alarm */ 3968a914bacSLiam Beguin static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 3978a914bacSLiam Beguin { 3988a914bacSLiam Beguin struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 39973ce0530SHugo Villeneuve u8 buf[5]; 40073ce0530SHugo Villeneuve unsigned int ctrl2; 4018a914bacSLiam Beguin int ret; 4028a914bacSLiam Beguin 4038a914bacSLiam Beguin ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 4048a914bacSLiam Beguin if (ret) 4058a914bacSLiam Beguin return ret; 4068a914bacSLiam Beguin 4078a914bacSLiam Beguin ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 4088a914bacSLiam Beguin if (ret) 4098a914bacSLiam Beguin return ret; 4108a914bacSLiam Beguin 4117c6f0db4SHugo Villeneuve ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 4127c6f0db4SHugo Villeneuve buf, sizeof(buf)); 4138a914bacSLiam Beguin if (ret) 4148a914bacSLiam Beguin return ret; 4158a914bacSLiam Beguin 4168a914bacSLiam Beguin alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE; 4178a914bacSLiam Beguin alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF; 4188a914bacSLiam Beguin 4198a914bacSLiam Beguin alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F); 4208a914bacSLiam Beguin alrm->time.tm_min = bcd2bin(buf[1] & 0x7F); 4218a914bacSLiam Beguin alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F); 4228a914bacSLiam Beguin alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F); 4238a914bacSLiam Beguin 4248a914bacSLiam Beguin return 0; 4258a914bacSLiam Beguin } 4268a914bacSLiam Beguin 4278a914bacSLiam Beguin static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable) 4288a914bacSLiam Beguin { 4298a914bacSLiam Beguin struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 4308a914bacSLiam Beguin int ret; 4318a914bacSLiam Beguin 4328a914bacSLiam Beguin ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 4338a914bacSLiam Beguin PCF2127_BIT_CTRL2_AIE, 4348a914bacSLiam Beguin enable ? PCF2127_BIT_CTRL2_AIE : 0); 4358a914bacSLiam Beguin if (ret) 4368a914bacSLiam Beguin return ret; 4378a914bacSLiam Beguin 4388a914bacSLiam Beguin return pcf2127_wdt_active_ping(&pcf2127->wdd); 4398a914bacSLiam Beguin } 4408a914bacSLiam Beguin 4418a914bacSLiam Beguin static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 4428a914bacSLiam Beguin { 4438a914bacSLiam Beguin struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 4448a914bacSLiam Beguin uint8_t buf[5]; 4458a914bacSLiam Beguin int ret; 4468a914bacSLiam Beguin 4478a914bacSLiam Beguin ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2, 4488a914bacSLiam Beguin PCF2127_BIT_CTRL2_AF, 0); 4498a914bacSLiam Beguin if (ret) 4508a914bacSLiam Beguin return ret; 4518a914bacSLiam Beguin 4528a914bacSLiam Beguin ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 4538a914bacSLiam Beguin if (ret) 4548a914bacSLiam Beguin return ret; 4558a914bacSLiam Beguin 4568a914bacSLiam Beguin buf[0] = bin2bcd(alrm->time.tm_sec); 4578a914bacSLiam Beguin buf[1] = bin2bcd(alrm->time.tm_min); 4588a914bacSLiam Beguin buf[2] = bin2bcd(alrm->time.tm_hour); 4598a914bacSLiam Beguin buf[3] = bin2bcd(alrm->time.tm_mday); 46027006416SAlexandre Belloni buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */ 4618a914bacSLiam Beguin 4627c6f0db4SHugo Villeneuve ret = regmap_bulk_write(pcf2127->regmap, pcf2127->cfg->regs_alarm_base, 4637c6f0db4SHugo Villeneuve buf, sizeof(buf)); 4648a914bacSLiam Beguin if (ret) 4658a914bacSLiam Beguin return ret; 4668a914bacSLiam Beguin 4678a914bacSLiam Beguin return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled); 4688a914bacSLiam Beguin } 4698a914bacSLiam Beguin 4702f861984SMian Yousaf Kaukab /* 471*420cc9e8SHugo Villeneuve * This function reads one timestamp function data, caller is responsible for 472*420cc9e8SHugo Villeneuve * calling pcf2127_wdt_active_ping() 4732f861984SMian Yousaf Kaukab */ 474*420cc9e8SHugo Villeneuve static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts, 475*420cc9e8SHugo Villeneuve int ts_id) 4762f861984SMian Yousaf Kaukab { 4772f861984SMian Yousaf Kaukab struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 4782f861984SMian Yousaf Kaukab struct rtc_time tm; 4792f861984SMian Yousaf Kaukab int ret; 480720fb4b8SHugo Villeneuve unsigned char data[7]; 4812f861984SMian Yousaf Kaukab 482*420cc9e8SHugo Villeneuve ret = regmap_bulk_read(pcf2127->regmap, pcf2127->cfg->ts[ts_id].reg_base, 483*420cc9e8SHugo Villeneuve data, sizeof(data)); 4842f861984SMian Yousaf Kaukab if (ret) { 4852f861984SMian Yousaf Kaukab dev_err(dev, "%s: read error ret=%d\n", __func__, ret); 4862f861984SMian Yousaf Kaukab return ret; 4872f861984SMian Yousaf Kaukab } 4882f861984SMian Yousaf Kaukab 4892f861984SMian Yousaf Kaukab dev_dbg(dev, 490720fb4b8SHugo Villeneuve "%s: raw data is ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n", 491720fb4b8SHugo Villeneuve __func__, data[1], data[2], data[3], data[4], data[5], data[6]); 4922f861984SMian Yousaf Kaukab 493720fb4b8SHugo Villeneuve tm.tm_sec = bcd2bin(data[1] & 0x7F); 494720fb4b8SHugo Villeneuve tm.tm_min = bcd2bin(data[2] & 0x7F); 495720fb4b8SHugo Villeneuve tm.tm_hour = bcd2bin(data[3] & 0x3F); 496720fb4b8SHugo Villeneuve tm.tm_mday = bcd2bin(data[4] & 0x3F); 4972f861984SMian Yousaf Kaukab /* TS_MO register (month) value range: 1-12 */ 498720fb4b8SHugo Villeneuve tm.tm_mon = bcd2bin(data[5] & 0x1F) - 1; 499720fb4b8SHugo Villeneuve tm.tm_year = bcd2bin(data[6]); 5002f861984SMian Yousaf Kaukab if (tm.tm_year < 70) 5012f861984SMian Yousaf Kaukab tm.tm_year += 100; /* assume we are in 1970...2069 */ 5022f861984SMian Yousaf Kaukab 5032f861984SMian Yousaf Kaukab ret = rtc_valid_tm(&tm); 5042f861984SMian Yousaf Kaukab if (ret) { 5052f861984SMian Yousaf Kaukab dev_err(dev, "Invalid timestamp. ret=%d\n", ret); 5062f861984SMian Yousaf Kaukab return ret; 5072f861984SMian Yousaf Kaukab } 5082f861984SMian Yousaf Kaukab 5092f861984SMian Yousaf Kaukab *ts = rtc_tm_to_time64(&tm); 5102f861984SMian Yousaf Kaukab return 0; 5112f861984SMian Yousaf Kaukab }; 5122f861984SMian Yousaf Kaukab 513*420cc9e8SHugo Villeneuve static void pcf2127_rtc_ts_snapshot(struct device *dev, int ts_id) 5142f861984SMian Yousaf Kaukab { 5152f861984SMian Yousaf Kaukab struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 5162f861984SMian Yousaf Kaukab int ret; 5172f861984SMian Yousaf Kaukab 518*420cc9e8SHugo Villeneuve if (ts_id >= pcf2127->cfg->ts_count) 5192f861984SMian Yousaf Kaukab return; 5202f861984SMian Yousaf Kaukab 521*420cc9e8SHugo Villeneuve /* Let userspace read the first timestamp */ 522*420cc9e8SHugo Villeneuve if (pcf2127->ts_valid[ts_id]) 523*420cc9e8SHugo Villeneuve return; 524*420cc9e8SHugo Villeneuve 525*420cc9e8SHugo Villeneuve ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts[ts_id], ts_id); 5262f861984SMian Yousaf Kaukab if (!ret) 527*420cc9e8SHugo Villeneuve pcf2127->ts_valid[ts_id] = true; 5282f861984SMian Yousaf Kaukab } 5292f861984SMian Yousaf Kaukab 5308a914bacSLiam Beguin static irqreturn_t pcf2127_rtc_irq(int irq, void *dev) 5318a914bacSLiam Beguin { 5328a914bacSLiam Beguin struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 5332f861984SMian Yousaf Kaukab unsigned int ctrl1, ctrl2; 5348a914bacSLiam Beguin int ret = 0; 5358a914bacSLiam Beguin 5362f861984SMian Yousaf Kaukab ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1); 5372f861984SMian Yousaf Kaukab if (ret) 5382f861984SMian Yousaf Kaukab return IRQ_NONE; 5392f861984SMian Yousaf Kaukab 5408a914bacSLiam Beguin ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2); 5418a914bacSLiam Beguin if (ret) 5428a914bacSLiam Beguin return IRQ_NONE; 5438a914bacSLiam Beguin 5442f861984SMian Yousaf Kaukab if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK)) 54527006416SAlexandre Belloni return IRQ_NONE; 54627006416SAlexandre Belloni 5472f861984SMian Yousaf Kaukab if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2) 548*420cc9e8SHugo Villeneuve pcf2127_rtc_ts_snapshot(dev, 0); 5498a914bacSLiam Beguin 5502f861984SMian Yousaf Kaukab if (ctrl1 & PCF2127_CTRL1_IRQ_MASK) 5512f861984SMian Yousaf Kaukab regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1, 5522f861984SMian Yousaf Kaukab ctrl1 & ~PCF2127_CTRL1_IRQ_MASK); 5532f861984SMian Yousaf Kaukab 5542f861984SMian Yousaf Kaukab if (ctrl2 & PCF2127_CTRL2_IRQ_MASK) 5552f861984SMian Yousaf Kaukab regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2, 5562f861984SMian Yousaf Kaukab ctrl2 & ~PCF2127_CTRL2_IRQ_MASK); 5572f861984SMian Yousaf Kaukab 5582f861984SMian Yousaf Kaukab if (ctrl2 & PCF2127_BIT_CTRL2_AF) 5598a914bacSLiam Beguin rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF); 5608a914bacSLiam Beguin 56127006416SAlexandre Belloni pcf2127_wdt_active_ping(&pcf2127->wdd); 5628a914bacSLiam Beguin 5638a914bacSLiam Beguin return IRQ_HANDLED; 5648a914bacSLiam Beguin } 5658a914bacSLiam Beguin 56625cbe9c8SAlexandre Belloni static const struct rtc_class_ops pcf2127_rtc_ops = { 5678a914bacSLiam Beguin .ioctl = pcf2127_rtc_ioctl, 5688a914bacSLiam Beguin .read_time = pcf2127_rtc_read_time, 5698a914bacSLiam Beguin .set_time = pcf2127_rtc_set_time, 5708a914bacSLiam Beguin .read_alarm = pcf2127_rtc_read_alarm, 5718a914bacSLiam Beguin .set_alarm = pcf2127_rtc_set_alarm, 5728a914bacSLiam Beguin .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable, 5738a914bacSLiam Beguin }; 5748a914bacSLiam Beguin 57503623b4bSBruno Thomsen /* sysfs interface */ 57603623b4bSBruno Thomsen 577*420cc9e8SHugo Villeneuve static ssize_t timestamp_store(struct device *dev, 57803623b4bSBruno Thomsen struct device_attribute *attr, 579*420cc9e8SHugo Villeneuve const char *buf, size_t count, int ts_id) 58003623b4bSBruno Thomsen { 58103623b4bSBruno Thomsen struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 58203623b4bSBruno Thomsen int ret; 58303623b4bSBruno Thomsen 584*420cc9e8SHugo Villeneuve if (ts_id >= pcf2127->cfg->ts_count) 585*420cc9e8SHugo Villeneuve return 0; 586*420cc9e8SHugo Villeneuve 5872f861984SMian Yousaf Kaukab if (pcf2127->irq_enabled) { 588*420cc9e8SHugo Villeneuve pcf2127->ts_valid[ts_id] = false; 5892f861984SMian Yousaf Kaukab } else { 590*420cc9e8SHugo Villeneuve /* Always clear GND interrupt bit. */ 591*420cc9e8SHugo Villeneuve ret = regmap_update_bits(pcf2127->regmap, 592*420cc9e8SHugo Villeneuve pcf2127->cfg->ts[ts_id].gnd_detect_reg, 593*420cc9e8SHugo Villeneuve pcf2127->cfg->ts[ts_id].gnd_detect_bit, 594*420cc9e8SHugo Villeneuve 0); 595*420cc9e8SHugo Villeneuve 59603623b4bSBruno Thomsen if (ret) { 597*420cc9e8SHugo Villeneuve dev_err(dev, "%s: update TS gnd detect ret=%d\n", __func__, ret); 59803623b4bSBruno Thomsen return ret; 59903623b4bSBruno Thomsen } 60003623b4bSBruno Thomsen 601*420cc9e8SHugo Villeneuve if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 602*420cc9e8SHugo Villeneuve /* Clear intermediate level interrupt bit if supported. */ 603*420cc9e8SHugo Villeneuve ret = regmap_update_bits(pcf2127->regmap, 604*420cc9e8SHugo Villeneuve pcf2127->cfg->ts[ts_id].inter_detect_reg, 605*420cc9e8SHugo Villeneuve pcf2127->cfg->ts[ts_id].inter_detect_bit, 606*420cc9e8SHugo Villeneuve 0); 60703623b4bSBruno Thomsen if (ret) { 608*420cc9e8SHugo Villeneuve dev_err(dev, "%s: update TS intermediate level detect ret=%d\n", 609*420cc9e8SHugo Villeneuve __func__, ret); 61003623b4bSBruno Thomsen return ret; 61103623b4bSBruno Thomsen } 612*420cc9e8SHugo Villeneuve } 61303623b4bSBruno Thomsen 61403623b4bSBruno Thomsen ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 61503623b4bSBruno Thomsen if (ret) 61603623b4bSBruno Thomsen return ret; 6172f861984SMian Yousaf Kaukab } 61803623b4bSBruno Thomsen 61903623b4bSBruno Thomsen return count; 620*420cc9e8SHugo Villeneuve } 621*420cc9e8SHugo Villeneuve 622*420cc9e8SHugo Villeneuve static ssize_t timestamp0_store(struct device *dev, 623*420cc9e8SHugo Villeneuve struct device_attribute *attr, 624*420cc9e8SHugo Villeneuve const char *buf, size_t count) 625*420cc9e8SHugo Villeneuve { 626*420cc9e8SHugo Villeneuve return timestamp_store(dev, attr, buf, count, 0); 62703623b4bSBruno Thomsen }; 62803623b4bSBruno Thomsen 629*420cc9e8SHugo Villeneuve static ssize_t timestamp_show(struct device *dev, 630*420cc9e8SHugo Villeneuve struct device_attribute *attr, char *buf, 631*420cc9e8SHugo Villeneuve int ts_id) 63203623b4bSBruno Thomsen { 63303623b4bSBruno Thomsen struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent); 63403623b4bSBruno Thomsen int ret; 6352f861984SMian Yousaf Kaukab time64_t ts; 63603623b4bSBruno Thomsen 637*420cc9e8SHugo Villeneuve if (ts_id >= pcf2127->cfg->ts_count) 638*420cc9e8SHugo Villeneuve return 0; 639*420cc9e8SHugo Villeneuve 6402f861984SMian Yousaf Kaukab if (pcf2127->irq_enabled) { 641*420cc9e8SHugo Villeneuve if (!pcf2127->ts_valid[ts_id]) 6422f861984SMian Yousaf Kaukab return 0; 643*420cc9e8SHugo Villeneuve ts = pcf2127->ts[ts_id]; 6442f861984SMian Yousaf Kaukab } else { 645*420cc9e8SHugo Villeneuve u8 valid_low = 0; 646*420cc9e8SHugo Villeneuve u8 valid_inter = 0; 647*420cc9e8SHugo Villeneuve unsigned int ctrl; 648*420cc9e8SHugo Villeneuve 649*420cc9e8SHugo Villeneuve /* Check if TS input pin is driven to GND, supported by all 650*420cc9e8SHugo Villeneuve * variants. 651*420cc9e8SHugo Villeneuve */ 652*420cc9e8SHugo Villeneuve ret = regmap_read(pcf2127->regmap, 653*420cc9e8SHugo Villeneuve pcf2127->cfg->ts[ts_id].gnd_detect_reg, 654*420cc9e8SHugo Villeneuve &ctrl); 6552f861984SMian Yousaf Kaukab if (ret) 6562f861984SMian Yousaf Kaukab return 0; 65703623b4bSBruno Thomsen 658*420cc9e8SHugo Villeneuve valid_low = ctrl & pcf2127->cfg->ts[ts_id].gnd_detect_bit; 659*420cc9e8SHugo Villeneuve 660*420cc9e8SHugo Villeneuve if (pcf2127->cfg->ts[ts_id].inter_detect_bit) { 661*420cc9e8SHugo Villeneuve /* Check if TS input pin is driven to intermediate level 662*420cc9e8SHugo Villeneuve * between GND and supply, if supported by variant. 663*420cc9e8SHugo Villeneuve */ 664*420cc9e8SHugo Villeneuve ret = regmap_read(pcf2127->regmap, 665*420cc9e8SHugo Villeneuve pcf2127->cfg->ts[ts_id].inter_detect_reg, 666*420cc9e8SHugo Villeneuve &ctrl); 6672f861984SMian Yousaf Kaukab if (ret) 6682f861984SMian Yousaf Kaukab return 0; 6692f861984SMian Yousaf Kaukab 670*420cc9e8SHugo Villeneuve valid_inter = ctrl & pcf2127->cfg->ts[ts_id].inter_detect_bit; 671*420cc9e8SHugo Villeneuve } 672*420cc9e8SHugo Villeneuve 673*420cc9e8SHugo Villeneuve if (!valid_low && !valid_inter) 6742f861984SMian Yousaf Kaukab return 0; 6752f861984SMian Yousaf Kaukab 676*420cc9e8SHugo Villeneuve ret = pcf2127_rtc_ts_read(dev->parent, &ts, ts_id); 6772f861984SMian Yousaf Kaukab if (ret) 6782f861984SMian Yousaf Kaukab return 0; 67903623b4bSBruno Thomsen 68003623b4bSBruno Thomsen ret = pcf2127_wdt_active_ping(&pcf2127->wdd); 68103623b4bSBruno Thomsen if (ret) 68203623b4bSBruno Thomsen return ret; 6832f861984SMian Yousaf Kaukab } 6842f861984SMian Yousaf Kaukab return sprintf(buf, "%llu\n", (unsigned long long)ts); 685*420cc9e8SHugo Villeneuve } 686*420cc9e8SHugo Villeneuve 687*420cc9e8SHugo Villeneuve static ssize_t timestamp0_show(struct device *dev, 688*420cc9e8SHugo Villeneuve struct device_attribute *attr, char *buf) 689*420cc9e8SHugo Villeneuve { 690*420cc9e8SHugo Villeneuve return timestamp_show(dev, attr, buf, 0); 69103623b4bSBruno Thomsen }; 69203623b4bSBruno Thomsen 69303623b4bSBruno Thomsen static DEVICE_ATTR_RW(timestamp0); 69403623b4bSBruno Thomsen 69503623b4bSBruno Thomsen static struct attribute *pcf2127_attrs[] = { 69603623b4bSBruno Thomsen &dev_attr_timestamp0.attr, 69703623b4bSBruno Thomsen NULL 69803623b4bSBruno Thomsen }; 69903623b4bSBruno Thomsen 700fd28ceb4SHugo Villeneuve static struct pcf21xx_config pcf21xx_cfg[] = { 701fd28ceb4SHugo Villeneuve [PCF2127] = { 702fd28ceb4SHugo Villeneuve .type = PCF2127, 703fd28ceb4SHugo Villeneuve .max_register = 0x1d, 704fd28ceb4SHugo Villeneuve .has_nvmem = 1, 705fd28ceb4SHugo Villeneuve .has_bit_wd_ctl_cd0 = 1, 7066211aceeSHugo Villeneuve .reg_time_base = PCF2127_REG_TIME_BASE, 7077c6f0db4SHugo Villeneuve .regs_alarm_base = PCF2127_REG_ALARM_BASE, 7086b57ec29SHugo Villeneuve .reg_wd_ctl = PCF2127_REG_WD_CTL, 7096b57ec29SHugo Villeneuve .reg_wd_val = PCF2127_REG_WD_VAL, 710fc16599eSHugo Villeneuve .reg_clkout = PCF2127_REG_CLKOUT, 711*420cc9e8SHugo Villeneuve .ts_count = 1, 712*420cc9e8SHugo Villeneuve .ts[0] = { 713*420cc9e8SHugo Villeneuve .reg_base = PCF2127_REG_TS1_BASE, 714*420cc9e8SHugo Villeneuve .gnd_detect_reg = PCF2127_REG_CTRL1, 715*420cc9e8SHugo Villeneuve .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 716*420cc9e8SHugo Villeneuve .inter_detect_reg = PCF2127_REG_CTRL2, 717*420cc9e8SHugo Villeneuve .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 718*420cc9e8SHugo Villeneuve .ie_reg = PCF2127_REG_CTRL2, 719*420cc9e8SHugo Villeneuve .ie_bit = PCF2127_BIT_CTRL2_TSIE, 720*420cc9e8SHugo Villeneuve }, 721*420cc9e8SHugo Villeneuve .attribute_group = { 722*420cc9e8SHugo Villeneuve .attrs = pcf2127_attrs, 723*420cc9e8SHugo Villeneuve }, 724fd28ceb4SHugo Villeneuve }, 725fd28ceb4SHugo Villeneuve [PCF2129] = { 726fd28ceb4SHugo Villeneuve .type = PCF2129, 727fd28ceb4SHugo Villeneuve .max_register = 0x19, 728fd28ceb4SHugo Villeneuve .has_nvmem = 0, 729fd28ceb4SHugo Villeneuve .has_bit_wd_ctl_cd0 = 0, 7306211aceeSHugo Villeneuve .reg_time_base = PCF2127_REG_TIME_BASE, 7317c6f0db4SHugo Villeneuve .regs_alarm_base = PCF2127_REG_ALARM_BASE, 7326b57ec29SHugo Villeneuve .reg_wd_ctl = PCF2127_REG_WD_CTL, 7336b57ec29SHugo Villeneuve .reg_wd_val = PCF2127_REG_WD_VAL, 734fc16599eSHugo Villeneuve .reg_clkout = PCF2127_REG_CLKOUT, 735*420cc9e8SHugo Villeneuve .ts_count = 1, 736*420cc9e8SHugo Villeneuve .ts[0] = { 737*420cc9e8SHugo Villeneuve .reg_base = PCF2127_REG_TS1_BASE, 738*420cc9e8SHugo Villeneuve .gnd_detect_reg = PCF2127_REG_CTRL1, 739*420cc9e8SHugo Villeneuve .gnd_detect_bit = PCF2127_BIT_CTRL1_TSF1, 740*420cc9e8SHugo Villeneuve .inter_detect_reg = PCF2127_REG_CTRL2, 741*420cc9e8SHugo Villeneuve .inter_detect_bit = PCF2127_BIT_CTRL2_TSF2, 742*420cc9e8SHugo Villeneuve .ie_reg = PCF2127_REG_CTRL2, 743*420cc9e8SHugo Villeneuve .ie_bit = PCF2127_BIT_CTRL2_TSIE, 744*420cc9e8SHugo Villeneuve }, 745*420cc9e8SHugo Villeneuve .attribute_group = { 746*420cc9e8SHugo Villeneuve .attrs = pcf2127_attrs, 747*420cc9e8SHugo Villeneuve }, 748fd28ceb4SHugo Villeneuve }, 749fd28ceb4SHugo Villeneuve }; 750fd28ceb4SHugo Villeneuve 751*420cc9e8SHugo Villeneuve /* 752*420cc9e8SHugo Villeneuve * Enable timestamp function and corresponding interrupt(s). 753*420cc9e8SHugo Villeneuve */ 754*420cc9e8SHugo Villeneuve static int pcf2127_enable_ts(struct device *dev, int ts_id) 755*420cc9e8SHugo Villeneuve { 756*420cc9e8SHugo Villeneuve struct pcf2127 *pcf2127 = dev_get_drvdata(dev); 757*420cc9e8SHugo Villeneuve int ret; 758*420cc9e8SHugo Villeneuve 759*420cc9e8SHugo Villeneuve if (ts_id >= pcf2127->cfg->ts_count) { 760*420cc9e8SHugo Villeneuve dev_err(dev, "%s: invalid tamper detection ID (%d)\n", 761*420cc9e8SHugo Villeneuve __func__, ts_id); 762*420cc9e8SHugo Villeneuve return -EINVAL; 763*420cc9e8SHugo Villeneuve } 764*420cc9e8SHugo Villeneuve 765*420cc9e8SHugo Villeneuve /* Enable timestamp function. */ 766*420cc9e8SHugo Villeneuve ret = regmap_update_bits(pcf2127->regmap, 767*420cc9e8SHugo Villeneuve pcf2127->cfg->ts[ts_id].reg_base, 768*420cc9e8SHugo Villeneuve PCF2127_BIT_TS_CTRL_TSOFF | 769*420cc9e8SHugo Villeneuve PCF2127_BIT_TS_CTRL_TSM, 770*420cc9e8SHugo Villeneuve PCF2127_BIT_TS_CTRL_TSM); 771*420cc9e8SHugo Villeneuve if (ret) { 772*420cc9e8SHugo Villeneuve dev_err(dev, "%s: tamper detection config (ts%d_ctrl) failed\n", 773*420cc9e8SHugo Villeneuve __func__, ts_id); 774*420cc9e8SHugo Villeneuve return ret; 775*420cc9e8SHugo Villeneuve } 776*420cc9e8SHugo Villeneuve 777*420cc9e8SHugo Villeneuve /* TS input pin driven to GND detection is supported by all variants. 778*420cc9e8SHugo Villeneuve * Make sure that interrupt bit is defined. 779*420cc9e8SHugo Villeneuve */ 780*420cc9e8SHugo Villeneuve if (pcf2127->cfg->ts[ts_id].gnd_detect_bit == 0) { 781*420cc9e8SHugo Villeneuve dev_err(dev, "%s: tamper detection to GND configuration invalid\n", 782*420cc9e8SHugo Villeneuve __func__); 783*420cc9e8SHugo Villeneuve return ret; 784*420cc9e8SHugo Villeneuve } 785*420cc9e8SHugo Villeneuve 786*420cc9e8SHugo Villeneuve /* 787*420cc9e8SHugo Villeneuve * Enable interrupt generation when TSF timestamp flag is set. 788*420cc9e8SHugo Villeneuve * Interrupt signals are open-drain outputs and can be left floating if 789*420cc9e8SHugo Villeneuve * unused. 790*420cc9e8SHugo Villeneuve */ 791*420cc9e8SHugo Villeneuve ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->ts[ts_id].ie_reg, 792*420cc9e8SHugo Villeneuve pcf2127->cfg->ts[ts_id].ie_bit, 793*420cc9e8SHugo Villeneuve pcf2127->cfg->ts[ts_id].ie_bit); 794*420cc9e8SHugo Villeneuve if (ret) { 795*420cc9e8SHugo Villeneuve dev_err(dev, "%s: tamper detection TSIE%d config failed\n", 796*420cc9e8SHugo Villeneuve __func__, ts_id); 797*420cc9e8SHugo Villeneuve return ret; 798*420cc9e8SHugo Villeneuve } 799*420cc9e8SHugo Villeneuve 800*420cc9e8SHugo Villeneuve return ret; 801*420cc9e8SHugo Villeneuve } 802*420cc9e8SHugo Villeneuve 803907b3262SAkinobu Mita static int pcf2127_probe(struct device *dev, struct regmap *regmap, 804fd28ceb4SHugo Villeneuve int alarm_irq, const char *name, const struct pcf21xx_config *config) 80518cb6368SRenaud Cerrato { 80618cb6368SRenaud Cerrato struct pcf2127 *pcf2127; 807d6c3029fSUwe Kleine-König int ret = 0; 80815f57b3eSPhilipp Rosenberger unsigned int val; 80918cb6368SRenaud Cerrato 810907b3262SAkinobu Mita dev_dbg(dev, "%s\n", __func__); 81118cb6368SRenaud Cerrato 812907b3262SAkinobu Mita pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL); 81318cb6368SRenaud Cerrato if (!pcf2127) 81418cb6368SRenaud Cerrato return -ENOMEM; 81518cb6368SRenaud Cerrato 816907b3262SAkinobu Mita pcf2127->regmap = regmap; 817fd28ceb4SHugo Villeneuve pcf2127->cfg = config; 81818cb6368SRenaud Cerrato 819907b3262SAkinobu Mita dev_set_drvdata(dev, pcf2127); 820907b3262SAkinobu Mita 821e788771cSBruno Thomsen pcf2127->rtc = devm_rtc_allocate_device(dev); 822d6c3029fSUwe Kleine-König if (IS_ERR(pcf2127->rtc)) 823d6c3029fSUwe Kleine-König return PTR_ERR(pcf2127->rtc); 82418cb6368SRenaud Cerrato 825e788771cSBruno Thomsen pcf2127->rtc->ops = &pcf2127_rtc_ops; 826b139bb5cSAlexandre Belloni pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; 827b139bb5cSAlexandre Belloni pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099; 828b139bb5cSAlexandre Belloni pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */ 829bda10273SAlexandre Belloni set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features); 830689fafd5SAlexandre Belloni clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features); 83125cbe9c8SAlexandre Belloni clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 832e788771cSBruno Thomsen 83335425bafSBiwen Li if (alarm_irq > 0) { 834d4785b46SHugo Villeneuve unsigned long flags; 835d4785b46SHugo Villeneuve 836d4785b46SHugo Villeneuve /* 837d4785b46SHugo Villeneuve * If flags = 0, devm_request_threaded_irq() will use IRQ flags 838d4785b46SHugo Villeneuve * obtained from device tree. 839d4785b46SHugo Villeneuve */ 840d4785b46SHugo Villeneuve if (dev_fwnode(dev)) 841d4785b46SHugo Villeneuve flags = 0; 842d4785b46SHugo Villeneuve else 843d4785b46SHugo Villeneuve flags = IRQF_TRIGGER_LOW; 844d4785b46SHugo Villeneuve 84527006416SAlexandre Belloni ret = devm_request_threaded_irq(dev, alarm_irq, NULL, 84627006416SAlexandre Belloni pcf2127_rtc_irq, 847d4785b46SHugo Villeneuve flags | IRQF_ONESHOT, 8488a914bacSLiam Beguin dev_name(dev), dev); 8498a914bacSLiam Beguin if (ret) { 8508a914bacSLiam Beguin dev_err(dev, "failed to request alarm irq\n"); 8518a914bacSLiam Beguin return ret; 8528a914bacSLiam Beguin } 8532f861984SMian Yousaf Kaukab pcf2127->irq_enabled = true; 8548a914bacSLiam Beguin } 8558a914bacSLiam Beguin 85635425bafSBiwen Li if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) { 8578a914bacSLiam Beguin device_init_wakeup(dev, true); 85825cbe9c8SAlexandre Belloni set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features); 8598a914bacSLiam Beguin } 8608a914bacSLiam Beguin 861fd28ceb4SHugo Villeneuve if (pcf2127->cfg->has_nvmem) { 862d6c3029fSUwe Kleine-König struct nvmem_config nvmem_cfg = { 863d6c3029fSUwe Kleine-König .priv = pcf2127, 864d6c3029fSUwe Kleine-König .reg_read = pcf2127_nvmem_read, 865d6c3029fSUwe Kleine-König .reg_write = pcf2127_nvmem_write, 866d6c3029fSUwe Kleine-König .size = 512, 867d6c3029fSUwe Kleine-König }; 868d6c3029fSUwe Kleine-König 8693a905c2dSBartosz Golaszewski ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg); 870d6c3029fSUwe Kleine-König } 871d6c3029fSUwe Kleine-König 8720e735eaaSBruno Thomsen /* 873b9ac079aSPhilipp Rosenberger * The "Power-On Reset Override" facility prevents the RTC to do a reset 874b9ac079aSPhilipp Rosenberger * after power on. For normal operation the PORO must be disabled. 875b9ac079aSPhilipp Rosenberger */ 876b9ac079aSPhilipp Rosenberger regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, 877b9ac079aSPhilipp Rosenberger PCF2127_BIT_CTRL1_POR_OVRD); 878b9ac079aSPhilipp Rosenberger 879fc16599eSHugo Villeneuve ret = regmap_read(pcf2127->regmap, pcf2127->cfg->reg_clkout, &val); 88015f57b3eSPhilipp Rosenberger if (ret < 0) 88115f57b3eSPhilipp Rosenberger return ret; 88215f57b3eSPhilipp Rosenberger 88315f57b3eSPhilipp Rosenberger if (!(val & PCF2127_BIT_CLKOUT_OTPR)) { 884fc16599eSHugo Villeneuve ret = regmap_set_bits(pcf2127->regmap, pcf2127->cfg->reg_clkout, 88515f57b3eSPhilipp Rosenberger PCF2127_BIT_CLKOUT_OTPR); 88615f57b3eSPhilipp Rosenberger if (ret < 0) 88715f57b3eSPhilipp Rosenberger return ret; 88815f57b3eSPhilipp Rosenberger 88915f57b3eSPhilipp Rosenberger msleep(100); 89015f57b3eSPhilipp Rosenberger } 89115f57b3eSPhilipp Rosenberger 892b9ac079aSPhilipp Rosenberger /* 8930e735eaaSBruno Thomsen * Watchdog timer enabled and reset pin /RST activated when timed out. 8940e735eaaSBruno Thomsen * Select 1Hz clock source for watchdog timer. 8950e735eaaSBruno Thomsen * Note: Countdown timer disabled and not available. 8962843d565SBiwen Li * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD 8972843d565SBiwen Li * of register watchdg_tim_ctl. The bit[6] is labeled 8982843d565SBiwen Li * as T. Bits labeled as T must always be written with 8992843d565SBiwen Li * logic 0. 9000e735eaaSBruno Thomsen */ 9016b57ec29SHugo Villeneuve ret = regmap_update_bits(pcf2127->regmap, pcf2127->cfg->reg_wd_ctl, 9020e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_CD1 | 9030e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_CD0 | 9040e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_TF1 | 9050e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_TF0, 9060e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_CD1 | 907fd28ceb4SHugo Villeneuve (pcf2127->cfg->has_bit_wd_ctl_cd0 ? PCF2127_BIT_WD_CTL_CD0 : 0) | 9080e735eaaSBruno Thomsen PCF2127_BIT_WD_CTL_TF1); 9090e735eaaSBruno Thomsen if (ret) { 9100e735eaaSBruno Thomsen dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__); 9110e735eaaSBruno Thomsen return ret; 9120e735eaaSBruno Thomsen } 9130e735eaaSBruno Thomsen 9145d78533aSUwe Kleine-König pcf2127_watchdog_init(dev, pcf2127); 9150e735eaaSBruno Thomsen 91603623b4bSBruno Thomsen /* 91703623b4bSBruno Thomsen * Disable battery low/switch-over timestamp and interrupts. 91803623b4bSBruno Thomsen * Clear battery interrupt flags which can block new trigger events. 91903623b4bSBruno Thomsen * Note: This is the default chip behaviour but added to ensure 92003623b4bSBruno Thomsen * correct tamper timestamp and interrupt function. 92103623b4bSBruno Thomsen */ 92203623b4bSBruno Thomsen ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3, 92303623b4bSBruno Thomsen PCF2127_BIT_CTRL3_BTSE | 92403623b4bSBruno Thomsen PCF2127_BIT_CTRL3_BIE | 92503623b4bSBruno Thomsen PCF2127_BIT_CTRL3_BLIE, 0); 92603623b4bSBruno Thomsen if (ret) { 92703623b4bSBruno Thomsen dev_err(dev, "%s: interrupt config (ctrl3) failed\n", 92803623b4bSBruno Thomsen __func__); 92903623b4bSBruno Thomsen return ret; 93003623b4bSBruno Thomsen } 93103623b4bSBruno Thomsen 93203623b4bSBruno Thomsen /* 933*420cc9e8SHugo Villeneuve * Enable timestamp functions 1 to 4. 93403623b4bSBruno Thomsen */ 935*420cc9e8SHugo Villeneuve for (int i = 0; i < pcf2127->cfg->ts_count; i++) { 936*420cc9e8SHugo Villeneuve ret = pcf2127_enable_ts(dev, i); 937*420cc9e8SHugo Villeneuve if (ret) 93803623b4bSBruno Thomsen return ret; 93903623b4bSBruno Thomsen } 94003623b4bSBruno Thomsen 941*420cc9e8SHugo Villeneuve ret = rtc_add_group(pcf2127->rtc, &pcf2127->cfg->attribute_group); 94203623b4bSBruno Thomsen if (ret) { 94303623b4bSBruno Thomsen dev_err(dev, "%s: tamper sysfs registering failed\n", 94403623b4bSBruno Thomsen __func__); 94503623b4bSBruno Thomsen return ret; 94603623b4bSBruno Thomsen } 94703623b4bSBruno Thomsen 948fdcfd854SBartosz Golaszewski return devm_rtc_register_device(pcf2127->rtc); 94918cb6368SRenaud Cerrato } 95018cb6368SRenaud Cerrato 95118cb6368SRenaud Cerrato #ifdef CONFIG_OF 95218cb6368SRenaud Cerrato static const struct of_device_id pcf2127_of_match[] = { 953fd28ceb4SHugo Villeneuve { .compatible = "nxp,pcf2127", .data = &pcf21xx_cfg[PCF2127] }, 954fd28ceb4SHugo Villeneuve { .compatible = "nxp,pcf2129", .data = &pcf21xx_cfg[PCF2129] }, 955fd28ceb4SHugo Villeneuve { .compatible = "nxp,pca2129", .data = &pcf21xx_cfg[PCF2129] }, 95618cb6368SRenaud Cerrato {} 95718cb6368SRenaud Cerrato }; 95818cb6368SRenaud Cerrato MODULE_DEVICE_TABLE(of, pcf2127_of_match); 95918cb6368SRenaud Cerrato #endif 96018cb6368SRenaud Cerrato 9619408ec1aSAkinobu Mita #if IS_ENABLED(CONFIG_I2C) 9629408ec1aSAkinobu Mita 963907b3262SAkinobu Mita static int pcf2127_i2c_write(void *context, const void *data, size_t count) 964907b3262SAkinobu Mita { 965907b3262SAkinobu Mita struct device *dev = context; 966907b3262SAkinobu Mita struct i2c_client *client = to_i2c_client(dev); 967907b3262SAkinobu Mita int ret; 968907b3262SAkinobu Mita 969907b3262SAkinobu Mita ret = i2c_master_send(client, data, count); 970907b3262SAkinobu Mita if (ret != count) 971907b3262SAkinobu Mita return ret < 0 ? ret : -EIO; 972907b3262SAkinobu Mita 973907b3262SAkinobu Mita return 0; 974907b3262SAkinobu Mita } 975907b3262SAkinobu Mita 976907b3262SAkinobu Mita static int pcf2127_i2c_gather_write(void *context, 977907b3262SAkinobu Mita const void *reg, size_t reg_size, 978907b3262SAkinobu Mita const void *val, size_t val_size) 979907b3262SAkinobu Mita { 980907b3262SAkinobu Mita struct device *dev = context; 981907b3262SAkinobu Mita struct i2c_client *client = to_i2c_client(dev); 982907b3262SAkinobu Mita int ret; 983907b3262SAkinobu Mita void *buf; 984907b3262SAkinobu Mita 985907b3262SAkinobu Mita if (WARN_ON(reg_size != 1)) 986907b3262SAkinobu Mita return -EINVAL; 987907b3262SAkinobu Mita 988907b3262SAkinobu Mita buf = kmalloc(val_size + 1, GFP_KERNEL); 989907b3262SAkinobu Mita if (!buf) 990907b3262SAkinobu Mita return -ENOMEM; 991907b3262SAkinobu Mita 992907b3262SAkinobu Mita memcpy(buf, reg, 1); 993907b3262SAkinobu Mita memcpy(buf + 1, val, val_size); 994907b3262SAkinobu Mita 995907b3262SAkinobu Mita ret = i2c_master_send(client, buf, val_size + 1); 9969bde0afbSXulin Sun 9979bde0afbSXulin Sun kfree(buf); 9989bde0afbSXulin Sun 999907b3262SAkinobu Mita if (ret != val_size + 1) 1000907b3262SAkinobu Mita return ret < 0 ? ret : -EIO; 1001907b3262SAkinobu Mita 1002907b3262SAkinobu Mita return 0; 1003907b3262SAkinobu Mita } 1004907b3262SAkinobu Mita 1005907b3262SAkinobu Mita static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size, 1006907b3262SAkinobu Mita void *val, size_t val_size) 1007907b3262SAkinobu Mita { 1008907b3262SAkinobu Mita struct device *dev = context; 1009907b3262SAkinobu Mita struct i2c_client *client = to_i2c_client(dev); 1010907b3262SAkinobu Mita int ret; 1011907b3262SAkinobu Mita 1012907b3262SAkinobu Mita if (WARN_ON(reg_size != 1)) 1013907b3262SAkinobu Mita return -EINVAL; 1014907b3262SAkinobu Mita 1015907b3262SAkinobu Mita ret = i2c_master_send(client, reg, 1); 1016907b3262SAkinobu Mita if (ret != 1) 1017907b3262SAkinobu Mita return ret < 0 ? ret : -EIO; 1018907b3262SAkinobu Mita 1019907b3262SAkinobu Mita ret = i2c_master_recv(client, val, val_size); 1020907b3262SAkinobu Mita if (ret != val_size) 1021907b3262SAkinobu Mita return ret < 0 ? ret : -EIO; 1022907b3262SAkinobu Mita 1023907b3262SAkinobu Mita return 0; 1024907b3262SAkinobu Mita } 1025907b3262SAkinobu Mita 1026907b3262SAkinobu Mita /* 1027907b3262SAkinobu Mita * The reason we need this custom regmap_bus instead of using regmap_init_i2c() 1028907b3262SAkinobu Mita * is that the STOP condition is required between set register address and 1029907b3262SAkinobu Mita * read register data when reading from registers. 1030907b3262SAkinobu Mita */ 1031907b3262SAkinobu Mita static const struct regmap_bus pcf2127_i2c_regmap = { 1032907b3262SAkinobu Mita .write = pcf2127_i2c_write, 1033907b3262SAkinobu Mita .gather_write = pcf2127_i2c_gather_write, 1034907b3262SAkinobu Mita .read = pcf2127_i2c_read, 103518cb6368SRenaud Cerrato }; 103618cb6368SRenaud Cerrato 1037907b3262SAkinobu Mita static struct i2c_driver pcf2127_i2c_driver; 1038907b3262SAkinobu Mita 10395418e595SUwe Kleine-König static const struct i2c_device_id pcf2127_i2c_id[] = { 1040fd28ceb4SHugo Villeneuve { "pcf2127", PCF2127 }, 1041fd28ceb4SHugo Villeneuve { "pcf2129", PCF2129 }, 1042fd28ceb4SHugo Villeneuve { "pca2129", PCF2129 }, 10435418e595SUwe Kleine-König { } 10445418e595SUwe Kleine-König }; 10455418e595SUwe Kleine-König MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id); 10465418e595SUwe Kleine-König 10475418e595SUwe Kleine-König static int pcf2127_i2c_probe(struct i2c_client *client) 1048907b3262SAkinobu Mita { 1049907b3262SAkinobu Mita struct regmap *regmap; 1050fd28ceb4SHugo Villeneuve static struct regmap_config config = { 1051907b3262SAkinobu Mita .reg_bits = 8, 1052907b3262SAkinobu Mita .val_bits = 8, 1053907b3262SAkinobu Mita }; 1054fd28ceb4SHugo Villeneuve const struct pcf21xx_config *variant; 1055907b3262SAkinobu Mita 1056907b3262SAkinobu Mita if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 1057907b3262SAkinobu Mita return -ENODEV; 1058907b3262SAkinobu Mita 1059fd28ceb4SHugo Villeneuve if (client->dev.of_node) { 1060fd28ceb4SHugo Villeneuve variant = of_device_get_match_data(&client->dev); 1061fd28ceb4SHugo Villeneuve if (!variant) 1062fd28ceb4SHugo Villeneuve return -ENODEV; 1063fd28ceb4SHugo Villeneuve } else { 1064fd28ceb4SHugo Villeneuve enum pcf21xx_type type = 1065fd28ceb4SHugo Villeneuve i2c_match_id(pcf2127_i2c_id, client)->driver_data; 1066fd28ceb4SHugo Villeneuve 1067fd28ceb4SHugo Villeneuve if (type >= PCF21XX_LAST_ID) 1068fd28ceb4SHugo Villeneuve return -ENODEV; 1069fd28ceb4SHugo Villeneuve variant = &pcf21xx_cfg[type]; 1070fd28ceb4SHugo Villeneuve } 1071fd28ceb4SHugo Villeneuve 1072fd28ceb4SHugo Villeneuve config.max_register = variant->max_register, 1073fd28ceb4SHugo Villeneuve 1074907b3262SAkinobu Mita regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap, 1075907b3262SAkinobu Mita &client->dev, &config); 1076907b3262SAkinobu Mita if (IS_ERR(regmap)) { 1077907b3262SAkinobu Mita dev_err(&client->dev, "%s: regmap allocation failed: %ld\n", 1078907b3262SAkinobu Mita __func__, PTR_ERR(regmap)); 1079907b3262SAkinobu Mita return PTR_ERR(regmap); 1080907b3262SAkinobu Mita } 1081907b3262SAkinobu Mita 108227006416SAlexandre Belloni return pcf2127_probe(&client->dev, regmap, client->irq, 1083fd28ceb4SHugo Villeneuve pcf2127_i2c_driver.driver.name, variant); 1084907b3262SAkinobu Mita } 1085907b3262SAkinobu Mita 1086907b3262SAkinobu Mita static struct i2c_driver pcf2127_i2c_driver = { 1087907b3262SAkinobu Mita .driver = { 1088907b3262SAkinobu Mita .name = "rtc-pcf2127-i2c", 1089907b3262SAkinobu Mita .of_match_table = of_match_ptr(pcf2127_of_match), 1090907b3262SAkinobu Mita }, 109131b0cecbSUwe Kleine-König .probe = pcf2127_i2c_probe, 1092907b3262SAkinobu Mita .id_table = pcf2127_i2c_id, 1093907b3262SAkinobu Mita }; 10949408ec1aSAkinobu Mita 10959408ec1aSAkinobu Mita static int pcf2127_i2c_register_driver(void) 10969408ec1aSAkinobu Mita { 10979408ec1aSAkinobu Mita return i2c_add_driver(&pcf2127_i2c_driver); 10989408ec1aSAkinobu Mita } 10999408ec1aSAkinobu Mita 11009408ec1aSAkinobu Mita static void pcf2127_i2c_unregister_driver(void) 11019408ec1aSAkinobu Mita { 11029408ec1aSAkinobu Mita i2c_del_driver(&pcf2127_i2c_driver); 11039408ec1aSAkinobu Mita } 11049408ec1aSAkinobu Mita 11059408ec1aSAkinobu Mita #else 11069408ec1aSAkinobu Mita 11079408ec1aSAkinobu Mita static int pcf2127_i2c_register_driver(void) 11089408ec1aSAkinobu Mita { 11099408ec1aSAkinobu Mita return 0; 11109408ec1aSAkinobu Mita } 11119408ec1aSAkinobu Mita 11129408ec1aSAkinobu Mita static void pcf2127_i2c_unregister_driver(void) 11139408ec1aSAkinobu Mita { 11149408ec1aSAkinobu Mita } 11159408ec1aSAkinobu Mita 11169408ec1aSAkinobu Mita #endif 11179408ec1aSAkinobu Mita 11189408ec1aSAkinobu Mita #if IS_ENABLED(CONFIG_SPI_MASTER) 11199408ec1aSAkinobu Mita 11209408ec1aSAkinobu Mita static struct spi_driver pcf2127_spi_driver; 1121fd28ceb4SHugo Villeneuve static const struct spi_device_id pcf2127_spi_id[]; 11229408ec1aSAkinobu Mita 11239408ec1aSAkinobu Mita static int pcf2127_spi_probe(struct spi_device *spi) 11249408ec1aSAkinobu Mita { 1125fd28ceb4SHugo Villeneuve static struct regmap_config config = { 11269408ec1aSAkinobu Mita .reg_bits = 8, 11279408ec1aSAkinobu Mita .val_bits = 8, 11289408ec1aSAkinobu Mita .read_flag_mask = 0xa0, 11299408ec1aSAkinobu Mita .write_flag_mask = 0x20, 11309408ec1aSAkinobu Mita }; 11319408ec1aSAkinobu Mita struct regmap *regmap; 1132fd28ceb4SHugo Villeneuve const struct pcf21xx_config *variant; 1133fd28ceb4SHugo Villeneuve 1134fd28ceb4SHugo Villeneuve if (spi->dev.of_node) { 1135fd28ceb4SHugo Villeneuve variant = of_device_get_match_data(&spi->dev); 1136fd28ceb4SHugo Villeneuve if (!variant) 1137fd28ceb4SHugo Villeneuve return -ENODEV; 1138fd28ceb4SHugo Villeneuve } else { 1139fd28ceb4SHugo Villeneuve enum pcf21xx_type type = spi_get_device_id(spi)->driver_data; 1140fd28ceb4SHugo Villeneuve 1141fd28ceb4SHugo Villeneuve if (type >= PCF21XX_LAST_ID) 1142fd28ceb4SHugo Villeneuve return -ENODEV; 1143fd28ceb4SHugo Villeneuve variant = &pcf21xx_cfg[type]; 1144fd28ceb4SHugo Villeneuve } 1145fd28ceb4SHugo Villeneuve 1146fd28ceb4SHugo Villeneuve config.max_register = variant->max_register, 11479408ec1aSAkinobu Mita 11489408ec1aSAkinobu Mita regmap = devm_regmap_init_spi(spi, &config); 11499408ec1aSAkinobu Mita if (IS_ERR(regmap)) { 11509408ec1aSAkinobu Mita dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n", 11519408ec1aSAkinobu Mita __func__, PTR_ERR(regmap)); 11529408ec1aSAkinobu Mita return PTR_ERR(regmap); 11539408ec1aSAkinobu Mita } 11549408ec1aSAkinobu Mita 115527006416SAlexandre Belloni return pcf2127_probe(&spi->dev, regmap, spi->irq, 115627006416SAlexandre Belloni pcf2127_spi_driver.driver.name, 1157fd28ceb4SHugo Villeneuve variant); 11589408ec1aSAkinobu Mita } 11599408ec1aSAkinobu Mita 11609408ec1aSAkinobu Mita static const struct spi_device_id pcf2127_spi_id[] = { 1161fd28ceb4SHugo Villeneuve { "pcf2127", PCF2127 }, 1162fd28ceb4SHugo Villeneuve { "pcf2129", PCF2129 }, 1163fd28ceb4SHugo Villeneuve { "pca2129", PCF2129 }, 11649408ec1aSAkinobu Mita { } 11659408ec1aSAkinobu Mita }; 11669408ec1aSAkinobu Mita MODULE_DEVICE_TABLE(spi, pcf2127_spi_id); 11679408ec1aSAkinobu Mita 11689408ec1aSAkinobu Mita static struct spi_driver pcf2127_spi_driver = { 11699408ec1aSAkinobu Mita .driver = { 11709408ec1aSAkinobu Mita .name = "rtc-pcf2127-spi", 11719408ec1aSAkinobu Mita .of_match_table = of_match_ptr(pcf2127_of_match), 11729408ec1aSAkinobu Mita }, 11739408ec1aSAkinobu Mita .probe = pcf2127_spi_probe, 11749408ec1aSAkinobu Mita .id_table = pcf2127_spi_id, 11759408ec1aSAkinobu Mita }; 11769408ec1aSAkinobu Mita 11779408ec1aSAkinobu Mita static int pcf2127_spi_register_driver(void) 11789408ec1aSAkinobu Mita { 11799408ec1aSAkinobu Mita return spi_register_driver(&pcf2127_spi_driver); 11809408ec1aSAkinobu Mita } 11819408ec1aSAkinobu Mita 11829408ec1aSAkinobu Mita static void pcf2127_spi_unregister_driver(void) 11839408ec1aSAkinobu Mita { 11849408ec1aSAkinobu Mita spi_unregister_driver(&pcf2127_spi_driver); 11859408ec1aSAkinobu Mita } 11869408ec1aSAkinobu Mita 11879408ec1aSAkinobu Mita #else 11889408ec1aSAkinobu Mita 11899408ec1aSAkinobu Mita static int pcf2127_spi_register_driver(void) 11909408ec1aSAkinobu Mita { 11919408ec1aSAkinobu Mita return 0; 11929408ec1aSAkinobu Mita } 11939408ec1aSAkinobu Mita 11949408ec1aSAkinobu Mita static void pcf2127_spi_unregister_driver(void) 11959408ec1aSAkinobu Mita { 11969408ec1aSAkinobu Mita } 11979408ec1aSAkinobu Mita 11989408ec1aSAkinobu Mita #endif 11999408ec1aSAkinobu Mita 12009408ec1aSAkinobu Mita static int __init pcf2127_init(void) 12019408ec1aSAkinobu Mita { 12029408ec1aSAkinobu Mita int ret; 12039408ec1aSAkinobu Mita 12049408ec1aSAkinobu Mita ret = pcf2127_i2c_register_driver(); 12059408ec1aSAkinobu Mita if (ret) { 12069408ec1aSAkinobu Mita pr_err("Failed to register pcf2127 i2c driver: %d\n", ret); 12079408ec1aSAkinobu Mita return ret; 12089408ec1aSAkinobu Mita } 12099408ec1aSAkinobu Mita 12109408ec1aSAkinobu Mita ret = pcf2127_spi_register_driver(); 12119408ec1aSAkinobu Mita if (ret) { 12129408ec1aSAkinobu Mita pr_err("Failed to register pcf2127 spi driver: %d\n", ret); 12139408ec1aSAkinobu Mita pcf2127_i2c_unregister_driver(); 12149408ec1aSAkinobu Mita } 12159408ec1aSAkinobu Mita 12169408ec1aSAkinobu Mita return ret; 12179408ec1aSAkinobu Mita } 12189408ec1aSAkinobu Mita module_init(pcf2127_init) 12199408ec1aSAkinobu Mita 12209408ec1aSAkinobu Mita static void __exit pcf2127_exit(void) 12219408ec1aSAkinobu Mita { 12229408ec1aSAkinobu Mita pcf2127_spi_unregister_driver(); 12239408ec1aSAkinobu Mita pcf2127_i2c_unregister_driver(); 12249408ec1aSAkinobu Mita } 12259408ec1aSAkinobu Mita module_exit(pcf2127_exit) 122618cb6368SRenaud Cerrato 122718cb6368SRenaud Cerrato MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>"); 1228cee2cc21SAkinobu Mita MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver"); 12294d8318bcSUwe Kleine-König MODULE_LICENSE("GPL v2"); 1230