1 /* 2 * An SPI driver for the Philips PCF2123 RTC 3 * Copyright 2009 Cyber Switching, Inc. 4 * 5 * Author: Chris Verges <chrisv@cyberswitching.com> 6 * Maintainers: http://www.cyberswitching.com 7 * 8 * based on the RS5C348 driver in this same directory. 9 * 10 * Thanks to Christian Pellegrin <chripell@fsfe.org> for 11 * the sysfs contributions to this driver. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 * 17 * Please note that the CS is active high, so platform data 18 * should look something like: 19 * 20 * static struct spi_board_info ek_spi_devices[] = { 21 * ... 22 * { 23 * .modalias = "rtc-pcf2123", 24 * .chip_select = 1, 25 * .controller_data = (void *)AT91_PIN_PA10, 26 * .max_speed_hz = 1000 * 1000, 27 * .mode = SPI_CS_HIGH, 28 * .bus_num = 0, 29 * }, 30 * ... 31 *}; 32 * 33 */ 34 35 #include <linux/bcd.h> 36 #include <linux/delay.h> 37 #include <linux/device.h> 38 #include <linux/errno.h> 39 #include <linux/init.h> 40 #include <linux/kernel.h> 41 #include <linux/of.h> 42 #include <linux/string.h> 43 #include <linux/slab.h> 44 #include <linux/rtc.h> 45 #include <linux/spi/spi.h> 46 #include <linux/module.h> 47 #include <linux/sysfs.h> 48 49 /* REGISTERS */ 50 #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ 51 #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ 52 #define PCF2123_REG_SC (0x02) /* datetime */ 53 #define PCF2123_REG_MN (0x03) 54 #define PCF2123_REG_HR (0x04) 55 #define PCF2123_REG_DM (0x05) 56 #define PCF2123_REG_DW (0x06) 57 #define PCF2123_REG_MO (0x07) 58 #define PCF2123_REG_YR (0x08) 59 #define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ 60 #define PCF2123_REG_ALRM_HR (0x0a) 61 #define PCF2123_REG_ALRM_DM (0x0b) 62 #define PCF2123_REG_ALRM_DW (0x0c) 63 #define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ 64 #define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ 65 #define PCF2123_REG_CTDWN_TMR (0x0f) 66 67 /* PCF2123_REG_CTRL1 BITS */ 68 #define CTRL1_CLEAR (0) /* Clear */ 69 #define CTRL1_CORR_INT BIT(1) /* Correction irq enable */ 70 #define CTRL1_12_HOUR BIT(2) /* 12 hour time */ 71 #define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */ 72 #define CTRL1_STOP BIT(5) /* Stop the clock */ 73 #define CTRL1_EXT_TEST BIT(7) /* External clock test mode */ 74 75 /* PCF2123_REG_CTRL2 BITS */ 76 #define CTRL2_TIE BIT(0) /* Countdown timer irq enable */ 77 #define CTRL2_AIE BIT(1) /* Alarm irq enable */ 78 #define CTRL2_TF BIT(2) /* Countdown timer flag */ 79 #define CTRL2_AF BIT(3) /* Alarm flag */ 80 #define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */ 81 #define CTRL2_MSF BIT(5) /* Minute or second irq flag */ 82 #define CTRL2_SI BIT(6) /* Second irq enable */ 83 #define CTRL2_MI BIT(7) /* Minute irq enable */ 84 85 /* PCF2123_REG_SC BITS */ 86 #define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */ 87 88 /* PCF2123_REG_ALRM_XX BITS */ 89 #define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */ 90 91 /* PCF2123_REG_TMR_CLKOUT BITS */ 92 #define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */ 93 #define CD_TMR_64HZ (1) /* 64 Hz countdown timer */ 94 #define CD_TMR_1HZ (2) /* 1 Hz countdown timer */ 95 #define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */ 96 #define CD_TMR_TE BIT(3) /* Countdown timer enable */ 97 98 /* PCF2123_REG_OFFSET BITS */ 99 #define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */ 100 #define OFFSET_COARSE BIT(7) /* Coarse mode offset */ 101 #define OFFSET_STEP (2170) /* Offset step in parts per billion */ 102 103 /* READ/WRITE ADDRESS BITS */ 104 #define PCF2123_WRITE BIT(4) 105 #define PCF2123_READ (BIT(4) | BIT(7)) 106 107 108 static struct spi_driver pcf2123_driver; 109 110 struct pcf2123_sysfs_reg { 111 struct device_attribute attr; 112 char name[2]; 113 }; 114 115 struct pcf2123_plat_data { 116 struct rtc_device *rtc; 117 struct pcf2123_sysfs_reg regs[16]; 118 }; 119 120 /* 121 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select 122 * is released properly after an SPI write. This function should be 123 * called after EVERY read/write call over SPI. 124 */ 125 static inline void pcf2123_delay_trec(void) 126 { 127 ndelay(30); 128 } 129 130 static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size) 131 { 132 struct spi_device *spi = to_spi_device(dev); 133 int ret; 134 135 reg |= PCF2123_READ; 136 ret = spi_write_then_read(spi, ®, 1, rxbuf, size); 137 pcf2123_delay_trec(); 138 139 return ret; 140 } 141 142 static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size) 143 { 144 struct spi_device *spi = to_spi_device(dev); 145 int ret; 146 147 txbuf[0] |= PCF2123_WRITE; 148 ret = spi_write(spi, txbuf, size); 149 pcf2123_delay_trec(); 150 151 return ret; 152 } 153 154 static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val) 155 { 156 u8 txbuf[2]; 157 158 txbuf[0] = reg; 159 txbuf[1] = val; 160 return pcf2123_write(dev, txbuf, sizeof(txbuf)); 161 } 162 163 static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr, 164 char *buffer) 165 { 166 struct pcf2123_sysfs_reg *r; 167 u8 rxbuf[1]; 168 unsigned long reg; 169 int ret; 170 171 r = container_of(attr, struct pcf2123_sysfs_reg, attr); 172 173 ret = kstrtoul(r->name, 16, ®); 174 if (ret) 175 return ret; 176 177 ret = pcf2123_read(dev, reg, rxbuf, 1); 178 if (ret < 0) 179 return -EIO; 180 181 return sprintf(buffer, "0x%x\n", rxbuf[0]); 182 } 183 184 static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr, 185 const char *buffer, size_t count) { 186 struct pcf2123_sysfs_reg *r; 187 unsigned long reg; 188 unsigned long val; 189 190 int ret; 191 192 r = container_of(attr, struct pcf2123_sysfs_reg, attr); 193 194 ret = kstrtoul(r->name, 16, ®); 195 if (ret) 196 return ret; 197 198 ret = kstrtoul(buffer, 10, &val); 199 if (ret) 200 return ret; 201 202 pcf2123_write_reg(dev, reg, val); 203 if (ret < 0) 204 return -EIO; 205 return count; 206 } 207 208 static int pcf2123_read_offset(struct device *dev, long *offset) 209 { 210 int ret; 211 s8 reg; 212 213 ret = pcf2123_read(dev, PCF2123_REG_OFFSET, ®, 1); 214 if (ret < 0) 215 return ret; 216 217 if (reg & OFFSET_COARSE) 218 reg <<= 1; /* multiply by 2 and sign extend */ 219 else 220 reg = sign_extend32(reg, OFFSET_SIGN_BIT); 221 222 *offset = ((long)reg) * OFFSET_STEP; 223 224 return 0; 225 } 226 227 /* 228 * The offset register is a 7 bit signed value with a coarse bit in bit 7. 229 * The main difference between the two is normal offset adjusts the first 230 * second of n minutes every other hour, with 61, 62 and 63 being shoved 231 * into the 60th minute. 232 * The coarse adjustment does the same, but every hour. 233 * the two overlap, with every even normal offset value corresponding 234 * to a coarse offset. Based on this algorithm, it seems that despite the 235 * name, coarse offset is a better fit for overlapping values. 236 */ 237 static int pcf2123_set_offset(struct device *dev, long offset) 238 { 239 s8 reg; 240 241 if (offset > OFFSET_STEP * 127) 242 reg = 127; 243 else if (offset < OFFSET_STEP * -128) 244 reg = -128; 245 else 246 reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP); 247 248 /* choose fine offset only for odd values in the normal range */ 249 if (reg & 1 && reg <= 63 && reg >= -64) { 250 /* Normal offset. Clear the coarse bit */ 251 reg &= ~OFFSET_COARSE; 252 } else { 253 /* Coarse offset. Divide by 2 and set the coarse bit */ 254 reg >>= 1; 255 reg |= OFFSET_COARSE; 256 } 257 258 return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg); 259 } 260 261 static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm) 262 { 263 u8 rxbuf[7]; 264 int ret; 265 266 ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf)); 267 if (ret < 0) 268 return ret; 269 270 if (rxbuf[0] & OSC_HAS_STOPPED) { 271 dev_info(dev, "clock was stopped. Time is not valid\n"); 272 return -EINVAL; 273 } 274 275 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F); 276 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F); 277 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */ 278 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F); 279 tm->tm_wday = rxbuf[4] & 0x07; 280 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */ 281 tm->tm_year = bcd2bin(rxbuf[6]); 282 if (tm->tm_year < 70) 283 tm->tm_year += 100; /* assume we are in 1970...2069 */ 284 285 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 286 "mday=%d, mon=%d, year=%d, wday=%d\n", 287 __func__, 288 tm->tm_sec, tm->tm_min, tm->tm_hour, 289 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 290 291 return rtc_valid_tm(tm); 292 } 293 294 static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm) 295 { 296 u8 txbuf[8]; 297 int ret; 298 299 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " 300 "mday=%d, mon=%d, year=%d, wday=%d\n", 301 __func__, 302 tm->tm_sec, tm->tm_min, tm->tm_hour, 303 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); 304 305 /* Stop the counter first */ 306 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP); 307 if (ret < 0) 308 return ret; 309 310 /* Set the new time */ 311 txbuf[0] = PCF2123_REG_SC; 312 txbuf[1] = bin2bcd(tm->tm_sec & 0x7F); 313 txbuf[2] = bin2bcd(tm->tm_min & 0x7F); 314 txbuf[3] = bin2bcd(tm->tm_hour & 0x3F); 315 txbuf[4] = bin2bcd(tm->tm_mday & 0x3F); 316 txbuf[5] = tm->tm_wday & 0x07; 317 txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */ 318 txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100); 319 320 ret = pcf2123_write(dev, txbuf, sizeof(txbuf)); 321 if (ret < 0) 322 return ret; 323 324 /* Start the counter */ 325 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR); 326 if (ret < 0) 327 return ret; 328 329 return 0; 330 } 331 332 static int pcf2123_reset(struct device *dev) 333 { 334 int ret; 335 u8 rxbuf[2]; 336 337 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET); 338 if (ret < 0) 339 return ret; 340 341 /* Stop the counter */ 342 dev_dbg(dev, "stopping RTC\n"); 343 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP); 344 if (ret < 0) 345 return ret; 346 347 /* See if the counter was actually stopped */ 348 dev_dbg(dev, "checking for presence of RTC\n"); 349 ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf)); 350 if (ret < 0) 351 return ret; 352 353 dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n", 354 rxbuf[0], rxbuf[1]); 355 if (!(rxbuf[0] & CTRL1_STOP)) 356 return -ENODEV; 357 358 /* Start the counter */ 359 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR); 360 if (ret < 0) 361 return ret; 362 363 return 0; 364 } 365 366 static const struct rtc_class_ops pcf2123_rtc_ops = { 367 .read_time = pcf2123_rtc_read_time, 368 .set_time = pcf2123_rtc_set_time, 369 .read_offset = pcf2123_read_offset, 370 .set_offset = pcf2123_set_offset, 371 372 }; 373 374 static int pcf2123_probe(struct spi_device *spi) 375 { 376 struct rtc_device *rtc; 377 struct rtc_time tm; 378 struct pcf2123_plat_data *pdata; 379 int ret, i; 380 381 pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data), 382 GFP_KERNEL); 383 if (!pdata) 384 return -ENOMEM; 385 spi->dev.platform_data = pdata; 386 387 ret = pcf2123_rtc_read_time(&spi->dev, &tm); 388 if (ret < 0) { 389 ret = pcf2123_reset(&spi->dev); 390 if (ret < 0) { 391 dev_err(&spi->dev, "chip not found\n"); 392 goto kfree_exit; 393 } 394 } 395 396 dev_info(&spi->dev, "spiclk %u KHz.\n", 397 (spi->max_speed_hz + 500) / 1000); 398 399 /* Finalize the initialization */ 400 rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name, 401 &pcf2123_rtc_ops, THIS_MODULE); 402 403 if (IS_ERR(rtc)) { 404 dev_err(&spi->dev, "failed to register.\n"); 405 ret = PTR_ERR(rtc); 406 goto kfree_exit; 407 } 408 409 pdata->rtc = rtc; 410 411 for (i = 0; i < 16; i++) { 412 sysfs_attr_init(&pdata->regs[i].attr.attr); 413 sprintf(pdata->regs[i].name, "%1x", i); 414 pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR; 415 pdata->regs[i].attr.attr.name = pdata->regs[i].name; 416 pdata->regs[i].attr.show = pcf2123_show; 417 pdata->regs[i].attr.store = pcf2123_store; 418 ret = device_create_file(&spi->dev, &pdata->regs[i].attr); 419 if (ret) { 420 dev_err(&spi->dev, "Unable to create sysfs %s\n", 421 pdata->regs[i].name); 422 goto sysfs_exit; 423 } 424 } 425 426 return 0; 427 428 sysfs_exit: 429 for (i--; i >= 0; i--) 430 device_remove_file(&spi->dev, &pdata->regs[i].attr); 431 432 kfree_exit: 433 spi->dev.platform_data = NULL; 434 return ret; 435 } 436 437 static int pcf2123_remove(struct spi_device *spi) 438 { 439 struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev); 440 int i; 441 442 if (pdata) { 443 for (i = 0; i < 16; i++) 444 if (pdata->regs[i].name[0]) 445 device_remove_file(&spi->dev, 446 &pdata->regs[i].attr); 447 } 448 449 return 0; 450 } 451 452 #ifdef CONFIG_OF 453 static const struct of_device_id pcf2123_dt_ids[] = { 454 { .compatible = "nxp,rtc-pcf2123", }, 455 { /* sentinel */ } 456 }; 457 MODULE_DEVICE_TABLE(of, pcf2123_dt_ids); 458 #endif 459 460 static struct spi_driver pcf2123_driver = { 461 .driver = { 462 .name = "rtc-pcf2123", 463 .of_match_table = of_match_ptr(pcf2123_dt_ids), 464 }, 465 .probe = pcf2123_probe, 466 .remove = pcf2123_remove, 467 }; 468 469 module_spi_driver(pcf2123_driver); 470 471 MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>"); 472 MODULE_DESCRIPTION("NXP PCF2123 RTC driver"); 473 MODULE_LICENSE("GPL"); 474