1 /* 2 * TI OMAP Real Time Clock interface for Linux 3 * 4 * Copyright (C) 2003 MontaVista Software, Inc. 5 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> 6 * 7 * Copyright (C) 2006 David Brownell (new RTC framework) 8 * Copyright (C) 2014 Johan Hovold <johan@kernel.org> 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 */ 15 16 #include <dt-bindings/gpio/gpio.h> 17 #include <linux/bcd.h> 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/init.h> 21 #include <linux/io.h> 22 #include <linux/ioport.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/rtc.h> 33 34 /* 35 * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock 36 * with century-range alarm matching, driven by the 32kHz clock. 37 * 38 * The main user-visible ways it differs from PC RTCs are by omitting 39 * "don't care" alarm fields and sub-second periodic IRQs, and having 40 * an autoadjust mechanism to calibrate to the true oscillator rate. 41 * 42 * Board-specific wiring options include using split power mode with 43 * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), 44 * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from 45 * low power modes) for OMAP1 boards (OMAP-L138 has this built into 46 * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. 47 */ 48 49 /* RTC registers */ 50 #define OMAP_RTC_SECONDS_REG 0x00 51 #define OMAP_RTC_MINUTES_REG 0x04 52 #define OMAP_RTC_HOURS_REG 0x08 53 #define OMAP_RTC_DAYS_REG 0x0C 54 #define OMAP_RTC_MONTHS_REG 0x10 55 #define OMAP_RTC_YEARS_REG 0x14 56 #define OMAP_RTC_WEEKS_REG 0x18 57 58 #define OMAP_RTC_ALARM_SECONDS_REG 0x20 59 #define OMAP_RTC_ALARM_MINUTES_REG 0x24 60 #define OMAP_RTC_ALARM_HOURS_REG 0x28 61 #define OMAP_RTC_ALARM_DAYS_REG 0x2c 62 #define OMAP_RTC_ALARM_MONTHS_REG 0x30 63 #define OMAP_RTC_ALARM_YEARS_REG 0x34 64 65 #define OMAP_RTC_CTRL_REG 0x40 66 #define OMAP_RTC_STATUS_REG 0x44 67 #define OMAP_RTC_INTERRUPTS_REG 0x48 68 69 #define OMAP_RTC_COMP_LSB_REG 0x4c 70 #define OMAP_RTC_COMP_MSB_REG 0x50 71 #define OMAP_RTC_OSC_REG 0x54 72 73 #define OMAP_RTC_SCRATCH0_REG 0x60 74 #define OMAP_RTC_SCRATCH1_REG 0x64 75 #define OMAP_RTC_SCRATCH2_REG 0x68 76 77 #define OMAP_RTC_KICK0_REG 0x6c 78 #define OMAP_RTC_KICK1_REG 0x70 79 80 #define OMAP_RTC_IRQWAKEEN 0x7c 81 82 #define OMAP_RTC_ALARM2_SECONDS_REG 0x80 83 #define OMAP_RTC_ALARM2_MINUTES_REG 0x84 84 #define OMAP_RTC_ALARM2_HOURS_REG 0x88 85 #define OMAP_RTC_ALARM2_DAYS_REG 0x8c 86 #define OMAP_RTC_ALARM2_MONTHS_REG 0x90 87 #define OMAP_RTC_ALARM2_YEARS_REG 0x94 88 89 #define OMAP_RTC_PMIC_REG 0x98 90 91 /* OMAP_RTC_CTRL_REG bit fields: */ 92 #define OMAP_RTC_CTRL_SPLIT BIT(7) 93 #define OMAP_RTC_CTRL_DISABLE BIT(6) 94 #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) 95 #define OMAP_RTC_CTRL_TEST BIT(4) 96 #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) 97 #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) 98 #define OMAP_RTC_CTRL_ROUND_30S BIT(1) 99 #define OMAP_RTC_CTRL_STOP BIT(0) 100 101 /* OMAP_RTC_STATUS_REG bit fields: */ 102 #define OMAP_RTC_STATUS_POWER_UP BIT(7) 103 #define OMAP_RTC_STATUS_ALARM2 BIT(7) 104 #define OMAP_RTC_STATUS_ALARM BIT(6) 105 #define OMAP_RTC_STATUS_1D_EVENT BIT(5) 106 #define OMAP_RTC_STATUS_1H_EVENT BIT(4) 107 #define OMAP_RTC_STATUS_1M_EVENT BIT(3) 108 #define OMAP_RTC_STATUS_1S_EVENT BIT(2) 109 #define OMAP_RTC_STATUS_RUN BIT(1) 110 #define OMAP_RTC_STATUS_BUSY BIT(0) 111 112 /* OMAP_RTC_INTERRUPTS_REG bit fields: */ 113 #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4) 114 #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) 115 #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) 116 117 /* OMAP_RTC_OSC_REG bit fields: */ 118 #define OMAP_RTC_OSC_32KCLK_EN BIT(6) 119 #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3) 120 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4) 121 122 /* OMAP_RTC_IRQWAKEEN bit fields: */ 123 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) 124 125 /* OMAP_RTC_PMIC bit fields: */ 126 #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16) 127 #define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x) 128 #define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x) 129 130 /* OMAP_RTC_KICKER values */ 131 #define KICK0_VALUE 0x83e70b13 132 #define KICK1_VALUE 0x95a4f1e0 133 134 struct omap_rtc; 135 136 struct omap_rtc_device_type { 137 bool has_32kclk_en; 138 bool has_irqwakeen; 139 bool has_pmic_mode; 140 bool has_power_up_reset; 141 void (*lock)(struct omap_rtc *rtc); 142 void (*unlock)(struct omap_rtc *rtc); 143 }; 144 145 struct omap_rtc { 146 struct rtc_device *rtc; 147 void __iomem *base; 148 struct clk *clk; 149 int irq_alarm; 150 int irq_timer; 151 u8 interrupts_reg; 152 bool is_pmic_controller; 153 bool has_ext_clk; 154 bool is_suspending; 155 const struct omap_rtc_device_type *type; 156 struct pinctrl_dev *pctldev; 157 }; 158 159 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) 160 { 161 return readb(rtc->base + reg); 162 } 163 164 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg) 165 { 166 return readl(rtc->base + reg); 167 } 168 169 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) 170 { 171 writeb(val, rtc->base + reg); 172 } 173 174 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) 175 { 176 writel(val, rtc->base + reg); 177 } 178 179 static void am3352_rtc_unlock(struct omap_rtc *rtc) 180 { 181 rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); 182 rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); 183 } 184 185 static void am3352_rtc_lock(struct omap_rtc *rtc) 186 { 187 rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); 188 rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0); 189 } 190 191 static void default_rtc_unlock(struct omap_rtc *rtc) 192 { 193 } 194 195 static void default_rtc_lock(struct omap_rtc *rtc) 196 { 197 } 198 199 /* 200 * We rely on the rtc framework to handle locking (rtc->ops_lock), 201 * so the only other requirement is that register accesses which 202 * require BUSY to be clear are made with IRQs locally disabled 203 */ 204 static void rtc_wait_not_busy(struct omap_rtc *rtc) 205 { 206 int count; 207 u8 status; 208 209 /* BUSY may stay active for 1/32768 second (~30 usec) */ 210 for (count = 0; count < 50; count++) { 211 status = rtc_read(rtc, OMAP_RTC_STATUS_REG); 212 if (!(status & OMAP_RTC_STATUS_BUSY)) 213 break; 214 udelay(1); 215 } 216 /* now we have ~15 usec to read/write various registers */ 217 } 218 219 static irqreturn_t rtc_irq(int irq, void *dev_id) 220 { 221 struct omap_rtc *rtc = dev_id; 222 unsigned long events = 0; 223 u8 irq_data; 224 225 irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); 226 227 /* alarm irq? */ 228 if (irq_data & OMAP_RTC_STATUS_ALARM) { 229 rtc->type->unlock(rtc); 230 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); 231 rtc->type->lock(rtc); 232 events |= RTC_IRQF | RTC_AF; 233 } 234 235 /* 1/sec periodic/update irq? */ 236 if (irq_data & OMAP_RTC_STATUS_1S_EVENT) 237 events |= RTC_IRQF | RTC_UF; 238 239 rtc_update_irq(rtc->rtc, 1, events); 240 241 return IRQ_HANDLED; 242 } 243 244 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 245 { 246 struct omap_rtc *rtc = dev_get_drvdata(dev); 247 u8 reg, irqwake_reg = 0; 248 249 local_irq_disable(); 250 rtc_wait_not_busy(rtc); 251 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 252 if (rtc->type->has_irqwakeen) 253 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); 254 255 if (enabled) { 256 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; 257 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; 258 } else { 259 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; 260 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; 261 } 262 rtc_wait_not_busy(rtc); 263 rtc->type->unlock(rtc); 264 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); 265 if (rtc->type->has_irqwakeen) 266 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); 267 rtc->type->lock(rtc); 268 local_irq_enable(); 269 270 return 0; 271 } 272 273 /* this hardware doesn't support "don't care" alarm fields */ 274 static int tm2bcd(struct rtc_time *tm) 275 { 276 tm->tm_sec = bin2bcd(tm->tm_sec); 277 tm->tm_min = bin2bcd(tm->tm_min); 278 tm->tm_hour = bin2bcd(tm->tm_hour); 279 tm->tm_mday = bin2bcd(tm->tm_mday); 280 281 tm->tm_mon = bin2bcd(tm->tm_mon + 1); 282 283 /* epoch == 1900 */ 284 if (tm->tm_year < 100 || tm->tm_year > 199) 285 return -EINVAL; 286 tm->tm_year = bin2bcd(tm->tm_year - 100); 287 288 return 0; 289 } 290 291 static void bcd2tm(struct rtc_time *tm) 292 { 293 tm->tm_sec = bcd2bin(tm->tm_sec); 294 tm->tm_min = bcd2bin(tm->tm_min); 295 tm->tm_hour = bcd2bin(tm->tm_hour); 296 tm->tm_mday = bcd2bin(tm->tm_mday); 297 tm->tm_mon = bcd2bin(tm->tm_mon) - 1; 298 /* epoch == 1900 */ 299 tm->tm_year = bcd2bin(tm->tm_year) + 100; 300 } 301 302 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm) 303 { 304 tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); 305 tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); 306 tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); 307 tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); 308 tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); 309 tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); 310 } 311 312 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) 313 { 314 struct omap_rtc *rtc = dev_get_drvdata(dev); 315 316 /* we don't report wday/yday/isdst ... */ 317 local_irq_disable(); 318 rtc_wait_not_busy(rtc); 319 omap_rtc_read_time_raw(rtc, tm); 320 local_irq_enable(); 321 322 bcd2tm(tm); 323 324 return 0; 325 } 326 327 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) 328 { 329 struct omap_rtc *rtc = dev_get_drvdata(dev); 330 331 if (tm2bcd(tm) < 0) 332 return -EINVAL; 333 334 local_irq_disable(); 335 rtc_wait_not_busy(rtc); 336 337 rtc->type->unlock(rtc); 338 rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); 339 rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); 340 rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); 341 rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); 342 rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); 343 rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); 344 rtc->type->lock(rtc); 345 346 local_irq_enable(); 347 348 return 0; 349 } 350 351 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) 352 { 353 struct omap_rtc *rtc = dev_get_drvdata(dev); 354 u8 interrupts; 355 356 local_irq_disable(); 357 rtc_wait_not_busy(rtc); 358 359 alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); 360 alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); 361 alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); 362 alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); 363 alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); 364 alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); 365 366 local_irq_enable(); 367 368 bcd2tm(&alm->time); 369 370 interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 371 alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM); 372 373 return 0; 374 } 375 376 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) 377 { 378 struct omap_rtc *rtc = dev_get_drvdata(dev); 379 u8 reg, irqwake_reg = 0; 380 381 if (tm2bcd(&alm->time) < 0) 382 return -EINVAL; 383 384 local_irq_disable(); 385 rtc_wait_not_busy(rtc); 386 387 rtc->type->unlock(rtc); 388 rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); 389 rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); 390 rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); 391 rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); 392 rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); 393 rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); 394 395 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 396 if (rtc->type->has_irqwakeen) 397 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); 398 399 if (alm->enabled) { 400 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; 401 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; 402 } else { 403 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; 404 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; 405 } 406 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); 407 if (rtc->type->has_irqwakeen) 408 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); 409 rtc->type->lock(rtc); 410 411 local_irq_enable(); 412 413 return 0; 414 } 415 416 static struct omap_rtc *omap_rtc_power_off_rtc; 417 418 /* 419 * omap_rtc_poweroff: RTC-controlled power off 420 * 421 * The RTC can be used to control an external PMIC via the pmic_power_en pin, 422 * which can be configured to transition to OFF on ALARM2 events. 423 * 424 * Notes: 425 * The two-second alarm offset is the shortest offset possible as the alarm 426 * registers must be set before the next timer update and the offset 427 * calculation is too heavy for everything to be done within a single access 428 * period (~15 us). 429 * 430 * Called with local interrupts disabled. 431 */ 432 static void omap_rtc_power_off(void) 433 { 434 struct omap_rtc *rtc = omap_rtc_power_off_rtc; 435 struct rtc_time tm; 436 unsigned long now; 437 u32 val; 438 439 rtc->type->unlock(rtc); 440 /* enable pmic_power_en control */ 441 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); 442 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN); 443 444 /* set alarm two seconds from now */ 445 omap_rtc_read_time_raw(rtc, &tm); 446 bcd2tm(&tm); 447 rtc_tm_to_time(&tm, &now); 448 rtc_time_to_tm(now + 2, &tm); 449 450 if (tm2bcd(&tm) < 0) { 451 dev_err(&rtc->rtc->dev, "power off failed\n"); 452 rtc->type->lock(rtc); 453 return; 454 } 455 456 rtc_wait_not_busy(rtc); 457 458 rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec); 459 rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min); 460 rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour); 461 rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday); 462 rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon); 463 rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year); 464 465 /* 466 * enable ALARM2 interrupt 467 * 468 * NOTE: this fails on AM3352 if rtc_write (writeb) is used 469 */ 470 val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 471 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 472 val | OMAP_RTC_INTERRUPTS_IT_ALARM2); 473 rtc->type->lock(rtc); 474 475 /* 476 * Wait for alarm to trigger (within two seconds) and external PMIC to 477 * power off the system. Add a 500 ms margin for external latencies 478 * (e.g. debounce circuits). 479 */ 480 mdelay(2500); 481 } 482 483 static const struct rtc_class_ops omap_rtc_ops = { 484 .read_time = omap_rtc_read_time, 485 .set_time = omap_rtc_set_time, 486 .read_alarm = omap_rtc_read_alarm, 487 .set_alarm = omap_rtc_set_alarm, 488 .alarm_irq_enable = omap_rtc_alarm_irq_enable, 489 }; 490 491 static const struct omap_rtc_device_type omap_rtc_default_type = { 492 .has_power_up_reset = true, 493 .lock = default_rtc_lock, 494 .unlock = default_rtc_unlock, 495 }; 496 497 static const struct omap_rtc_device_type omap_rtc_am3352_type = { 498 .has_32kclk_en = true, 499 .has_irqwakeen = true, 500 .has_pmic_mode = true, 501 .lock = am3352_rtc_lock, 502 .unlock = am3352_rtc_unlock, 503 }; 504 505 static const struct omap_rtc_device_type omap_rtc_da830_type = { 506 .lock = am3352_rtc_lock, 507 .unlock = am3352_rtc_unlock, 508 }; 509 510 static const struct platform_device_id omap_rtc_id_table[] = { 511 { 512 .name = "omap_rtc", 513 .driver_data = (kernel_ulong_t)&omap_rtc_default_type, 514 }, { 515 .name = "am3352-rtc", 516 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type, 517 }, { 518 .name = "da830-rtc", 519 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type, 520 }, { 521 /* sentinel */ 522 } 523 }; 524 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table); 525 526 static const struct of_device_id omap_rtc_of_match[] = { 527 { 528 .compatible = "ti,am3352-rtc", 529 .data = &omap_rtc_am3352_type, 530 }, { 531 .compatible = "ti,da830-rtc", 532 .data = &omap_rtc_da830_type, 533 }, { 534 /* sentinel */ 535 } 536 }; 537 MODULE_DEVICE_TABLE(of, omap_rtc_of_match); 538 539 static const struct pinctrl_pin_desc rtc_pins_desc[] = { 540 PINCTRL_PIN(0, "ext_wakeup0"), 541 PINCTRL_PIN(1, "ext_wakeup1"), 542 PINCTRL_PIN(2, "ext_wakeup2"), 543 PINCTRL_PIN(3, "ext_wakeup3"), 544 }; 545 546 static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 547 { 548 return 0; 549 } 550 551 static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 552 unsigned int group) 553 { 554 return NULL; 555 } 556 557 static const struct pinctrl_ops rtc_pinctrl_ops = { 558 .get_groups_count = rtc_pinctrl_get_groups_count, 559 .get_group_name = rtc_pinctrl_get_group_name, 560 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 561 .dt_free_map = pinconf_generic_dt_free_map, 562 }; 563 564 enum rtc_pin_config_param { 565 PIN_CONFIG_ACTIVE_HIGH = PIN_CONFIG_END + 1, 566 }; 567 568 static const struct pinconf_generic_params rtc_params[] = { 569 {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0}, 570 }; 571 572 #ifdef CONFIG_DEBUG_FS 573 static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = { 574 PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false), 575 }; 576 #endif 577 578 static int rtc_pinconf_get(struct pinctrl_dev *pctldev, 579 unsigned int pin, unsigned long *config) 580 { 581 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); 582 unsigned int param = pinconf_to_config_param(*config); 583 u32 val; 584 u16 arg = 0; 585 586 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); 587 588 switch (param) { 589 case PIN_CONFIG_INPUT_ENABLE: 590 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin))) 591 return -EINVAL; 592 break; 593 case PIN_CONFIG_ACTIVE_HIGH: 594 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin)) 595 return -EINVAL; 596 break; 597 default: 598 return -ENOTSUPP; 599 }; 600 601 *config = pinconf_to_config_packed(param, arg); 602 603 return 0; 604 } 605 606 static int rtc_pinconf_set(struct pinctrl_dev *pctldev, 607 unsigned int pin, unsigned long *configs, 608 unsigned int num_configs) 609 { 610 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); 611 u32 val; 612 unsigned int param; 613 u32 param_val; 614 int i; 615 616 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); 617 618 /* active low by default */ 619 val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin); 620 621 for (i = 0; i < num_configs; i++) { 622 param = pinconf_to_config_param(configs[i]); 623 param_val = pinconf_to_config_argument(configs[i]); 624 625 switch (param) { 626 case PIN_CONFIG_INPUT_ENABLE: 627 if (param_val) 628 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin); 629 else 630 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin); 631 break; 632 case PIN_CONFIG_ACTIVE_HIGH: 633 val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin); 634 break; 635 default: 636 dev_err(&rtc->rtc->dev, "Property %u not supported\n", 637 param); 638 return -ENOTSUPP; 639 } 640 } 641 642 rtc->type->unlock(rtc); 643 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val); 644 rtc->type->lock(rtc); 645 646 return 0; 647 } 648 649 static const struct pinconf_ops rtc_pinconf_ops = { 650 .is_generic = true, 651 .pin_config_get = rtc_pinconf_get, 652 .pin_config_set = rtc_pinconf_set, 653 }; 654 655 static struct pinctrl_desc rtc_pinctrl_desc = { 656 .pins = rtc_pins_desc, 657 .npins = ARRAY_SIZE(rtc_pins_desc), 658 .pctlops = &rtc_pinctrl_ops, 659 .confops = &rtc_pinconf_ops, 660 .custom_params = rtc_params, 661 .num_custom_params = ARRAY_SIZE(rtc_params), 662 #ifdef CONFIG_DEBUG_FS 663 .custom_conf_items = rtc_conf_items, 664 #endif 665 .owner = THIS_MODULE, 666 }; 667 668 static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val, 669 size_t bytes) 670 { 671 struct omap_rtc *rtc = priv; 672 u32 *val = _val; 673 int i; 674 675 for (i = 0; i < bytes / 4; i++) 676 val[i] = rtc_readl(rtc, 677 OMAP_RTC_SCRATCH0_REG + offset + (i * 4)); 678 679 return 0; 680 } 681 682 static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val, 683 size_t bytes) 684 { 685 struct omap_rtc *rtc = priv; 686 u32 *val = _val; 687 int i; 688 689 rtc->type->unlock(rtc); 690 for (i = 0; i < bytes / 4; i++) 691 rtc_writel(rtc, 692 OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]); 693 rtc->type->lock(rtc); 694 695 return 0; 696 } 697 698 static struct nvmem_config omap_rtc_nvmem_config = { 699 .name = "omap_rtc_scratch", 700 .word_size = 4, 701 .stride = 4, 702 .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG, 703 .reg_read = omap_rtc_scratch_read, 704 .reg_write = omap_rtc_scratch_write, 705 }; 706 707 static int omap_rtc_probe(struct platform_device *pdev) 708 { 709 struct omap_rtc *rtc; 710 struct resource *res; 711 u8 reg, mask, new_ctrl; 712 const struct platform_device_id *id_entry; 713 const struct of_device_id *of_id; 714 int ret; 715 716 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 717 if (!rtc) 718 return -ENOMEM; 719 720 of_id = of_match_device(omap_rtc_of_match, &pdev->dev); 721 if (of_id) { 722 rtc->type = of_id->data; 723 rtc->is_pmic_controller = rtc->type->has_pmic_mode && 724 of_property_read_bool(pdev->dev.of_node, 725 "system-power-controller"); 726 } else { 727 id_entry = platform_get_device_id(pdev); 728 rtc->type = (void *)id_entry->driver_data; 729 } 730 731 rtc->irq_timer = platform_get_irq(pdev, 0); 732 if (rtc->irq_timer <= 0) 733 return -ENOENT; 734 735 rtc->irq_alarm = platform_get_irq(pdev, 1); 736 if (rtc->irq_alarm <= 0) 737 return -ENOENT; 738 739 rtc->clk = devm_clk_get(&pdev->dev, "ext-clk"); 740 if (!IS_ERR(rtc->clk)) 741 rtc->has_ext_clk = true; 742 else 743 rtc->clk = devm_clk_get(&pdev->dev, "int-clk"); 744 745 if (!IS_ERR(rtc->clk)) 746 clk_prepare_enable(rtc->clk); 747 748 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 749 rtc->base = devm_ioremap_resource(&pdev->dev, res); 750 if (IS_ERR(rtc->base)) { 751 clk_disable_unprepare(rtc->clk); 752 return PTR_ERR(rtc->base); 753 } 754 755 platform_set_drvdata(pdev, rtc); 756 757 /* Enable the clock/module so that we can access the registers */ 758 pm_runtime_enable(&pdev->dev); 759 pm_runtime_get_sync(&pdev->dev); 760 761 rtc->type->unlock(rtc); 762 763 /* 764 * disable interrupts 765 * 766 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used 767 */ 768 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); 769 770 /* enable RTC functional clock */ 771 if (rtc->type->has_32kclk_en) { 772 reg = rtc_read(rtc, OMAP_RTC_OSC_REG); 773 rtc_writel(rtc, OMAP_RTC_OSC_REG, 774 reg | OMAP_RTC_OSC_32KCLK_EN); 775 } 776 777 /* clear old status */ 778 reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); 779 780 mask = OMAP_RTC_STATUS_ALARM; 781 782 if (rtc->type->has_pmic_mode) 783 mask |= OMAP_RTC_STATUS_ALARM2; 784 785 if (rtc->type->has_power_up_reset) { 786 mask |= OMAP_RTC_STATUS_POWER_UP; 787 if (reg & OMAP_RTC_STATUS_POWER_UP) 788 dev_info(&pdev->dev, "RTC power up reset detected\n"); 789 } 790 791 if (reg & mask) 792 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); 793 794 /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ 795 reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); 796 if (reg & OMAP_RTC_CTRL_STOP) 797 dev_info(&pdev->dev, "already running\n"); 798 799 /* force to 24 hour mode */ 800 new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); 801 new_ctrl |= OMAP_RTC_CTRL_STOP; 802 803 /* 804 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: 805 * 806 * - Device wake-up capability setting should come through chip 807 * init logic. OMAP1 boards should initialize the "wakeup capable" 808 * flag in the platform device if the board is wired right for 809 * being woken up by RTC alarm. For OMAP-L138, this capability 810 * is built into the SoC by the "Deep Sleep" capability. 811 * 812 * - Boards wired so RTC_ON_nOFF is used as the reset signal, 813 * rather than nPWRON_RESET, should forcibly enable split 814 * power mode. (Some chip errata report that RTC_CTRL_SPLIT 815 * is write-only, and always reads as zero...) 816 */ 817 818 if (new_ctrl & OMAP_RTC_CTRL_SPLIT) 819 dev_info(&pdev->dev, "split power mode\n"); 820 821 if (reg != new_ctrl) 822 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); 823 824 /* 825 * If we have the external clock then switch to it so we can keep 826 * ticking across suspend. 827 */ 828 if (rtc->has_ext_clk) { 829 reg = rtc_read(rtc, OMAP_RTC_OSC_REG); 830 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE; 831 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC; 832 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg); 833 } 834 835 rtc->type->lock(rtc); 836 837 device_init_wakeup(&pdev->dev, true); 838 839 rtc->rtc = devm_rtc_allocate_device(&pdev->dev); 840 if (IS_ERR(rtc->rtc)) { 841 ret = PTR_ERR(rtc->rtc); 842 goto err; 843 } 844 845 rtc->rtc->ops = &omap_rtc_ops; 846 omap_rtc_nvmem_config.priv = rtc; 847 848 /* handle periodic and alarm irqs */ 849 ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, 850 dev_name(&rtc->rtc->dev), rtc); 851 if (ret) 852 goto err; 853 854 if (rtc->irq_timer != rtc->irq_alarm) { 855 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, 856 dev_name(&rtc->rtc->dev), rtc); 857 if (ret) 858 goto err; 859 } 860 861 /* Support ext_wakeup pinconf */ 862 rtc_pinctrl_desc.name = dev_name(&pdev->dev); 863 864 rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc); 865 if (IS_ERR(rtc->pctldev)) { 866 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 867 ret = PTR_ERR(rtc->pctldev); 868 goto err; 869 } 870 871 ret = rtc_register_device(rtc->rtc); 872 if (ret) 873 goto err_deregister_pinctrl; 874 875 rtc_nvmem_register(rtc->rtc, &omap_rtc_nvmem_config); 876 877 if (rtc->is_pmic_controller) { 878 if (!pm_power_off) { 879 omap_rtc_power_off_rtc = rtc; 880 pm_power_off = omap_rtc_power_off; 881 } 882 } 883 884 return 0; 885 886 err_deregister_pinctrl: 887 pinctrl_unregister(rtc->pctldev); 888 err: 889 clk_disable_unprepare(rtc->clk); 890 device_init_wakeup(&pdev->dev, false); 891 rtc->type->lock(rtc); 892 pm_runtime_put_sync(&pdev->dev); 893 pm_runtime_disable(&pdev->dev); 894 895 return ret; 896 } 897 898 static int omap_rtc_remove(struct platform_device *pdev) 899 { 900 struct omap_rtc *rtc = platform_get_drvdata(pdev); 901 u8 reg; 902 903 if (pm_power_off == omap_rtc_power_off && 904 omap_rtc_power_off_rtc == rtc) { 905 pm_power_off = NULL; 906 omap_rtc_power_off_rtc = NULL; 907 } 908 909 device_init_wakeup(&pdev->dev, 0); 910 911 if (!IS_ERR(rtc->clk)) 912 clk_disable_unprepare(rtc->clk); 913 914 rtc->type->unlock(rtc); 915 /* leave rtc running, but disable irqs */ 916 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); 917 918 if (rtc->has_ext_clk) { 919 reg = rtc_read(rtc, OMAP_RTC_OSC_REG); 920 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC; 921 rtc_write(rtc, OMAP_RTC_OSC_REG, reg); 922 } 923 924 rtc->type->lock(rtc); 925 926 /* Disable the clock/module */ 927 pm_runtime_put_sync(&pdev->dev); 928 pm_runtime_disable(&pdev->dev); 929 930 /* Remove ext_wakeup pinconf */ 931 pinctrl_unregister(rtc->pctldev); 932 933 return 0; 934 } 935 936 static int __maybe_unused omap_rtc_suspend(struct device *dev) 937 { 938 struct omap_rtc *rtc = dev_get_drvdata(dev); 939 940 rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 941 942 rtc->type->unlock(rtc); 943 /* 944 * FIXME: the RTC alarm is not currently acting as a wakeup event 945 * source on some platforms, and in fact this enable() call is just 946 * saving a flag that's never used... 947 */ 948 if (device_may_wakeup(dev)) 949 enable_irq_wake(rtc->irq_alarm); 950 else 951 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); 952 rtc->type->lock(rtc); 953 954 rtc->is_suspending = true; 955 956 return 0; 957 } 958 959 static int __maybe_unused omap_rtc_resume(struct device *dev) 960 { 961 struct omap_rtc *rtc = dev_get_drvdata(dev); 962 963 rtc->type->unlock(rtc); 964 if (device_may_wakeup(dev)) 965 disable_irq_wake(rtc->irq_alarm); 966 else 967 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); 968 rtc->type->lock(rtc); 969 970 rtc->is_suspending = false; 971 972 return 0; 973 } 974 975 static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev) 976 { 977 struct omap_rtc *rtc = dev_get_drvdata(dev); 978 979 if (rtc->is_suspending && !rtc->has_ext_clk) 980 return -EBUSY; 981 982 return 0; 983 } 984 985 static const struct dev_pm_ops omap_rtc_pm_ops = { 986 SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume) 987 SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL) 988 }; 989 990 static void omap_rtc_shutdown(struct platform_device *pdev) 991 { 992 struct omap_rtc *rtc = platform_get_drvdata(pdev); 993 u8 mask; 994 995 /* 996 * Keep the ALARM interrupt enabled to allow the system to power up on 997 * alarm events. 998 */ 999 rtc->type->unlock(rtc); 1000 mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 1001 mask &= OMAP_RTC_INTERRUPTS_IT_ALARM; 1002 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask); 1003 rtc->type->lock(rtc); 1004 } 1005 1006 static struct platform_driver omap_rtc_driver = { 1007 .probe = omap_rtc_probe, 1008 .remove = omap_rtc_remove, 1009 .shutdown = omap_rtc_shutdown, 1010 .driver = { 1011 .name = "omap_rtc", 1012 .pm = &omap_rtc_pm_ops, 1013 .of_match_table = omap_rtc_of_match, 1014 }, 1015 .id_table = omap_rtc_id_table, 1016 }; 1017 1018 module_platform_driver(omap_rtc_driver); 1019 1020 MODULE_ALIAS("platform:omap_rtc"); 1021 MODULE_AUTHOR("George G. Davis (and others)"); 1022 MODULE_LICENSE("GPL"); 1023