xref: /openbmc/linux/drivers/rtc/rtc-omap.c (revision c819e2cf)
1 /*
2  * TI OMAP Real Time Clock interface for Linux
3  *
4  * Copyright (C) 2003 MontaVista Software, Inc.
5  * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
6  *
7  * Copyright (C) 2006 David Brownell (new RTC framework)
8  * Copyright (C) 2014 Johan Hovold <johan@kernel.org>
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version
13  * 2 of the License, or (at your option) any later version.
14  */
15 
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/rtc.h>
22 #include <linux/bcd.h>
23 #include <linux/platform_device.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/io.h>
28 
29 /*
30  * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock
31  * with century-range alarm matching, driven by the 32kHz clock.
32  *
33  * The main user-visible ways it differs from PC RTCs are by omitting
34  * "don't care" alarm fields and sub-second periodic IRQs, and having
35  * an autoadjust mechanism to calibrate to the true oscillator rate.
36  *
37  * Board-specific wiring options include using split power mode with
38  * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
39  * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
40  * low power modes) for OMAP1 boards (OMAP-L138 has this built into
41  * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
42  */
43 
44 /* RTC registers */
45 #define OMAP_RTC_SECONDS_REG		0x00
46 #define OMAP_RTC_MINUTES_REG		0x04
47 #define OMAP_RTC_HOURS_REG		0x08
48 #define OMAP_RTC_DAYS_REG		0x0C
49 #define OMAP_RTC_MONTHS_REG		0x10
50 #define OMAP_RTC_YEARS_REG		0x14
51 #define OMAP_RTC_WEEKS_REG		0x18
52 
53 #define OMAP_RTC_ALARM_SECONDS_REG	0x20
54 #define OMAP_RTC_ALARM_MINUTES_REG	0x24
55 #define OMAP_RTC_ALARM_HOURS_REG	0x28
56 #define OMAP_RTC_ALARM_DAYS_REG		0x2c
57 #define OMAP_RTC_ALARM_MONTHS_REG	0x30
58 #define OMAP_RTC_ALARM_YEARS_REG	0x34
59 
60 #define OMAP_RTC_CTRL_REG		0x40
61 #define OMAP_RTC_STATUS_REG		0x44
62 #define OMAP_RTC_INTERRUPTS_REG		0x48
63 
64 #define OMAP_RTC_COMP_LSB_REG		0x4c
65 #define OMAP_RTC_COMP_MSB_REG		0x50
66 #define OMAP_RTC_OSC_REG		0x54
67 
68 #define OMAP_RTC_KICK0_REG		0x6c
69 #define OMAP_RTC_KICK1_REG		0x70
70 
71 #define OMAP_RTC_IRQWAKEEN		0x7c
72 
73 #define OMAP_RTC_ALARM2_SECONDS_REG	0x80
74 #define OMAP_RTC_ALARM2_MINUTES_REG	0x84
75 #define OMAP_RTC_ALARM2_HOURS_REG	0x88
76 #define OMAP_RTC_ALARM2_DAYS_REG	0x8c
77 #define OMAP_RTC_ALARM2_MONTHS_REG	0x90
78 #define OMAP_RTC_ALARM2_YEARS_REG	0x94
79 
80 #define OMAP_RTC_PMIC_REG		0x98
81 
82 /* OMAP_RTC_CTRL_REG bit fields: */
83 #define OMAP_RTC_CTRL_SPLIT		BIT(7)
84 #define OMAP_RTC_CTRL_DISABLE		BIT(6)
85 #define OMAP_RTC_CTRL_SET_32_COUNTER	BIT(5)
86 #define OMAP_RTC_CTRL_TEST		BIT(4)
87 #define OMAP_RTC_CTRL_MODE_12_24	BIT(3)
88 #define OMAP_RTC_CTRL_AUTO_COMP		BIT(2)
89 #define OMAP_RTC_CTRL_ROUND_30S		BIT(1)
90 #define OMAP_RTC_CTRL_STOP		BIT(0)
91 
92 /* OMAP_RTC_STATUS_REG bit fields: */
93 #define OMAP_RTC_STATUS_POWER_UP	BIT(7)
94 #define OMAP_RTC_STATUS_ALARM2		BIT(7)
95 #define OMAP_RTC_STATUS_ALARM		BIT(6)
96 #define OMAP_RTC_STATUS_1D_EVENT	BIT(5)
97 #define OMAP_RTC_STATUS_1H_EVENT	BIT(4)
98 #define OMAP_RTC_STATUS_1M_EVENT	BIT(3)
99 #define OMAP_RTC_STATUS_1S_EVENT	BIT(2)
100 #define OMAP_RTC_STATUS_RUN		BIT(1)
101 #define OMAP_RTC_STATUS_BUSY		BIT(0)
102 
103 /* OMAP_RTC_INTERRUPTS_REG bit fields: */
104 #define OMAP_RTC_INTERRUPTS_IT_ALARM2	BIT(4)
105 #define OMAP_RTC_INTERRUPTS_IT_ALARM	BIT(3)
106 #define OMAP_RTC_INTERRUPTS_IT_TIMER	BIT(2)
107 
108 /* OMAP_RTC_OSC_REG bit fields: */
109 #define OMAP_RTC_OSC_32KCLK_EN		BIT(6)
110 
111 /* OMAP_RTC_IRQWAKEEN bit fields: */
112 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN	BIT(1)
113 
114 /* OMAP_RTC_PMIC bit fields: */
115 #define OMAP_RTC_PMIC_POWER_EN_EN	BIT(16)
116 
117 /* OMAP_RTC_KICKER values */
118 #define	KICK0_VALUE			0x83e70b13
119 #define	KICK1_VALUE			0x95a4f1e0
120 
121 struct omap_rtc_device_type {
122 	bool has_32kclk_en;
123 	bool has_kicker;
124 	bool has_irqwakeen;
125 	bool has_pmic_mode;
126 	bool has_power_up_reset;
127 };
128 
129 struct omap_rtc {
130 	struct rtc_device *rtc;
131 	void __iomem *base;
132 	int irq_alarm;
133 	int irq_timer;
134 	u8 interrupts_reg;
135 	bool is_pmic_controller;
136 	const struct omap_rtc_device_type *type;
137 };
138 
139 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg)
140 {
141 	return readb(rtc->base + reg);
142 }
143 
144 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg)
145 {
146 	return readl(rtc->base + reg);
147 }
148 
149 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val)
150 {
151 	writeb(val, rtc->base + reg);
152 }
153 
154 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val)
155 {
156 	writel(val, rtc->base + reg);
157 }
158 
159 /*
160  * We rely on the rtc framework to handle locking (rtc->ops_lock),
161  * so the only other requirement is that register accesses which
162  * require BUSY to be clear are made with IRQs locally disabled
163  */
164 static void rtc_wait_not_busy(struct omap_rtc *rtc)
165 {
166 	int count;
167 	u8 status;
168 
169 	/* BUSY may stay active for 1/32768 second (~30 usec) */
170 	for (count = 0; count < 50; count++) {
171 		status = rtc_read(rtc, OMAP_RTC_STATUS_REG);
172 		if (!(status & OMAP_RTC_STATUS_BUSY))
173 			break;
174 		udelay(1);
175 	}
176 	/* now we have ~15 usec to read/write various registers */
177 }
178 
179 static irqreturn_t rtc_irq(int irq, void *dev_id)
180 {
181 	struct omap_rtc	*rtc = dev_id;
182 	unsigned long events = 0;
183 	u8 irq_data;
184 
185 	irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG);
186 
187 	/* alarm irq? */
188 	if (irq_data & OMAP_RTC_STATUS_ALARM) {
189 		rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM);
190 		events |= RTC_IRQF | RTC_AF;
191 	}
192 
193 	/* 1/sec periodic/update irq? */
194 	if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
195 		events |= RTC_IRQF | RTC_UF;
196 
197 	rtc_update_irq(rtc->rtc, 1, events);
198 
199 	return IRQ_HANDLED;
200 }
201 
202 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
203 {
204 	struct omap_rtc *rtc = dev_get_drvdata(dev);
205 	u8 reg, irqwake_reg = 0;
206 
207 	local_irq_disable();
208 	rtc_wait_not_busy(rtc);
209 	reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
210 	if (rtc->type->has_irqwakeen)
211 		irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
212 
213 	if (enabled) {
214 		reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
215 		irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
216 	} else {
217 		reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
218 		irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
219 	}
220 	rtc_wait_not_busy(rtc);
221 	rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
222 	if (rtc->type->has_irqwakeen)
223 		rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
224 	local_irq_enable();
225 
226 	return 0;
227 }
228 
229 /* this hardware doesn't support "don't care" alarm fields */
230 static int tm2bcd(struct rtc_time *tm)
231 {
232 	if (rtc_valid_tm(tm) != 0)
233 		return -EINVAL;
234 
235 	tm->tm_sec = bin2bcd(tm->tm_sec);
236 	tm->tm_min = bin2bcd(tm->tm_min);
237 	tm->tm_hour = bin2bcd(tm->tm_hour);
238 	tm->tm_mday = bin2bcd(tm->tm_mday);
239 
240 	tm->tm_mon = bin2bcd(tm->tm_mon + 1);
241 
242 	/* epoch == 1900 */
243 	if (tm->tm_year < 100 || tm->tm_year > 199)
244 		return -EINVAL;
245 	tm->tm_year = bin2bcd(tm->tm_year - 100);
246 
247 	return 0;
248 }
249 
250 static void bcd2tm(struct rtc_time *tm)
251 {
252 	tm->tm_sec = bcd2bin(tm->tm_sec);
253 	tm->tm_min = bcd2bin(tm->tm_min);
254 	tm->tm_hour = bcd2bin(tm->tm_hour);
255 	tm->tm_mday = bcd2bin(tm->tm_mday);
256 	tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
257 	/* epoch == 1900 */
258 	tm->tm_year = bcd2bin(tm->tm_year) + 100;
259 }
260 
261 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm)
262 {
263 	tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG);
264 	tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG);
265 	tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG);
266 	tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG);
267 	tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG);
268 	tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG);
269 }
270 
271 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
272 {
273 	struct omap_rtc *rtc = dev_get_drvdata(dev);
274 
275 	/* we don't report wday/yday/isdst ... */
276 	local_irq_disable();
277 	rtc_wait_not_busy(rtc);
278 	omap_rtc_read_time_raw(rtc, tm);
279 	local_irq_enable();
280 
281 	bcd2tm(tm);
282 
283 	return 0;
284 }
285 
286 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
287 {
288 	struct omap_rtc *rtc = dev_get_drvdata(dev);
289 
290 	if (tm2bcd(tm) < 0)
291 		return -EINVAL;
292 
293 	local_irq_disable();
294 	rtc_wait_not_busy(rtc);
295 
296 	rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year);
297 	rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon);
298 	rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday);
299 	rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour);
300 	rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min);
301 	rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec);
302 
303 	local_irq_enable();
304 
305 	return 0;
306 }
307 
308 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
309 {
310 	struct omap_rtc *rtc = dev_get_drvdata(dev);
311 	u8 interrupts;
312 
313 	local_irq_disable();
314 	rtc_wait_not_busy(rtc);
315 
316 	alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG);
317 	alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG);
318 	alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG);
319 	alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG);
320 	alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG);
321 	alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG);
322 
323 	local_irq_enable();
324 
325 	bcd2tm(&alm->time);
326 
327 	interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
328 	alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM);
329 
330 	return 0;
331 }
332 
333 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
334 {
335 	struct omap_rtc *rtc = dev_get_drvdata(dev);
336 	u8 reg, irqwake_reg = 0;
337 
338 	if (tm2bcd(&alm->time) < 0)
339 		return -EINVAL;
340 
341 	local_irq_disable();
342 	rtc_wait_not_busy(rtc);
343 
344 	rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year);
345 	rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon);
346 	rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday);
347 	rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour);
348 	rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min);
349 	rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec);
350 
351 	reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
352 	if (rtc->type->has_irqwakeen)
353 		irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN);
354 
355 	if (alm->enabled) {
356 		reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
357 		irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
358 	} else {
359 		reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
360 		irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
361 	}
362 	rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg);
363 	if (rtc->type->has_irqwakeen)
364 		rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg);
365 
366 	local_irq_enable();
367 
368 	return 0;
369 }
370 
371 static struct omap_rtc *omap_rtc_power_off_rtc;
372 
373 /*
374  * omap_rtc_poweroff: RTC-controlled power off
375  *
376  * The RTC can be used to control an external PMIC via the pmic_power_en pin,
377  * which can be configured to transition to OFF on ALARM2 events.
378  *
379  * Notes:
380  * The two-second alarm offset is the shortest offset possible as the alarm
381  * registers must be set before the next timer update and the offset
382  * calculation is too heavy for everything to be done within a single access
383  * period (~15 us).
384  *
385  * Called with local interrupts disabled.
386  */
387 static void omap_rtc_power_off(void)
388 {
389 	struct omap_rtc *rtc = omap_rtc_power_off_rtc;
390 	struct rtc_time tm;
391 	unsigned long now;
392 	u32 val;
393 
394 	/* enable pmic_power_en control */
395 	val = rtc_readl(rtc, OMAP_RTC_PMIC_REG);
396 	rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN);
397 
398 	/* set alarm two seconds from now */
399 	omap_rtc_read_time_raw(rtc, &tm);
400 	bcd2tm(&tm);
401 	rtc_tm_to_time(&tm, &now);
402 	rtc_time_to_tm(now + 2, &tm);
403 
404 	if (tm2bcd(&tm) < 0) {
405 		dev_err(&rtc->rtc->dev, "power off failed\n");
406 		return;
407 	}
408 
409 	rtc_wait_not_busy(rtc);
410 
411 	rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec);
412 	rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min);
413 	rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour);
414 	rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday);
415 	rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon);
416 	rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year);
417 
418 	/*
419 	 * enable ALARM2 interrupt
420 	 *
421 	 * NOTE: this fails on AM3352 if rtc_write (writeb) is used
422 	 */
423 	val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
424 	rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG,
425 			val | OMAP_RTC_INTERRUPTS_IT_ALARM2);
426 
427 	/*
428 	 * Wait for alarm to trigger (within two seconds) and external PMIC to
429 	 * power off the system. Add a 500 ms margin for external latencies
430 	 * (e.g. debounce circuits).
431 	 */
432 	mdelay(2500);
433 }
434 
435 static struct rtc_class_ops omap_rtc_ops = {
436 	.read_time	= omap_rtc_read_time,
437 	.set_time	= omap_rtc_set_time,
438 	.read_alarm	= omap_rtc_read_alarm,
439 	.set_alarm	= omap_rtc_set_alarm,
440 	.alarm_irq_enable = omap_rtc_alarm_irq_enable,
441 };
442 
443 static const struct omap_rtc_device_type omap_rtc_default_type = {
444 	.has_power_up_reset = true,
445 };
446 
447 static const struct omap_rtc_device_type omap_rtc_am3352_type = {
448 	.has_32kclk_en	= true,
449 	.has_kicker	= true,
450 	.has_irqwakeen	= true,
451 	.has_pmic_mode	= true,
452 };
453 
454 static const struct omap_rtc_device_type omap_rtc_da830_type = {
455 	.has_kicker	= true,
456 };
457 
458 static const struct platform_device_id omap_rtc_id_table[] = {
459 	{
460 		.name	= "omap_rtc",
461 		.driver_data = (kernel_ulong_t)&omap_rtc_default_type,
462 	}, {
463 		.name	= "am3352-rtc",
464 		.driver_data = (kernel_ulong_t)&omap_rtc_am3352_type,
465 	}, {
466 		.name	= "da830-rtc",
467 		.driver_data = (kernel_ulong_t)&omap_rtc_da830_type,
468 	}, {
469 		/* sentinel */
470 	}
471 };
472 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table);
473 
474 static const struct of_device_id omap_rtc_of_match[] = {
475 	{
476 		.compatible	= "ti,am3352-rtc",
477 		.data		= &omap_rtc_am3352_type,
478 	}, {
479 		.compatible	= "ti,da830-rtc",
480 		.data		= &omap_rtc_da830_type,
481 	}, {
482 		/* sentinel */
483 	}
484 };
485 MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
486 
487 static int __init omap_rtc_probe(struct platform_device *pdev)
488 {
489 	struct omap_rtc	*rtc;
490 	struct resource	*res;
491 	u8 reg, mask, new_ctrl;
492 	const struct platform_device_id *id_entry;
493 	const struct of_device_id *of_id;
494 	int ret;
495 
496 	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
497 	if (!rtc)
498 		return -ENOMEM;
499 
500 	of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
501 	if (of_id) {
502 		rtc->type = of_id->data;
503 		rtc->is_pmic_controller = rtc->type->has_pmic_mode &&
504 				of_property_read_bool(pdev->dev.of_node,
505 						"system-power-controller");
506 	} else {
507 		id_entry = platform_get_device_id(pdev);
508 		rtc->type = (void *)id_entry->driver_data;
509 	}
510 
511 	rtc->irq_timer = platform_get_irq(pdev, 0);
512 	if (rtc->irq_timer <= 0)
513 		return -ENOENT;
514 
515 	rtc->irq_alarm = platform_get_irq(pdev, 1);
516 	if (rtc->irq_alarm <= 0)
517 		return -ENOENT;
518 
519 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
520 	rtc->base = devm_ioremap_resource(&pdev->dev, res);
521 	if (IS_ERR(rtc->base))
522 		return PTR_ERR(rtc->base);
523 
524 	platform_set_drvdata(pdev, rtc);
525 
526 	/* Enable the clock/module so that we can access the registers */
527 	pm_runtime_enable(&pdev->dev);
528 	pm_runtime_get_sync(&pdev->dev);
529 
530 	if (rtc->type->has_kicker) {
531 		rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE);
532 		rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE);
533 	}
534 
535 	/*
536 	 * disable interrupts
537 	 *
538 	 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
539 	 */
540 	rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
541 
542 	/* enable RTC functional clock */
543 	if (rtc->type->has_32kclk_en) {
544 		reg = rtc_read(rtc, OMAP_RTC_OSC_REG);
545 		rtc_writel(rtc, OMAP_RTC_OSC_REG,
546 				reg | OMAP_RTC_OSC_32KCLK_EN);
547 	}
548 
549 	/* clear old status */
550 	reg = rtc_read(rtc, OMAP_RTC_STATUS_REG);
551 
552 	mask = OMAP_RTC_STATUS_ALARM;
553 
554 	if (rtc->type->has_pmic_mode)
555 		mask |= OMAP_RTC_STATUS_ALARM2;
556 
557 	if (rtc->type->has_power_up_reset) {
558 		mask |= OMAP_RTC_STATUS_POWER_UP;
559 		if (reg & OMAP_RTC_STATUS_POWER_UP)
560 			dev_info(&pdev->dev, "RTC power up reset detected\n");
561 	}
562 
563 	if (reg & mask)
564 		rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask);
565 
566 	/* On boards with split power, RTC_ON_NOFF won't reset the RTC */
567 	reg = rtc_read(rtc, OMAP_RTC_CTRL_REG);
568 	if (reg & OMAP_RTC_CTRL_STOP)
569 		dev_info(&pdev->dev, "already running\n");
570 
571 	/* force to 24 hour mode */
572 	new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
573 	new_ctrl |= OMAP_RTC_CTRL_STOP;
574 
575 	/*
576 	 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
577 	 *
578 	 *  - Device wake-up capability setting should come through chip
579 	 *    init logic. OMAP1 boards should initialize the "wakeup capable"
580 	 *    flag in the platform device if the board is wired right for
581 	 *    being woken up by RTC alarm. For OMAP-L138, this capability
582 	 *    is built into the SoC by the "Deep Sleep" capability.
583 	 *
584 	 *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
585 	 *    rather than nPWRON_RESET, should forcibly enable split
586 	 *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
587 	 *    is write-only, and always reads as zero...)
588 	 */
589 
590 	if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
591 		dev_info(&pdev->dev, "split power mode\n");
592 
593 	if (reg != new_ctrl)
594 		rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl);
595 
596 	device_init_wakeup(&pdev->dev, true);
597 
598 	rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
599 			&omap_rtc_ops, THIS_MODULE);
600 	if (IS_ERR(rtc->rtc)) {
601 		ret = PTR_ERR(rtc->rtc);
602 		goto err;
603 	}
604 
605 	/* handle periodic and alarm irqs */
606 	ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0,
607 			dev_name(&rtc->rtc->dev), rtc);
608 	if (ret)
609 		goto err;
610 
611 	if (rtc->irq_timer != rtc->irq_alarm) {
612 		ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0,
613 				dev_name(&rtc->rtc->dev), rtc);
614 		if (ret)
615 			goto err;
616 	}
617 
618 	if (rtc->is_pmic_controller) {
619 		if (!pm_power_off) {
620 			omap_rtc_power_off_rtc = rtc;
621 			pm_power_off = omap_rtc_power_off;
622 		}
623 	}
624 
625 	return 0;
626 
627 err:
628 	device_init_wakeup(&pdev->dev, false);
629 	if (rtc->type->has_kicker)
630 		rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
631 	pm_runtime_put_sync(&pdev->dev);
632 	pm_runtime_disable(&pdev->dev);
633 
634 	return ret;
635 }
636 
637 static int __exit omap_rtc_remove(struct platform_device *pdev)
638 {
639 	struct omap_rtc *rtc = platform_get_drvdata(pdev);
640 
641 	if (pm_power_off == omap_rtc_power_off &&
642 			omap_rtc_power_off_rtc == rtc) {
643 		pm_power_off = NULL;
644 		omap_rtc_power_off_rtc = NULL;
645 	}
646 
647 	device_init_wakeup(&pdev->dev, 0);
648 
649 	/* leave rtc running, but disable irqs */
650 	rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
651 
652 	if (rtc->type->has_kicker)
653 		rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0);
654 
655 	/* Disable the clock/module */
656 	pm_runtime_put_sync(&pdev->dev);
657 	pm_runtime_disable(&pdev->dev);
658 
659 	return 0;
660 }
661 
662 #ifdef CONFIG_PM_SLEEP
663 static int omap_rtc_suspend(struct device *dev)
664 {
665 	struct omap_rtc *rtc = dev_get_drvdata(dev);
666 
667 	rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
668 
669 	/*
670 	 * FIXME: the RTC alarm is not currently acting as a wakeup event
671 	 * source on some platforms, and in fact this enable() call is just
672 	 * saving a flag that's never used...
673 	 */
674 	if (device_may_wakeup(dev))
675 		enable_irq_wake(rtc->irq_alarm);
676 	else
677 		rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0);
678 
679 	/* Disable the clock/module */
680 	pm_runtime_put_sync(dev);
681 
682 	return 0;
683 }
684 
685 static int omap_rtc_resume(struct device *dev)
686 {
687 	struct omap_rtc *rtc = dev_get_drvdata(dev);
688 
689 	/* Enable the clock/module so that we can access the registers */
690 	pm_runtime_get_sync(dev);
691 
692 	if (device_may_wakeup(dev))
693 		disable_irq_wake(rtc->irq_alarm);
694 	else
695 		rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg);
696 
697 	return 0;
698 }
699 #endif
700 
701 static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume);
702 
703 static void omap_rtc_shutdown(struct platform_device *pdev)
704 {
705 	struct omap_rtc *rtc = platform_get_drvdata(pdev);
706 	u8 mask;
707 
708 	/*
709 	 * Keep the ALARM interrupt enabled to allow the system to power up on
710 	 * alarm events.
711 	 */
712 	mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG);
713 	mask &= OMAP_RTC_INTERRUPTS_IT_ALARM;
714 	rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask);
715 }
716 
717 static struct platform_driver omap_rtc_driver = {
718 	.remove		= __exit_p(omap_rtc_remove),
719 	.shutdown	= omap_rtc_shutdown,
720 	.driver		= {
721 		.name	= "omap_rtc",
722 		.pm	= &omap_rtc_pm_ops,
723 		.of_match_table = omap_rtc_of_match,
724 	},
725 	.id_table	= omap_rtc_id_table,
726 };
727 
728 module_platform_driver_probe(omap_rtc_driver, omap_rtc_probe);
729 
730 MODULE_ALIAS("platform:omap_rtc");
731 MODULE_AUTHOR("George G. Davis (and others)");
732 MODULE_LICENSE("GPL");
733