1 /* 2 * TI OMAP Real Time Clock interface for Linux 3 * 4 * Copyright (C) 2003 MontaVista Software, Inc. 5 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> 6 * 7 * Copyright (C) 2006 David Brownell (new RTC framework) 8 * Copyright (C) 2014 Johan Hovold <johan@kernel.org> 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 */ 15 16 #include <dt-bindings/gpio/gpio.h> 17 #include <linux/bcd.h> 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/init.h> 21 #include <linux/io.h> 22 #include <linux/ioport.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/rtc.h> 33 34 /* 35 * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock 36 * with century-range alarm matching, driven by the 32kHz clock. 37 * 38 * The main user-visible ways it differs from PC RTCs are by omitting 39 * "don't care" alarm fields and sub-second periodic IRQs, and having 40 * an autoadjust mechanism to calibrate to the true oscillator rate. 41 * 42 * Board-specific wiring options include using split power mode with 43 * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), 44 * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from 45 * low power modes) for OMAP1 boards (OMAP-L138 has this built into 46 * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. 47 */ 48 49 /* RTC registers */ 50 #define OMAP_RTC_SECONDS_REG 0x00 51 #define OMAP_RTC_MINUTES_REG 0x04 52 #define OMAP_RTC_HOURS_REG 0x08 53 #define OMAP_RTC_DAYS_REG 0x0C 54 #define OMAP_RTC_MONTHS_REG 0x10 55 #define OMAP_RTC_YEARS_REG 0x14 56 #define OMAP_RTC_WEEKS_REG 0x18 57 58 #define OMAP_RTC_ALARM_SECONDS_REG 0x20 59 #define OMAP_RTC_ALARM_MINUTES_REG 0x24 60 #define OMAP_RTC_ALARM_HOURS_REG 0x28 61 #define OMAP_RTC_ALARM_DAYS_REG 0x2c 62 #define OMAP_RTC_ALARM_MONTHS_REG 0x30 63 #define OMAP_RTC_ALARM_YEARS_REG 0x34 64 65 #define OMAP_RTC_CTRL_REG 0x40 66 #define OMAP_RTC_STATUS_REG 0x44 67 #define OMAP_RTC_INTERRUPTS_REG 0x48 68 69 #define OMAP_RTC_COMP_LSB_REG 0x4c 70 #define OMAP_RTC_COMP_MSB_REG 0x50 71 #define OMAP_RTC_OSC_REG 0x54 72 73 #define OMAP_RTC_SCRATCH0_REG 0x60 74 #define OMAP_RTC_SCRATCH1_REG 0x64 75 #define OMAP_RTC_SCRATCH2_REG 0x68 76 77 #define OMAP_RTC_KICK0_REG 0x6c 78 #define OMAP_RTC_KICK1_REG 0x70 79 80 #define OMAP_RTC_IRQWAKEEN 0x7c 81 82 #define OMAP_RTC_ALARM2_SECONDS_REG 0x80 83 #define OMAP_RTC_ALARM2_MINUTES_REG 0x84 84 #define OMAP_RTC_ALARM2_HOURS_REG 0x88 85 #define OMAP_RTC_ALARM2_DAYS_REG 0x8c 86 #define OMAP_RTC_ALARM2_MONTHS_REG 0x90 87 #define OMAP_RTC_ALARM2_YEARS_REG 0x94 88 89 #define OMAP_RTC_PMIC_REG 0x98 90 91 /* OMAP_RTC_CTRL_REG bit fields: */ 92 #define OMAP_RTC_CTRL_SPLIT BIT(7) 93 #define OMAP_RTC_CTRL_DISABLE BIT(6) 94 #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) 95 #define OMAP_RTC_CTRL_TEST BIT(4) 96 #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) 97 #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) 98 #define OMAP_RTC_CTRL_ROUND_30S BIT(1) 99 #define OMAP_RTC_CTRL_STOP BIT(0) 100 101 /* OMAP_RTC_STATUS_REG bit fields: */ 102 #define OMAP_RTC_STATUS_POWER_UP BIT(7) 103 #define OMAP_RTC_STATUS_ALARM2 BIT(7) 104 #define OMAP_RTC_STATUS_ALARM BIT(6) 105 #define OMAP_RTC_STATUS_1D_EVENT BIT(5) 106 #define OMAP_RTC_STATUS_1H_EVENT BIT(4) 107 #define OMAP_RTC_STATUS_1M_EVENT BIT(3) 108 #define OMAP_RTC_STATUS_1S_EVENT BIT(2) 109 #define OMAP_RTC_STATUS_RUN BIT(1) 110 #define OMAP_RTC_STATUS_BUSY BIT(0) 111 112 /* OMAP_RTC_INTERRUPTS_REG bit fields: */ 113 #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4) 114 #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) 115 #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) 116 117 /* OMAP_RTC_OSC_REG bit fields: */ 118 #define OMAP_RTC_OSC_32KCLK_EN BIT(6) 119 #define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3) 120 #define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4) 121 122 /* OMAP_RTC_IRQWAKEEN bit fields: */ 123 #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) 124 125 /* OMAP_RTC_PMIC bit fields: */ 126 #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16) 127 #define OMAP_RTC_PMIC_EXT_WKUP_EN(x) BIT(x) 128 #define OMAP_RTC_PMIC_EXT_WKUP_POL(x) BIT(4 + x) 129 130 /* OMAP_RTC_KICKER values */ 131 #define KICK0_VALUE 0x83e70b13 132 #define KICK1_VALUE 0x95a4f1e0 133 134 struct omap_rtc; 135 136 struct omap_rtc_device_type { 137 bool has_32kclk_en; 138 bool has_irqwakeen; 139 bool has_pmic_mode; 140 bool has_power_up_reset; 141 void (*lock)(struct omap_rtc *rtc); 142 void (*unlock)(struct omap_rtc *rtc); 143 }; 144 145 struct omap_rtc { 146 struct rtc_device *rtc; 147 void __iomem *base; 148 struct clk *clk; 149 int irq_alarm; 150 int irq_timer; 151 u8 interrupts_reg; 152 bool is_pmic_controller; 153 bool has_ext_clk; 154 bool is_suspending; 155 const struct omap_rtc_device_type *type; 156 struct pinctrl_dev *pctldev; 157 }; 158 159 static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) 160 { 161 return readb(rtc->base + reg); 162 } 163 164 static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg) 165 { 166 return readl(rtc->base + reg); 167 } 168 169 static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) 170 { 171 writeb(val, rtc->base + reg); 172 } 173 174 static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) 175 { 176 writel(val, rtc->base + reg); 177 } 178 179 static void am3352_rtc_unlock(struct omap_rtc *rtc) 180 { 181 rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); 182 rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); 183 } 184 185 static void am3352_rtc_lock(struct omap_rtc *rtc) 186 { 187 rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); 188 rtc_writel(rtc, OMAP_RTC_KICK1_REG, 0); 189 } 190 191 static void default_rtc_unlock(struct omap_rtc *rtc) 192 { 193 } 194 195 static void default_rtc_lock(struct omap_rtc *rtc) 196 { 197 } 198 199 /* 200 * We rely on the rtc framework to handle locking (rtc->ops_lock), 201 * so the only other requirement is that register accesses which 202 * require BUSY to be clear are made with IRQs locally disabled 203 */ 204 static void rtc_wait_not_busy(struct omap_rtc *rtc) 205 { 206 int count; 207 u8 status; 208 209 /* BUSY may stay active for 1/32768 second (~30 usec) */ 210 for (count = 0; count < 50; count++) { 211 status = rtc_read(rtc, OMAP_RTC_STATUS_REG); 212 if (!(status & OMAP_RTC_STATUS_BUSY)) 213 break; 214 udelay(1); 215 } 216 /* now we have ~15 usec to read/write various registers */ 217 } 218 219 static irqreturn_t rtc_irq(int irq, void *dev_id) 220 { 221 struct omap_rtc *rtc = dev_id; 222 unsigned long events = 0; 223 u8 irq_data; 224 225 irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); 226 227 /* alarm irq? */ 228 if (irq_data & OMAP_RTC_STATUS_ALARM) { 229 rtc->type->unlock(rtc); 230 rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); 231 rtc->type->lock(rtc); 232 events |= RTC_IRQF | RTC_AF; 233 } 234 235 /* 1/sec periodic/update irq? */ 236 if (irq_data & OMAP_RTC_STATUS_1S_EVENT) 237 events |= RTC_IRQF | RTC_UF; 238 239 rtc_update_irq(rtc->rtc, 1, events); 240 241 return IRQ_HANDLED; 242 } 243 244 static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 245 { 246 struct omap_rtc *rtc = dev_get_drvdata(dev); 247 u8 reg, irqwake_reg = 0; 248 249 local_irq_disable(); 250 rtc_wait_not_busy(rtc); 251 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 252 if (rtc->type->has_irqwakeen) 253 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); 254 255 if (enabled) { 256 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; 257 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; 258 } else { 259 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; 260 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; 261 } 262 rtc_wait_not_busy(rtc); 263 rtc->type->unlock(rtc); 264 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); 265 if (rtc->type->has_irqwakeen) 266 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); 267 rtc->type->lock(rtc); 268 local_irq_enable(); 269 270 return 0; 271 } 272 273 /* this hardware doesn't support "don't care" alarm fields */ 274 static int tm2bcd(struct rtc_time *tm) 275 { 276 if (rtc_valid_tm(tm) != 0) 277 return -EINVAL; 278 279 tm->tm_sec = bin2bcd(tm->tm_sec); 280 tm->tm_min = bin2bcd(tm->tm_min); 281 tm->tm_hour = bin2bcd(tm->tm_hour); 282 tm->tm_mday = bin2bcd(tm->tm_mday); 283 284 tm->tm_mon = bin2bcd(tm->tm_mon + 1); 285 286 /* epoch == 1900 */ 287 if (tm->tm_year < 100 || tm->tm_year > 199) 288 return -EINVAL; 289 tm->tm_year = bin2bcd(tm->tm_year - 100); 290 291 return 0; 292 } 293 294 static void bcd2tm(struct rtc_time *tm) 295 { 296 tm->tm_sec = bcd2bin(tm->tm_sec); 297 tm->tm_min = bcd2bin(tm->tm_min); 298 tm->tm_hour = bcd2bin(tm->tm_hour); 299 tm->tm_mday = bcd2bin(tm->tm_mday); 300 tm->tm_mon = bcd2bin(tm->tm_mon) - 1; 301 /* epoch == 1900 */ 302 tm->tm_year = bcd2bin(tm->tm_year) + 100; 303 } 304 305 static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm) 306 { 307 tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); 308 tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); 309 tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); 310 tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); 311 tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); 312 tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); 313 } 314 315 static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) 316 { 317 struct omap_rtc *rtc = dev_get_drvdata(dev); 318 319 /* we don't report wday/yday/isdst ... */ 320 local_irq_disable(); 321 rtc_wait_not_busy(rtc); 322 omap_rtc_read_time_raw(rtc, tm); 323 local_irq_enable(); 324 325 bcd2tm(tm); 326 327 return 0; 328 } 329 330 static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) 331 { 332 struct omap_rtc *rtc = dev_get_drvdata(dev); 333 334 if (tm2bcd(tm) < 0) 335 return -EINVAL; 336 337 local_irq_disable(); 338 rtc_wait_not_busy(rtc); 339 340 rtc->type->unlock(rtc); 341 rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); 342 rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); 343 rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); 344 rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); 345 rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); 346 rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); 347 rtc->type->lock(rtc); 348 349 local_irq_enable(); 350 351 return 0; 352 } 353 354 static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) 355 { 356 struct omap_rtc *rtc = dev_get_drvdata(dev); 357 u8 interrupts; 358 359 local_irq_disable(); 360 rtc_wait_not_busy(rtc); 361 362 alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); 363 alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); 364 alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); 365 alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); 366 alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); 367 alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); 368 369 local_irq_enable(); 370 371 bcd2tm(&alm->time); 372 373 interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 374 alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM); 375 376 return 0; 377 } 378 379 static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) 380 { 381 struct omap_rtc *rtc = dev_get_drvdata(dev); 382 u8 reg, irqwake_reg = 0; 383 384 if (tm2bcd(&alm->time) < 0) 385 return -EINVAL; 386 387 local_irq_disable(); 388 rtc_wait_not_busy(rtc); 389 390 rtc->type->unlock(rtc); 391 rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); 392 rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); 393 rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); 394 rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); 395 rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); 396 rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); 397 398 reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 399 if (rtc->type->has_irqwakeen) 400 irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); 401 402 if (alm->enabled) { 403 reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; 404 irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; 405 } else { 406 reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; 407 irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; 408 } 409 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); 410 if (rtc->type->has_irqwakeen) 411 rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); 412 rtc->type->lock(rtc); 413 414 local_irq_enable(); 415 416 return 0; 417 } 418 419 static struct omap_rtc *omap_rtc_power_off_rtc; 420 421 /* 422 * omap_rtc_poweroff: RTC-controlled power off 423 * 424 * The RTC can be used to control an external PMIC via the pmic_power_en pin, 425 * which can be configured to transition to OFF on ALARM2 events. 426 * 427 * Notes: 428 * The two-second alarm offset is the shortest offset possible as the alarm 429 * registers must be set before the next timer update and the offset 430 * calculation is too heavy for everything to be done within a single access 431 * period (~15 us). 432 * 433 * Called with local interrupts disabled. 434 */ 435 static void omap_rtc_power_off(void) 436 { 437 struct omap_rtc *rtc = omap_rtc_power_off_rtc; 438 struct rtc_time tm; 439 unsigned long now; 440 u32 val; 441 442 rtc->type->unlock(rtc); 443 /* enable pmic_power_en control */ 444 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); 445 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN); 446 447 /* set alarm two seconds from now */ 448 omap_rtc_read_time_raw(rtc, &tm); 449 bcd2tm(&tm); 450 rtc_tm_to_time(&tm, &now); 451 rtc_time_to_tm(now + 2, &tm); 452 453 if (tm2bcd(&tm) < 0) { 454 dev_err(&rtc->rtc->dev, "power off failed\n"); 455 return; 456 } 457 458 rtc_wait_not_busy(rtc); 459 460 rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec); 461 rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min); 462 rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour); 463 rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday); 464 rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon); 465 rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year); 466 467 /* 468 * enable ALARM2 interrupt 469 * 470 * NOTE: this fails on AM3352 if rtc_write (writeb) is used 471 */ 472 val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 473 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 474 val | OMAP_RTC_INTERRUPTS_IT_ALARM2); 475 rtc->type->lock(rtc); 476 477 /* 478 * Wait for alarm to trigger (within two seconds) and external PMIC to 479 * power off the system. Add a 500 ms margin for external latencies 480 * (e.g. debounce circuits). 481 */ 482 mdelay(2500); 483 } 484 485 static const struct rtc_class_ops omap_rtc_ops = { 486 .read_time = omap_rtc_read_time, 487 .set_time = omap_rtc_set_time, 488 .read_alarm = omap_rtc_read_alarm, 489 .set_alarm = omap_rtc_set_alarm, 490 .alarm_irq_enable = omap_rtc_alarm_irq_enable, 491 }; 492 493 static const struct omap_rtc_device_type omap_rtc_default_type = { 494 .has_power_up_reset = true, 495 .lock = default_rtc_lock, 496 .unlock = default_rtc_unlock, 497 }; 498 499 static const struct omap_rtc_device_type omap_rtc_am3352_type = { 500 .has_32kclk_en = true, 501 .has_irqwakeen = true, 502 .has_pmic_mode = true, 503 .lock = am3352_rtc_lock, 504 .unlock = am3352_rtc_unlock, 505 }; 506 507 static const struct omap_rtc_device_type omap_rtc_da830_type = { 508 .lock = am3352_rtc_lock, 509 .unlock = am3352_rtc_unlock, 510 }; 511 512 static const struct platform_device_id omap_rtc_id_table[] = { 513 { 514 .name = "omap_rtc", 515 .driver_data = (kernel_ulong_t)&omap_rtc_default_type, 516 }, { 517 .name = "am3352-rtc", 518 .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type, 519 }, { 520 .name = "da830-rtc", 521 .driver_data = (kernel_ulong_t)&omap_rtc_da830_type, 522 }, { 523 /* sentinel */ 524 } 525 }; 526 MODULE_DEVICE_TABLE(platform, omap_rtc_id_table); 527 528 static const struct of_device_id omap_rtc_of_match[] = { 529 { 530 .compatible = "ti,am3352-rtc", 531 .data = &omap_rtc_am3352_type, 532 }, { 533 .compatible = "ti,da830-rtc", 534 .data = &omap_rtc_da830_type, 535 }, { 536 /* sentinel */ 537 } 538 }; 539 MODULE_DEVICE_TABLE(of, omap_rtc_of_match); 540 541 static const struct pinctrl_pin_desc rtc_pins_desc[] = { 542 PINCTRL_PIN(0, "ext_wakeup0"), 543 PINCTRL_PIN(1, "ext_wakeup1"), 544 PINCTRL_PIN(2, "ext_wakeup2"), 545 PINCTRL_PIN(3, "ext_wakeup3"), 546 }; 547 548 static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 549 { 550 return 0; 551 } 552 553 static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 554 unsigned int group) 555 { 556 return NULL; 557 } 558 559 static const struct pinctrl_ops rtc_pinctrl_ops = { 560 .get_groups_count = rtc_pinctrl_get_groups_count, 561 .get_group_name = rtc_pinctrl_get_group_name, 562 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 563 .dt_free_map = pinconf_generic_dt_free_map, 564 }; 565 566 enum rtc_pin_config_param { 567 PIN_CONFIG_ACTIVE_HIGH = PIN_CONFIG_END + 1, 568 }; 569 570 static const struct pinconf_generic_params rtc_params[] = { 571 {"ti,active-high", PIN_CONFIG_ACTIVE_HIGH, 0}, 572 }; 573 574 #ifdef CONFIG_DEBUG_FS 575 static const struct pin_config_item rtc_conf_items[ARRAY_SIZE(rtc_params)] = { 576 PCONFDUMP(PIN_CONFIG_ACTIVE_HIGH, "input active high", NULL, false), 577 }; 578 #endif 579 580 static int rtc_pinconf_get(struct pinctrl_dev *pctldev, 581 unsigned int pin, unsigned long *config) 582 { 583 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); 584 unsigned int param = pinconf_to_config_param(*config); 585 u32 val; 586 u16 arg = 0; 587 588 rtc->type->unlock(rtc); 589 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); 590 rtc->type->lock(rtc); 591 592 switch (param) { 593 case PIN_CONFIG_INPUT_ENABLE: 594 if (!(val & OMAP_RTC_PMIC_EXT_WKUP_EN(pin))) 595 return -EINVAL; 596 break; 597 case PIN_CONFIG_ACTIVE_HIGH: 598 if (val & OMAP_RTC_PMIC_EXT_WKUP_POL(pin)) 599 return -EINVAL; 600 break; 601 default: 602 return -ENOTSUPP; 603 }; 604 605 *config = pinconf_to_config_packed(param, arg); 606 607 return 0; 608 } 609 610 static int rtc_pinconf_set(struct pinctrl_dev *pctldev, 611 unsigned int pin, unsigned long *configs, 612 unsigned int num_configs) 613 { 614 struct omap_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); 615 u32 val; 616 unsigned int param; 617 u32 param_val; 618 int i; 619 620 rtc->type->unlock(rtc); 621 val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); 622 rtc->type->lock(rtc); 623 624 /* active low by default */ 625 val |= OMAP_RTC_PMIC_EXT_WKUP_POL(pin); 626 627 for (i = 0; i < num_configs; i++) { 628 param = pinconf_to_config_param(configs[i]); 629 param_val = pinconf_to_config_argument(configs[i]); 630 631 switch (param) { 632 case PIN_CONFIG_INPUT_ENABLE: 633 if (param_val) 634 val |= OMAP_RTC_PMIC_EXT_WKUP_EN(pin); 635 else 636 val &= ~OMAP_RTC_PMIC_EXT_WKUP_EN(pin); 637 break; 638 case PIN_CONFIG_ACTIVE_HIGH: 639 val &= ~OMAP_RTC_PMIC_EXT_WKUP_POL(pin); 640 break; 641 default: 642 dev_err(&rtc->rtc->dev, "Property %u not supported\n", 643 param); 644 return -ENOTSUPP; 645 } 646 } 647 648 rtc->type->unlock(rtc); 649 rtc_writel(rtc, OMAP_RTC_PMIC_REG, val); 650 rtc->type->lock(rtc); 651 652 return 0; 653 } 654 655 static const struct pinconf_ops rtc_pinconf_ops = { 656 .is_generic = true, 657 .pin_config_get = rtc_pinconf_get, 658 .pin_config_set = rtc_pinconf_set, 659 }; 660 661 static struct pinctrl_desc rtc_pinctrl_desc = { 662 .pins = rtc_pins_desc, 663 .npins = ARRAY_SIZE(rtc_pins_desc), 664 .pctlops = &rtc_pinctrl_ops, 665 .confops = &rtc_pinconf_ops, 666 .custom_params = rtc_params, 667 .num_custom_params = ARRAY_SIZE(rtc_params), 668 #ifdef CONFIG_DEBUG_FS 669 .custom_conf_items = rtc_conf_items, 670 #endif 671 .owner = THIS_MODULE, 672 }; 673 674 static int omap_rtc_scratch_read(void *priv, unsigned int offset, void *_val, 675 size_t bytes) 676 { 677 struct omap_rtc *rtc = priv; 678 u32 *val = _val; 679 int i; 680 681 for (i = 0; i < bytes / 4; i++) 682 val[i] = rtc_readl(rtc, 683 OMAP_RTC_SCRATCH0_REG + offset + (i * 4)); 684 685 return 0; 686 } 687 688 static int omap_rtc_scratch_write(void *priv, unsigned int offset, void *_val, 689 size_t bytes) 690 { 691 struct omap_rtc *rtc = priv; 692 u32 *val = _val; 693 int i; 694 695 rtc->type->unlock(rtc); 696 for (i = 0; i < bytes / 4; i++) 697 rtc_writel(rtc, 698 OMAP_RTC_SCRATCH0_REG + offset + (i * 4), val[i]); 699 rtc->type->lock(rtc); 700 701 return 0; 702 } 703 704 static struct nvmem_config omap_rtc_nvmem_config = { 705 .name = "omap_rtc_scratch", 706 .word_size = 4, 707 .stride = 4, 708 .size = OMAP_RTC_KICK0_REG - OMAP_RTC_SCRATCH0_REG, 709 .reg_read = omap_rtc_scratch_read, 710 .reg_write = omap_rtc_scratch_write, 711 }; 712 713 static int omap_rtc_probe(struct platform_device *pdev) 714 { 715 struct omap_rtc *rtc; 716 struct resource *res; 717 u8 reg, mask, new_ctrl; 718 const struct platform_device_id *id_entry; 719 const struct of_device_id *of_id; 720 int ret; 721 722 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 723 if (!rtc) 724 return -ENOMEM; 725 726 of_id = of_match_device(omap_rtc_of_match, &pdev->dev); 727 if (of_id) { 728 rtc->type = of_id->data; 729 rtc->is_pmic_controller = rtc->type->has_pmic_mode && 730 of_property_read_bool(pdev->dev.of_node, 731 "system-power-controller"); 732 } else { 733 id_entry = platform_get_device_id(pdev); 734 rtc->type = (void *)id_entry->driver_data; 735 } 736 737 rtc->irq_timer = platform_get_irq(pdev, 0); 738 if (rtc->irq_timer <= 0) 739 return -ENOENT; 740 741 rtc->irq_alarm = platform_get_irq(pdev, 1); 742 if (rtc->irq_alarm <= 0) 743 return -ENOENT; 744 745 rtc->clk = devm_clk_get(&pdev->dev, "ext-clk"); 746 if (!IS_ERR(rtc->clk)) 747 rtc->has_ext_clk = true; 748 else 749 rtc->clk = devm_clk_get(&pdev->dev, "int-clk"); 750 751 if (!IS_ERR(rtc->clk)) 752 clk_prepare_enable(rtc->clk); 753 754 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 755 rtc->base = devm_ioremap_resource(&pdev->dev, res); 756 if (IS_ERR(rtc->base)) { 757 clk_disable_unprepare(rtc->clk); 758 return PTR_ERR(rtc->base); 759 } 760 761 platform_set_drvdata(pdev, rtc); 762 763 /* Enable the clock/module so that we can access the registers */ 764 pm_runtime_enable(&pdev->dev); 765 pm_runtime_get_sync(&pdev->dev); 766 767 rtc->type->unlock(rtc); 768 769 /* 770 * disable interrupts 771 * 772 * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used 773 */ 774 rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); 775 776 /* enable RTC functional clock */ 777 if (rtc->type->has_32kclk_en) { 778 reg = rtc_read(rtc, OMAP_RTC_OSC_REG); 779 rtc_writel(rtc, OMAP_RTC_OSC_REG, 780 reg | OMAP_RTC_OSC_32KCLK_EN); 781 } 782 783 /* clear old status */ 784 reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); 785 786 mask = OMAP_RTC_STATUS_ALARM; 787 788 if (rtc->type->has_pmic_mode) 789 mask |= OMAP_RTC_STATUS_ALARM2; 790 791 if (rtc->type->has_power_up_reset) { 792 mask |= OMAP_RTC_STATUS_POWER_UP; 793 if (reg & OMAP_RTC_STATUS_POWER_UP) 794 dev_info(&pdev->dev, "RTC power up reset detected\n"); 795 } 796 797 if (reg & mask) 798 rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); 799 800 /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ 801 reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); 802 if (reg & OMAP_RTC_CTRL_STOP) 803 dev_info(&pdev->dev, "already running\n"); 804 805 /* force to 24 hour mode */ 806 new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); 807 new_ctrl |= OMAP_RTC_CTRL_STOP; 808 809 /* 810 * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: 811 * 812 * - Device wake-up capability setting should come through chip 813 * init logic. OMAP1 boards should initialize the "wakeup capable" 814 * flag in the platform device if the board is wired right for 815 * being woken up by RTC alarm. For OMAP-L138, this capability 816 * is built into the SoC by the "Deep Sleep" capability. 817 * 818 * - Boards wired so RTC_ON_nOFF is used as the reset signal, 819 * rather than nPWRON_RESET, should forcibly enable split 820 * power mode. (Some chip errata report that RTC_CTRL_SPLIT 821 * is write-only, and always reads as zero...) 822 */ 823 824 if (new_ctrl & OMAP_RTC_CTRL_SPLIT) 825 dev_info(&pdev->dev, "split power mode\n"); 826 827 if (reg != new_ctrl) 828 rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); 829 830 /* 831 * If we have the external clock then switch to it so we can keep 832 * ticking across suspend. 833 */ 834 if (rtc->has_ext_clk) { 835 reg = rtc_read(rtc, OMAP_RTC_OSC_REG); 836 reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE; 837 reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC; 838 rtc_writel(rtc, OMAP_RTC_OSC_REG, reg); 839 } 840 841 rtc->type->lock(rtc); 842 843 device_init_wakeup(&pdev->dev, true); 844 845 rtc->rtc = devm_rtc_allocate_device(&pdev->dev); 846 if (IS_ERR(rtc->rtc)) { 847 ret = PTR_ERR(rtc->rtc); 848 goto err; 849 } 850 851 rtc->rtc->ops = &omap_rtc_ops; 852 omap_rtc_nvmem_config.priv = rtc; 853 rtc->rtc->nvmem_config = &omap_rtc_nvmem_config; 854 855 /* handle periodic and alarm irqs */ 856 ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, 857 dev_name(&rtc->rtc->dev), rtc); 858 if (ret) 859 goto err; 860 861 if (rtc->irq_timer != rtc->irq_alarm) { 862 ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, 863 dev_name(&rtc->rtc->dev), rtc); 864 if (ret) 865 goto err; 866 } 867 868 if (rtc->is_pmic_controller) { 869 if (!pm_power_off) { 870 omap_rtc_power_off_rtc = rtc; 871 pm_power_off = omap_rtc_power_off; 872 } 873 } 874 875 /* Support ext_wakeup pinconf */ 876 rtc_pinctrl_desc.name = dev_name(&pdev->dev); 877 878 rtc->pctldev = pinctrl_register(&rtc_pinctrl_desc, &pdev->dev, rtc); 879 if (IS_ERR(rtc->pctldev)) { 880 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 881 ret = PTR_ERR(rtc->pctldev); 882 goto err; 883 } 884 885 ret = rtc_register_device(rtc->rtc); 886 if (ret) 887 goto err; 888 889 return 0; 890 891 err: 892 clk_disable_unprepare(rtc->clk); 893 device_init_wakeup(&pdev->dev, false); 894 rtc->type->lock(rtc); 895 pm_runtime_put_sync(&pdev->dev); 896 pm_runtime_disable(&pdev->dev); 897 898 return ret; 899 } 900 901 static int omap_rtc_remove(struct platform_device *pdev) 902 { 903 struct omap_rtc *rtc = platform_get_drvdata(pdev); 904 u8 reg; 905 906 if (pm_power_off == omap_rtc_power_off && 907 omap_rtc_power_off_rtc == rtc) { 908 pm_power_off = NULL; 909 omap_rtc_power_off_rtc = NULL; 910 } 911 912 device_init_wakeup(&pdev->dev, 0); 913 914 if (!IS_ERR(rtc->clk)) 915 clk_disable_unprepare(rtc->clk); 916 917 rtc->type->unlock(rtc); 918 /* leave rtc running, but disable irqs */ 919 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); 920 921 if (rtc->has_ext_clk) { 922 reg = rtc_read(rtc, OMAP_RTC_OSC_REG); 923 reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC; 924 rtc_write(rtc, OMAP_RTC_OSC_REG, reg); 925 } 926 927 rtc->type->lock(rtc); 928 929 /* Disable the clock/module */ 930 pm_runtime_put_sync(&pdev->dev); 931 pm_runtime_disable(&pdev->dev); 932 933 /* Remove ext_wakeup pinconf */ 934 pinctrl_unregister(rtc->pctldev); 935 936 return 0; 937 } 938 939 static int __maybe_unused omap_rtc_suspend(struct device *dev) 940 { 941 struct omap_rtc *rtc = dev_get_drvdata(dev); 942 943 rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 944 945 rtc->type->unlock(rtc); 946 /* 947 * FIXME: the RTC alarm is not currently acting as a wakeup event 948 * source on some platforms, and in fact this enable() call is just 949 * saving a flag that's never used... 950 */ 951 if (device_may_wakeup(dev)) 952 enable_irq_wake(rtc->irq_alarm); 953 else 954 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); 955 rtc->type->lock(rtc); 956 957 rtc->is_suspending = true; 958 959 return 0; 960 } 961 962 static int __maybe_unused omap_rtc_resume(struct device *dev) 963 { 964 struct omap_rtc *rtc = dev_get_drvdata(dev); 965 966 rtc->type->unlock(rtc); 967 if (device_may_wakeup(dev)) 968 disable_irq_wake(rtc->irq_alarm); 969 else 970 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); 971 rtc->type->lock(rtc); 972 973 rtc->is_suspending = false; 974 975 return 0; 976 } 977 978 static int __maybe_unused omap_rtc_runtime_suspend(struct device *dev) 979 { 980 struct omap_rtc *rtc = dev_get_drvdata(dev); 981 982 if (rtc->is_suspending && !rtc->has_ext_clk) 983 return -EBUSY; 984 985 return 0; 986 } 987 988 static const struct dev_pm_ops omap_rtc_pm_ops = { 989 SET_SYSTEM_SLEEP_PM_OPS(omap_rtc_suspend, omap_rtc_resume) 990 SET_RUNTIME_PM_OPS(omap_rtc_runtime_suspend, NULL, NULL) 991 }; 992 993 static void omap_rtc_shutdown(struct platform_device *pdev) 994 { 995 struct omap_rtc *rtc = platform_get_drvdata(pdev); 996 u8 mask; 997 998 /* 999 * Keep the ALARM interrupt enabled to allow the system to power up on 1000 * alarm events. 1001 */ 1002 rtc->type->unlock(rtc); 1003 mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); 1004 mask &= OMAP_RTC_INTERRUPTS_IT_ALARM; 1005 rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask); 1006 rtc->type->lock(rtc); 1007 } 1008 1009 static struct platform_driver omap_rtc_driver = { 1010 .probe = omap_rtc_probe, 1011 .remove = omap_rtc_remove, 1012 .shutdown = omap_rtc_shutdown, 1013 .driver = { 1014 .name = "omap_rtc", 1015 .pm = &omap_rtc_pm_ops, 1016 .of_match_table = omap_rtc_of_match, 1017 }, 1018 .id_table = omap_rtc_id_table, 1019 }; 1020 1021 module_platform_driver(omap_rtc_driver); 1022 1023 MODULE_ALIAS("platform:omap_rtc"); 1024 MODULE_AUTHOR("George G. Davis (and others)"); 1025 MODULE_LICENSE("GPL"); 1026