1 /* 2 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12 #include <linux/io.h> 13 #include <linux/rtc.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/interrupt.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 22 #define RTC_INPUT_CLK_32768HZ (0x00 << 5) 23 #define RTC_INPUT_CLK_32000HZ (0x01 << 5) 24 #define RTC_INPUT_CLK_38400HZ (0x02 << 5) 25 26 #define RTC_SW_BIT (1 << 0) 27 #define RTC_ALM_BIT (1 << 2) 28 #define RTC_1HZ_BIT (1 << 4) 29 #define RTC_2HZ_BIT (1 << 7) 30 #define RTC_SAM0_BIT (1 << 8) 31 #define RTC_SAM1_BIT (1 << 9) 32 #define RTC_SAM2_BIT (1 << 10) 33 #define RTC_SAM3_BIT (1 << 11) 34 #define RTC_SAM4_BIT (1 << 12) 35 #define RTC_SAM5_BIT (1 << 13) 36 #define RTC_SAM6_BIT (1 << 14) 37 #define RTC_SAM7_BIT (1 << 15) 38 #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \ 39 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \ 40 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT) 41 42 #define RTC_ENABLE_BIT (1 << 7) 43 44 #define MAX_PIE_NUM 9 45 #define MAX_PIE_FREQ 512 46 47 #define MXC_RTC_TIME 0 48 #define MXC_RTC_ALARM 1 49 50 #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */ 51 #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */ 52 #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */ 53 #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */ 54 #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */ 55 #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */ 56 #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */ 57 #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */ 58 #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */ 59 #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */ 60 #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */ 61 #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */ 62 #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */ 63 64 enum imx_rtc_type { 65 IMX1_RTC, 66 IMX21_RTC, 67 }; 68 69 struct rtc_plat_data { 70 struct rtc_device *rtc; 71 void __iomem *ioaddr; 72 int irq; 73 struct clk *clk_ref; 74 struct clk *clk_ipg; 75 struct rtc_time g_rtc_alarm; 76 enum imx_rtc_type devtype; 77 }; 78 79 static const struct platform_device_id imx_rtc_devtype[] = { 80 { 81 .name = "imx1-rtc", 82 .driver_data = IMX1_RTC, 83 }, { 84 .name = "imx21-rtc", 85 .driver_data = IMX21_RTC, 86 }, { 87 /* sentinel */ 88 } 89 }; 90 MODULE_DEVICE_TABLE(platform, imx_rtc_devtype); 91 92 #ifdef CONFIG_OF 93 static const struct of_device_id imx_rtc_dt_ids[] = { 94 { .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC }, 95 { .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC }, 96 {} 97 }; 98 MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids); 99 #endif 100 101 static inline int is_imx1_rtc(struct rtc_plat_data *data) 102 { 103 return data->devtype == IMX1_RTC; 104 } 105 106 /* 107 * This function is used to obtain the RTC time or the alarm value in 108 * second. 109 */ 110 static time64_t get_alarm_or_time(struct device *dev, int time_alarm) 111 { 112 struct platform_device *pdev = to_platform_device(dev); 113 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 114 void __iomem *ioaddr = pdata->ioaddr; 115 u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0; 116 117 switch (time_alarm) { 118 case MXC_RTC_TIME: 119 day = readw(ioaddr + RTC_DAYR); 120 hr_min = readw(ioaddr + RTC_HOURMIN); 121 sec = readw(ioaddr + RTC_SECOND); 122 break; 123 case MXC_RTC_ALARM: 124 day = readw(ioaddr + RTC_DAYALARM); 125 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; 126 sec = readw(ioaddr + RTC_ALRM_SEC); 127 break; 128 } 129 130 hr = hr_min >> 8; 131 min = hr_min & 0xff; 132 133 return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec; 134 } 135 136 /* 137 * This function sets the RTC alarm value or the time value. 138 */ 139 static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time) 140 { 141 u32 tod, day, hr, min, sec, temp; 142 struct platform_device *pdev = to_platform_device(dev); 143 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 144 void __iomem *ioaddr = pdata->ioaddr; 145 146 day = div_s64_rem(time, 86400, &tod); 147 148 /* time is within a day now */ 149 hr = tod / 3600; 150 tod -= hr * 3600; 151 152 /* time is within an hour now */ 153 min = tod / 60; 154 sec = tod - min * 60; 155 156 temp = (hr << 8) + min; 157 158 switch (time_alarm) { 159 case MXC_RTC_TIME: 160 writew(day, ioaddr + RTC_DAYR); 161 writew(sec, ioaddr + RTC_SECOND); 162 writew(temp, ioaddr + RTC_HOURMIN); 163 break; 164 case MXC_RTC_ALARM: 165 writew(day, ioaddr + RTC_DAYALARM); 166 writew(sec, ioaddr + RTC_ALRM_SEC); 167 writew(temp, ioaddr + RTC_ALRM_HM); 168 break; 169 } 170 } 171 172 /* 173 * This function updates the RTC alarm registers and then clears all the 174 * interrupt status bits. 175 */ 176 static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm) 177 { 178 time64_t time; 179 struct platform_device *pdev = to_platform_device(dev); 180 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 181 void __iomem *ioaddr = pdata->ioaddr; 182 183 time = rtc_tm_to_time64(alrm); 184 185 /* clear all the interrupt status bits */ 186 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); 187 set_alarm_or_time(dev, MXC_RTC_ALARM, time); 188 } 189 190 static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit, 191 unsigned int enabled) 192 { 193 struct platform_device *pdev = to_platform_device(dev); 194 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 195 void __iomem *ioaddr = pdata->ioaddr; 196 u32 reg; 197 198 spin_lock_irq(&pdata->rtc->irq_lock); 199 reg = readw(ioaddr + RTC_RTCIENR); 200 201 if (enabled) 202 reg |= bit; 203 else 204 reg &= ~bit; 205 206 writew(reg, ioaddr + RTC_RTCIENR); 207 spin_unlock_irq(&pdata->rtc->irq_lock); 208 } 209 210 /* This function is the RTC interrupt service routine. */ 211 static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) 212 { 213 struct platform_device *pdev = dev_id; 214 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 215 void __iomem *ioaddr = pdata->ioaddr; 216 unsigned long flags; 217 u32 status; 218 u32 events = 0; 219 220 spin_lock_irqsave(&pdata->rtc->irq_lock, flags); 221 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); 222 /* clear interrupt sources */ 223 writew(status, ioaddr + RTC_RTCISR); 224 225 /* update irq data & counter */ 226 if (status & RTC_ALM_BIT) { 227 events |= (RTC_AF | RTC_IRQF); 228 /* RTC alarm should be one-shot */ 229 mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0); 230 } 231 232 if (status & PIT_ALL_ON) 233 events |= (RTC_PF | RTC_IRQF); 234 235 rtc_update_irq(pdata->rtc, 1, events); 236 spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags); 237 238 return IRQ_HANDLED; 239 } 240 241 static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 242 { 243 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled); 244 return 0; 245 } 246 247 /* 248 * This function reads the current RTC time into tm in Gregorian date. 249 */ 250 static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) 251 { 252 time64_t val; 253 254 /* Avoid roll-over from reading the different registers */ 255 do { 256 val = get_alarm_or_time(dev, MXC_RTC_TIME); 257 } while (val != get_alarm_or_time(dev, MXC_RTC_TIME)); 258 259 rtc_time64_to_tm(val, tm); 260 261 return 0; 262 } 263 264 /* 265 * This function sets the internal RTC time based on tm in Gregorian date. 266 */ 267 static int mxc_rtc_set_mmss(struct device *dev, time64_t time) 268 { 269 struct platform_device *pdev = to_platform_device(dev); 270 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 271 272 /* 273 * TTC_DAYR register is 9-bit in MX1 SoC, save time and day of year only 274 */ 275 if (is_imx1_rtc(pdata)) { 276 struct rtc_time tm; 277 278 rtc_time64_to_tm(time, &tm); 279 tm.tm_year = 70; 280 time = rtc_tm_to_time64(&tm); 281 } 282 283 /* Avoid roll-over from reading the different registers */ 284 do { 285 set_alarm_or_time(dev, MXC_RTC_TIME, time); 286 } while (time != get_alarm_or_time(dev, MXC_RTC_TIME)); 287 288 return 0; 289 } 290 291 /* 292 * This function reads the current alarm value into the passed in 'alrm' 293 * argument. It updates the alrm's pending field value based on the whether 294 * an alarm interrupt occurs or not. 295 */ 296 static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 297 { 298 struct platform_device *pdev = to_platform_device(dev); 299 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 300 void __iomem *ioaddr = pdata->ioaddr; 301 302 rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time); 303 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; 304 305 return 0; 306 } 307 308 /* 309 * This function sets the RTC alarm based on passed in alrm. 310 */ 311 static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 312 { 313 struct platform_device *pdev = to_platform_device(dev); 314 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 315 316 rtc_update_alarm(dev, &alrm->time); 317 318 memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); 319 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled); 320 321 return 0; 322 } 323 324 /* RTC layer */ 325 static const struct rtc_class_ops mxc_rtc_ops = { 326 .read_time = mxc_rtc_read_time, 327 .set_mmss64 = mxc_rtc_set_mmss, 328 .read_alarm = mxc_rtc_read_alarm, 329 .set_alarm = mxc_rtc_set_alarm, 330 .alarm_irq_enable = mxc_rtc_alarm_irq_enable, 331 }; 332 333 static int mxc_rtc_probe(struct platform_device *pdev) 334 { 335 struct resource *res; 336 struct rtc_device *rtc; 337 struct rtc_plat_data *pdata = NULL; 338 u32 reg; 339 unsigned long rate; 340 int ret; 341 const struct of_device_id *of_id; 342 343 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 344 if (!pdata) 345 return -ENOMEM; 346 347 of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev); 348 if (of_id) 349 pdata->devtype = (enum imx_rtc_type)of_id->data; 350 else 351 pdata->devtype = pdev->id_entry->driver_data; 352 353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 354 pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res); 355 if (IS_ERR(pdata->ioaddr)) 356 return PTR_ERR(pdata->ioaddr); 357 358 pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 359 if (IS_ERR(pdata->clk_ipg)) { 360 dev_err(&pdev->dev, "unable to get ipg clock!\n"); 361 return PTR_ERR(pdata->clk_ipg); 362 } 363 364 ret = clk_prepare_enable(pdata->clk_ipg); 365 if (ret) 366 return ret; 367 368 pdata->clk_ref = devm_clk_get(&pdev->dev, "ref"); 369 if (IS_ERR(pdata->clk_ref)) { 370 dev_err(&pdev->dev, "unable to get ref clock!\n"); 371 ret = PTR_ERR(pdata->clk_ref); 372 goto exit_put_clk_ipg; 373 } 374 375 ret = clk_prepare_enable(pdata->clk_ref); 376 if (ret) 377 goto exit_put_clk_ipg; 378 379 rate = clk_get_rate(pdata->clk_ref); 380 381 if (rate == 32768) 382 reg = RTC_INPUT_CLK_32768HZ; 383 else if (rate == 32000) 384 reg = RTC_INPUT_CLK_32000HZ; 385 else if (rate == 38400) 386 reg = RTC_INPUT_CLK_38400HZ; 387 else { 388 dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate); 389 ret = -EINVAL; 390 goto exit_put_clk_ref; 391 } 392 393 reg |= RTC_ENABLE_BIT; 394 writew(reg, (pdata->ioaddr + RTC_RTCCTL)); 395 if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) { 396 dev_err(&pdev->dev, "hardware module can't be enabled!\n"); 397 ret = -EIO; 398 goto exit_put_clk_ref; 399 } 400 401 platform_set_drvdata(pdev, pdata); 402 403 /* Configure and enable the RTC */ 404 pdata->irq = platform_get_irq(pdev, 0); 405 406 if (pdata->irq >= 0 && 407 devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 408 IRQF_SHARED, pdev->name, pdev) < 0) { 409 dev_warn(&pdev->dev, "interrupt not available.\n"); 410 pdata->irq = -1; 411 } 412 413 if (pdata->irq >= 0) 414 device_init_wakeup(&pdev->dev, 1); 415 416 rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops, 417 THIS_MODULE); 418 if (IS_ERR(rtc)) { 419 ret = PTR_ERR(rtc); 420 goto exit_put_clk_ref; 421 } 422 423 pdata->rtc = rtc; 424 425 return 0; 426 427 exit_put_clk_ref: 428 clk_disable_unprepare(pdata->clk_ref); 429 exit_put_clk_ipg: 430 clk_disable_unprepare(pdata->clk_ipg); 431 432 return ret; 433 } 434 435 static int mxc_rtc_remove(struct platform_device *pdev) 436 { 437 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 438 439 clk_disable_unprepare(pdata->clk_ref); 440 clk_disable_unprepare(pdata->clk_ipg); 441 442 return 0; 443 } 444 445 #ifdef CONFIG_PM_SLEEP 446 static int mxc_rtc_suspend(struct device *dev) 447 { 448 struct rtc_plat_data *pdata = dev_get_drvdata(dev); 449 450 if (device_may_wakeup(dev)) 451 enable_irq_wake(pdata->irq); 452 453 return 0; 454 } 455 456 static int mxc_rtc_resume(struct device *dev) 457 { 458 struct rtc_plat_data *pdata = dev_get_drvdata(dev); 459 460 if (device_may_wakeup(dev)) 461 disable_irq_wake(pdata->irq); 462 463 return 0; 464 } 465 #endif 466 467 static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume); 468 469 static struct platform_driver mxc_rtc_driver = { 470 .driver = { 471 .name = "mxc_rtc", 472 .of_match_table = of_match_ptr(imx_rtc_dt_ids), 473 .pm = &mxc_rtc_pm_ops, 474 }, 475 .id_table = imx_rtc_devtype, 476 .probe = mxc_rtc_probe, 477 .remove = mxc_rtc_remove, 478 }; 479 480 module_platform_driver(mxc_rtc_driver) 481 482 MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>"); 483 MODULE_DESCRIPTION("RTC driver for Freescale MXC"); 484 MODULE_LICENSE("GPL"); 485 486