1 /* 2 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11 12 #include <linux/io.h> 13 #include <linux/rtc.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/interrupt.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 20 #include <mach/hardware.h> 21 22 #define RTC_INPUT_CLK_32768HZ (0x00 << 5) 23 #define RTC_INPUT_CLK_32000HZ (0x01 << 5) 24 #define RTC_INPUT_CLK_38400HZ (0x02 << 5) 25 26 #define RTC_SW_BIT (1 << 0) 27 #define RTC_ALM_BIT (1 << 2) 28 #define RTC_1HZ_BIT (1 << 4) 29 #define RTC_2HZ_BIT (1 << 7) 30 #define RTC_SAM0_BIT (1 << 8) 31 #define RTC_SAM1_BIT (1 << 9) 32 #define RTC_SAM2_BIT (1 << 10) 33 #define RTC_SAM3_BIT (1 << 11) 34 #define RTC_SAM4_BIT (1 << 12) 35 #define RTC_SAM5_BIT (1 << 13) 36 #define RTC_SAM6_BIT (1 << 14) 37 #define RTC_SAM7_BIT (1 << 15) 38 #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \ 39 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \ 40 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT) 41 42 #define RTC_ENABLE_BIT (1 << 7) 43 44 #define MAX_PIE_NUM 9 45 #define MAX_PIE_FREQ 512 46 static const u32 PIE_BIT_DEF[MAX_PIE_NUM][2] = { 47 { 2, RTC_2HZ_BIT }, 48 { 4, RTC_SAM0_BIT }, 49 { 8, RTC_SAM1_BIT }, 50 { 16, RTC_SAM2_BIT }, 51 { 32, RTC_SAM3_BIT }, 52 { 64, RTC_SAM4_BIT }, 53 { 128, RTC_SAM5_BIT }, 54 { 256, RTC_SAM6_BIT }, 55 { MAX_PIE_FREQ, RTC_SAM7_BIT }, 56 }; 57 58 /* Those are the bits from a classic RTC we want to mimic */ 59 #define RTC_IRQF 0x80 /* any of the following 3 is active */ 60 #define RTC_PF 0x40 /* Periodic interrupt */ 61 #define RTC_AF 0x20 /* Alarm interrupt */ 62 #define RTC_UF 0x10 /* Update interrupt for 1Hz RTC */ 63 64 #define MXC_RTC_TIME 0 65 #define MXC_RTC_ALARM 1 66 67 #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */ 68 #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */ 69 #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */ 70 #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */ 71 #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */ 72 #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */ 73 #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */ 74 #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */ 75 #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */ 76 #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */ 77 #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */ 78 #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */ 79 #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */ 80 81 struct rtc_plat_data { 82 struct rtc_device *rtc; 83 void __iomem *ioaddr; 84 int irq; 85 struct clk *clk; 86 struct rtc_time g_rtc_alarm; 87 }; 88 89 /* 90 * This function is used to obtain the RTC time or the alarm value in 91 * second. 92 */ 93 static u32 get_alarm_or_time(struct device *dev, int time_alarm) 94 { 95 struct platform_device *pdev = to_platform_device(dev); 96 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 97 void __iomem *ioaddr = pdata->ioaddr; 98 u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0; 99 100 switch (time_alarm) { 101 case MXC_RTC_TIME: 102 day = readw(ioaddr + RTC_DAYR); 103 hr_min = readw(ioaddr + RTC_HOURMIN); 104 sec = readw(ioaddr + RTC_SECOND); 105 break; 106 case MXC_RTC_ALARM: 107 day = readw(ioaddr + RTC_DAYALARM); 108 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; 109 sec = readw(ioaddr + RTC_ALRM_SEC); 110 break; 111 } 112 113 hr = hr_min >> 8; 114 min = hr_min & 0xff; 115 116 return (((day * 24 + hr) * 60) + min) * 60 + sec; 117 } 118 119 /* 120 * This function sets the RTC alarm value or the time value. 121 */ 122 static void set_alarm_or_time(struct device *dev, int time_alarm, u32 time) 123 { 124 u32 day, hr, min, sec, temp; 125 struct platform_device *pdev = to_platform_device(dev); 126 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 127 void __iomem *ioaddr = pdata->ioaddr; 128 129 day = time / 86400; 130 time -= day * 86400; 131 132 /* time is within a day now */ 133 hr = time / 3600; 134 time -= hr * 3600; 135 136 /* time is within an hour now */ 137 min = time / 60; 138 sec = time - min * 60; 139 140 temp = (hr << 8) + min; 141 142 switch (time_alarm) { 143 case MXC_RTC_TIME: 144 writew(day, ioaddr + RTC_DAYR); 145 writew(sec, ioaddr + RTC_SECOND); 146 writew(temp, ioaddr + RTC_HOURMIN); 147 break; 148 case MXC_RTC_ALARM: 149 writew(day, ioaddr + RTC_DAYALARM); 150 writew(sec, ioaddr + RTC_ALRM_SEC); 151 writew(temp, ioaddr + RTC_ALRM_HM); 152 break; 153 } 154 } 155 156 /* 157 * This function updates the RTC alarm registers and then clears all the 158 * interrupt status bits. 159 */ 160 static int rtc_update_alarm(struct device *dev, struct rtc_time *alrm) 161 { 162 struct rtc_time alarm_tm, now_tm; 163 unsigned long now, time; 164 int ret; 165 struct platform_device *pdev = to_platform_device(dev); 166 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 167 void __iomem *ioaddr = pdata->ioaddr; 168 169 now = get_alarm_or_time(dev, MXC_RTC_TIME); 170 rtc_time_to_tm(now, &now_tm); 171 alarm_tm.tm_year = now_tm.tm_year; 172 alarm_tm.tm_mon = now_tm.tm_mon; 173 alarm_tm.tm_mday = now_tm.tm_mday; 174 alarm_tm.tm_hour = alrm->tm_hour; 175 alarm_tm.tm_min = alrm->tm_min; 176 alarm_tm.tm_sec = alrm->tm_sec; 177 rtc_tm_to_time(&now_tm, &now); 178 rtc_tm_to_time(&alarm_tm, &time); 179 180 if (time < now) { 181 time += 60 * 60 * 24; 182 rtc_time_to_tm(time, &alarm_tm); 183 } 184 185 ret = rtc_tm_to_time(&alarm_tm, &time); 186 187 /* clear all the interrupt status bits */ 188 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); 189 set_alarm_or_time(dev, MXC_RTC_ALARM, time); 190 191 return ret; 192 } 193 194 /* This function is the RTC interrupt service routine. */ 195 static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id) 196 { 197 struct platform_device *pdev = dev_id; 198 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 199 void __iomem *ioaddr = pdata->ioaddr; 200 u32 status; 201 u32 events = 0; 202 203 spin_lock_irq(&pdata->rtc->irq_lock); 204 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); 205 /* clear interrupt sources */ 206 writew(status, ioaddr + RTC_RTCISR); 207 208 /* clear alarm interrupt if it has occurred */ 209 if (status & RTC_ALM_BIT) 210 status &= ~RTC_ALM_BIT; 211 212 /* update irq data & counter */ 213 if (status & RTC_ALM_BIT) 214 events |= (RTC_AF | RTC_IRQF); 215 216 if (status & RTC_1HZ_BIT) 217 events |= (RTC_UF | RTC_IRQF); 218 219 if (status & PIT_ALL_ON) 220 events |= (RTC_PF | RTC_IRQF); 221 222 if ((status & RTC_ALM_BIT) && rtc_valid_tm(&pdata->g_rtc_alarm)) 223 rtc_update_alarm(&pdev->dev, &pdata->g_rtc_alarm); 224 225 rtc_update_irq(pdata->rtc, 1, events); 226 spin_unlock_irq(&pdata->rtc->irq_lock); 227 228 return IRQ_HANDLED; 229 } 230 231 /* 232 * Clear all interrupts and release the IRQ 233 */ 234 static void mxc_rtc_release(struct device *dev) 235 { 236 struct platform_device *pdev = to_platform_device(dev); 237 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 238 void __iomem *ioaddr = pdata->ioaddr; 239 240 spin_lock_irq(&pdata->rtc->irq_lock); 241 242 /* Disable all rtc interrupts */ 243 writew(0, ioaddr + RTC_RTCIENR); 244 245 /* Clear all interrupt status */ 246 writew(0xffffffff, ioaddr + RTC_RTCISR); 247 248 spin_unlock_irq(&pdata->rtc->irq_lock); 249 } 250 251 static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit, 252 unsigned int enabled) 253 { 254 struct platform_device *pdev = to_platform_device(dev); 255 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 256 void __iomem *ioaddr = pdata->ioaddr; 257 u32 reg; 258 259 spin_lock_irq(&pdata->rtc->irq_lock); 260 reg = readw(ioaddr + RTC_RTCIENR); 261 262 if (enabled) 263 reg |= bit; 264 else 265 reg &= ~bit; 266 267 writew(reg, ioaddr + RTC_RTCIENR); 268 spin_unlock_irq(&pdata->rtc->irq_lock); 269 } 270 271 static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 272 { 273 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled); 274 return 0; 275 } 276 277 /* 278 * This function reads the current RTC time into tm in Gregorian date. 279 */ 280 static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm) 281 { 282 u32 val; 283 284 /* Avoid roll-over from reading the different registers */ 285 do { 286 val = get_alarm_or_time(dev, MXC_RTC_TIME); 287 } while (val != get_alarm_or_time(dev, MXC_RTC_TIME)); 288 289 rtc_time_to_tm(val, tm); 290 291 return 0; 292 } 293 294 /* 295 * This function sets the internal RTC time based on tm in Gregorian date. 296 */ 297 static int mxc_rtc_set_mmss(struct device *dev, unsigned long time) 298 { 299 /* Avoid roll-over from reading the different registers */ 300 do { 301 set_alarm_or_time(dev, MXC_RTC_TIME, time); 302 } while (time != get_alarm_or_time(dev, MXC_RTC_TIME)); 303 304 return 0; 305 } 306 307 /* 308 * This function reads the current alarm value into the passed in 'alrm' 309 * argument. It updates the alrm's pending field value based on the whether 310 * an alarm interrupt occurs or not. 311 */ 312 static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 313 { 314 struct platform_device *pdev = to_platform_device(dev); 315 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 316 void __iomem *ioaddr = pdata->ioaddr; 317 318 rtc_time_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time); 319 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; 320 321 return 0; 322 } 323 324 /* 325 * This function sets the RTC alarm based on passed in alrm. 326 */ 327 static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 328 { 329 struct platform_device *pdev = to_platform_device(dev); 330 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 331 int ret; 332 333 if (rtc_valid_tm(&alrm->time)) { 334 if (alrm->time.tm_sec > 59 || 335 alrm->time.tm_hour > 23 || 336 alrm->time.tm_min > 59) 337 return -EINVAL; 338 339 ret = rtc_update_alarm(dev, &alrm->time); 340 } else { 341 ret = rtc_valid_tm(&alrm->time); 342 if (ret) 343 return ret; 344 345 ret = rtc_update_alarm(dev, &alrm->time); 346 } 347 348 if (ret) 349 return ret; 350 351 memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time)); 352 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled); 353 354 return 0; 355 } 356 357 /* RTC layer */ 358 static struct rtc_class_ops mxc_rtc_ops = { 359 .release = mxc_rtc_release, 360 .read_time = mxc_rtc_read_time, 361 .set_mmss = mxc_rtc_set_mmss, 362 .read_alarm = mxc_rtc_read_alarm, 363 .set_alarm = mxc_rtc_set_alarm, 364 .alarm_irq_enable = mxc_rtc_alarm_irq_enable, 365 }; 366 367 static int __init mxc_rtc_probe(struct platform_device *pdev) 368 { 369 struct resource *res; 370 struct rtc_device *rtc; 371 struct rtc_plat_data *pdata = NULL; 372 u32 reg; 373 unsigned long rate; 374 int ret; 375 376 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 377 if (!res) 378 return -ENODEV; 379 380 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 381 if (!pdata) 382 return -ENOMEM; 383 384 if (!devm_request_mem_region(&pdev->dev, res->start, 385 resource_size(res), pdev->name)) 386 return -EBUSY; 387 388 pdata->ioaddr = devm_ioremap(&pdev->dev, res->start, 389 resource_size(res)); 390 391 pdata->clk = clk_get(&pdev->dev, "rtc"); 392 if (IS_ERR(pdata->clk)) { 393 dev_err(&pdev->dev, "unable to get clock!\n"); 394 ret = PTR_ERR(pdata->clk); 395 goto exit_free_pdata; 396 } 397 398 clk_enable(pdata->clk); 399 rate = clk_get_rate(pdata->clk); 400 401 if (rate == 32768) 402 reg = RTC_INPUT_CLK_32768HZ; 403 else if (rate == 32000) 404 reg = RTC_INPUT_CLK_32000HZ; 405 else if (rate == 38400) 406 reg = RTC_INPUT_CLK_38400HZ; 407 else { 408 dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate); 409 ret = -EINVAL; 410 goto exit_put_clk; 411 } 412 413 reg |= RTC_ENABLE_BIT; 414 writew(reg, (pdata->ioaddr + RTC_RTCCTL)); 415 if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) { 416 dev_err(&pdev->dev, "hardware module can't be enabled!\n"); 417 ret = -EIO; 418 goto exit_put_clk; 419 } 420 421 rtc = rtc_device_register(pdev->name, &pdev->dev, &mxc_rtc_ops, 422 THIS_MODULE); 423 if (IS_ERR(rtc)) { 424 ret = PTR_ERR(rtc); 425 goto exit_put_clk; 426 } 427 428 pdata->rtc = rtc; 429 platform_set_drvdata(pdev, pdata); 430 431 /* Configure and enable the RTC */ 432 pdata->irq = platform_get_irq(pdev, 0); 433 434 if (pdata->irq >= 0 && 435 devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 436 IRQF_SHARED, pdev->name, pdev) < 0) { 437 dev_warn(&pdev->dev, "interrupt not available.\n"); 438 pdata->irq = -1; 439 } 440 441 return 0; 442 443 exit_put_clk: 444 clk_disable(pdata->clk); 445 clk_put(pdata->clk); 446 447 exit_free_pdata: 448 449 return ret; 450 } 451 452 static int __exit mxc_rtc_remove(struct platform_device *pdev) 453 { 454 struct rtc_plat_data *pdata = platform_get_drvdata(pdev); 455 456 rtc_device_unregister(pdata->rtc); 457 458 clk_disable(pdata->clk); 459 clk_put(pdata->clk); 460 platform_set_drvdata(pdev, NULL); 461 462 return 0; 463 } 464 465 static struct platform_driver mxc_rtc_driver = { 466 .driver = { 467 .name = "mxc_rtc", 468 .owner = THIS_MODULE, 469 }, 470 .remove = __exit_p(mxc_rtc_remove), 471 }; 472 473 static int __init mxc_rtc_init(void) 474 { 475 return platform_driver_probe(&mxc_rtc_driver, mxc_rtc_probe); 476 } 477 478 static void __exit mxc_rtc_exit(void) 479 { 480 platform_driver_unregister(&mxc_rtc_driver); 481 } 482 483 module_init(mxc_rtc_init); 484 module_exit(mxc_rtc_exit); 485 486 MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>"); 487 MODULE_DESCRIPTION("RTC driver for Freescale MXC"); 488 MODULE_LICENSE("GPL"); 489 490