1 /* 2 * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time 3 * chips. 4 * 5 * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>. 6 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>. 7 * 8 * References: 9 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10. 10 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10. 11 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105. 12 * Application Note 90, Using the Multiplex Bus RTC Extended Features. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20 21 #include <linux/bcd.h> 22 #include <linux/delay.h> 23 #include <linux/io.h> 24 #include <linux/module.h> 25 #include <linux/platform_device.h> 26 #include <linux/rtc.h> 27 #include <linux/workqueue.h> 28 29 #include <linux/rtc/ds1685.h> 30 31 #ifdef CONFIG_PROC_FS 32 #include <linux/proc_fs.h> 33 #endif 34 35 #define DRV_VERSION "0.42.0" 36 37 38 /* ----------------------------------------------------------------------- */ 39 /* Standard read/write functions if platform does not provide overrides */ 40 41 /** 42 * ds1685_read - read a value from an rtc register. 43 * @rtc: pointer to the ds1685 rtc structure. 44 * @reg: the register address to read. 45 */ 46 static u8 47 ds1685_read(struct ds1685_priv *rtc, int reg) 48 { 49 return readb((u8 __iomem *)rtc->regs + 50 (reg * rtc->regstep)); 51 } 52 53 /** 54 * ds1685_write - write a value to an rtc register. 55 * @rtc: pointer to the ds1685 rtc structure. 56 * @reg: the register address to write. 57 * @value: value to write to the register. 58 */ 59 static void 60 ds1685_write(struct ds1685_priv *rtc, int reg, u8 value) 61 { 62 writeb(value, ((u8 __iomem *)rtc->regs + 63 (reg * rtc->regstep))); 64 } 65 /* ----------------------------------------------------------------------- */ 66 67 68 /* ----------------------------------------------------------------------- */ 69 /* Inlined functions */ 70 71 /** 72 * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD. 73 * @rtc: pointer to the ds1685 rtc structure. 74 * @val: u8 time value to consider converting. 75 * @bcd_mask: u8 mask value if BCD mode is used. 76 * @bin_mask: u8 mask value if BIN mode is used. 77 * 78 * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE. 79 */ 80 static inline u8 81 ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask) 82 { 83 if (rtc->bcd_mode) 84 return (bcd2bin(val) & bcd_mask); 85 86 return (val & bin_mask); 87 } 88 89 /** 90 * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD. 91 * @rtc: pointer to the ds1685 rtc structure. 92 * @val: u8 time value to consider converting. 93 * @bin_mask: u8 mask value if BIN mode is used. 94 * @bcd_mask: u8 mask value if BCD mode is used. 95 * 96 * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE. 97 */ 98 static inline u8 99 ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask) 100 { 101 if (rtc->bcd_mode) 102 return (bin2bcd(val) & bcd_mask); 103 104 return (val & bin_mask); 105 } 106 107 /** 108 * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0. 109 * @rtc: pointer to the ds1685 rtc structure. 110 */ 111 static inline void 112 ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc) 113 { 114 rtc->write(rtc, RTC_CTRL_A, 115 (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0))); 116 } 117 118 /** 119 * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1. 120 * @rtc: pointer to the ds1685 rtc structure. 121 */ 122 static inline void 123 ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc) 124 { 125 rtc->write(rtc, RTC_CTRL_A, 126 (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0)); 127 } 128 129 /** 130 * ds1685_rtc_begin_data_access - prepare the rtc for data access. 131 * @rtc: pointer to the ds1685 rtc structure. 132 * 133 * This takes several steps to prepare the rtc for access to get/set time 134 * and alarm values from the rtc registers: 135 * - Sets the SET bit in Control Register B. 136 * - Reads Ext Control Register 4A and checks the INCR bit. 137 * - If INCR is active, a short delay is added before Ext Control Register 4A 138 * is read again in a loop until INCR is inactive. 139 * - Switches the rtc to bank 1. This allows access to all relevant 140 * data for normal rtc operation, as bank 0 contains only the nvram. 141 */ 142 static inline void 143 ds1685_rtc_begin_data_access(struct ds1685_priv *rtc) 144 { 145 /* Set the SET bit in Ctrl B */ 146 rtc->write(rtc, RTC_CTRL_B, 147 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); 148 149 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ 150 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) 151 cpu_relax(); 152 153 /* Switch to Bank 1 */ 154 ds1685_rtc_switch_to_bank1(rtc); 155 } 156 157 /** 158 * ds1685_rtc_end_data_access - end data access on the rtc. 159 * @rtc: pointer to the ds1685 rtc structure. 160 * 161 * This ends what was started by ds1685_rtc_begin_data_access: 162 * - Switches the rtc back to bank 0. 163 * - Clears the SET bit in Control Register B. 164 */ 165 static inline void 166 ds1685_rtc_end_data_access(struct ds1685_priv *rtc) 167 { 168 /* Switch back to Bank 0 */ 169 ds1685_rtc_switch_to_bank1(rtc); 170 171 /* Clear the SET bit in Ctrl B */ 172 rtc->write(rtc, RTC_CTRL_B, 173 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); 174 } 175 176 /** 177 * ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access. 178 * @rtc: pointer to the ds1685 rtc structure. 179 * @flags: irq flags variable for spin_lock_irqsave. 180 * 181 * This takes several steps to prepare the rtc for access to read just the 182 * control registers: 183 * - Sets a spinlock on the rtc IRQ. 184 * - Switches the rtc to bank 1. This allows access to the two extended 185 * control registers. 186 * 187 * Only use this where you are certain another lock will not be held. 188 */ 189 static inline void 190 ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long flags) 191 { 192 spin_lock_irqsave(&rtc->lock, flags); 193 ds1685_rtc_switch_to_bank1(rtc); 194 } 195 196 /** 197 * ds1685_rtc_end_ctrl_access - end ctrl access on the rtc. 198 * @rtc: pointer to the ds1685 rtc structure. 199 * @flags: irq flags variable for spin_unlock_irqrestore. 200 * 201 * This ends what was started by ds1685_rtc_begin_ctrl_access: 202 * - Switches the rtc back to bank 0. 203 * - Unsets the spinlock on the rtc IRQ. 204 */ 205 static inline void 206 ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags) 207 { 208 ds1685_rtc_switch_to_bank0(rtc); 209 spin_unlock_irqrestore(&rtc->lock, flags); 210 } 211 212 /** 213 * ds1685_rtc_get_ssn - retrieve the silicon serial number. 214 * @rtc: pointer to the ds1685 rtc structure. 215 * @ssn: u8 array to hold the bits of the silicon serial number. 216 * 217 * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The 218 * first byte is the model number, the next six bytes are the serial number 219 * digits, and the final byte is a CRC check byte. Together, they form the 220 * silicon serial number. 221 * 222 * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be 223 * called first before calling this function, else data will be read out of 224 * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done. 225 */ 226 static inline void 227 ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn) 228 { 229 ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL); 230 ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1); 231 ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2); 232 ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3); 233 ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4); 234 ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5); 235 ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6); 236 ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC); 237 } 238 /* ----------------------------------------------------------------------- */ 239 240 241 /* ----------------------------------------------------------------------- */ 242 /* Read/Set Time & Alarm functions */ 243 244 /** 245 * ds1685_rtc_read_time - reads the time registers. 246 * @dev: pointer to device structure. 247 * @tm: pointer to rtc_time structure. 248 */ 249 static int 250 ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm) 251 { 252 struct platform_device *pdev = to_platform_device(dev); 253 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 254 u8 ctrlb, century; 255 u8 seconds, minutes, hours, wday, mday, month, years; 256 257 /* Fetch the time info from the RTC registers. */ 258 ds1685_rtc_begin_data_access(rtc); 259 seconds = rtc->read(rtc, RTC_SECS); 260 minutes = rtc->read(rtc, RTC_MINS); 261 hours = rtc->read(rtc, RTC_HRS); 262 wday = rtc->read(rtc, RTC_WDAY); 263 mday = rtc->read(rtc, RTC_MDAY); 264 month = rtc->read(rtc, RTC_MONTH); 265 years = rtc->read(rtc, RTC_YEAR); 266 century = rtc->read(rtc, RTC_CENTURY); 267 ctrlb = rtc->read(rtc, RTC_CTRL_B); 268 ds1685_rtc_end_data_access(rtc); 269 270 /* bcd2bin if needed, perform fixups, and store to rtc_time. */ 271 years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK, 272 RTC_YEAR_BIN_MASK); 273 century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK, 274 RTC_CENTURY_MASK); 275 tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK, 276 RTC_SECS_BIN_MASK); 277 tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK, 278 RTC_MINS_BIN_MASK); 279 tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK, 280 RTC_HRS_24_BIN_MASK); 281 tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK, 282 RTC_WDAY_MASK) - 1); 283 tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, 284 RTC_MDAY_BIN_MASK); 285 tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK, 286 RTC_MONTH_BIN_MASK) - 1); 287 tm->tm_year = ((years + (century * 100)) - 1900); 288 tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); 289 tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */ 290 291 return rtc_valid_tm(tm); 292 } 293 294 /** 295 * ds1685_rtc_set_time - sets the time registers. 296 * @dev: pointer to device structure. 297 * @tm: pointer to rtc_time structure. 298 */ 299 static int 300 ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm) 301 { 302 struct platform_device *pdev = to_platform_device(dev); 303 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 304 u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century; 305 306 /* Fetch the time info from rtc_time. */ 307 seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK, 308 RTC_SECS_BCD_MASK); 309 minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK, 310 RTC_MINS_BCD_MASK); 311 hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK, 312 RTC_HRS_24_BCD_MASK); 313 wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK, 314 RTC_WDAY_MASK); 315 mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK, 316 RTC_MDAY_BCD_MASK); 317 month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK, 318 RTC_MONTH_BCD_MASK); 319 years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100), 320 RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK); 321 century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100), 322 RTC_CENTURY_MASK, RTC_CENTURY_MASK); 323 324 /* 325 * Perform Sanity Checks: 326 * - Months: !> 12, Month Day != 0. 327 * - Month Day !> Max days in current month. 328 * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7. 329 */ 330 if ((tm->tm_mon > 11) || (mday == 0)) 331 return -EDOM; 332 333 if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year)) 334 return -EDOM; 335 336 if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) || 337 (tm->tm_sec >= 60) || (wday > 7)) 338 return -EDOM; 339 340 /* 341 * Set the data mode to use and store the time values in the 342 * RTC registers. 343 */ 344 ds1685_rtc_begin_data_access(rtc); 345 ctrlb = rtc->read(rtc, RTC_CTRL_B); 346 if (rtc->bcd_mode) 347 ctrlb &= ~(RTC_CTRL_B_DM); 348 else 349 ctrlb |= RTC_CTRL_B_DM; 350 rtc->write(rtc, RTC_CTRL_B, ctrlb); 351 rtc->write(rtc, RTC_SECS, seconds); 352 rtc->write(rtc, RTC_MINS, minutes); 353 rtc->write(rtc, RTC_HRS, hours); 354 rtc->write(rtc, RTC_WDAY, wday); 355 rtc->write(rtc, RTC_MDAY, mday); 356 rtc->write(rtc, RTC_MONTH, month); 357 rtc->write(rtc, RTC_YEAR, years); 358 rtc->write(rtc, RTC_CENTURY, century); 359 ds1685_rtc_end_data_access(rtc); 360 361 return 0; 362 } 363 364 /** 365 * ds1685_rtc_read_alarm - reads the alarm registers. 366 * @dev: pointer to device structure. 367 * @alrm: pointer to rtc_wkalrm structure. 368 * 369 * There are three primary alarm registers: seconds, minutes, and hours. 370 * A fourth alarm register for the month date is also available in bank1 for 371 * kickstart/wakeup features. The DS1685/DS1687 manual states that a 372 * "don't care" value ranging from 0xc0 to 0xff may be written into one or 373 * more of the three alarm bytes to act as a wildcard value. The fourth 374 * byte doesn't support a "don't care" value. 375 */ 376 static int 377 ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 378 { 379 struct platform_device *pdev = to_platform_device(dev); 380 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 381 u8 seconds, minutes, hours, mday, ctrlb, ctrlc; 382 383 /* Fetch the alarm info from the RTC alarm registers. */ 384 ds1685_rtc_begin_data_access(rtc); 385 seconds = rtc->read(rtc, RTC_SECS_ALARM); 386 minutes = rtc->read(rtc, RTC_MINS_ALARM); 387 hours = rtc->read(rtc, RTC_HRS_ALARM); 388 mday = rtc->read(rtc, RTC_MDAY_ALARM); 389 ctrlb = rtc->read(rtc, RTC_CTRL_B); 390 ctrlc = rtc->read(rtc, RTC_CTRL_C); 391 ds1685_rtc_end_data_access(rtc); 392 393 /* Check month date. */ 394 if (!(mday >= 1) && (mday <= 31)) 395 return -EDOM; 396 397 /* 398 * Check the three alarm bytes. 399 * 400 * The Linux RTC system doesn't support the "don't care" capability 401 * of this RTC chip. We check for it anyways in case support is 402 * added in the future. 403 */ 404 if (unlikely(seconds >= 0xc0)) 405 alrm->time.tm_sec = -1; 406 else 407 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, 408 RTC_SECS_BCD_MASK, 409 RTC_SECS_BIN_MASK); 410 411 if (unlikely(minutes >= 0xc0)) 412 alrm->time.tm_min = -1; 413 else 414 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes, 415 RTC_MINS_BCD_MASK, 416 RTC_MINS_BIN_MASK); 417 418 if (unlikely(hours >= 0xc0)) 419 alrm->time.tm_hour = -1; 420 else 421 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours, 422 RTC_HRS_24_BCD_MASK, 423 RTC_HRS_24_BIN_MASK); 424 425 /* Write the data to rtc_wkalrm. */ 426 alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK, 427 RTC_MDAY_BIN_MASK); 428 alrm->time.tm_mon = -1; 429 alrm->time.tm_year = -1; 430 alrm->time.tm_wday = -1; 431 alrm->time.tm_yday = -1; 432 alrm->time.tm_isdst = -1; 433 alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE); 434 alrm->pending = !!(ctrlc & RTC_CTRL_C_AF); 435 436 return 0; 437 } 438 439 /** 440 * ds1685_rtc_set_alarm - sets the alarm in registers. 441 * @dev: pointer to device structure. 442 * @alrm: pointer to rtc_wkalrm structure. 443 */ 444 static int 445 ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 446 { 447 struct platform_device *pdev = to_platform_device(dev); 448 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 449 u8 ctrlb, seconds, minutes, hours, mday; 450 451 /* Fetch the alarm info and convert to BCD. */ 452 seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec, 453 RTC_SECS_BIN_MASK, 454 RTC_SECS_BCD_MASK); 455 minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min, 456 RTC_MINS_BIN_MASK, 457 RTC_MINS_BCD_MASK); 458 hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour, 459 RTC_HRS_24_BIN_MASK, 460 RTC_HRS_24_BCD_MASK); 461 mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday, 462 RTC_MDAY_BIN_MASK, 463 RTC_MDAY_BCD_MASK); 464 465 /* Check the month date for validity. */ 466 if (!(mday >= 1) && (mday <= 31)) 467 return -EDOM; 468 469 /* 470 * Check the three alarm bytes. 471 * 472 * The Linux RTC system doesn't support the "don't care" capability 473 * of this RTC chip because rtc_valid_tm tries to validate every 474 * field, and we only support four fields. We put the support 475 * here anyways for the future. 476 */ 477 if (unlikely(seconds >= 0xc0)) 478 seconds = 0xff; 479 480 if (unlikely(minutes >= 0xc0)) 481 minutes = 0xff; 482 483 if (unlikely(hours >= 0xc0)) 484 hours = 0xff; 485 486 alrm->time.tm_mon = -1; 487 alrm->time.tm_year = -1; 488 alrm->time.tm_wday = -1; 489 alrm->time.tm_yday = -1; 490 alrm->time.tm_isdst = -1; 491 492 /* Disable the alarm interrupt first. */ 493 ds1685_rtc_begin_data_access(rtc); 494 ctrlb = rtc->read(rtc, RTC_CTRL_B); 495 rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE))); 496 497 /* Read ctrlc to clear RTC_CTRL_C_AF. */ 498 rtc->read(rtc, RTC_CTRL_C); 499 500 /* 501 * Set the data mode to use and store the time values in the 502 * RTC registers. 503 */ 504 ctrlb = rtc->read(rtc, RTC_CTRL_B); 505 if (rtc->bcd_mode) 506 ctrlb &= ~(RTC_CTRL_B_DM); 507 else 508 ctrlb |= RTC_CTRL_B_DM; 509 rtc->write(rtc, RTC_CTRL_B, ctrlb); 510 rtc->write(rtc, RTC_SECS_ALARM, seconds); 511 rtc->write(rtc, RTC_MINS_ALARM, minutes); 512 rtc->write(rtc, RTC_HRS_ALARM, hours); 513 rtc->write(rtc, RTC_MDAY_ALARM, mday); 514 515 /* Re-enable the alarm if needed. */ 516 if (alrm->enabled) { 517 ctrlb = rtc->read(rtc, RTC_CTRL_B); 518 ctrlb |= RTC_CTRL_B_AIE; 519 rtc->write(rtc, RTC_CTRL_B, ctrlb); 520 } 521 522 /* Done! */ 523 ds1685_rtc_end_data_access(rtc); 524 525 return 0; 526 } 527 /* ----------------------------------------------------------------------- */ 528 529 530 /* ----------------------------------------------------------------------- */ 531 /* /dev/rtcX Interface functions */ 532 533 /** 534 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off. 535 * @dev: pointer to device structure. 536 * @enabled: flag indicating whether to enable or disable. 537 */ 538 static int 539 ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 540 { 541 struct ds1685_priv *rtc = dev_get_drvdata(dev); 542 unsigned long flags = 0; 543 544 /* Enable/disable the Alarm IRQ-Enable flag. */ 545 spin_lock_irqsave(&rtc->lock, flags); 546 547 /* Flip the requisite interrupt-enable bit. */ 548 if (enabled) 549 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) | 550 RTC_CTRL_B_AIE)); 551 else 552 rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) & 553 ~(RTC_CTRL_B_AIE))); 554 555 /* Read Control C to clear all the flag bits. */ 556 rtc->read(rtc, RTC_CTRL_C); 557 spin_unlock_irqrestore(&rtc->lock, flags); 558 559 return 0; 560 } 561 /* ----------------------------------------------------------------------- */ 562 563 564 /* ----------------------------------------------------------------------- */ 565 /* IRQ handler & workqueue. */ 566 567 /** 568 * ds1685_rtc_irq_handler - IRQ handler. 569 * @irq: IRQ number. 570 * @dev_id: platform device pointer. 571 */ 572 static irqreturn_t 573 ds1685_rtc_irq_handler(int irq, void *dev_id) 574 { 575 struct platform_device *pdev = dev_id; 576 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 577 u8 ctrlb, ctrlc; 578 unsigned long events = 0; 579 u8 num_irqs = 0; 580 581 /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */ 582 if (unlikely(!rtc)) 583 return IRQ_HANDLED; 584 585 /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */ 586 spin_lock(&rtc->lock); 587 ctrlb = rtc->read(rtc, RTC_CTRL_B); 588 ctrlc = rtc->read(rtc, RTC_CTRL_C); 589 590 /* Is the IRQF bit set? */ 591 if (likely(ctrlc & RTC_CTRL_C_IRQF)) { 592 /* 593 * We need to determine if it was one of the standard 594 * events: PF, AF, or UF. If so, we handle them and 595 * update the RTC core. 596 */ 597 if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) { 598 events = RTC_IRQF; 599 600 /* Check for a periodic interrupt. */ 601 if ((ctrlb & RTC_CTRL_B_PIE) && 602 (ctrlc & RTC_CTRL_C_PF)) { 603 events |= RTC_PF; 604 num_irqs++; 605 } 606 607 /* Check for an alarm interrupt. */ 608 if ((ctrlb & RTC_CTRL_B_AIE) && 609 (ctrlc & RTC_CTRL_C_AF)) { 610 events |= RTC_AF; 611 num_irqs++; 612 } 613 614 /* Check for an update interrupt. */ 615 if ((ctrlb & RTC_CTRL_B_UIE) && 616 (ctrlc & RTC_CTRL_C_UF)) { 617 events |= RTC_UF; 618 num_irqs++; 619 } 620 621 rtc_update_irq(rtc->dev, num_irqs, events); 622 } else { 623 /* 624 * One of the "extended" interrupts was received that 625 * is not recognized by the RTC core. These need to 626 * be handled in task context as they can call other 627 * functions and the time spent in irq context needs 628 * to be minimized. Schedule them into a workqueue 629 * and inform the RTC core that the IRQs were handled. 630 */ 631 spin_unlock(&rtc->lock); 632 schedule_work(&rtc->work); 633 rtc_update_irq(rtc->dev, 0, 0); 634 return IRQ_HANDLED; 635 } 636 } 637 spin_unlock(&rtc->lock); 638 639 return events ? IRQ_HANDLED : IRQ_NONE; 640 } 641 642 /** 643 * ds1685_rtc_work_queue - work queue handler. 644 * @work: work_struct containing data to work on in task context. 645 */ 646 static void 647 ds1685_rtc_work_queue(struct work_struct *work) 648 { 649 struct ds1685_priv *rtc = container_of(work, 650 struct ds1685_priv, work); 651 struct platform_device *pdev = to_platform_device(&rtc->dev->dev); 652 struct mutex *rtc_mutex = &rtc->dev->ops_lock; 653 u8 ctrl4a, ctrl4b; 654 655 mutex_lock(rtc_mutex); 656 657 ds1685_rtc_switch_to_bank1(rtc); 658 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 659 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); 660 661 /* 662 * Check for a kickstart interrupt. With Vcc applied, this 663 * typically means that the power button was pressed, so we 664 * begin the shutdown sequence. 665 */ 666 if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) { 667 /* Briefly disable kickstarts to debounce button presses. */ 668 rtc->write(rtc, RTC_EXT_CTRL_4B, 669 (rtc->read(rtc, RTC_EXT_CTRL_4B) & 670 ~(RTC_CTRL_4B_KSE))); 671 672 /* Clear the kickstart flag. */ 673 rtc->write(rtc, RTC_EXT_CTRL_4A, 674 (ctrl4a & ~(RTC_CTRL_4A_KF))); 675 676 677 /* 678 * Sleep 500ms before re-enabling kickstarts. This allows 679 * adequate time to avoid reading signal jitter as additional 680 * button presses. 681 */ 682 msleep(500); 683 rtc->write(rtc, RTC_EXT_CTRL_4B, 684 (rtc->read(rtc, RTC_EXT_CTRL_4B) | 685 RTC_CTRL_4B_KSE)); 686 687 /* Call the platform pre-poweroff function. Else, shutdown. */ 688 if (rtc->prepare_poweroff != NULL) 689 rtc->prepare_poweroff(); 690 else 691 ds1685_rtc_poweroff(pdev); 692 } 693 694 /* 695 * Check for a wake-up interrupt. With Vcc applied, this is 696 * essentially a second alarm interrupt, except it takes into 697 * account the 'date' register in bank1 in addition to the 698 * standard three alarm registers. 699 */ 700 if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) { 701 rtc->write(rtc, RTC_EXT_CTRL_4A, 702 (ctrl4a & ~(RTC_CTRL_4A_WF))); 703 704 /* Call the platform wake_alarm function if defined. */ 705 if (rtc->wake_alarm != NULL) 706 rtc->wake_alarm(); 707 else 708 dev_warn(&pdev->dev, 709 "Wake Alarm IRQ just occurred!\n"); 710 } 711 712 /* 713 * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0 714 * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting 715 * each byte to a logic 1. This has no effect on any extended 716 * NV-SRAM that might be present, nor on the time/calendar/alarm 717 * registers. After a ram-clear is completed, there is a minimum 718 * recovery time of ~150ms in which all reads/writes are locked out. 719 * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot 720 * catch this scenario. 721 */ 722 if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) { 723 rtc->write(rtc, RTC_EXT_CTRL_4A, 724 (ctrl4a & ~(RTC_CTRL_4A_RF))); 725 msleep(150); 726 727 /* Call the platform post_ram_clear function if defined. */ 728 if (rtc->post_ram_clear != NULL) 729 rtc->post_ram_clear(); 730 else 731 dev_warn(&pdev->dev, 732 "RAM-Clear IRQ just occurred!\n"); 733 } 734 ds1685_rtc_switch_to_bank0(rtc); 735 736 mutex_unlock(rtc_mutex); 737 } 738 /* ----------------------------------------------------------------------- */ 739 740 741 /* ----------------------------------------------------------------------- */ 742 /* ProcFS interface */ 743 744 #ifdef CONFIG_PROC_FS 745 #define NUM_REGS 6 /* Num of control registers. */ 746 #define NUM_BITS 8 /* Num bits per register. */ 747 #define NUM_SPACES 4 /* Num spaces between each bit. */ 748 749 /* 750 * Periodic Interrupt Rates. 751 */ 752 static const char *ds1685_rtc_pirq_rate[16] = { 753 "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms", 754 "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms", 755 "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms" 756 }; 757 758 /* 759 * Square-Wave Output Frequencies. 760 */ 761 static const char *ds1685_rtc_sqw_freq[16] = { 762 "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz", 763 "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz" 764 }; 765 766 #ifdef CONFIG_RTC_DS1685_PROC_REGS 767 /** 768 * ds1685_rtc_print_regs - helper function to print register values. 769 * @hex: hex byte to convert into binary bits. 770 * @dest: destination char array. 771 * 772 * This is basically a hex->binary function, just with extra spacing between 773 * the digits. It only works on 1-byte values (8 bits). 774 */ 775 static char* 776 ds1685_rtc_print_regs(u8 hex, char *dest) 777 { 778 u32 i, j; 779 char *tmp = dest; 780 781 for (i = 0; i < NUM_BITS; i++) { 782 *tmp++ = ((hex & 0x80) != 0 ? '1' : '0'); 783 for (j = 0; j < NUM_SPACES; j++) 784 *tmp++ = ' '; 785 hex <<= 1; 786 } 787 *tmp++ = '\0'; 788 789 return dest; 790 } 791 #endif 792 793 /** 794 * ds1685_rtc_proc - procfs access function. 795 * @dev: pointer to device structure. 796 * @seq: pointer to seq_file structure. 797 */ 798 static int 799 ds1685_rtc_proc(struct device *dev, struct seq_file *seq) 800 { 801 struct platform_device *pdev = to_platform_device(dev); 802 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 803 u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8]; 804 char *model; 805 #ifdef CONFIG_RTC_DS1685_PROC_REGS 806 char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1]; 807 #endif 808 809 /* Read all the relevant data from the control registers. */ 810 ds1685_rtc_switch_to_bank1(rtc); 811 ds1685_rtc_get_ssn(rtc, ssn); 812 ctrla = rtc->read(rtc, RTC_CTRL_A); 813 ctrlb = rtc->read(rtc, RTC_CTRL_B); 814 ctrlc = rtc->read(rtc, RTC_CTRL_C); 815 ctrld = rtc->read(rtc, RTC_CTRL_D); 816 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 817 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); 818 ds1685_rtc_switch_to_bank0(rtc); 819 820 /* Determine the RTC model. */ 821 switch (ssn[0]) { 822 case RTC_MODEL_DS1685: 823 model = "DS1685/DS1687\0"; 824 break; 825 case RTC_MODEL_DS1689: 826 model = "DS1689/DS1693\0"; 827 break; 828 case RTC_MODEL_DS17285: 829 model = "DS17285/DS17287\0"; 830 break; 831 case RTC_MODEL_DS17485: 832 model = "DS17485/DS17487\0"; 833 break; 834 case RTC_MODEL_DS17885: 835 model = "DS17885/DS17887\0"; 836 break; 837 default: 838 model = "Unknown\0"; 839 break; 840 } 841 842 /* Print out the information. */ 843 seq_printf(seq, 844 "Model\t\t: %s\n" 845 "Oscillator\t: %s\n" 846 "12/24hr\t\t: %s\n" 847 "DST\t\t: %s\n" 848 "Data mode\t: %s\n" 849 "Battery\t\t: %s\n" 850 "Aux batt\t: %s\n" 851 "Update IRQ\t: %s\n" 852 "Periodic IRQ\t: %s\n" 853 "Periodic Rate\t: %s\n" 854 "SQW Freq\t: %s\n" 855 #ifdef CONFIG_RTC_DS1685_PROC_REGS 856 "Serial #\t: %8phC\n" 857 "Register Status\t:\n" 858 " Ctrl A\t: UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n" 859 "\t\t: %s\n" 860 " Ctrl B\t: SET PIE AIE UIE SQWE DM 2412 DSE\n" 861 "\t\t: %s\n" 862 " Ctrl C\t: IRQF PF AF UF --- --- --- ---\n" 863 "\t\t: %s\n" 864 " Ctrl D\t: VRT --- --- --- --- --- --- ---\n" 865 "\t\t: %s\n" 866 #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) 867 " Ctrl 4A\t: VRT2 INCR BME --- PAB RF WF KF\n" 868 #else 869 " Ctrl 4A\t: VRT2 INCR --- --- PAB RF WF KF\n" 870 #endif 871 "\t\t: %s\n" 872 " Ctrl 4B\t: ABE E32k CS RCE PRS RIE WIE KSE\n" 873 "\t\t: %s\n", 874 #else 875 "Serial #\t: %8phC\n", 876 #endif 877 model, 878 ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"), 879 ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"), 880 ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"), 881 ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"), 882 ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"), 883 ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"), 884 ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"), 885 ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"), 886 (!(ctrl4b & RTC_CTRL_4B_E32K) ? 887 ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"), 888 (!((ctrl4b & RTC_CTRL_4B_E32K)) ? 889 ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"), 890 #ifdef CONFIG_RTC_DS1685_PROC_REGS 891 ssn, 892 ds1685_rtc_print_regs(ctrla, bits[0]), 893 ds1685_rtc_print_regs(ctrlb, bits[1]), 894 ds1685_rtc_print_regs(ctrlc, bits[2]), 895 ds1685_rtc_print_regs(ctrld, bits[3]), 896 ds1685_rtc_print_regs(ctrl4a, bits[4]), 897 ds1685_rtc_print_regs(ctrl4b, bits[5])); 898 #else 899 ssn); 900 #endif 901 return 0; 902 } 903 #else 904 #define ds1685_rtc_proc NULL 905 #endif /* CONFIG_PROC_FS */ 906 /* ----------------------------------------------------------------------- */ 907 908 909 /* ----------------------------------------------------------------------- */ 910 /* RTC Class operations */ 911 912 static const struct rtc_class_ops 913 ds1685_rtc_ops = { 914 .proc = ds1685_rtc_proc, 915 .read_time = ds1685_rtc_read_time, 916 .set_time = ds1685_rtc_set_time, 917 .read_alarm = ds1685_rtc_read_alarm, 918 .set_alarm = ds1685_rtc_set_alarm, 919 .alarm_irq_enable = ds1685_rtc_alarm_irq_enable, 920 }; 921 /* ----------------------------------------------------------------------- */ 922 923 924 /* ----------------------------------------------------------------------- */ 925 /* SysFS interface */ 926 927 #ifdef CONFIG_SYSFS 928 /** 929 * ds1685_rtc_sysfs_nvram_read - reads rtc nvram via sysfs. 930 * @file: pointer to file structure. 931 * @kobj: pointer to kobject structure. 932 * @bin_attr: pointer to bin_attribute structure. 933 * @buf: pointer to char array to hold the output. 934 * @pos: current file position pointer. 935 * @size: size of the data to read. 936 */ 937 static ssize_t 938 ds1685_rtc_sysfs_nvram_read(struct file *filp, struct kobject *kobj, 939 struct bin_attribute *bin_attr, char *buf, 940 loff_t pos, size_t size) 941 { 942 struct platform_device *pdev = 943 to_platform_device(container_of(kobj, struct device, kobj)); 944 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 945 ssize_t count; 946 unsigned long flags = 0; 947 948 spin_lock_irqsave(&rtc->lock, flags); 949 ds1685_rtc_switch_to_bank0(rtc); 950 951 /* Read NVRAM in time and bank0 registers. */ 952 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; 953 count++, size--) { 954 if (count < NVRAM_SZ_TIME) 955 *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++)); 956 else 957 *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++)); 958 } 959 960 #ifndef CONFIG_RTC_DRV_DS1689 961 if (size > 0) { 962 ds1685_rtc_switch_to_bank1(rtc); 963 964 #ifndef CONFIG_RTC_DRV_DS1685 965 /* Enable burst-mode on DS17x85/DS17x87 */ 966 rtc->write(rtc, RTC_EXT_CTRL_4A, 967 (rtc->read(rtc, RTC_EXT_CTRL_4A) | 968 RTC_CTRL_4A_BME)); 969 970 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start 971 * reading with burst-mode */ 972 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, 973 (pos - NVRAM_TOTAL_SZ_BANK0)); 974 #endif 975 976 /* Read NVRAM in bank1 registers. */ 977 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; 978 count++, size--) { 979 #ifdef CONFIG_RTC_DRV_DS1685 980 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR 981 * before each read. */ 982 rtc->write(rtc, RTC_BANK1_RAM_ADDR, 983 (pos - NVRAM_TOTAL_SZ_BANK0)); 984 #endif 985 *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT); 986 pos++; 987 } 988 989 #ifndef CONFIG_RTC_DRV_DS1685 990 /* Disable burst-mode on DS17x85/DS17x87 */ 991 rtc->write(rtc, RTC_EXT_CTRL_4A, 992 (rtc->read(rtc, RTC_EXT_CTRL_4A) & 993 ~(RTC_CTRL_4A_BME))); 994 #endif 995 ds1685_rtc_switch_to_bank0(rtc); 996 } 997 #endif /* !CONFIG_RTC_DRV_DS1689 */ 998 spin_unlock_irqrestore(&rtc->lock, flags); 999 1000 /* 1001 * XXX: Bug? this appears to cause the function to get executed 1002 * several times in succession. But it's the only way to actually get 1003 * data written out to a file. 1004 */ 1005 return count; 1006 } 1007 1008 /** 1009 * ds1685_rtc_sysfs_nvram_write - writes rtc nvram via sysfs. 1010 * @file: pointer to file structure. 1011 * @kobj: pointer to kobject structure. 1012 * @bin_attr: pointer to bin_attribute structure. 1013 * @buf: pointer to char array to hold the input. 1014 * @pos: current file position pointer. 1015 * @size: size of the data to write. 1016 */ 1017 static ssize_t 1018 ds1685_rtc_sysfs_nvram_write(struct file *filp, struct kobject *kobj, 1019 struct bin_attribute *bin_attr, char *buf, 1020 loff_t pos, size_t size) 1021 { 1022 struct platform_device *pdev = 1023 to_platform_device(container_of(kobj, struct device, kobj)); 1024 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 1025 ssize_t count; 1026 unsigned long flags = 0; 1027 1028 spin_lock_irqsave(&rtc->lock, flags); 1029 ds1685_rtc_switch_to_bank0(rtc); 1030 1031 /* Write NVRAM in time and bank0 registers. */ 1032 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0; 1033 count++, size--) 1034 if (count < NVRAM_SZ_TIME) 1035 rtc->write(rtc, (NVRAM_TIME_BASE + pos++), 1036 *buf++); 1037 else 1038 rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++); 1039 1040 #ifndef CONFIG_RTC_DRV_DS1689 1041 if (size > 0) { 1042 ds1685_rtc_switch_to_bank1(rtc); 1043 1044 #ifndef CONFIG_RTC_DRV_DS1685 1045 /* Enable burst-mode on DS17x85/DS17x87 */ 1046 rtc->write(rtc, RTC_EXT_CTRL_4A, 1047 (rtc->read(rtc, RTC_EXT_CTRL_4A) | 1048 RTC_CTRL_4A_BME)); 1049 1050 /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start 1051 * writing with burst-mode */ 1052 rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB, 1053 (pos - NVRAM_TOTAL_SZ_BANK0)); 1054 #endif 1055 1056 /* Write NVRAM in bank1 registers. */ 1057 for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ; 1058 count++, size--) { 1059 #ifdef CONFIG_RTC_DRV_DS1685 1060 /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR 1061 * before each read. */ 1062 rtc->write(rtc, RTC_BANK1_RAM_ADDR, 1063 (pos - NVRAM_TOTAL_SZ_BANK0)); 1064 #endif 1065 rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++); 1066 pos++; 1067 } 1068 1069 #ifndef CONFIG_RTC_DRV_DS1685 1070 /* Disable burst-mode on DS17x85/DS17x87 */ 1071 rtc->write(rtc, RTC_EXT_CTRL_4A, 1072 (rtc->read(rtc, RTC_EXT_CTRL_4A) & 1073 ~(RTC_CTRL_4A_BME))); 1074 #endif 1075 ds1685_rtc_switch_to_bank0(rtc); 1076 } 1077 #endif /* !CONFIG_RTC_DRV_DS1689 */ 1078 spin_unlock_irqrestore(&rtc->lock, flags); 1079 1080 return count; 1081 } 1082 1083 /** 1084 * struct ds1685_rtc_sysfs_nvram_attr - sysfs attributes for rtc nvram. 1085 * @attr: nvram attributes. 1086 * @read: nvram read function. 1087 * @write: nvram write function. 1088 * @size: nvram total size (bank0 + extended). 1089 */ 1090 static struct bin_attribute 1091 ds1685_rtc_sysfs_nvram_attr = { 1092 .attr = { 1093 .name = "nvram", 1094 .mode = S_IRUGO | S_IWUSR, 1095 }, 1096 .read = ds1685_rtc_sysfs_nvram_read, 1097 .write = ds1685_rtc_sysfs_nvram_write, 1098 .size = NVRAM_TOTAL_SZ 1099 }; 1100 1101 /** 1102 * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status. 1103 * @dev: pointer to device structure. 1104 * @attr: pointer to device_attribute structure. 1105 * @buf: pointer to char array to hold the output. 1106 */ 1107 static ssize_t 1108 ds1685_rtc_sysfs_battery_show(struct device *dev, 1109 struct device_attribute *attr, char *buf) 1110 { 1111 struct platform_device *pdev = to_platform_device(dev); 1112 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 1113 u8 ctrld; 1114 1115 ctrld = rtc->read(rtc, RTC_CTRL_D); 1116 1117 return sprintf(buf, "%s\n", 1118 (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A"); 1119 } 1120 static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL); 1121 1122 /** 1123 * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status. 1124 * @dev: pointer to device structure. 1125 * @attr: pointer to device_attribute structure. 1126 * @buf: pointer to char array to hold the output. 1127 */ 1128 static ssize_t 1129 ds1685_rtc_sysfs_auxbatt_show(struct device *dev, 1130 struct device_attribute *attr, char *buf) 1131 { 1132 struct platform_device *pdev = to_platform_device(dev); 1133 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 1134 u8 ctrl4a; 1135 1136 ds1685_rtc_switch_to_bank1(rtc); 1137 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 1138 ds1685_rtc_switch_to_bank0(rtc); 1139 1140 return sprintf(buf, "%s\n", 1141 (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A"); 1142 } 1143 static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL); 1144 1145 /** 1146 * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number. 1147 * @dev: pointer to device structure. 1148 * @attr: pointer to device_attribute structure. 1149 * @buf: pointer to char array to hold the output. 1150 */ 1151 static ssize_t 1152 ds1685_rtc_sysfs_serial_show(struct device *dev, 1153 struct device_attribute *attr, char *buf) 1154 { 1155 struct platform_device *pdev = to_platform_device(dev); 1156 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 1157 u8 ssn[8]; 1158 1159 ds1685_rtc_switch_to_bank1(rtc); 1160 ds1685_rtc_get_ssn(rtc, ssn); 1161 ds1685_rtc_switch_to_bank0(rtc); 1162 1163 return sprintf(buf, "%8phC\n", ssn); 1164 } 1165 static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL); 1166 1167 /** 1168 * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features. 1169 */ 1170 static struct attribute* 1171 ds1685_rtc_sysfs_misc_attrs[] = { 1172 &dev_attr_battery.attr, 1173 &dev_attr_auxbatt.attr, 1174 &dev_attr_serial.attr, 1175 NULL, 1176 }; 1177 1178 /** 1179 * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features. 1180 */ 1181 static const struct attribute_group 1182 ds1685_rtc_sysfs_misc_grp = { 1183 .name = "misc", 1184 .attrs = ds1685_rtc_sysfs_misc_attrs, 1185 }; 1186 1187 #ifdef CONFIG_RTC_DS1685_SYSFS_REGS 1188 /** 1189 * struct ds1685_rtc_ctrl_regs. 1190 * @name: char pointer for the bit name. 1191 * @reg: control register the bit is in. 1192 * @bit: the bit's offset in the register. 1193 */ 1194 struct ds1685_rtc_ctrl_regs { 1195 const char *name; 1196 const u8 reg; 1197 const u8 bit; 1198 }; 1199 1200 /* 1201 * Ctrl register bit lookup table. 1202 */ 1203 static const struct ds1685_rtc_ctrl_regs 1204 ds1685_ctrl_regs_table[] = { 1205 { "uip", RTC_CTRL_A, RTC_CTRL_A_UIP }, 1206 { "dv2", RTC_CTRL_A, RTC_CTRL_A_DV2 }, 1207 { "dv1", RTC_CTRL_A, RTC_CTRL_A_DV1 }, 1208 { "dv0", RTC_CTRL_A, RTC_CTRL_A_DV0 }, 1209 { "rs3", RTC_CTRL_A, RTC_CTRL_A_RS3 }, 1210 { "rs2", RTC_CTRL_A, RTC_CTRL_A_RS2 }, 1211 { "rs1", RTC_CTRL_A, RTC_CTRL_A_RS1 }, 1212 { "rs0", RTC_CTRL_A, RTC_CTRL_A_RS0 }, 1213 { "set", RTC_CTRL_B, RTC_CTRL_B_SET }, 1214 { "pie", RTC_CTRL_B, RTC_CTRL_B_PIE }, 1215 { "aie", RTC_CTRL_B, RTC_CTRL_B_AIE }, 1216 { "uie", RTC_CTRL_B, RTC_CTRL_B_UIE }, 1217 { "sqwe", RTC_CTRL_B, RTC_CTRL_B_SQWE }, 1218 { "dm", RTC_CTRL_B, RTC_CTRL_B_DM }, 1219 { "2412", RTC_CTRL_B, RTC_CTRL_B_2412 }, 1220 { "dse", RTC_CTRL_B, RTC_CTRL_B_DSE }, 1221 { "irqf", RTC_CTRL_C, RTC_CTRL_C_IRQF }, 1222 { "pf", RTC_CTRL_C, RTC_CTRL_C_PF }, 1223 { "af", RTC_CTRL_C, RTC_CTRL_C_AF }, 1224 { "uf", RTC_CTRL_C, RTC_CTRL_C_UF }, 1225 { "vrt", RTC_CTRL_D, RTC_CTRL_D_VRT }, 1226 { "vrt2", RTC_EXT_CTRL_4A, RTC_CTRL_4A_VRT2 }, 1227 { "incr", RTC_EXT_CTRL_4A, RTC_CTRL_4A_INCR }, 1228 { "pab", RTC_EXT_CTRL_4A, RTC_CTRL_4A_PAB }, 1229 { "rf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_RF }, 1230 { "wf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_WF }, 1231 { "kf", RTC_EXT_CTRL_4A, RTC_CTRL_4A_KF }, 1232 #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) 1233 { "bme", RTC_EXT_CTRL_4A, RTC_CTRL_4A_BME }, 1234 #endif 1235 { "abe", RTC_EXT_CTRL_4B, RTC_CTRL_4B_ABE }, 1236 { "e32k", RTC_EXT_CTRL_4B, RTC_CTRL_4B_E32K }, 1237 { "cs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_CS }, 1238 { "rce", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RCE }, 1239 { "prs", RTC_EXT_CTRL_4B, RTC_CTRL_4B_PRS }, 1240 { "rie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_RIE }, 1241 { "wie", RTC_EXT_CTRL_4B, RTC_CTRL_4B_WIE }, 1242 { "kse", RTC_EXT_CTRL_4B, RTC_CTRL_4B_KSE }, 1243 { NULL, 0, 0 }, 1244 }; 1245 1246 /** 1247 * ds1685_rtc_sysfs_ctrl_regs_lookup - ctrl register bit lookup function. 1248 * @name: ctrl register bit to look up in ds1685_ctrl_regs_table. 1249 */ 1250 static const struct ds1685_rtc_ctrl_regs* 1251 ds1685_rtc_sysfs_ctrl_regs_lookup(const char *name) 1252 { 1253 const struct ds1685_rtc_ctrl_regs *p = ds1685_ctrl_regs_table; 1254 1255 for (; p->name != NULL; ++p) 1256 if (strcmp(p->name, name) == 0) 1257 return p; 1258 1259 return NULL; 1260 } 1261 1262 /** 1263 * ds1685_rtc_sysfs_ctrl_regs_show - reads a ctrl register bit via sysfs. 1264 * @dev: pointer to device structure. 1265 * @attr: pointer to device_attribute structure. 1266 * @buf: pointer to char array to hold the output. 1267 */ 1268 static ssize_t 1269 ds1685_rtc_sysfs_ctrl_regs_show(struct device *dev, 1270 struct device_attribute *attr, char *buf) 1271 { 1272 u8 tmp; 1273 struct ds1685_priv *rtc = dev_get_drvdata(dev); 1274 const struct ds1685_rtc_ctrl_regs *reg_info = 1275 ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name); 1276 1277 /* Make sure we actually matched something. */ 1278 if (!reg_info) 1279 return -EINVAL; 1280 1281 /* No spinlock during a read -- mutex is already held. */ 1282 ds1685_rtc_switch_to_bank1(rtc); 1283 tmp = rtc->read(rtc, reg_info->reg) & reg_info->bit; 1284 ds1685_rtc_switch_to_bank0(rtc); 1285 1286 return sprintf(buf, "%d\n", (tmp ? 1 : 0)); 1287 } 1288 1289 /** 1290 * ds1685_rtc_sysfs_ctrl_regs_store - writes a ctrl register bit via sysfs. 1291 * @dev: pointer to device structure. 1292 * @attr: pointer to device_attribute structure. 1293 * @buf: pointer to char array to hold the output. 1294 * @count: number of bytes written. 1295 */ 1296 static ssize_t 1297 ds1685_rtc_sysfs_ctrl_regs_store(struct device *dev, 1298 struct device_attribute *attr, 1299 const char *buf, size_t count) 1300 { 1301 struct ds1685_priv *rtc = dev_get_drvdata(dev); 1302 u8 reg = 0, bit = 0, tmp; 1303 unsigned long flags = 0; 1304 long int val = 0; 1305 const struct ds1685_rtc_ctrl_regs *reg_info = 1306 ds1685_rtc_sysfs_ctrl_regs_lookup(attr->attr.name); 1307 1308 /* We only accept numbers. */ 1309 if (kstrtol(buf, 10, &val) < 0) 1310 return -EINVAL; 1311 1312 /* bits are binary, 0 or 1 only. */ 1313 if ((val != 0) && (val != 1)) 1314 return -ERANGE; 1315 1316 /* Make sure we actually matched something. */ 1317 if (!reg_info) 1318 return -EINVAL; 1319 1320 reg = reg_info->reg; 1321 bit = reg_info->bit; 1322 1323 /* Safe to spinlock during a write. */ 1324 ds1685_rtc_begin_ctrl_access(rtc, flags); 1325 tmp = rtc->read(rtc, reg); 1326 rtc->write(rtc, reg, (val ? (tmp | bit) : (tmp & ~(bit)))); 1327 ds1685_rtc_end_ctrl_access(rtc, flags); 1328 1329 return count; 1330 } 1331 1332 /** 1333 * DS1685_RTC_SYSFS_CTRL_REG_RO - device_attribute for read-only register bit. 1334 * @bit: bit to read. 1335 */ 1336 #define DS1685_RTC_SYSFS_CTRL_REG_RO(bit) \ 1337 static DEVICE_ATTR(bit, S_IRUGO, \ 1338 ds1685_rtc_sysfs_ctrl_regs_show, NULL) 1339 1340 /** 1341 * DS1685_RTC_SYSFS_CTRL_REG_RW - device_attribute for read-write register bit. 1342 * @bit: bit to read or write. 1343 */ 1344 #define DS1685_RTC_SYSFS_CTRL_REG_RW(bit) \ 1345 static DEVICE_ATTR(bit, S_IRUGO | S_IWUSR, \ 1346 ds1685_rtc_sysfs_ctrl_regs_show, \ 1347 ds1685_rtc_sysfs_ctrl_regs_store) 1348 1349 /* 1350 * Control Register A bits. 1351 */ 1352 DS1685_RTC_SYSFS_CTRL_REG_RO(uip); 1353 DS1685_RTC_SYSFS_CTRL_REG_RW(dv2); 1354 DS1685_RTC_SYSFS_CTRL_REG_RW(dv1); 1355 DS1685_RTC_SYSFS_CTRL_REG_RO(dv0); 1356 DS1685_RTC_SYSFS_CTRL_REG_RW(rs3); 1357 DS1685_RTC_SYSFS_CTRL_REG_RW(rs2); 1358 DS1685_RTC_SYSFS_CTRL_REG_RW(rs1); 1359 DS1685_RTC_SYSFS_CTRL_REG_RW(rs0); 1360 1361 static struct attribute* 1362 ds1685_rtc_sysfs_ctrla_attrs[] = { 1363 &dev_attr_uip.attr, 1364 &dev_attr_dv2.attr, 1365 &dev_attr_dv1.attr, 1366 &dev_attr_dv0.attr, 1367 &dev_attr_rs3.attr, 1368 &dev_attr_rs2.attr, 1369 &dev_attr_rs1.attr, 1370 &dev_attr_rs0.attr, 1371 NULL, 1372 }; 1373 1374 static const struct attribute_group 1375 ds1685_rtc_sysfs_ctrla_grp = { 1376 .name = "ctrla", 1377 .attrs = ds1685_rtc_sysfs_ctrla_attrs, 1378 }; 1379 1380 1381 /* 1382 * Control Register B bits. 1383 */ 1384 DS1685_RTC_SYSFS_CTRL_REG_RO(set); 1385 DS1685_RTC_SYSFS_CTRL_REG_RW(pie); 1386 DS1685_RTC_SYSFS_CTRL_REG_RW(aie); 1387 DS1685_RTC_SYSFS_CTRL_REG_RW(uie); 1388 DS1685_RTC_SYSFS_CTRL_REG_RW(sqwe); 1389 DS1685_RTC_SYSFS_CTRL_REG_RO(dm); 1390 DS1685_RTC_SYSFS_CTRL_REG_RO(2412); 1391 DS1685_RTC_SYSFS_CTRL_REG_RO(dse); 1392 1393 static struct attribute* 1394 ds1685_rtc_sysfs_ctrlb_attrs[] = { 1395 &dev_attr_set.attr, 1396 &dev_attr_pie.attr, 1397 &dev_attr_aie.attr, 1398 &dev_attr_uie.attr, 1399 &dev_attr_sqwe.attr, 1400 &dev_attr_dm.attr, 1401 &dev_attr_2412.attr, 1402 &dev_attr_dse.attr, 1403 NULL, 1404 }; 1405 1406 static const struct attribute_group 1407 ds1685_rtc_sysfs_ctrlb_grp = { 1408 .name = "ctrlb", 1409 .attrs = ds1685_rtc_sysfs_ctrlb_attrs, 1410 }; 1411 1412 /* 1413 * Control Register C bits. 1414 * 1415 * Reading Control C clears these bits! Reading them individually can 1416 * possibly cause an interrupt to be missed. Use the /proc interface 1417 * to see all the bits in this register simultaneously. 1418 */ 1419 DS1685_RTC_SYSFS_CTRL_REG_RO(irqf); 1420 DS1685_RTC_SYSFS_CTRL_REG_RO(pf); 1421 DS1685_RTC_SYSFS_CTRL_REG_RO(af); 1422 DS1685_RTC_SYSFS_CTRL_REG_RO(uf); 1423 1424 static struct attribute* 1425 ds1685_rtc_sysfs_ctrlc_attrs[] = { 1426 &dev_attr_irqf.attr, 1427 &dev_attr_pf.attr, 1428 &dev_attr_af.attr, 1429 &dev_attr_uf.attr, 1430 NULL, 1431 }; 1432 1433 static const struct attribute_group 1434 ds1685_rtc_sysfs_ctrlc_grp = { 1435 .name = "ctrlc", 1436 .attrs = ds1685_rtc_sysfs_ctrlc_attrs, 1437 }; 1438 1439 /* 1440 * Control Register D bits. 1441 */ 1442 DS1685_RTC_SYSFS_CTRL_REG_RO(vrt); 1443 1444 static struct attribute* 1445 ds1685_rtc_sysfs_ctrld_attrs[] = { 1446 &dev_attr_vrt.attr, 1447 NULL, 1448 }; 1449 1450 static const struct attribute_group 1451 ds1685_rtc_sysfs_ctrld_grp = { 1452 .name = "ctrld", 1453 .attrs = ds1685_rtc_sysfs_ctrld_attrs, 1454 }; 1455 1456 /* 1457 * Control Register 4A bits. 1458 */ 1459 DS1685_RTC_SYSFS_CTRL_REG_RO(vrt2); 1460 DS1685_RTC_SYSFS_CTRL_REG_RO(incr); 1461 DS1685_RTC_SYSFS_CTRL_REG_RW(pab); 1462 DS1685_RTC_SYSFS_CTRL_REG_RW(rf); 1463 DS1685_RTC_SYSFS_CTRL_REG_RW(wf); 1464 DS1685_RTC_SYSFS_CTRL_REG_RW(kf); 1465 #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) 1466 DS1685_RTC_SYSFS_CTRL_REG_RO(bme); 1467 #endif 1468 1469 static struct attribute* 1470 ds1685_rtc_sysfs_ctrl4a_attrs[] = { 1471 &dev_attr_vrt2.attr, 1472 &dev_attr_incr.attr, 1473 &dev_attr_pab.attr, 1474 &dev_attr_rf.attr, 1475 &dev_attr_wf.attr, 1476 &dev_attr_kf.attr, 1477 #if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689) 1478 &dev_attr_bme.attr, 1479 #endif 1480 NULL, 1481 }; 1482 1483 static const struct attribute_group 1484 ds1685_rtc_sysfs_ctrl4a_grp = { 1485 .name = "ctrl4a", 1486 .attrs = ds1685_rtc_sysfs_ctrl4a_attrs, 1487 }; 1488 1489 /* 1490 * Control Register 4B bits. 1491 */ 1492 DS1685_RTC_SYSFS_CTRL_REG_RW(abe); 1493 DS1685_RTC_SYSFS_CTRL_REG_RW(e32k); 1494 DS1685_RTC_SYSFS_CTRL_REG_RO(cs); 1495 DS1685_RTC_SYSFS_CTRL_REG_RW(rce); 1496 DS1685_RTC_SYSFS_CTRL_REG_RW(prs); 1497 DS1685_RTC_SYSFS_CTRL_REG_RW(rie); 1498 DS1685_RTC_SYSFS_CTRL_REG_RW(wie); 1499 DS1685_RTC_SYSFS_CTRL_REG_RW(kse); 1500 1501 static struct attribute* 1502 ds1685_rtc_sysfs_ctrl4b_attrs[] = { 1503 &dev_attr_abe.attr, 1504 &dev_attr_e32k.attr, 1505 &dev_attr_cs.attr, 1506 &dev_attr_rce.attr, 1507 &dev_attr_prs.attr, 1508 &dev_attr_rie.attr, 1509 &dev_attr_wie.attr, 1510 &dev_attr_kse.attr, 1511 NULL, 1512 }; 1513 1514 static const struct attribute_group 1515 ds1685_rtc_sysfs_ctrl4b_grp = { 1516 .name = "ctrl4b", 1517 .attrs = ds1685_rtc_sysfs_ctrl4b_attrs, 1518 }; 1519 1520 1521 /** 1522 * struct ds1685_rtc_ctrl_regs. 1523 * @name: char pointer for the bit name. 1524 * @reg: control register the bit is in. 1525 * @bit: the bit's offset in the register. 1526 */ 1527 struct ds1685_rtc_time_regs { 1528 const char *name; 1529 const u8 reg; 1530 const u8 mask; 1531 const u8 min; 1532 const u8 max; 1533 }; 1534 1535 /* 1536 * Time/Date register lookup tables. 1537 */ 1538 static const struct ds1685_rtc_time_regs 1539 ds1685_time_regs_bcd_table[] = { 1540 { "seconds", RTC_SECS, RTC_SECS_BCD_MASK, 0, 59 }, 1541 { "minutes", RTC_MINS, RTC_MINS_BCD_MASK, 0, 59 }, 1542 { "hours", RTC_HRS, RTC_HRS_24_BCD_MASK, 0, 23 }, 1543 { "wday", RTC_WDAY, RTC_WDAY_MASK, 1, 7 }, 1544 { "mday", RTC_MDAY, RTC_MDAY_BCD_MASK, 1, 31 }, 1545 { "month", RTC_MONTH, RTC_MONTH_BCD_MASK, 1, 12 }, 1546 { "year", RTC_YEAR, RTC_YEAR_BCD_MASK, 0, 99 }, 1547 { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0, 99 }, 1548 { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BCD_MASK, 0, 59 }, 1549 { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BCD_MASK, 0, 59 }, 1550 { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BCD_MASK, 0, 23 }, 1551 { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 1, 31 }, 1552 { NULL, 0, 0, 0, 0 }, 1553 }; 1554 1555 static const struct ds1685_rtc_time_regs 1556 ds1685_time_regs_bin_table[] = { 1557 { "seconds", RTC_SECS, RTC_SECS_BIN_MASK, 0x00, 0x3b }, 1558 { "minutes", RTC_MINS, RTC_MINS_BIN_MASK, 0x00, 0x3b }, 1559 { "hours", RTC_HRS, RTC_HRS_24_BIN_MASK, 0x00, 0x17 }, 1560 { "wday", RTC_WDAY, RTC_WDAY_MASK, 0x01, 0x07 }, 1561 { "mday", RTC_MDAY, RTC_MDAY_BIN_MASK, 0x01, 0x1f }, 1562 { "month", RTC_MONTH, RTC_MONTH_BIN_MASK, 0x01, 0x0c }, 1563 { "year", RTC_YEAR, RTC_YEAR_BIN_MASK, 0x00, 0x63 }, 1564 { "century", RTC_CENTURY, RTC_CENTURY_MASK, 0x00, 0x63 }, 1565 { "alarm_seconds", RTC_SECS_ALARM, RTC_SECS_BIN_MASK, 0x00, 0x3b }, 1566 { "alarm_minutes", RTC_MINS_ALARM, RTC_MINS_BIN_MASK, 0x00, 0x3b }, 1567 { "alarm_hours", RTC_HRS_ALARM, RTC_HRS_24_BIN_MASK, 0x00, 0x17 }, 1568 { "alarm_mday", RTC_MDAY_ALARM, RTC_MDAY_ALARM_MASK, 0x01, 0x1f }, 1569 { NULL, 0, 0, 0x00, 0x00 }, 1570 }; 1571 1572 /** 1573 * ds1685_rtc_sysfs_time_regs_bcd_lookup - time/date reg bit lookup function. 1574 * @name: register bit to look up in ds1685_time_regs_bcd_table. 1575 */ 1576 static const struct ds1685_rtc_time_regs* 1577 ds1685_rtc_sysfs_time_regs_lookup(const char *name, bool bcd_mode) 1578 { 1579 const struct ds1685_rtc_time_regs *p; 1580 1581 if (bcd_mode) 1582 p = ds1685_time_regs_bcd_table; 1583 else 1584 p = ds1685_time_regs_bin_table; 1585 1586 for (; p->name != NULL; ++p) 1587 if (strcmp(p->name, name) == 0) 1588 return p; 1589 1590 return NULL; 1591 } 1592 1593 /** 1594 * ds1685_rtc_sysfs_time_regs_show - reads a time/date register via sysfs. 1595 * @dev: pointer to device structure. 1596 * @attr: pointer to device_attribute structure. 1597 * @buf: pointer to char array to hold the output. 1598 */ 1599 static ssize_t 1600 ds1685_rtc_sysfs_time_regs_show(struct device *dev, 1601 struct device_attribute *attr, char *buf) 1602 { 1603 u8 tmp; 1604 struct ds1685_priv *rtc = dev_get_drvdata(dev); 1605 const struct ds1685_rtc_time_regs *bcd_reg_info = 1606 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true); 1607 const struct ds1685_rtc_time_regs *bin_reg_info = 1608 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false); 1609 1610 /* Make sure we actually matched something. */ 1611 if (!bcd_reg_info || !bin_reg_info) 1612 return -EINVAL; 1613 1614 /* bcd_reg_info->reg == bin_reg_info->reg. */ 1615 ds1685_rtc_begin_data_access(rtc); 1616 tmp = rtc->read(rtc, bcd_reg_info->reg); 1617 ds1685_rtc_end_data_access(rtc); 1618 1619 tmp = ds1685_rtc_bcd2bin(rtc, tmp, bcd_reg_info->mask, 1620 bin_reg_info->mask); 1621 1622 return sprintf(buf, "%d\n", tmp); 1623 } 1624 1625 /** 1626 * ds1685_rtc_sysfs_time_regs_store - writes a time/date register via sysfs. 1627 * @dev: pointer to device structure. 1628 * @attr: pointer to device_attribute structure. 1629 * @buf: pointer to char array to hold the output. 1630 * @count: number of bytes written. 1631 */ 1632 static ssize_t 1633 ds1685_rtc_sysfs_time_regs_store(struct device *dev, 1634 struct device_attribute *attr, 1635 const char *buf, size_t count) 1636 { 1637 long int val = 0; 1638 struct ds1685_priv *rtc = dev_get_drvdata(dev); 1639 const struct ds1685_rtc_time_regs *bcd_reg_info = 1640 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, true); 1641 const struct ds1685_rtc_time_regs *bin_reg_info = 1642 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false); 1643 1644 /* We only accept numbers. */ 1645 if (kstrtol(buf, 10, &val) < 0) 1646 return -EINVAL; 1647 1648 /* Make sure we actually matched something. */ 1649 if (!bcd_reg_info || !bin_reg_info) 1650 return -EINVAL; 1651 1652 /* Check for a valid range. */ 1653 if (rtc->bcd_mode) { 1654 if ((val < bcd_reg_info->min) || (val > bcd_reg_info->max)) 1655 return -ERANGE; 1656 } else { 1657 if ((val < bin_reg_info->min) || (val > bin_reg_info->max)) 1658 return -ERANGE; 1659 } 1660 1661 val = ds1685_rtc_bin2bcd(rtc, val, bin_reg_info->mask, 1662 bcd_reg_info->mask); 1663 1664 /* bcd_reg_info->reg == bin_reg_info->reg. */ 1665 ds1685_rtc_begin_data_access(rtc); 1666 rtc->write(rtc, bcd_reg_info->reg, val); 1667 ds1685_rtc_end_data_access(rtc); 1668 1669 return count; 1670 } 1671 1672 /** 1673 * DS1685_RTC_SYSFS_REG_RW - device_attribute for a read-write time register. 1674 * @reg: time/date register to read or write. 1675 */ 1676 #define DS1685_RTC_SYSFS_TIME_REG_RW(reg) \ 1677 static DEVICE_ATTR(reg, S_IRUGO | S_IWUSR, \ 1678 ds1685_rtc_sysfs_time_regs_show, \ 1679 ds1685_rtc_sysfs_time_regs_store) 1680 1681 /* 1682 * Time/Date Register bits. 1683 */ 1684 DS1685_RTC_SYSFS_TIME_REG_RW(seconds); 1685 DS1685_RTC_SYSFS_TIME_REG_RW(minutes); 1686 DS1685_RTC_SYSFS_TIME_REG_RW(hours); 1687 DS1685_RTC_SYSFS_TIME_REG_RW(wday); 1688 DS1685_RTC_SYSFS_TIME_REG_RW(mday); 1689 DS1685_RTC_SYSFS_TIME_REG_RW(month); 1690 DS1685_RTC_SYSFS_TIME_REG_RW(year); 1691 DS1685_RTC_SYSFS_TIME_REG_RW(century); 1692 DS1685_RTC_SYSFS_TIME_REG_RW(alarm_seconds); 1693 DS1685_RTC_SYSFS_TIME_REG_RW(alarm_minutes); 1694 DS1685_RTC_SYSFS_TIME_REG_RW(alarm_hours); 1695 DS1685_RTC_SYSFS_TIME_REG_RW(alarm_mday); 1696 1697 static struct attribute* 1698 ds1685_rtc_sysfs_time_attrs[] = { 1699 &dev_attr_seconds.attr, 1700 &dev_attr_minutes.attr, 1701 &dev_attr_hours.attr, 1702 &dev_attr_wday.attr, 1703 &dev_attr_mday.attr, 1704 &dev_attr_month.attr, 1705 &dev_attr_year.attr, 1706 &dev_attr_century.attr, 1707 NULL, 1708 }; 1709 1710 static const struct attribute_group 1711 ds1685_rtc_sysfs_time_grp = { 1712 .name = "datetime", 1713 .attrs = ds1685_rtc_sysfs_time_attrs, 1714 }; 1715 1716 static struct attribute* 1717 ds1685_rtc_sysfs_alarm_attrs[] = { 1718 &dev_attr_alarm_seconds.attr, 1719 &dev_attr_alarm_minutes.attr, 1720 &dev_attr_alarm_hours.attr, 1721 &dev_attr_alarm_mday.attr, 1722 NULL, 1723 }; 1724 1725 static const struct attribute_group 1726 ds1685_rtc_sysfs_alarm_grp = { 1727 .name = "alarm", 1728 .attrs = ds1685_rtc_sysfs_alarm_attrs, 1729 }; 1730 #endif /* CONFIG_RTC_DS1685_SYSFS_REGS */ 1731 1732 1733 /** 1734 * ds1685_rtc_sysfs_register - register sysfs files. 1735 * @dev: pointer to device structure. 1736 */ 1737 static int 1738 ds1685_rtc_sysfs_register(struct device *dev) 1739 { 1740 int ret = 0; 1741 1742 sysfs_bin_attr_init(&ds1685_rtc_sysfs_nvram_attr); 1743 ret = sysfs_create_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr); 1744 if (ret) 1745 return ret; 1746 1747 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp); 1748 if (ret) 1749 return ret; 1750 1751 #ifdef CONFIG_RTC_DS1685_SYSFS_REGS 1752 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp); 1753 if (ret) 1754 return ret; 1755 1756 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp); 1757 if (ret) 1758 return ret; 1759 1760 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp); 1761 if (ret) 1762 return ret; 1763 1764 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp); 1765 if (ret) 1766 return ret; 1767 1768 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp); 1769 if (ret) 1770 return ret; 1771 1772 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp); 1773 if (ret) 1774 return ret; 1775 1776 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp); 1777 if (ret) 1778 return ret; 1779 1780 ret = sysfs_create_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp); 1781 if (ret) 1782 return ret; 1783 #endif 1784 return 0; 1785 } 1786 1787 /** 1788 * ds1685_rtc_sysfs_unregister - unregister sysfs files. 1789 * @dev: pointer to device structure. 1790 */ 1791 static int 1792 ds1685_rtc_sysfs_unregister(struct device *dev) 1793 { 1794 sysfs_remove_bin_file(&dev->kobj, &ds1685_rtc_sysfs_nvram_attr); 1795 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_misc_grp); 1796 1797 #ifdef CONFIG_RTC_DS1685_SYSFS_REGS 1798 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrla_grp); 1799 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlb_grp); 1800 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrlc_grp); 1801 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrld_grp); 1802 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4a_grp); 1803 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_ctrl4b_grp); 1804 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_time_grp); 1805 sysfs_remove_group(&dev->kobj, &ds1685_rtc_sysfs_alarm_grp); 1806 #endif 1807 1808 return 0; 1809 } 1810 #endif /* CONFIG_SYSFS */ 1811 1812 1813 1814 /* ----------------------------------------------------------------------- */ 1815 /* Driver Probe/Removal */ 1816 1817 /** 1818 * ds1685_rtc_probe - initializes rtc driver. 1819 * @pdev: pointer to platform_device structure. 1820 */ 1821 static int 1822 ds1685_rtc_probe(struct platform_device *pdev) 1823 { 1824 struct rtc_device *rtc_dev; 1825 struct resource *res; 1826 struct ds1685_priv *rtc; 1827 struct ds1685_rtc_platform_data *pdata; 1828 u8 ctrla, ctrlb, hours; 1829 unsigned char am_pm; 1830 int ret = 0; 1831 1832 /* Get the platform data. */ 1833 pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data; 1834 if (!pdata) 1835 return -ENODEV; 1836 1837 /* Allocate memory for the rtc device. */ 1838 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 1839 if (!rtc) 1840 return -ENOMEM; 1841 1842 /* 1843 * Allocate/setup any IORESOURCE_MEM resources, if required. Not all 1844 * platforms put the RTC in an easy-access place. Like the SGI Octane, 1845 * which attaches the RTC to a "ByteBus", hooked to a SuperIO chip 1846 * that sits behind the IOC3 PCI metadevice. 1847 */ 1848 if (pdata->alloc_io_resources) { 1849 /* Get the platform resources. */ 1850 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1851 if (!res) 1852 return -ENXIO; 1853 rtc->size = resource_size(res); 1854 1855 /* Request a memory region. */ 1856 /* XXX: mmio-only for now. */ 1857 if (!devm_request_mem_region(&pdev->dev, res->start, rtc->size, 1858 pdev->name)) 1859 return -EBUSY; 1860 1861 /* 1862 * Set the base address for the rtc, and ioremap its 1863 * registers. 1864 */ 1865 rtc->baseaddr = res->start; 1866 rtc->regs = devm_ioremap(&pdev->dev, res->start, rtc->size); 1867 if (!rtc->regs) 1868 return -ENOMEM; 1869 } 1870 rtc->alloc_io_resources = pdata->alloc_io_resources; 1871 1872 /* Get the register step size. */ 1873 if (pdata->regstep > 0) 1874 rtc->regstep = pdata->regstep; 1875 else 1876 rtc->regstep = 1; 1877 1878 /* Platform read function, else default if mmio setup */ 1879 if (pdata->plat_read) 1880 rtc->read = pdata->plat_read; 1881 else 1882 if (pdata->alloc_io_resources) 1883 rtc->read = ds1685_read; 1884 else 1885 return -ENXIO; 1886 1887 /* Platform write function, else default if mmio setup */ 1888 if (pdata->plat_write) 1889 rtc->write = pdata->plat_write; 1890 else 1891 if (pdata->alloc_io_resources) 1892 rtc->write = ds1685_write; 1893 else 1894 return -ENXIO; 1895 1896 /* Platform pre-shutdown function, if defined. */ 1897 if (pdata->plat_prepare_poweroff) 1898 rtc->prepare_poweroff = pdata->plat_prepare_poweroff; 1899 1900 /* Platform wake_alarm function, if defined. */ 1901 if (pdata->plat_wake_alarm) 1902 rtc->wake_alarm = pdata->plat_wake_alarm; 1903 1904 /* Platform post_ram_clear function, if defined. */ 1905 if (pdata->plat_post_ram_clear) 1906 rtc->post_ram_clear = pdata->plat_post_ram_clear; 1907 1908 /* Init the spinlock, workqueue, & set the driver data. */ 1909 spin_lock_init(&rtc->lock); 1910 INIT_WORK(&rtc->work, ds1685_rtc_work_queue); 1911 platform_set_drvdata(pdev, rtc); 1912 1913 /* Turn the oscillator on if is not already on (DV1 = 1). */ 1914 ctrla = rtc->read(rtc, RTC_CTRL_A); 1915 if (!(ctrla & RTC_CTRL_A_DV1)) 1916 ctrla |= RTC_CTRL_A_DV1; 1917 1918 /* Enable the countdown chain (DV2 = 0) */ 1919 ctrla &= ~(RTC_CTRL_A_DV2); 1920 1921 /* Clear RS3-RS0 in Control A. */ 1922 ctrla &= ~(RTC_CTRL_A_RS_MASK); 1923 1924 /* 1925 * All done with Control A. Switch to Bank 1 for the remainder of 1926 * the RTC setup so we have access to the extended functions. 1927 */ 1928 ctrla |= RTC_CTRL_A_DV0; 1929 rtc->write(rtc, RTC_CTRL_A, ctrla); 1930 1931 /* Default to 32768kHz output. */ 1932 rtc->write(rtc, RTC_EXT_CTRL_4B, 1933 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K)); 1934 1935 /* Set the SET bit in Control B so we can do some housekeeping. */ 1936 rtc->write(rtc, RTC_CTRL_B, 1937 (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET)); 1938 1939 /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */ 1940 while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR) 1941 cpu_relax(); 1942 1943 /* 1944 * If the platform supports BCD mode, then set DM=0 in Control B. 1945 * Otherwise, set DM=1 for BIN mode. 1946 */ 1947 ctrlb = rtc->read(rtc, RTC_CTRL_B); 1948 if (pdata->bcd_mode) 1949 ctrlb &= ~(RTC_CTRL_B_DM); 1950 else 1951 ctrlb |= RTC_CTRL_B_DM; 1952 rtc->bcd_mode = pdata->bcd_mode; 1953 1954 /* 1955 * Disable Daylight Savings Time (DSE = 0). 1956 * The RTC has hardcoded timezone information that is rendered 1957 * obselete. We'll let the OS deal with DST settings instead. 1958 */ 1959 if (ctrlb & RTC_CTRL_B_DSE) 1960 ctrlb &= ~(RTC_CTRL_B_DSE); 1961 1962 /* Force 24-hour mode (2412 = 1). */ 1963 if (!(ctrlb & RTC_CTRL_B_2412)) { 1964 /* Reinitialize the time hours. */ 1965 hours = rtc->read(rtc, RTC_HRS); 1966 am_pm = hours & RTC_HRS_AMPM_MASK; 1967 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, 1968 RTC_HRS_12_BIN_MASK); 1969 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); 1970 1971 /* Enable 24-hour mode. */ 1972 ctrlb |= RTC_CTRL_B_2412; 1973 1974 /* Write back to Control B, including DM & DSE bits. */ 1975 rtc->write(rtc, RTC_CTRL_B, ctrlb); 1976 1977 /* Write the time hours back. */ 1978 rtc->write(rtc, RTC_HRS, 1979 ds1685_rtc_bin2bcd(rtc, hours, 1980 RTC_HRS_24_BIN_MASK, 1981 RTC_HRS_24_BCD_MASK)); 1982 1983 /* Reinitialize the alarm hours. */ 1984 hours = rtc->read(rtc, RTC_HRS_ALARM); 1985 am_pm = hours & RTC_HRS_AMPM_MASK; 1986 hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK, 1987 RTC_HRS_12_BIN_MASK); 1988 hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours)); 1989 1990 /* Write the alarm hours back. */ 1991 rtc->write(rtc, RTC_HRS_ALARM, 1992 ds1685_rtc_bin2bcd(rtc, hours, 1993 RTC_HRS_24_BIN_MASK, 1994 RTC_HRS_24_BCD_MASK)); 1995 } else { 1996 /* 24-hour mode is already set, so write Control B back. */ 1997 rtc->write(rtc, RTC_CTRL_B, ctrlb); 1998 } 1999 2000 /* Unset the SET bit in Control B so the RTC can update. */ 2001 rtc->write(rtc, RTC_CTRL_B, 2002 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET))); 2003 2004 /* Check the main battery. */ 2005 if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT)) 2006 dev_warn(&pdev->dev, 2007 "Main battery is exhausted! RTC may be invalid!\n"); 2008 2009 /* Check the auxillary battery. It is optional. */ 2010 if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2)) 2011 dev_warn(&pdev->dev, 2012 "Aux battery is exhausted or not available.\n"); 2013 2014 /* Read Ctrl B and clear PIE/AIE/UIE. */ 2015 rtc->write(rtc, RTC_CTRL_B, 2016 (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK))); 2017 2018 /* Reading Ctrl C auto-clears PF/AF/UF. */ 2019 rtc->read(rtc, RTC_CTRL_C); 2020 2021 /* Read Ctrl 4B and clear RIE/WIE/KSE. */ 2022 rtc->write(rtc, RTC_EXT_CTRL_4B, 2023 (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK))); 2024 2025 /* Clear RF/WF/KF in Ctrl 4A. */ 2026 rtc->write(rtc, RTC_EXT_CTRL_4A, 2027 (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK))); 2028 2029 /* 2030 * Re-enable KSE to handle power button events. We do not enable 2031 * WIE or RIE by default. 2032 */ 2033 rtc->write(rtc, RTC_EXT_CTRL_4B, 2034 (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE)); 2035 2036 /* 2037 * Fetch the IRQ and setup the interrupt handler. 2038 * 2039 * Not all platforms have the IRQF pin tied to something. If not, the 2040 * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but 2041 * there won't be an automatic way of notifying the kernel about it, 2042 * unless ctrlc is explicitly polled. 2043 */ 2044 if (!pdata->no_irq) { 2045 ret = platform_get_irq(pdev, 0); 2046 if (ret > 0) { 2047 rtc->irq_num = ret; 2048 2049 /* Request an IRQ. */ 2050 ret = devm_request_irq(&pdev->dev, rtc->irq_num, 2051 ds1685_rtc_irq_handler, 2052 IRQF_SHARED, pdev->name, pdev); 2053 2054 /* Check to see if something came back. */ 2055 if (unlikely(ret)) { 2056 dev_warn(&pdev->dev, 2057 "RTC interrupt not available\n"); 2058 rtc->irq_num = 0; 2059 } 2060 } else 2061 return ret; 2062 } 2063 rtc->no_irq = pdata->no_irq; 2064 2065 /* Setup complete. */ 2066 ds1685_rtc_switch_to_bank0(rtc); 2067 2068 /* Register the device as an RTC. */ 2069 rtc_dev = rtc_device_register(pdev->name, &pdev->dev, 2070 &ds1685_rtc_ops, THIS_MODULE); 2071 2072 /* Success? */ 2073 if (IS_ERR(rtc_dev)) 2074 return PTR_ERR(rtc_dev); 2075 2076 /* Maximum periodic rate is 8192Hz (0.122070ms). */ 2077 rtc_dev->max_user_freq = RTC_MAX_USER_FREQ; 2078 2079 /* See if the platform doesn't support UIE. */ 2080 if (pdata->uie_unsupported) 2081 rtc_dev->uie_unsupported = 1; 2082 rtc->uie_unsupported = pdata->uie_unsupported; 2083 2084 rtc->dev = rtc_dev; 2085 2086 #ifdef CONFIG_SYSFS 2087 ret = ds1685_rtc_sysfs_register(&pdev->dev); 2088 if (ret) 2089 rtc_device_unregister(rtc->dev); 2090 #endif 2091 2092 /* Done! */ 2093 return ret; 2094 } 2095 2096 /** 2097 * ds1685_rtc_remove - removes rtc driver. 2098 * @pdev: pointer to platform_device structure. 2099 */ 2100 static int 2101 ds1685_rtc_remove(struct platform_device *pdev) 2102 { 2103 struct ds1685_priv *rtc = platform_get_drvdata(pdev); 2104 2105 #ifdef CONFIG_SYSFS 2106 ds1685_rtc_sysfs_unregister(&pdev->dev); 2107 #endif 2108 2109 rtc_device_unregister(rtc->dev); 2110 2111 /* Read Ctrl B and clear PIE/AIE/UIE. */ 2112 rtc->write(rtc, RTC_CTRL_B, 2113 (rtc->read(rtc, RTC_CTRL_B) & 2114 ~(RTC_CTRL_B_PAU_MASK))); 2115 2116 /* Reading Ctrl C auto-clears PF/AF/UF. */ 2117 rtc->read(rtc, RTC_CTRL_C); 2118 2119 /* Read Ctrl 4B and clear RIE/WIE/KSE. */ 2120 rtc->write(rtc, RTC_EXT_CTRL_4B, 2121 (rtc->read(rtc, RTC_EXT_CTRL_4B) & 2122 ~(RTC_CTRL_4B_RWK_MASK))); 2123 2124 /* Manually clear RF/WF/KF in Ctrl 4A. */ 2125 rtc->write(rtc, RTC_EXT_CTRL_4A, 2126 (rtc->read(rtc, RTC_EXT_CTRL_4A) & 2127 ~(RTC_CTRL_4A_RWK_MASK))); 2128 2129 cancel_work_sync(&rtc->work); 2130 2131 return 0; 2132 } 2133 2134 /** 2135 * ds1685_rtc_driver - rtc driver properties. 2136 */ 2137 static struct platform_driver ds1685_rtc_driver = { 2138 .driver = { 2139 .name = "rtc-ds1685", 2140 }, 2141 .probe = ds1685_rtc_probe, 2142 .remove = ds1685_rtc_remove, 2143 }; 2144 module_platform_driver(ds1685_rtc_driver); 2145 /* ----------------------------------------------------------------------- */ 2146 2147 2148 /* ----------------------------------------------------------------------- */ 2149 /* Poweroff function */ 2150 2151 /** 2152 * ds1685_rtc_poweroff - uses the RTC chip to power the system off. 2153 * @pdev: pointer to platform_device structure. 2154 */ 2155 void __noreturn 2156 ds1685_rtc_poweroff(struct platform_device *pdev) 2157 { 2158 u8 ctrla, ctrl4a, ctrl4b; 2159 struct ds1685_priv *rtc; 2160 2161 /* Check for valid RTC data, else, spin forever. */ 2162 if (unlikely(!pdev)) { 2163 pr_emerg("platform device data not available, spinning forever ...\n"); 2164 unreachable(); 2165 } else { 2166 /* Get the rtc data. */ 2167 rtc = platform_get_drvdata(pdev); 2168 2169 /* 2170 * Disable our IRQ. We're powering down, so we're not 2171 * going to worry about cleaning up. Most of that should 2172 * have been taken care of by the shutdown scripts and this 2173 * is the final function call. 2174 */ 2175 if (!rtc->no_irq) 2176 disable_irq_nosync(rtc->irq_num); 2177 2178 /* Oscillator must be on and the countdown chain enabled. */ 2179 ctrla = rtc->read(rtc, RTC_CTRL_A); 2180 ctrla |= RTC_CTRL_A_DV1; 2181 ctrla &= ~(RTC_CTRL_A_DV2); 2182 rtc->write(rtc, RTC_CTRL_A, ctrla); 2183 2184 /* 2185 * Read Control 4A and check the status of the auxillary 2186 * battery. This must be present and working (VRT2 = 1) 2187 * for wakeup and kickstart functionality to be useful. 2188 */ 2189 ds1685_rtc_switch_to_bank1(rtc); 2190 ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A); 2191 if (ctrl4a & RTC_CTRL_4A_VRT2) { 2192 /* Clear all of the interrupt flags on Control 4A. */ 2193 ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK); 2194 rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a); 2195 2196 /* 2197 * The auxillary battery is present and working. 2198 * Enable extended functions (ABE=1), enable 2199 * wake-up (WIE=1), and enable kickstart (KSE=1) 2200 * in Control 4B. 2201 */ 2202 ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B); 2203 ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE | 2204 RTC_CTRL_4B_KSE); 2205 rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b); 2206 } 2207 2208 /* Set PAB to 1 in Control 4A to power the system down. */ 2209 dev_warn(&pdev->dev, "Powerdown.\n"); 2210 msleep(20); 2211 rtc->write(rtc, RTC_EXT_CTRL_4A, 2212 (ctrl4a | RTC_CTRL_4A_PAB)); 2213 2214 /* Spin ... we do not switch back to bank0. */ 2215 unreachable(); 2216 } 2217 } 2218 EXPORT_SYMBOL(ds1685_rtc_poweroff); 2219 /* ----------------------------------------------------------------------- */ 2220 2221 2222 MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>"); 2223 MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>"); 2224 MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver"); 2225 MODULE_LICENSE("GPL"); 2226 MODULE_VERSION(DRV_VERSION); 2227 MODULE_ALIAS("platform:rtc-ds1685"); 2228